34 #ifndef _RTE_MEMORY_H_ 35 #define _RTE_MEMORY_H_ 55 RTE_PGSIZE_4K = 1ULL << 12,
56 RTE_PGSIZE_64K = 1ULL << 16,
57 RTE_PGSIZE_256K = 1ULL << 18,
58 RTE_PGSIZE_2M = 1ULL << 21,
59 RTE_PGSIZE_16M = 1ULL << 24,
60 RTE_PGSIZE_256M = 1ULL << 28,
61 RTE_PGSIZE_512M = 1ULL << 29,
62 RTE_PGSIZE_1G = 1ULL << 30,
63 RTE_PGSIZE_4G = 1ULL << 32,
64 RTE_PGSIZE_16G = 1ULL << 34,
67 #define SOCKET_ID_ANY -1 68 #define RTE_CACHE_LINE_MASK (RTE_CACHE_LINE_SIZE-1) 70 #define RTE_CACHE_LINE_ROUNDUP(size) \ 71 (RTE_CACHE_LINE_SIZE * ((size + RTE_CACHE_LINE_SIZE - 1) / RTE_CACHE_LINE_SIZE)) 75 #if RTE_CACHE_LINE_SIZE == 64 76 #define RTE_CACHE_LINE_SIZE_LOG2 6 77 #elif RTE_CACHE_LINE_SIZE == 128 78 #define RTE_CACHE_LINE_SIZE_LOG2 7 80 #error "Unsupported cache line size" 83 #define RTE_CACHE_LINE_MIN_SIZE 64 88 #define __rte_cache_aligned __rte_aligned(RTE_CACHE_LINE_SIZE) 93 #define __rte_cache_min_aligned __rte_aligned(RTE_CACHE_LINE_MIN_SIZE) 96 #define RTE_BAD_PHYS_ADDR ((phys_addr_t)-1) 105 #define RTE_BAD_IOVA ((rte_iova_t)-1)
unsigned rte_memory_get_nchannel(void)
const struct rte_memseg * rte_eal_get_physmem_layout(void)
int rte_eal_using_phys_addrs(void)
int rte_mem_lock_page(const void *virt)
unsigned rte_memory_get_nrank(void)
phys_addr_t rte_mem_virt2phy(const void *virt)
uint64_t rte_eal_get_physmem_size(void)
void rte_dump_physmem_layout(FILE *f)
rte_iova_t rte_mem_virt2iova(const void *virt)