/*
 * Copyright 2007-2008 Analog Devices Inc.
 *
 * Licensed under the GPL-2 or later
 */

#ifndef _CDEF_BF52X_H
#define _CDEF_BF52X_H

#include <asm/blackfin.h>

#include "defBF52x_base.h"

/* Include core specific register pointer definitions 								*/
#include <asm/cdef_LPBlackfin.h>

/* ==== begin from cdefBF534.h ==== */

/* Clock and System Control	(0xFFC00000 - 0xFFC000FF)								*/
#define bfin_read_PLL_CTL()			bfin_read16(PLL_CTL)
#define bfin_read_PLL_DIV()			bfin_read16(PLL_DIV)
#define bfin_write_PLL_DIV(val)			bfin_write16(PLL_DIV, val)
#define bfin_read_VR_CTL()			bfin_read16(VR_CTL)
#define bfin_read_PLL_STAT()			bfin_read16(PLL_STAT)
#define bfin_write_PLL_STAT(val)		bfin_write16(PLL_STAT, val)
#define bfin_read_PLL_LOCKCNT()			bfin_read16(PLL_LOCKCNT)
#define bfin_write_PLL_LOCKCNT(val)		bfin_write16(PLL_LOCKCNT, val)
#define bfin_read_CHIPID()			bfin_read32(CHIPID)
#define bfin_write_CHIPID(val)			bfin_write32(CHIPID, val)


/* System Interrupt Controller (0xFFC00100 - 0xFFC001FF)							*/
#define bfin_read_SWRST()			bfin_read16(SWRST)
#define bfin_write_SWRST(val)			bfin_write16(SWRST, val)
#define bfin_read_SYSCR()			bfin_read16(SYSCR)
#define bfin_write_SYSCR(val)			bfin_write16(SYSCR, val)

#define bfin_read_SIC_RVECT()			bfin_read32(SIC_RVECT)
#define bfin_write_SIC_RVECT(val)		bfin_write32(SIC_RVECT, val)
#define bfin_read_SIC_IMASK0()			bfin_read32(SIC_IMASK0)
#define bfin_write_SIC_IMASK0(val)		bfin_write32(SIC_IMASK0, val)
#define bfin_read_SIC_IMASK(x)			bfin_read32(SIC_IMASK0 + (x << 6))
#define bfin_write_SIC_IMASK(x, val)		bfin_write32((SIC_IMASK0 + (x << 6)), val)

#define bfin_read_SIC_IAR0()			bfin_read32(SIC_IAR0)
#define bfin_write_SIC_IAR0(val)		bfin_write32(SIC_IAR0, val)
#define bfin_read_SIC_IAR1()			bfin_read32(SIC_IAR1)
#define bfin_write_SIC_IAR1(val)		bfin_write32(SIC_IAR1, val)
#define bfin_read_SIC_IAR2()			bfin_read32(SIC_IAR2)
#define bfin_write_SIC_IAR2(val)		bfin_write32(SIC_IAR2, val)
#define bfin_read_SIC_IAR3()			bfin_read32(SIC_IAR3)
#define bfin_write_SIC_IAR3(val)		bfin_write32(SIC_IAR3, val)

#define bfin_read_SIC_ISR0()			bfin_read32(SIC_ISR0)
#define bfin_write_SIC_ISR0(val)		bfin_write32(SIC_ISR0, val)
#define bfin_read_SIC_ISR(x)			bfin_read32(SIC_ISR0 + (x << 6))
#define bfin_write_SIC_ISR(x, val)		bfin_write32((SIC_ISR0 + (x << 6)), val)

#define bfin_read_SIC_IWR0()			bfin_read32(SIC_IWR0)
#define bfin_write_SIC_IWR0(val)		bfin_write32(SIC_IWR0, val)
#define bfin_read_SIC_IWR(x)			bfin_read32(SIC_IWR0 + (x << 6))
#define bfin_write_SIC_IWR(x, val)		bfin_write32((SIC_IWR0 + (x << 6)), val)

/* SIC Additions to ADSP-BF52x (0xFFC0014C - 0xFFC00162) */

#define bfin_read_SIC_IMASK1()			bfin_read32(SIC_IMASK1)
#define bfin_write_SIC_IMASK1(val)		bfin_write32(SIC_IMASK1, val)
#define bfin_read_SIC_IAR4()			bfin_read32(SIC_IAR4)
#define bfin_write_SIC_IAR4(val)		bfin_write32(SIC_IAR4, val)
#define bfin_read_SIC_IAR5()			bfin_read32(SIC_IAR5)
#define bfin_write_SIC_IAR5(val)		bfin_write32(SIC_IAR5, val)
#define bfin_read_SIC_IAR6()			bfin_read32(SIC_IAR6)
#define bfin_write_SIC_IAR6(val)		bfin_write32(SIC_IAR6, val)
#define bfin_read_SIC_IAR7()			bfin_read32(SIC_IAR7)
#define bfin_write_SIC_IAR7(val)		bfin_write32(SIC_IAR7, val)
#define bfin_read_SIC_ISR1()			bfin_read32(SIC_ISR1)
#define bfin_write_SIC_ISR1(val)		bfin_write32(SIC_ISR1, val)
#define bfin_read_SIC_IWR1()			bfin_read32(SIC_IWR1)
#define bfin_write_SIC_IWR1(val)		bfin_write32(SIC_IWR1, val)

/* Watchdog Timer		(0xFFC00200 - 0xFFC002FF)									*/
#define bfin_read_WDOG_CTL()			bfin_read16(WDOG_CTL)
#define bfin_write_WDOG_CTL(val)		bfin_write16(WDOG_CTL, val)
#define bfin_read_WDOG_CNT()			bfin_read32(WDOG_CNT)
#define bfin_write_WDOG_CNT(val)		bfin_write32(WDOG_CNT, val)
#define bfin_read_WDOG_STAT()			bfin_read32(WDOG_STAT)
#define bfin_write_WDOG_STAT(val)		bfin_write32(WDOG_STAT, val)


/* Real Time Clock		(0xFFC00300 - 0xFFC003FF)									*/
#define bfin_read_RTC_STAT()			bfin_read32(RTC_STAT)
#define bfin_write_RTC_STAT(val)		bfin_write32(RTC_STAT, val)
#define bfin_read_RTC_ICTL()			bfin_read16(RTC_ICTL)
#define bfin_write_RTC_ICTL(val)		bfin_write16(RTC_ICTL, val)
#define bfin_read_RTC_ISTAT()			bfin_read16(RTC_ISTAT)
#define bfin_write_RTC_ISTAT(val)		bfin_write16(RTC_ISTAT, val)
#define bfin_read_RTC_SWCNT()			bfin_read16(RTC_SWCNT)
#define bfin_write_RTC_SWCNT(val)		bfin_write16(RTC_SWCNT, val)
#define bfin_read_RTC_ALARM()			bfin_read32(RTC_ALARM)
#define bfin_write_RTC_ALARM(val)		bfin_write32(RTC_ALARM, val)
#define bfin_read_RTC_FAST()			bfin_read16(RTC_FAST)
#define bfin_write_RTC_FAST(val)		bfin_write16(RTC_FAST, val)
#define bfin_read_RTC_PREN()			bfin_read16(RTC_PREN)
#define bfin_write_RTC_PREN(val)		bfin_write16(RTC_PREN, val)


/* UART0 Controller		(0xFFC00400 - 0xFFC004FF)									*/
#define bfin_read_UART0_THR()			bfin_read16(UART0_THR)
#define bfin_write_UART0_THR(val)		bfin_write16(UART0_THR, val)
#define bfin_read_UART0_RBR()			bfin_read16(UART0_RBR)
#define bfin_write_UART0_RBR(val)		bfin_write16(UART0_RBR, val)
#define bfin_read_UART0_DLL()			bfin_read16(UART0_DLL)
#define bfin_write_UART0_DLL(val)		bfin_write16(UART0_DLL, val)
#define bfin_read_UART0_IER()			bfin_read16(UART0_IER)
#define bfin_write_UART0_IER(val)		bfin_write16(UART0_IER, val)
#define bfin_read_UART0_DLH()			bfin_read16(UART0_DLH)
#define bfin_write_UART0_DLH(val)		bfin_write16(UART0_DLH, val)
#define bfin_read_UART0_IIR()			bfin_read16(UART0_IIR)
#define bfin_write_UART0_IIR(val)		bfin_write16(UART0_IIR, val)
#define bfin_read_UART0_LCR()			bfin_read16(UART0_LCR)
#define bfin_write_UART0_LCR(val)		bfin_write16(UART0_LCR, val)
#define bfin_read_UART0_MCR()			bfin_read16(UART0_MCR)
#define bfin_write_UART0_MCR(val)		bfin_write16(UART0_MCR, val)
#define bfin_read_UART0_LSR()			bfin_read16(UART0_LSR)
#define bfin_write_UART0_LSR(val)		bfin_write16(UART0_LSR, val)
#define bfin_read_UART0_MSR()			bfin_read16(UART0_MSR)
#define bfin_write_UART0_MSR(val)		bfin_write16(UART0_MSR, val)
#define bfin_read_UART0_SCR()			bfin_read16(UART0_SCR)
#define bfin_write_UART0_SCR(val)		bfin_write16(UART0_SCR, val)
#define bfin_read_UART0_GCTL()			bfin_read16(UART0_GCTL)
#define bfin_write_UART0_GCTL(val)		bfin_write16(UART0_GCTL, val)


/* SPI Controller		(0xFFC00500 - 0xFFC005FF)									*/
#define bfin_read_SPI_CTL()			bfin_read16(SPI_CTL)
#define bfin_write_SPI_CTL(val)			bfin_write16(SPI_CTL, val)
#define bfin_read_SPI_FLG()			bfin_read16(SPI_FLG)
#define bfin_write_SPI_FLG(val)			bfin_write16(SPI_FLG, val)
#define bfin_read_SPI_STAT()			bfin_read16(SPI_STAT)
#define bfin_write_SPI_STAT(val)		bfin_write16(SPI_STAT, val)
#define bfin_read_SPI_TDBR()			bfin_read16(SPI_TDBR)
#define bfin_write_SPI_TDBR(val)		bfin_write16(SPI_TDBR, val)
#define bfin_read_SPI_RDBR()			bfin_read16(SPI_RDBR)
#define bfin_write_SPI_RDBR(val)		bfin_write16(SPI_RDBR, val)
#define bfin_read_SPI_BAUD()			bfin_read16(SPI_BAUD)
#define bfin_write_SPI_BAUD(val)		bfin_write16(SPI_BAUD, val)
#define bfin_read_SPI_SHADOW()			bfin_read16(SPI_SHADOW)
#define bfin_write_SPI_SHADOW(val)		bfin_write16(SPI_SHADOW, val)


/* TIMER0-7 Registers		(0xFFC00600 - 0xFFC006FF)								*/
#define bfin_read_TIMER0_CONFIG()		bfin_read16(TIMER0_CONFIG)
#define bfin_write_TIMER0_CONFIG(val)		bfin_write16(TIMER0_CONFIG, val)
#define bfin_read_TIMER0_COUNTER()		bfin_read32(TIMER0_COUNTER)
#define bfin_write_TIMER0_COUNTER(val)		bfin_write32(TIMER0_COUNTER, val)
#define bfin_read_TIMER0_PERIOD()		bfin_read32(TIMER0_PERIOD)
#define bfin_write_TIMER0_PERIOD(val)		bfin_write32(TIMER0_PERIOD, val)
#define bfin_read_TIMER0_WIDTH()		bfin_read32(TIMER0_WIDTH)
#define bfin_write_TIMER0_WIDTH(val)		bfin_write32(TIMER0_WIDTH, val)

#define bfin_read_TIMER1_CONFIG()		bfin_read16(TIMER1_CONFIG)
#define bfin_write_TIMER1_CONFIG(val)		bfin_write16(TIMER1_CONFIG, val)
#define bfin_read_TIMER1_COUNTER()		bfin_read32(TIMER1_COUNTER)
#define bfin_write_TIMER1_COUNTER(val)		bfin_write32(TIMER1_COUNTER, val)
#define bfin_read_TIMER1_PERIOD()		bfin_read32(TIMER1_PERIOD)
#define bfin_write_TIMER1_PERIOD(val)		bfin_write32(TIMER1_PERIOD, val)
#define bfin_read_TIMER1_WIDTH()		bfin_read32(TIMER1_WIDTH)
#define bfin_write_TIMER1_WIDTH(val)		bfin_write32(TIMER1_WIDTH, val)

#define bfin_read_TIMER2_CONFIG()		bfin_read16(TIMER2_CONFIG)
#define bfin_write_TIMER2_CONFIG(val)		bfin_write16(TIMER2_CONFIG, val)
#define bfin_read_TIMER2_COUNTER()		bfin_read32(TIMER2_COUNTER)
#define bfin_write_TIMER2_COUNTER(val)		bfin_write32(TIMER2_COUNTER, val)
#define bfin_read_TIMER2_PERIOD()		bfin_read32(TIMER2_PERIOD)
#define bfin_write_TIMER2_PERIOD(val)		bfin_write32(TIMER2_PERIOD, val)
#define bfin_read_TIMER2_WIDTH()		bfin_read32(TIMER2_WIDTH)
#define bfin_write_TIMER2_WIDTH(val)		bfin_write32(TIMER2_WIDTH, val)

#define bfin_read_TIMER3_CONFIG()		bfin_read16(TIMER3_CONFIG)
#define bfin_write_TIMER3_CONFIG(val)		bfin_write16(TIMER3_CONFIG, val)
#define bfin_read_TIMER3_COUNTER()		bfin_read32(TIMER3_COUNTER)
#define bfin_write_TIMER3_COUNTER(val)		bfin_write32(TIMER3_COUNTER, val)
#define bfin_read_TIMER3_PERIOD()		bfin_read32(TIMER3_PERIOD)
#define bfin_write_TIMER3_PERIOD(val)		bfin_write32(TIMER3_PERIOD, val)
#define bfin_read_TIMER3_WIDTH()		bfin_read32(TIMER3_WIDTH)
#define bfin_write_TIMER3_WIDTH(val)		bfin_write32(TIMER3_WIDTH, val)

#define bfin_read_TIMER4_CONFIG()		bfin_read16(TIMER4_CONFIG)
#define bfin_write_TIMER4_CONFIG(val)		bfin_write16(TIMER4_CONFIG, val)
#define bfin_read_TIMER4_COUNTER()		bfin_read32(TIMER4_COUNTER)
#define bfin_write_TIMER4_COUNTER(val)		bfin_write32(TIMER4_COUNTER, val)
#define bfin_read_TIMER4_PERIOD()		bfin_read32(TIMER4_PERIOD)
#define bfin_write_TIMER4_PERIOD(val)		bfin_write32(TIMER4_PERIOD, val)
#define bfin_read_TIMER4_WIDTH()		bfin_read32(TIMER4_WIDTH)
#define bfin_write_TIMER4_WIDTH(val)		bfin_write32(TIMER4_WIDTH, val)

#define bfin_read_TIMER5_CONFIG()		bfin_read16(TIMER5_CONFIG)
#define bfin_write_TIMER5_CONFIG(val)		bfin_write16(TIMER5_CONFIG, val)
#define bfin_read_TIMER5_COUNTER()		bfin_read32(TIMER5_COUNTER)
#define bfin_write_TIMER5_COUNTER(val)		bfin_write32(TIMER5_COUNTER, val)
#define bfin_read_TIMER5_PERIOD()		bfin_read32(TIMER5_PERIOD)
#define bfin_write_TIMER5_PERIOD(val)		bfin_write32(TIMER5_PERIOD, val)
#define bfin_read_TIMER5_WIDTH()		bfin_read32(TIMER5_WIDTH)
#define bfin_write_TIMER5_WIDTH(val)		bfin_write32(TIMER5_WIDTH, val)

#define bfin_read_TIMER6_CONFIG()		bfin_read16(TIMER6_CONFIG)
#define bfin_write_TIMER6_CONFIG(val)		bfin_write16(TIMER6_CONFIG, val)
#define bfin_read_TIMER6_COUNTER()		bfin_read32(TIMER6_COUNTER)
#define bfin_write_TIMER6_COUNTER(val)		bfin_write32(TIMER6_COUNTER, val)
#define bfin_read_TIMER6_PERIOD()		bfin_read32(TIMER6_PERIOD)
#define bfin_write_TIMER6_PERIOD(val)		bfin_write32(TIMER6_PERIOD, val)
#define bfin_read_TIMER6_WIDTH()		bfin_read32(TIMER6_WIDTH)
#define bfin_write_TIMER6_WIDTH(val)		bfin_write32(TIMER6_WIDTH, val)

#define bfin_read_TIMER7_CONFIG()		bfin_read16(TIMER7_CONFIG)
#define bfin_write_TIMER7_CONFIG(val)		bfin_write16(TIMER7_CONFIG, val)
#define bfin_read_TIMER7_COUNTER()		bfin_read32(TIMER7_COUNTER)
#define bfin_write_TIMER7_COUNTER(val)		bfin_write32(TIMER7_COUNTER, val)
#define bfin_read_TIMER7_PERIOD()		bfin_read32(TIMER7_PERIOD)
#define bfin_write_TIMER7_PERIOD(val)		bfin_write32(TIMER7_PERIOD, val)
#define bfin_read_TIMER7_WIDTH()		bfin_read32(TIMER7_WIDTH)
#define bfin_write_TIMER7_WIDTH(val)		bfin_write32(TIMER7_WIDTH, val)

#define bfin_read_TIMER_ENABLE()		bfin_read16(TIMER_ENABLE)
#define bfin_write_TIMER_ENABLE(val)		bfin_write16(TIMER_ENABLE, val)
#define bfin_read_TIMER_DISABLE()		bfin_read16(TIMER_DISABLE)
#define bfin_write_TIMER_DISABLE(val)		bfin_write16(TIMER_DISABLE, val)
#define bfin_read_TIMER_STATUS()		bfin_read32(TIMER_STATUS)
#define bfin_write_TIMER_STATUS(val)		bfin_write32(TIMER_STATUS, val)


/* General Purpose I/O Port F (0xFFC00700 - 0xFFC007FF)								*/
#define bfin_read_PORTFIO()			bfin_read16(PORTFIO)
#define bfin_write_PORTFIO(val)			bfin_write16(PORTFIO, val)
#define bfin_read_PORTFIO_CLEAR()		bfin_read16(PORTFIO_CLEAR)
#define bfin_write_PORTFIO_CLEAR(val)		bfin_write16(PORTFIO_CLEAR, val)
#define bfin_read_PORTFIO_SET()			bfin_read16(PORTFIO_SET)
#define bfin_write_PORTFIO_SET(val)		bfin_write16(PORTFIO_SET, val)
#define bfin_read_PORTFIO_TOGGLE()		bfin_read16(PORTFIO_TOGGLE)
#define bfin_write_PORTFIO_TOGGLE(val)		bfin_write16(PORTFIO_TOGGLE, val)
#define bfin_read_PORTFIO_MASKA()		bfin_read16(PORTFIO_MASKA)
#define bfin_write_PORTFIO_MASKA(val)		bfin_write16(PORTFIO_MASKA, val)
#define bfin_read_PORTFIO_MASKA_CLEAR()		bfin_read16(PORTFIO_MASKA_CLEAR)
#define bfin_write_PORTFIO_MASKA_CLEAR(val)	bfin_write16(PORTFIO_MASKA_CLEAR, val)
#define bfin_read_PORTFIO_MASKA_SET()		bfin_read16(PORTFIO_MASKA_SET)
#define bfin_write_PORTFIO_MASKA_SET(val)	bfin_write16(PORTFIO_MASKA_SET, val)
#define bfin_read_PORTFIO_MASKA_TOGGLE()	bfin_read16(PORTFIO_MASKA_TOGGLE)
#define bfin_write_PORTFIO_MASKA_TOGGLE(val)	bfin_write16(PORTFIO_MASKA_TOGGLE, val)
#define bfin_read_PORTFIO_MASKB()		bfin_read16(PORTFIO_MASKB)
#define bfin_write_PORTFIO_MASKB(val)		bfin_write16(PORTFIO_MASKB, val)
#define bfin_read_PORTFIO_MASKB_CLEAR()		bfin_read16(PORTFIO_MASKB_CLEAR)
#define bfin_write_PORTFIO_MASKB_CLEAR(val)	bfin_write16(PORTFIO_MASKB_CLEAR, val)
#define bfin_read_PORTFIO_MASKB_SET()		bfin_read16(PORTFIO_MASKB_SET)
#define bfin_write_PORTFIO_MASKB_SET(val)	bfin_write16(PORTFIO_MASKB_SET, val)
#define bfin_read_PORTFIO_MASKB_TOGGLE()	bfin_read16(PORTFIO_MASKB_TOGGLE)
#define bfin_write_PORTFIO_MASKB_TOGGLE(val)	bfin_write16(PORTFIO_MASKB_TOGGLE, val)
#define bfin_read_PORTFIO_DIR()			bfin_read16(PORTFIO_DIR)
#define bfin_write_PORTFIO_DIR(val)		bfin_write16(PORTFIO_DIR, val)
#define bfin_read_PORTFIO_POLAR()		bfin_read16(PORTFIO_POLAR)
#define bfin_write_PORTFIO_POLAR(val)		bfin_write16(PORTFIO_POLAR, val)
#define bfin_read_PORTFIO_EDGE()		bfin_read16(PORTFIO_EDGE)
#define bfin_write_PORTFIO_EDGE(val)		bfin_write16(PORTFIO_EDGE, val)
#define bfin_read_PORTFIO_BOTH()		bfin_read16(PORTFIO_BOTH)
#define bfin_write_PORTFIO_BOTH(val)		bfin_write16(PORTFIO_BOTH, val)
#define bfin_read_PORTFIO_INEN()		bfin_read16(PORTFIO_INEN)
#define bfin_write_PORTFIO_INEN(val)		bfin_write16(PORTFIO_INEN, val)


/* SPORT0 Controller		(0xFFC00800 - 0xFFC008FF)								*/
#define bfin_read_SPORT0_TCR1()			bfin_read16(SPORT0_TCR1)
#define bfin_write_SPORT0_TCR1(val)		bfin_write16(SPORT0_TCR1, val)
#define bfin_read_SPORT0_TCR2()			bfin_read16(SPORT0_TCR2)
#define bfin_write_SPORT0_TCR2(val)		bfin_write16(SPORT0_TCR2, val)
#define bfin_read_SPORT0_TCLKDIV()		bfin_read16(SPORT0_TCLKDIV)
#define bfin_write_SPORT0_TCLKDIV(val)		bfin_write16(SPORT0_TCLKDIV, val)
#define bfin_read_SPORT0_TFSDIV()		bfin_read16(SPORT0_TFSDIV)
#define bfin_write_SPORT0_TFSDIV(val)		bfin_write16(SPORT0_TFSDIV, val)
#define bfin_read_SPORT0_TX()			bfin_read32(SPORT0_TX)
#define bfin_write_SPORT0_TX(val)		bfin_write32(SPORT0_TX, val)
#define bfin_read_SPORT0_RX()			bfin_read32(SPORT0_RX)
#define bfin_write_SPORT0_RX(val)		bfin_write32(SPORT0_RX, val)
#define bfin_read_SPORT0_TX32()			bfin_read32(SPORT0_TX32)
#define bfin_write_SPORT0_TX32(val)		bfin_write32(SPORT0_TX32, val)
#define bfin_read_SPORT0_RX32()			bfin_read32(SPORT0_RX32)
#define bfin_write_SPORT0_RX32(val)		bfin_write32(SPORT0_RX32, val)
#define bfin_read_SPORT0_TX16()			bfin_read16(SPORT0_TX16)
#define bfin_write_SPORT0_TX16(val)		bfin_write16(SPORT0_TX16, val)
#define bfin_read_SPORT0_RX16()			bfin_read16(SPORT0_RX16)
#define bfin_write_SPORT0_RX16(val)		bfin_write16(SPORT0_RX16, val)
#define bfin_read_SPORT0_RCR1()			bfin_read16(SPORT0_RCR1)
#define bfin_write_SPORT0_RCR1(val)		bfin_write16(SPORT0_RCR1, val)
#define bfin_read_SPORT0_RCR2()			bfin_read16(SPORT0_RCR2)
#define bfin_write_SPORT0_RCR2(val)		bfin_write16(SPORT0_RCR2, val)
#define bfin_read_SPORT0_RCLKDIV()		bfin_read16(SPORT0_RCLKDIV)
#define bfin_write_SPORT0_RCLKDIV(val)		bfin_write16(SPORT0_RCLKDIV, val)
#define bfin_read_SPORT0_RFSDIV()		bfin_read16(SPORT0_RFSDIV)
#define bfin_write_SPORT0_RFSDIV(val)		bfin_write16(SPORT0_RFSDIV, val)
#define bfin_read_SPORT0_STAT()			bfin_read16(SPORT0_STAT)
#define bfin_write_SPORT0_STAT(val)		bfin_write16(SPORT0_STAT, val)
#define bfin_read_SPORT0_CHNL()			bfin_read16(SPORT0_CHNL)
#define bfin_write_SPORT0_CHNL(val)		bfin_write16(SPORT0_CHNL, val)
#define bfin_read_SPORT0_MCMC1()		bfin_read16(SPORT0_MCMC1)
#define bfin_write_SPORT0_MCMC1(val)		bfin_write16(SPORT0_MCMC1, val)
#define bfin_read_SPORT0_MCMC2()		bfin_read16(SPORT0_MCMC2)
#define bfin_write_SPORT0_MCMC2(val)		bfin_write16(SPORT0_MCMC2, val)
#define bfin_read_SPORT0_MTCS0()		bfin_read32(SPORT0_MTCS0)
#define bfin_write_SPORT0_MTCS0(val)		bfin_write32(SPORT0_MTCS0, val)
#define bfin_read_SPORT0_MTCS1()		bfin_read32(SPORT0_MTCS1)
#define bfin_write_SPORT0_MTCS1(val)		bfin_write32(SPORT0_MTCS1, val)
#define bfin_read_SPORT0_MTCS2()		bfin_read32(SPORT0_MTCS2)
#define bfin_write_SPORT0_MTCS2(val)		bfin_write32(SPORT0_MTCS2, val)
#define bfin_read_SPORT0_MTCS3()		bfin_read32(SPORT0_MTCS3)
#define bfin_write_SPORT0_MTCS3(val)		bfin_write32(SPORT0_MTCS3, val)
#define bfin_read_SPORT0_MRCS0()		bfin_read32(SPORT0_MRCS0)
#define bfin_write_SPORT0_MRCS0(val)		bfin_write32(SPORT0_MRCS0, val)
#define bfin_read_SPORT0_MRCS1()		bfin_read32(SPORT0_MRCS1)
#define bfin_write_SPORT0_MRCS1(val)		bfin_write32(SPORT0_MRCS1, val)
#define bfin_read_SPORT0_MRCS2()		bfin_read32(SPORT0_MRCS2)
#define bfin_write_SPORT0_MRCS2(val)		bfin_write32(SPORT0_MRCS2, val)
#define bfin_read_SPORT0_MRCS3()		bfin_read32(SPORT0_MRCS3)
#define bfin_write_SPORT0_MRCS3(val)		bfin_write32(SPORT0_MRCS3, val)


/* SPORT1 Controller		(0xFFC00900 - 0xFFC009FF)								*/
#define bfin_read_SPORT1_TCR1()			bfin_read16(SPORT1_TCR1)
#define bfin_write_SPORT1_TCR1(val)		bfin_write16(SPORT1_TCR1, val)
#define bfin_read_SPORT1_TCR2()			bfin_read16(SPORT1_TCR2)
#define bfin_write_SPORT1_TCR2(val)		bfin_write16(SPORT1_TCR2, val)
#define bfin_read_SPORT1_TCLKDIV()		bfin_read16(SPORT1_TCLKDIV)
#define bfin_write_SPORT1_TCLKDIV(val)		bfin_write16(SPORT1_TCLKDIV, val)
#define bfin_read_SPORT1_TFSDIV()		bfin_read16(SPORT1_TFSDIV)
#define bfin_write_SPORT1_TFSDIV(val)		bfin_write16(SPORT1_TFSDIV, val)
#define bfin_read_SPORT1_TX()			bfin_read32(SPORT1_TX)
#define bfin_write_SPORT1_TX(val)		bfin_write32(SPORT1_TX, val)
#define bfin_read_SPORT1_RX()			bfin_read32(SPORT1_RX)
#define bfin_write_SPORT1_RX(val)		bfin_write32(SPORT1_RX, val)
#define bfin_read_SPORT1_TX32()			bfin_read32(SPORT1_TX32)
#define bfin_write_SPORT1_TX32(val)		bfin_write32(SPORT1_TX32, val)
#define bfin_read_SPORT1_RX32()			bfin_read32(SPORT1_RX32)
#define bfin_write_SPORT1_RX32(val)		bfin_write32(SPORT1_RX32, val)
#define bfin_read_SPORT1_TX16()			bfin_read16(SPORT1_TX16)
#define bfin_write_SPORT1_TX16(val)		bfin_write16(SPORT1_TX16, val)
#define bfin_read_SPORT1_RX16()			bfin_read16(SPORT1_RX16)
#define bfin_write_SPORT1_RX16(val)		bfin_write16(SPORT1_RX16, val)
#define bfin_read_SPORT1_RCR1()			bfin_read16(SPORT1_RCR1)
#define bfin_write_SPORT1_RCR1(val)		bfin_write16(SPORT1_RCR1, val)
#define bfin_read_SPORT1_RCR2()			bfin_read16(SPORT1_RCR2)
#define bfin_write_SPORT1_RCR2(val)		bfin_write16(SPORT1_RCR2, val)
#define bfin_read_SPORT1_RCLKDIV()		bfin_read16(SPORT1_RCLKDIV)
#define bfin_write_SPORT1_RCLKDIV(val)		bfin_write16(SPORT1_RCLKDIV, val)
#define bfin_read_SPORT1_RFSDIV()		bfin_read16(SPORT1_RFSDIV)
#define bfin_write_SPORT1_RFSDIV(val)		bfin_write16(SPORT1_RFSDIV, val)
#define bfin_read_SPORT1_STAT()			bfin_read16(SPORT1_STAT)
#define bfin_write_SPORT1_STAT(val)		bfin_write16(SPORT1_STAT, val)
#define bfin_read_SPORT1_CHNL()			bfin_read16(SPORT1_CHNL)
#define bfin_write_SPORT1_CHNL(val)		bfin_write16(SPORT1_CHNL, val)
#define bfin_read_SPORT1_MCMC1()		bfin_read16(SPORT1_MCMC1)
#define bfin_write_SPORT1_MCMC1(val)		bfin_write16(SPORT1_MCMC1, val)
#define bfin_read_SPORT1_MCMC2()		bfin_read16(SPORT1_MCMC2)
#define bfin_write_SPORT1_MCMC2(val)		bfin_write16(SPORT1_MCMC2, val)
#define bfin_read_SPORT1_MTCS0()		bfin_read32(SPORT1_MTCS0)
#define bfin_write_SPORT1_MTCS0(val)		bfin_write32(SPORT1_MTCS0, val)
#define bfin_read_SPORT1_MTCS1()		bfin_read32(SPORT1_MTCS1)
#define bfin_write_SPORT1_MTCS1(val)		bfin_write32(SPORT1_MTCS1, val)
#define bfin_read_SPORT1_MTCS2()		bfin_read32(SPORT1_MTCS2)
#define bfin_write_SPORT1_MTCS2(val)		bfin_write32(SPORT1_MTCS2, val)
#define bfin_read_SPORT1_MTCS3()		bfin_read32(SPORT1_MTCS3)
#define bfin_write_SPORT1_MTCS3(val)		bfin_write32(SPORT1_MTCS3, val)
#define bfin_read_SPORT1_MRCS0()		bfin_read32(SPORT1_MRCS0)
#define bfin_write_SPORT1_MRCS0(val)		bfin_write32(SPORT1_MRCS0, val)
#define bfin_read_SPORT1_MRCS1()		bfin_read32(SPORT1_MRCS1)
#define bfin_write_SPORT1_MRCS1(val)		bfin_write32(SPORT1_MRCS1, val)
#define bfin_read_SPORT1_MRCS2()		bfin_read32(SPORT1_MRCS2)
#define bfin_write_SPORT1_MRCS2(val)		bfin_write32(SPORT1_MRCS2, val)
#define bfin_read_SPORT1_MRCS3()		bfin_read32(SPORT1_MRCS3)
#define bfin_write_SPORT1_MRCS3(val)		bfin_write32(SPORT1_MRCS3, val)


/* External Bus Interface Unit (0xFFC00A00 - 0xFFC00AFF)							*/
#define bfin_read_EBIU_AMGCTL()			bfin_read16(EBIU_AMGCTL)
#define bfin_write_EBIU_AMGCTL(val)		bfin_write16(EBIU_AMGCTL, val)
#define bfin_read_EBIU_AMBCTL0()		bfin_read32(EBIU_AMBCTL0)
#define bfin_write_EBIU_AMBCTL0(val)		bfin_write32(EBIU_AMBCTL0, val)
#define bfin_read_EBIU_AMBCTL1()		bfin_read32(EBIU_AMBCTL1)
#define bfin_write_EBIU_AMBCTL1(val)		bfin_write32(EBIU_AMBCTL1, val)
#define bfin_read_EBIU_SDGCTL()			bfin_read32(EBIU_SDGCTL)
#define bfin_write_EBIU_SDGCTL(val)		bfin_write32(EBIU_SDGCTL, val)
#define bfin_read_EBIU_SDBCTL()			bfin_read16(EBIU_SDBCTL)
#define bfin_write_EBIU_SDBCTL(val)		bfin_write16(EBIU_SDBCTL, val)
#define bfin_read_EBIU_SDRRC()			bfin_read16(EBIU_SDRRC)
#define bfin_write_EBIU_SDRRC(val)		bfin_write16(EBIU_SDRRC, val)
#define bfin_read_EBIU_SDSTAT()			bfin_read16(EBIU_SDSTAT)
#define bfin_write_EBIU_SDSTAT(val)		bfin_write16(EBIU_SDSTAT, val)


/* DMA Traffic Control Registers													*/
#define bfin_read_DMA_TC_PER()			bfin_read16(DMA_TC_PER)
#define bfin_write_DMA_TC_PER(val)		bfin_write16(DMA_TC_PER, val)
#define bfin_read_DMA_TC_CNT()			bfin_read16(DMA_TC_CNT)
#define bfin_write_DMA_TC_CNT(val)		bfin_write16(DMA_TC_CNT, val)

/* Alternate deprecated register names (below) provided for backwards code compatibility */
#define bfin_read_DMA_TCPER()			bfin_read16(DMA_TCPER)
#define bfin_write_DMA_TCPER(val)		bfin_write16(DMA_TCPER, val)
#define bfin_read_DMA_TCCNT()			bfin_read16(DMA_TCCNT)
#define bfin_write_DMA_TCCNT(val)		bfin_write16(DMA_TCCNT, val)

/* DMA Controller																	*/
#define bfin_read_DMA0_CONFIG()			bfin_read16(DMA0_CONFIG)
#define bfin_write_DMA0_CONFIG(val)		bfin_write16(DMA0_CONFIG, val)
#define bfin_read_DMA0_NEXT_DESC_PTR()		bfin_read32(DMA0_NEXT_DESC_PTR)
#define bfin_write_DMA0_NEXT_DESC_PTR(val)	bfin_write32(DMA0_NEXT_DESC_PTR, val)
#define bfin_read_DMA0_START_ADDR()		bfin_read32(DMA0_START_ADDR)
#define bfin_write_DMA0_START_ADDR(val)		bfin_write32(DMA0_START_ADDR, val)
#define bfin_read_DMA0_X_COUNT()		bfin_read16(DMA0_X_COUNT)
#define bfin_write_DMA0_X_COUNT(val)		bfin_write16(DMA0_X_COUNT, val)
#define bfin_read_DMA0_Y_COUNT()		bfin_read16(DMA0_Y_COUNT)
#define bfin_write_DMA0_Y_COUNT(val)		bfin_write16(DMA0_Y_COUNT, val)
#define bfin_read_DMA0_X_MODIFY()		bfin_read16(DMA0_X_MODIFY)
#define bfin_write_DMA0_X_MODIFY(val)		bfin_write16(DMA0_X_MODIFY, val)
#define bfin_read_DMA0_Y_MODIFY()		bfin_read16(DMA0_Y_MODIFY)
#define bfin_write_DMA0_Y_MODIFY(val)		bfin_write16(DMA0_Y_MODIFY, val)
#define bfin_read_DMA0_CURR_DESC_PTR()		bfin_read32(DMA0_CURR_DESC_PTR)
#define bfin_write_DMA0_CURR_DESC_PTR(val)	bfin_write32(DMA0_CURR_DESC_PTR, val)
#define bfin_read_DMA0_CURR_ADDR()		bfin_read32(DMA0_CURR_ADDR)
#define bfin_write_DMA0_CURR_ADDR(val)		bfin_write32(DMA0_CURR_ADDR, val)
#define bfin_read_DMA0_CURR_X_COUNT()		bfin_read16(DMA0_CURR_X_COUNT)
#define bfin_write_DMA0_CURR_X_COUNT(val)	bfin_write16(DMA0_CURR_X_COUNT, val)
#define bfin_read_DMA0_CURR_Y_COUNT()		bfin_read16(DMA0_CURR_Y_COUNT)
#define bfin_write_DMA0_CURR_Y_COUNT(val)	bfin_write16(DMA0_CURR_Y_COUNT, val)
#define bfin_read_DMA0_IRQ_STATUS()		bfin_read16(DMA0_IRQ_STATUS)
#define bfin_write_DMA0_IRQ_STATUS(val)		bfin_write16(DMA0_IRQ_STATUS, val)
#define bfin_read_DMA0_PERIPHERAL_MAP()		bfin_read16(DMA0_PERIPHERAL_MAP)
#define bfin_write_DMA0_PERIPHERAL_MAP(val)	bfin_write16(DMA0_PERIPHERAL_MAP, val)

#define bfin_read_DMA1_CONFIG()			bfin_read16(DMA1_CONFIG)
#define bfin_write_DMA1_CONFIG(val)		bfin_write16(DMA1_CONFIG, val)
#define bfin_read_DMA1_NEXT_DESC_PTR()		bfin_read32(DMA1_NEXT_DESC_PTR)
#define bfin_write_DMA1_NEXT_DESC_PTR(val)	bfin_write32(DMA1_NEXT_DESC_PTR, val)
#define bfin_read_DMA1_START_ADDR()		bfin_read32(DMA1_START_ADDR)
#define bfin_write_DMA1_START_ADDR(val)		bfin_write32(DMA1_START_ADDR, val)
#define bfin_read_DMA1_X_COUNT()		bfin_read16(DMA1_X_COUNT)
#define bfin_write_DMA1_X_COUNT(val)		bfin_write16(DMA1_X_COUNT, val)
#define bfin_read_DMA1_Y_COUNT()		bfin_read16(DMA1_Y_COUNT)
#define bfin_write_DMA1_Y_COUNT(val)		bfin_write16(DMA1_Y_COUNT, val)
#define bfin_read_DMA1_X_MODIFY()		bfin_read16(DMA1_X_MODIFY)
#define bfin_write_DMA1_X_MODIFY(val)		bfin_write16(DMA1_X_MODIFY, val)
#define bfin_read_DMA1_Y_MODIFY()		bfin_read16(DMA1_Y_MODIFY)
#define bfin_write_DMA1_Y_MODIFY(val)		bfin_write16(DMA1_Y_MODIFY, val)
#define bfin_read_DMA1_CURR_DESC_PTR()		bfin_read32(DMA1_CURR_DESC_PTR)
#define bfin_write_DMA1_CURR_DESC_PTR(val)	bfin_write32(DMA1_CURR_DESC_PTR, val)
#define bfin_read_DMA1_CURR_ADDR()		bfin_read32(DMA1_CURR_ADDR)
#define bfin_write_DMA1_CURR_ADDR(val)		bfin_write32(DMA1_CURR_ADDR, val)
#define bfin_read_DMA1_CURR_X_COUNT()		bfin_read16(DMA1_CURR_X_COUNT)
#define bfin_write_DMA1_CURR_X_COUNT(val)	bfin_write16(DMA1_CURR_X_COUNT, val)
#define bfin_read_DMA1_CURR_Y_COUNT()		bfin_read16(DMA1_CURR_Y_COUNT)
#define bfin_write_DMA1_CURR_Y_COUNT(val)	bfin_write16(DMA1_CURR_Y_COUNT, val)
#define bfin_read_DMA1_IRQ_STATUS()		bfin_read16(DMA1_IRQ_STATUS)
#define bfin_write_DMA1_IRQ_STATUS(val)		bfin_write16(DMA1_IRQ_STATUS, val)
#define bfin_read_DMA1_PERIPHERAL_MAP()		bfin_read16(DMA1_PERIPHERAL_MAP)
#define bfin_write_DMA1_PERIPHERAL_MAP(val)	bfin_write16(DMA1_PERIPHERAL_MAP, val)

#define bfin_read_DMA2_CONFIG()			bfin_read16(DMA2_CONFIG)
#define bfin_write_DMA2_CONFIG(val)		bfin_write16(DMA2_CONFIG, val)
#define bfin_read_DMA2_NEXT_DESC_PTR()		bfin_read32(DMA2_NEXT_DESC_PTR)
#define bfin_write_DMA2_NEXT_DESC_PTR(val)	bfin_write32(DMA2_NEXT_DESC_PTR, val)
#define bfin_read_DMA2_START_ADDR()		bfin_read32(DMA2_START_ADDR)
#define bfin_write_DMA2_START_ADDR(val)		bfin_write32(DMA2_START_ADDR, val)
#define bfin_read_DMA2_X_COUNT()		bfin_read16(DMA2_X_COUNT)
#define bfin_write_DMA2_X_COUNT(val)		bfin_write16(DMA2_X_COUNT, val)
#define bfin_read_DMA2_Y_COUNT()		bfin_read16(DMA2_Y_COUNT)
#define bfin_write_DMA2_Y_COUNT(val)		bfin_write16(DMA2_Y_COUNT, val)
#define bfin_read_DMA2_X_MODIFY()		bfin_read16(DMA2_X_MODIFY)
#define bfin_write_DMA2_X_MODIFY(val)		bfin_write16(DMA2_X_MODIFY, val)
#define bfin_read_DMA2_Y_MODIFY()		bfin_read16(DMA2_Y_MODIFY)
#define bfin_write_DMA2_Y_MODIFY(val)		bfin_write16(DMA2_Y_MODIFY, val)
#define bfin_read_DMA2_CURR_DESC_PTR()		bfin_read32(DMA2_CURR_DESC_PTR)
#define bfin_write_DMA2_CURR_DESC_PTR(val)	bfin_write32(DMA2_CURR_DESC_PTR, val)
#define bfin_read_DMA2_CURR_ADDR()		bfin_read32(DMA2_CURR_ADDR)
#define bfin_write_DMA2_CURR_ADDR(val)		bfin_write32(DMA2_CURR_ADDR, val)
#define bfin_read_DMA2_CURR_X_COUNT()		bfin_read16(DMA2_CURR_X_COUNT)
#define bfin_write_DMA2_CURR_X_COUNT(val)	bfin_write16(DMA2_CURR_X_COUNT, val)
#define bfin_read_DMA2_CURR_Y_COUNT()		bfin_read16(DMA2_CURR_Y_COUNT)
#define bfin_write_DMA2_CURR_Y_COUNT(val)	bfin_write16(DMA2_CURR_Y_COUNT, val)
#define bfin_read_DMA2_IRQ_STATUS()		bfin_read16(DMA2_IRQ_STATUS)
#define bfin_write_DMA2_IRQ_STATUS(val)		bfin_write16(DMA2_IRQ_STATUS, val)
#define bfin_read_DMA2_PERIPHERAL_MAP()		bfin_read16(DMA2_PERIPHERAL_MAP)
#define bfin_write_DMA2_PERIPHERAL_MAP(val)	bfin_write16(DMA2_PERIPHERAL_MAP, val)

#define bfin_read_DMA3_CONFIG()			bfin_read16(DMA3_CONFIG)
#define bfin_write_DMA3_CONFIG(val)		bfin_write16(DMA3_CONFIG, val)
#define bfin_read_DMA3_NEXT_DESC_PTR()		bfin_read32(DMA3_NEXT_DESC_PTR)
#define bfin_write_DMA3_NEXT_DESC_PTR(val)	bfin_write32(DMA3_NEXT_DESC_PTR, val)
#define bfin_read_DMA3_START_ADDR()		bfin_read32(DMA3_START_ADDR)
#define bfin_write_DMA3_START_ADDR(val)		bfin_write32(DMA3_START_ADDR, val)
#define bfin_read_DMA3_X_COUNT()		bfin_read16(DMA3_X_COUNT)
#define bfin_write_DMA3_X_COUNT(val)		bfin_write16(DMA3_X_COUNT, val)
#define bfin_read_DMA3_Y_COUNT()		bfin_read16(DMA3_Y_COUNT)
#define bfin_write_DMA3_Y_COUNT(val)		bfin_write16(DMA3_Y_COUNT, val)
#define bfin_read_DMA3_X_MODIFY()		bfin_read16(DMA3_X_MODIFY)
#define bfin_write_DMA3_X_MODIFY(val)		bfin_write16(DMA3_X_MODIFY, val)
#define bfin_read_DMA3_Y_MODIFY()		bfin_read16(DMA3_Y_MODIFY)
#define bfin_write_DMA3_Y_MODIFY(val)		bfin_write16(DMA3_Y_MODIFY, val)
#define bfin_read_DMA3_CURR_DESC_PTR()		bfin_read32(DMA3_CURR_DESC_PTR)
#define bfin_write_DMA3_CURR_DESC_PTR(val)	bfin_write32(DMA3_CURR_DESC_PTR, val)
#define bfin_read_DMA3_CURR_ADDR()		bfin_read32(DMA3_CURR_ADDR)
#define bfin_write_DMA3_CURR_ADDR(val)		bfin_write32(DMA3_CURR_ADDR, val)
#define bfin_read_DMA3_CURR_X_COUNT()		bfin_read16(DMA3_CURR_X_COUNT)
#define bfin_write_DMA3_CURR_X_COUNT(val)	bfin_write16(DMA3_CURR_X_COUNT, val)
#define bfin_read_DMA3_CURR_Y_COUNT()		bfin_read16(DMA3_CURR_Y_COUNT)
#define bfin_write_DMA3_CURR_Y_COUNT(val)	bfin_write16(DMA3_CURR_Y_COUNT, val)
#define bfin_read_DMA3_IRQ_STATUS()		bfin_read16(DMA3_IRQ_STATUS)
#define bfin_write_DMA3_IRQ_STATUS(val)		bfin_write16(DMA3_IRQ_STATUS, val)
#define bfin_read_DMA3_PERIPHERAL_MAP()		bfin_read16(DMA3_PERIPHERAL_MAP)
#define bfin_write_DMA3_PERIPHERAL_MAP(val)	bfin_write16(DMA3_PERIPHERAL_MAP, val)

#define bfin_read_DMA4_CONFIG()			bfin_read16(DMA4_CONFIG)
#define bfin_write_DMA4_CONFIG(val)		bfin_write16(DMA4_CONFIG, val)
#define bfin_read_DMA4_NEXT_DESC_PTR()		bfin_read32(DMA4_NEXT_DESC_PTR)
#define bfin_write_DMA4_NEXT_DESC_PTR(val)	bfin_write32(DMA4_NEXT_DESC_PTR, val)
#define bfin_read_DMA4_START_ADDR()		bfin_read32(DMA4_START_ADDR)
#define bfin_write_DMA4_START_ADDR(val)		bfin_write32(DMA4_START_ADDR, val)
#define bfin_read_DMA4_X_COUNT()		bfin_read16(DMA4_X_COUNT)
#define bfin_write_DMA4_X_COUNT(val)		bfin_write16(DMA4_X_COUNT, val)
#define bfin_read_DMA4_Y_COUNT()		bfin_read16(DMA4_Y_COUNT)
#define bfin_write_DMA4_Y_COUNT(val)		bfin_write16(DMA4_Y_COUNT, val)
#define bfin_read_DMA4_X_MODIFY()		bfin_read16(DMA4_X_MODIFY)
#define bfin_write_DMA4_X_MODIFY(val)		bfin_write16(DMA4_X_MODIFY, val)
#define bfin_read_DMA4_Y_MODIFY()		bfin_read16(DMA4_Y_MODIFY)
#define bfin_write_DMA4_Y_MODIFY(val)		bfin_write16(DMA4_Y_MODIFY, val)
#define bfin_read_DMA4_CURR_DESC_PTR()		bfin_read32(DMA4_CURR_DESC_PTR)
#define bfin_write_DMA4_CURR_DESC_PTR(val)	bfin_write32(DMA4_CURR_DESC_PTR, val)
#define bfin_read_DMA4_CURR_ADDR()		bfin_read32(DMA4_CURR_ADDR)
#define bfin_write_DMA4_CURR_ADDR(val)		bfin_write32(DMA4_CURR_ADDR, val)
#define bfin_read_DMA4_CURR_X_COUNT()		bfin_read16(DMA4_CURR_X_COUNT)
#define bfin_write_DMA4_CURR_X_COUNT(val)	bfin_write16(DMA4_CURR_X_COUNT, val)
#define bfin_read_DMA4_CURR_Y_COUNT()		bfin_read16(DMA4_CURR_Y_COUNT)
#define bfin_write_DMA4_CURR_Y_COUNT(val)	bfin_write16(DMA4_CURR_Y_COUNT, val)
#define bfin_read_DMA4_IRQ_STATUS()		bfin_read16(DMA4_IRQ_STATUS)
#define bfin_write_DMA4_IRQ_STATUS(val)		bfin_write16(DMA4_IRQ_STATUS, val)
#define bfin_read_DMA4_PERIPHERAL_MAP()		bfin_read16(DMA4_PERIPHERAL_MAP)
#define bfin_write_DMA4_PERIPHERAL_MAP(val)	bfin_write16(DMA4_PERIPHERAL_MAP, val)

#define bfin_read_DMA5_CONFIG()			bfin_read16(DMA5_CONFIG)
#define bfin_write_DMA5_CONFIG(val)		bfin_write16(DMA5_CONFIG, val)
#define bfin_read_DMA5_NEXT_DESC_PTR()		bfin_read32(DMA5_NEXT_DESC_PTR)
#define bfin_write_DMA5_NEXT_DESC_PTR(val)	bfin_write32(DMA5_NEXT_DESC_PTR, val)
#define bfin_read_DMA5_START_ADDR()		bfin_read32(DMA5_START_ADDR)
#define bfin_write_DMA5_START_ADDR(val)		bfin_write32(DMA5_START_ADDR, val)
#define bfin_read_DMA5_X_COUNT()		bfin_read16(DMA5_X_COUNT)
#define bfin_write_DMA5_X_COUNT(val)		bfin_write16(DMA5_X_COUNT, val)
#define bfin_read_DMA5_Y_COUNT()		bfin_read16(DMA5_Y_COUNT)
#define bfin_write_DMA5_Y_COUNT(val)		bfin_write16(DMA5_Y_COUNT, val)
#define bfin_read_DMA5_X_MODIFY()		bfin_read16(DMA5_X_MODIFY)
#define bfin_write_DMA5_X_MODIFY(val)		bfin_write16(DMA5_X_MODIFY, val)
#define bfin_read_DMA5_Y_MODIFY()		bfin_read16(DMA5_Y_MODIFY)
#define bfin_write_DMA5_Y_MODIFY(val)		bfin_write16(DMA5_Y_MODIFY, val)
#define bfin_read_DMA5_CURR_DESC_PTR()		bfin_read32(DMA5_CURR_DESC_PTR)
#define bfin_write_DMA5_CURR_DESC_PTR(val)	bfin_write32(DMA5_CURR_DESC_PTR, val)
#define bfin_read_DMA5_CURR_ADDR()		bfin_read32(DMA5_CURR_ADDR)
#define bfin_write_DMA5_CURR_ADDR(val)		bfin_write32(DMA5_CURR_ADDR, val)
#define bfin_read_DMA5_CURR_X_COUNT()		bfin_read16(DMA5_CURR_X_COUNT)
#define bfin_write_DMA5_CURR_X_COUNT(val)	bfin_write16(DMA5_CURR_X_COUNT, val)
#define bfin_read_DMA5_CURR_Y_COUNT()		bfin_read16(DMA5_CURR_Y_COUNT)
#define bfin_write_DMA5_CURR_Y_COUNT(val)	bfin_write16(DMA5_CURR_Y_COUNT, val)
#define bfin_read_DMA5_IRQ_STATUS()		bfin_read16(DMA5_IRQ_STATUS)
#define bfin_write_DMA5_IRQ_STATUS(val)		bfin_write16(DMA5_IRQ_STATUS, val)
#define bfin_read_DMA5_PERIPHERAL_MAP()		bfin_read16(DMA5_PERIPHERAL_MAP)
#define bfin_write_DMA5_PERIPHERAL_MAP(val)	bfin_write16(DMA5_PERIPHERAL_MAP, val)

#define bfin_read_DMA6_CONFIG()			bfin_read16(DMA6_CONFIG)
#define bfin_write_DMA6_CONFIG(val)		bfin_write16(DMA6_CONFIG, val)
#define bfin_read_DMA6_NEXT_DESC_PTR()		bfin_read32(DMA6_NEXT_DESC_PTR)
#define bfin_write_DMA6_NEXT_DESC_PTR(val)	bfin_write32(DMA6_NEXT_DESC_PTR, val)
#define bfin_read_DMA6_START_ADDR()		bfin_read32(DMA6_START_ADDR)
#define bfin_write_DMA6_START_ADDR(val)		bfin_write32(DMA6_START_ADDR, val)
#define bfin_read_DMA6_X_COUNT()		bfin_read16(DMA6_X_COUNT)
#define bfin_write_DMA6_X_COUNT(val)		bfin_write16(DMA6_X_COUNT, val)
#define bfin_read_DMA6_Y_COUNT()		bfin_read16(DMA6_Y_COUNT)
#define bfin_write_DMA6_Y_COUNT(val)		bfin_write16(DMA6_Y_COUNT, val)
#define bfin_read_DMA6_X_MODIFY()		bfin_read16(DMA6_X_MODIFY)
#define bfin_write_DMA6_X_MODIFY(val)		bfin_write16(DMA6_X_MODIFY, val)
#define bfin_read_DMA6_Y_MODIFY()		bfin_read16(DMA6_Y_MODIFY)
#define bfin_write_DMA6_Y_MODIFY(val)		bfin_write16(DMA6_Y_MODIFY, val)
#define bfin_read_DMA6_CURR_DESC_PTR()		bfin_read32(DMA6_CURR_DESC_PTR)
#define bfin_write_DMA6_CURR_DESC_PTR(val)	bfin_write32(DMA6_CURR_DESC_PTR, val)
#define bfin_read_DMA6_CURR_ADDR()		bfin_read32(DMA6_CURR_ADDR)
#define bfin_write_DMA6_CURR_ADDR(val)		bfin_write32(DMA6_CURR_ADDR, val)
#define bfin_read_DMA6_CURR_X_COUNT()		bfin_read16(DMA6_CURR_X_COUNT)
#define bfin_write_DMA6_CURR_X_COUNT(val)	bfin_write16(DMA6_CURR_X_COUNT, val)
#define bfin_read_DMA6_CURR_Y_COUNT()		bfin_read16(DMA6_CURR_Y_COUNT)
#define bfin_write_DMA6_CURR_Y_COUNT(val)	bfin_write16(DMA6_CURR_Y_COUNT, val)
#define bfin_read_DMA6_IRQ_STATUS()		bfin_read16(DMA6_IRQ_STATUS)
#define bfin_write_DMA6_IRQ_STATUS(val)		bfin_write16(DMA6_IRQ_STATUS, val)
#define bfin_read_DMA6_PERIPHERAL_MAP()		bfin_read16(DMA6_PERIPHERAL_MAP)
#define bfin_write_DMA6_PERIPHERAL_MAP(val)	bfin_write16(DMA6_PERIPHERAL_MAP, val)

#define bfin_read_DMA7_CONFIG()			bfin_read16(DMA7_CONFIG)
#define bfin_write_DMA7_CONFIG(val)		bfin_write16(DMA7_CONFIG, val)
#define bfin_read_DMA7_NEXT_DESC_PTR()		bfin_read32(DMA7_NEXT_DESC_PTR)
#define bfin_write_DMA7_NEXT_DESC_PTR(val)	bfin_write32(DMA7_NEXT_DESC_PTR, val)
#define bfin_read_DMA7_START_ADDR()		bfin_read32(DMA7_START_ADDR)
#define bfin_write_DMA7_START_ADDR(val)		bfin_write32(DMA7_START_ADDR, val)
#define bfin_read_DMA7_X_COUNT()		bfin_read16(DMA7_X_COUNT)
#define bfin_write_DMA7_X_COUNT(val)		bfin_write16(DMA7_X_COUNT, val)
#define bfin_read_DMA7_Y_COUNT()		bfin_read16(DMA7_Y_COUNT)
#define bfin_write_DMA7_Y_COUNT(val)		bfin_write16(DMA7_Y_COUNT, val)
#define bfin_read_DMA7_X_MODIFY()		bfin_read16(DMA7_X_MODIFY)
#define bfin_write_DMA7_X_MODIFY(val)		bfin_write16(DMA7_X_MODIFY, val)
#define bfin_read_DMA7_Y_MODIFY()		bfin_read16(DMA7_Y_MODIFY)
#define bfin_write_DMA7_Y_MODIFY(val)		bfin_write16(DMA7_Y_MODIFY, val)
#define bfin_read_DMA7_CURR_DESC_PTR()		bfin_read32(DMA7_CURR_DESC_PTR)
#define bfin_write_DMA7_CURR_DESC_PTR(val)	bfin_write32(DMA7_CURR_DESC_PTR, val)
#define bfin_read_DMA7_CURR_ADDR()		bfin_read32(DMA7_CURR_ADDR)
#define bfin_write_DMA7_CURR_ADDR(val)		bfin_write32(DMA7_CURR_ADDR, val)
#define bfin_read_DMA7_CURR_X_COUNT()		bfin_read16(DMA7_CURR_X_COUNT)
#define bfin_write_DMA7_CURR_X_COUNT(val)	bfin_write16(DMA7_CURR_X_COUNT, val)
#define bfin_read_DMA7_CURR_Y_COUNT()		bfin_read16(DMA7_CURR_Y_COUNT)
#define bfin_write_DMA7_CURR_Y_COUNT(val)	bfin_write16(DMA7_CURR_Y_COUNT, val)
#define bfin_read_DMA7_IRQ_STATUS()		bfin_read16(DMA7_IRQ_STATUS)
#define bfin_write_DMA7_IRQ_STATUS(val)		bfin_write16(DMA7_IRQ_STATUS, val)
#define bfin_read_DMA7_PERIPHERAL_MAP()		bfin_read16(DMA7_PERIPHERAL_MAP)
#define bfin_write_DMA7_PERIPHERAL_MAP(val)	bfin_write16(DMA7_PERIPHERAL_MAP, val)

#define bfin_read_DMA8_CONFIG()			bfin_read16(DMA8_CONFIG)
#define bfin_write_DMA8_CONFIG(val)		bfin_write16(DMA8_CONFIG, val)
#define bfin_read_DMA8_NEXT_DESC_PTR()		bfin_read32(DMA8_NEXT_DESC_PTR)
#define bfin_write_DMA8_NEXT_DESC_PTR(val)	bfin_write32(DMA8_NEXT_DESC_PTR, val)
#define bfin_read_DMA8_START_ADDR()		bfin_read32(DMA8_START_ADDR)
#define bfin_write_DMA8_START_ADDR(val)		bfin_write32(DMA8_START_ADDR, val)
#define bfin_read_DMA8_X_COUNT()		bfin_read16(DMA8_X_COUNT)
#define bfin_write_DMA8_X_COUNT(val)		bfin_write16(DMA8_X_COUNT, val)
#define bfin_read_DMA8_Y_COUNT()		bfin_read16(DMA8_Y_COUNT)
#define bfin_write_DMA8_Y_COUNT(val)		bfin_write16(DMA8_Y_COUNT, val)
#define bfin_read_DMA8_X_MODIFY()		bfin_read16(DMA8_X_MODIFY)
#define bfin_write_DMA8_X_MODIFY(val)		bfin_write16(DMA8_X_MODIFY, val)
#define bfin_read_DMA8_Y_MODIFY()		bfin_read16(DMA8_Y_MODIFY)
#define bfin_write_DMA8_Y_MODIFY(val)		bfin_write16(DMA8_Y_MODIFY, val)
#define bfin_read_DMA8_CURR_DESC_PTR()		bfin_read32(DMA8_CURR_DESC_PTR)
#define bfin_write_DMA8_CURR_DESC_PTR(val)	bfin_write32(DMA8_CURR_DESC_PTR, val)
#define bfin_read_DMA8_CURR_ADDR()		bfin_read32(DMA8_CURR_ADDR)
#define bfin_write_DMA8_CURR_ADDR(val)		bfin_write32(DMA8_CURR_ADDR, val)
#define bfin_read_DMA8_CURR_X_COUNT()		bfin_read16(DMA8_CURR_X_COUNT)
#define bfin_write_DMA8_CURR_X_COUNT(val)	bfin_write16(DMA8_CURR_X_COUNT, val)
#define bfin_read_DMA8_CURR_Y_COUNT()		bfin_read16(DMA8_CURR_Y_COUNT)
#define bfin_write_DMA8_CURR_Y_COUNT(val)	bfin_write16(DMA8_CURR_Y_COUNT, val)
#define bfin_read_DMA8_IRQ_STATUS()		bfin_read16(DMA8_IRQ_STATUS)
#define bfin_write_DMA8_IRQ_STATUS(val)		bfin_write16(DMA8_IRQ_STATUS, val)
#define bfin_read_DMA8_PERIPHERAL_MAP()		bfin_read16(DMA8_PERIPHERAL_MAP)
#define bfin_write_DMA8_PERIPHERAL_MAP(val)	bfin_write16(DMA8_PERIPHERAL_MAP, val)

#define bfin_read_DMA9_CONFIG()			bfin_read16(DMA9_CONFIG)
#define bfin_write_DMA9_CONFIG(val)		bfin_write16(DMA9_CONFIG, val)
#define bfin_read_DMA9_NEXT_DESC_PTR()		bfin_read32(DMA9_NEXT_DESC_PTR)
#define bfin_write_DMA9_NEXT_DESC_PTR(val)	bfin_write32(DMA9_NEXT_DESC_PTR, val)
#define bfin_read_DMA9_START_ADDR()		bfin_read32(DMA9_START_ADDR)
#define bfin_write_DMA9_START_ADDR(val)		bfin_write32(DMA9_START_ADDR, val)
#define bfin_read_DMA9_X_COUNT()		bfin_read16(DMA9_X_COUNT)
#define bfin_write_DMA9_X_COUNT(val)		bfin_write16(DMA9_X_COUNT, val)
#define bfin_read_DMA9_Y_COUNT()		bfin_read16(DMA9_Y_COUNT)
#define bfin_write_DMA9_Y_COUNT(val)		bfin_write16(DMA9_Y_COUNT, val)
#define bfin_read_DMA9_X_MODIFY()		bfin_read16(DMA9_X_MODIFY)
#define bfin_write_DMA9_X_MODIFY(val)		bfin_write16(DMA9_X_MODIFY, val)
#define bfin_read_DMA9_Y_MODIFY()		bfin_read16(DMA9_Y_MODIFY)
#define bfin_write_DMA9_Y_MODIFY(val)		bfin_write16(DMA9_Y_MODIFY, val)
#define bfin_read_DMA9_CURR_DESC_PTR()		bfin_read32(DMA9_CURR_DESC_PTR)
#define bfin_write_DMA9_CURR_DESC_PTR(val)	bfin_write32(DMA9_CURR_DESC_PTR, val)
#define bfin_read_DMA9_CURR_ADDR()		bfin_read32(DMA9_CURR_ADDR)
#define bfin_write_DMA9_CURR_ADDR(val)		bfin_write32(DMA9_CURR_ADDR, val)
#define bfin_read_DMA9_CURR_X_COUNT()		bfin_read16(DMA9_CURR_X_COUNT)
#define bfin_write_DMA9_CURR_X_COUNT(val)	bfin_write16(DMA9_CURR_X_COUNT, val)
#define bfin_read_DMA9_CURR_Y_COUNT()		bfin_read16(DMA9_CURR_Y_COUNT)
#define bfin_write_DMA9_CURR_Y_COUNT(val)	bfin_write16(DMA9_CURR_Y_COUNT, val)
#define bfin_read_DMA9_IRQ_STATUS()		bfin_read16(DMA9_IRQ_STATUS)
#define bfin_write_DMA9_IRQ_STATUS(val)		bfin_write16(DMA9_IRQ_STATUS, val)
#define bfin_read_DMA9_PERIPHERAL_MAP()		bfin_read16(DMA9_PERIPHERAL_MAP)
#define bfin_write_DMA9_PERIPHERAL_MAP(val)	bfin_write16(DMA9_PERIPHERAL_MAP, val)

#define bfin_read_DMA10_CONFIG()		bfin_read16(DMA10_CONFIG)
#define bfin_write_DMA10_CONFIG(val)		bfin_write16(DMA10_CONFIG, val)
#define bfin_read_DMA10_NEXT_DESC_PTR()		bfin_read32(DMA10_NEXT_DESC_PTR)
#define bfin_write_DMA10_NEXT_DESC_PTR(val)	bfin_write32(DMA10_NEXT_DESC_PTR, val)
#define bfin_read_DMA10_START_ADDR()		bfin_read32(DMA10_START_ADDR)
#define bfin_write_DMA10_START_ADDR(val)	bfin_write32(DMA10_START_ADDR, val)
#define bfin_read_DMA10_X_COUNT()		bfin_read16(DMA10_X_COUNT)
#define bfin_write_DMA10_X_COUNT(val)		bfin_write16(DMA10_X_COUNT, val)
#define bfin_read_DMA10_Y_COUNT()		bfin_read16(DMA10_Y_COUNT)
#define bfin_write_DMA10_Y_COUNT(val)		bfin_write16(DMA10_Y_COUNT, val)
#define bfin_read_DMA10_X_MODIFY()		bfin_read16(DMA10_X_MODIFY)
#define bfin_write_DMA10_X_MODIFY(val)		bfin_write16(DMA10_X_MODIFY, val)
#define bfin_read_DMA10_Y_MODIFY()		bfin_read16(DMA10_Y_MODIFY)
#define bfin_write_DMA10_Y_MODIFY(val)		bfin_write16(DMA10_Y_MODIFY, val)
#define bfin_read_DMA10_CURR_DESC_PTR()		bfin_read32(DMA10_CURR_DESC_PTR)
#define bfin_write_DMA10_CURR_DESC_PTR(val)	bfin_write32(DMA10_CURR_DESC_PTR, val)
#define bfin_read_DMA10_CURR_ADDR()		bfin_read32(DMA10_CURR_ADDR)
#define bfin_write_DMA10_CURR_ADDR(val)		bfin_write32(DMA10_CURR_ADDR, val)
#define bfin_read_DMA10_CURR_X_COUNT()		bfin_read16(DMA10_CURR_X_COUNT)
#define bfin_write_DMA10_CURR_X_COUNT(val)	bfin_write16(DMA10_CURR_X_COUNT, val)
#define bfin_read_DMA10_CURR_Y_COUNT()		bfin_read16(DMA10_CURR_Y_COUNT)
#define bfin_write_DMA10_CURR_Y_COUNT(val)	bfin_write16(DMA10_CURR_Y_COUNT, val)
#define bfin_read_DMA10_IRQ_STATUS()		bfin_read16(DMA10_IRQ_STATUS)
#define bfin_write_DMA10_IRQ_STATUS(val)	bfin_write16(DMA10_IRQ_STATUS, val)
#define bfin_read_DMA10_PERIPHERAL_MAP()	bfin_read16(DMA10_PERIPHERAL_MAP)
#define bfin_write_DMA10_PERIPHERAL_MAP(val)	bfin_write16(DMA10_PERIPHERAL_MAP, val)

#define bfin_read_DMA11_CONFIG()		bfin_read16(DMA11_CONFIG)
#define bfin_write_DMA11_CONFIG(val)		bfin_write16(DMA11_CONFIG, val)
#define bfin_read_DMA11_NEXT_DESC_PTR()		bfin_read32(DMA11_NEXT_DESC_PTR)
#define bfin_write_DMA11_NEXT_DESC_PTR(val)	bfin_write32(DMA11_NEXT_DESC_PTR, val)
#define bfin_read_DMA11_START_ADDR()		bfin_read32(DMA11_START_ADDR)
#define bfin_write_DMA11_START_ADDR(val)	bfin_write32(DMA11_START_ADDR, val)
#define bfin_read_DMA11_X_COUNT()		bfin_read16(DMA11_X_COUNT)
#define bfin_write_DMA11_X_COUNT(val)		bfin_write16(DMA11_X_COUNT, val)
#define bfin_read_DMA11_Y_COUNT()		bfin_read16(DMA11_Y_COUNT)
#define bfin_write_DMA11_Y_COUNT(val)		bfin_write16(DMA11_Y_COUNT, val)
#define bfin_read_DMA11_X_MODIFY()		bfin_read16(DMA11_X_MODIFY)
#define bfin_write_DMA11_X_MODIFY(val)		bfin_write16(DMA11_X_MODIFY, val)
#define bfin_read_DMA11_Y_MODIFY()		bfin_read16(DMA11_Y_MODIFY)
#define bfin_write_DMA11_Y_MODIFY(val)		bfin_write16(DMA11_Y_MODIFY, val)
#define bfin_read_DMA11_CURR_DESC_PTR()		bfin_read32(DMA11_CURR_DESC_PTR)
#define bfin_write_DMA11_CURR_DESC_PTR(val)	bfin_write32(DMA11_CURR_DESC_PTR, val)
#define bfin_read_DMA11_CURR_ADDR()		bfin_read32(DMA11_CURR_ADDR)
#define bfin_write_DMA11_CURR_ADDR(val)		bfin_write32(DMA11_CURR_ADDR, val)
#define bfin_read_DMA11_CURR_X_COUNT()		bfin_read16(DMA11_CURR_X_COUNT)
#define bfin_write_DMA11_CURR_X_COUNT(val)	bfin_write16(DMA11_CURR_X_COUNT, val)
#define bfin_read_DMA11_CURR_Y_COUNT()		bfin_read16(DMA11_CURR_Y_COUNT)
#define bfin_write_DMA11_CURR_Y_COUNT(val)	bfin_write16(DMA11_CURR_Y_COUNT, val)
#define bfin_read_DMA11_IRQ_STATUS()		bfin_read16(DMA11_IRQ_STATUS)
#define bfin_write_DMA11_IRQ_STATUS(val)	bfin_write16(DMA11_IRQ_STATUS, val)
#define bfin_read_DMA11_PERIPHERAL_MAP()	bfin_read16(DMA11_PERIPHERAL_MAP)
#define bfin_write_DMA11_PERIPHERAL_MAP(val)	bfin_write16(DMA11_PERIPHERAL_MAP, val)

#define bfin_read_MDMA_D0_CONFIG()		bfin_read16(MDMA_D0_CONFIG)
#define bfin_write_MDMA_D0_CONFIG(val)		bfin_write16(MDMA_D0_CONFIG, val)
#define bfin_read_MDMA_D0_NEXT_DESC_PTR()	bfin_read32(MDMA_D0_NEXT_DESC_PTR)
#define bfin_write_MDMA_D0_NEXT_DESC_PTR(val)	bfin_write32(MDMA_D0_NEXT_DESC_PTR, val)
#define bfin_read_MDMA_D0_START_ADDR()		bfin_read32(MDMA_D0_START_ADDR)
#define bfin_write_MDMA_D0_START_ADDR(val)	bfin_write32(MDMA_D0_START_ADDR, val)
#define bfin_read_MDMA_D0_X_COUNT()		bfin_read16(MDMA_D0_X_COUNT)
#define bfin_write_MDMA_D0_X_COUNT(val)		bfin_write16(MDMA_D0_X_COUNT, val)
#define bfin_read_MDMA_D0_Y_COUNT()		bfin_read16(MDMA_D0_Y_COUNT)
#define bfin_write_MDMA_D0_Y_COUNT(val)		bfin_write16(MDMA_D0_Y_COUNT, val)
#define bfin_read_MDMA_D0_X_MODIFY()		bfin_read16(MDMA_D0_X_MODIFY)
#define bfin_write_MDMA_D0_X_MODIFY(val)	bfin_write16(MDMA_D0_X_MODIFY, val)
#define bfin_read_MDMA_D0_Y_MODIFY()		bfin_read16(MDMA_D0_Y_MODIFY)
#define bfin_write_MDMA_D0_Y_MODIFY(val)	bfin_write16(MDMA_D0_Y_MODIFY, val)
#define bfin_read_MDMA_D0_CURR_DESC_PTR()	bfin_read32(MDMA_D0_CURR_DESC_PTR)
#define bfin_write_MDMA_D0_CURR_DESC_PTR(val)	bfin_write32(MDMA_D0_CURR_DESC_PTR, val)
#define bfin_read_MDMA_D0_CURR_ADDR()		bfin_read32(MDMA_D0_CURR_ADDR)
#define bfin_write_MDMA_D0_CURR_ADDR(val)	bfin_write32(MDMA_D0_CURR_ADDR, val)
#define bfin_read_MDMA_D0_CURR_X_COUNT()	bfin_read16(MDMA_D0_CURR_X_COUNT)
#define bfin_write_MDMA_D0_CURR_X_COUNT(val)	bfin_write16(MDMA_D0_CURR_X_COUNT, val)
#define bfin_read_MDMA_D0_CURR_Y_COUNT()	bfin_read16(MDMA_D0_CURR_Y_COUNT)
#define bfin_write_MDMA_D0_CURR_Y_COUNT(val)	bfin_write16(MDMA_D0_CURR_Y_COUNT, val)
#define bfin_read_MDMA_D0_IRQ_STATUS()		bfin_read16(MDMA_D0_IRQ_STATUS)
#define bfin_write_MDMA_D0_IRQ_STATUS(val)	bfin_write16(MDMA_D0_IRQ_STATUS, val)
#define bfin_read_MDMA_D0_PERIPHERAL_MAP()	bfin_read16(MDMA_D0_PERIPHERAL_MAP)
#define bfin_write_MDMA_D0_PERIPHERAL_MAP(val)	bfin_write16(MDMA_D0_PERIPHERAL_MAP, val)

#define bfin_read_MDMA_S0_CONFIG()		bfin_read16(MDMA_S0_CONFIG)
#define bfin_write_MDMA_S0_CONFIG(val)		bfin_write16(MDMA_S0_CONFIG, val)
#define bfin_read_MDMA_S0_NEXT_DESC_PTR()	bfin_read32(MDMA_S0_NEXT_DESC_PTR)
#define bfin_write_MDMA_S0_NEXT_DESC_PTR(val)	bfin_write32(MDMA_S0_NEXT_DESC_PTR, val)
#define bfin_read_MDMA_S0_START_ADDR()		bfin_read32(MDMA_S0_START_ADDR)
#define bfin_write_MDMA_S0_START_ADDR(val)	bfin_write32(MDMA_S0_START_ADDR, val)
#define bfin_read_MDMA_S0_X_COUNT()		bfin_read16(MDMA_S0_X_COUNT)
#define bfin_write_MDMA_S0_X_COUNT(val)		bfin_write16(MDMA_S0_X_COUNT, val)
#define bfin_read_MDMA_S0_Y_COUNT()		bfin_read16(MDMA_S0_Y_COUNT)
#define bfin_write_MDMA_S0_Y_COUNT(val)		bfin_write16(MDMA_S0_Y_COUNT, val)
#define bfin_read_MDMA_S0_X_MODIFY()		bfin_read16(MDMA_S0_X_MODIFY)
#define bfin_write_MDMA_S0_X_MODIFY(val)	bfin_write16(MDMA_S0_X_MODIFY, val)
#define bfin_read_MDMA_S0_Y_MODIFY()		bfin_read16(MDMA_S0_Y_MODIFY)
#define bfin_write_MDMA_S0_Y_MODIFY(val)	bfin_write16(MDMA_S0_Y_MODIFY, val)
#define bfin_read_MDMA_S0_CURR_DESC_PTR()	bfin_read32(MDMA_S0_CURR_DESC_PTR)
#define bfin_write_MDMA_S0_CURR_DESC_PTR(val)	bfin_write32(MDMA_S0_CURR_DESC_PTR, val)
#define bfin_read_MDMA_S0_CURR_ADDR()		bfin_read32(MDMA_S0_CURR_ADDR)
#define bfin_write_MDMA_S0_CURR_ADDR(val)	bfin_write32(MDMA_S0_CURR_ADDR, val)
#define bfin_read_MDMA_S0_CURR_X_COUNT()	bfin_read16(MDMA_S0_CURR_X_COUNT)
#define bfin_write_MDMA_S0_CURR_X_COUNT(val)	bfin_write16(MDMA_S0_CURR_X_COUNT, val)
#define bfin_read_MDMA_S0_CURR_Y_COUNT()	bfin_read16(MDMA_S0_CURR_Y_COUNT)
#define bfin_write_MDMA_S0_CURR_Y_COUNT(val)	bfin_write16(MDMA_S0_CURR_Y_COUNT, val)
#define bfin_read_MDMA_S0_IRQ_STATUS()		bfin_read16(MDMA_S0_IRQ_STATUS)
#define bfin_write_MDMA_S0_IRQ_STATUS(val)	bfin_write16(MDMA_S0_IRQ_STATUS, val)
#define bfin_read_MDMA_S0_PERIPHERAL_MAP()	bfin_read16(MDMA_S0_PERIPHERAL_MAP)
#define bfin_write_MDMA_S0_PERIPHERAL_MAP(val)	bfin_write16(MDMA_S0_PERIPHERAL_MAP, val)

#define bfin_read_MDMA_D1_CONFIG()		bfin_read16(MDMA_D1_CONFIG)
#define bfin_write_MDMA_D1_CONFIG(val)		bfin_write16(MDMA_D1_CONFIG, val)
#define bfin_read_MDMA_D1_NEXT_DESC_PTR()	bfin_read32(MDMA_D1_NEXT_DESC_PTR)
#define bfin_write_MDMA_D1_NEXT_DESC_PTR(val)	bfin_write32(MDMA_D1_NEXT_DESC_PTR, val)
#define bfin_read_MDMA_D1_START_ADDR()		bfin_read32(MDMA_D1_START_ADDR)
#define bfin_write_MDMA_D1_START_ADDR(val)	bfin_write32(MDMA_D1_START_ADDR, val)
#define bfin_read_MDMA_D1_X_COUNT()		bfin_read16(MDMA_D1_X_COUNT)
#define bfin_write_MDMA_D1_X_COUNT(val)		bfin_write16(MDMA_D1_X_COUNT, val)
#define bfin_read_MDMA_D1_Y_COUNT()		bfin_read16(MDMA_D1_Y_COUNT)
#define bfin_write_MDMA_D1_Y_COUNT(val)		bfin_write16(MDMA_D1_Y_COUNT, val)
#define bfin_read_MDMA_D1_X_MODIFY()		bfin_read16(MDMA_D1_X_MODIFY)
#define bfin_write_MDMA_D1_X_MODIFY(val)	bfin_write16(MDMA_D1_X_MODIFY, val)
#define bfin_read_MDMA_D1_Y_MODIFY()		bfin_read16(MDMA_D1_Y_MODIFY)
#define bfin_write_MDMA_D1_Y_MODIFY(val)	bfin_write16(MDMA_D1_Y_MODIFY, val)
#define bfin_read_MDMA_D1_CURR_DESC_PTR()	bfin_read32(MDMA_D1_CURR_DESC_PTR)
#define bfin_write_MDMA_D1_CURR_DESC_PTR(val)	bfin_write32(MDMA_D1_CURR_DESC_PTR, val)
#define bfin_read_MDMA_D1_CURR_ADDR()		bfin_read32(MDMA_D1_CURR_ADDR)
#define bfin_write_MDMA_D1_CURR_ADDR(val)	bfin_write32(MDMA_D1_CURR_ADDR, val)
#define bfin_read_MDMA_D1_CURR_X_COUNT()	bfin_read16(MDMA_D1_CURR_X_COUNT)
#define bfin_write_MDMA_D1_CURR_X_COUNT(val)	bfin_write16(MDMA_D1_CURR_X_COUNT, val)
#define bfin_read_MDMA_D1_CURR_Y_COUNT()	bfin_read16(MDMA_D1_CURR_Y_COUNT)
#define bfin_write_MDMA_D1_CURR_Y_COUNT(val)	bfin_write16(MDMA_D1_CURR_Y_COUNT, val)
#define bfin_read_MDMA_D1_IRQ_STATUS()		bfin_read16(MDMA_D1_IRQ_STATUS)
#define bfin_write_MDMA_D1_IRQ_STATUS(val)	bfin_write16(MDMA_D1_IRQ_STATUS, val)
#define bfin_read_MDMA_D1_PERIPHERAL_MAP()	bfin_read16(MDMA_D1_PERIPHERAL_MAP)
#define bfin_write_MDMA_D1_PERIPHERAL_MAP(val)	bfin_write16(MDMA_D1_PERIPHERAL_MAP, val)

#define bfin_read_MDMA_S1_CONFIG()		bfin_read16(MDMA_S1_CONFIG)
#define bfin_write_MDMA_S1_CONFIG(val)		bfin_write16(MDMA_S1_CONFIG, val)
#define bfin_read_MDMA_S1_NEXT_DESC_PTR()	bfin_read32(MDMA_S1_NEXT_DESC_PTR)
#define bfin_write_MDMA_S1_NEXT_DESC_PTR(val)	bfin_write32(MDMA_S1_NEXT_DESC_PTR, val)
#define bfin_read_MDMA_S1_START_ADDR()		bfin_read32(MDMA_S1_START_ADDR)
#define bfin_write_MDMA_S1_START_ADDR(val)	bfin_write32(MDMA_S1_START_ADDR, val)
#define bfin_read_MDMA_S1_X_COUNT()		bfin_read16(MDMA_S1_X_COUNT)
#define bfin_write_MDMA_S1_X_COUNT(val)		bfin_write16(MDMA_S1_X_COUNT, val)
#define bfin_read_MDMA_S1_Y_COUNT()		bfin_read16(MDMA_S1_Y_COUNT)
#define bfin_write_MDMA_S1_Y_COUNT(val)		bfin_write16(MDMA_S1_Y_COUNT, val)
#define bfin_read_MDMA_S1_X_MODIFY()		bfin_read16(MDMA_S1_X_MODIFY)
#define bfin_write_MDMA_S1_X_MODIFY(val)	bfin_write16(MDMA_S1_X_MODIFY, val)
#define bfin_read_MDMA_S1_Y_MODIFY()		bfin_read16(MDMA_S1_Y_MODIFY)
#define bfin_write_MDMA_S1_Y_MODIFY(val)	bfin_write16(MDMA_S1_Y_MODIFY, val)
#define bfin_read_MDMA_S1_CURR_DESC_PTR()	bfin_read32(MDMA_S1_CURR_DESC_PTR)
#define bfin_write_MDMA_S1_CURR_DESC_PTR(val)	bfin_write32(MDMA_S1_CURR_DESC_PTR, val)
#define bfin_read_MDMA_S1_CURR_ADDR()		bfin_read32(MDMA_S1_CURR_ADDR)
#define bfin_write_MDMA_S1_CURR_ADDR(val)	bfin_write32(MDMA_S1_CURR_ADDR, val)
#define bfin_read_MDMA_S1_CURR_X_COUNT()	bfin_read16(MDMA_S1_CURR_X_COUNT)
#define bfin_write_MDMA_S1_CURR_X_COUNT(val)	bfin_write16(MDMA_S1_CURR_X_COUNT, val)
#define bfin_read_MDMA_S1_CURR_Y_COUNT()	bfin_read16(MDMA_S1_CURR_Y_COUNT)
#define bfin_write_MDMA_S1_CURR_Y_COUNT(val)	bfin_write16(MDMA_S1_CURR_Y_COUNT, val)
#define bfin_read_MDMA_S1_IRQ_STATUS()		bfin_read16(MDMA_S1_IRQ_STATUS)
#define bfin_write_MDMA_S1_IRQ_STATUS(val)	bfin_write16(MDMA_S1_IRQ_STATUS, val)
#define bfin_read_MDMA_S1_PERIPHERAL_MAP()	bfin_read16(MDMA_S1_PERIPHERAL_MAP)
#define bfin_write_MDMA_S1_PERIPHERAL_MAP(val)	bfin_write16(MDMA_S1_PERIPHERAL_MAP, val)


/* Parallel Peripheral Interface (0xFFC01000 - 0xFFC010FF)							*/
#define bfin_read_PPI_CONTROL()			bfin_read16(PPI_CONTROL)
#define bfin_write_PPI_CONTROL(val)		bfin_write16(PPI_CONTROL, val)
#define bfin_read_PPI_STATUS()			bfin_read16(PPI_STATUS)
#define bfin_write_PPI_STATUS(val)		bfin_write16(PPI_STATUS, val)
#define bfin_read_PPI_DELAY()			bfin_read16(PPI_DELAY)
#define bfin_write_PPI_DELAY(val)		bfin_write16(PPI_DELAY, val)
#define bfin_read_PPI_COUNT()			bfin_read16(PPI_COUNT)
#define bfin_write_PPI_COUNT(val)		bfin_write16(PPI_COUNT, val)
#define bfin_read_PPI_FRAME()			bfin_read16(PPI_FRAME)
#define bfin_write_PPI_FRAME(val)		bfin_write16(PPI_FRAME, val)


/* Two-Wire Interface		(0xFFC01400 - 0xFFC014FF)								*/

/* General Purpose I/O Port G (0xFFC01500 - 0xFFC015FF)								*/
#define bfin_read_PORTGIO()			bfin_read16(PORTGIO)
#define bfin_write_PORTGIO(val)			bfin_write16(PORTGIO, val)
#define bfin_read_PORTGIO_CLEAR()		bfin_read16(PORTGIO_CLEAR)
#define bfin_write_PORTGIO_CLEAR(val)		bfin_write16(PORTGIO_CLEAR, val)
#define bfin_read_PORTGIO_SET()			bfin_read16(PORTGIO_SET)
#define bfin_write_PORTGIO_SET(val)		bfin_write16(PORTGIO_SET, val)
#define bfin_read_PORTGIO_TOGGLE()		bfin_read16(PORTGIO_TOGGLE)
#define bfin_write_PORTGIO_TOGGLE(val)		bfin_write16(PORTGIO_TOGGLE, val)
#define bfin_read_PORTGIO_MASKA()		bfin_read16(PORTGIO_MASKA)
#define bfin_write_PORTGIO_MASKA(val)		bfin_write16(PORTGIO_MASKA, val)
#define bfin_read_PORTGIO_MASKA_CLEAR()		bfin_read16(PORTGIO_MASKA_CLEAR)
#define bfin_write_PORTGIO_MASKA_CLEAR(val)	bfin_write16(PORTGIO_MASKA_CLEAR, val)
#define bfin_read_PORTGIO_MASKA_SET()		bfin_read16(PORTGIO_MASKA_SET)
#define bfin_write_PORTGIO_MASKA_SET(val)	bfin_write16(PORTGIO_MASKA_SET, val)
#define bfin_read_PORTGIO_MASKA_TOGGLE()	bfin_read16(PORTGIO_MASKA_TOGGLE)
#define bfin_write_PORTGIO_MASKA_TOGGLE(val)	bfin_write16(PORTGIO_MASKA_TOGGLE, val)
#define bfin_read_PORTGIO_MASKB()		bfin_read16(PORTGIO_MASKB)
#define bfin_write_PORTGIO_MASKB(val)		bfin_write16(PORTGIO_MASKB, val)
#define bfin_read_PORTGIO_MASKB_CLEAR()		bfin_read16(PORTGIO_MASKB_CLEAR)
#define bfin_write_PORTGIO_MASKB_CLEAR(val)	bfin_write16(PORTGIO_MASKB_CLEAR, val)
#define bfin_read_PORTGIO_MASKB_SET()		bfin_read16(PORTGIO_MASKB_SET)
#define bfin_write_PORTGIO_MASKB_SET(val)	bfin_write16(PORTGIO_MASKB_SET, val)
#define bfin_read_PORTGIO_MASKB_TOGGLE()	bfin_read16(PORTGIO_MASKB_TOGGLE)
#define bfin_write_PORTGIO_MASKB_TOGGLE(val)	bfin_write16(PORTGIO_MASKB_TOGGLE, val)
#define bfin_read_PORTGIO_DIR()			bfin_read16(PORTGIO_DIR)
#define bfin_write_PORTGIO_DIR(val)		bfin_write16(PORTGIO_DIR, val)
#define bfin_read_PORTGIO_POLAR()		bfin_read16(PORTGIO_POLAR)
#define bfin_write_PORTGIO_POLAR(val)		bfin_write16(PORTGIO_POLAR, val)
#define bfin_read_PORTGIO_EDGE()		bfin_read16(PORTGIO_EDGE)
#define bfin_write_PORTGIO_EDGE(val)		bfin_write16(PORTGIO_EDGE, val)
#define bfin_read_PORTGIO_BOTH()		bfin_read16(PORTGIO_BOTH)
#define bfin_write_PORTGIO_BOTH(val)		bfin_write16(PORTGIO_BOTH, val)
#define bfin_read_PORTGIO_INEN()		bfin_read16(PORTGIO_INEN)
#define bfin_write_PORTGIO_INEN(val)		bfin_write16(PORTGIO_INEN, val)


/* General Purpose I/O Port H (0xFFC01700 - 0xFFC017FF)								*/
#define bfin_read_PORTHIO()			bfin_read16(PORTHIO)
#define bfin_write_PORTHIO(val)			bfin_write16(PORTHIO, val)
#define bfin_read_PORTHIO_CLEAR()		bfin_read16(PORTHIO_CLEAR)
#define bfin_write_PORTHIO_CLEAR(val)		bfin_write16(PORTHIO_CLEAR, val)
#define bfin_read_PORTHIO_SET()			bfin_read16(PORTHIO_SET)
#define bfin_write_PORTHIO_SET(val)		bfin_write16(PORTHIO_SET, val)
#define bfin_read_PORTHIO_TOGGLE()		bfin_read16(PORTHIO_TOGGLE)
#define bfin_write_PORTHIO_TOGGLE(val)		bfin_write16(PORTHIO_TOGGLE, val)
#define bfin_read_PORTHIO_MASKA()		bfin_read16(PORTHIO_MASKA)
#define bfin_write_PORTHIO_MASKA(val)		bfin_write16(PORTHIO_MASKA, val)
#define bfin_read_PORTHIO_MASKA_CLEAR()		bfin_read16(PORTHIO_MASKA_CLEAR)
#define bfin_write_PORTHIO_MASKA_CLEAR(val)	bfin_write16(PORTHIO_MASKA_CLEAR, val)
#define bfin_read_PORTHIO_MASKA_SET()		bfin_read16(PORTHIO_MASKA_SET)
#define bfin_write_PORTHIO_MASKA_SET(val)	bfin_write16(PORTHIO_MASKA_SET, val)
#define bfin_read_PORTHIO_MASKA_TOGGLE()	bfin_read16(PORTHIO_MASKA_TOGGLE)
#define bfin_write_PORTHIO_MASKA_TOGGLE(val)	bfin_write16(PORTHIO_MASKA_TOGGLE, val)
#define bfin_read_PORTHIO_MASKB()		bfin_read16(PORTHIO_MASKB)
#define bfin_write_PORTHIO_MASKB(val)		bfin_write16(PORTHIO_MASKB, val)
#define bfin_read_PORTHIO_MASKB_CLEAR()		bfin_read16(PORTHIO_MASKB_CLEAR)
#define bfin_write_PORTHIO_MASKB_CLEAR(val)	bfin_write16(PORTHIO_MASKB_CLEAR, val)
#define bfin_read_PORTHIO_MASKB_SET()		bfin_read16(PORTHIO_MASKB_SET)
#define bfin_write_PORTHIO_MASKB_SET(val)	bfin_write16(PORTHIO_MASKB_SET, val)
#define bfin_read_PORTHIO_MASKB_TOGGLE()	bfin_read16(PORTHIO_MASKB_TOGGLE)
#define bfin_write_PORTHIO_MASKB_TOGGLE(val)	bfin_write16(PORTHIO_MASKB_TOGGLE, val)
#define bfin_read_PORTHIO_DIR()			bfin_read16(PORTHIO_DIR)
#define bfin_write_PORTHIO_DIR(val)		bfin_write16(PORTHIO_DIR, val)
#define bfin_read_PORTHIO_POLAR()		bfin_read16(PORTHIO_POLAR)
#define bfin_write_PORTHIO_POLAR(val)		bfin_write16(PORTHIO_POLAR, val)
#define bfin_read_PORTHIO_EDGE()		bfin_read16(PORTHIO_EDGE)
#define bfin_write_PORTHIO_EDGE(val)		bfin_write16(PORTHIO_EDGE, val)
#define bfin_read_PORTHIO_BOTH()		bfin_read16(PORTHIO_BOTH)
#define bfin_write_PORTHIO_BOTH(val)		bfin_write16(PORTHIO_BOTH, val)
#define bfin_read_PORTHIO_INEN()		bfin_read16(PORTHIO_INEN)
#define bfin_write_PORTHIO_INEN(val)		bfin_write16(PORTHIO_INEN, val)


/* UART1 Controller		(0xFFC02000 - 0xFFC020FF)								*/
#define bfin_read_UART1_THR()			bfin_read16(UART1_THR)
#define bfin_write_UART1_THR(val)		bfin_write16(UART1_THR, val)
#define bfin_read_UART1_RBR()			bfin_read16(UART1_RBR)
#define bfin_write_UART1_RBR(val)		bfin_write16(UART1_RBR, val)
#define bfin_read_UART1_DLL()			bfin_read16(UART1_DLL)
#define bfin_write_UART1_DLL(val)		bfin_write16(UART1_DLL, val)
#define bfin_read_UART1_IER()			bfin_read16(UART1_IER)
#define bfin_write_UART1_IER(val)		bfin_write16(UART1_IER, val)
#define bfin_read_UART1_DLH()			bfin_read16(UART1_DLH)
#define bfin_write_UART1_DLH(val)		bfin_write16(UART1_DLH, val)
#define bfin_read_UART1_IIR()			bfin_read16(UART1_IIR)
#define bfin_write_UART1_IIR(val)		bfin_write16(UART1_IIR, val)
#define bfin_read_UART1_LCR()			bfin_read16(UART1_LCR)
#define bfin_write_UART1_LCR(val)		bfin_write16(UART1_LCR, val)
#define bfin_read_UART1_MCR()			bfin_read16(UART1_MCR)
#define bfin_write_UART1_MCR(val)		bfin_write16(UART1_MCR, val)
#define bfin_read_UART1_LSR()			bfin_read16(UART1_LSR)
#define bfin_write_UART1_LSR(val)		bfin_write16(UART1_LSR, val)
#define bfin_read_UART1_MSR()			bfin_read16(UART1_MSR)
#define bfin_write_UART1_MSR(val)		bfin_write16(UART1_MSR, val)
#define bfin_read_UART1_SCR()			bfin_read16(UART1_SCR)
#define bfin_write_UART1_SCR(val)		bfin_write16(UART1_SCR, val)
#define bfin_read_UART1_GCTL()			bfin_read16(UART1_GCTL)
#define bfin_write_UART1_GCTL(val)		bfin_write16(UART1_GCTL, val)

/* Omit CAN register sets from the cdefBF534.h (CAN is not in the ADSP-BF52x processor) */

/* Pin Control Registers	(0xFFC03200 - 0xFFC032FF)								*/
#define bfin_read_PORTF_FER()			bfin_read16(PORTF_FER)
#define bfin_write_PORTF_FER(val)		bfin_write16(PORTF_FER, val)
#define bfin_read_PORTG_FER()			bfin_read16(PORTG_FER)
#define bfin_write_PORTG_FER(val)		bfin_write16(PORTG_FER, val)
#define bfin_read_PORTH_FER()			bfin_read16(PORTH_FER)
#define bfin_write_PORTH_FER(val)		bfin_write16(PORTH_FER, val)
#define bfin_read_PORT_MUX()			bfin_read16(PORT_MUX)
#define bfin_write_PORT_MUX(val)		bfin_write16(PORT_MUX, val)


/* Handshake MDMA Registers	(0xFFC03300 - 0xFFC033FF)								*/
#define bfin_read_HMDMA0_CONTROL()		bfin_read16(HMDMA0_CONTROL)
#define bfin_write_HMDMA0_CONTROL(val)		bfin_write16(HMDMA0_CONTROL, val)
#define bfin_read_HMDMA0_ECINIT()		bfin_read16(HMDMA0_ECINIT)
#define bfin_write_HMDMA0_ECINIT(val)		bfin_write16(HMDMA0_ECINIT, val)
#define bfin_read_HMDMA0_BCINIT()		bfin_read16(HMDMA0_BCINIT)
#define bfin_write_HMDMA0_BCINIT(val)		bfin_write16(HMDMA0_BCINIT, val)
#define bfin_read_HMDMA0_ECURGENT()		bfin_read16(HMDMA0_ECURGENT)
#define bfin_write_HMDMA0_ECURGENT(val)		bfin_write16(HMDMA0_ECURGENT, val)
#define bfin_read_HMDMA0_ECOVERFLOW()		bfin_read16(HMDMA0_ECOVERFLOW)
#define bfin_write_HMDMA0_ECOVERFLOW(val)	bfin_write16(HMDMA0_ECOVERFLOW, val)
#define bfin_read_HMDMA0_ECOUNT()		bfin_read16(HMDMA0_ECOUNT)
#define bfin_write_HMDMA0_ECOUNT(val)		bfin_write16(HMDMA0_ECOUNT, val)
#define bfin_read_HMDMA0_BCOUNT()		bfin_read16(HMDMA0_BCOUNT)
#define bfin_write_HMDMA0_BCOUNT(val)		bfin_write16(HMDMA0_BCOUNT, val)

#define bfin_read_HMDMA1_CONTROL()		bfin_read16(HMDMA1_CONTROL)
#define bfin_write_HMDMA1_CONTROL(val)		bfin_write16(HMDMA1_CONTROL, val)
#define bfin_read_HMDMA1_ECINIT()		bfin_read16(HMDMA1_ECINIT)
#define bfin_write_HMDMA1_ECINIT(val)		bfin_write16(HMDMA1_ECINIT, val)
#define bfin_read_HMDMA1_BCINIT()		bfin_read16(HMDMA1_BCINIT)
#define bfin_write_HMDMA1_BCINIT(val)		bfin_write16(HMDMA1_BCINIT, val)
#define bfin_read_HMDMA1_ECURGENT()		bfin_read16(HMDMA1_ECURGENT)
#define bfin_write_HMDMA1_ECURGENT(val)		bfin_write16(HMDMA1_ECURGENT, val)
#define bfin_read_HMDMA1_ECOVERFLOW()		bfin_read16(HMDMA1_ECOVERFLOW)
#define bfin_write_HMDMA1_ECOVERFLOW(val)	bfin_write16(HMDMA1_ECOVERFLOW, val)
#define bfin_read_HMDMA1_ECOUNT()		bfin_read16(HMDMA1_ECOUNT)
#define bfin_write_HMDMA1_ECOUNT(val)		bfin_write16(HMDMA1_ECOUNT, val)
#define bfin_read_HMDMA1_BCOUNT()		bfin_read16(HMDMA1_BCOUNT)
#define bfin_write_HMDMA1_BCOUNT(val)		bfin_write16(HMDMA1_BCOUNT, val)

/* ==== end from cdefBF534.h ==== */

/* GPIO PIN mux (0xFFC03210 - OxFFC03288) */

#define bfin_read_PORTF_MUX()			bfin_read16(PORTF_MUX)
#define bfin_write_PORTF_MUX(val)		bfin_write16(PORTF_MUX, val)
#define bfin_read_PORTG_MUX()			bfin_read16(PORTG_MUX)
#define bfin_write_PORTG_MUX(val)		bfin_write16(PORTG_MUX, val)
#define bfin_read_PORTH_MUX()			bfin_read16(PORTH_MUX)
#define bfin_write_PORTH_MUX(val)		bfin_write16(PORTH_MUX, val)

#define bfin_read_PORTF_DRIVE()			bfin_read16(PORTF_DRIVE)
#define bfin_write_PORTF_DRIVE(val)		bfin_write16(PORTF_DRIVE, val)
#define bfin_read_PORTG_DRIVE()			bfin_read16(PORTG_DRIVE)
#define bfin_write_PORTG_DRIVE(val)		bfin_write16(PORTG_DRIVE, val)
#define bfin_read_PORTH_DRIVE()			bfin_read16(PORTH_DRIVE)
#define bfin_write_PORTH_DRIVE(val)		bfin_write16(PORTH_DRIVE, val)
#define bfin_read_PORTF_SLEW()			bfin_read16(PORTF_SLEW)
#define bfin_write_PORTF_SLEW(val)		bfin_write16(PORTF_SLEW, val)
#define bfin_read_PORTG_SLEW()			bfin_read16(PORTG_SLEW)
#define bfin_write_PORTG_SLEW(val)		bfin_write16(PORTG_SLEW, val)
#define bfin_read_PORTH_SLEW()			bfin_read16(PORTH_SLEW)
#define bfin_write_PORTH_SLEW(val)		bfin_write16(PORTH_SLEW, val)
#define bfin_read_PORTF_HYSTERISIS()		bfin_read16(PORTF_HYSTERISIS)
#define bfin_write_PORTF_HYSTERISIS(val)	bfin_write16(PORTF_HYSTERISIS, val)
#define bfin_read_PORTG_HYSTERISIS()		bfin_read16(PORTG_HYSTERISIS)
#define bfin_write_PORTG_HYSTERISIS(val)	bfin_write16(PORTG_HYSTERISIS, val)
#define bfin_read_PORTH_HYSTERISIS()		bfin_read16(PORTH_HYSTERISIS)
#define bfin_write_PORTH_HYSTERISIS(val)	bfin_write16(PORTH_HYSTERISIS, val)
#define bfin_read_MISCPORT_DRIVE()		bfin_read16(MISCPORT_DRIVE)
#define bfin_write_MISCPORT_DRIVE(val)		bfin_write16(MISCPORT_DRIVE, val)
#define bfin_read_MISCPORT_SLEW()		bfin_read16(MISCPORT_SLEW)
#define bfin_write_MISCPORT_SLEW(val)		bfin_write16(MISCPORT_SLEW, val)
#define bfin_read_MISCPORT_HYSTERISIS()		bfin_read16(MISCPORT_HYSTERISIS)
#define bfin_write_MISCPORT_HYSTERISIS(val)	bfin_write16(MISCPORT_HYSTERISIS, val)

/* HOST Port Registers */

#define bfin_read_HOST_CONTROL()		bfin_read16(HOST_CONTROL)
#define bfin_write_HOST_CONTROL(val)		bfin_write16(HOST_CONTROL, val)
#define bfin_read_HOST_STATUS()			bfin_read16(HOST_STATUS)
#define bfin_write_HOST_STATUS(val)		bfin_write16(HOST_STATUS, val)
#define bfin_read_HOST_TIMEOUT()		bfin_read16(HOST_TIMEOUT)
#define bfin_write_HOST_TIMEOUT(val)		bfin_write16(HOST_TIMEOUT, val)

/* Counter Registers */

#define bfin_read_CNT_CONFIG()			bfin_read16(CNT_CONFIG)
#define bfin_write_CNT_CONFIG(val)		bfin_write16(CNT_CONFIG, val)
#define bfin_read_CNT_IMASK()			bfin_read16(CNT_IMASK)
#define bfin_write_CNT_IMASK(val)		bfin_write16(CNT_IMASK, val)
#define bfin_read_CNT_STATUS()			bfin_read16(CNT_STATUS)
#define bfin_write_CNT_STATUS(val)		bfin_write16(CNT_STATUS, val)
#define bfin_read_CNT_COMMAND()			bfin_read16(CNT_COMMAND)
#define bfin_write_CNT_COMMAND(val)		bfin_write16(CNT_COMMAND, val)
#define bfin_read_CNT_DEBOUNCE()		bfin_read16(CNT_DEBOUNCE)
#define bfin_write_CNT_DEBOUNCE(val)		bfin_write16(CNT_DEBOUNCE, val)
#define bfin_read_CNT_COUNTER()			bfin_read32(CNT_COUNTER)
#define bfin_write_CNT_COUNTER(val)		bfin_write32(CNT_COUNTER, val)
#define bfin_read_CNT_MAX()			bfin_read32(CNT_MAX)
#define bfin_write_CNT_MAX(val)			bfin_write32(CNT_MAX, val)
#define bfin_read_CNT_MIN()			bfin_read32(CNT_MIN)
#define bfin_write_CNT_MIN(val)			bfin_write32(CNT_MIN, val)

/* OTP/FUSE Registers */

#define bfin_read_OTP_CONTROL()			bfin_read16(OTP_CONTROL)
#define bfin_write_OTP_CONTROL(val)		bfin_write16(OTP_CONTROL, val)
#define bfin_read_OTP_BEN()			bfin_read16(OTP_BEN)
#define bfin_write_OTP_BEN(val)			bfin_write16(OTP_BEN, val)
#define bfin_read_OTP_STATUS()			bfin_read16(OTP_STATUS)
#define bfin_write_OTP_STATUS(val)		bfin_write16(OTP_STATUS, val)
#define bfin_read_OTP_TIMING()			bfin_read32(OTP_TIMING)
#define bfin_write_OTP_TIMING(val)		bfin_write32(OTP_TIMING, val)

/* Security Registers */

#define bfin_read_SECURE_SYSSWT()		bfin_read32(SECURE_SYSSWT)
#define bfin_write_SECURE_SYSSWT(val)		bfin_write32(SECURE_SYSSWT, val)
#define bfin_read_SECURE_CONTROL()		bfin_read16(SECURE_CONTROL)
#define bfin_write_SECURE_CONTROL(val)		bfin_write16(SECURE_CONTROL, val)
#define bfin_read_SECURE_STATUS()		bfin_read16(SECURE_STATUS)
#define bfin_write_SECURE_STATUS(val)		bfin_write16(SECURE_STATUS, val)

/* OTP Read/Write Data Buffer Registers */

#define bfin_read_OTP_DATA0()			bfin_read32(OTP_DATA0)
#define bfin_write_OTP_DATA0(val)		bfin_write32(OTP_DATA0, val)
#define bfin_read_OTP_DATA1()			bfin_read32(OTP_DATA1)
#define bfin_write_OTP_DATA1(val)		bfin_write32(OTP_DATA1, val)
#define bfin_read_OTP_DATA2()			bfin_read32(OTP_DATA2)
#define bfin_write_OTP_DATA2(val)		bfin_write32(OTP_DATA2, val)
#define bfin_read_OTP_DATA3()			bfin_read32(OTP_DATA3)
#define bfin_write_OTP_DATA3(val)		bfin_write32(OTP_DATA3, val)

/* NFC Registers */

#define bfin_read_NFC_CTL()			bfin_read16(NFC_CTL)
#define bfin_write_NFC_CTL(val)			bfin_write16(NFC_CTL, val)
#define bfin_read_NFC_STAT()			bfin_read16(NFC_STAT)
#define bfin_write_NFC_STAT(val)		bfin_write16(NFC_STAT, val)
#define bfin_read_NFC_IRQSTAT()			bfin_read16(NFC_IRQSTAT)
#define bfin_write_NFC_IRQSTAT(val)		bfin_write16(NFC_IRQSTAT, val)
#define bfin_read_NFC_IRQMASK()			bfin_read16(NFC_IRQMASK)
#define bfin_write_NFC_IRQMASK(val)		bfin_write16(NFC_IRQMASK, val)
#define bfin_read_NFC_ECC0()			bfin_read16(NFC_ECC0)
#define bfin_write_NFC_ECC0(val)		bfin_write16(NFC_ECC0, val)
#define bfin_read_NFC_ECC1()			bfin_read16(NFC_ECC1)
#define bfin_write_NFC_ECC1(val)		bfin_write16(NFC_ECC1, val)
#define bfin_read_NFC_ECC2()			bfin_read16(NFC_ECC2)
#define bfin_write_NFC_ECC2(val)		bfin_write16(NFC_ECC2, val)
#define bfin_read_NFC_ECC3()			bfin_read16(NFC_ECC3)
#define bfin_write_NFC_ECC3(val)		bfin_write16(NFC_ECC3, val)
#define bfin_read_NFC_COUNT()			bfin_read16(NFC_COUNT)
#define bfin_write_NFC_COUNT(val)		bfin_write16(NFC_COUNT, val)
#define bfin_read_NFC_RST()			bfin_read16(NFC_RST)
#define bfin_write_NFC_RST(val)			bfin_write16(NFC_RST, val)
#define bfin_read_NFC_PGCTL()			bfin_read16(NFC_PGCTL)
#define bfin_write_NFC_PGCTL(val)		bfin_write16(NFC_PGCTL, val)
#define bfin_read_NFC_READ()			bfin_read16(NFC_READ)
#define bfin_write_NFC_READ(val)		bfin_write16(NFC_READ, val)
#define bfin_read_NFC_ADDR()			bfin_read16(NFC_ADDR)
#define bfin_write_NFC_ADDR(val)		bfin_write16(NFC_ADDR, val)
#define bfin_read_NFC_CMD()			bfin_read16(NFC_CMD)
#define bfin_write_NFC_CMD(val)			bfin_write16(NFC_CMD, val)
#define bfin_read_NFC_DATA_WR()			bfin_read16(NFC_DATA_WR)
#define bfin_write_NFC_DATA_WR(val)		bfin_write16(NFC_DATA_WR, val)
#define bfin_read_NFC_DATA_RD()			bfin_read16(NFC_DATA_RD)
#define bfin_write_NFC_DATA_RD(val)		bfin_write16(NFC_DATA_RD, val)

/* These need to be last due to the cdef/linux inter-dependencies */
#include <asm/irq.h>

/* Writing to PLL_CTL initiates a PLL relock sequence. */
static __inline__ void bfin_write_PLL_CTL(unsigned int val)
{
	unsigned long flags, iwr0, iwr1;

	if (val == bfin_read_PLL_CTL())
		return;

	local_irq_save_hw(flags);
	/* Enable the PLL Wakeup bit in SIC IWR */
	iwr0 = bfin_read32(SIC_IWR0);
	iwr1 = bfin_read32(SIC_IWR1);
	/* Only allow PPL Wakeup) */
	bfin_write32(SIC_IWR0, IWR_ENABLE(0));
	bfin_write32(SIC_IWR1, 0);

	bfin_write16(PLL_CTL, val);
	SSYNC();
	asm("IDLE;");

	bfin_write32(SIC_IWR0, iwr0);
	bfin_write32(SIC_IWR1, iwr1);
	local_irq_restore_hw(flags);
}

/* Writing to VR_CTL initiates a PLL relock sequence. */
static __inline__ void bfin_write_VR_CTL(unsigned int val)
{
	unsigned long flags, iwr0, iwr1;

	if (val == bfin_read_VR_CTL())
		return;

	local_irq_save_hw(flags);
	/* Enable the PLL Wakeup bit in SIC IWR */
	iwr0 = bfin_read32(SIC_IWR0);
	iwr1 = bfin_read32(SIC_IWR1);
	/* Only allow PPL Wakeup) */
	bfin_write32(SIC_IWR0, IWR_ENABLE(0));
	bfin_write32(SIC_IWR1, 0);

	bfin_write16(VR_CTL, val);
	SSYNC();
	asm("IDLE;");

	bfin_write32(SIC_IWR0, iwr0);
	bfin_write32(SIC_IWR1, iwr1);
	local_irq_restore_hw(flags);
}

#endif /* _CDEF_BF52X_H */
