<?php
/**
 * Verilog HDL キーワード定義ファイル
 */

$switchHash['`'] = PLUGIN_CODE_SPECIAL_IDENTIFIRE;   // ` から始まる予約語あり
$mkoutline = $option['outline'] = false; // アウトラインモード不可 

// コメント定義
$switchHash['/'] = PLUGIN_CODE_COMMENT;        //  コメントは /* から */ までと // から改行まで
$code_comment = Array(
	'/' => Array(
				 Array('/^\/\*/', '*/', 2),
				 Array('/^\/\//', "\n", 1),
	)
);


$code_css = Array(
  'operator',		// オペレータ関数
  'identifier',	// その他の識別子
  'pragma',		// module, import と pragma
  'system',		// 処理系組み込みの奴 __stdcall とか
  );

$code_keyword = Array(
  'always' => 2,
  'and' => 2,
  'assign' => 2,
  'automatic' => 2,
  'buf' => 2,
  'bufif' => 2,
  'bufif0' => 2,
  'bufif1' => 2,
  'cell' => 2,
  'cmos' => 2,
  'config' => 2,
  'deassign' => 2,
  'defparam' => 2,
  'design' => 2,
  'disable' => 2,
  'edge' => 2,
  'endconfig' => 2,
  'endfunction' => 2,
  'endgenerate' => 2,
  'endmodule' => 2,
  'endprimitive' => 2,
  'endspecify' => 2,
  'endtable' => 2,
  'endtask' => 2,
  'event' => 2,
  'force' => 2,
  'function' => 2,
  'generate' => 2,
  'genvar' => 2,
  'highz0' => 2,
  'highz1' => 2,
  'ifnone' => 2,
  'incdir' => 2,
  'include' => 2,
  'initial' => 2,
  'inout' => 2,
  'input' => 2,
  'instance' => 2,
  'integer' => 2,
  'large' => 2,
  'liblist' => 2,
  'library' => 2,
  'localparam' => 2,
  'macromodule' => 2,
  'medium' => 2,
  'module' => 2,
  'nand' => 2,
  'negedge' => 2,
  'nmos' => 2,
  'nor' => 2,
  'noshowcancelled' => 2,
  'not' => 2,
  'notif' => 2,
  'notif0' => 2,
  'notif1' => 2,
  'or' => 2,
  'output' => 2,
  'parameter' => 2,
  'pmos' => 2,
  'posedge' => 2,
  'primitive' => 2,
  'pull' => 2,
  'pull0' => 2,
  'pull1' => 2,
  'pulldown' => 2,
  'pullup' => 2,
  'pulsestyle_onevent' => 2,
  'pulsestyle_ondetect' => 2,
  'rcmos' => 2,
  'real' => 2,
  'realtime' => 2,
  'reg' => 2,
  'release' => 2,
  'rnmos' => 2,
  'rpmos' => 2,
  'rtran' => 2,
  'rtranif' => 2,
  'rtranif0' => 2,
  'rtranif1' => 2,
  'scalared' => 2,
  'showcancelled' => 2,
  'signed' => 2,
  'small' => 2,
  'specify' => 2,
  'specparam' => 2,
  'strong' => 2,
  'strong0' => 2,
  'strong1' => 2,
  'supply' => 2,
  'supply0' => 2,
  'supply1' => 2,
  'table' => 2,
  'task' => 2,
  'time' => 2,
  'tran' => 2,
  'tranif0' => 2,
  'tranif1' => 2,
  'tri' => 2,
  'tri0' => 2,
  'tri1' => 2,
  'triand' => 2,
  'trior' => 2,
  'trireg' => 2,
  'unsigned' => 2,
  'use' => 2,
  'vectored' => 2,
  'wait' => 2,
  'wand' => 2,
  'weak0' => 2,
  'weak1' => 2,
  'wire' => 2,
  'wor' => 2,
  'xnor' => 2,
  'xor' => 2,
  'begin' => 2,
  'end' => 2,
  'fork' => 2,
  'join' => 2,
  'if' => 2,
  'else' => 2,
  'case' => 2,
  'casex' => 2,
  'casez' => 2,
  'default' => 2,
  'endcase' => 2,
  'forever' => 2,
  'repeat' => 2,
  'while' => 2,
  'for' => 2,
  '`celldefine' => 2,
  '`default_nettype' => 2,
  '`define' => 2,
  '`else' => 2,
  '`elsif' => 2,
  '`endcelldefine' => 2,
  '`endif' => 2,
  '`ifdef' => 2,
  '`ifndef' => 2,
  '`include' => 2,
  '`line' => 2,
  '`nounconnected_drive' => 2,
  '`resetall' => 2,
  '`timescale' => 2,
  '`unconnected_drive' => 2,
  '`undef' => 2,

  );
?>