
/****************************************************************************************************//**
 * @file     LPC43xx.h
 *
 * @status   RELEASE
 *
 * @brief    CMSIS Cortex-M4 Core Peripheral Access Layer Header File for
 *           default LPC43xx Device Series
 *
 * @version  V5
 * @date     9. December 2011
 *
 * @note     Generated with SVDConv V2.6 Build 6c  on Friday, 09.12.2011 13:56:08
 *
 *           from CMSIS SVD File 'LPC43xxv5.xml' Version 5,
 *           created on Friday, 09.12.2011 21:56:03, last modified on Friday, 09.12.2011 21:56:04
 *
 *******************************************************************************************************/



/** @addtogroup (null)
  * @{
  */

/** @addtogroup LPC43xx
  * @{
  */

#ifndef __LPC43XX_H__
#define __LPC43XX_H__

#ifdef __cplusplus
extern "C" {
#endif 



/********************************************
** Start of section using anonymous unions **
*********************************************/

#if defined(__ARMCC_VERSION)
  #pragma push
  #pragma anon_unions
#elif defined(__CWCC__)
  #pragma push
  #pragma cpp_extensions on
#elif defined(__GNUC__)
  /* anonymous unions are enabled by default */
#elif defined(__IAR_SYSTEMS_ICC__)
  #pragma push
  #pragma language=extended
#else
  #error Not supported compiler type
#endif


 /* Interrupt Number Definition */

typedef enum {
// -------------------------  Cortex-M4 Processor Exceptions Numbers  -----------------------------
  Reset_IRQn                        = -15,  /*!<   1  Reset Vector, invoked on Power up and warm reset */
  NonMaskableInt_IRQn               = -14,  /*!<   2  Non maskable Interrupt, cannot be stopped or preempted */
  HardFault_IRQn                    = -13,  /*!<   3  Hard Fault, all classes of Fault */
  MemoryManagement_IRQn             = -12,  /*!<   4  Memory Management, MPU mismatch, including Access Violation and No Match */
  BusFault_IRQn                     = -11,  /*!<   5  Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */
  UsageFault_IRQn                   = -10,  /*!<   6  Usage Fault, i.e. Undef Instruction, Illegal State Transition */
  SVCall_IRQn                       =  -5,  /*!<  11  System Service Call via SVC instruction */
  DebugMonitor_IRQn                 =  -4,  /*!<  12  Debug Monitor                    */
  PendSV_IRQn                       =  -2,  /*!<  14  Pendable request for system service */
  SysTick_IRQn                      =  -1,  /*!<  15  System Tick Timer                */
// ---------------------------  LPC43xx Specific Interrupt Numbers  -------------------------------
  DAC_IRQn                          =   0,  /*!<   0  DAC                              */
  M0CORE_IRQn                  		=   1,  /*!<   1  M0a                              */
  DMA_IRQn                          =   2,  /*!<   2  DMA                              */
  RESERVED1_IRQn                    =   3,  /*!<   3  EZH/EDM                          */
  RESERVED2_IRQn                    =   4,
  ETHERNET_IRQn                     =   5,  /*!<   5  ETHERNET                         */
  SDIO_IRQn                         =   6,  /*!<   6  SDIO                             */
  LCD_IRQn                          =   7,  /*!<   7  LCD                              */
  USB0_IRQn                         =   8,  /*!<   8  USB0                             */
  USB1_IRQn                         =   9,  /*!<   9  USB1                             */
  SCT_IRQn                          =  10,  /*!<  10  SCT                              */
  RITIMER_IRQn                      =  11,  /*!<  11  RITIMER                          */
  TIMER0_IRQn                       =  12,  /*!<  12  TIMER0                           */
  TIMER1_IRQn                       =  13,  /*!<  13  TIMER1                           */
  TIMER2_IRQn                       =  14,  /*!<  14  TIMER2                           */
  TIMER3_IRQn                       =  15,  /*!<  15  TIMER3                           */
  MCPWM_IRQn                        =  16,  /*!<  16  MCPWM                            */
  ADC0_IRQn                         =  17,  /*!<  17  ADC0                             */
  I2C0_IRQn                         =  18,  /*!<  18  I2C0                             */
  I2C1_IRQn                         =  19,  /*!<  19  I2C1                             */
  SPI_INT_IRQn                      =  20,  /*!<  20  SPI_INT                          */
  ADC1_IRQn                         =  21,  /*!<  21  ADC1                             */
  SSP0_IRQn                         =  22,  /*!<  22  SSP0                             */
  SSP1_IRQn                         =  23,  /*!<  23  SSP1                             */
  USART0_IRQn                       =  24,  /*!<  24  USART0                           */
  UART1_IRQn                        =  25,  /*!<  25  UART1                            */
  USART2_IRQn                       =  26,  /*!<  26  USART2                           */
  USART3_IRQn                       =  27,  /*!<  27  USART3                           */
  I2S0_IRQn                         =  28,  /*!<  28  I2S0                             */
  I2S1_IRQn                         =  29,  /*!<  29  I2S1                             */
  RESERVED4_IRQn                    =  30,
  SGPIO_IINT_IRQn                   =  31,  /*!<  31  SGPIO_IINT                       */
  PIN_INT0_IRQn                     =  32,  /*!<  32  PIN_INT0                         */
  PIN_INT1_IRQn                     =  33,  /*!<  33  PIN_INT1                         */
  PIN_INT2_IRQn                     =  34,  /*!<  34  PIN_INT2                         */
  PIN_INT3_IRQn                     =  35,  /*!<  35  PIN_INT3                         */
  PIN_INT4_IRQn                     =  36,  /*!<  36  PIN_INT4                         */
  PIN_INT5_IRQn                     =  37,  /*!<  37  PIN_INT5                         */
  PIN_INT6_IRQn                     =  38,  /*!<  38  PIN_INT6                         */
  PIN_INT7_IRQn                     =  39,  /*!<  39  PIN_INT7                         */
  GINT0_IRQn                        =  40,  /*!<  40  GINT0                            */
  GINT1_IRQn                        =  41,  /*!<  41  GINT1                            */
  EVENTROUTER_IRQn                  =  42,  /*!<  42  EVENTROUTER                      */
  C_CAN1_IRQn                       =  43,  /*!<  43  C_CAN1                           */
  RESERVED6_IRQn                    =  44,
  RESERVED7_IRQn                    =  45,  /*!<  45  VADC                             */
  ATIMER_IRQn                       =  46,  /*!<  46  ATIMER                           */
  RTC_IRQn                          =  47,  /*!<  47  RTC                              */
  RESERVED8_IRQn                    =  48,
  WWDT_IRQn                         =  49,  /*!<  49  WWDT                             */
  RESERVED9_IRQn                    =  50,
  C_CAN0_IRQn                       =  51,  /*!<  51  C_CAN0                           */
  QEI_IRQn                          =  52,  /*!<  52  QEI                              */

// -------------------------  Cortex-M0 Processor Exceptions Numbers  -----------------------------
  M0_Reset_IRQn                     = -15,  /*!<   1  Reset Vector, invoked on Power up and warm reset */
  M0_NonMaskableInt_IRQn            = -14,  /*!<   2  Non maskable Interrupt, cannot be stopped or preempted */
  M0_HardFault_IRQn                 = -13,  /*!<   3  Hard Fault, all classes of Fault */
  M0_SVCall_IRQn                    =  -5,  /*!<  11  System Service Call via SVC instruction */
  M0_DebugMonitor_IRQn              =  -4,  /*!<  12  Debug Monitor                    */
  M0_PendSV_IRQn                    =  -2,  /*!<  14  Pendable request for system service */
  M0_SysTick_IRQn                   =  -1,  /*!<  15  System Tick Timer                */
// ---------------------------  LPC43xx Specific Interrupt Numbers  -------------------------------
  M0_RTC_IRQn                       =   0,  /*!<   0  RTC                              */
  M0_M4CORE_IRQn					=   1,  /*!<   1  M4                               */
  M0_DMA_IRQn                       =   2,  /*!<   2  DMA                              */
  M0_RESERVED0_IRQn					=   3,
  M0_RESERVED1_IRQn					=   4,
  M0_ETHERNET_IRQn                  =   5,  /*!<   5  ETHERNET                         */
  M0_SDIO_IRQn                      =   6,  /*!<   6  SDIO                             */
  M0_LCD_IRQn                       =   7,  /*!<   7  LCD                              */
  M0_USB0_IRQn                      =   8,  /*!<   8  USB0                             */
  M0_USB1_IRQn                      =   9,  /*!<   9  USB1                             */
  M0_SCT_IRQn                       =  10,  /*!<  10  SCT                              */
  M0_RITIMER_OR_WWDT_IRQn           =  11,  /*!<  11  RITIMER_OR_WWDT                  */
  M0_TIMER0_IRQn                    =  12,  /*!<  12  TIMER0                           */
  M0_GINT1_IRQn                     =  13,  /*!<  13  GINT1                            */
  M0_TIMER3_IRQn                    =  15,  /*!<  15  TIMER3                           */
  M0_RESERVED2_IRQn					=  14,
  M0_RESERVED3_IRQn					=  15,
  M0_MCPWM_IRQn                     =  16,  /*!<  16  MCPWM                            */
  M0_ADC0_IRQn                      =  17,  /*!<  17  ADC0                             */
  M0_I2C0_OR_I2C1_IRQn              =  18,  /*!<  18  I2C0_OR_I2C1                     */
  M0_SGPIO_IRQn                     =  19,  /*!<  19  SGPIO                            */
  M0_SPI_OR_DAC_IRQn                =  20,  /*!<  20  SPI_OR_DAC                       */
  M0_ADC1_IRQn                      =  21,  /*!<  21  ADC1                             */
  M0_SSP0_OR_SSP1_IRQn              =  22,  /*!<  22  SSP0_OR_SSP1                     */
  M0_EVENTROUTER_IRQn               =  23,  /*!<  23  EVENTROUTER                      */
  M0_USART0_IRQn                    =  24,  /*!<  24  USART0                           */
  M0_UART1_IRQn                     =  25,  /*!<  25  UART1                            */
  M0_USART2_OR_C_CAN1_IRQn          =  26,  /*!<  26  USART2_OR_C_CAN1                 */
  M0_USART3_IRQn                    =  27,  /*!<  27  USART3                           */
  M0_I2S0_OR_I2S1_OR_QEI_IRQn       =  28,  /*!<  28  I2S0_OR_I2S1_OR_QEI              */
  M0_C_CAN0_IRQn                    =  29   /*!<  29  C_CAN0                           */
} IRQn_Type;

 /* Event Router Input (ERI) Number Definitions */
typedef enum {
  WAKEUP0_ERIn                      = 0,
  WAKEUP1_ERIn                      = 1,
  WAKEUP2_ERIn                      = 2,
  WAKEUP3_ERIn                      = 3,
  ATIMER_ERIn                       = 4,
  RTC_ERIn                          = 5,
  BOD1_ERIn                         = 6,  /* Bod trip 1 */
  WWDT_ERIn                         = 7,
  ETH_ERIn                          = 8,
  USB0_ERIn                         = 9,
  USB1_ERIn                         = 10,
  SDIO_ERIn                         = 11,
  CAN_ERIn                          = 12, /* CAN0/1 or'ed */
  TIM2_ERIn                         = 13,
  TIM6_ERIn                         = 14,
  QEI_ERIn                          = 15,
  TIM14_ERIn                        = 16,
  RESERVED0_ERIn                    = 17, /* M0s */
  RESERVED1_ERIn                    = 18, /* M3/M4 */
  RESET_ERIn                        = 19
}ERIn_Type;

/** @addtogroup Configuration_of_CMSIS
  * @{
  */

/* Processor and Core Peripheral Section */ /* Configuration of the Cortex-M4 Processor and Core Peripherals */

#ifdef CORE_M4
#define __CM4_REV              0x0000       /*!< Cortex-M4 Core Revision               */
#define __MPU_PRESENT             1         /*!< MPU present or not                    */
#define __NVIC_PRIO_BITS          4         /*!< Number of Bits used for Priority Levels */
#define __Vendor_SysTickConfig    	0         	/*!< Set to 1 if different SysTick Config is used */
#define __FPU_PRESENT             1         /*!< FPU present or not                    */
/** @} */ /* End of group Configuration_of_CMSIS */

#include <core_cm4.h>                       /*!< Cortex-M4 processor and core peripherals */
#else
#ifdef CORE_M0
#define __MPU_PRESENT             0         /*!< MPU present or not                    */
#define __NVIC_PRIO_BITS          2         /*!< Number of Bits used for Priority Levels */
#define __Vendor_SysTickConfig    	0         	/*!< Set to 1 if different SysTick Config is used */
#define __FPU_PRESENT             0         /*!< FPU present or not                    */
/** @} */ /* End of group Configuration_of_CMSIS */

#include <core_cm0.h>                       /*!< Cortex-M4 processor and core peripherals */
#else
#error Please #define CORE_M0 or CORE_M4
#endif
#endif

/** @} */ /* End of group Configuration_of_CMSIS */
#include "system_LPC43xx.h"                 /*!< LPC43xx System                        */

/** @addtogroup Device_Peripheral_Registers
  * @{
  */


// ------------------------------------------------------------------------------------------------
// -----                                          SCT                                         -----
// ------------------------------------------------------------------------------------------------


/**
  * @brief Product name title=UM10430 Chapter title=LPC18xx State Configurable Timer (SCT) Modification date=1/18/2011 Major revision=0 Minor revision=7  (SCT)
  */

#define CONFIG_SCT_nEV   (16)            /* Number of events */
#define CONFIG_SCT_nRG   (16)            /* Number of match/compare registers */
#define CONFIG_SCT_nOU   (16)            /* Number of outputs */

typedef struct
{
    __IO  uint32_t CONFIG;              /* 0x000 Configuration Register */
    union {
        __IO uint32_t CTRL_U;           /* 0x004 Control Register */
        struct {
            __IO uint16_t CTRL_L;       /* 0x004 low control register */
            __IO uint16_t CTRL_H;       /* 0x006 high control register */
        };
    };
    __IO uint16_t LIMIT_L;              /* 0x008 limit register for counter L */
    __IO uint16_t LIMIT_H;              /* 0x00A limit register for counter H */
    __IO uint16_t HALT_L;               /* 0x00C halt register for counter L */
    __IO uint16_t HALT_H;               /* 0x00E halt register for counter H */
    __IO uint16_t STOP_L;               /* 0x010 stop register for counter L */
    __IO uint16_t STOP_H;               /* 0x012 stop register for counter H */
    __IO uint16_t START_L;              /* 0x014 start register for counter L */
    __IO uint16_t START_H;              /* 0x016 start register for counter H */
         uint32_t RESERVED1[10];        /* 0x018-0x03C reserved */
    union {
        __IO uint32_t COUNT_U;          /* 0x040 counter register */
        struct {
            __IO uint16_t COUNT_L;      /* 0x040 counter register for counter L */
            __IO uint16_t COUNT_H;      /* 0x042 counter register for counter H */
        };
    };
    __IO uint16_t STATE_L;              /* 0x044 state register for counter L */
    __IO uint16_t STATE_H;              /* 0x046 state register for counter H */
    __I  uint32_t INPUT;                /* 0x048 input register */
    __IO uint16_t REGMODE_L;            /* 0x04C match - capture registers mode register L */
    __IO uint16_t REGMODE_H;            /* 0x04E match - capture registers mode register H */
    __IO uint32_t OUTPUT;               /* 0x050 output register */
    __IO uint32_t OUTPUTDIRCTRL;        /* 0x054 Output counter direction Control Register */
    __IO uint32_t RES;                  /* 0x058 conflict resolution register */
    __IO uint32_t DMA0REQUEST;          /* 0x05C DMA0 Request Register */
    __IO uint32_t DMA1REQUEST;          /* 0x060 DMA1 Request Register */
         uint32_t RESERVED2[35];        /* 0x064-0x0EC reserved */
    __IO uint32_t EVEN;                 /* 0x0F0 event enable register */
    __IO uint32_t EVFLAG;               /* 0x0F4 event flag register */
    __IO uint32_t CONEN;                /* 0x0F8 conflict enable register */
    __IO uint32_t CONFLAG;              /* 0x0FC conflict flag register */

    union {
        __IO union {                    /* 0x100-... Match / Capture value */
            uint32_t U;                 /*       SCTMATCH[i].U  Unified 32-bit register */
            struct {
                uint16_t L;             /*       SCTMATCH[i].L  Access to L value */
                uint16_t H;             /*       SCTMATCH[i].H  Access to H value */
            };
        } MATCH[CONFIG_SCT_nRG];
        __I union {
            uint32_t U;                 /*       SCTCAP[i].U  Unified 32-bit register */
            struct {
                uint16_t L;             /*       SCTCAP[i].L  Access to H value */
                uint16_t H;             /*       SCTCAP[i].H  Access to H value */
            };
        } CAP[CONFIG_SCT_nRG];
    };

         uint32_t RESERVED3[32-CONFIG_SCT_nRG];      /* ...-0x17C reserved */

    union {
        __IO uint16_t MATCH_L[CONFIG_SCT_nRG];       /* 0x180-... Match Value L counter */
        __I  uint16_t CAP_L[CONFIG_SCT_nRG];         /* 0x180-... Capture Value L counter */
    };
         uint16_t RESERVED4[32-CONFIG_SCT_nRG];      /* ...-0x1BE reserved */
    union {
        __IO uint16_t MATCH_H[CONFIG_SCT_nRG];       /* 0x1C0-... Match Value H counter */
        __I  uint16_t CAP_H[CONFIG_SCT_nRG];         /* 0x1C0-... Capture Value H counter */
    };
         uint16_t RESERVED5[32-CONFIG_SCT_nRG];      /* ...-0x1FE reserved */

    union {
        __IO union {                    /* 0x200-... Match Reload / Capture Control value */
            uint32_t U;                 /*       SCTMATCHREL[i].U  Unified 32-bit register */
            struct {
                uint16_t L;             /*       SCTMATCHREL[i].L  Access to L value */
                uint16_t H;             /*       SCTMATCHREL[i].H  Access to H value */
            };
        } MATCHREL[CONFIG_SCT_nRG];
        __IO union {
            uint32_t U;                 /*       SCTCAPCTRL[i].U  Unified 32-bit register */
            struct {
                uint16_t L;             /*       SCTCAPCTRL[i].L  Access to H value */
                uint16_t H;             /*       SCTCAPCTRL[i].H  Access to H value */
            };
        } CAPCTRL[CONFIG_SCT_nRG];
    };

         uint32_t RESERVED6[32-CONFIG_SCT_nRG];      /* ...-0x27C reserved */

    union {
        __IO uint16_t MATCHREL_L[CONFIG_SCT_nRG];    /* 0x280-... Match Reload value L counter */
        __IO uint16_t CAPCTRL_L[CONFIG_SCT_nRG];     /* 0x280-... Capture Control value L counter */
    };
         uint16_t RESERVED7[32-CONFIG_SCT_nRG];      /* ...-0x2BE reserved */
    union {
        __IO uint16_t MATCHREL_H[CONFIG_SCT_nRG];    /* 0x2C0-... Match Reload value H counter */
        __IO uint16_t CAPCTRL_H[CONFIG_SCT_nRG];     /* 0x2C0-... Capture Control value H counter */
    };
         uint16_t RESERVED8[32-CONFIG_SCT_nRG];      /* ...-0x2FE reserved */

    __IO struct {                       /* 0x300-0x3FC  SCTEVENT[i].STATE / SCTEVENT[i].CTRL*/
        uint32_t STATE;                 /* Event State Register */
        uint32_t CTRL;                  /* Event Control Register */
    } EVENT[CONFIG_SCT_nEV];

         uint32_t RESERVED9[128-2*CONFIG_SCT_nEV];   /* ...-0x4FC reserved */

    __IO struct {                       /* 0x500-0x57C  SCTOUT[i].SET / SCTOUT[i].CLR */
        uint32_t SET;                   /* Output n Set Register */
        uint32_t CLR;                   /* Output n Clear Register */
    } OUT[CONFIG_SCT_nOU];

         uint32_t RESERVED10[191-2*CONFIG_SCT_nOU];  /* ...-0x7F8 reserved */

    __I  uint32_t MODULECONTENT;        /* 0x7FC Module Content */

} LPC_SCT_Type;


// ------------------------------------------------------------------------------------------------
// -----                                         GPDMA                                        -----
// ------------------------------------------------------------------------------------------------


/**
  * @brief Product name title=UM10430 Chapter title=LPC18xx General Purpose DMA (GPDMA) controller Modification date=1/19/2011 Major revision=0 Minor revision=7  (GPDMA)
  */

typedef struct {                            /*!< (@ 0x40002000) GPDMA Structure        */
  __I  uint32_t  INTSTAT;                   /*!< (@ 0x40002000) DMA Interrupt Status Register */
  __I  uint32_t  INTTCSTAT;                 /*!< (@ 0x40002004) DMA Interrupt Terminal Count Request Status Register */
  __O  uint32_t  INTTCCLEAR;                /*!< (@ 0x40002008) DMA Interrupt Terminal Count Request Clear Register */
  __I  uint32_t  INTERRSTAT;                /*!< (@ 0x4000200C) DMA Interrupt Error Status Register */
  __O  uint32_t  INTERRCLR;                 /*!< (@ 0x40002010) DMA Interrupt Error Clear Register */
  __I  uint32_t  RAWINTTCSTAT;              /*!< (@ 0x40002014) DMA Raw Interrupt Terminal Count Status Register */
  __I  uint32_t  RAWINTERRSTAT;             /*!< (@ 0x40002018) DMA Raw Error Interrupt Status Register */
  __I  uint32_t  ENBLDCHNS;                 /*!< (@ 0x4000201C) DMA Enabled Channel Register */
  __IO uint32_t  SOFTBREQ;                  /*!< (@ 0x40002020) DMA Software Burst Request Register */
  __IO uint32_t  SOFTSREQ;                  /*!< (@ 0x40002024) DMA Software Single Request Register */
  __IO uint32_t  SOFTLBREQ;                 /*!< (@ 0x40002028) DMA Software Last Burst Request Register */
  __IO uint32_t  SOFTLSREQ;                 /*!< (@ 0x4000202C) DMA Software Last Single Request Register */
  __IO uint32_t  CONFIG;                    /*!< (@ 0x40002030) DMA Configuration Register */
  __IO uint32_t  SYNC;                      /*!< (@ 0x40002034) DMA Synchronization Register */
  __I  uint32_t  RESERVED0[50];
  __IO uint32_t  C0SRCADDR;                 /*!< (@ 0x40002100) DMA Channel Source Address Register */
  __IO uint32_t  C0DESTADDR;                /*!< (@ 0x40002104) DMA Channel Destination Address Register */
  __IO uint32_t  C0LLI;                     /*!< (@ 0x40002108) DMA Channel Linked List Item Register */
  __IO uint32_t  C0CONTROL;                 /*!< (@ 0x4000210C) DMA Channel Control Register */
  __IO uint32_t  C0CONFIG;                  /*!< (@ 0x40002110) DMA Channel Configuration Register */
  __I  uint32_t  RESERVED1[3];
  __IO uint32_t  C1SRCADDR;                 /*!< (@ 0x40002120) DMA Channel Source Address Register */
  __IO uint32_t  C1DESTADDR;                /*!< (@ 0x40002124) DMA Channel Destination Address Register */
  __IO uint32_t  C1LLI;                     /*!< (@ 0x40002128) DMA Channel Linked List Item Register */
  __IO uint32_t  C1CONTROL;                 /*!< (@ 0x4000212C) DMA Channel Control Register */
  __IO uint32_t  C1CONFIG;                  /*!< (@ 0x40002130) DMA Channel Configuration Register */
  __I  uint32_t  RESERVED2[3];
  __IO uint32_t  C2SRCADDR;                 /*!< (@ 0x40002140) DMA Channel Source Address Register */
  __IO uint32_t  C2DESTADDR;                /*!< (@ 0x40002144) DMA Channel Destination Address Register */
  __IO uint32_t  C2LLI;                     /*!< (@ 0x40002148) DMA Channel Linked List Item Register */
  __IO uint32_t  C2CONTROL;                 /*!< (@ 0x4000214C) DMA Channel Control Register */
  __IO uint32_t  C2CONFIG;                  /*!< (@ 0x40002150) DMA Channel Configuration Register */
  __I  uint32_t  RESERVED3[3];
  __IO uint32_t  C3SRCADDR;                 /*!< (@ 0x40002160) DMA Channel Source Address Register */
  __IO uint32_t  C3DESTADDR;                /*!< (@ 0x40002164) DMA Channel Destination Address Register */
  __IO uint32_t  C3LLI;                     /*!< (@ 0x40002168) DMA Channel Linked List Item Register */
  __IO uint32_t  C3CONTROL;                 /*!< (@ 0x4000216C) DMA Channel Control Register */
  __IO uint32_t  C3CONFIG;                  /*!< (@ 0x40002170) DMA Channel Configuration Register */
  __I  uint32_t  RESERVED4[3];
  __IO uint32_t  C4SRCADDR;                 /*!< (@ 0x40002180) DMA Channel Source Address Register */
  __IO uint32_t  C4DESTADDR;                /*!< (@ 0x40002184) DMA Channel Destination Address Register */
  __IO uint32_t  C4LLI;                     /*!< (@ 0x40002188) DMA Channel Linked List Item Register */
  __IO uint32_t  C4CONTROL;                 /*!< (@ 0x4000218C) DMA Channel Control Register */
  __IO uint32_t  C4CONFIG;                  /*!< (@ 0x40002190) DMA Channel Configuration Register */
  __I  uint32_t  RESERVED5[3];
  __IO uint32_t  C5SRCADDR;                 /*!< (@ 0x400021A0) DMA Channel Source Address Register */
  __IO uint32_t  C5DESTADDR;                /*!< (@ 0x400021A4) DMA Channel Destination Address Register */
  __IO uint32_t  C5LLI;                     /*!< (@ 0x400021A8) DMA Channel Linked List Item Register */
  __IO uint32_t  C5CONTROL;                 /*!< (@ 0x400021AC) DMA Channel Control Register */
  __IO uint32_t  C5CONFIG;                  /*!< (@ 0x400021B0) DMA Channel Configuration Register */
  __I  uint32_t  RESERVED6[3];
  __IO uint32_t  C6SRCADDR;                 /*!< (@ 0x400021C0) DMA Channel Source Address Register */
  __IO uint32_t  C6DESTADDR;                /*!< (@ 0x400021C4) DMA Channel Destination Address Register */
  __IO uint32_t  C6LLI;                     /*!< (@ 0x400021C8) DMA Channel Linked List Item Register */
  __IO uint32_t  C6CONTROL;                 /*!< (@ 0x400021CC) DMA Channel Control Register */
  __IO uint32_t  C6CONFIG;                  /*!< (@ 0x400021D0) DMA Channel Configuration Register */
  __I  uint32_t  RESERVED7[3];
  __IO uint32_t  C7SRCADDR;                 /*!< (@ 0x400021E0) DMA Channel Source Address Register */
  __IO uint32_t  C7DESTADDR;                /*!< (@ 0x400021E4) DMA Channel Destination Address Register */
  __IO uint32_t  C7LLI;                     /*!< (@ 0x400021E8) DMA Channel Linked List Item Register */
  __IO uint32_t  C7CONTROL;                 /*!< (@ 0x400021EC) DMA Channel Control Register */
  __IO uint32_t  C7CONFIG;                  /*!< (@ 0x400021F0) DMA Channel Configuration Register */
} LPC_GPDMA_Type;


// ------------------------------------------------------------------------------------------------
// -----                                         SDMMC                                        -----
// ------------------------------------------------------------------------------------------------


/**
  * @brief Product name title=UM10430 Chapter title=LPC18xx SD/MMC Modification date=n/a Major revision=n/a Minor revision=n/a  (SDMMC)
  */

typedef struct {                            /*!< (@ 0x40004000) SDMMC Structure        */
  __IO uint32_t  CTRL;                      /*!< (@ 0x40004000) Control Register       */
  __IO uint32_t  PWREN;                     /*!< (@ 0x40004004) Power Enable Register  */
  __IO uint32_t  CLKDIV;                    /*!< (@ 0x40004008) Clock Divider Register */
  __IO uint32_t  CLKSRC;                    /*!< (@ 0x4000400C) SD Clock Source Register */
  __IO uint32_t  CLKENA;                    /*!< (@ 0x40004010) Clock Enable Register  */
  __IO uint32_t  TMOUT;                     /*!< (@ 0x40004014) Timeout Register       */
  __IO uint32_t  CTYPE;                     /*!< (@ 0x40004018) Card Type Register     */
  __IO uint32_t  BLKSIZ;                    /*!< (@ 0x4000401C) Block Size Register    */
  __IO uint32_t  BYTCNT;                    /*!< (@ 0x40004020) Byte Count Register    */
  __IO uint32_t  INTMASK;                   /*!< (@ 0x40004024) Interrupt Mask Register */
  __IO uint32_t  CMDARG;                    /*!< (@ 0x40004028) Command Argument Register */
  __IO uint32_t  CMD;                       /*!< (@ 0x4000402C) Command Register       */
  __I  uint32_t  RESP0;                     /*!< (@ 0x40004030) Response Register 0    */
  __I  uint32_t  RESP1;                     /*!< (@ 0x40004034) Response Register 1    */
  __I  uint32_t  RESP2;                     /*!< (@ 0x40004038) Response Register 2    */
  __I  uint32_t  RESP3;                     /*!< (@ 0x4000403C) Response Register 3    */
  __I  uint32_t  MINTSTS;                   /*!< (@ 0x40004040) Masked Interrupt Status Register */
  __IO uint32_t  RINTSTS;                   /*!< (@ 0x40004044) Raw Interrupt Status Register */
  __I  uint32_t  STATUS;                    /*!< (@ 0x40004048) Status Register        */
  __IO uint32_t  FIFOTH;                    /*!< (@ 0x4000404C) FIFO Threshold Watermark Register */
  __I  uint32_t  CDETECT;                   /*!< (@ 0x40004050) Card Detect Register   */
  __I  uint32_t  WRTPRT;                    /*!< (@ 0x40004054) Write Protect Register */
  __IO uint32_t  GPIO;                      /*!< (@ 0x40004058) General Purpose Input/Output Register */
  __I  uint32_t  TCBCNT;                    /*!< (@ 0x4000405C) Transferred CIU Card Byte Count Register */
  __I  uint32_t  TBBCNT;                    /*!< (@ 0x40004060) Transferred Host to BIU-FIFO Byte Count Register */
  __IO uint32_t  DEBNCE;                    /*!< (@ 0x40004064) Debounce Count Register */
  __IO uint32_t  USRID;                     /*!< (@ 0x40004068) User ID Register       */
  __I  uint32_t  VERID;                     /*!< (@ 0x4000406C) Version ID Register    */
  __I  uint32_t  RESERVED0;
  __IO uint32_t  UHS_REG;                   /*!< (@ 0x40004074) UHS-1 Register         */
  __IO uint32_t  RST_N;                     /*!< (@ 0x40004078) Hardware Reset         */
  __I  uint32_t  RESERVED1;
  __IO uint32_t  BMOD;                      /*!< (@ 0x40004080) Bus Mode Register      */
  __O  uint32_t  PLDMND;                    /*!< (@ 0x40004084) Poll Demand Register   */
  __IO uint32_t  DBADDR;                    /*!< (@ 0x40004088) Descriptor List Base Address Register */
  __IO uint32_t  IDSTS;                     /*!< (@ 0x4000408C) Internal DMAC Status Register */
  __IO uint32_t  IDINTEN;                   /*!< (@ 0x40004090) Internal DMAC Interrupt Enable Register */
  __I  uint32_t  DSCADDR;                   /*!< (@ 0x40004094) Current Host Descriptor Address Register */
  __I  uint32_t  BUFADDR;                   /*!< (@ 0x40004098) Current Buffer Descriptor Address Register */
} LPC_SDMMC_Type;


// ------------------------------------------------------------------------------------------------
// -----                                          EMC                                         -----
// ------------------------------------------------------------------------------------------------


/**
  * @brief Product name title=UM10430 Chapter title=LPC18xx External Memory Controller (EMC) Modification date=1/19/2011 Major revision=0 Minor revision=7  (EMC)
  */

typedef struct {                            /*!< (@ 0x40005000) EMC Structure          */
  __IO uint32_t  CONTROL;                   /*!< (@ 0x40005000) Controls operation of the memory controller. */
  __I  uint32_t  STATUS;                    /*!< (@ 0x40005004) Provides EMC status information. */
  __IO uint32_t  CONFIG;                    /*!< (@ 0x40005008) Configures operation of the memory controller. */
  __I  uint32_t  RESERVED0[5];
  __IO uint32_t  DYNAMICCONTROL;            /*!< (@ 0x40005020) Controls dynamic memory operation. */
  __IO uint32_t  DYNAMICREFRESH;            /*!< (@ 0x40005024) Configures dynamic memory refresh operation. */
  __IO uint32_t  DYNAMICREADCONFIG;         /*!< (@ 0x40005028) Configures the dynamic memory read strategy. */
  __I  uint32_t  RESERVED1;
  __IO uint32_t  DYNAMICRP;                 /*!< (@ 0x40005030) Selects the precharge command period. */
  __IO uint32_t  DYNAMICRAS;                /*!< (@ 0x40005034) Selects the active to precharge command period. */
  __IO uint32_t  DYNAMICSREX;               /*!< (@ 0x40005038) Selects the self-refresh exit time. */
  __IO uint32_t  DYNAMICAPR;                /*!< (@ 0x4000503C) Selects the last-data-out to active command time. */
  __IO uint32_t  DYNAMICDAL;                /*!< (@ 0x40005040) Selects the data-in to active command time. */
  __IO uint32_t  DYNAMICWR;                 /*!< (@ 0x40005044) Selects the write recovery time. */
  __IO uint32_t  DYNAMICRC;                 /*!< (@ 0x40005048) Selects the active to active command period. */
  __IO uint32_t  DYNAMICRFC;                /*!< (@ 0x4000504C) Selects the auto-refresh period. */
  __IO uint32_t  DYNAMICXSR;                /*!< (@ 0x40005050) Selects the exit self-refresh to active command time. */
  __IO uint32_t  DYNAMICRRD;                /*!< (@ 0x40005054) Selects the active bank A to active bank B latency. */
  __IO uint32_t  DYNAMICMRD;                /*!< (@ 0x40005058) Selects the load mode register to active command time. */
  __I  uint32_t  RESERVED2[9];
  __IO uint32_t  STATICEXTENDEDWAIT;        /*!< (@ 0x40005080) Selects time for long static memory read and write transfers. */
  __I  uint32_t  RESERVED3[31];
  __IO uint32_t  DYNAMICCONFIG0;            /*!< (@ 0x40005100) Selects the configuration information for dynamic memory chip select n. */
  __IO uint32_t  DYNAMICRASCAS0;            /*!< (@ 0x40005104) Selects the RAS and CAS latencies for dynamic memory chip select n. */
  __I  uint32_t  RESERVED4[6];
  __IO uint32_t  DYNAMICCONFIG1;            /*!< (@ 0x40005120) Selects the configuration information for dynamic memory chip select n. */
  __IO uint32_t  DYNAMICRASCAS1;            /*!< (@ 0x40005124) Selects the RAS and CAS latencies for dynamic memory chip select n. */
  __I  uint32_t  RESERVED5[6];
  __IO uint32_t  DYNAMICCONFIG2;            /*!< (@ 0x40005140) Selects the configuration information for dynamic memory chip select n. */
  __IO uint32_t  DYNAMICRASCAS2;            /*!< (@ 0x40005144) Selects the RAS and CAS latencies for dynamic memory chip select n. */
  __I  uint32_t  RESERVED6[6];
  __IO uint32_t  DYNAMICCONFIG3;            /*!< (@ 0x40005160) Selects the configuration information for dynamic memory chip select n. */
  __IO uint32_t  DYNAMICRASCAS3;            /*!< (@ 0x40005164) Selects the RAS and CAS latencies for dynamic memory chip select n. */
  __I  uint32_t  RESERVED7[38];
  __IO uint32_t  STATICCONFIG0;             /*!< (@ 0x40005200) Selects the memory configuration for static chip select n. */
  __IO uint32_t  STATICWAITWEN0;            /*!< (@ 0x40005204) Selects the delay from chip select n to write enable. */
  __IO uint32_t  STATICWAITOEN0;            /*!< (@ 0x40005208) Selects the delay from chip select n or address change, whichever is later, to output enable. */
  __IO uint32_t  STATICWAITRD0;             /*!< (@ 0x4000520C) Selects the delay from chip select n to a read access. */
  __IO uint32_t  STATICWAITPAG0;            /*!< (@ 0x40005210) Selects the delay for asynchronous page mode sequential accesses for chip select n. */
  __IO uint32_t  STATICWAITWR0;             /*!< (@ 0x40005214) Selects the delay from chip select n to a write access. */
  __IO uint32_t  STATICWAITTURN0;           /*!< (@ 0x40005218) Selects bus turnaround cycles */
  __I  uint32_t  RESERVED8;
  __IO uint32_t  STATICCONFIG1;             /*!< (@ 0x40005220) Selects the memory configuration for static chip select n. */
  __IO uint32_t  STATICWAITWEN1;            /*!< (@ 0x40005224) Selects the delay from chip select n to write enable. */
  __IO uint32_t  STATICWAITOEN1;            /*!< (@ 0x40005228) Selects the delay from chip select n or address change, whichever is later, to output enable. */
  __IO uint32_t  STATICWAITRD1;             /*!< (@ 0x4000522C) Selects the delay from chip select n to a read access. */
  __IO uint32_t  STATICWAITPAG1;            /*!< (@ 0x40005230) Selects the delay for asynchronous page mode sequential accesses for chip select n. */
  __IO uint32_t  STATICWAITWR1;             /*!< (@ 0x40005234) Selects the delay from chip select n to a write access. */
  __IO uint32_t  STATICWAITTURN1;           /*!< (@ 0x40005238) Selects bus turnaround cycles */
  __I  uint32_t  RESERVED9;
  __IO uint32_t  STATICCONFIG2;             /*!< (@ 0x40005240) Selects the memory configuration for static chip select n. */
  __IO uint32_t  STATICWAITWEN2;            /*!< (@ 0x40005244) Selects the delay from chip select n to write enable. */
  __IO uint32_t  STATICWAITOEN2;            /*!< (@ 0x40005248) Selects the delay from chip select n or address change, whichever is later, to output enable. */
  __IO uint32_t  STATICWAITRD2;             /*!< (@ 0x4000524C) Selects the delay from chip select n to a read access. */
  __IO uint32_t  STATICWAITPAG2;            /*!< (@ 0x40005250) Selects the delay for asynchronous page mode sequential accesses for chip select n. */
  __IO uint32_t  STATICWAITWR2;             /*!< (@ 0x40005254) Selects the delay from chip select n to a write access. */
  __IO uint32_t  STATICWAITTURN2;           /*!< (@ 0x40005258) Selects bus turnaround cycles */
  __I  uint32_t  RESERVED10;
  __IO uint32_t  STATICCONFIG3;             /*!< (@ 0x40005260) Selects the memory configuration for static chip select n. */
  __IO uint32_t  STATICWAITWEN3;            /*!< (@ 0x40005264) Selects the delay from chip select n to write enable. */
  __IO uint32_t  STATICWAITOEN3;            /*!< (@ 0x40005268) Selects the delay from chip select n or address change, whichever is later, to output enable. */
  __IO uint32_t  STATICWAITRD3;             /*!< (@ 0x4000526C) Selects the delay from chip select n to a read access. */
  __IO uint32_t  STATICWAITPAG3;            /*!< (@ 0x40005270) Selects the delay for asynchronous page mode sequential accesses for chip select n. */
  __IO uint32_t  STATICWAITWR3;             /*!< (@ 0x40005274) Selects the delay from chip select n to a write access. */
  __IO uint32_t  STATICWAITTURN3;           /*!< (@ 0x40005278) Selects bus turnaround cycles */
} LPC_EMC_Type;


// ------------------------------------------------------------------------------------------------
// -----                                         USB0                                         -----
// ------------------------------------------------------------------------------------------------


/**
  * @brief Product name title=UM10430 Chapter title=LPC18xx USB0 Host/Device/OTG controller Modification date=1/19/2011 Major revision=0 Minor revision=7  (USB0)
  */

typedef struct {                            /*!< (@ 0x40006000) USB0 Structure         */
  __I  uint32_t  RESERVED0[64];
  __I  uint32_t  CAPLENGTH;                 /*!< (@ 0x40006100) Capability register length */
  __I  uint32_t  HCSPARAMS;                 /*!< (@ 0x40006104) Host controller structural parameters */
  __I  uint32_t  HCCPARAMS;                 /*!< (@ 0x40006108) Host controller capability parameters */
  __I  uint32_t  RESERVED1[5];
  __I  uint32_t  DCIVERSION;                /*!< (@ 0x40006120) Device interface version number */
  __I  uint32_t  RESERVED2[7];
  
  union {
    __IO uint32_t  USBCMD_H;                /*!< (@ 0x40006140) USB command (host mode) */
    __IO uint32_t  USBCMD_D;                /*!< (@ 0x40006140) USB command (device mode) */
  } ;
  
  union {
    __IO uint32_t  USBSTS_H;                /*!< (@ 0x40006144) USB status (host mode) */
    __IO uint32_t  USBSTS_D;                /*!< (@ 0x40006144) USB status (device mode) */
  } ;
  
  union {
    __IO uint32_t  USBINTR_H;               /*!< (@ 0x40006148) USB interrupt enable (host mode) */
    __IO uint32_t  USBINTR_D;               /*!< (@ 0x40006148) USB interrupt enable (device mode) */
  } ;
  
  union {
    __IO uint32_t  FRINDEX_H;               /*!< (@ 0x4000614C) USB frame index (host mode) */
    __IO uint32_t  FRINDEX_D;               /*!< (@ 0x4000614C) USB frame index (device mode) */
  } ;
  __I  uint32_t  RESERVED3;
  
  union {
    __IO uint32_t  PERIODICLISTBASE;        /*!< (@ 0x40006154) Frame list base address (host mode) */
    __IO uint32_t  DEVICEADDR;              /*!< (@ 0x40006154) USB device address (device mode) */
  } ;
  
  union {
    __IO uint32_t  ASYNCLISTADDR;           /*!< (@ 0x40006158) Address of endpoint list in memory */
    __IO uint32_t  ENDPOINTLISTADDR;        /*!< (@ 0x40006158) Address of endpoint list in memory */
  } ;
  __IO uint32_t  TTCTRL;                    /*!< (@ 0x4000615C) Asynchronous buffer status for embedded TT (host mode) */
  __IO uint32_t  BURSTSIZE;                 /*!< (@ 0x40006160) Programmable burst size */
  __IO uint32_t  TXFILLTUNING;              /*!< (@ 0x40006164) Host transmit pre-buffer packet tuning (host mode) */
  __I  uint32_t  RESERVED4[3];
  __IO uint32_t  BINTERVAL;                 /*!< (@ 0x40006174) Length of virtual frame */
  __IO uint32_t  ENDPTNAK;                  /*!< (@ 0x40006178) Endpoint NAK (device mode) */
  __IO uint32_t  ENDPTNAKEN;                /*!< (@ 0x4000617C) Endpoint NAK Enable (device mode) */
  __I  uint32_t  RESERVED5;
  
  union {
    __IO uint32_t  PORTSC1_H;               /*!< (@ 0x40006184) Port 1 status/control (host mode) */
    __IO uint32_t  PORTSC1_D;               /*!< (@ 0x40006184) Port 1 status/control (device mode) */
  } ;
  __I  uint32_t  RESERVED6[7];
  __IO uint32_t  OTGSC;                     /*!< (@ 0x400061A4) OTG status and control */
  
  union {
    __IO uint32_t  USBMODE_H;               /*!< (@ 0x400061A8) USB mode (host mode)   */
    __IO uint32_t  USBMODE_D;               /*!< (@ 0x400061A8) USB device mode (device mode) */
  } ;
  __IO uint32_t  ENDPTSETUPSTAT;            /*!< (@ 0x400061AC) Endpoint setup status  */
  __IO uint32_t  ENDPTPRIME;                /*!< (@ 0x400061B0) Endpoint initialization */
  __IO uint32_t  ENDPTFLUSH;                /*!< (@ 0x400061B4) Endpoint de-initialization */
  __I  uint32_t  ENDPTSTAT;                 /*!< (@ 0x400061B8) Endpoint status        */
  __IO uint32_t  ENDPTCOMPLETE;             /*!< (@ 0x400061BC) Endpoint complete      */
  __IO uint32_t  ENDPTCTRL0;                /*!< (@ 0x400061C0) Endpoint control 0     */
  __IO uint32_t  ENDPTCTRL1;                /*!< (@ 0x400061C4) Endpoint control       */
  __IO uint32_t  ENDPTCTRL2;                /*!< (@ 0x400061C8) Endpoint control       */
  __IO uint32_t  ENDPTCTRL3;                /*!< (@ 0x400061CC) Endpoint control       */
  __IO uint32_t  ENDPTCTRL4;                /*!< (@ 0x400061D0) Endpoint control       */
  __IO uint32_t  ENDPTCTRL5;                /*!< (@ 0x400061D4) Endpoint control       */
} LPC_USB0_Type;


// ------------------------------------------------------------------------------------------------
// -----                                         USB1                                         -----
// ------------------------------------------------------------------------------------------------


/**
  * @brief Product name title=UM10430 Chapter title=LPC18xx USB1 Host/Device controller Modification date=1/19/2011 Major revision=0 Minor revision=7  (USB1)
  */

typedef struct {                            /*!< (@ 0x40007000) USB1 Structure         */
  __I  uint32_t  RESERVED0[64];
  __I  uint32_t  CAPLENGTH;                 /*!< (@ 0x40007100) Capability register length */
  __I  uint32_t  HCSPARAMS;                 /*!< (@ 0x40007104) Host controller structural parameters */
  __I  uint32_t  HCCPARAMS;                 /*!< (@ 0x40007108) Host controller capability parameters */
  __I  uint32_t  RESERVED1[5];
  __I  uint32_t  DCIVERSION;                /*!< (@ 0x40007120) Device interface version number */
  __I  uint32_t  RESERVED2[7];
  
  union {
    __IO uint32_t  USBCMD_H;                /*!< (@ 0x40007140) USB command (host mode) */
    __IO uint32_t  USBCMD_D;                /*!< (@ 0x40007140) USB command (device mode) */
  } ;
  
  union {
    __IO uint32_t  USBSTS_H;                /*!< (@ 0x40007144) USB status (host mode) */
    __IO uint32_t  USBSTS_D;                /*!< (@ 0x40007144) USB status (device mode) */
  } ;
  
  union {
    __IO uint32_t  USBINTR_H;               /*!< (@ 0x40007148) USB interrupt enable (host mode) */
    __IO uint32_t  USBINTR_D;               /*!< (@ 0x40007148) USB interrupt enable (device mode) */
  } ;
  
  union {
    __IO uint32_t  FRINDEX_H;               /*!< (@ 0x4000714C) USB frame index (host mode) */
    __I  uint32_t  FRINDEX_D;               /*!< (@ 0x4000714C) USB frame index (device mode) */
  } ;
  __I  uint32_t  RESERVED3;
  
  union {
    __IO uint32_t  PERIODICLISTBASE;        /*!< (@ 0x40007154) Frame list base address */
    __IO uint32_t  DEVICEADDR;              /*!< (@ 0x40007154) USB device address     */
  } ;
  
  union {
    __IO uint32_t  ASYNCLISTADDR;           /*!< (@ 0x40007158) Address of endpoint list in memory (host mode) */
    __IO uint32_t  ENDPOINTLISTADDR;        /*!< (@ 0x40007158) Address of endpoint list in memory (device mode) */
  } ;
  __IO uint32_t  TTCTRL;                    /*!< (@ 0x4000715C) Asynchronous buffer status for embedded TT (host mode) */
  __IO uint32_t  BURSTSIZE;                 /*!< (@ 0x40007160) Programmable burst size */
  __IO uint32_t  TXFILLTUNING;              /*!< (@ 0x40007164) Host transmit pre-buffer packet tuning (host mode) */
  __I  uint32_t  RESERVED4[2];
  __IO uint32_t  ULPIVIEWPORT;              /*!< (@ 0x40007170) ULPI viewport          */
  __IO uint32_t  BINTERVAL;                 /*!< (@ 0x40007174) Length of virtual frame */
  __IO uint32_t  ENDPTNAK;                  /*!< (@ 0x40007178) Endpoint NAK (device mode) */
  __IO uint32_t  ENDPTNAKEN;                /*!< (@ 0x4000717C) Endpoint NAK Enable (device mode) */
  __I  uint32_t  RESERVED5;
  
  union {
    __IO uint32_t  PORTSC1_H;               /*!< (@ 0x40007184) Port 1 status/control (host mode) */
    __IO uint32_t  PORTSC1_D;               /*!< (@ 0x40007184) Port 1 status/control (device mode) */
  } ;
  __I  uint32_t  RESERVED6[8];
  
  union {
    __IO uint32_t  USBMODE_H;               /*!< (@ 0x400071A8) USB mode (host mode)   */
    __IO uint32_t  USBMODE_D;               /*!< (@ 0x400071A8) USB mode (device mode) */
  } ;
  __IO uint32_t  ENDPTSETUPSTAT;            /*!< (@ 0x400071AC) Endpoint setup status  */
  __IO uint32_t  ENDPTPRIME;                /*!< (@ 0x400071B0) Endpoint initialization */
  __IO uint32_t  ENDPTFLUSH;                /*!< (@ 0x400071B4) Endpoint de-initialization */
  __I  uint32_t  ENDPTSTAT;                 /*!< (@ 0x400071B8) Endpoint status        */
  __IO uint32_t  ENDPTCOMPLETE;             /*!< (@ 0x400071BC) Endpoint complete      */
  __IO uint32_t  ENDPTCTRL0;                /*!< (@ 0x400071C0) Endpoint control 0     */
  __IO uint32_t  ENDPTCTRL1;                /*!< (@ 0x400071C4) Endpoint control       */
  __IO uint32_t  ENDPTCTRL2;                /*!< (@ 0x400071C8) Endpoint control       */
  __IO uint32_t  ENDPTCTRL3;                /*!< (@ 0x400071CC) Endpoint control       */
} LPC_USB1_Type;


// ------------------------------------------------------------------------------------------------
// -----                                          LCD                                         -----
// ------------------------------------------------------------------------------------------------


/**
  * @brief Product name title=UM10430 Chapter title=LPC18xx LCD Modification date=1/19/2011 Major revision=0 Minor revision=7  (LCD)
  */

typedef struct {                            /*!< (@ 0x40008000) LCD Structure          */
  __IO uint32_t  TIMH;                      /*!< (@ 0x40008000) Horizontal Timing Control register */
  __IO uint32_t  TIMV;                      /*!< (@ 0x40008004) Vertical Timing Control register */
  __IO uint32_t  POL;                       /*!< (@ 0x40008008) Clock and Signal Polarity Control register */
  __IO uint32_t  LE;                        /*!< (@ 0x4000800C) Line End Control register */
  __IO uint32_t  UPBASE;                    /*!< (@ 0x40008010) Upper Panel Frame Base Address register */
  __IO uint32_t  LPBASE;                    /*!< (@ 0x40008014) Lower Panel Frame Base Address register */
  __IO uint32_t  CTRL;                      /*!< (@ 0x40008018) LCD Control register   */
  __IO uint32_t  INTMSK;                    /*!< (@ 0x4000801C) Interrupt Mask register */
  __I  uint32_t  INTRAW;                    /*!< (@ 0x40008020) Raw Interrupt Status register */
  __I  uint32_t  INTSTAT;                   /*!< (@ 0x40008024) Masked Interrupt Status register */
  __O  uint32_t  INTCLR;                    /*!< (@ 0x40008028) Interrupt Clear register */
  __I  uint32_t  UPCURR;                    /*!< (@ 0x4000802C) Upper Panel Current Address Value register */
  __I  uint32_t  LPCURR;                    /*!< (@ 0x40008030) Lower Panel Current Address Value register */
  __I  uint32_t  RESERVED0[115];
  __IO uint32_t PAL[256];					/*!< (@ 0x40008200) 256x16-bit Color Palette registers */
  __I  uint32_t  RESERVED1[128];
  __IO uint32_t CRSR_IMG[256];              /*!< (@ 0x40008800) Cursor Image registers */
  __IO uint32_t  CRSR_CTRL;                 /*!< (@ 0x40008C00) Cursor Control register */
  __IO uint32_t  CRSR_CFG;                  /*!< (@ 0x40008C04) Cursor Configuration register */
  __IO uint32_t  CRSR_PAL0;                 /*!< (@ 0x40008C08) Cursor Palette register 0 */
  __IO uint32_t  CRSR_PAL1;                 /*!< (@ 0x40008C0C) Cursor Palette register 1 */
  __IO uint32_t  CRSR_XY;                   /*!< (@ 0x40008C10) Cursor XY Position register */
  __IO uint32_t  CRSR_CLIP;                 /*!< (@ 0x40008C14) Cursor Clip Position register */
  __I  uint32_t  RESERVED2[2];
  __IO uint32_t  CRSR_INTMSK;               /*!< (@ 0x40008C20) Cursor Interrupt Mask register */
  __O  uint32_t  CRSR_INTCLR;               /*!< (@ 0x40008C24) Cursor Interrupt Clear register */
  __I  uint32_t  CRSR_INTRAW;               /*!< (@ 0x40008C28) Cursor Raw Interrupt Status register */
  __I  uint32_t  CRSR_INTSTAT;              /*!< (@ 0x40008C2C) Cursor Masked Interrupt Status register */
} LPC_LCD_Type;


// ------------------------------------------------------------------------------------------------
// -----                                       ETHERNET                                       -----
// ------------------------------------------------------------------------------------------------


/**
  * @brief Product name title=UM10430 Chapter title=LPC18xx Ethernet Modification date=12/9/2011 Major revision=1.1 Minor revision=not available  (ETHERNET)
  */

typedef struct {                            /*!< (@ 0x40010000) ETHERNET Structure     */
  __IO uint32_t  MAC_CONFIG;                /*!< (@ 0x40010000) MAC configuration register */
  __IO uint32_t  MAC_FRAME_FILTER;          /*!< (@ 0x40010004) MAC frame filter       */
  __IO uint32_t  MAC_HASHTABLE_HIGH;        /*!< (@ 0x40010008) Hash table high register */
  __IO uint32_t  MAC_HASHTABLE_LOW;         /*!< (@ 0x4001000C) Hash table low register */
  __IO uint32_t  MAC_MII_ADDR;              /*!< (@ 0x40010010) MII address register   */
  __IO uint32_t  MAC_MII_DATA;              /*!< (@ 0x40010014) MII data register      */
  __IO uint32_t  MAC_FLOW_CTRL;             /*!< (@ 0x40010018) Flow control register  */
  __IO uint32_t  MAC_VLAN_TAG;              /*!< (@ 0x4001001C) VLAN tag register      */
  __I  uint32_t  RESERVED0;
  __I  uint32_t  MAC_DEBUG;                 /*!< (@ 0x40010024) Debug register         */
  __IO uint32_t  MAC_RWAKE_FRFLT;           /*!< (@ 0x40010028) Remote wake-up frame filter */
  __IO uint32_t  MAC_PMT_CTRL_STAT;         /*!< (@ 0x4001002C) PMT control and status */
  __I  uint32_t  RESERVED1[2];
  __I  uint32_t  MAC_INTR;                  /*!< (@ 0x40010038) Interrupt status register */
  __IO uint32_t  MAC_INTR_MASK;             /*!< (@ 0x4001003C) Interrupt mask register */
  __IO uint32_t  MAC_ADDR0_HIGH;            /*!< (@ 0x40010040) MAC address 0 high register */
  __IO uint32_t  MAC_ADDR0_LOW;             /*!< (@ 0x40010044) MAC address 0 low register */
  __I  uint32_t  RESERVED2[430];
  __IO uint32_t  MAC_TIMESTP_CTRL;          /*!< (@ 0x40010700) Time stamp control register */
  __IO uint32_t  SUBSECOND_INCR;            /*!< (@ 0x40010704) Sub-second increment register */
  __I  uint32_t  SECONDS;                   /*!< (@ 0x40010708) System time seconds register */
  __I  uint32_t  NANOSECONDS;               /*!< (@ 0x4001070C) System time nanoseconds register */
  __IO uint32_t  SECONDSUPDATE;             /*!< (@ 0x40010710) System time seconds update register */
  __IO uint32_t  NANOSECONDSUPDATE;         /*!< (@ 0x40010714) System time nanoseconds update register */
  __IO uint32_t  ADDEND;                    /*!< (@ 0x40010718) Time stamp addend register */
  __IO uint32_t  TARGETSECONDS;             /*!< (@ 0x4001071C) Target time seconds register */
  __IO uint32_t  TARGETNANOSECONDS;         /*!< (@ 0x40010720) Target time nanoseconds register */
  __IO uint32_t  HIGHWORD;                  /*!< (@ 0x40010724) System time higher word seconds register */
  __I  uint32_t  TIMESTAMPSTAT;             /*!< (@ 0x40010728) Time stamp status register */
  __IO uint32_t  PPSCTRL;                   /*!< (@ 0x4001072C) PPS control register   */
  __I  uint32_t  AUXNANOSECONDS;            /*!< (@ 0x40010730) Auxiliary time stamp nanoseconds register */
  __I  uint32_t  AUXSECONDS;                /*!< (@ 0x40010734) Auxiliary time stamp seconds register */
  __I  uint32_t  RESERVED3[562];
  __IO uint32_t  DMA_BUS_MODE;              /*!< (@ 0x40011000) Bus Mode Register      */
  __IO uint32_t  DMA_TRANS_POLL_DEMAND;     /*!< (@ 0x40011004) Transmit poll demand register */
  __IO uint32_t  DMA_REC_POLL_DEMAND;       /*!< (@ 0x40011008) Receive poll demand register */
  __IO uint32_t  DMA_REC_DES_ADDR;          /*!< (@ 0x4001100C) Receive descriptor list address register */
  __IO uint32_t  DMA_TRANS_DES_ADDR;        /*!< (@ 0x40011010) Transmit descriptor list address register */
  __IO uint32_t  DMA_STAT;                  /*!< (@ 0x40011014) Status register        */
  __IO uint32_t  DMA_OP_MODE;               /*!< (@ 0x40011018) Operation mode register */
  __IO uint32_t  DMA_INT_EN;                /*!< (@ 0x4001101C) Interrupt enable register */
  __I  uint32_t  DMA_MFRM_BUFOF;            /*!< (@ 0x40011020) Missed frame and buffer overflow register */
  __IO uint32_t  DMA_REC_INT_WDT;           /*!< (@ 0x40011024) Receive interrupt watchdog timer register */
  __I  uint32_t  RESERVED4[8];
  __I  uint32_t  DMA_CURHOST_TRANS_DES;     /*!< (@ 0x40011048) Current host transmit descriptor register */
  __I  uint32_t  DMA_CURHOST_REC_DES;       /*!< (@ 0x4001104C) Current host receive descriptor register */
  __I  uint32_t  DMA_CURHOST_TRANS_BUF;     /*!< (@ 0x40011050) Current host transmit buffer address register */
  __I  uint32_t  DMA_CURHOST_REC_BUF;       /*!< (@ 0x40011054) Current host receive buffer address register */
} LPC_ETHERNET_Type;


// ------------------------------------------------------------------------------------------------
// -----                                        ATIMER                                        -----
// ------------------------------------------------------------------------------------------------


/**
  * @brief Product name title=UM10430 Chapter title=LPC18xx Alarm timer Modification date=1/7/2011 Major revision=0 Minor revision=6  (ATIMER)
  */

typedef struct {                            /*!< (@ 0x40040000) ATIMER Structure       */
  __IO uint32_t  DOWNCOUNTER;               /*!< (@ 0x40040000) Downcounter register   */
  __IO uint32_t  PRESET;                    /*!< (@ 0x40040004) Preset value register  */
  __I  uint32_t  RESERVED0[1012];
  __O  uint32_t  CLR_EN;                    /*!< (@ 0x40040FD8) Interrupt clear enable register */
  __O  uint32_t  SET_EN;                    /*!< (@ 0x40040FDC) Interrupt set enable register */
  __I  uint32_t  STATUS;                    /*!< (@ 0x40040FE0) Status register        */
  __I  uint32_t  ENABLE;                    /*!< (@ 0x40040FE4) Enable register        */
  __O  uint32_t  CLR_STAT;                  /*!< (@ 0x40040FE8) Clear register         */
  __O  uint32_t  SET_STAT;                  /*!< (@ 0x40040FEC) Set register           */
} LPC_ATIMER_Type;


// ------------------------------------------------------------------------------------------------
// -----                                        REGFILE                                       -----
// ------------------------------------------------------------------------------------------------


/**
  * @brief Product name title=UM10430 Chapter title=LPC18xx rtc/REGFILE date=1/20/2011 Major revision=0 Minor revision=7  (REGFILE)
  */

typedef struct {                            /*!< (@ 0x40041000) REGFILE Structure      */
  __IO uint32_t REGFILE[64];                /*!< (@ 0x40041000) General purpose storage register */
} LPC_REGFILE_Type;


// ------------------------------------------------------------------------------------------------
// -----                                          PMC                                         -----
// ------------------------------------------------------------------------------------------------


/**
  * @brief Product name title=UM10430 Chapter title=LPC18xx Power Management Controller (PMC) Modification date=1/20/2011 Major revision=0 Minor revision=7  (PMC)
  */

typedef struct {                            /*!< (@ 0x40042000) PMC Structure          */
  __IO uint32_t  PD0_SLEEP0_HW_ENA;         /*!< (@ 0x40042000) Hardware sleep event enable register */
  __I  uint32_t  RESERVED0[6];
  __IO uint32_t  PD0_SLEEP0_MODE;           /*!< (@ 0x4004201C) Sleep power mode register */
} LPC_PMC_Type;


// ------------------------------------------------------------------------------------------------
// -----                                         CREG                                         -----
// ------------------------------------------------------------------------------------------------


/**
  * @brief Product name title=UM10503 Chapter title=LPC43xx Configuration Registers (CREG) Modification date=10/7/2011 Major revision=0 Minor revision=3  (CREG)
  */

typedef struct {                            /*!< (@ 0x40043000) CREG Structure         */
  __I  uint32_t  IRCTRM;                    /*!< (@ 0x40043000) IRC trim register      */
  __IO uint32_t  CREG0;                     /*!< (@ 0x40043004) Chip configuration register 32 kHz oscillator output and BOD control register. */
  __I  uint32_t  RESERVED1[62];
  __IO uint32_t  M4MEMMAP;                  /*!< (@ 0x40043100) ARM Cortex-M4 memory mapping */
  __I  uint32_t  RESERVED2[5];
  __IO uint32_t  CREG5;                     /*!< (@ 0x40043118) Chip configuration register 5. Controls JTAG access. */
  __IO uint32_t  DMAMUX;                    /*!< (@ 0x4004311C) DMA muxing control     */
  __I  uint32_t  RESERVED3[2];
  __IO uint32_t  ETBCFG;                    /*!< (@ 0x40043128) ETB RAM configuration  */
  __IO uint32_t  CREG6;                     /*!< (@ 0x4004312C) Chip configuration register 6. */
  __IO uint32_t  M4TXEVENT;                 /*!< (@ 0x40043130) Cortex-M4 TXEV event clear */
  __I  uint32_t  RESERVED4[51];
  __I  uint32_t  CHIPID;                    /*!< (@ 0x40043200) Part ID                */
  __I  uint32_t  RESERVED5[127];
  __IO uint32_t  M0TXEVENT;                 /*!< (@ 0x40043400) Cortex-M0 TXEV event clear */
  __IO uint32_t  M0APPMEMMAP;               /*!< (@ 0x40043404) ARM Cortex-M0 memory mapping */
} LPC_CREG_Type;


// ------------------------------------------------------------------------------------------------
// -----                                      EVENTROUTER                                     -----
// ------------------------------------------------------------------------------------------------


/**
  * @brief Product name title=UM10503 Chapter title=LPC43xx Event router Modification date=10/7/2011 Major revision=0 Minor revision=3  (EVENTROUTER)
  */

typedef struct {                            /*!< (@ 0x40044000) EVENTROUTER Structure  */
  __IO uint32_t  HILO;                      /*!< (@ 0x40044000) Level configuration register */
  __IO uint32_t  EDGE;                      /*!< (@ 0x40044004) Edge configuration     */
  __I  uint32_t  RESERVED0[1012];
  __O  uint32_t  CLR_EN;                    /*!< (@ 0x40044FD8) Clear event enable register */
  __O  uint32_t  SET_EN;                    /*!< (@ 0x40044FDC) Set event enable register */
  __I  uint32_t  STATUS;                    /*!< (@ 0x40044FE0) Event Status register  */
  __I  uint32_t  ENABLE;                    /*!< (@ 0x40044FE4) Event Enable register  */
  __O  uint32_t  CLR_STAT;                  /*!< (@ 0x40044FE8) Clear event status register */
  __O  uint32_t  SET_STAT;                  /*!< (@ 0x40044FEC) Set event status register */
} LPC_EVENTROUTER_Type;


// ------------------------------------------------------------------------------------------------
// -----                                          RTC                                         -----
// ------------------------------------------------------------------------------------------------


/**
  * @brief Product name title=UM10430 Chapter title=LPC18xx Real-Time Clock (RTC) Modification date=1/20/2011 Major revision=0 Minor revision=7  (RTC)
  */

typedef struct {                            /*!< (@ 0x40046000) RTC Structure          */
  __O  uint32_t  ILR;                       /*!< (@ 0x40046000) Interrupt Location Register */
  __I  uint32_t  RESERVED0;
  __IO uint32_t  CCR;                       /*!< (@ 0x40046008) Clock Control Register */
  __IO uint32_t  CIIR;                      /*!< (@ 0x4004600C) Counter Increment Interrupt Register */
  __IO uint32_t  AMR;                       /*!< (@ 0x40046010) Alarm Mask Register    */
  __I  uint32_t  CTIME0;                    /*!< (@ 0x40046014) Consolidated Time Register 0 */
  __I  uint32_t  CTIME1;                    /*!< (@ 0x40046018) Consolidated Time Register 1 */
  __I  uint32_t  CTIME2;                    /*!< (@ 0x4004601C) Consolidated Time Register 2 */
  __IO uint32_t  SEC;                       /*!< (@ 0x40046020) Seconds Register       */
  __IO uint32_t  MIN;                       /*!< (@ 0x40046024) Minutes Register       */
  __IO uint32_t  HRS;                       /*!< (@ 0x40046028) Hours Register         */
  __IO uint32_t  DOM;                       /*!< (@ 0x4004602C) Day of Month Register  */
  __IO uint32_t  DOW;                       /*!< (@ 0x40046030) Day of Week Register   */
  __IO uint32_t  DOY;                       /*!< (@ 0x40046034) Day of Year Register   */
  __IO uint32_t  MONTH;                     /*!< (@ 0x40046038) Months Register        */
  __IO uint32_t  YEAR;                      /*!< (@ 0x4004603C) Years Register         */
  __IO uint32_t  CALIBRATION;               /*!< (@ 0x40046040) Calibration Value Register */
  __I  uint32_t  RESERVED1[7];
  __IO uint32_t  ASEC;                      /*!< (@ 0x40046060) Alarm value for Seconds */
  __IO uint32_t  AMIN;                      /*!< (@ 0x40046064) Alarm value for Minutes */
  __IO uint32_t  AHRS;                      /*!< (@ 0x40046068) Alarm value for Hours  */
  __IO uint32_t  ADOM;                      /*!< (@ 0x4004606C) Alarm value for Day of Month */
  __IO uint32_t  ADOW;                      /*!< (@ 0x40046070) Alarm value for Day of Week */
  __IO uint32_t  ADOY;                      /*!< (@ 0x40046074) Alarm value for Day of Year */
  __IO uint32_t  AMON;                      /*!< (@ 0x40046078) Alarm value for Months */
  __IO uint32_t  AYRS;                      /*!< (@ 0x4004607C) Alarm value for Year   */
} LPC_RTC_Type;


// ------------------------------------------------------------------------------------------------
// -----                                          CGU                                         -----
// ------------------------------------------------------------------------------------------------


/**
  * @brief Product name title=UM10462 Chapter title=LPC18xx Clock Generation Unit (CGU) Modification date=6/1/2011 Major revision=0 Minor revision=1  (CGU)
  */

typedef struct {                            /*!< (@ 0x40050000) CGU Structure          */
  __I  uint32_t  RESERVED0[5];
  __IO uint32_t  FREQ_MON;                  /*!< (@ 0x40050014) Frequency monitor register */
  __IO uint32_t  XTAL_OSC_CTRL;             /*!< (@ 0x40050018) Crystal oscillator control register */
  __I  uint32_t  PLL0USB_STAT;              /*!< (@ 0x4005001C) PLL0 (USB) status register */
  __IO uint32_t  PLL0USB_CTRL;              /*!< (@ 0x40050020) PLL0 (USB) control register */
  __IO uint32_t  PLL0USB_MDIV;              /*!< (@ 0x40050024) PLL0 (USB) M-divider register */
  __IO uint32_t  PLL0USB_NP_DIV;            /*!< (@ 0x40050028) PLL0 (USB) N/P-divider register */
  __I  uint32_t  PLL0AUDIO_STAT;            /*!< (@ 0x4005002C) PLL0 (audio) status register */
  __IO uint32_t  PLL0AUDIO_CTRL;            /*!< (@ 0x40050030) PLL0 (audio) control register */
  __IO uint32_t  PLL0AUDIO_MDIV;            /*!< (@ 0x40050034) PLL0 (audio) M-divider register */
  __IO uint32_t  PLL0AUDIO_NP_DIV;          /*!< (@ 0x40050038) PLL0 (audio) N/P-divider register */
  __IO uint32_t  PLL0AUDIO_FRAC;            /*!< (@ 0x4005003C) PLL0 (audio)           */
  __I  uint32_t  PLL1_STAT;                 /*!< (@ 0x40050040) PLL1 status register   */
  __IO uint32_t  PLL1_CTRL;                 /*!< (@ 0x40050044) PLL1 control register  */
  __IO uint32_t  IDIVA_CTRL;                /*!< (@ 0x40050048) Integer divider A control register */
  __IO uint32_t  IDIVB_CTRL;                /*!< (@ 0x4005004C) Integer divider B control register */
  __IO uint32_t  IDIVC_CTRL;                /*!< (@ 0x40050050) Integer divider C control register */
  __IO uint32_t  IDIVD_CTRL;                /*!< (@ 0x40050054) Integer divider D control register */
  __IO uint32_t  IDIVE_CTRL;                /*!< (@ 0x40050058) Integer divider E control register */
  __IO uint32_t  BASE_SAFE_CLK;             /*!< (@ 0x4005005C) Output stage 0 control register for base clock BASE_SAFE_CLK */
  __IO uint32_t  BASE_USB0_CLK;             /*!< (@ 0x40050060) Output stage 1 control register for base clock BASE_USB0_CLK */
  __IO uint32_t  BASE_PERIPH_CLK;           /*!< (@ 0x40050064) Output stage 2 control register for base clock BASE_PERIPH_CLK */
  __IO uint32_t  BASE_USB1_CLK;             /*!< (@ 0x40050068) Output stage 3 control register for base clock BASE_USB1_CLK */
  __IO uint32_t  BASE_M4_CLK;               /*!< (@ 0x4005006C) Output stage BASE_M4_CLK control register */
  __IO uint32_t  BASE_SPIFI_CLK;            /*!< (@ 0x40050070) Output stage BASE_SPIFI_CLK control register */
  __IO uint32_t  BASE_SPI_CLK;              /*!< (@ 0x40050074) Output stage BASE_SPI_CLK control register */
  __IO uint32_t  BASE_PHY_RX_CLK;           /*!< (@ 0x40050078) Output stage BASE_PHY_RX_CLK control register */
  __IO uint32_t  BASE_PHY_TX_CLK;           /*!< (@ 0x4005007C) Output stage BASE_PHY_TX_CLK control register */
  __IO uint32_t  BASE_APB1_CLK;             /*!< (@ 0x40050080) Output stage BASE_APB1_CLK control register */
  __IO uint32_t  BASE_APB3_CLK;             /*!< (@ 0x40050084) Output stage BASE_APB3_CLK control register */
  __IO uint32_t  BASE_LCD_CLK;              /*!< (@ 0x40050088) Output stage BASE_LCD_CLK control register */
  __I  uint32_t  RESERVED2;
  __IO uint32_t  BASE_SDIO_CLK;             /*!< (@ 0x40050090) Output stage BASE_SDIO_CLK control register */
  __IO uint32_t  BASE_SSP0_CLK;             /*!< (@ 0x40050094) Output stage BASE_SSP0_CLK control register */
  __IO uint32_t  BASE_SSP1_CLK;             /*!< (@ 0x40050098) Output stage BASE_SSP1_CLK control register */
  __IO uint32_t  BASE_UART0_CLK;            /*!< (@ 0x4005009C) Output stage BASE_UART0_CLK control register */
  __IO uint32_t  BASE_UART1_CLK;            /*!< (@ 0x400500A0) Output stage BASE_UART1_CLK control register */
  __IO uint32_t  BASE_UART2_CLK;            /*!< (@ 0x400500A4) Output stage BASE_UART2_CLK control register */
  __IO uint32_t  BASE_UART3_CLK;            /*!< (@ 0x400500A8) Output stage BASE_UART3_CLK control register */
  __IO uint32_t  BASE_OUT_CLK;              /*!< (@ 0x400500AC) Output stage 20 control register for base clock BASE_OUT_CLK */
  __I  uint32_t  RESERVED3[4];
  __IO uint32_t  BASE_APLL_CLK;             /*!< (@ 0x400500C0) Output stage 25 control register for base clock BASE_APLL_CLK */
  __IO uint32_t  BASE_CGU_OUT0_CLK;         /*!< (@ 0x400500C4) Output stage 25 control register for base clock BASE_CGU_OUT0_CLK */
  __IO uint32_t  BASE_CGU_OUT1_CLK;         /*!< (@ 0x400500C8) Output stage 25 control register for base clock BASE_CGU_OUT1_CLK */
} LPC_CGU_Type;


// ------------------------------------------------------------------------------------------------
// -----                                         CCU1                                         -----
// ------------------------------------------------------------------------------------------------


/**
  * @brief Product name title=UM10430 Chapter title=LPC43xx Clock Control Unit (CCU) (CCU1)
  */

typedef struct {                            /*!< (@ 0x40051000) CCU1 Structure         */
  __IO uint32_t  PM;                        /*!< (@ 0x40051000) CCU1 power mode register */
  __I  uint32_t  BASE_STAT;                 /*!< (@ 0x40051004) CCU1 base clocks status register */
  __I  uint32_t  RESERVED0[62];
  __IO uint32_t  CLK_APB3_BUS_CFG;          /*!< (@ 0x40051100) CLK_APB3_BUS clock configuration register */
  __I  uint32_t  CLK_APB3_BUS_STAT;         /*!< (@ 0x40051104) CLK_APB3_BUS clock status register */
  __IO uint32_t  CLK_APB3_I2C1_CFG;         /*!< (@ 0x40051108) CLK_APB3_I2C1 clock configuration register */
  __I  uint32_t  CLK_APB3_I2C1_STAT;        /*!< (@ 0x4005110C) CLK_APB3_I2C1 clock status register */
  __IO uint32_t  CLK_APB3_DAC_CFG;          /*!< (@ 0x40051110) CLK_APB3_DAC clock configuration register */
  __I  uint32_t  CLK_APB3_DAC_STAT;         /*!< (@ 0x40051114) CLK_APB3_DAC clock status register */
  __IO uint32_t  CLK_APB3_ADC0_CFG;         /*!< (@ 0x40051118) CLK_APB3_ADC0 clock configuration register */
  __I  uint32_t  CLK_APB3_ADC0_STAT;        /*!< (@ 0x4005111C) CLK_APB3_ADC0 clock status register */
  __IO uint32_t  CLK_APB3_ADC1_CFG;         /*!< (@ 0x40051120) CLK_APB3_ADC1 clock configuration register */
  __I  uint32_t  CLK_APB3_ADC1_STAT;        /*!< (@ 0x40051124) CLK_APB3_ADC1 clock status register */
  __IO uint32_t  CLK_APB3_CAN0_CFG;         /*!< (@ 0x40051128) CLK_APB3_CAN0 clock configuration register */
  __I  uint32_t  CLK_APB3_CAN0_STAT;        /*!< (@ 0x4005112C) CLK_APB3_CAN0 clock status register */
  __I  uint32_t  RESERVED1[52];
  __IO uint32_t  CLK_APB1_BUS_CFG;          /*!< (@ 0x40051200) CLK_APB1_BUS clock configuration register */
  __I  uint32_t  CLK_APB1_BUS_STAT;         /*!< (@ 0x40051204) CLK_APB1_BUS clock status register */
  __IO uint32_t  CLK_APB1_MOTOCONPWM_CFG;   /*!< (@ 0x40051208) CLK_APB1_MOTOCONPWM clock configuration register */
  __I  uint32_t  CLK_APB1_MOTOCONPWM_STAT;  /*!< (@ 0x4005120C) CLK_APB1_MOTOCONPWM clock status register */
  __IO uint32_t  CLK_ABP1_I2C0_CFG;         /*!< (@ 0x40051210) CLK_ABP1_I2C0 clock configuration register */
  __I  uint32_t  CLK_APB1_I2C0_STAT;        /*!< (@ 0x40051214) CLK_APB1_I2C0 clock status register */
  __IO uint32_t  CLK_APB1_I2S_CFG;          /*!< (@ 0x40051218) CLK_APB1_I2S clock configuration register */
  __I  uint32_t  CLK_APB1_I2S_STAT;         /*!< (@ 0x4005121C) CLK_APB1_I2S clock status register */
  __IO uint32_t  CLK_APB1_CAN1_CFG;         /*!< (@ 0x40051220) CLK_APB1_CAN1 clock configuration register */
  __I  uint32_t  CLK_APB1_CAN1_STAT;        /*!< (@ 0x40051224) CLK_APB1_CAN1 clock status register */
  __I  uint32_t  RESERVED2[54];
  __IO uint32_t  CLK_SPIFI_CFG;             /*!< (@ 0x40051300) CLK_SPIFI clock configuration register */
  __I  uint32_t  CLK_SPIFI_STAT;            /*!< (@ 0x40051304) CLK_APB1_SPIFI clock status register */
  __I  uint32_t  RESERVED3[62];
  __IO uint32_t  CLK_M4_BUS_CFG;            /*!< (@ 0x40051400) CLK_M4_BUS clock configuration register */
  __I  uint32_t  CLK_M4_BUS_STAT;           /*!< (@ 0x40051404) CLK_M4_BUSclock status register */
  __IO uint32_t  CLK_M4_SPIFI_CFG;          /*!< (@ 0x40051408) CLK_M4_SPIFI clock configuration register */
  __I  uint32_t  CLK_M4_SPIFI_STAT;         /*!< (@ 0x4005140C) CLK_M4_SPIFI clock status register */
  __IO uint32_t  CLK_M4_GPIO_CFG;           /*!< (@ 0x40051410) CLK_M4_GPIO clock configuration register */
  __I  uint32_t  CLK_M4_GPIO_STAT;          /*!< (@ 0x40051414) CLK_M4_GPIO clock status register */
  __IO uint32_t  CLK_M4_LCD_CFG;            /*!< (@ 0x40051418) CLK_M4_LCD clock configuration register */
  __I  uint32_t  CLK_M4_LCD_STAT;           /*!< (@ 0x4005141C) CLK_M4_LCD clock status register */
  __IO uint32_t  CLK_M4_ETHERNET_CFG;       /*!< (@ 0x40051420) CLK_M4_ETHERNET clock configuration register */
  __I  uint32_t  CLK_M4_ETHERNET_STAT;      /*!< (@ 0x40051424) CLK_M4_ETHERNET clock status register */
  __IO uint32_t  CLK_M4_USB0_CFG;           /*!< (@ 0x40051428) CLK_M4_USB0 clock configuration register */
  __I  uint32_t  CLK_M4_USB0_STAT;          /*!< (@ 0x4005142C) CLK_M4_USB0 clock status register */
  __IO uint32_t  CLK_M4_EMC_CFG;            /*!< (@ 0x40051430) CLK_M4_EMC clock configuration register */
  __I  uint32_t  CLK_M4_EMC_STAT;           /*!< (@ 0x40051434) CLK_M4_EMC clock status register */
  __IO uint32_t  CLK_M4_SDIO_CFG;           /*!< (@ 0x40051438) CLK_M4_SDIO clock configuration register */
  __I  uint32_t  CLK_M4_SDIO_STAT;          /*!< (@ 0x4005143C) CLK_M4_SDIO clock status register */
  __IO uint32_t  CLK_M4_DMA_CFG;            /*!< (@ 0x40051440) CLK_M4_DMA clock configuration register */
  __I  uint32_t  CLK_M4_DMA_STAT;           /*!< (@ 0x40051444) CLK_M4_DMA clock status register */
  __IO uint32_t  CLK_M4_M4CORE_CFG;         /*!< (@ 0x40051448) CLK_M4_M4CORE clock configuration register */
  __I  uint32_t  CLK_M4_M3CORE_STAT;        /*!< (@ 0x4005144C) CLK_M4_M3CORE clock status register */
  __I  uint32_t  RESERVED4[6];
  __IO uint32_t  CLK_M4_SCT_CFG;            /*!< (@ 0x40051468) CLK_M4_SCT clock configuration register */
  __I  uint32_t  CLK_M4_SCT_STAT;           /*!< (@ 0x4005146C) CLK_M4_SCT clock status register */
  __IO uint32_t  CLK_M4_USB1_CFG;           /*!< (@ 0x40051470) CLK_M4_USB1 clock configuration register */
  __I  uint32_t  CLK_M4_USB1_STAT;          /*!< (@ 0x40051474) CLK_M4_USB1 clock status register */
  __IO uint32_t  CLK_M4_EMCDIV_CFG;         /*!< (@ 0x40051478) CLK_M4_EMCDIV clock configuration register */
  __I  uint32_t  CLK_M4_EMCDIV_STAT;        /*!< (@ 0x4005147C) CLK_M4_EMCDIV clock status register */
  __I  uint32_t  RESERVED5[4];
  __IO uint32_t  CLK_M4_M0APP_CFG;          /*!< (@ 0x40051490) CLK_M0APP_CFG clock configuration register */
  __I  uint32_t  CLK_M4_M0APP_STAT;         /*!< (@ 0x40051494) CLK_M4_MOAPP clock status register */
  __I  uint32_t  RESERVED6[26];
  __IO uint32_t  CLK_M4_WWDT_CFG;           /*!< (@ 0x40051500) CLK_M4_WWDT clock configuration register */
  __I  uint32_t  CLK_M4_WWDT_STAT;          /*!< (@ 0x40051504) CLK_M4_WWDT clock status register */
  __IO uint32_t  CLK_M4_USART0_CFG;         /*!< (@ 0x40051508) CLK_M4_USART0 clock configuration register */
  __I  uint32_t  CLK_M4_USART0_STAT;        /*!< (@ 0x4005150C) CLK_M4_USART0 clock status register */
  __IO uint32_t  CLK_M4_UART1_CFG;          /*!< (@ 0x40051510) CLK_M4_UART1 clock configuration register */
  __I  uint32_t  CLK_M4_UART1_STAT;         /*!< (@ 0x40051514) CLK_M4_UART1 clock status register */
  __IO uint32_t  CLK_M4_SSP0_CFG;           /*!< (@ 0x40051518) CLK_M4_SSP0 clock configuration register */
  __I  uint32_t  CLK_M4_SSP0_STAT;          /*!< (@ 0x4005151C) CLK_M4_SSP0 clock status register */
  __IO uint32_t  CLK_M4_TIMER0_CFG;         /*!< (@ 0x40051520) CLK_M4_TIMER0 clock configuration register */
  __I  uint32_t  CLK_M4_TIMER0_STAT;        /*!< (@ 0x40051524) CLK_M4_TIMER0 clock status register */
  __IO uint32_t  CLK_M4_TIMER1_CFG;         /*!< (@ 0x40051528) CLK_M4_TIMER1clock configuration register */
  __I  uint32_t  CLK_M4_TIMER1_STAT;        /*!< (@ 0x4005152C) CLK_M4_TIMER1 clock status register */
  __IO uint32_t  CLK_M4_SCU_CFG;            /*!< (@ 0x40051530) CLK_M4_SCU clock configuration register */
  __I  uint32_t  CLK_M4_SCU_STAT;           /*!< (@ 0x40051534) CLK_SCU_XXX clock status register */
  __IO uint32_t  CLK_M4_CREG_CFG;           /*!< (@ 0x40051538) CLK_M4_CREGclock configuration register */
  __I  uint32_t  CLK_M4_CREG_STAT;          /*!< (@ 0x4005153C) CLK_M4_CREG clock status register */
  __I  uint32_t  RESERVED7[48];
  __IO uint32_t  CLK_M4_RITIMER_CFG;        /*!< (@ 0x40051600) CLK_M4_RITIMER clock configuration register */
  __I  uint32_t  CLK_M4_RITIMER_STAT;       /*!< (@ 0x40051604) CLK_M4_RITIMER clock status register */
  __IO uint32_t  CLK_M4_USART2_CFG;         /*!< (@ 0x40051608) CLK_M4_USART2 clock configuration register */
  __I  uint32_t  CLK_M4_USART2_STAT;        /*!< (@ 0x4005160C) CLK_M4_USART2 clock status register */
  __IO uint32_t  CLK_M4_USART3_CFG;         /*!< (@ 0x40051610) CLK_M4_USART3 clock configuration register */
  __I  uint32_t  CLK_M4_USART3_STAT;        /*!< (@ 0x40051614) CLK_M4_USART3 clock status register */
  __IO uint32_t  CLK_M4_TIMER2_CFG;         /*!< (@ 0x40051618) CLK_M4_TIMER2 clock configuration register */
  __I  uint32_t  CLK_M4_TIMER2_STAT;        /*!< (@ 0x4005161C) CLK_M4_TIMER2 clock status register */
  __IO uint32_t  CLK_M4_TIMER3_CFG;         /*!< (@ 0x40051620) CLK_M4_TIMER3 clock configuration register */
  __I  uint32_t  CLK_M4_TIMER3_STAT;        /*!< (@ 0x40051624) CLK_M4_TIMER3 clock status register */
  __IO uint32_t  CLK_M4_SSP1_CFG;           /*!< (@ 0x40051628) CLK_M4_SSP1 clock configuration register */
  __I  uint32_t  CLK_M4_SSP1_STAT;          /*!< (@ 0x4005162C) CLK_M4_SSP1 clock status register */
  __IO uint32_t  CLK_M4_QEI_CFG;            /*!< (@ 0x40051630) CLK_M4_QEIclock configuration register */
  __I  uint32_t  CLK_M4_QEI_STAT;           /*!< (@ 0x40051634) CLK_M4_QEI clock status register */
  __I  uint32_t  RESERVED8[50];
  __IO uint32_t  CLK_PERIPH_BUS_CFG;        /*!< (@ 0x40051700) CLK_PERIPH_BUS_CFG clock configuration register */
  __I  uint32_t  CLK_PERIPH_BUS_STAT;       /*!< (@ 0x40051704) CLK_PERIPH_BUS_STAT clock status register */
  __I  uint32_t  RESERVED9[2];
  __IO uint32_t  CLK_PERIPH_CORE_CFG;       /*!< (@ 0x40051710) CLK_PERIPH_CORE_CFG clock configuration register */
  __I  uint32_t  CLK_PERIPH_CORE_STAT;      /*!< (@ 0x40051714) CLK_CORE_BUS_STAT clock status register */
  __IO uint32_t  CLK_PERIPH_SGPIO_CFG;      /*!< (@ 0x40051718) CLK_PERIPH_SGPIO_CFG clock configuration register */
  __I  uint32_t  CLK_PERIPH_SGPIO_STAT;     /*!< (@ 0x4005171C) CLK_CORE_SGPIO_STAT clock status register */
  __I  uint32_t  RESERVED10[56];
  __IO uint32_t  CLK_USB0_CFG;              /*!< (@ 0x40051800) CLK_M4_USB0 clock configuration register */
  __I  uint32_t  CLK_USB0_STAT;             /*!< (@ 0x40051804) CLK_USB0 clock status register */
  __I  uint32_t  RESERVED11[62];
  __IO uint32_t  CLK_USB1_CFG;              /*!< (@ 0x40051900) CLK_USB1 clock configuration register */
  __I  uint32_t  CLK_USB1_STAT;             /*!< (@ 0x40051904) CLK_USB1 clock status register */
  __I  uint32_t  RESERVED12[62];
  __IO uint32_t  CLK_SPI_CFG;               /*!< (@ 0x40051A00) CLK_SPI clock configuration register */
  __I  uint32_t  CLK_SPI_STAT;              /*!< (@ 0x40051A04) CLK_SPI clock status register */
  __I  uint32_t  RESERVED13[62];
  __IO uint32_t  CLK_VADC_CFG;              /*!< (@ 0x40051B00) CLK_VADC clock configuration register */
  __I  uint32_t  CLK_VADC_STAT;             /*!< (@ 0x40051B04) CLK_VADC clock status register */
} LPC_CCU1_Type;


// ------------------------------------------------------------------------------------------------
// -----                                         CCU2                                         -----
// ------------------------------------------------------------------------------------------------


/**
  * @brief Product name title=UM10430 Chapter title=LPC18xx Clock Control Unit (CCU) Modification date=1/21/2011 Major revision=0 Minor revision=7  (CCU2)
  */

typedef struct {                            /*!< (@ 0x40052000) CCU2 Structure         */
  __IO uint32_t  PM;                        /*!< (@ 0x40052000) Power mode register    */
  __I  uint32_t  BASE_STAT;                 /*!< (@ 0x40052004) CCU base clocks status register */
  __I  uint32_t  RESERVED0[62];
  __IO uint32_t  CLK_APLL_CFG;              /*!< (@ 0x40052100) CLK_APLL clock configuration register */
  __I  uint32_t  CLK_APLL_STAT;             /*!< (@ 0x40052104) CLK_APLL clock status register */
  __I  uint32_t  RESERVED1[62];
  __IO uint32_t  CLK_APB2_USART3_CFG;       /*!< (@ 0x40052200) CLK_APB2_USART3 clock configuration register */
  __I  uint32_t  CLK_APB2_USART3_STAT;      /*!< (@ 0x40052204) CLK_APB2_USART3 clock status register */
  __I  uint32_t  RESERVED2[62];
  __IO uint32_t  CLK_APB2_USART2_CFG;       /*!< (@ 0x40052300) CLK_APB2_USART2 clock configuration register */
  __I  uint32_t  CLK_APB2_USART2_STAT;      /*!< (@ 0x40052304) CLK_APB2_USART clock status register */
  __I  uint32_t  RESERVED3[62];
  __IO uint32_t  CLK_APB0_UART1_CFG;        /*!< (@ 0x40052400) CLK_APB2_UART1 clock configuration register */
  __I  uint32_t  CLK_APB0_UART1_STAT;       /*!< (@ 0x40052404) CLK_APB0_UART1 clock status register */
  __I  uint32_t  RESERVED4[62];
  __IO uint32_t  CLK_APB0_USART0_CFG;       /*!< (@ 0x40052500) CLK_APB2_USART0 clock configuration register */
  __I  uint32_t  CLK_APB0_USART0_STAT;      /*!< (@ 0x40052504) CLK_APB0_USART0 clock status register */
  __I  uint32_t  RESERVED5[62];
  __IO uint32_t  CLK_APB2_SSP1_CFG;         /*!< (@ 0x40052600) CLK_APB2_SSP1 clock configuration register */
  __I  uint32_t  CLK_APB2_SSP1_STAT;        /*!< (@ 0x40052604) CLK_APB2_SSP1 clock status register */
  __I  uint32_t  RESERVED6[62];
  __IO uint32_t  CLK_APB0_SSP0_CFG;         /*!< (@ 0x40052700) CLK_APB0_SSP0 clock configuration register */
  __I  uint32_t  CLK_APB0_SSP0_STAT;        /*!< (@ 0x40052704) CLK_APB0_SSP0 clock status register */
  __I  uint32_t  RESERVED7[62];
  __IO uint32_t  CLK_SDIO_CFG;              /*!< (@ 0x40052800) CLK_SDIO clock configuration register */
  __I  uint32_t  CLK_SDIO_STAT;             /*!< (@ 0x40052804) CLK_SDIO clock status register */
} LPC_CCU2_Type;


// ------------------------------------------------------------------------------------------------
// -----                                          RGU                                         -----
// ------------------------------------------------------------------------------------------------


/**
  * @brief Product name title=UM10503 Chapter title=LPC43xx Reset GenerationUnit (RGU) Modification date=7/20/2011 Major revision=0 Minor revision=13  (RGU)
  */

typedef struct {                            /*!< (@ 0x40053000) RGU Structure          */
  __I  uint32_t  RESERVED0[64];
  __O  uint32_t  RESET_CTRL0;               /*!< (@ 0x40053100) Reset control register 0 */
  __O  uint32_t  RESET_CTRL1;               /*!< (@ 0x40053104) Reset control register 1 */
  __I  uint32_t  RESERVED1[2];
  __IO uint32_t  RESET_STATUS0;             /*!< (@ 0x40053110) Reset status register 0 */
  __IO uint32_t  RESET_STATUS1;             /*!< (@ 0x40053114) Reset status register 1 */
  __IO uint32_t  RESET_STATUS2;             /*!< (@ 0x40053118) Reset status register 2 */
  __IO uint32_t  RESET_STATUS3;             /*!< (@ 0x4005311C) Reset status register 3 */
  __I  uint32_t  RESERVED2[12];
  __I  uint32_t  RESET_ACTIVE_STATUS0;      /*!< (@ 0x40053150) Reset active status register 0 */
  __I  uint32_t  RESET_ACTIVE_STATUS1;      /*!< (@ 0x40053154) Reset active status register 1 */
  __I  uint32_t  RESERVED3[170];
  __IO uint32_t  RESET_EXT_STAT0;           /*!< (@ 0x40053400) Reset external status register 0 for CORE_RST */
  __IO uint32_t  RESET_EXT_STAT1;           /*!< (@ 0x40053404) Reset external status register 1 for PERIPH_RST */
  __IO uint32_t  RESET_EXT_STAT2;           /*!< (@ 0x40053408) Reset external status register 2 for MASTER_RST */
  __I  uint32_t  RESERVED4;
  __IO uint32_t  RESET_EXT_STAT4;           /*!< (@ 0x40053410) Reset external status register 4 for WWDT_RST */
  __IO uint32_t  RESET_EXT_STAT5;           /*!< (@ 0x40053414) Reset external status register 5 for CREG_RST */
  __I  uint32_t  RESERVED5[2];
  __IO uint32_t  RESET_EXT_STAT8;           /*!< (@ 0x40053420) Reset external status register */
  __IO uint32_t  RESET_EXT_STAT9;           /*!< (@ 0x40053424) Reset external status register */
  __I  uint32_t  RESERVED6[3];
  __IO uint32_t  RESET_EXT_STAT13;          /*!< (@ 0x40053434) Reset external status register */
  __I  uint32_t  RESERVED7[2];
  __IO uint32_t  RESET_EXT_STAT16;          /*!< (@ 0x40053440) Reset external status register */
  __IO uint32_t  RESET_EXT_STAT17;          /*!< (@ 0x40053444) Reset external status register */
  __IO uint32_t  RESET_EXT_STAT18;          /*!< (@ 0x40053448) Reset external status register */
  __IO uint32_t  RESET_EXT_STAT19;          /*!< (@ 0x4005344C) Reset external status register */
  __IO uint32_t  RESET_EXT_STAT20;          /*!< (@ 0x40053450) Reset external status register */
  __IO uint32_t  RESET_EXT_STAT21;          /*!< (@ 0x40053454) Reset external status register */
  __IO uint32_t  RESET_EXT_STAT22;          /*!< (@ 0x40053458) Reset external status register */
  __IO uint32_t  RESET_EXT_STAT23;          /*!< (@ 0x4005345C) Reset external status register */
  __I  uint32_t  RESERVED8[4];
  __IO uint32_t  RESET_EXT_STAT28;          /*!< (@ 0x40053470) Reset external status register */
  __I  uint32_t  RESERVED9[3];
  __IO uint32_t  RESET_EXT_STAT32;          /*!< (@ 0x40053480) Reset external status register */
  __IO uint32_t  RESET_EXT_STAT33;          /*!< (@ 0x40053484) Reset external status register */
  __IO uint32_t  RESET_EXT_STAT34;          /*!< (@ 0x40053488) Reset external status register */
  __IO uint32_t  RESET_EXT_STAT35;          /*!< (@ 0x4005348C) Reset external status register */
  __IO uint32_t  RESET_EXT_STAT36;          /*!< (@ 0x40053490) Reset external status register */
  __IO uint32_t  RESET_EXT_STAT37;          /*!< (@ 0x40053494) Reset external status register */
  __IO uint32_t  RESET_EXT_STAT38;          /*!< (@ 0x40053498) Reset external status register */
  __IO uint32_t  RESET_EXT_STAT39;          /*!< (@ 0x4005349C) Reset external status register */
  __IO uint32_t  RESET_EXT_STAT40;          /*!< (@ 0x400534A0) Reset external status register */
  __IO uint32_t  RESET_EXT_STAT41;          /*!< (@ 0x400534A4) Reset external status register */
  __IO uint32_t  RESET_EXT_STAT42;          /*!< (@ 0x400534A8) Reset external status register */
  __I  uint32_t  RESERVED10;
  __IO uint32_t  RESET_EXT_STAT44;          /*!< (@ 0x400534B0) Reset external status register */
  __IO uint32_t  RESET_EXT_STAT45;          /*!< (@ 0x400534B4) Reset external status register */
  __IO uint32_t  RESET_EXT_STAT46;          /*!< (@ 0x400534B8) Reset external status register */
  __IO uint32_t  RESET_EXT_STAT47;          /*!< (@ 0x400534BC) Reset external status register */
  __IO uint32_t  RESET_EXT_STAT48;          /*!< (@ 0x400534C0) Reset external status register */
  __IO uint32_t  RESET_EXT_STAT49;          /*!< (@ 0x400534C4) Reset external status register */
  __IO uint32_t  RESET_EXT_STAT50;          /*!< (@ 0x400534C8) Reset external status register */
  __IO uint32_t  RESET_EXT_STAT51;          /*!< (@ 0x400534CC) Reset external status register */
  __IO uint32_t  RESET_EXT_STAT52;          /*!< (@ 0x400534D0) Reset external status register */
  __IO uint32_t  RESET_EXT_STAT53;          /*!< (@ 0x400534D4) Reset external status register */
  __IO uint32_t  RESET_EXT_STAT54;          /*!< (@ 0x400534D8) Reset external status register */
  __IO uint32_t  RESET_EXT_STAT55;          /*!< (@ 0x400534DC) Reset external status register */
} LPC_RGU_Type;


// ------------------------------------------------------------------------------------------------
// -----                                         WWDT                                         -----
// ------------------------------------------------------------------------------------------------


/**
  * @brief Product name title=UM10430 Chapter title=LPC18xx Windowed Watchdog timer (WWDT) Modification date=1/14/2011 Major revision=0 Minor revision=7  (WWDT)
  */

typedef struct {                            /*!< (@ 0x40080000) WWDT Structure         */
  __IO uint32_t  MOD;                       /*!< (@ 0x40080000) Watchdog mode register. This register contains the basic mode and status of the Watchdog Timer. */
  __IO uint32_t  TC;                        /*!< (@ 0x40080004) Watchdog timer constant register. This register determines the time-out value. */
  __O  uint32_t  FEED;                      /*!< (@ 0x40080008) Watchdog feed sequence register. Writing 0xAA followed by 0x55 to this register reloads the Watchdog timer with the value contained in WDTC. */
  __I  uint32_t  TV;                        /*!< (@ 0x4008000C) Watchdog timer value register. This register reads out the current value of the Watchdog timer. */
  __I  uint32_t  RESERVED0;
  __IO uint32_t  WARNINT;                   /*!< (@ 0x40080014) Watchdog warning interrupt register. This register contains the Watchdog warning interrupt compare value. */
  __IO uint32_t  WINDOW;                    /*!< (@ 0x40080018) Watchdog timer window register. This register contains the Watchdog window value. */
} LPC_WWDT_Type;


// ------------------------------------------------------------------------------------------------
// -----                                        USARTn                                        -----
// ------------------------------------------------------------------------------------------------


/**
  * @brief Product name title=UM10430 Chapter title=LPC18xx USART0_2_3 Modification date=1/14/2011 Major revision=0 Minor revision=7  (USARTn)
  */

typedef struct {                            /*!< (@ 0x400xx000) USARTn Structure       */
  
  union {
    __IO uint32_t  DLL;                     /*!< (@ 0x400xx000) Divisor Latch LSB. Least significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider (DLAB = 1). */
    __O  uint32_t  THR;                     /*!< (@ 0x400xx000) Transmit Holding Register. The next character to be transmitted is written here (DLAB = 0). */
    __I  uint32_t  RBR;                     /*!< (@ 0x400xx000) Receiver Buffer Register. Contains the next received character to be read (DLAB = 0). */
  } ;
  
  union {
    __IO uint32_t IER;                      /*!< (@ 0x400xx004) Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential UART interrupts (DLAB = 0). */
    __IO uint32_t DLM;                      /*!< (@ 0x400xx004) Divisor Latch MSB. Most significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider (DLAB = 1). */
  } ;
  
  union {
    __O  uint32_t FCR;                      /*!< (@ 0x400xx008) FIFO Control Register. Controls UART FIFO usage and modes. */
    __I  uint32_t IIR;                      /*!< (@ 0x400xx008) Interrupt ID Register. Identifies which interrupt(s) are pending. */
  } ;
  __IO uint32_t LCR;                        /*!< (@ 0x400xx00C) Line Control Register. Contains controls for frame formatting and break generation. */
  __I  uint32_t RESERVED0[1];
  __I  uint32_t LSR;                        /*!< (@ 0x400xx014) Line Status Register. Contains flags for transmit and receive status, including line errors. */
  __I  uint32_t RESERVED1[1];
  __IO uint32_t SCR;                        /*!< (@ 0x400xx01C) Scratch Pad Register. Eight-bit temporary storage for software. */
  __IO uint32_t ACR;                        /*!< (@ 0x400xx020) Auto-baud Control Register. Contains controls for the auto-baud feature. */
  __IO uint32_t ICR;                        /*!< (@ 0x400xx024) IrDA control register (UART3 only) */
  __IO uint32_t FDR;                        /*!< (@ 0x400xx028) Fractional Divider Register. Generates a clock input for the baud rate divider. */
  __IO uint32_t OSR;                        /*!< (@ 0x400xx02C) Oversampling Register. Controls the degree of oversampling during each bit time. */
  __I  uint32_t  RESERVED2[4];
  __IO uint32_t HDEN;                       /*!< (@ 0x400xx03C) Half-duplex enable Register */
  __I  uint32_t RESERVED3[1];
  __IO uint32_t SCICTRL;                    /*!< (@ 0x400xx048) Smart card interface control register */
  __IO uint32_t RS485CTRL;                  /*!< (@ 0x400xx04C) RS-485/EIA-485 Control. Contains controls to configure various aspects of RS-485/EIA-485 modes. */
  __IO uint32_t RS485ADRMATCH;              /*!< (@ 0x400xx050) RS-485/EIA-485 address match. Contains the address match value for RS-485/EIA-485 mode. */
  __IO uint32_t RS485DLY;                   /*!< (@ 0x400xx054) RS-485/EIA-485 direction control delay. */
  __IO uint32_t SYNCCTRL;                   /*!< (@ 0x400xx058) Synchronous mode control register. */
  __IO uint32_t TER;                        /*!< (@ 0x400xx05C) Transmit Enable Register. Turns off UART transmitter for use with software flow control. */
} LPC_USARTn_Type;


// ------------------------------------------------------------------------------------------------
// -----                                         UART1                                        -----
// ------------------------------------------------------------------------------------------------


/**
  * @brief Product name title=UM10430 Chapter title=LPC18xx UART1 Modification date=1/14/2011 Major revision=0 Minor revision=7  (UART1)
  */

typedef struct {                            /*!< (@ 0x40082000) UART1 Structure        */
  
  union {
    __IO uint32_t  DLL;                     /*!< (@ 0x40082000) Divisor Latch LSB. Least significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider. (DLAB=1) */
    __O  uint32_t  THR;                     /*!< (@ 0x40082000) Transmit Holding Register. The next character to be transmitted is written here. (DLAB=0) */
    __I  uint32_t  RBR;                     /*!< (@ 0x40082000) Receiver Buffer Register. Contains the next received character to be read. (DLAB=0) */
  } ;
  
  union {
    __IO uint32_t  IER;                     /*!< (@ 0x40082004) Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential UART1 interrupts. (DLAB=0) */
    __IO uint32_t  DLM;                     /*!< (@ 0x40082004) Divisor Latch MSB. Most significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider.(DLAB=1) */
  } ;
  
  union {
    __O  uint32_t  FCR;                     /*!< (@ 0x40082008) FIFO Control Register. Controls UART1 FIFO usage and modes. */
    __I  uint32_t  IIR;                     /*!< (@ 0x40082008) Interrupt ID Register. Identifies which interrupt(s) are pending. */
  } ;
  __IO uint32_t  LCR;                       /*!< (@ 0x4008200C) Line Control Register. Contains controls for frame formatting and break generation. */
  __IO uint32_t  MCR;                       /*!< (@ 0x40082010) Modem Control Register. Contains controls for flow control handshaking and loopback mode. */
  __I  uint32_t  LSR;                       /*!< (@ 0x40082014) Line Status Register. Contains flags for transmit and receive status, including line errors. */
  __I  uint32_t  MSR;                       /*!< (@ 0x40082018) Modem Status Register. Contains handshake signal status flags. */
  __IO uint32_t  SCR;                       /*!< (@ 0x4008201C) Scratch Pad Register. 8-bit temporary storage for software. */
  __IO uint32_t  ACR;                       /*!< (@ 0x40082020) Auto-baud Control Register. Contains controls for the auto-baud feature. */
  __I  uint32_t  RESERVED0;
  __IO uint32_t  FDR;                       /*!< (@ 0x40082028) Fractional Divider Register. Generates a clock input for the baud rate divider. */
  __I  uint32_t  RESERVED1;
  __IO uint32_t  TER;                       /*!< (@ 0x40082030) Transmit Enable Register. Turns off UART transmitter for use with software flow control. */
  __I  uint32_t  RESERVED2[6];
  __IO uint32_t  RS485CTRL;                 /*!< (@ 0x4008204C) RS-485/EIA-485 Control. Contains controls to configure various aspects of RS-485/EIA-485 modes. */
  __IO uint32_t  RS485ADRMATCH;             /*!< (@ 0x40082050) RS-485/EIA-485 address match. Contains the address match value for RS-485/EIA-485 mode. */
  __IO uint32_t  RS485DLY;                  /*!< (@ 0x40082054) RS-485/EIA-485 direction control delay. */
  __I  uint32_t  FIFOLVL;                   /*!< (@ 0x40082058) FIFO Level register. Provides the current fill levels of the transmit and receive FIFOs.  */
} LPC_UART1_Type;


// ------------------------------------------------------------------------------------------------
// -----                                         SSPn                                         -----
// ------------------------------------------------------------------------------------------------


/**
  * @brief Product name title=UM10430 Chapter title=LPC18xx SSP0/1 Modification date=1/14/2011 Major revision=0 Minor revision=7  (SSP0)
  */

typedef struct {                            /*!< (@ 0x400xx000) SSPn Structure         */
  __IO uint32_t CR0;                        /*!< (@ 0x400xx000) Control Register 0. Selects the serial clock rate, bus type, and data size. */
  __IO uint32_t CR1;                        /*!< (@ 0x400xx004) Control Register 1. Selects master/slave and other modes. */
  __IO uint32_t DR;                         /*!< (@ 0x400xx008) Data Register. Writes fill the transmit FIFO, and reads empty the receive FIFO. */
  __I  uint32_t SR;                         /*!< (@ 0x400xx00C) Status Register        */
  __IO uint32_t CPSR;                       /*!< (@ 0x400xx010) Clock Prescale Register */
  __IO uint32_t IMSC;                       /*!< (@ 0x400xx014) Interrupt Mask Set and Clear Register */
  __I  uint32_t RIS;                        /*!< (@ 0x400xx018) Raw Interrupt Status Register */
  __I  uint32_t MIS;                        /*!< (@ 0x400xx01C) Masked Interrupt Status Register */
  __O  uint32_t ICR;                        /*!< (@ 0x400xx020) SSPICR Interrupt Clear Register */
  __IO uint32_t DMACR;                      /*!< (@ 0x400xx024) SSPn DMA control register */
} LPC_SSPn_Type;


// ------------------------------------------------------------------------------------------------
// -----                                        TIMERn                                        -----
// ------------------------------------------------------------------------------------------------


/**
  * @brief Product name title=UM10430 Chapter title=LPC18xx Timer0/1/2/3 Modification date=1/14/2011 Major revision=0 Minor revision=7  (TIMERn)
  */

typedef struct {                            /*!< (@ 0x400xx000) TIMERn Structure       */
  __IO uint32_t IR;                         /*!< (@ 0x400xx000) Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending. */
  __IO uint32_t TCR;                        /*!< (@ 0x400xx004) Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR. */
  __IO uint32_t TC;                         /*!< (@ 0x400xx008) Timer Counter. The 32 bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR. */
  __IO uint32_t PR;                         /*!< (@ 0x400xx00C) Prescale Register. The Prescale Counter (below) is equal to this value, the next clock increments the TC and clears the PC. */
  __IO uint32_t PC;                         /*!< (@ 0x400xx010) Prescale Counter. The 32 bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface. */
  __IO uint32_t MCR;                        /*!< (@ 0x400xx014) Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs. */
  __IO uint32_t MR[4];                      /*!< (@ 0x400xx018) Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC. */
  __IO uint32_t CCR;                        /*!< (@ 0x400xx028) Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place. */
  __IO uint32_t CR[4];                      /*!< (@ 0x400xx02C) Capture Register. CR is loaded with the value of TC when there is an event on the CAPn.0 input. */
  __IO uint32_t EMR;                        /*!< (@ 0x400xx03C) External Match Register. The EMR controls the external match pins MATn.0-3 (MAT0.0-3 and MAT1.0-3 respectively). */
  __I  uint32_t  RESERVED0[12];
  __IO uint32_t CTCR;                       /*!< (@ 0x400xx070) Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting. */
} LPC_TIMERn_Type;




// ------------------------------------------------------------------------------------------------
// -----                                          SCU                                         -----
// ------------------------------------------------------------------------------------------------


/**
  * @brief Product name title=UM10430 Chapter title=LPC18xx System Control Unit (SCU) Modification date=6/8/2011 Major revision=0 Minor revision=10  (SCU)
  */

typedef struct {                            /*!< (@ 0x40086000) SCU Structure          */
  __IO uint32_t  SFSP0_0;                   /*!< (@ 0x40086000) Pin configuration register for pins P0 */
  __IO uint32_t  SFSP0_1;                   /*!< (@ 0x40086004) Pin configuration register for pins P0 */
  __I  uint32_t  RESERVED0[30];
  __IO uint32_t  SFSP1_0;                   /*!< (@ 0x40086080) Pin configuration register for pins P1 */
  __IO uint32_t  SFSP1_1;                   /*!< (@ 0x40086084) Pin configuration register for pins P1 */
  __IO uint32_t  SFSP1_2;                   /*!< (@ 0x40086088) Pin configuration register for pins P1 */
  __IO uint32_t  SFSP1_3;                   /*!< (@ 0x4008608C) Pin configuration register for pins P1 */
  __IO uint32_t  SFSP1_4;                   /*!< (@ 0x40086090) Pin configuration register for pins P1 */
  __IO uint32_t  SFSP1_5;                   /*!< (@ 0x40086094) Pin configuration register for pins P1 */
  __IO uint32_t  SFSP1_6;                   /*!< (@ 0x40086098) Pin configuration register for pins P1 */
  __IO uint32_t  SFSP1_7;                   /*!< (@ 0x4008609C) Pin configuration register for pins P1 */
  __IO uint32_t  SFSP1_8;                   /*!< (@ 0x400860A0) Pin configuration register for pins P1 */
  __IO uint32_t  SFSP1_9;                   /*!< (@ 0x400860A4) Pin configuration register for pins P1 */
  __IO uint32_t  SFSP1_10;                  /*!< (@ 0x400860A8) Pin configuration register for pins P1 */
  __IO uint32_t  SFSP1_11;                  /*!< (@ 0x400860AC) Pin configuration register for pins P1 */
  __IO uint32_t  SFSP1_12;                  /*!< (@ 0x400860B0) Pin configuration register for pins P1 */
  __IO uint32_t  SFSP1_13;                  /*!< (@ 0x400860B4) Pin configuration register for pins P1 */
  __IO uint32_t  SFSP1_14;                  /*!< (@ 0x400860B8) Pin configuration register for pins P1 */
  __IO uint32_t  SFSP1_15;                  /*!< (@ 0x400860BC) Pin configuration register for pins P1 */
  __IO uint32_t  SFSP1_16;                  /*!< (@ 0x400860C0) Pin configuration register for pins P1 */
  __IO uint32_t  SFSP1_17;                  /*!< (@ 0x400860C4) Pin configuration register for pins P1 */
  __IO uint32_t  SFSP1_18;                  /*!< (@ 0x400860C8) Pin configuration register for pins P1 */
  __IO uint32_t  SFSP1_19;                  /*!< (@ 0x400860CC) Pin configuration register for pins P1 */
  __IO uint32_t  SFSP1_20;                  /*!< (@ 0x400860D0) Pin configuration register for pins P1 */
  __I  uint32_t  RESERVED1[11];
  __IO uint32_t  SFSP2_0;                   /*!< (@ 0x40086100) Pin configuration register for pins P2 */
  __IO uint32_t  SFSP2_1;                   /*!< (@ 0x40086104) Pin configuration register for pins P2 */
  __IO uint32_t  SFSP2_2;                   /*!< (@ 0x40086108) Pin configuration register for pins P2 */
  __IO uint32_t  SFSP2_3;                   /*!< (@ 0x4008610C) Pin configuration register for pins P2 */
  __IO uint32_t  SFSP2_4;                   /*!< (@ 0x40086110) Pin configuration register for pins P2 */
  __IO uint32_t  SFSP2_5;                   /*!< (@ 0x40086114) Pin configuration register for pins P2 */
  __IO uint32_t  SFSP2_6;                   /*!< (@ 0x40086118) Pin configuration register for pins P2 */
  __IO uint32_t  SFSP2_7;                   /*!< (@ 0x4008611C) Pin configuration register for pins P2 */
  __IO uint32_t  SFSP2_8;                   /*!< (@ 0x40086120) Pin configuration register for pins P2 */
  __IO uint32_t  SFSP2_9;                   /*!< (@ 0x40086124) Pin configuration register for pins P2 */
  __IO uint32_t  SFSP2_10;                  /*!< (@ 0x40086128) Pin configuration register for pins P2 */
  __IO uint32_t  SFSP2_11;                  /*!< (@ 0x4008612C) Pin configuration register for pins P2 */
  __IO uint32_t  SFSP2_12;                  /*!< (@ 0x40086130) Pin configuration register for pins P2 */
  __IO uint32_t  SFSP2_13;                  /*!< (@ 0x40086134) Pin configuration register for pins P2 */
  __I  uint32_t  RESERVED2[18];
  __IO uint32_t  SFSP3_0;                   /*!< (@ 0x40086180) Pin configuration register for pins P3 */
  __IO uint32_t  SFSP3_1;                   /*!< (@ 0x40086184) Pin configuration register for pins P3 */
  __IO uint32_t  SFSP3_2;                   /*!< (@ 0x40086188) Pin configuration register for pins P3 */
  __IO uint32_t  SFSP3_3;                   /*!< (@ 0x4008618C) Pin configuration register for pins P3 */
  __IO uint32_t  SFSP3_4;                   /*!< (@ 0x40086190) Pin configuration register for pins P3 */
  __IO uint32_t  SFSP3_5;                   /*!< (@ 0x40086194) Pin configuration register for pins P3 */
  __IO uint32_t  SFSP3_6;                   /*!< (@ 0x40086198) Pin configuration register for pins P3 */
  __IO uint32_t  SFSP3_7;                   /*!< (@ 0x4008619C) Pin configuration register for pins P3 */
  __IO uint32_t  SFSP3_8;                   /*!< (@ 0x400861A0) Pin configuration register for pins P3 */
  __I  uint32_t  RESERVED3[23];
  __IO uint32_t  SFSP4_0;                   /*!< (@ 0x40086200) Pin configuration register for pins P4 */
  __IO uint32_t  SFSP4_1;                   /*!< (@ 0x40086204) Pin configuration register for pins P4 */
  __IO uint32_t  SFSP4_2;                   /*!< (@ 0x40086208) Pin configuration register for pins P4 */
  __IO uint32_t  SFSP4_3;                   /*!< (@ 0x4008620C) Pin configuration register for pins P4 */
  __IO uint32_t  SFSP4_4;                   /*!< (@ 0x40086210) Pin configuration register for pins P4 */
  __IO uint32_t  SFSP4_5;                   /*!< (@ 0x40086214) Pin configuration register for pins P4 */
  __IO uint32_t  SFSP4_6;                   /*!< (@ 0x40086218) Pin configuration register for pins P4 */
  __IO uint32_t  SFSP4_7;                   /*!< (@ 0x4008621C) Pin configuration register for pins P4 */
  __IO uint32_t  SFSP4_8;                   /*!< (@ 0x40086220) Pin configuration register for pins P4 */
  __IO uint32_t  SFSP4_9;                   /*!< (@ 0x40086224) Pin configuration register for pins P4 */
  __IO uint32_t  SFSP4_10;                  /*!< (@ 0x40086228) Pin configuration register for pins P4 */
  __I  uint32_t  RESERVED4[21];
  __IO uint32_t  SFSP5_0;                   /*!< (@ 0x40086280) Pin configuration register for pins P5 */
  __IO uint32_t  SFSP5_1;                   /*!< (@ 0x40086284) Pin configuration register for pins P5 */
  __IO uint32_t  SFSP5_2;                   /*!< (@ 0x40086288) Pin configuration register for pins P5 */
  __IO uint32_t  SFSP5_3;                   /*!< (@ 0x4008628C) Pin configuration register for pins P5 */
  __IO uint32_t  SFSP5_4;                   /*!< (@ 0x40086290) Pin configuration register for pins P5 */
  __IO uint32_t  SFSP5_5;                   /*!< (@ 0x40086294) Pin configuration register for pins P5 */
  __IO uint32_t  SFSP5_6;                   /*!< (@ 0x40086298) Pin configuration register for pins P5 */
  __IO uint32_t  SFSP5_7;                   /*!< (@ 0x4008629C) Pin configuration register for pins P5 */
  __I  uint32_t  RESERVED5[24];
  __IO uint32_t  SFSP6_0;                   /*!< (@ 0x40086300) Pin configuration register for pins P6 */
  __IO uint32_t  SFSP6_1;                   /*!< (@ 0x40086304) Pin configuration register for pins P6 */
  __IO uint32_t  SFSP6_2;                   /*!< (@ 0x40086308) Pin configuration register for pins P6 */
  __IO uint32_t  SFSP6_3;                   /*!< (@ 0x4008630C) Pin configuration register for pins P6 */
  __IO uint32_t  SFSP6_4;                   /*!< (@ 0x40086310) Pin configuration register for pins P6 */
  __IO uint32_t  SFSP6_5;                   /*!< (@ 0x40086314) Pin configuration register for pins P6 */
  __IO uint32_t  SFSP6_6;                   /*!< (@ 0x40086318) Pin configuration register for pins P6 */
  __IO uint32_t  SFSP6_7;                   /*!< (@ 0x4008631C) Pin configuration register for pins P6 */
  __IO uint32_t  SFSP6_8;                   /*!< (@ 0x40086320) Pin configuration register for pins P6 */
  __IO uint32_t  SFSP6_9;                   /*!< (@ 0x40086324) Pin configuration register for pins P6 */
  __IO uint32_t  SFSP6_10;                  /*!< (@ 0x40086328) Pin configuration register for pins P6 */
  __IO uint32_t  SFSP6_11;                  /*!< (@ 0x4008632C) Pin configuration register for pins P6 */
  __IO uint32_t  SFSP6_12;                  /*!< (@ 0x40086330) Pin configuration register for pins P6 */
  __I  uint32_t  RESERVED6[19];
  __IO uint32_t  SFSP7_0;                   /*!< (@ 0x40086380) Pin configuration register for pins P7 */
  __IO uint32_t  SFSP7_1;                   /*!< (@ 0x40086384) Pin configuration register for pins P7 */
  __IO uint32_t  SFSP7_2;                   /*!< (@ 0x40086388) Pin configuration register for pins P7 */
  __IO uint32_t  SFSP7_3;                   /*!< (@ 0x4008638C) Pin configuration register for pins P7 */
  __IO uint32_t  SFSP7_4;                   /*!< (@ 0x40086390) Pin configuration register for pins P7 */
  __IO uint32_t  SFSP7_5;                   /*!< (@ 0x40086394) Pin configuration register for pins P7 */
  __IO uint32_t  SFSP7_6;                   /*!< (@ 0x40086398) Pin configuration register for pins P7 */
  __IO uint32_t  SFSP7_7;                   /*!< (@ 0x4008639C) Pin configuration register for pins P7 */
  __I  uint32_t  RESERVED7[24];
  __IO uint32_t  SFSP8_0;                   /*!< (@ 0x40086400) Pin configuration register for pins P8 */
  __IO uint32_t  SFSP8_1;                   /*!< (@ 0x40086404) Pin configuration register for pins P8 */
  __IO uint32_t  SFSP8_2;                   /*!< (@ 0x40086408) Pin configuration register for pins P8 */
  __IO uint32_t  SFSP8_3;                   /*!< (@ 0x4008640C) Pin configuration register for pins P8 */
  __IO uint32_t  SFSP8_4;                   /*!< (@ 0x40086410) Pin configuration register for pins P8 */
  __IO uint32_t  SFSP8_5;                   /*!< (@ 0x40086414) Pin configuration register for pins P8 */
  __IO uint32_t  SFSP8_6;                   /*!< (@ 0x40086418) Pin configuration register for pins P8 */
  __IO uint32_t  SFSP8_7;                   /*!< (@ 0x4008641C) Pin configuration register for pins P8 */
  __IO uint32_t  SFSP8_8;                   /*!< (@ 0x40086420) Pin configuration register for pins P8 */
  __I  uint32_t  RESERVED8[23];
  __IO uint32_t  SFSP9_0;                   /*!< (@ 0x40086480) Pin configuration register for pins P9 */
  __IO uint32_t  SFSP9_1;                   /*!< (@ 0x40086484) Pin configuration register for pins P9 */
  __IO uint32_t  SFSP9_2;                   /*!< (@ 0x40086488) Pin configuration register for pins P9 */
  __IO uint32_t  SFSP9_3;                   /*!< (@ 0x4008648C) Pin configuration register for pins P9 */
  __IO uint32_t  SFSP9_4;                   /*!< (@ 0x40086490) Pin configuration register for pins P9 */
  __IO uint32_t  SFSP9_5;                   /*!< (@ 0x40086494) Pin configuration register for pins P9 */
  __IO uint32_t  SFSP9_6;                   /*!< (@ 0x40086498) Pin configuration register for pins P9 */
  __I  uint32_t  RESERVED9[25];
  __IO uint32_t  SFSPA_0;                   /*!< (@ 0x40086500) Pin configuration register for pins PA */
  __IO uint32_t  SFSPA_1;                   /*!< (@ 0x40086504) Pin configuration register for pins PA */
  __IO uint32_t  SFSPA_2;                   /*!< (@ 0x40086508) Pin configuration register for pins PA */
  __IO uint32_t  SFSPA_3;                   /*!< (@ 0x4008650C) Pin configuration register for pins PA */
  __IO uint32_t  SFSPA_4;                   /*!< (@ 0x40086510) Pin configuration register for pins PA */
  __I  uint32_t  RESERVED10[27];
  __IO uint32_t  SFSPB_0;                   /*!< (@ 0x40086580) Pin configuration register for pins PB */
  __IO uint32_t  SFSPB_1;                   /*!< (@ 0x40086584) Pin configuration register for pins PB */
  __IO uint32_t  SFSPB_2;                   /*!< (@ 0x40086588) Pin configuration register for pins PB */
  __IO uint32_t  SFSPB_3;                   /*!< (@ 0x4008658C) Pin configuration register for pins PB */
  __IO uint32_t  SFSPB_4;                   /*!< (@ 0x40086590) Pin configuration register for pins PB */
  __IO uint32_t  SFSPB_5;                   /*!< (@ 0x40086594) Pin configuration register for pins PB */
  __IO uint32_t  SFSPB_6;                   /*!< (@ 0x40086598) Pin configuration register for pins PB */
  __I  uint32_t  RESERVED11[25];
  __IO uint32_t  SFSPC_0;                   /*!< (@ 0x40086600) Pin configuration register for pins PC */
  __IO uint32_t  SFSPC_1;                   /*!< (@ 0x40086604) Pin configuration register for pins PC */
  __IO uint32_t  SFSPC_2;                   /*!< (@ 0x40086608) Pin configuration register for pins PC */
  __IO uint32_t  SFSPC_3;                   /*!< (@ 0x4008660C) Pin configuration register for pins PC */
  __IO uint32_t  SFSPC_4;                   /*!< (@ 0x40086610) Pin configuration register for pins PC */
  __IO uint32_t  SFSPC_5;                   /*!< (@ 0x40086614) Pin configuration register for pins PC */
  __IO uint32_t  SFSPC_6;                   /*!< (@ 0x40086618) Pin configuration register for pins PC */
  __IO uint32_t  SFSPC_7;                   /*!< (@ 0x4008661C) Pin configuration register for pins PC */
  __IO uint32_t  SFSPC_8;                   /*!< (@ 0x40086620) Pin configuration register for pins PC */
  __IO uint32_t  SFSPC_9;                   /*!< (@ 0x40086624) Pin configuration register for pins PC */
  __IO uint32_t  SFSPC_10;                  /*!< (@ 0x40086628) Pin configuration register for pins PC */
  __IO uint32_t  SFSPC_11;                  /*!< (@ 0x4008662C) Pin configuration register for pins PC */
  __IO uint32_t  SFSPC_12;                  /*!< (@ 0x40086630) Pin configuration register for pins PC */
  __IO uint32_t  SFSPC_13;                  /*!< (@ 0x40086634) Pin configuration register for pins PC */
  __IO uint32_t  SFSPC_14;                  /*!< (@ 0x40086638) Pin configuration register for pins PC */
  __I  uint32_t  RESERVED12[17];
  __IO uint32_t  SFSPD_0;                   /*!< (@ 0x40086680) Pin configuration register for pins PD */
  __IO uint32_t  SFSPD_1;                   /*!< (@ 0x40086684) Pin configuration register for pins PD */
  __IO uint32_t  SFSPD_2;                   /*!< (@ 0x40086688) Pin configuration register for pins PD */
  __IO uint32_t  SFSPD_3;                   /*!< (@ 0x4008668C) Pin configuration register for pins PD */
  __IO uint32_t  SFSPD_4;                   /*!< (@ 0x40086690) Pin configuration register for pins PD */
  __IO uint32_t  SFSPD_5;                   /*!< (@ 0x40086694) Pin configuration register for pins PD */
  __IO uint32_t  SFSPD_6;                   /*!< (@ 0x40086698) Pin configuration register for pins PD */
  __IO uint32_t  SFSPD_7;                   /*!< (@ 0x4008669C) Pin configuration register for pins PD */
  __IO uint32_t  SFSPD_8;                   /*!< (@ 0x400866A0) Pin configuration register for pins PD */
  __IO uint32_t  SFSPD_9;                   /*!< (@ 0x400866A4) Pin configuration register for pins PD */
  __IO uint32_t  SFSPD_10;                  /*!< (@ 0x400866A8) Pin configuration register for pins PD */
  __IO uint32_t  SFSPD_11;                  /*!< (@ 0x400866AC) Pin configuration register for pins PD */
  __IO uint32_t  SFSPD_12;                  /*!< (@ 0x400866B0) Pin configuration register for pins PD */
  __IO uint32_t  SFSPD_13;                  /*!< (@ 0x400866B4) Pin configuration register for pins PD */
  __IO uint32_t  SFSPD_14;                  /*!< (@ 0x400866B8) Pin configuration register for pins PD */
  __IO uint32_t  SFSPD_15;                  /*!< (@ 0x400866BC) Pin configuration register for pins PD */
  __IO uint32_t  SFSPD_16;                  /*!< (@ 0x400866C0) Pin configuration register for pins PD */
  __I  uint32_t  RESERVED13[15];
  __IO uint32_t  SFSPE_0;                   /*!< (@ 0x40086700) Pin configuration register for pins PE */
  __IO uint32_t  SFSPE_1;                   /*!< (@ 0x40086704) Pin configuration register for pins PE */
  __IO uint32_t  SFSPE_2;                   /*!< (@ 0x40086708) Pin configuration register for pins PE */
  __IO uint32_t  SFSPE_3;                   /*!< (@ 0x4008670C) Pin configuration register for pins PE */
  __IO uint32_t  SFSPE_4;                   /*!< (@ 0x40086710) Pin configuration register for pins PE */
  __IO uint32_t  SFSPE_5;                   /*!< (@ 0x40086714) Pin configuration register for pins PE */
  __IO uint32_t  SFSPE_6;                   /*!< (@ 0x40086718) Pin configuration register for pins PE */
  __IO uint32_t  SFSPE_7;                   /*!< (@ 0x4008671C) Pin configuration register for pins PE */
  __IO uint32_t  SFSPE_8;                   /*!< (@ 0x40086720) Pin configuration register for pins PE */
  __IO uint32_t  SFSPE_9;                   /*!< (@ 0x40086724) Pin configuration register for pins PE */
  __IO uint32_t  SFSPE_10;                  /*!< (@ 0x40086728) Pin configuration register for pins PE */
  __IO uint32_t  SFSPE_11;                  /*!< (@ 0x4008672C) Pin configuration register for pins PE */
  __IO uint32_t  SFSPE_12;                  /*!< (@ 0x40086730) Pin configuration register for pins PE */
  __IO uint32_t  SFSPE_13;                  /*!< (@ 0x40086734) Pin configuration register for pins PE */
  __IO uint32_t  SFSPE_14;                  /*!< (@ 0x40086738) Pin configuration register for pins PE */
  __IO uint32_t  SFSPE_15;                  /*!< (@ 0x4008673C) Pin configuration register for pins PE */
  __I  uint32_t  RESERVED14[16];
  __IO uint32_t  SFSPF_0;                   /*!< (@ 0x40086780) Pin configuration register for pins PF */
  __IO uint32_t  SFSPF_1;                   /*!< (@ 0x40086784) Pin configuration register for pins PF */
  __IO uint32_t  SFSPF_2;                   /*!< (@ 0x40086788) Pin configuration register for pins PF */
  __IO uint32_t  SFSPF_3;                   /*!< (@ 0x4008678C) Pin configuration register for pins PF */
  __IO uint32_t  SFSPF_4;                   /*!< (@ 0x40086790) Pin configuration register for pins PF */
  __IO uint32_t  SFSPF_5;                   /*!< (@ 0x40086794) Pin configuration register for pins PF */
  __IO uint32_t  SFSPF_6;                   /*!< (@ 0x40086798) Pin configuration register for pins PF */
  __IO uint32_t  SFSPF_7;                   /*!< (@ 0x4008679C) Pin configuration register for pins PF */
  __IO uint32_t  SFSPF_8;                   /*!< (@ 0x400867A0) Pin configuration register for pins PF */
  __IO uint32_t  SFSPF_9;                   /*!< (@ 0x400867A4) Pin configuration register for pins PF */
  __IO uint32_t  SFSPF_10;                  /*!< (@ 0x400867A8) Pin configuration register for pins PF */
  __IO uint32_t  SFSPF_11;                  /*!< (@ 0x400867AC) Pin configuration register for pins PF */
  __I  uint32_t  RESERVED15[276];
  __IO uint32_t  SFSCLK_0;                  /*!< (@ 0x40086C00) Pin configuration register for pin CLK0 */
  __IO uint32_t  SFSCLK_1;                  /*!< (@ 0x40086C04) Pin configuration register for pin CLK1 */
  __IO uint32_t  SFSCLK_2;                  /*!< (@ 0x40086C08) Pin configuration register for pin CLK2 */
  __IO uint32_t  SFSCLK_3;                  /*!< (@ 0x40086C0C) Pin configuration register for pin CLK3 */
  __I  uint32_t  RESERVED16[28];
  __IO uint32_t  SFSUSB;                    /*!< (@ 0x40086C80) Pin configuration register for */
  __IO uint32_t  SFSI2C0;                   /*!< (@ 0x40086C84) Pin configuration register for I 2C0-bus pins */
  __IO uint32_t  ENAIO0;                    /*!< (@ 0x40086C88) ADC0 function select register */
  __IO uint32_t  ENAIO1;                    /*!< (@ 0x40086C8C) ADC1 function select register */
  __IO uint32_t  ENAIO2;                    /*!< (@ 0x40086C90) Analog function select register */
  __I  uint32_t  RESERVED17[27];
  __IO uint32_t  EMCDELAYCLK;               /*!< (@ 0x40086D00) EMC clock delay register */
  __I  uint32_t  RESERVED18[63];
  __IO uint32_t  PINTSEL0;                  /*!< (@ 0x40086E00) Pin interrupt select register for pin interrupts 0 to 3. */
  __IO uint32_t  PINTSEL1;                  /*!< (@ 0x40086E04) Pin interrupt select register for pin interrupts 4 to 7. */
} LPC_SCU_Type;


// ------------------------------------------------------------------------------------------------
// -----                                     GPIO_PIN_INT                                     -----
// ------------------------------------------------------------------------------------------------


/**
  * @brief GPIO pin interrupt (GPIO_PIN_INT)
  */

typedef struct {                            /*!< (@ 0x40087000) GPIO_PIN_INT Structure */
  __IO uint32_t  ISEL;                      /*!< (@ 0x40087000) Pin Interrupt Mode register */
  __IO uint32_t  IENR;                      /*!< (@ 0x40087004) Pin Interrupt Enable (Rising) register */
  __O  uint32_t  SIENR;                     /*!< (@ 0x40087008) Set Pin Interrupt Enable (Rising) register */
  __O  uint32_t  CIENR;                     /*!< (@ 0x4008700C) Clear Pin Interrupt Enable (Rising) register */
  __IO uint32_t  IENF;                      /*!< (@ 0x40087010) Pin Interrupt Enable Falling Edge / Active Level register */
  __O  uint32_t  SIENF;                     /*!< (@ 0x40087014) Set Pin Interrupt Enable Falling Edge / Active Level register */
  __O  uint32_t  CIENF;                     /*!< (@ 0x40087018) Clear Pin Interrupt Enable Falling Edge / Active Level address */
  __IO uint32_t  RISE;                      /*!< (@ 0x4008701C) Pin Interrupt Rising Edge register */
  __IO uint32_t  FALL;                      /*!< (@ 0x40087020) Pin Interrupt Falling Edge register */
  __IO uint32_t  IST;                       /*!< (@ 0x40087024) Pin Interrupt Status register */
} LPC_GPIO_PIN_INT_Type;


// ------------------------------------------------------------------------------------------------
// -----                                    GPIO_GROUP_INTn                                   -----
// ------------------------------------------------------------------------------------------------


/**
  * @brief GPIO group interrupt 0 (GPIO_GROUP_INTn)
  */

typedef struct {                            /*!< (@ 0x40088000) GPIO_GROUP_INTn Structure */
  __IO uint32_t  CTRL;                      /*!< (@ 0x40088000) GPIO grouped interrupt control register */
  __I  uint32_t  RESERVED0[7];
  __IO uint32_t  PORT_POL0;                 /*!< (@ 0x40088020) GPIO grouped interrupt port polarity register */
  __IO uint32_t  PORT_POL1;                 /*!< (@ 0x40088024) GPIO grouped interrupt port polarity register */
  __IO uint32_t  PORT_POL2;                 /*!< (@ 0x40088028) GPIO grouped interrupt port polarity register */
  __IO uint32_t  PORT_POL3;                 /*!< (@ 0x4008802C) GPIO grouped interrupt port polarity register */
  __IO uint32_t  PORT_POL4;                 /*!< (@ 0x40088030) GPIO grouped interrupt port polarity register */
  __IO uint32_t  PORT_POL5;                 /*!< (@ 0x40088034) GPIO grouped interrupt port polarity register */
  __IO uint32_t  PORT_POL6;                 /*!< (@ 0x40088038) GPIO grouped interrupt port polarity register */
  __IO uint32_t  PORT_POL7;                 /*!< (@ 0x4008803C) GPIO grouped interrupt port polarity register */
  __IO uint32_t  PORT_ENA0;                 /*!< (@ 0x40088040) GPIO grouped interrupt port m enable register */
  __IO uint32_t  PORT_ENA1;                 /*!< (@ 0x40088044) GPIO grouped interrupt port m enable register */
  __IO uint32_t  PORT_ENA2;                 /*!< (@ 0x40088048) GPIO grouped interrupt port m enable register */
  __IO uint32_t  PORT_ENA3;                 /*!< (@ 0x4008804C) GPIO grouped interrupt port m enable register */
  __IO uint32_t  PORT_ENA4;                 /*!< (@ 0x40088050) GPIO grouped interrupt port m enable register */
  __IO uint32_t  PORT_ENA5;                 /*!< (@ 0x40088054) GPIO grouped interrupt port m enable register */
  __IO uint32_t  PORT_ENA6;                 /*!< (@ 0x40088058) GPIO grouped interrupt port m enable register */
  __IO uint32_t  PORT_ENA7;                 /*!< (@ 0x4008805C) GPIO grouped interrupt port m enable register */
} LPC_GPIO_GROUP_INTn_Type;


// ------------------------------------------------------------------------------------------------
// -----                                         MCPWM                                        -----
// ------------------------------------------------------------------------------------------------


/**
  * @brief Product name title=UM10430 Chapter title=LPC18xx Motor Control PWM (MOTOCONPWM) Modification date=1/14/2011 Major revision=0 Minor revision=7  (MCPWM)
  */

typedef struct {                            /*!< (@ 0x400A0000) MCPWM Structure        */
  __I  uint32_t  CON;                       /*!< (@ 0x400A0000) PWM Control read address */
  __O  uint32_t  CON_SET;                   /*!< (@ 0x400A0004) PWM Control set address */
  __O  uint32_t  CON_CLR;                   /*!< (@ 0x400A0008) PWM Control clear address */
  __I  uint32_t  CAPCON;                    /*!< (@ 0x400A000C) Capture Control read address */
  __O  uint32_t  CAPCON_SET;                /*!< (@ 0x400A0010) Capture Control set address */
  __O  uint32_t  CAPCON_CLR;                /*!< (@ 0x400A0014) Event Control clear address */
  __IO uint32_t TC[3];                      /*!< (@ 0x400A0018) Timer Counter register */
  __IO uint32_t LIM[3];                     /*!< (@ 0x400A0024) Limit register         */
  __IO uint32_t MAT[3];                     /*!< (@ 0x400A0030) Match register         */
  __IO uint32_t  DT;                        /*!< (@ 0x400A003C) Dead time register     */
  __IO uint32_t  CCP;                       /*!< (@ 0x400A0040) Communication Pattern register */
  __I  uint32_t CAP[3];                     /*!< (@ 0x400A0044) Capture register       */
  __I  uint32_t  INTEN;                     /*!< (@ 0x400A0050) Interrupt Enable read address */
  __O  uint32_t  INTEN_SET;                 /*!< (@ 0x400A0054) Interrupt Enable set address */
  __O  uint32_t  INTEN_CLR;                 /*!< (@ 0x400A0058) Interrupt Enable clear address */
  __I  uint32_t  CNTCON;                    /*!< (@ 0x400A005C) Count Control read address */
  __O  uint32_t  CNTCON_SET;                /*!< (@ 0x400A0060) Count Control set address */
  __O  uint32_t  CNTCON_CLR;                /*!< (@ 0x400A0064) Count Control clear address */
  __I  uint32_t  INTF;                      /*!< (@ 0x400A0068) Interrupt flags read address */
  __O  uint32_t  INTF_SET;                  /*!< (@ 0x400A006C) Interrupt flags set address */
  __O  uint32_t  INTF_CLR;                  /*!< (@ 0x400A0070) Interrupt flags clear address */
  __O  uint32_t  CAP_CLR;                   /*!< (@ 0x400A0074) Capture clear address  */
} LPC_MCPWM_Type;


// ------------------------------------------------------------------------------------------------
// -----                                         I2C0                                         -----
// ------------------------------------------------------------------------------------------------


/**
  * @brief Product name title=UM10430 Chapter title=LPC18xx I2C-bus interface Modification date=1/14/2011 Major revision=0 Minor revision=7  (I2Cn)
  */

typedef struct {                            /*!< (@ 0x400xx000) I2C0 Structure         */
  __IO uint32_t CONSET;                     /*!< (@ 0x400xx000) I2C Control Set Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is set. Writing a zero has no effect on the corresponding bit in the I2C control register. */
  __I  uint32_t STAT;                       /*!< (@ 0x400xx004) I2C Status Register. During I2C operation, this register provides detailed status codes that allow software to determine the next action needed. */
  __IO uint32_t DAT;                        /*!< (@ 0x400xx008) I2C Data Register. During master or slave transmit mode, data to be transmitted is written to this register. During master or slave receive mode, data that has been received may be read from this register. */
  __IO uint32_t ADR0;                       /*!< (@ 0x400xx00C) I2C Slave Address Register 0. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. */
  __IO uint32_t SCLH;                       /*!< (@ 0x400xx010) SCH Duty Cycle Register High Half Word. Determines the high time of the I2C clock. */
  __IO uint32_t SCLL;                       /*!< (@ 0x400xx014) SCL Duty Cycle Register Low Half Word. Determines the low time of the I2C clock. SCLL and SCLH together determine the clock frequency generated by an I2C master and certain times used in slave mode. */
  __O  uint32_t CONCLR;                     /*!< (@ 0x400xx018) I2C Control Clear Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is cleared. Writing a zero has no effect on the corresponding bit in the I2C control register. */
  __IO uint32_t MMCTRL;                     /*!< (@ 0x400xx01C) Monitor mode control register. */
  __IO uint32_t ADR1;                       /*!< (@ 0x400xx020) I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. */
  __IO uint32_t ADR2;                       /*!< (@ 0x400xx024) I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. */
  __IO uint32_t ADR3;                       /*!< (@ 0x400xx028) I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. */
  __I  uint32_t DATA_BUFFER;                /*!< (@ 0x400xx02C) Data buffer register. The contents of the 8 MSBs of the DAT shift register will be transferred to the DATA_BUFFER automatically after every nine bits (8 bits of data plus ACK or NACK) has been received on the bus. */
  __IO uint32_t MASK[4];                    /*!< (@ 0x400xx030) I2C Slave address mask register */
} LPC_I2Cn_Type;

// ------------------------------------------------------------------------------------------------
// -----                                         I2Sn                                         -----
// ------------------------------------------------------------------------------------------------


/**
  * @brief Product name title=UM10430 Chapter title=LPC18xx I2S interface Modification date=1/14/2011 Major revision=0 Minor revision=7  (I2Sn)
    0x400A2000 / 0x400A3000
  */

typedef struct {                            /*!< (@ 0x400Ax000) I2S Structure         */
  __IO uint32_t DAO;                        /*!< (@ 0x400Ax000) I2S Digital Audio Output Register. Contains control bits for the I2S transmit channel. */
  __IO uint32_t DAI;                        /*!< (@ 0x400Ax004) I2S Digital Audio Input Register. Contains control bits for the I2S receive channel. */
  __O  uint32_t TXFIFO;                     /*!< (@ 0x400Ax008) I2S Transmit FIFO. Access register for the 8 x 32-bit transmitter FIFO. */
  __I  uint32_t RXFIFO;                     /*!< (@ 0x400Ax00C) I2S Receive FIFO. Access register for the 8 x 32-bit receiver FIFO. */
  __I  uint32_t STATE;                      /*!< (@ 0x400Ax010) I2S Status Feedback Register. Contains status information about the I2S interface. */
  __IO uint32_t DMA1;                       /*!< (@ 0x400Ax014) I2S DMA Configuration Register 1. Contains control information for DMA request 1. */
  __IO uint32_t DMA2;                       /*!< (@ 0x400Ax018) I2S DMA Configuration Register 2. Contains control information for DMA request 2. */
  __IO uint32_t IRQ;                        /*!< (@ 0x400Ax01C) I2S Interrupt Request Control Register. Contains bits that control how the I2S interrupt request is generated. */
  __IO uint32_t TXRATE;                     /*!< (@ 0x400Ax020) I2S Transmit MCLK divider. This register determines the I2S TX MCLK rate by specifying the value to divide PCLK by in order to produce MCLK. */
  __IO uint32_t RXRATE;                     /*!< (@ 0x400Ax024) I2S Receive MCLK divider. This register determines the I2S RX MCLK rate by specifying the value to divide PCLK by in order to produce MCLK. */
  __IO uint32_t TXBITRATE;                  /*!< (@ 0x400Ax028) I2S Transmit bit rate divider. This register determines the I2S transmit bit rate by specifying the value to divide TX_MCLK by in order to produce the transmit bit clock. */
  __IO uint32_t RXBITRATE;                  /*!< (@ 0x400Ax02C) I2S Receive bit rate divider. This register determines the I2S receive bit rate by specifying the value to divide RX_MCLK by in order to produce the receive bit clock. */
  __IO uint32_t TXMODE;                     /*!< (@ 0x400Ax030) I2S Transmit mode control. */
  __IO uint32_t RXMODE;                     /*!< (@ 0x400Ax034) I2S Receive mode control. */
} LPC_I2Sn_Type;

// ------------------------------------------------------------------------------------------------
// -----                                        C_CANn                                        -----
// ------------------------------------------------------------------------------------------------


/**
  * @brief Product name title=UM10430 Chapter title=LPC18xx C_CAN Modification date=1/18/2011 Major revision=0 Minor revision=7  (C_CANn)
    0x400A4000 / 0x400E2000
  */

typedef struct {                            /*!< (@ 0x400E2000) C_CAN Structure       */
  __IO uint32_t CNTL;                       /*!< (@ 0x400E2000) CAN control            */
  __IO uint32_t STAT;                       /*!< (@ 0x400E2004) Status register        */
  __I  uint32_t EC;                         /*!< (@ 0x400E2008) Error counter          */
  __IO uint32_t BT;                         /*!< (@ 0x400E200C) Bit timing register    */
  __I  uint32_t INT;                        /*!< (@ 0x400E2010) Interrupt register     */
  __IO uint32_t TEST;                       /*!< (@ 0x400E2014) Test register          */
  __IO uint32_t BRPE;                       /*!< (@ 0x400E2018) Baud rate prescaler extension register */
  __I  uint32_t  RESERVED0;
  __IO uint32_t IF1_CMDREQ;                 /*!< (@ 0x400E2020) Message interface command request  */
  
  union {
    __IO uint32_t IF1_CMDMSK_R;             /*!< (@ 0x400E2024) Message interface command mask (read direction) */
    __IO uint32_t IF1_CMDMSK_W;             /*!< (@ 0x400E2024) Message interface command mask (write direction) */
  } ;
  __IO uint32_t IF1_MSK1;                   /*!< (@ 0x400E2028) Message interface mask 1 */
  __IO uint32_t IF1_MSK2;                   /*!< (@ 0x400E202C) Message interface 1 mask 2 */
  __IO uint32_t IF1_ARB1;                   /*!< (@ 0x400E2030) Message interface 1 arbitration 1 */
  __IO uint32_t IF1_ARB2;                   /*!< (@ 0x400E2034) Message interface 1 arbitration 2 */
  __IO uint32_t IF1_MCTRL;                  /*!< (@ 0x400E2038) Message interface 1 message control */
  __IO uint32_t IF1_DA1;                    /*!< (@ 0x400E203C) Message interface data A1 */
  __IO uint32_t IF1_DA2;                    /*!< (@ 0x400E2040) Message interface 1 data A2 */
  __IO uint32_t IF1_DB1;                    /*!< (@ 0x400E2044) Message interface 1 data B1 */
  __IO uint32_t IF1_DB2;                    /*!< (@ 0x400E2048) Message interface 1 data B2 */
  __I  uint32_t  RESERVED1[13];
  __IO uint32_t IF2_CMDREQ;                 /*!< (@ 0x400E2080) Message interface command request  */
  
  union {
    __IO uint32_t IF2_CMDMSK_R;             /*!< (@ 0x400E2084) Message interface command mask (read direction) */
    __IO uint32_t IF2_CMDMSK_W;             /*!< (@ 0x400E2084) Message interface command mask (write direction) */
  } ;
  __IO uint32_t IF2_MSK1;                   /*!< (@ 0x400E2088) Message interface mask 1 */
  __IO uint32_t IF2_MSK2;                   /*!< (@ 0x400E208C) Message interface 1 mask 2 */
  __IO uint32_t IF2_ARB1;                   /*!< (@ 0x400E2090) Message interface 1 arbitration 1 */
  __IO uint32_t IF2_ARB2;                   /*!< (@ 0x400E2094) Message interface 1 arbitration 2 */
  __IO uint32_t IF2_MCTRL;                  /*!< (@ 0x400E2098) Message interface 1 message control */
  __IO uint32_t IF2_DA1;                    /*!< (@ 0x400E209C) Message interface data A1 */
  __IO uint32_t IF2_DA2;                    /*!< (@ 0x400E20A0) Message interface 1 data A2 */
  __IO uint32_t IF2_DB1;                    /*!< (@ 0x400E20A4) Message interface 1 data B1 */
  __IO uint32_t IF2_DB2;                    /*!< (@ 0x400E20A8) Message interface 1 data B2 */
  __I  uint32_t  RESERVED2[21];
  __I  uint32_t TXREQ1;                     /*!< (@ 0x400E2100) Transmission request 1 */
  __I  uint32_t TXREQ2;                     /*!< (@ 0x400E2104) Transmission request 2 */
  __I  uint32_t  RESERVED3[6];
  __I  uint32_t ND1;                        /*!< (@ 0x400E2120) New data 1             */
  __I  uint32_t ND2;                        /*!< (@ 0x400E2124) New data 2             */
  __I  uint32_t  RESERVED4[6];
  __I  uint32_t IR1;                        /*!< (@ 0x400E2140) Interrupt pending 1    */
  __I  uint32_t IR2;                        /*!< (@ 0x400E2144) Interrupt pending 2    */
  __I  uint32_t  RESERVED5[6];
  __I  uint32_t MSGV1;                      /*!< (@ 0x400E2160) Message valid 1        */
  __I  uint32_t MSGV2;                      /*!< (@ 0x400E2164) Message valid 2        */
  __I  uint32_t  RESERVED6[6];
  __IO uint32_t CLKDIV;                     /*!< (@ 0x400E2180) CAN clock divider register */
} LPC_C_CANn_Type;


// ------------------------------------------------------------------------------------------------
// -----                                        RITIMER                                       -----
// ------------------------------------------------------------------------------------------------


/**
  * @brief Product name title=UM10430 Chapter title=LPC18xx Repetitive Interrupt Timer (RIT) Modification date=1/14/2011 Major revision=0 Minor revision=7  (RITIMER)
  */

typedef struct {                            /*!< (@ 0x400C0000) RITIMER Structure      */
  __IO uint32_t  COMPVAL;                   /*!< (@ 0x400C0000) Compare register       */
  __IO uint32_t  MASK;                      /*!< (@ 0x400C0004) Mask register. This register holds the 32-bit mask value. A 1 written to any bit will force a compare on the corresponding bit of the counter and compare register. */
  __IO uint32_t  CTRL;                      /*!< (@ 0x400C0008) Control register.      */
  __IO uint32_t  COUNTER;                   /*!< (@ 0x400C000C) 32-bit counter         */
} LPC_RITIMER_Type;


// ------------------------------------------------------------------------------------------------
// -----                                          QEI                                         -----
// ------------------------------------------------------------------------------------------------


/**
  * @brief Product name title=UM10430 Chapter title=LPC18xx Quadrature Encoder Interface (QEI) Modification date=1/18/2011 Major revision=0 Minor revision=7  (QEI)
  */

typedef struct {                            /*!< (@ 0x400C6000) QEI Structure          */
  __O  uint32_t  CON;                       /*!< (@ 0x400C6000) Control register       */
  __I  uint32_t  STAT;                      /*!< (@ 0x400C6004) Encoder status register */
  __IO uint32_t  CONF;                      /*!< (@ 0x400C6008) Configuration register */
  __I  uint32_t  POS;                       /*!< (@ 0x400C600C) Position register      */
  __IO uint32_t  MAXPOS;                    /*!< (@ 0x400C6010) Maximum position register */
  __IO uint32_t  CMPOS0;                    /*!< (@ 0x400C6014) position compare register 0 */
  __IO uint32_t  CMPOS1;                    /*!< (@ 0x400C6018) position compare register 1 */
  __IO uint32_t  CMPOS2;                    /*!< (@ 0x400C601C) position compare register 2 */
  __I  uint32_t  INXCNT;                    /*!< (@ 0x400C6020) Index count register   */
  __IO uint32_t  INXCMP0;                   /*!< (@ 0x400C6024) Index compare register 0 */
  __IO uint32_t  LOAD;                      /*!< (@ 0x400C6028) Velocity timer reload register */
  __I  uint32_t  TIME;                      /*!< (@ 0x400C602C) Velocity timer register */
  __I  uint32_t  VEL;                       /*!< (@ 0x400C6030) Velocity counter register */
  __I  uint32_t  CAP;                       /*!< (@ 0x400C6034) Velocity capture register */
  __IO uint32_t  VELCOMP;                   /*!< (@ 0x400C6038) Velocity compare register */
  __IO uint32_t  FILTERPHA;                 /*!< (@ 0x400C603C) Digital filter register on input phase A (QEI_A) */
  __IO uint32_t  FILTERPHB;                 /*!< (@ 0x400C6040) Digital filter register on input phase B (QEI_B) */
  __IO uint32_t  FILTERINX;                 /*!< (@ 0x400C6044) Digital filter register on input index (QEI_IDX) */
  __IO uint32_t  WINDOW;                    /*!< (@ 0x400C6048) Index acceptance window register */
  __IO uint32_t  INXCMP1;                   /*!< (@ 0x400C604C) Index compare register 1 */
  __IO uint32_t  INXCMP2;                   /*!< (@ 0x400C6050) Index compare register 2 */
  __I  uint32_t  RESERVED0[993];
  __O  uint32_t  IEC;                       /*!< (@ 0x400C6FD8) Interrupt enable clear register */
  __O  uint32_t  IES;                       /*!< (@ 0x400C6FDC) Interrupt enable set register */
  __I  uint32_t  INTSTAT;                   /*!< (@ 0x400C6FE0) Interrupt status register */
  __I  uint32_t  IE;                        /*!< (@ 0x400C6FE4) Interrupt enable register */
  __O  uint32_t  CLR;                       /*!< (@ 0x400C6FE8) Interrupt status clear register */
  __O  uint32_t  SET;                       /*!< (@ 0x400C6FEC) Interrupt status set register */
} LPC_QEI_Type;


// ------------------------------------------------------------------------------------------------
// -----                                         GIMA                                         -----
// ------------------------------------------------------------------------------------------------


/**
  * @brief Product name title=UM10503 Chapter title=LPC43xx Global Input Multiplexer Array (GIMA) Modification date=10/7/2011 Major revision=0 Minor revision=3  (GIMA)
  */

typedef struct {                            /*!< (@ 0x400C7000) GIMA Structure         */
  __IO uint32_t  CAP0_0_IN;                 /*!< (@ 0x400C7000) Timer 0 CAP0_0 capture input multiplexer (GIMA output 0) */
  __IO uint32_t  CAP0_1_IN;                 /*!< (@ 0x400C7004) Timer 0 CAP0_1 capture input multiplexer (GIMA output 1) */
  __IO uint32_t  CAP0_2_IN;                 /*!< (@ 0x400C7008) Timer 0 CAP0_2 capture input multiplexer (GIMA output 2) */
  __IO uint32_t  CAP0_3_IN;                 /*!< (@ 0x400C700C) Timer 0 CAP0_3 capture input multiplexer (GIMA output 3) */
  __IO uint32_t  CAP1_0_IN;                 /*!< (@ 0x400C7010) Timer 1 CAP1_0 capture input multiplexer (GIMA output 4) */
  __IO uint32_t  CAP1_1_IN;                 /*!< (@ 0x400C7014) Timer 1 CAP1_1 capture input multiplexer (GIMA output 5) */
  __IO uint32_t  CAP1_2_IN;                 /*!< (@ 0x400C7018) Timer 1 CAP1_2 capture input multiplexer (GIMA output 6) */
  __IO uint32_t  CAP1_3_IN;                 /*!< (@ 0x400C701C) Timer 1 CAP1_3 capture input multiplexer (GIMA output 7) */
  __IO uint32_t  CAP2_0_IN;                 /*!< (@ 0x400C7020) Timer 2 CAP2_0 capture input multiplexer (GIMA output 8) */
  __IO uint32_t  CAP2_1_IN;                 /*!< (@ 0x400C7024) Timer 2 CAP2_1 capture input multiplexer (GIMA output 9) */
  __IO uint32_t  CAP2_2_IN;                 /*!< (@ 0x400C7028) Timer 2 CAP2_2 capture input multiplexer (GIMA output 10) */
  __IO uint32_t  CAP2_3_IN;                 /*!< (@ 0x400C702C) Timer 2 CAP2_3 capture input multiplexer (GIMA output 11) */
  __IO uint32_t  CAP3_0_IN;                 /*!< (@ 0x400C7030) Timer 3 CAP3_0 capture input multiplexer (GIMA output 12) */
  __IO uint32_t  CAP3_1_IN;                 /*!< (@ 0x400C7034) Timer 3 CAP3_1 capture input multiplexer (GIMA output 13) */
  __IO uint32_t  CAP3_2_IN;                 /*!< (@ 0x400C7038) Timer 3 CAP3_2 capture input multiplexer (GIMA output 14) */
  __IO uint32_t  CAP3_3_IN;                 /*!< (@ 0x400C703C) Timer 3 CAP3_3 capture input multiplexer (GIMA output 15) */
  __IO uint32_t  CTIN_0_IN;                 /*!< (@ 0x400C7040) SCT CTIN_0 capture input multiplexer (GIMA output 16) */
  __IO uint32_t  CTIN_1_IN;                 /*!< (@ 0x400C7044) SCT CTIN_1 capture input multiplexer (GIMA output 17) */
  __IO uint32_t  CTIN_2_IN;                 /*!< (@ 0x400C7048) SCT CTIN_2 capture input multiplexer (GIMA output 18) */
  __IO uint32_t  CTIN_3_IN;                 /*!< (@ 0x400C704C) SCT CTIN_3 capture input multiplexer (GIMA output 19) */
  __IO uint32_t  CTIN_4_IN;                 /*!< (@ 0x400C7050) SCT CTIN_4 capture input multiplexer (GIMA output 20) */
  __IO uint32_t  CTIN_5_IN;                 /*!< (@ 0x400C7054) SCT CTIN_5 capture input multiplexer (GIMA output 21) */
  __IO uint32_t  CTIN_6_IN;                 /*!< (@ 0x400C7058) SCT CTIN_6 capture input multiplexer (GIMA output 22) */
  __IO uint32_t  CTIN_7_IN;                 /*!< (@ 0x400C705C) SCT CTIN_7 capture input multiplexer (GIMA output 23) */
  __IO uint32_t  VADC_TRIGGER_IN;           /*!< (@ 0x400C7060) VADC trigger input multiplexer (GIMA output 24) */
  __IO uint32_t  EVENTROUTER_13_IN;         /*!< (@ 0x400C7064) Event router input 13 multiplexer (GIMA output 25) */
  __IO uint32_t  EVENTROUTER_14_IN;         /*!< (@ 0x400C7068) Event router input 14 multiplexer (GIMA output 26) */
  __IO uint32_t  EVENTROUTER_16_IN;         /*!< (@ 0x400C706C) Event router input 16 multiplexer (GIMA output 27) */
  __IO uint32_t  ADCSTART0_IN;              /*!< (@ 0x400C7070) ADC start0 input multiplexer (GIMA output 28) */
  __IO uint32_t  ADCSTART1_IN;              /*!< (@ 0x400C7074) ADC start1 input multiplexer (GIMA output 29) */
} LPC_GIMA_Type;


// ------------------------------------------------------------------------------------------------
// -----                                          DAC                                         -----
// ------------------------------------------------------------------------------------------------


/**
  * @brief Product name title=UM10430 Chapter title=LPC18xx DAC Modification date=1/18/2011 Major revision=0 Minor revision=7  (DAC)
  */

typedef struct {                            /*!< (@ 0x400E1000) DAC Structure          */
  __IO uint32_t  CR;                        /*!< (@ 0x400E1000) DAC register. Holds the conversion data. */
  __IO uint32_t  CTRL;                      /*!< (@ 0x400E1004) DAC control register.  */
  __IO uint32_t  CNTVAL;                    /*!< (@ 0x400E1008) DAC counter value register. */
} LPC_DAC_Type;



// ------------------------------------------------------------------------------------------------
// -----                                         ADCn                                         -----
// ------------------------------------------------------------------------------------------------


/**
  * @brief Product name title=UM10430 Chapter title=LPC18xx 10-bit ADC0/1 Modification date=1/18/2011 Major revision=0 Minor revision=7  (ADCn)
    0x400E3000 / 0x400E4000
  */

typedef struct {                            /*!< (@ 0x400Ex000) ADCn Structure         */
  __IO uint32_t CR;                         /*!< (@ 0x400Ex000) A/D Control Register. The AD0CR register must be written to select the operating mode before A/D conversion can occur. */
  __I  uint32_t GDR;                        /*!< (@ 0x400Ex004) A/D Global Data Register. Contains the result of the most recent A/D conversion. */
  __I  uint32_t  RESERVED0;
  __IO uint32_t INTEN;                      /*!< (@ 0x400Ex00C) A/D Interrupt Enable Register. This register contains enable bits that allow the DONE flag of each A/D channel to be included or excluded from contributing to the generation of an A/D interrupt. */
  __I  uint32_t DR[8];                      /*!< (@ 0x400Ex010) A/D Channel Data Register. This register contains the result of the most recent conversion completed on channel n. */
  __I  uint32_t STAT;                       /*!< (@ 0x400Ex030) A/D Status Register. This register contains DONE and OVERRUN flags for all of the A/D channels, as well as the A/D interrupt flag. */
} LPC_ADCn_Type;


// ------------------------------------------------------------------------------------------------
// -----                                       GPIO_PORT                                      -----
// ------------------------------------------------------------------------------------------------


/**
  * @brief GPIO port  (GPIO_PORT)
  */

typedef struct {                            /*!< (@ 0x400F4000) GPIO_PORT Structure    */
  __IO uint8_t B[256];                      /*!< (@ 0x400F4000) Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31 */
  __I  uint32_t  RESERVED0[960];
  __IO uint32_t W[256];                     /*!< (@ 0x400F5000) Word pin registers port 0 to 5 */
  __I  uint32_t  RESERVED1[768];
  __IO uint32_t DIR[8];                     /*!< (@ 0x400F6000) Direction registers port n */
  __I  uint32_t  RESERVED2[24];
  __IO uint32_t MASK[8];                    /*!< (@ 0x400F6080) Mask register port n   */
  __I  uint32_t  RESERVED3[24];
  __IO uint32_t PIN[8];                     /*!< (@ 0x400F6100) Portpin register port n */
  __I  uint32_t  RESERVED4[24];
  __IO uint32_t MPIN[8];                    /*!< (@ 0x400F6180) Masked port register port n */
  __I  uint32_t  RESERVED5[24];
  __IO uint32_t SET[8];                     /*!< (@ 0x400F6200) Write: Set register for port n Read: output bits for port n */
  __I  uint32_t  RESERVED6[24];
  __O  uint32_t CLR[8];                     /*!< (@ 0x400F6280) Clear port n           */
  __I  uint32_t  RESERVED7[24];
  __O  uint32_t NOT[8];                     /*!< (@ 0x400F6300) Toggle port n          */
} LPC_GPIO_PORT_Type;


// ------------------------------------------------------------------------------------------------
// -----                                          SPI                                         -----
// ------------------------------------------------------------------------------------------------


/**
  * @brief Product name title=UM10503 Chapter title=LPC43xxSPI Modification date=10/7/2011 Major revision=0 Minor revision=3  (SPI)
  */

typedef struct {                            /*!< (@ 0x40100000) SPI Structure          */
  __IO uint32_t  CR;                        /*!< (@ 0x40100000) SPI Control Register. This register controls the operation of the SPI. */
  __I  uint32_t  SR;                        /*!< (@ 0x40100004) SPI Status Register. This register shows the status of the SPI. */
  __IO uint32_t  DR;                        /*!< (@ 0x40100008) SPI Data Register. This bi-directional register provides the transmit and receive data for the SPI. Transmit data is provided to the SPI0 by writing to this register. Data received by the SPI0 can be read from this register. */
  __IO uint32_t  CCR;                       /*!< (@ 0x4010000C) SPI Clock Counter Register. This register controls the frequency of a master's SCK0. */
  __IO uint32_t  TCR;                       /*!< (@ 0x40100010) SPI Test Control register. For functional testing only. */
  __IO uint32_t  TSR;                       /*!< (@ 0x40100014) SPI Test Status register. For functional testing only. */
  __I  uint32_t  RESERVED0;
  __IO uint32_t  INT;                       /*!< (@ 0x4010001C) SPI Interrupt Flag. This register contains the interrupt flag for the SPI interface. */
} LPC_SPI_Type;


// ------------------------------------------------------------------------------------------------
// -----                                         SGPIO                                        -----
// ------------------------------------------------------------------------------------------------


/**
  * @brief Product name title=UM10503 Chapter title=LPC43xx SerialGPIO (SGPIO) Modification date=10/7/2011 Major revision=0 Minor revision=3  (SGPIO)
  */

typedef struct {                            /*!< (@ 0x40101000) SGPIO Structure        */
  __IO uint32_t  OUT_MUX_CFG[16];              /*!< (@ 0x40101000) Pin multiplexer configurationregisters. */
  __IO uint32_t  SGPIO_MUX_CFG[16];            /*!< (@ 0x40101040) SGPIO multiplexer configuration registers. */
  __IO uint32_t  SLICE_MUX_CFG[16];            /*!< (@ 0x40101080) Slice multiplexer configuration registers. */
  __IO uint32_t  REG[16];                      /*!< (@ 0x401010C0) Slice data registers. Eachtime COUNT0 reaches 0x0 the register shifts loading bit 31 withdata captured from DIN(n). DOUT(n) is set to REG(0) */
  __IO uint32_t  REG_SS[16];                   /*!< (@ 0x40101100) Slice data shadow registers. Each time POSreaches 0x0 the contents of REG_SS is exchanged with the contentof REG */
  __IO uint32_t  PRESET[16];                   /*!< (@ 0x40101140) Reload valueof COUNT0, loaded when COUNT0 reaches 0x0 */
  __IO uint32_t  COUNT[16];                    /*!< (@ 0x40101180) Down counter, counts down each clock cycle. */
  __IO uint32_t  POS[16];                      /*!< (@ 0x401011C0) Each time COUNT0 reaches 0x0 */
  __IO uint32_t  MASK_A;                    /*!< (@ 0x40101200) Mask for pattern match function of slice A */
  __IO uint32_t  MASK_H;                    /*!< (@ 0x40101204) Mask for pattern match function of slice H */
  __IO uint32_t  MASK_I;                    /*!< (@ 0x40101208) Mask for pattern match function of slice I */
  __IO uint32_t  MASK_P;                    /*!< (@ 0x4010120C) Mask for pattern match function of slice P */
  __I  uint32_t  GPIO_INREG;                /*!< (@ 0x40101210) GPIO input status register */
  __IO uint32_t  GPIO_OUTREG;               /*!< (@ 0x40101214) GPIO output control register */
  __IO uint32_t  GPIO_OENREG;               /*!< (@ 0x40101218) GPIO OE control register */
  __IO uint32_t  CTRL_ENABLED;              /*!< (@ 0x4010121C) Enables the slice COUNT counter */
  __IO uint32_t  CTRL_DISABLED;             /*!< (@ 0x40101220) Disables the slice COUNT counter */
  __I  uint32_t  RESERVED0[823];
  __O  uint32_t  CLR_EN_0;                  /*!< (@ 0x40101F00) Shift clock interrupt clear mask */
  __O  uint32_t  SET_EN_0;                  /*!< (@ 0x40101F04) Shift clock interrupt set mask */
  __I  uint32_t  ENABLE_0;                  /*!< (@ 0x40101F08) Shift clock interrupt enable */
  __I  uint32_t  STATUS_0;                  /*!< (@ 0x40101F0C) Shift clock interrupt status */
  __O  uint32_t  CTR_STATUS_0;              /*!< (@ 0x40101F10) Shift clock interrupt clear status */
  __O  uint32_t  SET_STATUS_0;              /*!< (@ 0x40101F14) Shift clock interrupt set status */
  __I  uint32_t  RESERVED1[2];
  __O  uint32_t  CLR_EN_1;                  /*!< (@ 0x40101F20) Capture clock interrupt clear mask */
  __O  uint32_t  SET_EN_1;                  /*!< (@ 0x40101F24) Capture clock interrupt set mask */
  __I  uint32_t  ENABLE_1;                  /*!< (@ 0x40101F28) Capture clock interrupt enable */
  __I  uint32_t  STATUS_1;                  /*!< (@ 0x40101F2C) Capture clock interrupt status */
  __O  uint32_t  CTR_STATUS_1;              /*!< (@ 0x40101F30) Capture clock interrupt clear status */
  __O  uint32_t  SET_STATUS_1;              /*!< (@ 0x40101F34) Capture clock interrupt set status */
  __I  uint32_t  RESERVED2[2];
  __O  uint32_t  CLR_EN_2;                  /*!< (@ 0x40101F40) Pattern match interrupt clear mask */
  __O  uint32_t  SET_EN_2;                  /*!< (@ 0x40101F44) Pattern match interrupt set mask */
  __I  uint32_t  ENABLE_2;                  /*!< (@ 0x40101F48) Pattern match interrupt enable */
  __I  uint32_t  STATUS_2;                  /*!< (@ 0x40101F4C) Pattern match interrupt status */
  __O  uint32_t  CTR_STATUS_2;              /*!< (@ 0x40101F50) Pattern match interrupt clear status */
  __O  uint32_t  SET_STATUS_2;              /*!< (@ 0x40101F54) Pattern match interrupt set status */
  __I  uint32_t  RESERVED3[2];
  __O  uint32_t  CLR_EN_3;                  /*!< (@ 0x40101F60) Input interrupt clear mask */
  __O  uint32_t  SET_EN_3;                  /*!< (@ 0x40101F64) Input bit match interrupt set mask */
  __I  uint32_t  ENABLE_3;                  /*!< (@ 0x40101F68) Input bit match interrupt enable */
  __I  uint32_t  STATUS_3;                  /*!< (@ 0x40101F6C) Input bit match interrupt status */
  __O  uint32_t  CTR_STATUS_3;              /*!< (@ 0x40101F70) Input bit match interrupt clear status */
  __O  uint32_t  SET_STATUS_3;              /*!< (@ 0x40101F74) Shift clock interrupt set status */
} LPC_SGPIO_Type;



/********************************************
** End of section using anonymous unions   **
*********************************************/

#if defined(__ARMCC_VERSION)
  #pragma pop
#elif defined(__CWCC__)
  #pragma pop
#elif defined(__GNUC__)
  /* leave anonymous unions enabled */
#elif defined(__IAR_SYSTEMS_ICC__)
  #pragma pop
#else
  #error Not supported compiler type
#endif


#ifdef CMSIS_BITPOSITIONS
// ------------------------------------------------------------------------------------------------
// -----                                  SCT Position & Mask                                 -----
// ------------------------------------------------------------------------------------------------


// ---------------------------------------  SCT_CONFIG  -------------------------------------------
#define SCT_CONFIG_UNIFY_Pos                                  0                                                         /*!< SCT CONFIG: UNIFY Position          */
#define SCT_CONFIG_UNIFY_Msk                                  (0x01UL << SCT_CONFIG_UNIFY_Pos)                          /*!< SCT CONFIG: UNIFY Mask              */
#define SCT_CONFIG_CLKMODE_Pos                                1                                                         /*!< SCT CONFIG: CLKMODE Position        */
#define SCT_CONFIG_CLKMODE_Msk                                (0x03UL << SCT_CONFIG_CLKMODE_Pos)                        /*!< SCT CONFIG: CLKMODE Mask            */
#define SCT_CONFIG_CLKSEL_Pos                                 3                                                         /*!< SCT CONFIG: CLKSEL Position         */
#define SCT_CONFIG_CLKSEL_Msk                                 (0x0fUL << SCT_CONFIG_CLKSEL_Pos)                         /*!< SCT CONFIG: CLKSEL Mask             */
#define SCT_CONFIG_NORELAODL_NORELOADU_Pos                    7                                                         /*!< SCT CONFIG: NORELAODL_NORELOADU Position */
#define SCT_CONFIG_NORELAODL_NORELOADU_Msk                    (0x01UL << SCT_CONFIG_NORELAODL_NORELOADU_Pos)            /*!< SCT CONFIG: NORELAODL_NORELOADU Mask */
#define SCT_CONFIG_NORELOADH_Pos                              8                                                         /*!< SCT CONFIG: NORELOADH Position      */
#define SCT_CONFIG_NORELOADH_Msk                              (0x01UL << SCT_CONFIG_NORELOADH_Pos)                      /*!< SCT CONFIG: NORELOADH Mask          */
#define SCT_CONFIG_INSYNCn_Pos                                9                                                         /*!< SCT CONFIG: INSYNCn Position        */
#define SCT_CONFIG_INSYNCn_Msk                                (0x000000ffUL << SCT_CONFIG_INSYNCn_Pos)                  /*!< SCT CONFIG: INSYNCn Mask            */

// ----------------------------------------  SCT_CTRL  --------------------------------------------
#define SCT_CTRL_DOWN_L_Pos                                   0                                                         /*!< SCT CTRL: DOWN_L Position           */
#define SCT_CTRL_DOWN_L_Msk                                   (0x01UL << SCT_CTRL_DOWN_L_Pos)                           /*!< SCT CTRL: DOWN_L Mask               */
#define SCT_CTRL_STOP_L_Pos                                   1                                                         /*!< SCT CTRL: STOP_L Position           */
#define SCT_CTRL_STOP_L_Msk                                   (0x01UL << SCT_CTRL_STOP_L_Pos)                           /*!< SCT CTRL: STOP_L Mask               */
#define SCT_CTRL_HALT_L_Pos                                   2                                                         /*!< SCT CTRL: HALT_L Position           */
#define SCT_CTRL_HALT_L_Msk                                   (0x01UL << SCT_CTRL_HALT_L_Pos)                           /*!< SCT CTRL: HALT_L Mask               */
#define SCT_CTRL_CLRCTR_L_Pos                                 3                                                         /*!< SCT CTRL: CLRCTR_L Position         */
#define SCT_CTRL_CLRCTR_L_Msk                                 (0x01UL << SCT_CTRL_CLRCTR_L_Pos)                         /*!< SCT CTRL: CLRCTR_L Mask             */
#define SCT_CTRL_BIDIR_L_Pos                                  4                                                         /*!< SCT CTRL: BIDIR_L Position          */
#define SCT_CTRL_BIDIR_L_Msk                                  (0x01UL << SCT_CTRL_BIDIR_L_Pos)                          /*!< SCT CTRL: BIDIR_L Mask              */
#define SCT_CTRL_PRE_L_Pos                                    5                                                         /*!< SCT CTRL: PRE_L Position            */
#define SCT_CTRL_PRE_L_Msk                                    (0x000000ffUL << SCT_CTRL_PRE_L_Pos)                      /*!< SCT CTRL: PRE_L Mask                */
#define SCT_CTRL_DOWN_H_Pos                                   16                                                        /*!< SCT CTRL: DOWN_H Position           */
#define SCT_CTRL_DOWN_H_Msk                                   (0x01UL << SCT_CTRL_DOWN_H_Pos)                           /*!< SCT CTRL: DOWN_H Mask               */
#define SCT_CTRL_STOP_H_Pos                                   17                                                        /*!< SCT CTRL: STOP_H Position           */
#define SCT_CTRL_STOP_H_Msk                                   (0x01UL << SCT_CTRL_STOP_H_Pos)                           /*!< SCT CTRL: STOP_H Mask               */
#define SCT_CTRL_HALT_H_Pos                                   18                                                        /*!< SCT CTRL: HALT_H Position           */
#define SCT_CTRL_HALT_H_Msk                                   (0x01UL << SCT_CTRL_HALT_H_Pos)                           /*!< SCT CTRL: HALT_H Mask               */
#define SCT_CTRL_CLRCTR_H_Pos                                 19                                                        /*!< SCT CTRL: CLRCTR_H Position         */
#define SCT_CTRL_CLRCTR_H_Msk                                 (0x01UL << SCT_CTRL_CLRCTR_H_Pos)                         /*!< SCT CTRL: CLRCTR_H Mask             */
#define SCT_CTRL_BIDIR_H_Pos                                  20                                                        /*!< SCT CTRL: BIDIR_H Position          */
#define SCT_CTRL_BIDIR_H_Msk                                  (0x01UL << SCT_CTRL_BIDIR_H_Pos)                          /*!< SCT CTRL: BIDIR_H Mask              */
#define SCT_CTRL_PRE_H_Pos                                    21                                                        /*!< SCT CTRL: PRE_H Position            */
#define SCT_CTRL_PRE_H_Msk                                    (0x000000ffUL << SCT_CTRL_PRE_H_Pos)                      /*!< SCT CTRL: PRE_H Mask                */

// ----------------------------------------  SCT_LIMIT  -------------------------------------------
#define SCT_LIMIT_LIMMSK_L_Pos                                0                                                         /*!< SCT LIMIT: LIMMSK_L Position        */
#define SCT_LIMIT_LIMMSK_L_Msk                                (0x0000ffffUL << SCT_LIMIT_LIMMSK_L_Pos)                  /*!< SCT LIMIT: LIMMSK_L Mask            */
#define SCT_LIMIT_LIMMSK_H_Pos                                16                                                        /*!< SCT LIMIT: LIMMSK_H Position        */
#define SCT_LIMIT_LIMMSK_H_Msk                                (0x0000ffffUL << SCT_LIMIT_LIMMSK_H_Pos)                  /*!< SCT LIMIT: LIMMSK_H Mask            */

// ----------------------------------------  SCT_HALT  --------------------------------------------
#define SCT_HALT_HALTMSK_L_Pos                                0                                                         /*!< SCT HALT: HALTMSK_L Position        */
#define SCT_HALT_HALTMSK_L_Msk                                (0x0000ffffUL << SCT_HALT_HALTMSK_L_Pos)                  /*!< SCT HALT: HALTMSK_L Mask            */
#define SCT_HALT_HALTMSK_H_Pos                                16                                                        /*!< SCT HALT: HALTMSK_H Position        */
#define SCT_HALT_HALTMSK_H_Msk                                (0x0000ffffUL << SCT_HALT_HALTMSK_H_Pos)                  /*!< SCT HALT: HALTMSK_H Mask            */

// ----------------------------------------  SCT_STOP  --------------------------------------------
#define SCT_STOP_STOPMSK_L_Pos                                0                                                         /*!< SCT STOP: STOPMSK_L Position        */
#define SCT_STOP_STOPMSK_L_Msk                                (0x0000ffffUL << SCT_STOP_STOPMSK_L_Pos)                  /*!< SCT STOP: STOPMSK_L Mask            */
#define SCT_STOP_STOPMSK_H_Pos                                16                                                        /*!< SCT STOP: STOPMSK_H Position        */
#define SCT_STOP_STOPMSK_H_Msk                                (0x0000ffffUL << SCT_STOP_STOPMSK_H_Pos)                  /*!< SCT STOP: STOPMSK_H Mask            */

// ----------------------------------------  SCT_START  -------------------------------------------
#define SCT_START_STARTMSK_L_Pos                              0                                                         /*!< SCT START: STARTMSK_L Position      */
#define SCT_START_STARTMSK_L_Msk                              (0x0000ffffUL << SCT_START_STARTMSK_L_Pos)                /*!< SCT START: STARTMSK_L Mask          */
#define SCT_START_STARTMSK_H_Pos                              16                                                        /*!< SCT START: STARTMSK_H Position      */
#define SCT_START_STARTMSK_H_Msk                              (0x0000ffffUL << SCT_START_STARTMSK_H_Pos)                /*!< SCT START: STARTMSK_H Mask          */

// ----------------------------------------  SCT_COUNT  -------------------------------------------
#define SCT_COUNT_CTR_L_Pos                                   0                                                         /*!< SCT COUNT: CTR_L Position           */
#define SCT_COUNT_CTR_L_Msk                                   (0x0000ffffUL << SCT_COUNT_CTR_L_Pos)                     /*!< SCT COUNT: CTR_L Mask               */
#define SCT_COUNT_CTR_H_Pos                                   16                                                        /*!< SCT COUNT: CTR_H Position           */
#define SCT_COUNT_CTR_H_Msk                                   (0x0000ffffUL << SCT_COUNT_CTR_H_Pos)                     /*!< SCT COUNT: CTR_H Mask               */

// ----------------------------------------  SCT_STATE  -------------------------------------------
#define SCT_STATE_STATE_L_Pos                                 0                                                         /*!< SCT STATE: STATE_L Position         */
#define SCT_STATE_STATE_L_Msk                                 (0x1fUL << SCT_STATE_STATE_L_Pos)                         /*!< SCT STATE: STATE_L Mask             */
#define SCT_STATE_STATE_H_Pos                                 16                                                        /*!< SCT STATE: STATE_H Position         */
#define SCT_STATE_STATE_H_Msk                                 (0x1fUL << SCT_STATE_STATE_H_Pos)                         /*!< SCT STATE: STATE_H Mask             */

// ----------------------------------------  SCT_INPUT  -------------------------------------------
#define SCT_INPUT_AIN0_Pos                                    0                                                         /*!< SCT INPUT: AIN0 Position            */
#define SCT_INPUT_AIN0_Msk                                    (0x01UL << SCT_INPUT_AIN0_Pos)                            /*!< SCT INPUT: AIN0 Mask                */
#define SCT_INPUT_AIN1_Pos                                    1                                                         /*!< SCT INPUT: AIN1 Position            */
#define SCT_INPUT_AIN1_Msk                                    (0x01UL << SCT_INPUT_AIN1_Pos)                            /*!< SCT INPUT: AIN1 Mask                */
#define SCT_INPUT_AIN2_Pos                                    2                                                         /*!< SCT INPUT: AIN2 Position            */
#define SCT_INPUT_AIN2_Msk                                    (0x01UL << SCT_INPUT_AIN2_Pos)                            /*!< SCT INPUT: AIN2 Mask                */
#define SCT_INPUT_AIN3_Pos                                    3                                                         /*!< SCT INPUT: AIN3 Position            */
#define SCT_INPUT_AIN3_Msk                                    (0x01UL << SCT_INPUT_AIN3_Pos)                            /*!< SCT INPUT: AIN3 Mask                */
#define SCT_INPUT_AIN4_Pos                                    4                                                         /*!< SCT INPUT: AIN4 Position            */
#define SCT_INPUT_AIN4_Msk                                    (0x01UL << SCT_INPUT_AIN4_Pos)                            /*!< SCT INPUT: AIN4 Mask                */
#define SCT_INPUT_AIN5_Pos                                    5                                                         /*!< SCT INPUT: AIN5 Position            */
#define SCT_INPUT_AIN5_Msk                                    (0x01UL << SCT_INPUT_AIN5_Pos)                            /*!< SCT INPUT: AIN5 Mask                */
#define SCT_INPUT_AIN6_Pos                                    6                                                         /*!< SCT INPUT: AIN6 Position            */
#define SCT_INPUT_AIN6_Msk                                    (0x01UL << SCT_INPUT_AIN6_Pos)                            /*!< SCT INPUT: AIN6 Mask                */
#define SCT_INPUT_AIN7_Pos                                    7                                                         /*!< SCT INPUT: AIN7 Position            */
#define SCT_INPUT_AIN7_Msk                                    (0x01UL << SCT_INPUT_AIN7_Pos)                            /*!< SCT INPUT: AIN7 Mask                */
#define SCT_INPUT_SIN0_Pos                                    16                                                        /*!< SCT INPUT: SIN0 Position            */
#define SCT_INPUT_SIN0_Msk                                    (0x01UL << SCT_INPUT_SIN0_Pos)                            /*!< SCT INPUT: SIN0 Mask                */
#define SCT_INPUT_SIN1_Pos                                    17                                                        /*!< SCT INPUT: SIN1 Position            */
#define SCT_INPUT_SIN1_Msk                                    (0x01UL << SCT_INPUT_SIN1_Pos)                            /*!< SCT INPUT: SIN1 Mask                */
#define SCT_INPUT_SIN2_Pos                                    18                                                        /*!< SCT INPUT: SIN2 Position            */
#define SCT_INPUT_SIN2_Msk                                    (0x01UL << SCT_INPUT_SIN2_Pos)                            /*!< SCT INPUT: SIN2 Mask                */
#define SCT_INPUT_SIN3_Pos                                    19                                                        /*!< SCT INPUT: SIN3 Position            */
#define SCT_INPUT_SIN3_Msk                                    (0x01UL << SCT_INPUT_SIN3_Pos)                            /*!< SCT INPUT: SIN3 Mask                */
#define SCT_INPUT_SIN4_Pos                                    20                                                        /*!< SCT INPUT: SIN4 Position            */
#define SCT_INPUT_SIN4_Msk                                    (0x01UL << SCT_INPUT_SIN4_Pos)                            /*!< SCT INPUT: SIN4 Mask                */
#define SCT_INPUT_SIN5_Pos                                    21                                                        /*!< SCT INPUT: SIN5 Position            */
#define SCT_INPUT_SIN5_Msk                                    (0x01UL << SCT_INPUT_SIN5_Pos)                            /*!< SCT INPUT: SIN5 Mask                */
#define SCT_INPUT_SIN6_Pos                                    22                                                        /*!< SCT INPUT: SIN6 Position            */
#define SCT_INPUT_SIN6_Msk                                    (0x01UL << SCT_INPUT_SIN6_Pos)                            /*!< SCT INPUT: SIN6 Mask                */
#define SCT_INPUT_SIN7_Pos                                    23                                                        /*!< SCT INPUT: SIN7 Position            */
#define SCT_INPUT_SIN7_Msk                                    (0x01UL << SCT_INPUT_SIN7_Pos)                            /*!< SCT INPUT: SIN7 Mask                */

// ---------------------------------------  SCT_REGMODE  ------------------------------------------
#define SCT_REGMODE_REGMOD_L0_Pos                             0                                                         /*!< SCT REGMODE: REGMOD_L0 Position     */
#define SCT_REGMODE_REGMOD_L0_Msk                             (0x01UL << SCT_REGMODE_REGMOD_L0_Pos)                     /*!< SCT REGMODE: REGMOD_L0 Mask         */
#define SCT_REGMODE_REGMOD_L1_Pos                             1                                                         /*!< SCT REGMODE: REGMOD_L1 Position     */
#define SCT_REGMODE_REGMOD_L1_Msk                             (0x01UL << SCT_REGMODE_REGMOD_L1_Pos)                     /*!< SCT REGMODE: REGMOD_L1 Mask         */
#define SCT_REGMODE_REGMOD_L2_Pos                             2                                                         /*!< SCT REGMODE: REGMOD_L2 Position     */
#define SCT_REGMODE_REGMOD_L2_Msk                             (0x01UL << SCT_REGMODE_REGMOD_L2_Pos)                     /*!< SCT REGMODE: REGMOD_L2 Mask         */
#define SCT_REGMODE_REGMOD_L3_Pos                             3                                                         /*!< SCT REGMODE: REGMOD_L3 Position     */
#define SCT_REGMODE_REGMOD_L3_Msk                             (0x01UL << SCT_REGMODE_REGMOD_L3_Pos)                     /*!< SCT REGMODE: REGMOD_L3 Mask         */
#define SCT_REGMODE_REGMOD_L4_Pos                             4                                                         /*!< SCT REGMODE: REGMOD_L4 Position     */
#define SCT_REGMODE_REGMOD_L4_Msk                             (0x01UL << SCT_REGMODE_REGMOD_L4_Pos)                     /*!< SCT REGMODE: REGMOD_L4 Mask         */
#define SCT_REGMODE_REGMOD_L5_Pos                             5                                                         /*!< SCT REGMODE: REGMOD_L5 Position     */
#define SCT_REGMODE_REGMOD_L5_Msk                             (0x01UL << SCT_REGMODE_REGMOD_L5_Pos)                     /*!< SCT REGMODE: REGMOD_L5 Mask         */
#define SCT_REGMODE_REGMOD_L6_Pos                             6                                                         /*!< SCT REGMODE: REGMOD_L6 Position     */
#define SCT_REGMODE_REGMOD_L6_Msk                             (0x01UL << SCT_REGMODE_REGMOD_L6_Pos)                     /*!< SCT REGMODE: REGMOD_L6 Mask         */
#define SCT_REGMODE_REGMOD_L7_Pos                             7                                                         /*!< SCT REGMODE: REGMOD_L7 Position     */
#define SCT_REGMODE_REGMOD_L7_Msk                             (0x01UL << SCT_REGMODE_REGMOD_L7_Pos)                     /*!< SCT REGMODE: REGMOD_L7 Mask         */
#define SCT_REGMODE_REGMOD_L8_Pos                             8                                                         /*!< SCT REGMODE: REGMOD_L8 Position     */
#define SCT_REGMODE_REGMOD_L8_Msk                             (0x01UL << SCT_REGMODE_REGMOD_L8_Pos)                     /*!< SCT REGMODE: REGMOD_L8 Mask         */
#define SCT_REGMODE_REGMOD_L9_Pos                             9                                                         /*!< SCT REGMODE: REGMOD_L9 Position     */
#define SCT_REGMODE_REGMOD_L9_Msk                             (0x01UL << SCT_REGMODE_REGMOD_L9_Pos)                     /*!< SCT REGMODE: REGMOD_L9 Mask         */
#define SCT_REGMODE_REGMOD_L10_Pos                            10                                                        /*!< SCT REGMODE: REGMOD_L10 Position    */
#define SCT_REGMODE_REGMOD_L10_Msk                            (0x01UL << SCT_REGMODE_REGMOD_L10_Pos)                    /*!< SCT REGMODE: REGMOD_L10 Mask        */
#define SCT_REGMODE_REGMOD_L11_Pos                            11                                                        /*!< SCT REGMODE: REGMOD_L11 Position    */
#define SCT_REGMODE_REGMOD_L11_Msk                            (0x01UL << SCT_REGMODE_REGMOD_L11_Pos)                    /*!< SCT REGMODE: REGMOD_L11 Mask        */
#define SCT_REGMODE_REGMOD_L12_Pos                            12                                                        /*!< SCT REGMODE: REGMOD_L12 Position    */
#define SCT_REGMODE_REGMOD_L12_Msk                            (0x01UL << SCT_REGMODE_REGMOD_L12_Pos)                    /*!< SCT REGMODE: REGMOD_L12 Mask        */
#define SCT_REGMODE_REGMOD_L13_Pos                            13                                                        /*!< SCT REGMODE: REGMOD_L13 Position    */
#define SCT_REGMODE_REGMOD_L13_Msk                            (0x01UL << SCT_REGMODE_REGMOD_L13_Pos)                    /*!< SCT REGMODE: REGMOD_L13 Mask        */
#define SCT_REGMODE_REGMOD_L14_Pos                            14                                                        /*!< SCT REGMODE: REGMOD_L14 Position    */
#define SCT_REGMODE_REGMOD_L14_Msk                            (0x01UL << SCT_REGMODE_REGMOD_L14_Pos)                    /*!< SCT REGMODE: REGMOD_L14 Mask        */
#define SCT_REGMODE_REGMOD_L15_Pos                            15                                                        /*!< SCT REGMODE: REGMOD_L15 Position    */
#define SCT_REGMODE_REGMOD_L15_Msk                            (0x01UL << SCT_REGMODE_REGMOD_L15_Pos)                    /*!< SCT REGMODE: REGMOD_L15 Mask        */
#define SCT_REGMODE_REGMOD_H16_Pos                            16                                                        /*!< SCT REGMODE: REGMOD_H16 Position    */
#define SCT_REGMODE_REGMOD_H16_Msk                            (0x01UL << SCT_REGMODE_REGMOD_H16_Pos)                    /*!< SCT REGMODE: REGMOD_H16 Mask        */
#define SCT_REGMODE_REGMOD_H17_Pos                            17                                                        /*!< SCT REGMODE: REGMOD_H17 Position    */
#define SCT_REGMODE_REGMOD_H17_Msk                            (0x01UL << SCT_REGMODE_REGMOD_H17_Pos)                    /*!< SCT REGMODE: REGMOD_H17 Mask        */
#define SCT_REGMODE_REGMOD_H18_Pos                            18                                                        /*!< SCT REGMODE: REGMOD_H18 Position    */
#define SCT_REGMODE_REGMOD_H18_Msk                            (0x01UL << SCT_REGMODE_REGMOD_H18_Pos)                    /*!< SCT REGMODE: REGMOD_H18 Mask        */
#define SCT_REGMODE_REGMOD_H19_Pos                            19                                                        /*!< SCT REGMODE: REGMOD_H19 Position    */
#define SCT_REGMODE_REGMOD_H19_Msk                            (0x01UL << SCT_REGMODE_REGMOD_H19_Pos)                    /*!< SCT REGMODE: REGMOD_H19 Mask        */
#define SCT_REGMODE_REGMOD_H20_Pos                            20                                                        /*!< SCT REGMODE: REGMOD_H20 Position    */
#define SCT_REGMODE_REGMOD_H20_Msk                            (0x01UL << SCT_REGMODE_REGMOD_H20_Pos)                    /*!< SCT REGMODE: REGMOD_H20 Mask        */
#define SCT_REGMODE_REGMOD_H21_Pos                            21                                                        /*!< SCT REGMODE: REGMOD_H21 Position    */
#define SCT_REGMODE_REGMOD_H21_Msk                            (0x01UL << SCT_REGMODE_REGMOD_H21_Pos)                    /*!< SCT REGMODE: REGMOD_H21 Mask        */
#define SCT_REGMODE_REGMOD_H22_Pos                            22                                                        /*!< SCT REGMODE: REGMOD_H22 Position    */
#define SCT_REGMODE_REGMOD_H22_Msk                            (0x01UL << SCT_REGMODE_REGMOD_H22_Pos)                    /*!< SCT REGMODE: REGMOD_H22 Mask        */
#define SCT_REGMODE_REGMOD_H23_Pos                            23                                                        /*!< SCT REGMODE: REGMOD_H23 Position    */
#define SCT_REGMODE_REGMOD_H23_Msk                            (0x01UL << SCT_REGMODE_REGMOD_H23_Pos)                    /*!< SCT REGMODE: REGMOD_H23 Mask        */
#define SCT_REGMODE_REGMOD_H24_Pos                            24                                                        /*!< SCT REGMODE: REGMOD_H24 Position    */
#define SCT_REGMODE_REGMOD_H24_Msk                            (0x01UL << SCT_REGMODE_REGMOD_H24_Pos)                    /*!< SCT REGMODE: REGMOD_H24 Mask        */
#define SCT_REGMODE_REGMOD_H25_Pos                            25                                                        /*!< SCT REGMODE: REGMOD_H25 Position    */
#define SCT_REGMODE_REGMOD_H25_Msk                            (0x01UL << SCT_REGMODE_REGMOD_H25_Pos)                    /*!< SCT REGMODE: REGMOD_H25 Mask        */
#define SCT_REGMODE_REGMOD_H26_Pos                            26                                                        /*!< SCT REGMODE: REGMOD_H26 Position    */
#define SCT_REGMODE_REGMOD_H26_Msk                            (0x01UL << SCT_REGMODE_REGMOD_H26_Pos)                    /*!< SCT REGMODE: REGMOD_H26 Mask        */
#define SCT_REGMODE_REGMOD_H27_Pos                            27                                                        /*!< SCT REGMODE: REGMOD_H27 Position    */
#define SCT_REGMODE_REGMOD_H27_Msk                            (0x01UL << SCT_REGMODE_REGMOD_H27_Pos)                    /*!< SCT REGMODE: REGMOD_H27 Mask        */
#define SCT_REGMODE_REGMOD_H28_Pos                            28                                                        /*!< SCT REGMODE: REGMOD_H28 Position    */
#define SCT_REGMODE_REGMOD_H28_Msk                            (0x01UL << SCT_REGMODE_REGMOD_H28_Pos)                    /*!< SCT REGMODE: REGMOD_H28 Mask        */
#define SCT_REGMODE_REGMOD_H29_Pos                            29                                                        /*!< SCT REGMODE: REGMOD_H29 Position    */
#define SCT_REGMODE_REGMOD_H29_Msk                            (0x01UL << SCT_REGMODE_REGMOD_H29_Pos)                    /*!< SCT REGMODE: REGMOD_H29 Mask        */
#define SCT_REGMODE_REGMOD_H30_Pos                            30                                                        /*!< SCT REGMODE: REGMOD_H30 Position    */
#define SCT_REGMODE_REGMOD_H30_Msk                            (0x01UL << SCT_REGMODE_REGMOD_H30_Pos)                    /*!< SCT REGMODE: REGMOD_H30 Mask        */
#define SCT_REGMODE_REGMOD_H31_Pos                            31                                                        /*!< SCT REGMODE: REGMOD_H31 Position    */
#define SCT_REGMODE_REGMOD_H31_Msk                            (0x01UL << SCT_REGMODE_REGMOD_H31_Pos)                    /*!< SCT REGMODE: REGMOD_H31 Mask        */

// ---------------------------------------  SCT_OUTPUT  -------------------------------------------
#define SCT_OUTPUT_OUT0_Pos                                   0                                                         /*!< SCT OUTPUT: OUT0 Position           */
#define SCT_OUTPUT_OUT0_Msk                                   (0x01UL << SCT_OUTPUT_OUT0_Pos)                           /*!< SCT OUTPUT: OUT0 Mask               */
#define SCT_OUTPUT_OUT1_Pos                                   1                                                         /*!< SCT OUTPUT: OUT1 Position           */
#define SCT_OUTPUT_OUT1_Msk                                   (0x01UL << SCT_OUTPUT_OUT1_Pos)                           /*!< SCT OUTPUT: OUT1 Mask               */
#define SCT_OUTPUT_OUT2_Pos                                   2                                                         /*!< SCT OUTPUT: OUT2 Position           */
#define SCT_OUTPUT_OUT2_Msk                                   (0x01UL << SCT_OUTPUT_OUT2_Pos)                           /*!< SCT OUTPUT: OUT2 Mask               */
#define SCT_OUTPUT_OUT3_Pos                                   3                                                         /*!< SCT OUTPUT: OUT3 Position           */
#define SCT_OUTPUT_OUT3_Msk                                   (0x01UL << SCT_OUTPUT_OUT3_Pos)                           /*!< SCT OUTPUT: OUT3 Mask               */
#define SCT_OUTPUT_OUT4_Pos                                   4                                                         /*!< SCT OUTPUT: OUT4 Position           */
#define SCT_OUTPUT_OUT4_Msk                                   (0x01UL << SCT_OUTPUT_OUT4_Pos)                           /*!< SCT OUTPUT: OUT4 Mask               */
#define SCT_OUTPUT_OUT5_Pos                                   5                                                         /*!< SCT OUTPUT: OUT5 Position           */
#define SCT_OUTPUT_OUT5_Msk                                   (0x01UL << SCT_OUTPUT_OUT5_Pos)                           /*!< SCT OUTPUT: OUT5 Mask               */
#define SCT_OUTPUT_OUT6_Pos                                   6                                                         /*!< SCT OUTPUT: OUT6 Position           */
#define SCT_OUTPUT_OUT6_Msk                                   (0x01UL << SCT_OUTPUT_OUT6_Pos)                           /*!< SCT OUTPUT: OUT6 Mask               */
#define SCT_OUTPUT_OUT7_Pos                                   7                                                         /*!< SCT OUTPUT: OUT7 Position           */
#define SCT_OUTPUT_OUT7_Msk                                   (0x01UL << SCT_OUTPUT_OUT7_Pos)                           /*!< SCT OUTPUT: OUT7 Mask               */
#define SCT_OUTPUT_OUT8_Pos                                   8                                                         /*!< SCT OUTPUT: OUT8 Position           */
#define SCT_OUTPUT_OUT8_Msk                                   (0x01UL << SCT_OUTPUT_OUT8_Pos)                           /*!< SCT OUTPUT: OUT8 Mask               */
#define SCT_OUTPUT_OUT9_Pos                                   9                                                         /*!< SCT OUTPUT: OUT9 Position           */
#define SCT_OUTPUT_OUT9_Msk                                   (0x01UL << SCT_OUTPUT_OUT9_Pos)                           /*!< SCT OUTPUT: OUT9 Mask               */
#define SCT_OUTPUT_OUT10_Pos                                  10                                                        /*!< SCT OUTPUT: OUT10 Position          */
#define SCT_OUTPUT_OUT10_Msk                                  (0x01UL << SCT_OUTPUT_OUT10_Pos)                          /*!< SCT OUTPUT: OUT10 Mask              */
#define SCT_OUTPUT_OUT11_Pos                                  11                                                        /*!< SCT OUTPUT: OUT11 Position          */
#define SCT_OUTPUT_OUT11_Msk                                  (0x01UL << SCT_OUTPUT_OUT11_Pos)                          /*!< SCT OUTPUT: OUT11 Mask              */
#define SCT_OUTPUT_OUT12_Pos                                  12                                                        /*!< SCT OUTPUT: OUT12 Position          */
#define SCT_OUTPUT_OUT12_Msk                                  (0x01UL << SCT_OUTPUT_OUT12_Pos)                          /*!< SCT OUTPUT: OUT12 Mask              */
#define SCT_OUTPUT_OUT13_Pos                                  13                                                        /*!< SCT OUTPUT: OUT13 Position          */
#define SCT_OUTPUT_OUT13_Msk                                  (0x01UL << SCT_OUTPUT_OUT13_Pos)                          /*!< SCT OUTPUT: OUT13 Mask              */
#define SCT_OUTPUT_OUT14_Pos                                  14                                                        /*!< SCT OUTPUT: OUT14 Position          */
#define SCT_OUTPUT_OUT14_Msk                                  (0x01UL << SCT_OUTPUT_OUT14_Pos)                          /*!< SCT OUTPUT: OUT14 Mask              */
#define SCT_OUTPUT_OUT15_Pos                                  15                                                        /*!< SCT OUTPUT: OUT15 Position          */
#define SCT_OUTPUT_OUT15_Msk                                  (0x01UL << SCT_OUTPUT_OUT15_Pos)                          /*!< SCT OUTPUT: OUT15 Mask              */

// ------------------------------------  SCT_OUTPUTDIRCTRL  ---------------------------------------
#define SCT_OUTPUTDIRCTRL_SETCLR0_Pos                         0                                                         /*!< SCT OUTPUTDIRCTRL: SETCLR0 Position */
#define SCT_OUTPUTDIRCTRL_SETCLR0_Msk                         (0x03UL << SCT_OUTPUTDIRCTRL_SETCLR0_Pos)                 /*!< SCT OUTPUTDIRCTRL: SETCLR0 Mask     */
#define SCT_OUTPUTDIRCTRL_SETCLR1_Pos                         2                                                         /*!< SCT OUTPUTDIRCTRL: SETCLR1 Position */
#define SCT_OUTPUTDIRCTRL_SETCLR1_Msk                         (0x03UL << SCT_OUTPUTDIRCTRL_SETCLR1_Pos)                 /*!< SCT OUTPUTDIRCTRL: SETCLR1 Mask     */
#define SCT_OUTPUTDIRCTRL_SETCLR2_Pos                         4                                                         /*!< SCT OUTPUTDIRCTRL: SETCLR2 Position */
#define SCT_OUTPUTDIRCTRL_SETCLR2_Msk                         (0x03UL << SCT_OUTPUTDIRCTRL_SETCLR2_Pos)                 /*!< SCT OUTPUTDIRCTRL: SETCLR2 Mask     */
#define SCT_OUTPUTDIRCTRL_SETCLR3_Pos                         6                                                         /*!< SCT OUTPUTDIRCTRL: SETCLR3 Position */
#define SCT_OUTPUTDIRCTRL_SETCLR3_Msk                         (0x03UL << SCT_OUTPUTDIRCTRL_SETCLR3_Pos)                 /*!< SCT OUTPUTDIRCTRL: SETCLR3 Mask     */
#define SCT_OUTPUTDIRCTRL_SETCLR4_Pos                         8                                                         /*!< SCT OUTPUTDIRCTRL: SETCLR4 Position */
#define SCT_OUTPUTDIRCTRL_SETCLR4_Msk                         (0x03UL << SCT_OUTPUTDIRCTRL_SETCLR4_Pos)                 /*!< SCT OUTPUTDIRCTRL: SETCLR4 Mask     */
#define SCT_OUTPUTDIRCTRL_SETCLR5_Pos                         10                                                        /*!< SCT OUTPUTDIRCTRL: SETCLR5 Position */
#define SCT_OUTPUTDIRCTRL_SETCLR5_Msk                         (0x03UL << SCT_OUTPUTDIRCTRL_SETCLR5_Pos)                 /*!< SCT OUTPUTDIRCTRL: SETCLR5 Mask     */
#define SCT_OUTPUTDIRCTRL_SETCLR6_Pos                         12                                                        /*!< SCT OUTPUTDIRCTRL: SETCLR6 Position */
#define SCT_OUTPUTDIRCTRL_SETCLR6_Msk                         (0x03UL << SCT_OUTPUTDIRCTRL_SETCLR6_Pos)                 /*!< SCT OUTPUTDIRCTRL: SETCLR6 Mask     */
#define SCT_OUTPUTDIRCTRL_SETCLR7_Pos                         14                                                        /*!< SCT OUTPUTDIRCTRL: SETCLR7 Position */
#define SCT_OUTPUTDIRCTRL_SETCLR7_Msk                         (0x03UL << SCT_OUTPUTDIRCTRL_SETCLR7_Pos)                 /*!< SCT OUTPUTDIRCTRL: SETCLR7 Mask     */
#define SCT_OUTPUTDIRCTRL_SETCLR8_Pos                         16                                                        /*!< SCT OUTPUTDIRCTRL: SETCLR8 Position */
#define SCT_OUTPUTDIRCTRL_SETCLR8_Msk                         (0x03UL << SCT_OUTPUTDIRCTRL_SETCLR8_Pos)                 /*!< SCT OUTPUTDIRCTRL: SETCLR8 Mask     */
#define SCT_OUTPUTDIRCTRL_SETCLR9_Pos                         18                                                        /*!< SCT OUTPUTDIRCTRL: SETCLR9 Position */
#define SCT_OUTPUTDIRCTRL_SETCLR9_Msk                         (0x03UL << SCT_OUTPUTDIRCTRL_SETCLR9_Pos)                 /*!< SCT OUTPUTDIRCTRL: SETCLR9 Mask     */
#define SCT_OUTPUTDIRCTRL_SETCLR10_Pos                        20                                                        /*!< SCT OUTPUTDIRCTRL: SETCLR10 Position */
#define SCT_OUTPUTDIRCTRL_SETCLR10_Msk                        (0x03UL << SCT_OUTPUTDIRCTRL_SETCLR10_Pos)                /*!< SCT OUTPUTDIRCTRL: SETCLR10 Mask    */
#define SCT_OUTPUTDIRCTRL_SETCLR11_Pos                        22                                                        /*!< SCT OUTPUTDIRCTRL: SETCLR11 Position */
#define SCT_OUTPUTDIRCTRL_SETCLR11_Msk                        (0x03UL << SCT_OUTPUTDIRCTRL_SETCLR11_Pos)                /*!< SCT OUTPUTDIRCTRL: SETCLR11 Mask    */
#define SCT_OUTPUTDIRCTRL_SETCLR12_Pos                        24                                                        /*!< SCT OUTPUTDIRCTRL: SETCLR12 Position */
#define SCT_OUTPUTDIRCTRL_SETCLR12_Msk                        (0x03UL << SCT_OUTPUTDIRCTRL_SETCLR12_Pos)                /*!< SCT OUTPUTDIRCTRL: SETCLR12 Mask    */
#define SCT_OUTPUTDIRCTRL_SETCLR13_Pos                        26                                                        /*!< SCT OUTPUTDIRCTRL: SETCLR13 Position */
#define SCT_OUTPUTDIRCTRL_SETCLR13_Msk                        (0x03UL << SCT_OUTPUTDIRCTRL_SETCLR13_Pos)                /*!< SCT OUTPUTDIRCTRL: SETCLR13 Mask    */
#define SCT_OUTPUTDIRCTRL_SETCLR14_Pos                        28                                                        /*!< SCT OUTPUTDIRCTRL: SETCLR14 Position */
#define SCT_OUTPUTDIRCTRL_SETCLR14_Msk                        (0x03UL << SCT_OUTPUTDIRCTRL_SETCLR14_Pos)                /*!< SCT OUTPUTDIRCTRL: SETCLR14 Mask    */
#define SCT_OUTPUTDIRCTRL_SETCLR15_Pos                        30                                                        /*!< SCT OUTPUTDIRCTRL: SETCLR15 Position */
#define SCT_OUTPUTDIRCTRL_SETCLR15_Msk                        (0x03UL << SCT_OUTPUTDIRCTRL_SETCLR15_Pos)                /*!< SCT OUTPUTDIRCTRL: SETCLR15 Mask    */

// -----------------------------------------  SCT_RES  --------------------------------------------
#define SCT_RES_O0RES_Pos                                     0                                                         /*!< SCT RES: O0RES Position             */
#define SCT_RES_O0RES_Msk                                     (0x03UL << SCT_RES_O0RES_Pos)                             /*!< SCT RES: O0RES Mask                 */
#define SCT_RES_O1RES_Pos                                     2                                                         /*!< SCT RES: O1RES Position             */
#define SCT_RES_O1RES_Msk                                     (0x03UL << SCT_RES_O1RES_Pos)                             /*!< SCT RES: O1RES Mask                 */
#define SCT_RES_O2RES_Pos                                     4                                                         /*!< SCT RES: O2RES Position             */
#define SCT_RES_O2RES_Msk                                     (0x03UL << SCT_RES_O2RES_Pos)                             /*!< SCT RES: O2RES Mask                 */
#define SCT_RES_O3RES_Pos                                     6                                                         /*!< SCT RES: O3RES Position             */
#define SCT_RES_O3RES_Msk                                     (0x03UL << SCT_RES_O3RES_Pos)                             /*!< SCT RES: O3RES Mask                 */
#define SCT_RES_O4RES_Pos                                     8                                                         /*!< SCT RES: O4RES Position             */
#define SCT_RES_O4RES_Msk                                     (0x03UL << SCT_RES_O4RES_Pos)                             /*!< SCT RES: O4RES Mask                 */
#define SCT_RES_O5RES_Pos                                     10                                                        /*!< SCT RES: O5RES Position             */
#define SCT_RES_O5RES_Msk                                     (0x03UL << SCT_RES_O5RES_Pos)                             /*!< SCT RES: O5RES Mask                 */
#define SCT_RES_O6RES_Pos                                     12                                                        /*!< SCT RES: O6RES Position             */
#define SCT_RES_O6RES_Msk                                     (0x03UL << SCT_RES_O6RES_Pos)                             /*!< SCT RES: O6RES Mask                 */
#define SCT_RES_O7RES_Pos                                     14                                                        /*!< SCT RES: O7RES Position             */
#define SCT_RES_O7RES_Msk                                     (0x03UL << SCT_RES_O7RES_Pos)                             /*!< SCT RES: O7RES Mask                 */
#define SCT_RES_O8RES_Pos                                     16                                                        /*!< SCT RES: O8RES Position             */
#define SCT_RES_O8RES_Msk                                     (0x03UL << SCT_RES_O8RES_Pos)                             /*!< SCT RES: O8RES Mask                 */
#define SCT_RES_O9RES_Pos                                     18                                                        /*!< SCT RES: O9RES Position             */
#define SCT_RES_O9RES_Msk                                     (0x03UL << SCT_RES_O9RES_Pos)                             /*!< SCT RES: O9RES Mask                 */
#define SCT_RES_O10RES_Pos                                    20                                                        /*!< SCT RES: O10RES Position            */
#define SCT_RES_O10RES_Msk                                    (0x03UL << SCT_RES_O10RES_Pos)                            /*!< SCT RES: O10RES Mask                */
#define SCT_RES_O11RES_Pos                                    22                                                        /*!< SCT RES: O11RES Position            */
#define SCT_RES_O11RES_Msk                                    (0x03UL << SCT_RES_O11RES_Pos)                            /*!< SCT RES: O11RES Mask                */
#define SCT_RES_O12RES_Pos                                    24                                                        /*!< SCT RES: O12RES Position            */
#define SCT_RES_O12RES_Msk                                    (0x03UL << SCT_RES_O12RES_Pos)                            /*!< SCT RES: O12RES Mask                */
#define SCT_RES_O13RES_Pos                                    26                                                        /*!< SCT RES: O13RES Position            */
#define SCT_RES_O13RES_Msk                                    (0x03UL << SCT_RES_O13RES_Pos)                            /*!< SCT RES: O13RES Mask                */
#define SCT_RES_O14RES_Pos                                    28                                                        /*!< SCT RES: O14RES Position            */
#define SCT_RES_O14RES_Msk                                    (0x03UL << SCT_RES_O14RES_Pos)                            /*!< SCT RES: O14RES Mask                */
#define SCT_RES_O15RES_Pos                                    30                                                        /*!< SCT RES: O15RES Position            */
#define SCT_RES_O15RES_Msk                                    (0x03UL << SCT_RES_O15RES_Pos)                            /*!< SCT RES: O15RES Mask                */

// ---------------------------------------  SCT_DMAREQ0  ------------------------------------------
#define SCT_DMAREQ0_DEV_0_0_Pos                               0                                                         /*!< SCT DMAREQ0: DEV_0_0 Position       */
#define SCT_DMAREQ0_DEV_0_0_Msk                               (0x01UL << SCT_DMAREQ0_DEV_0_0_Pos)                       /*!< SCT DMAREQ0: DEV_0_0 Mask           */
#define SCT_DMAREQ0_DEV_0_1_Pos                               1                                                         /*!< SCT DMAREQ0: DEV_0_1 Position       */
#define SCT_DMAREQ0_DEV_0_1_Msk                               (0x01UL << SCT_DMAREQ0_DEV_0_1_Pos)                       /*!< SCT DMAREQ0: DEV_0_1 Mask           */
#define SCT_DMAREQ0_DEV_0_2_Pos                               2                                                         /*!< SCT DMAREQ0: DEV_0_2 Position       */
#define SCT_DMAREQ0_DEV_0_2_Msk                               (0x01UL << SCT_DMAREQ0_DEV_0_2_Pos)                       /*!< SCT DMAREQ0: DEV_0_2 Mask           */
#define SCT_DMAREQ0_DEV_0_3_Pos                               3                                                         /*!< SCT DMAREQ0: DEV_0_3 Position       */
#define SCT_DMAREQ0_DEV_0_3_Msk                               (0x01UL << SCT_DMAREQ0_DEV_0_3_Pos)                       /*!< SCT DMAREQ0: DEV_0_3 Mask           */
#define SCT_DMAREQ0_DEV_0_4_Pos                               4                                                         /*!< SCT DMAREQ0: DEV_0_4 Position       */
#define SCT_DMAREQ0_DEV_0_4_Msk                               (0x01UL << SCT_DMAREQ0_DEV_0_4_Pos)                       /*!< SCT DMAREQ0: DEV_0_4 Mask           */
#define SCT_DMAREQ0_DEV_0_5_Pos                               5                                                         /*!< SCT DMAREQ0: DEV_0_5 Position       */
#define SCT_DMAREQ0_DEV_0_5_Msk                               (0x01UL << SCT_DMAREQ0_DEV_0_5_Pos)                       /*!< SCT DMAREQ0: DEV_0_5 Mask           */
#define SCT_DMAREQ0_DEV_0_6_Pos                               6                                                         /*!< SCT DMAREQ0: DEV_0_6 Position       */
#define SCT_DMAREQ0_DEV_0_6_Msk                               (0x01UL << SCT_DMAREQ0_DEV_0_6_Pos)                       /*!< SCT DMAREQ0: DEV_0_6 Mask           */
#define SCT_DMAREQ0_DEV_0_7_Pos                               7                                                         /*!< SCT DMAREQ0: DEV_0_7 Position       */
#define SCT_DMAREQ0_DEV_0_7_Msk                               (0x01UL << SCT_DMAREQ0_DEV_0_7_Pos)                       /*!< SCT DMAREQ0: DEV_0_7 Mask           */
#define SCT_DMAREQ0_DEV_0_8_Pos                               8                                                         /*!< SCT DMAREQ0: DEV_0_8 Position       */
#define SCT_DMAREQ0_DEV_0_8_Msk                               (0x01UL << SCT_DMAREQ0_DEV_0_8_Pos)                       /*!< SCT DMAREQ0: DEV_0_8 Mask           */
#define SCT_DMAREQ0_DEV_0_9_Pos                               9                                                         /*!< SCT DMAREQ0: DEV_0_9 Position       */
#define SCT_DMAREQ0_DEV_0_9_Msk                               (0x01UL << SCT_DMAREQ0_DEV_0_9_Pos)                       /*!< SCT DMAREQ0: DEV_0_9 Mask           */
#define SCT_DMAREQ0_DEV_0_10_Pos                              10                                                        /*!< SCT DMAREQ0: DEV_0_10 Position      */
#define SCT_DMAREQ0_DEV_0_10_Msk                              (0x01UL << SCT_DMAREQ0_DEV_0_10_Pos)                      /*!< SCT DMAREQ0: DEV_0_10 Mask          */
#define SCT_DMAREQ0_DEV_0_11_Pos                              11                                                        /*!< SCT DMAREQ0: DEV_0_11 Position      */
#define SCT_DMAREQ0_DEV_0_11_Msk                              (0x01UL << SCT_DMAREQ0_DEV_0_11_Pos)                      /*!< SCT DMAREQ0: DEV_0_11 Mask          */
#define SCT_DMAREQ0_DEV_0_12_Pos                              12                                                        /*!< SCT DMAREQ0: DEV_0_12 Position      */
#define SCT_DMAREQ0_DEV_0_12_Msk                              (0x01UL << SCT_DMAREQ0_DEV_0_12_Pos)                      /*!< SCT DMAREQ0: DEV_0_12 Mask          */
#define SCT_DMAREQ0_DEV_0_13_Pos                              13                                                        /*!< SCT DMAREQ0: DEV_0_13 Position      */
#define SCT_DMAREQ0_DEV_0_13_Msk                              (0x01UL << SCT_DMAREQ0_DEV_0_13_Pos)                      /*!< SCT DMAREQ0: DEV_0_13 Mask          */
#define SCT_DMAREQ0_DEV_0_14_Pos                              14                                                        /*!< SCT DMAREQ0: DEV_0_14 Position      */
#define SCT_DMAREQ0_DEV_0_14_Msk                              (0x01UL << SCT_DMAREQ0_DEV_0_14_Pos)                      /*!< SCT DMAREQ0: DEV_0_14 Mask          */
#define SCT_DMAREQ0_DEV_0_15_Pos                              15                                                        /*!< SCT DMAREQ0: DEV_0_15 Position      */
#define SCT_DMAREQ0_DEV_0_15_Msk                              (0x01UL << SCT_DMAREQ0_DEV_0_15_Pos)                      /*!< SCT DMAREQ0: DEV_0_15 Mask          */
#define SCT_DMAREQ0_DRL0_Pos                                  30                                                        /*!< SCT DMAREQ0: DRL0 Position          */
#define SCT_DMAREQ0_DRL0_Msk                                  (0x01UL << SCT_DMAREQ0_DRL0_Pos)                          /*!< SCT DMAREQ0: DRL0 Mask              */
#define SCT_DMAREQ0_DRQ0_Pos                                  31                                                        /*!< SCT DMAREQ0: DRQ0 Position          */
#define SCT_DMAREQ0_DRQ0_Msk                                  (0x01UL << SCT_DMAREQ0_DRQ0_Pos)                          /*!< SCT DMAREQ0: DRQ0 Mask              */

// ---------------------------------------  SCT_DMAREQ1  ------------------------------------------
#define SCT_DMAREQ1_DEV_1_0_Pos                               0                                                         /*!< SCT DMAREQ1: DEV_1_0 Position       */
#define SCT_DMAREQ1_DEV_1_0_Msk                               (0x01UL << SCT_DMAREQ1_DEV_1_0_Pos)                       /*!< SCT DMAREQ1: DEV_1_0 Mask           */
#define SCT_DMAREQ1_DEV_1_1_Pos                               1                                                         /*!< SCT DMAREQ1: DEV_1_1 Position       */
#define SCT_DMAREQ1_DEV_1_1_Msk                               (0x01UL << SCT_DMAREQ1_DEV_1_1_Pos)                       /*!< SCT DMAREQ1: DEV_1_1 Mask           */
#define SCT_DMAREQ1_DEV_1_2_Pos                               2                                                         /*!< SCT DMAREQ1: DEV_1_2 Position       */
#define SCT_DMAREQ1_DEV_1_2_Msk                               (0x01UL << SCT_DMAREQ1_DEV_1_2_Pos)                       /*!< SCT DMAREQ1: DEV_1_2 Mask           */
#define SCT_DMAREQ1_DEV_1_3_Pos                               3                                                         /*!< SCT DMAREQ1: DEV_1_3 Position       */
#define SCT_DMAREQ1_DEV_1_3_Msk                               (0x01UL << SCT_DMAREQ1_DEV_1_3_Pos)                       /*!< SCT DMAREQ1: DEV_1_3 Mask           */
#define SCT_DMAREQ1_DEV_1_4_Pos                               4                                                         /*!< SCT DMAREQ1: DEV_1_4 Position       */
#define SCT_DMAREQ1_DEV_1_4_Msk                               (0x01UL << SCT_DMAREQ1_DEV_1_4_Pos)                       /*!< SCT DMAREQ1: DEV_1_4 Mask           */
#define SCT_DMAREQ1_DEV_1_5_Pos                               5                                                         /*!< SCT DMAREQ1: DEV_1_5 Position       */
#define SCT_DMAREQ1_DEV_1_5_Msk                               (0x01UL << SCT_DMAREQ1_DEV_1_5_Pos)                       /*!< SCT DMAREQ1: DEV_1_5 Mask           */
#define SCT_DMAREQ1_DEV_1_6_Pos                               6                                                         /*!< SCT DMAREQ1: DEV_1_6 Position       */
#define SCT_DMAREQ1_DEV_1_6_Msk                               (0x01UL << SCT_DMAREQ1_DEV_1_6_Pos)                       /*!< SCT DMAREQ1: DEV_1_6 Mask           */
#define SCT_DMAREQ1_DEV_1_7_Pos                               7                                                         /*!< SCT DMAREQ1: DEV_1_7 Position       */
#define SCT_DMAREQ1_DEV_1_7_Msk                               (0x01UL << SCT_DMAREQ1_DEV_1_7_Pos)                       /*!< SCT DMAREQ1: DEV_1_7 Mask           */
#define SCT_DMAREQ1_DEV_1_8_Pos                               8                                                         /*!< SCT DMAREQ1: DEV_1_8 Position       */
#define SCT_DMAREQ1_DEV_1_8_Msk                               (0x01UL << SCT_DMAREQ1_DEV_1_8_Pos)                       /*!< SCT DMAREQ1: DEV_1_8 Mask           */
#define SCT_DMAREQ1_DEV_1_9_Pos                               9                                                         /*!< SCT DMAREQ1: DEV_1_9 Position       */
#define SCT_DMAREQ1_DEV_1_9_Msk                               (0x01UL << SCT_DMAREQ1_DEV_1_9_Pos)                       /*!< SCT DMAREQ1: DEV_1_9 Mask           */
#define SCT_DMAREQ1_DEV_1_10_Pos                              10                                                        /*!< SCT DMAREQ1: DEV_1_10 Position      */
#define SCT_DMAREQ1_DEV_1_10_Msk                              (0x01UL << SCT_DMAREQ1_DEV_1_10_Pos)                      /*!< SCT DMAREQ1: DEV_1_10 Mask          */
#define SCT_DMAREQ1_DEV_1_11_Pos                              11                                                        /*!< SCT DMAREQ1: DEV_1_11 Position      */
#define SCT_DMAREQ1_DEV_1_11_Msk                              (0x01UL << SCT_DMAREQ1_DEV_1_11_Pos)                      /*!< SCT DMAREQ1: DEV_1_11 Mask          */
#define SCT_DMAREQ1_DEV_1_12_Pos                              12                                                        /*!< SCT DMAREQ1: DEV_1_12 Position      */
#define SCT_DMAREQ1_DEV_1_12_Msk                              (0x01UL << SCT_DMAREQ1_DEV_1_12_Pos)                      /*!< SCT DMAREQ1: DEV_1_12 Mask          */
#define SCT_DMAREQ1_DEV_1_13_Pos                              13                                                        /*!< SCT DMAREQ1: DEV_1_13 Position      */
#define SCT_DMAREQ1_DEV_1_13_Msk                              (0x01UL << SCT_DMAREQ1_DEV_1_13_Pos)                      /*!< SCT DMAREQ1: DEV_1_13 Mask          */
#define SCT_DMAREQ1_DEV_1_14_Pos                              14                                                        /*!< SCT DMAREQ1: DEV_1_14 Position      */
#define SCT_DMAREQ1_DEV_1_14_Msk                              (0x01UL << SCT_DMAREQ1_DEV_1_14_Pos)                      /*!< SCT DMAREQ1: DEV_1_14 Mask          */
#define SCT_DMAREQ1_DEV_1_15_Pos                              15                                                        /*!< SCT DMAREQ1: DEV_1_15 Position      */
#define SCT_DMAREQ1_DEV_1_15_Msk                              (0x01UL << SCT_DMAREQ1_DEV_1_15_Pos)                      /*!< SCT DMAREQ1: DEV_1_15 Mask          */
#define SCT_DMAREQ1_DRL1_Pos                                  30                                                        /*!< SCT DMAREQ1: DRL1 Position          */
#define SCT_DMAREQ1_DRL1_Msk                                  (0x01UL << SCT_DMAREQ1_DRL1_Pos)                          /*!< SCT DMAREQ1: DRL1 Mask              */
#define SCT_DMAREQ1_DRQ1_Pos                                  31                                                        /*!< SCT DMAREQ1: DRQ1 Position          */
#define SCT_DMAREQ1_DRQ1_Msk                                  (0x01UL << SCT_DMAREQ1_DRQ1_Pos)                          /*!< SCT DMAREQ1: DRQ1 Mask              */

// ----------------------------------------  SCT_EVEN  --------------------------------------------
#define SCT_EVEN_IEN0_Pos                                     0                                                         /*!< SCT EVEN: IEN0 Position             */
#define SCT_EVEN_IEN0_Msk                                     (0x01UL << SCT_EVEN_IEN0_Pos)                             /*!< SCT EVEN: IEN0 Mask                 */
#define SCT_EVEN_IEN1_Pos                                     1                                                         /*!< SCT EVEN: IEN1 Position             */
#define SCT_EVEN_IEN1_Msk                                     (0x01UL << SCT_EVEN_IEN1_Pos)                             /*!< SCT EVEN: IEN1 Mask                 */
#define SCT_EVEN_IEN2_Pos                                     2                                                         /*!< SCT EVEN: IEN2 Position             */
#define SCT_EVEN_IEN2_Msk                                     (0x01UL << SCT_EVEN_IEN2_Pos)                             /*!< SCT EVEN: IEN2 Mask                 */
#define SCT_EVEN_IEN3_Pos                                     3                                                         /*!< SCT EVEN: IEN3 Position             */
#define SCT_EVEN_IEN3_Msk                                     (0x01UL << SCT_EVEN_IEN3_Pos)                             /*!< SCT EVEN: IEN3 Mask                 */
#define SCT_EVEN_IEN4_Pos                                     4                                                         /*!< SCT EVEN: IEN4 Position             */
#define SCT_EVEN_IEN4_Msk                                     (0x01UL << SCT_EVEN_IEN4_Pos)                             /*!< SCT EVEN: IEN4 Mask                 */
#define SCT_EVEN_IEN5_Pos                                     5                                                         /*!< SCT EVEN: IEN5 Position             */
#define SCT_EVEN_IEN5_Msk                                     (0x01UL << SCT_EVEN_IEN5_Pos)                             /*!< SCT EVEN: IEN5 Mask                 */
#define SCT_EVEN_IEN6_Pos                                     6                                                         /*!< SCT EVEN: IEN6 Position             */
#define SCT_EVEN_IEN6_Msk                                     (0x01UL << SCT_EVEN_IEN6_Pos)                             /*!< SCT EVEN: IEN6 Mask                 */
#define SCT_EVEN_IEN7_Pos                                     7                                                         /*!< SCT EVEN: IEN7 Position             */
#define SCT_EVEN_IEN7_Msk                                     (0x01UL << SCT_EVEN_IEN7_Pos)                             /*!< SCT EVEN: IEN7 Mask                 */
#define SCT_EVEN_IEN8_Pos                                     8                                                         /*!< SCT EVEN: IEN8 Position             */
#define SCT_EVEN_IEN8_Msk                                     (0x01UL << SCT_EVEN_IEN8_Pos)                             /*!< SCT EVEN: IEN8 Mask                 */
#define SCT_EVEN_IEN9_Pos                                     9                                                         /*!< SCT EVEN: IEN9 Position             */
#define SCT_EVEN_IEN9_Msk                                     (0x01UL << SCT_EVEN_IEN9_Pos)                             /*!< SCT EVEN: IEN9 Mask                 */
#define SCT_EVEN_IEN10_Pos                                    10                                                        /*!< SCT EVEN: IEN10 Position            */
#define SCT_EVEN_IEN10_Msk                                    (0x01UL << SCT_EVEN_IEN10_Pos)                            /*!< SCT EVEN: IEN10 Mask                */
#define SCT_EVEN_IEN11_Pos                                    11                                                        /*!< SCT EVEN: IEN11 Position            */
#define SCT_EVEN_IEN11_Msk                                    (0x01UL << SCT_EVEN_IEN11_Pos)                            /*!< SCT EVEN: IEN11 Mask                */
#define SCT_EVEN_IEN12_Pos                                    12                                                        /*!< SCT EVEN: IEN12 Position            */
#define SCT_EVEN_IEN12_Msk                                    (0x01UL << SCT_EVEN_IEN12_Pos)                            /*!< SCT EVEN: IEN12 Mask                */
#define SCT_EVEN_IEN13_Pos                                    13                                                        /*!< SCT EVEN: IEN13 Position            */
#define SCT_EVEN_IEN13_Msk                                    (0x01UL << SCT_EVEN_IEN13_Pos)                            /*!< SCT EVEN: IEN13 Mask                */
#define SCT_EVEN_IEN14_Pos                                    14                                                        /*!< SCT EVEN: IEN14 Position            */
#define SCT_EVEN_IEN14_Msk                                    (0x01UL << SCT_EVEN_IEN14_Pos)                            /*!< SCT EVEN: IEN14 Mask                */
#define SCT_EVEN_IEN15_Pos                                    15                                                        /*!< SCT EVEN: IEN15 Position            */
#define SCT_EVEN_IEN15_Msk                                    (0x01UL << SCT_EVEN_IEN15_Pos)                            /*!< SCT EVEN: IEN15 Mask                */

// ---------------------------------------  SCT_EVFLAG  -------------------------------------------
#define SCT_EVFLAG_FLAG0_Pos                                  0                                                         /*!< SCT EVFLAG: FLAG0 Position          */
#define SCT_EVFLAG_FLAG0_Msk                                  (0x01UL << SCT_EVFLAG_FLAG0_Pos)                          /*!< SCT EVFLAG: FLAG0 Mask              */
#define SCT_EVFLAG_FLAG1_Pos                                  1                                                         /*!< SCT EVFLAG: FLAG1 Position          */
#define SCT_EVFLAG_FLAG1_Msk                                  (0x01UL << SCT_EVFLAG_FLAG1_Pos)                          /*!< SCT EVFLAG: FLAG1 Mask              */
#define SCT_EVFLAG_FLAG2_Pos                                  2                                                         /*!< SCT EVFLAG: FLAG2 Position          */
#define SCT_EVFLAG_FLAG2_Msk                                  (0x01UL << SCT_EVFLAG_FLAG2_Pos)                          /*!< SCT EVFLAG: FLAG2 Mask              */
#define SCT_EVFLAG_FLAG3_Pos                                  3                                                         /*!< SCT EVFLAG: FLAG3 Position          */
#define SCT_EVFLAG_FLAG3_Msk                                  (0x01UL << SCT_EVFLAG_FLAG3_Pos)                          /*!< SCT EVFLAG: FLAG3 Mask              */
#define SCT_EVFLAG_FLAG4_Pos                                  4                                                         /*!< SCT EVFLAG: FLAG4 Position          */
#define SCT_EVFLAG_FLAG4_Msk                                  (0x01UL << SCT_EVFLAG_FLAG4_Pos)                          /*!< SCT EVFLAG: FLAG4 Mask              */
#define SCT_EVFLAG_FLAG5_Pos                                  5                                                         /*!< SCT EVFLAG: FLAG5 Position          */
#define SCT_EVFLAG_FLAG5_Msk                                  (0x01UL << SCT_EVFLAG_FLAG5_Pos)                          /*!< SCT EVFLAG: FLAG5 Mask              */
#define SCT_EVFLAG_FLAG6_Pos                                  6                                                         /*!< SCT EVFLAG: FLAG6 Position          */
#define SCT_EVFLAG_FLAG6_Msk                                  (0x01UL << SCT_EVFLAG_FLAG6_Pos)                          /*!< SCT EVFLAG: FLAG6 Mask              */
#define SCT_EVFLAG_FLAG7_Pos                                  7                                                         /*!< SCT EVFLAG: FLAG7 Position          */
#define SCT_EVFLAG_FLAG7_Msk                                  (0x01UL << SCT_EVFLAG_FLAG7_Pos)                          /*!< SCT EVFLAG: FLAG7 Mask              */
#define SCT_EVFLAG_FLAG8_Pos                                  8                                                         /*!< SCT EVFLAG: FLAG8 Position          */
#define SCT_EVFLAG_FLAG8_Msk                                  (0x01UL << SCT_EVFLAG_FLAG8_Pos)                          /*!< SCT EVFLAG: FLAG8 Mask              */
#define SCT_EVFLAG_FLAG9_Pos                                  9                                                         /*!< SCT EVFLAG: FLAG9 Position          */
#define SCT_EVFLAG_FLAG9_Msk                                  (0x01UL << SCT_EVFLAG_FLAG9_Pos)                          /*!< SCT EVFLAG: FLAG9 Mask              */
#define SCT_EVFLAG_FLAG10_Pos                                 10                                                        /*!< SCT EVFLAG: FLAG10 Position         */
#define SCT_EVFLAG_FLAG10_Msk                                 (0x01UL << SCT_EVFLAG_FLAG10_Pos)                         /*!< SCT EVFLAG: FLAG10 Mask             */
#define SCT_EVFLAG_FLAG11_Pos                                 11                                                        /*!< SCT EVFLAG: FLAG11 Position         */
#define SCT_EVFLAG_FLAG11_Msk                                 (0x01UL << SCT_EVFLAG_FLAG11_Pos)                         /*!< SCT EVFLAG: FLAG11 Mask             */
#define SCT_EVFLAG_FLAG12_Pos                                 12                                                        /*!< SCT EVFLAG: FLAG12 Position         */
#define SCT_EVFLAG_FLAG12_Msk                                 (0x01UL << SCT_EVFLAG_FLAG12_Pos)                         /*!< SCT EVFLAG: FLAG12 Mask             */
#define SCT_EVFLAG_FLAG13_Pos                                 13                                                        /*!< SCT EVFLAG: FLAG13 Position         */
#define SCT_EVFLAG_FLAG13_Msk                                 (0x01UL << SCT_EVFLAG_FLAG13_Pos)                         /*!< SCT EVFLAG: FLAG13 Mask             */
#define SCT_EVFLAG_FLAG14_Pos                                 14                                                        /*!< SCT EVFLAG: FLAG14 Position         */
#define SCT_EVFLAG_FLAG14_Msk                                 (0x01UL << SCT_EVFLAG_FLAG14_Pos)                         /*!< SCT EVFLAG: FLAG14 Mask             */
#define SCT_EVFLAG_FLAG15_Pos                                 15                                                        /*!< SCT EVFLAG: FLAG15 Position         */
#define SCT_EVFLAG_FLAG15_Msk                                 (0x01UL << SCT_EVFLAG_FLAG15_Pos)                         /*!< SCT EVFLAG: FLAG15 Mask             */

// ----------------------------------------  SCT_CONEN  -------------------------------------------
#define SCT_CONEN_NCEN0_Pos                                   0                                                         /*!< SCT CONEN: NCEN0 Position           */
#define SCT_CONEN_NCEN0_Msk                                   (0x01UL << SCT_CONEN_NCEN0_Pos)                           /*!< SCT CONEN: NCEN0 Mask               */
#define SCT_CONEN_NCEN1_Pos                                   1                                                         /*!< SCT CONEN: NCEN1 Position           */
#define SCT_CONEN_NCEN1_Msk                                   (0x01UL << SCT_CONEN_NCEN1_Pos)                           /*!< SCT CONEN: NCEN1 Mask               */
#define SCT_CONEN_NCEN2_Pos                                   2                                                         /*!< SCT CONEN: NCEN2 Position           */
#define SCT_CONEN_NCEN2_Msk                                   (0x01UL << SCT_CONEN_NCEN2_Pos)                           /*!< SCT CONEN: NCEN2 Mask               */
#define SCT_CONEN_NCEN3_Pos                                   3                                                         /*!< SCT CONEN: NCEN3 Position           */
#define SCT_CONEN_NCEN3_Msk                                   (0x01UL << SCT_CONEN_NCEN3_Pos)                           /*!< SCT CONEN: NCEN3 Mask               */
#define SCT_CONEN_NCEN4_Pos                                   4                                                         /*!< SCT CONEN: NCEN4 Position           */
#define SCT_CONEN_NCEN4_Msk                                   (0x01UL << SCT_CONEN_NCEN4_Pos)                           /*!< SCT CONEN: NCEN4 Mask               */
#define SCT_CONEN_NCEN5_Pos                                   5                                                         /*!< SCT CONEN: NCEN5 Position           */
#define SCT_CONEN_NCEN5_Msk                                   (0x01UL << SCT_CONEN_NCEN5_Pos)                           /*!< SCT CONEN: NCEN5 Mask               */
#define SCT_CONEN_NCEN6_Pos                                   6                                                         /*!< SCT CONEN: NCEN6 Position           */
#define SCT_CONEN_NCEN6_Msk                                   (0x01UL << SCT_CONEN_NCEN6_Pos)                           /*!< SCT CONEN: NCEN6 Mask               */
#define SCT_CONEN_NCEN7_Pos                                   7                                                         /*!< SCT CONEN: NCEN7 Position           */
#define SCT_CONEN_NCEN7_Msk                                   (0x01UL << SCT_CONEN_NCEN7_Pos)                           /*!< SCT CONEN: NCEN7 Mask               */
#define SCT_CONEN_NCEN8_Pos                                   8                                                         /*!< SCT CONEN: NCEN8 Position           */
#define SCT_CONEN_NCEN8_Msk                                   (0x01UL << SCT_CONEN_NCEN8_Pos)                           /*!< SCT CONEN: NCEN8 Mask               */
#define SCT_CONEN_NCEN9_Pos                                   9                                                         /*!< SCT CONEN: NCEN9 Position           */
#define SCT_CONEN_NCEN9_Msk                                   (0x01UL << SCT_CONEN_NCEN9_Pos)                           /*!< SCT CONEN: NCEN9 Mask               */
#define SCT_CONEN_NCEN10_Pos                                  10                                                        /*!< SCT CONEN: NCEN10 Position          */
#define SCT_CONEN_NCEN10_Msk                                  (0x01UL << SCT_CONEN_NCEN10_Pos)                          /*!< SCT CONEN: NCEN10 Mask              */
#define SCT_CONEN_NCEN11_Pos                                  11                                                        /*!< SCT CONEN: NCEN11 Position          */
#define SCT_CONEN_NCEN11_Msk                                  (0x01UL << SCT_CONEN_NCEN11_Pos)                          /*!< SCT CONEN: NCEN11 Mask              */
#define SCT_CONEN_NCEN12_Pos                                  12                                                        /*!< SCT CONEN: NCEN12 Position          */
#define SCT_CONEN_NCEN12_Msk                                  (0x01UL << SCT_CONEN_NCEN12_Pos)                          /*!< SCT CONEN: NCEN12 Mask              */
#define SCT_CONEN_NCEN13_Pos                                  13                                                        /*!< SCT CONEN: NCEN13 Position          */
#define SCT_CONEN_NCEN13_Msk                                  (0x01UL << SCT_CONEN_NCEN13_Pos)                          /*!< SCT CONEN: NCEN13 Mask              */
#define SCT_CONEN_NCEN14_Pos                                  14                                                        /*!< SCT CONEN: NCEN14 Position          */
#define SCT_CONEN_NCEN14_Msk                                  (0x01UL << SCT_CONEN_NCEN14_Pos)                          /*!< SCT CONEN: NCEN14 Mask              */
#define SCT_CONEN_NCEN15_Pos                                  15                                                        /*!< SCT CONEN: NCEN15 Position          */
#define SCT_CONEN_NCEN15_Msk                                  (0x01UL << SCT_CONEN_NCEN15_Pos)                          /*!< SCT CONEN: NCEN15 Mask              */

// ---------------------------------------  SCT_CONFLAG  ------------------------------------------
#define SCT_CONFLAG_NCFLAG0_Pos                               0                                                         /*!< SCT CONFLAG: NCFLAG0 Position       */
#define SCT_CONFLAG_NCFLAG0_Msk                               (0x01UL << SCT_CONFLAG_NCFLAG0_Pos)                       /*!< SCT CONFLAG: NCFLAG0 Mask           */
#define SCT_CONFLAG_NCFLAG1_Pos                               1                                                         /*!< SCT CONFLAG: NCFLAG1 Position       */
#define SCT_CONFLAG_NCFLAG1_Msk                               (0x01UL << SCT_CONFLAG_NCFLAG1_Pos)                       /*!< SCT CONFLAG: NCFLAG1 Mask           */
#define SCT_CONFLAG_NCFLAG2_Pos                               2                                                         /*!< SCT CONFLAG: NCFLAG2 Position       */
#define SCT_CONFLAG_NCFLAG2_Msk                               (0x01UL << SCT_CONFLAG_NCFLAG2_Pos)                       /*!< SCT CONFLAG: NCFLAG2 Mask           */
#define SCT_CONFLAG_NCFLAG3_Pos                               3                                                         /*!< SCT CONFLAG: NCFLAG3 Position       */
#define SCT_CONFLAG_NCFLAG3_Msk                               (0x01UL << SCT_CONFLAG_NCFLAG3_Pos)                       /*!< SCT CONFLAG: NCFLAG3 Mask           */
#define SCT_CONFLAG_NCFLAG4_Pos                               4                                                         /*!< SCT CONFLAG: NCFLAG4 Position       */
#define SCT_CONFLAG_NCFLAG4_Msk                               (0x01UL << SCT_CONFLAG_NCFLAG4_Pos)                       /*!< SCT CONFLAG: NCFLAG4 Mask           */
#define SCT_CONFLAG_NCFLAG5_Pos                               5                                                         /*!< SCT CONFLAG: NCFLAG5 Position       */
#define SCT_CONFLAG_NCFLAG5_Msk                               (0x01UL << SCT_CONFLAG_NCFLAG5_Pos)                       /*!< SCT CONFLAG: NCFLAG5 Mask           */
#define SCT_CONFLAG_NCFLAG6_Pos                               6                                                         /*!< SCT CONFLAG: NCFLAG6 Position       */
#define SCT_CONFLAG_NCFLAG6_Msk                               (0x01UL << SCT_CONFLAG_NCFLAG6_Pos)                       /*!< SCT CONFLAG: NCFLAG6 Mask           */
#define SCT_CONFLAG_NCFLAG7_Pos                               7                                                         /*!< SCT CONFLAG: NCFLAG7 Position       */
#define SCT_CONFLAG_NCFLAG7_Msk                               (0x01UL << SCT_CONFLAG_NCFLAG7_Pos)                       /*!< SCT CONFLAG: NCFLAG7 Mask           */
#define SCT_CONFLAG_NCFLAG8_Pos                               8                                                         /*!< SCT CONFLAG: NCFLAG8 Position       */
#define SCT_CONFLAG_NCFLAG8_Msk                               (0x01UL << SCT_CONFLAG_NCFLAG8_Pos)                       /*!< SCT CONFLAG: NCFLAG8 Mask           */
#define SCT_CONFLAG_NCFLAG9_Pos                               9                                                         /*!< SCT CONFLAG: NCFLAG9 Position       */
#define SCT_CONFLAG_NCFLAG9_Msk                               (0x01UL << SCT_CONFLAG_NCFLAG9_Pos)                       /*!< SCT CONFLAG: NCFLAG9 Mask           */
#define SCT_CONFLAG_NCFLAG10_Pos                              10                                                        /*!< SCT CONFLAG: NCFLAG10 Position      */
#define SCT_CONFLAG_NCFLAG10_Msk                              (0x01UL << SCT_CONFLAG_NCFLAG10_Pos)                      /*!< SCT CONFLAG: NCFLAG10 Mask          */
#define SCT_CONFLAG_NCFLAG11_Pos                              11                                                        /*!< SCT CONFLAG: NCFLAG11 Position      */
#define SCT_CONFLAG_NCFLAG11_Msk                              (0x01UL << SCT_CONFLAG_NCFLAG11_Pos)                      /*!< SCT CONFLAG: NCFLAG11 Mask          */
#define SCT_CONFLAG_NCFLAG12_Pos                              12                                                        /*!< SCT CONFLAG: NCFLAG12 Position      */
#define SCT_CONFLAG_NCFLAG12_Msk                              (0x01UL << SCT_CONFLAG_NCFLAG12_Pos)                      /*!< SCT CONFLAG: NCFLAG12 Mask          */
#define SCT_CONFLAG_NCFLAG13_Pos                              13                                                        /*!< SCT CONFLAG: NCFLAG13 Position      */
#define SCT_CONFLAG_NCFLAG13_Msk                              (0x01UL << SCT_CONFLAG_NCFLAG13_Pos)                      /*!< SCT CONFLAG: NCFLAG13 Mask          */
#define SCT_CONFLAG_NCFLAG14_Pos                              14                                                        /*!< SCT CONFLAG: NCFLAG14 Position      */
#define SCT_CONFLAG_NCFLAG14_Msk                              (0x01UL << SCT_CONFLAG_NCFLAG14_Pos)                      /*!< SCT CONFLAG: NCFLAG14 Mask          */
#define SCT_CONFLAG_NCFLAG15_Pos                              15                                                        /*!< SCT CONFLAG: NCFLAG15 Position      */
#define SCT_CONFLAG_NCFLAG15_Msk                              (0x01UL << SCT_CONFLAG_NCFLAG15_Pos)                      /*!< SCT CONFLAG: NCFLAG15 Mask          */
#define SCT_CONFLAG_BUSERRL_Pos                               30                                                        /*!< SCT CONFLAG: BUSERRL Position       */
#define SCT_CONFLAG_BUSERRL_Msk                               (0x01UL << SCT_CONFLAG_BUSERRL_Pos)                       /*!< SCT CONFLAG: BUSERRL Mask           */
#define SCT_CONFLAG_BUSERRH_Pos                               31                                                        /*!< SCT CONFLAG: BUSERRH Position       */
#define SCT_CONFLAG_BUSERRH_Msk                               (0x01UL << SCT_CONFLAG_BUSERRH_Pos)                       /*!< SCT CONFLAG: BUSERRH Mask           */

// ---------------------------------------  SCT_MATCH0  -------------------------------------------
#define SCT_MATCH0_MATCHn_L_Pos                               0                                                         /*!< SCT MATCH0: MATCHn_L Position       */
#define SCT_MATCH0_MATCHn_L_Msk                               (0x0000ffffUL << SCT_MATCH0_MATCHn_L_Pos)                 /*!< SCT MATCH0: MATCHn_L Mask           */
#define SCT_MATCH0_MATCHn_H_Pos                               16                                                        /*!< SCT MATCH0: MATCHn_H Position       */
#define SCT_MATCH0_MATCHn_H_Msk                               (0x0000ffffUL << SCT_MATCH0_MATCHn_H_Pos)                 /*!< SCT MATCH0: MATCHn_H Mask           */

// ----------------------------------------  SCT_CAP0  --------------------------------------------
#define SCT_CAP0_CAPn_L_Pos                                   0                                                         /*!< SCT CAP0: CAPn_L Position           */
#define SCT_CAP0_CAPn_L_Msk                                   (0x0000ffffUL << SCT_CAP0_CAPn_L_Pos)                     /*!< SCT CAP0: CAPn_L Mask               */
#define SCT_CAP0_CAPn_H_Pos                                   16                                                        /*!< SCT CAP0: CAPn_H Position           */
#define SCT_CAP0_CAPn_H_Msk                                   (0x0000ffffUL << SCT_CAP0_CAPn_H_Pos)                     /*!< SCT CAP0: CAPn_H Mask               */

// ---------------------------------------  SCT_MATCH1  -------------------------------------------
#define SCT_MATCH1_MATCHn_L_Pos                               0                                                         /*!< SCT MATCH1: MATCHn_L Position       */
#define SCT_MATCH1_MATCHn_L_Msk                               (0x0000ffffUL << SCT_MATCH1_MATCHn_L_Pos)                 /*!< SCT MATCH1: MATCHn_L Mask           */
#define SCT_MATCH1_MATCHn_H_Pos                               16                                                        /*!< SCT MATCH1: MATCHn_H Position       */
#define SCT_MATCH1_MATCHn_H_Msk                               (0x0000ffffUL << SCT_MATCH1_MATCHn_H_Pos)                 /*!< SCT MATCH1: MATCHn_H Mask           */

// ----------------------------------------  SCT_CAP1  --------------------------------------------
#define SCT_CAP1_CAPn_L_Pos                                   0                                                         /*!< SCT CAP1: CAPn_L Position           */
#define SCT_CAP1_CAPn_L_Msk                                   (0x0000ffffUL << SCT_CAP1_CAPn_L_Pos)                     /*!< SCT CAP1: CAPn_L Mask               */
#define SCT_CAP1_CAPn_H_Pos                                   16                                                        /*!< SCT CAP1: CAPn_H Position           */
#define SCT_CAP1_CAPn_H_Msk                                   (0x0000ffffUL << SCT_CAP1_CAPn_H_Pos)                     /*!< SCT CAP1: CAPn_H Mask               */

// ---------------------------------------  SCT_MATCH2  -------------------------------------------
#define SCT_MATCH2_MATCHn_L_Pos                               0                                                         /*!< SCT MATCH2: MATCHn_L Position       */
#define SCT_MATCH2_MATCHn_L_Msk                               (0x0000ffffUL << SCT_MATCH2_MATCHn_L_Pos)                 /*!< SCT MATCH2: MATCHn_L Mask           */
#define SCT_MATCH2_MATCHn_H_Pos                               16                                                        /*!< SCT MATCH2: MATCHn_H Position       */
#define SCT_MATCH2_MATCHn_H_Msk                               (0x0000ffffUL << SCT_MATCH2_MATCHn_H_Pos)                 /*!< SCT MATCH2: MATCHn_H Mask           */

// ----------------------------------------  SCT_CAP2  --------------------------------------------
#define SCT_CAP2_CAPn_L_Pos                                   0                                                         /*!< SCT CAP2: CAPn_L Position           */
#define SCT_CAP2_CAPn_L_Msk                                   (0x0000ffffUL << SCT_CAP2_CAPn_L_Pos)                     /*!< SCT CAP2: CAPn_L Mask               */
#define SCT_CAP2_CAPn_H_Pos                                   16                                                        /*!< SCT CAP2: CAPn_H Position           */
#define SCT_CAP2_CAPn_H_Msk                                   (0x0000ffffUL << SCT_CAP2_CAPn_H_Pos)                     /*!< SCT CAP2: CAPn_H Mask               */

// ----------------------------------------  SCT_CAP3  --------------------------------------------
#define SCT_CAP3_CAPn_L_Pos                                   0                                                         /*!< SCT CAP3: CAPn_L Position           */
#define SCT_CAP3_CAPn_L_Msk                                   (0x0000ffffUL << SCT_CAP3_CAPn_L_Pos)                     /*!< SCT CAP3: CAPn_L Mask               */
#define SCT_CAP3_CAPn_H_Pos                                   16                                                        /*!< SCT CAP3: CAPn_H Position           */
#define SCT_CAP3_CAPn_H_Msk                                   (0x0000ffffUL << SCT_CAP3_CAPn_H_Pos)                     /*!< SCT CAP3: CAPn_H Mask               */

// ---------------------------------------  SCT_MATCH3  -------------------------------------------
#define SCT_MATCH3_MATCHn_L_Pos                               0                                                         /*!< SCT MATCH3: MATCHn_L Position       */
#define SCT_MATCH3_MATCHn_L_Msk                               (0x0000ffffUL << SCT_MATCH3_MATCHn_L_Pos)                 /*!< SCT MATCH3: MATCHn_L Mask           */
#define SCT_MATCH3_MATCHn_H_Pos                               16                                                        /*!< SCT MATCH3: MATCHn_H Position       */
#define SCT_MATCH3_MATCHn_H_Msk                               (0x0000ffffUL << SCT_MATCH3_MATCHn_H_Pos)                 /*!< SCT MATCH3: MATCHn_H Mask           */

// ---------------------------------------  SCT_MATCH4  -------------------------------------------
#define SCT_MATCH4_MATCHn_L_Pos                               0                                                         /*!< SCT MATCH4: MATCHn_L Position       */
#define SCT_MATCH4_MATCHn_L_Msk                               (0x0000ffffUL << SCT_MATCH4_MATCHn_L_Pos)                 /*!< SCT MATCH4: MATCHn_L Mask           */
#define SCT_MATCH4_MATCHn_H_Pos                               16                                                        /*!< SCT MATCH4: MATCHn_H Position       */
#define SCT_MATCH4_MATCHn_H_Msk                               (0x0000ffffUL << SCT_MATCH4_MATCHn_H_Pos)                 /*!< SCT MATCH4: MATCHn_H Mask           */

// ----------------------------------------  SCT_CAP4  --------------------------------------------
#define SCT_CAP4_CAPn_L_Pos                                   0                                                         /*!< SCT CAP4: CAPn_L Position           */
#define SCT_CAP4_CAPn_L_Msk                                   (0x0000ffffUL << SCT_CAP4_CAPn_L_Pos)                     /*!< SCT CAP4: CAPn_L Mask               */
#define SCT_CAP4_CAPn_H_Pos                                   16                                                        /*!< SCT CAP4: CAPn_H Position           */
#define SCT_CAP4_CAPn_H_Msk                                   (0x0000ffffUL << SCT_CAP4_CAPn_H_Pos)                     /*!< SCT CAP4: CAPn_H Mask               */

// ---------------------------------------  SCT_MATCH5  -------------------------------------------
#define SCT_MATCH5_MATCHn_L_Pos                               0                                                         /*!< SCT MATCH5: MATCHn_L Position       */
#define SCT_MATCH5_MATCHn_L_Msk                               (0x0000ffffUL << SCT_MATCH5_MATCHn_L_Pos)                 /*!< SCT MATCH5: MATCHn_L Mask           */
#define SCT_MATCH5_MATCHn_H_Pos                               16                                                        /*!< SCT MATCH5: MATCHn_H Position       */
#define SCT_MATCH5_MATCHn_H_Msk                               (0x0000ffffUL << SCT_MATCH5_MATCHn_H_Pos)                 /*!< SCT MATCH5: MATCHn_H Mask           */

// ----------------------------------------  SCT_CAP5  --------------------------------------------
#define SCT_CAP5_CAPn_L_Pos                                   0                                                         /*!< SCT CAP5: CAPn_L Position           */
#define SCT_CAP5_CAPn_L_Msk                                   (0x0000ffffUL << SCT_CAP5_CAPn_L_Pos)                     /*!< SCT CAP5: CAPn_L Mask               */
#define SCT_CAP5_CAPn_H_Pos                                   16                                                        /*!< SCT CAP5: CAPn_H Position           */
#define SCT_CAP5_CAPn_H_Msk                                   (0x0000ffffUL << SCT_CAP5_CAPn_H_Pos)                     /*!< SCT CAP5: CAPn_H Mask               */

// ---------------------------------------  SCT_MATCH6  -------------------------------------------
#define SCT_MATCH6_MATCHn_L_Pos                               0                                                         /*!< SCT MATCH6: MATCHn_L Position       */
#define SCT_MATCH6_MATCHn_L_Msk                               (0x0000ffffUL << SCT_MATCH6_MATCHn_L_Pos)                 /*!< SCT MATCH6: MATCHn_L Mask           */
#define SCT_MATCH6_MATCHn_H_Pos                               16                                                        /*!< SCT MATCH6: MATCHn_H Position       */
#define SCT_MATCH6_MATCHn_H_Msk                               (0x0000ffffUL << SCT_MATCH6_MATCHn_H_Pos)                 /*!< SCT MATCH6: MATCHn_H Mask           */

// ----------------------------------------  SCT_CAP6  --------------------------------------------
#define SCT_CAP6_CAPn_L_Pos                                   0                                                         /*!< SCT CAP6: CAPn_L Position           */
#define SCT_CAP6_CAPn_L_Msk                                   (0x0000ffffUL << SCT_CAP6_CAPn_L_Pos)                     /*!< SCT CAP6: CAPn_L Mask               */
#define SCT_CAP6_CAPn_H_Pos                                   16                                                        /*!< SCT CAP6: CAPn_H Position           */
#define SCT_CAP6_CAPn_H_Msk                                   (0x0000ffffUL << SCT_CAP6_CAPn_H_Pos)                     /*!< SCT CAP6: CAPn_H Mask               */

// ----------------------------------------  SCT_CAP7  --------------------------------------------
#define SCT_CAP7_CAPn_L_Pos                                   0                                                         /*!< SCT CAP7: CAPn_L Position           */
#define SCT_CAP7_CAPn_L_Msk                                   (0x0000ffffUL << SCT_CAP7_CAPn_L_Pos)                     /*!< SCT CAP7: CAPn_L Mask               */
#define SCT_CAP7_CAPn_H_Pos                                   16                                                        /*!< SCT CAP7: CAPn_H Position           */
#define SCT_CAP7_CAPn_H_Msk                                   (0x0000ffffUL << SCT_CAP7_CAPn_H_Pos)                     /*!< SCT CAP7: CAPn_H Mask               */

// ---------------------------------------  SCT_MATCH7  -------------------------------------------
#define SCT_MATCH7_MATCHn_L_Pos                               0                                                         /*!< SCT MATCH7: MATCHn_L Position       */
#define SCT_MATCH7_MATCHn_L_Msk                               (0x0000ffffUL << SCT_MATCH7_MATCHn_L_Pos)                 /*!< SCT MATCH7: MATCHn_L Mask           */
#define SCT_MATCH7_MATCHn_H_Pos                               16                                                        /*!< SCT MATCH7: MATCHn_H Position       */
#define SCT_MATCH7_MATCHn_H_Msk                               (0x0000ffffUL << SCT_MATCH7_MATCHn_H_Pos)                 /*!< SCT MATCH7: MATCHn_H Mask           */

// ----------------------------------------  SCT_CAP8  --------------------------------------------
#define SCT_CAP8_CAPn_L_Pos                                   0                                                         /*!< SCT CAP8: CAPn_L Position           */
#define SCT_CAP8_CAPn_L_Msk                                   (0x0000ffffUL << SCT_CAP8_CAPn_L_Pos)                     /*!< SCT CAP8: CAPn_L Mask               */
#define SCT_CAP8_CAPn_H_Pos                                   16                                                        /*!< SCT CAP8: CAPn_H Position           */
#define SCT_CAP8_CAPn_H_Msk                                   (0x0000ffffUL << SCT_CAP8_CAPn_H_Pos)                     /*!< SCT CAP8: CAPn_H Mask               */

// ---------------------------------------  SCT_MATCH8  -------------------------------------------
#define SCT_MATCH8_MATCHn_L_Pos                               0                                                         /*!< SCT MATCH8: MATCHn_L Position       */
#define SCT_MATCH8_MATCHn_L_Msk                               (0x0000ffffUL << SCT_MATCH8_MATCHn_L_Pos)                 /*!< SCT MATCH8: MATCHn_L Mask           */
#define SCT_MATCH8_MATCHn_H_Pos                               16                                                        /*!< SCT MATCH8: MATCHn_H Position       */
#define SCT_MATCH8_MATCHn_H_Msk                               (0x0000ffffUL << SCT_MATCH8_MATCHn_H_Pos)                 /*!< SCT MATCH8: MATCHn_H Mask           */

// ---------------------------------------  SCT_MATCH9  -------------------------------------------
#define SCT_MATCH9_MATCHn_L_Pos                               0                                                         /*!< SCT MATCH9: MATCHn_L Position       */
#define SCT_MATCH9_MATCHn_L_Msk                               (0x0000ffffUL << SCT_MATCH9_MATCHn_L_Pos)                 /*!< SCT MATCH9: MATCHn_L Mask           */
#define SCT_MATCH9_MATCHn_H_Pos                               16                                                        /*!< SCT MATCH9: MATCHn_H Position       */
#define SCT_MATCH9_MATCHn_H_Msk                               (0x0000ffffUL << SCT_MATCH9_MATCHn_H_Pos)                 /*!< SCT MATCH9: MATCHn_H Mask           */

// ----------------------------------------  SCT_CAP9  --------------------------------------------
#define SCT_CAP9_CAPn_L_Pos                                   0                                                         /*!< SCT CAP9: CAPn_L Position           */
#define SCT_CAP9_CAPn_L_Msk                                   (0x0000ffffUL << SCT_CAP9_CAPn_L_Pos)                     /*!< SCT CAP9: CAPn_L Mask               */
#define SCT_CAP9_CAPn_H_Pos                                   16                                                        /*!< SCT CAP9: CAPn_H Position           */
#define SCT_CAP9_CAPn_H_Msk                                   (0x0000ffffUL << SCT_CAP9_CAPn_H_Pos)                     /*!< SCT CAP9: CAPn_H Mask               */

// ----------------------------------------  SCT_CAP10  -------------------------------------------
#define SCT_CAP10_CAPn_L_Pos                                  0                                                         /*!< SCT CAP10: CAPn_L Position          */
#define SCT_CAP10_CAPn_L_Msk                                  (0x0000ffffUL << SCT_CAP10_CAPn_L_Pos)                    /*!< SCT CAP10: CAPn_L Mask              */
#define SCT_CAP10_CAPn_H_Pos                                  16                                                        /*!< SCT CAP10: CAPn_H Position          */
#define SCT_CAP10_CAPn_H_Msk                                  (0x0000ffffUL << SCT_CAP10_CAPn_H_Pos)                    /*!< SCT CAP10: CAPn_H Mask              */

// ---------------------------------------  SCT_MATCH10  ------------------------------------------
#define SCT_MATCH10_MATCHn_L_Pos                              0                                                         /*!< SCT MATCH10: MATCHn_L Position      */
#define SCT_MATCH10_MATCHn_L_Msk                              (0x0000ffffUL << SCT_MATCH10_MATCHn_L_Pos)                /*!< SCT MATCH10: MATCHn_L Mask          */
#define SCT_MATCH10_MATCHn_H_Pos                              16                                                        /*!< SCT MATCH10: MATCHn_H Position      */
#define SCT_MATCH10_MATCHn_H_Msk                              (0x0000ffffUL << SCT_MATCH10_MATCHn_H_Pos)                /*!< SCT MATCH10: MATCHn_H Mask          */

// ----------------------------------------  SCT_CAP11  -------------------------------------------
#define SCT_CAP11_CAPn_L_Pos                                  0                                                         /*!< SCT CAP11: CAPn_L Position          */
#define SCT_CAP11_CAPn_L_Msk                                  (0x0000ffffUL << SCT_CAP11_CAPn_L_Pos)                    /*!< SCT CAP11: CAPn_L Mask              */
#define SCT_CAP11_CAPn_H_Pos                                  16                                                        /*!< SCT CAP11: CAPn_H Position          */
#define SCT_CAP11_CAPn_H_Msk                                  (0x0000ffffUL << SCT_CAP11_CAPn_H_Pos)                    /*!< SCT CAP11: CAPn_H Mask              */

// ---------------------------------------  SCT_MATCH11  ------------------------------------------
#define SCT_MATCH11_MATCHn_L_Pos                              0                                                         /*!< SCT MATCH11: MATCHn_L Position      */
#define SCT_MATCH11_MATCHn_L_Msk                              (0x0000ffffUL << SCT_MATCH11_MATCHn_L_Pos)                /*!< SCT MATCH11: MATCHn_L Mask          */
#define SCT_MATCH11_MATCHn_H_Pos                              16                                                        /*!< SCT MATCH11: MATCHn_H Position      */
#define SCT_MATCH11_MATCHn_H_Msk                              (0x0000ffffUL << SCT_MATCH11_MATCHn_H_Pos)                /*!< SCT MATCH11: MATCHn_H Mask          */

// ---------------------------------------  SCT_MATCH12  ------------------------------------------
#define SCT_MATCH12_MATCHn_L_Pos                              0                                                         /*!< SCT MATCH12: MATCHn_L Position      */
#define SCT_MATCH12_MATCHn_L_Msk                              (0x0000ffffUL << SCT_MATCH12_MATCHn_L_Pos)                /*!< SCT MATCH12: MATCHn_L Mask          */
#define SCT_MATCH12_MATCHn_H_Pos                              16                                                        /*!< SCT MATCH12: MATCHn_H Position      */
#define SCT_MATCH12_MATCHn_H_Msk                              (0x0000ffffUL << SCT_MATCH12_MATCHn_H_Pos)                /*!< SCT MATCH12: MATCHn_H Mask          */

// ----------------------------------------  SCT_CAP12  -------------------------------------------
#define SCT_CAP12_CAPn_L_Pos                                  0                                                         /*!< SCT CAP12: CAPn_L Position          */
#define SCT_CAP12_CAPn_L_Msk                                  (0x0000ffffUL << SCT_CAP12_CAPn_L_Pos)                    /*!< SCT CAP12: CAPn_L Mask              */
#define SCT_CAP12_CAPn_H_Pos                                  16                                                        /*!< SCT CAP12: CAPn_H Position          */
#define SCT_CAP12_CAPn_H_Msk                                  (0x0000ffffUL << SCT_CAP12_CAPn_H_Pos)                    /*!< SCT CAP12: CAPn_H Mask              */

// ----------------------------------------  SCT_CAP13  -------------------------------------------
#define SCT_CAP13_CAPn_L_Pos                                  0                                                         /*!< SCT CAP13: CAPn_L Position          */
#define SCT_CAP13_CAPn_L_Msk                                  (0x0000ffffUL << SCT_CAP13_CAPn_L_Pos)                    /*!< SCT CAP13: CAPn_L Mask              */
#define SCT_CAP13_CAPn_H_Pos                                  16                                                        /*!< SCT CAP13: CAPn_H Position          */
#define SCT_CAP13_CAPn_H_Msk                                  (0x0000ffffUL << SCT_CAP13_CAPn_H_Pos)                    /*!< SCT CAP13: CAPn_H Mask              */

// ---------------------------------------  SCT_MATCH13  ------------------------------------------
#define SCT_MATCH13_MATCHn_L_Pos                              0                                                         /*!< SCT MATCH13: MATCHn_L Position      */
#define SCT_MATCH13_MATCHn_L_Msk                              (0x0000ffffUL << SCT_MATCH13_MATCHn_L_Pos)                /*!< SCT MATCH13: MATCHn_L Mask          */
#define SCT_MATCH13_MATCHn_H_Pos                              16                                                        /*!< SCT MATCH13: MATCHn_H Position      */
#define SCT_MATCH13_MATCHn_H_Msk                              (0x0000ffffUL << SCT_MATCH13_MATCHn_H_Pos)                /*!< SCT MATCH13: MATCHn_H Mask          */

// ---------------------------------------  SCT_MATCH14  ------------------------------------------
#define SCT_MATCH14_MATCHn_L_Pos                              0                                                         /*!< SCT MATCH14: MATCHn_L Position      */
#define SCT_MATCH14_MATCHn_L_Msk                              (0x0000ffffUL << SCT_MATCH14_MATCHn_L_Pos)                /*!< SCT MATCH14: MATCHn_L Mask          */
#define SCT_MATCH14_MATCHn_H_Pos                              16                                                        /*!< SCT MATCH14: MATCHn_H Position      */
#define SCT_MATCH14_MATCHn_H_Msk                              (0x0000ffffUL << SCT_MATCH14_MATCHn_H_Pos)                /*!< SCT MATCH14: MATCHn_H Mask          */

// ----------------------------------------  SCT_CAP14  -------------------------------------------
#define SCT_CAP14_CAPn_L_Pos                                  0                                                         /*!< SCT CAP14: CAPn_L Position          */
#define SCT_CAP14_CAPn_L_Msk                                  (0x0000ffffUL << SCT_CAP14_CAPn_L_Pos)                    /*!< SCT CAP14: CAPn_L Mask              */
#define SCT_CAP14_CAPn_H_Pos                                  16                                                        /*!< SCT CAP14: CAPn_H Position          */
#define SCT_CAP14_CAPn_H_Msk                                  (0x0000ffffUL << SCT_CAP14_CAPn_H_Pos)                    /*!< SCT CAP14: CAPn_H Mask              */

// ---------------------------------------  SCT_MATCH15  ------------------------------------------
#define SCT_MATCH15_MATCHn_L_Pos                              0                                                         /*!< SCT MATCH15: MATCHn_L Position      */
#define SCT_MATCH15_MATCHn_L_Msk                              (0x0000ffffUL << SCT_MATCH15_MATCHn_L_Pos)                /*!< SCT MATCH15: MATCHn_L Mask          */
#define SCT_MATCH15_MATCHn_H_Pos                              16                                                        /*!< SCT MATCH15: MATCHn_H Position      */
#define SCT_MATCH15_MATCHn_H_Msk                              (0x0000ffffUL << SCT_MATCH15_MATCHn_H_Pos)                /*!< SCT MATCH15: MATCHn_H Mask          */

// ----------------------------------------  SCT_CAP15  -------------------------------------------
#define SCT_CAP15_CAPn_L_Pos                                  0                                                         /*!< SCT CAP15: CAPn_L Position          */
#define SCT_CAP15_CAPn_L_Msk                                  (0x0000ffffUL << SCT_CAP15_CAPn_L_Pos)                    /*!< SCT CAP15: CAPn_L Mask              */
#define SCT_CAP15_CAPn_H_Pos                                  16                                                        /*!< SCT CAP15: CAPn_H Position          */
#define SCT_CAP15_CAPn_H_Msk                                  (0x0000ffffUL << SCT_CAP15_CAPn_H_Pos)                    /*!< SCT CAP15: CAPn_H Mask              */

// --------------------------------------  SCT_MATCHREL0  -----------------------------------------
#define SCT_MATCHREL0_RELOADn_L_Pos                           0                                                         /*!< SCT MATCHREL0: RELOADn_L Position   */
#define SCT_MATCHREL0_RELOADn_L_Msk                           (0x0000ffffUL << SCT_MATCHREL0_RELOADn_L_Pos)             /*!< SCT MATCHREL0: RELOADn_L Mask       */
#define SCT_MATCHREL0_RELOADn_H_Pos                           16                                                        /*!< SCT MATCHREL0: RELOADn_H Position   */
#define SCT_MATCHREL0_RELOADn_H_Msk                           (0x0000ffffUL << SCT_MATCHREL0_RELOADn_H_Pos)             /*!< SCT MATCHREL0: RELOADn_H Mask       */

// --------------------------------------  SCT_CAPCTRL0  ------------------------------------------
#define SCT_CAPCTRL0_CAPCONn_L0_Pos                           0                                                         /*!< SCT CAPCTRL0: CAPCONn_L0 Position   */
#define SCT_CAPCTRL0_CAPCONn_L0_Msk                           (0x01UL << SCT_CAPCTRL0_CAPCONn_L0_Pos)                   /*!< SCT CAPCTRL0: CAPCONn_L0 Mask       */
#define SCT_CAPCTRL0_CAPCONn_L1_Pos                           1                                                         /*!< SCT CAPCTRL0: CAPCONn_L1 Position   */
#define SCT_CAPCTRL0_CAPCONn_L1_Msk                           (0x01UL << SCT_CAPCTRL0_CAPCONn_L1_Pos)                   /*!< SCT CAPCTRL0: CAPCONn_L1 Mask       */
#define SCT_CAPCTRL0_CAPCONn_L2_Pos                           2                                                         /*!< SCT CAPCTRL0: CAPCONn_L2 Position   */
#define SCT_CAPCTRL0_CAPCONn_L2_Msk                           (0x01UL << SCT_CAPCTRL0_CAPCONn_L2_Pos)                   /*!< SCT CAPCTRL0: CAPCONn_L2 Mask       */
#define SCT_CAPCTRL0_CAPCONn_L3_Pos                           3                                                         /*!< SCT CAPCTRL0: CAPCONn_L3 Position   */
#define SCT_CAPCTRL0_CAPCONn_L3_Msk                           (0x01UL << SCT_CAPCTRL0_CAPCONn_L3_Pos)                   /*!< SCT CAPCTRL0: CAPCONn_L3 Mask       */
#define SCT_CAPCTRL0_CAPCONn_L4_Pos                           4                                                         /*!< SCT CAPCTRL0: CAPCONn_L4 Position   */
#define SCT_CAPCTRL0_CAPCONn_L4_Msk                           (0x01UL << SCT_CAPCTRL0_CAPCONn_L4_Pos)                   /*!< SCT CAPCTRL0: CAPCONn_L4 Mask       */
#define SCT_CAPCTRL0_CAPCONn_L5_Pos                           5                                                         /*!< SCT CAPCTRL0: CAPCONn_L5 Position   */
#define SCT_CAPCTRL0_CAPCONn_L5_Msk                           (0x01UL << SCT_CAPCTRL0_CAPCONn_L5_Pos)                   /*!< SCT CAPCTRL0: CAPCONn_L5 Mask       */
#define SCT_CAPCTRL0_CAPCONn_L6_Pos                           6                                                         /*!< SCT CAPCTRL0: CAPCONn_L6 Position   */
#define SCT_CAPCTRL0_CAPCONn_L6_Msk                           (0x01UL << SCT_CAPCTRL0_CAPCONn_L6_Pos)                   /*!< SCT CAPCTRL0: CAPCONn_L6 Mask       */
#define SCT_CAPCTRL0_CAPCONn_L7_Pos                           7                                                         /*!< SCT CAPCTRL0: CAPCONn_L7 Position   */
#define SCT_CAPCTRL0_CAPCONn_L7_Msk                           (0x01UL << SCT_CAPCTRL0_CAPCONn_L7_Pos)                   /*!< SCT CAPCTRL0: CAPCONn_L7 Mask       */
#define SCT_CAPCTRL0_CAPCONn_L8_Pos                           8                                                         /*!< SCT CAPCTRL0: CAPCONn_L8 Position   */
#define SCT_CAPCTRL0_CAPCONn_L8_Msk                           (0x01UL << SCT_CAPCTRL0_CAPCONn_L8_Pos)                   /*!< SCT CAPCTRL0: CAPCONn_L8 Mask       */
#define SCT_CAPCTRL0_CAPCONn_L9_Pos                           9                                                         /*!< SCT CAPCTRL0: CAPCONn_L9 Position   */
#define SCT_CAPCTRL0_CAPCONn_L9_Msk                           (0x01UL << SCT_CAPCTRL0_CAPCONn_L9_Pos)                   /*!< SCT CAPCTRL0: CAPCONn_L9 Mask       */
#define SCT_CAPCTRL0_CAPCONn_L10_Pos                          10                                                        /*!< SCT CAPCTRL0: CAPCONn_L10 Position  */
#define SCT_CAPCTRL0_CAPCONn_L10_Msk                          (0x01UL << SCT_CAPCTRL0_CAPCONn_L10_Pos)                  /*!< SCT CAPCTRL0: CAPCONn_L10 Mask      */
#define SCT_CAPCTRL0_CAPCONn_L11_Pos                          11                                                        /*!< SCT CAPCTRL0: CAPCONn_L11 Position  */
#define SCT_CAPCTRL0_CAPCONn_L11_Msk                          (0x01UL << SCT_CAPCTRL0_CAPCONn_L11_Pos)                  /*!< SCT CAPCTRL0: CAPCONn_L11 Mask      */
#define SCT_CAPCTRL0_CAPCONn_L12_Pos                          12                                                        /*!< SCT CAPCTRL0: CAPCONn_L12 Position  */
#define SCT_CAPCTRL0_CAPCONn_L12_Msk                          (0x01UL << SCT_CAPCTRL0_CAPCONn_L12_Pos)                  /*!< SCT CAPCTRL0: CAPCONn_L12 Mask      */
#define SCT_CAPCTRL0_CAPCONn_L13_Pos                          13                                                        /*!< SCT CAPCTRL0: CAPCONn_L13 Position  */
#define SCT_CAPCTRL0_CAPCONn_L13_Msk                          (0x01UL << SCT_CAPCTRL0_CAPCONn_L13_Pos)                  /*!< SCT CAPCTRL0: CAPCONn_L13 Mask      */
#define SCT_CAPCTRL0_CAPCONn_L14_Pos                          14                                                        /*!< SCT CAPCTRL0: CAPCONn_L14 Position  */
#define SCT_CAPCTRL0_CAPCONn_L14_Msk                          (0x01UL << SCT_CAPCTRL0_CAPCONn_L14_Pos)                  /*!< SCT CAPCTRL0: CAPCONn_L14 Mask      */
#define SCT_CAPCTRL0_CAPCONn_L15_Pos                          15                                                        /*!< SCT CAPCTRL0: CAPCONn_L15 Position  */
#define SCT_CAPCTRL0_CAPCONn_L15_Msk                          (0x01UL << SCT_CAPCTRL0_CAPCONn_L15_Pos)                  /*!< SCT CAPCTRL0: CAPCONn_L15 Mask      */
#define SCT_CAPCTRL0_CAPCONn_H_Pos                            16                                                        /*!< SCT CAPCTRL0: CAPCONn_H Position    */
#define SCT_CAPCTRL0_CAPCONn_H_Msk                            (0x0000ffffUL << SCT_CAPCTRL0_CAPCONn_H_Pos)              /*!< SCT CAPCTRL0: CAPCONn_H Mask        */

// --------------------------------------  SCT_MATCHREL1  -----------------------------------------
#define SCT_MATCHREL1_RELOADn_L_Pos                           0                                                         /*!< SCT MATCHREL1: RELOADn_L Position   */
#define SCT_MATCHREL1_RELOADn_L_Msk                           (0x0000ffffUL << SCT_MATCHREL1_RELOADn_L_Pos)             /*!< SCT MATCHREL1: RELOADn_L Mask       */
#define SCT_MATCHREL1_RELOADn_H_Pos                           16                                                        /*!< SCT MATCHREL1: RELOADn_H Position   */
#define SCT_MATCHREL1_RELOADn_H_Msk                           (0x0000ffffUL << SCT_MATCHREL1_RELOADn_H_Pos)             /*!< SCT MATCHREL1: RELOADn_H Mask       */

// --------------------------------------  SCT_CAPCTRL1  ------------------------------------------
#define SCT_CAPCTRL1_CAPCONn_L0_Pos                           0                                                         /*!< SCT CAPCTRL1: CAPCONn_L0 Position   */
#define SCT_CAPCTRL1_CAPCONn_L0_Msk                           (0x01UL << SCT_CAPCTRL1_CAPCONn_L0_Pos)                   /*!< SCT CAPCTRL1: CAPCONn_L0 Mask       */
#define SCT_CAPCTRL1_CAPCONn_L1_Pos                           1                                                         /*!< SCT CAPCTRL1: CAPCONn_L1 Position   */
#define SCT_CAPCTRL1_CAPCONn_L1_Msk                           (0x01UL << SCT_CAPCTRL1_CAPCONn_L1_Pos)                   /*!< SCT CAPCTRL1: CAPCONn_L1 Mask       */
#define SCT_CAPCTRL1_CAPCONn_L2_Pos                           2                                                         /*!< SCT CAPCTRL1: CAPCONn_L2 Position   */
#define SCT_CAPCTRL1_CAPCONn_L2_Msk                           (0x01UL << SCT_CAPCTRL1_CAPCONn_L2_Pos)                   /*!< SCT CAPCTRL1: CAPCONn_L2 Mask       */
#define SCT_CAPCTRL1_CAPCONn_L3_Pos                           3                                                         /*!< SCT CAPCTRL1: CAPCONn_L3 Position   */
#define SCT_CAPCTRL1_CAPCONn_L3_Msk                           (0x01UL << SCT_CAPCTRL1_CAPCONn_L3_Pos)                   /*!< SCT CAPCTRL1: CAPCONn_L3 Mask       */
#define SCT_CAPCTRL1_CAPCONn_L4_Pos                           4                                                         /*!< SCT CAPCTRL1: CAPCONn_L4 Position   */
#define SCT_CAPCTRL1_CAPCONn_L4_Msk                           (0x01UL << SCT_CAPCTRL1_CAPCONn_L4_Pos)                   /*!< SCT CAPCTRL1: CAPCONn_L4 Mask       */
#define SCT_CAPCTRL1_CAPCONn_L5_Pos                           5                                                         /*!< SCT CAPCTRL1: CAPCONn_L5 Position   */
#define SCT_CAPCTRL1_CAPCONn_L5_Msk                           (0x01UL << SCT_CAPCTRL1_CAPCONn_L5_Pos)                   /*!< SCT CAPCTRL1: CAPCONn_L5 Mask       */
#define SCT_CAPCTRL1_CAPCONn_L6_Pos                           6                                                         /*!< SCT CAPCTRL1: CAPCONn_L6 Position   */
#define SCT_CAPCTRL1_CAPCONn_L6_Msk                           (0x01UL << SCT_CAPCTRL1_CAPCONn_L6_Pos)                   /*!< SCT CAPCTRL1: CAPCONn_L6 Mask       */
#define SCT_CAPCTRL1_CAPCONn_L7_Pos                           7                                                         /*!< SCT CAPCTRL1: CAPCONn_L7 Position   */
#define SCT_CAPCTRL1_CAPCONn_L7_Msk                           (0x01UL << SCT_CAPCTRL1_CAPCONn_L7_Pos)                   /*!< SCT CAPCTRL1: CAPCONn_L7 Mask       */
#define SCT_CAPCTRL1_CAPCONn_L8_Pos                           8                                                         /*!< SCT CAPCTRL1: CAPCONn_L8 Position   */
#define SCT_CAPCTRL1_CAPCONn_L8_Msk                           (0x01UL << SCT_CAPCTRL1_CAPCONn_L8_Pos)                   /*!< SCT CAPCTRL1: CAPCONn_L8 Mask       */
#define SCT_CAPCTRL1_CAPCONn_L9_Pos                           9                                                         /*!< SCT CAPCTRL1: CAPCONn_L9 Position   */
#define SCT_CAPCTRL1_CAPCONn_L9_Msk                           (0x01UL << SCT_CAPCTRL1_CAPCONn_L9_Pos)                   /*!< SCT CAPCTRL1: CAPCONn_L9 Mask       */
#define SCT_CAPCTRL1_CAPCONn_L10_Pos                          10                                                        /*!< SCT CAPCTRL1: CAPCONn_L10 Position  */
#define SCT_CAPCTRL1_CAPCONn_L10_Msk                          (0x01UL << SCT_CAPCTRL1_CAPCONn_L10_Pos)                  /*!< SCT CAPCTRL1: CAPCONn_L10 Mask      */
#define SCT_CAPCTRL1_CAPCONn_L11_Pos                          11                                                        /*!< SCT CAPCTRL1: CAPCONn_L11 Position  */
#define SCT_CAPCTRL1_CAPCONn_L11_Msk                          (0x01UL << SCT_CAPCTRL1_CAPCONn_L11_Pos)                  /*!< SCT CAPCTRL1: CAPCONn_L11 Mask      */
#define SCT_CAPCTRL1_CAPCONn_L12_Pos                          12                                                        /*!< SCT CAPCTRL1: CAPCONn_L12 Position  */
#define SCT_CAPCTRL1_CAPCONn_L12_Msk                          (0x01UL << SCT_CAPCTRL1_CAPCONn_L12_Pos)                  /*!< SCT CAPCTRL1: CAPCONn_L12 Mask      */
#define SCT_CAPCTRL1_CAPCONn_L13_Pos                          13                                                        /*!< SCT CAPCTRL1: CAPCONn_L13 Position  */
#define SCT_CAPCTRL1_CAPCONn_L13_Msk                          (0x01UL << SCT_CAPCTRL1_CAPCONn_L13_Pos)                  /*!< SCT CAPCTRL1: CAPCONn_L13 Mask      */
#define SCT_CAPCTRL1_CAPCONn_L14_Pos                          14                                                        /*!< SCT CAPCTRL1: CAPCONn_L14 Position  */
#define SCT_CAPCTRL1_CAPCONn_L14_Msk                          (0x01UL << SCT_CAPCTRL1_CAPCONn_L14_Pos)                  /*!< SCT CAPCTRL1: CAPCONn_L14 Mask      */
#define SCT_CAPCTRL1_CAPCONn_L15_Pos                          15                                                        /*!< SCT CAPCTRL1: CAPCONn_L15 Position  */
#define SCT_CAPCTRL1_CAPCONn_L15_Msk                          (0x01UL << SCT_CAPCTRL1_CAPCONn_L15_Pos)                  /*!< SCT CAPCTRL1: CAPCONn_L15 Mask      */
#define SCT_CAPCTRL1_CAPCONn_H_Pos                            16                                                        /*!< SCT CAPCTRL1: CAPCONn_H Position    */
#define SCT_CAPCTRL1_CAPCONn_H_Msk                            (0x0000ffffUL << SCT_CAPCTRL1_CAPCONn_H_Pos)              /*!< SCT CAPCTRL1: CAPCONn_H Mask        */

// --------------------------------------  SCT_MATCHREL2  -----------------------------------------
#define SCT_MATCHREL2_RELOADn_L_Pos                           0                                                         /*!< SCT MATCHREL2: RELOADn_L Position   */
#define SCT_MATCHREL2_RELOADn_L_Msk                           (0x0000ffffUL << SCT_MATCHREL2_RELOADn_L_Pos)             /*!< SCT MATCHREL2: RELOADn_L Mask       */
#define SCT_MATCHREL2_RELOADn_H_Pos                           16                                                        /*!< SCT MATCHREL2: RELOADn_H Position   */
#define SCT_MATCHREL2_RELOADn_H_Msk                           (0x0000ffffUL << SCT_MATCHREL2_RELOADn_H_Pos)             /*!< SCT MATCHREL2: RELOADn_H Mask       */

// --------------------------------------  SCT_CAPCTRL2  ------------------------------------------
#define SCT_CAPCTRL2_CAPCONn_L0_Pos                           0                                                         /*!< SCT CAPCTRL2: CAPCONn_L0 Position   */
#define SCT_CAPCTRL2_CAPCONn_L0_Msk                           (0x01UL << SCT_CAPCTRL2_CAPCONn_L0_Pos)                   /*!< SCT CAPCTRL2: CAPCONn_L0 Mask       */
#define SCT_CAPCTRL2_CAPCONn_L1_Pos                           1                                                         /*!< SCT CAPCTRL2: CAPCONn_L1 Position   */
#define SCT_CAPCTRL2_CAPCONn_L1_Msk                           (0x01UL << SCT_CAPCTRL2_CAPCONn_L1_Pos)                   /*!< SCT CAPCTRL2: CAPCONn_L1 Mask       */
#define SCT_CAPCTRL2_CAPCONn_L2_Pos                           2                                                         /*!< SCT CAPCTRL2: CAPCONn_L2 Position   */
#define SCT_CAPCTRL2_CAPCONn_L2_Msk                           (0x01UL << SCT_CAPCTRL2_CAPCONn_L2_Pos)                   /*!< SCT CAPCTRL2: CAPCONn_L2 Mask       */
#define SCT_CAPCTRL2_CAPCONn_L3_Pos                           3                                                         /*!< SCT CAPCTRL2: CAPCONn_L3 Position   */
#define SCT_CAPCTRL2_CAPCONn_L3_Msk                           (0x01UL << SCT_CAPCTRL2_CAPCONn_L3_Pos)                   /*!< SCT CAPCTRL2: CAPCONn_L3 Mask       */
#define SCT_CAPCTRL2_CAPCONn_L4_Pos                           4                                                         /*!< SCT CAPCTRL2: CAPCONn_L4 Position   */
#define SCT_CAPCTRL2_CAPCONn_L4_Msk                           (0x01UL << SCT_CAPCTRL2_CAPCONn_L4_Pos)                   /*!< SCT CAPCTRL2: CAPCONn_L4 Mask       */
#define SCT_CAPCTRL2_CAPCONn_L5_Pos                           5                                                         /*!< SCT CAPCTRL2: CAPCONn_L5 Position   */
#define SCT_CAPCTRL2_CAPCONn_L5_Msk                           (0x01UL << SCT_CAPCTRL2_CAPCONn_L5_Pos)                   /*!< SCT CAPCTRL2: CAPCONn_L5 Mask       */
#define SCT_CAPCTRL2_CAPCONn_L6_Pos                           6                                                         /*!< SCT CAPCTRL2: CAPCONn_L6 Position   */
#define SCT_CAPCTRL2_CAPCONn_L6_Msk                           (0x01UL << SCT_CAPCTRL2_CAPCONn_L6_Pos)                   /*!< SCT CAPCTRL2: CAPCONn_L6 Mask       */
#define SCT_CAPCTRL2_CAPCONn_L7_Pos                           7                                                         /*!< SCT CAPCTRL2: CAPCONn_L7 Position   */
#define SCT_CAPCTRL2_CAPCONn_L7_Msk                           (0x01UL << SCT_CAPCTRL2_CAPCONn_L7_Pos)                   /*!< SCT CAPCTRL2: CAPCONn_L7 Mask       */
#define SCT_CAPCTRL2_CAPCONn_L8_Pos                           8                                                         /*!< SCT CAPCTRL2: CAPCONn_L8 Position   */
#define SCT_CAPCTRL2_CAPCONn_L8_Msk                           (0x01UL << SCT_CAPCTRL2_CAPCONn_L8_Pos)                   /*!< SCT CAPCTRL2: CAPCONn_L8 Mask       */
#define SCT_CAPCTRL2_CAPCONn_L9_Pos                           9                                                         /*!< SCT CAPCTRL2: CAPCONn_L9 Position   */
#define SCT_CAPCTRL2_CAPCONn_L9_Msk                           (0x01UL << SCT_CAPCTRL2_CAPCONn_L9_Pos)                   /*!< SCT CAPCTRL2: CAPCONn_L9 Mask       */
#define SCT_CAPCTRL2_CAPCONn_L10_Pos                          10                                                        /*!< SCT CAPCTRL2: CAPCONn_L10 Position  */
#define SCT_CAPCTRL2_CAPCONn_L10_Msk                          (0x01UL << SCT_CAPCTRL2_CAPCONn_L10_Pos)                  /*!< SCT CAPCTRL2: CAPCONn_L10 Mask      */
#define SCT_CAPCTRL2_CAPCONn_L11_Pos                          11                                                        /*!< SCT CAPCTRL2: CAPCONn_L11 Position  */
#define SCT_CAPCTRL2_CAPCONn_L11_Msk                          (0x01UL << SCT_CAPCTRL2_CAPCONn_L11_Pos)                  /*!< SCT CAPCTRL2: CAPCONn_L11 Mask      */
#define SCT_CAPCTRL2_CAPCONn_L12_Pos                          12                                                        /*!< SCT CAPCTRL2: CAPCONn_L12 Position  */
#define SCT_CAPCTRL2_CAPCONn_L12_Msk                          (0x01UL << SCT_CAPCTRL2_CAPCONn_L12_Pos)                  /*!< SCT CAPCTRL2: CAPCONn_L12 Mask      */
#define SCT_CAPCTRL2_CAPCONn_L13_Pos                          13                                                        /*!< SCT CAPCTRL2: CAPCONn_L13 Position  */
#define SCT_CAPCTRL2_CAPCONn_L13_Msk                          (0x01UL << SCT_CAPCTRL2_CAPCONn_L13_Pos)                  /*!< SCT CAPCTRL2: CAPCONn_L13 Mask      */
#define SCT_CAPCTRL2_CAPCONn_L14_Pos                          14                                                        /*!< SCT CAPCTRL2: CAPCONn_L14 Position  */
#define SCT_CAPCTRL2_CAPCONn_L14_Msk                          (0x01UL << SCT_CAPCTRL2_CAPCONn_L14_Pos)                  /*!< SCT CAPCTRL2: CAPCONn_L14 Mask      */
#define SCT_CAPCTRL2_CAPCONn_L15_Pos                          15                                                        /*!< SCT CAPCTRL2: CAPCONn_L15 Position  */
#define SCT_CAPCTRL2_CAPCONn_L15_Msk                          (0x01UL << SCT_CAPCTRL2_CAPCONn_L15_Pos)                  /*!< SCT CAPCTRL2: CAPCONn_L15 Mask      */
#define SCT_CAPCTRL2_CAPCONn_H_Pos                            16                                                        /*!< SCT CAPCTRL2: CAPCONn_H Position    */
#define SCT_CAPCTRL2_CAPCONn_H_Msk                            (0x0000ffffUL << SCT_CAPCTRL2_CAPCONn_H_Pos)              /*!< SCT CAPCTRL2: CAPCONn_H Mask        */

// --------------------------------------  SCT_MATCHREL3  -----------------------------------------
#define SCT_MATCHREL3_RELOADn_L_Pos                           0                                                         /*!< SCT MATCHREL3: RELOADn_L Position   */
#define SCT_MATCHREL3_RELOADn_L_Msk                           (0x0000ffffUL << SCT_MATCHREL3_RELOADn_L_Pos)             /*!< SCT MATCHREL3: RELOADn_L Mask       */
#define SCT_MATCHREL3_RELOADn_H_Pos                           16                                                        /*!< SCT MATCHREL3: RELOADn_H Position   */
#define SCT_MATCHREL3_RELOADn_H_Msk                           (0x0000ffffUL << SCT_MATCHREL3_RELOADn_H_Pos)             /*!< SCT MATCHREL3: RELOADn_H Mask       */

// --------------------------------------  SCT_CAPCTRL3  ------------------------------------------
#define SCT_CAPCTRL3_CAPCONn_L0_Pos                           0                                                         /*!< SCT CAPCTRL3: CAPCONn_L0 Position   */
#define SCT_CAPCTRL3_CAPCONn_L0_Msk                           (0x01UL << SCT_CAPCTRL3_CAPCONn_L0_Pos)                   /*!< SCT CAPCTRL3: CAPCONn_L0 Mask       */
#define SCT_CAPCTRL3_CAPCONn_L1_Pos                           1                                                         /*!< SCT CAPCTRL3: CAPCONn_L1 Position   */
#define SCT_CAPCTRL3_CAPCONn_L1_Msk                           (0x01UL << SCT_CAPCTRL3_CAPCONn_L1_Pos)                   /*!< SCT CAPCTRL3: CAPCONn_L1 Mask       */
#define SCT_CAPCTRL3_CAPCONn_L2_Pos                           2                                                         /*!< SCT CAPCTRL3: CAPCONn_L2 Position   */
#define SCT_CAPCTRL3_CAPCONn_L2_Msk                           (0x01UL << SCT_CAPCTRL3_CAPCONn_L2_Pos)                   /*!< SCT CAPCTRL3: CAPCONn_L2 Mask       */
#define SCT_CAPCTRL3_CAPCONn_L3_Pos                           3                                                         /*!< SCT CAPCTRL3: CAPCONn_L3 Position   */
#define SCT_CAPCTRL3_CAPCONn_L3_Msk                           (0x01UL << SCT_CAPCTRL3_CAPCONn_L3_Pos)                   /*!< SCT CAPCTRL3: CAPCONn_L3 Mask       */
#define SCT_CAPCTRL3_CAPCONn_L4_Pos                           4                                                         /*!< SCT CAPCTRL3: CAPCONn_L4 Position   */
#define SCT_CAPCTRL3_CAPCONn_L4_Msk                           (0x01UL << SCT_CAPCTRL3_CAPCONn_L4_Pos)                   /*!< SCT CAPCTRL3: CAPCONn_L4 Mask       */
#define SCT_CAPCTRL3_CAPCONn_L5_Pos                           5                                                         /*!< SCT CAPCTRL3: CAPCONn_L5 Position   */
#define SCT_CAPCTRL3_CAPCONn_L5_Msk                           (0x01UL << SCT_CAPCTRL3_CAPCONn_L5_Pos)                   /*!< SCT CAPCTRL3: CAPCONn_L5 Mask       */
#define SCT_CAPCTRL3_CAPCONn_L6_Pos                           6                                                         /*!< SCT CAPCTRL3: CAPCONn_L6 Position   */
#define SCT_CAPCTRL3_CAPCONn_L6_Msk                           (0x01UL << SCT_CAPCTRL3_CAPCONn_L6_Pos)                   /*!< SCT CAPCTRL3: CAPCONn_L6 Mask       */
#define SCT_CAPCTRL3_CAPCONn_L7_Pos                           7                                                         /*!< SCT CAPCTRL3: CAPCONn_L7 Position   */
#define SCT_CAPCTRL3_CAPCONn_L7_Msk                           (0x01UL << SCT_CAPCTRL3_CAPCONn_L7_Pos)                   /*!< SCT CAPCTRL3: CAPCONn_L7 Mask       */
#define SCT_CAPCTRL3_CAPCONn_L8_Pos                           8                                                         /*!< SCT CAPCTRL3: CAPCONn_L8 Position   */
#define SCT_CAPCTRL3_CAPCONn_L8_Msk                           (0x01UL << SCT_CAPCTRL3_CAPCONn_L8_Pos)                   /*!< SCT CAPCTRL3: CAPCONn_L8 Mask       */
#define SCT_CAPCTRL3_CAPCONn_L9_Pos                           9                                                         /*!< SCT CAPCTRL3: CAPCONn_L9 Position   */
#define SCT_CAPCTRL3_CAPCONn_L9_Msk                           (0x01UL << SCT_CAPCTRL3_CAPCONn_L9_Pos)                   /*!< SCT CAPCTRL3: CAPCONn_L9 Mask       */
#define SCT_CAPCTRL3_CAPCONn_L10_Pos                          10                                                        /*!< SCT CAPCTRL3: CAPCONn_L10 Position  */
#define SCT_CAPCTRL3_CAPCONn_L10_Msk                          (0x01UL << SCT_CAPCTRL3_CAPCONn_L10_Pos)                  /*!< SCT CAPCTRL3: CAPCONn_L10 Mask      */
#define SCT_CAPCTRL3_CAPCONn_L11_Pos                          11                                                        /*!< SCT CAPCTRL3: CAPCONn_L11 Position  */
#define SCT_CAPCTRL3_CAPCONn_L11_Msk                          (0x01UL << SCT_CAPCTRL3_CAPCONn_L11_Pos)                  /*!< SCT CAPCTRL3: CAPCONn_L11 Mask      */
#define SCT_CAPCTRL3_CAPCONn_L12_Pos                          12                                                        /*!< SCT CAPCTRL3: CAPCONn_L12 Position  */
#define SCT_CAPCTRL3_CAPCONn_L12_Msk                          (0x01UL << SCT_CAPCTRL3_CAPCONn_L12_Pos)                  /*!< SCT CAPCTRL3: CAPCONn_L12 Mask      */
#define SCT_CAPCTRL3_CAPCONn_L13_Pos                          13                                                        /*!< SCT CAPCTRL3: CAPCONn_L13 Position  */
#define SCT_CAPCTRL3_CAPCONn_L13_Msk                          (0x01UL << SCT_CAPCTRL3_CAPCONn_L13_Pos)                  /*!< SCT CAPCTRL3: CAPCONn_L13 Mask      */
#define SCT_CAPCTRL3_CAPCONn_L14_Pos                          14                                                        /*!< SCT CAPCTRL3: CAPCONn_L14 Position  */
#define SCT_CAPCTRL3_CAPCONn_L14_Msk                          (0x01UL << SCT_CAPCTRL3_CAPCONn_L14_Pos)                  /*!< SCT CAPCTRL3: CAPCONn_L14 Mask      */
#define SCT_CAPCTRL3_CAPCONn_L15_Pos                          15                                                        /*!< SCT CAPCTRL3: CAPCONn_L15 Position  */
#define SCT_CAPCTRL3_CAPCONn_L15_Msk                          (0x01UL << SCT_CAPCTRL3_CAPCONn_L15_Pos)                  /*!< SCT CAPCTRL3: CAPCONn_L15 Mask      */
#define SCT_CAPCTRL3_CAPCONn_H_Pos                            16                                                        /*!< SCT CAPCTRL3: CAPCONn_H Position    */
#define SCT_CAPCTRL3_CAPCONn_H_Msk                            (0x0000ffffUL << SCT_CAPCTRL3_CAPCONn_H_Pos)              /*!< SCT CAPCTRL3: CAPCONn_H Mask        */

// --------------------------------------  SCT_CAPCTRL4  ------------------------------------------
#define SCT_CAPCTRL4_CAPCONn_L0_Pos                           0                                                         /*!< SCT CAPCTRL4: CAPCONn_L0 Position   */
#define SCT_CAPCTRL4_CAPCONn_L0_Msk                           (0x01UL << SCT_CAPCTRL4_CAPCONn_L0_Pos)                   /*!< SCT CAPCTRL4: CAPCONn_L0 Mask       */
#define SCT_CAPCTRL4_CAPCONn_L1_Pos                           1                                                         /*!< SCT CAPCTRL4: CAPCONn_L1 Position   */
#define SCT_CAPCTRL4_CAPCONn_L1_Msk                           (0x01UL << SCT_CAPCTRL4_CAPCONn_L1_Pos)                   /*!< SCT CAPCTRL4: CAPCONn_L1 Mask       */
#define SCT_CAPCTRL4_CAPCONn_L2_Pos                           2                                                         /*!< SCT CAPCTRL4: CAPCONn_L2 Position   */
#define SCT_CAPCTRL4_CAPCONn_L2_Msk                           (0x01UL << SCT_CAPCTRL4_CAPCONn_L2_Pos)                   /*!< SCT CAPCTRL4: CAPCONn_L2 Mask       */
#define SCT_CAPCTRL4_CAPCONn_L3_Pos                           3                                                         /*!< SCT CAPCTRL4: CAPCONn_L3 Position   */
#define SCT_CAPCTRL4_CAPCONn_L3_Msk                           (0x01UL << SCT_CAPCTRL4_CAPCONn_L3_Pos)                   /*!< SCT CAPCTRL4: CAPCONn_L3 Mask       */
#define SCT_CAPCTRL4_CAPCONn_L4_Pos                           4                                                         /*!< SCT CAPCTRL4: CAPCONn_L4 Position   */
#define SCT_CAPCTRL4_CAPCONn_L4_Msk                           (0x01UL << SCT_CAPCTRL4_CAPCONn_L4_Pos)                   /*!< SCT CAPCTRL4: CAPCONn_L4 Mask       */
#define SCT_CAPCTRL4_CAPCONn_L5_Pos                           5                                                         /*!< SCT CAPCTRL4: CAPCONn_L5 Position   */
#define SCT_CAPCTRL4_CAPCONn_L5_Msk                           (0x01UL << SCT_CAPCTRL4_CAPCONn_L5_Pos)                   /*!< SCT CAPCTRL4: CAPCONn_L5 Mask       */
#define SCT_CAPCTRL4_CAPCONn_L6_Pos                           6                                                         /*!< SCT CAPCTRL4: CAPCONn_L6 Position   */
#define SCT_CAPCTRL4_CAPCONn_L6_Msk                           (0x01UL << SCT_CAPCTRL4_CAPCONn_L6_Pos)                   /*!< SCT CAPCTRL4: CAPCONn_L6 Mask       */
#define SCT_CAPCTRL4_CAPCONn_L7_Pos                           7                                                         /*!< SCT CAPCTRL4: CAPCONn_L7 Position   */
#define SCT_CAPCTRL4_CAPCONn_L7_Msk                           (0x01UL << SCT_CAPCTRL4_CAPCONn_L7_Pos)                   /*!< SCT CAPCTRL4: CAPCONn_L7 Mask       */
#define SCT_CAPCTRL4_CAPCONn_L8_Pos                           8                                                         /*!< SCT CAPCTRL4: CAPCONn_L8 Position   */
#define SCT_CAPCTRL4_CAPCONn_L8_Msk                           (0x01UL << SCT_CAPCTRL4_CAPCONn_L8_Pos)                   /*!< SCT CAPCTRL4: CAPCONn_L8 Mask       */
#define SCT_CAPCTRL4_CAPCONn_L9_Pos                           9                                                         /*!< SCT CAPCTRL4: CAPCONn_L9 Position   */
#define SCT_CAPCTRL4_CAPCONn_L9_Msk                           (0x01UL << SCT_CAPCTRL4_CAPCONn_L9_Pos)                   /*!< SCT CAPCTRL4: CAPCONn_L9 Mask       */
#define SCT_CAPCTRL4_CAPCONn_L10_Pos                          10                                                        /*!< SCT CAPCTRL4: CAPCONn_L10 Position  */
#define SCT_CAPCTRL4_CAPCONn_L10_Msk                          (0x01UL << SCT_CAPCTRL4_CAPCONn_L10_Pos)                  /*!< SCT CAPCTRL4: CAPCONn_L10 Mask      */
#define SCT_CAPCTRL4_CAPCONn_L11_Pos                          11                                                        /*!< SCT CAPCTRL4: CAPCONn_L11 Position  */
#define SCT_CAPCTRL4_CAPCONn_L11_Msk                          (0x01UL << SCT_CAPCTRL4_CAPCONn_L11_Pos)                  /*!< SCT CAPCTRL4: CAPCONn_L11 Mask      */
#define SCT_CAPCTRL4_CAPCONn_L12_Pos                          12                                                        /*!< SCT CAPCTRL4: CAPCONn_L12 Position  */
#define SCT_CAPCTRL4_CAPCONn_L12_Msk                          (0x01UL << SCT_CAPCTRL4_CAPCONn_L12_Pos)                  /*!< SCT CAPCTRL4: CAPCONn_L12 Mask      */
#define SCT_CAPCTRL4_CAPCONn_L13_Pos                          13                                                        /*!< SCT CAPCTRL4: CAPCONn_L13 Position  */
#define SCT_CAPCTRL4_CAPCONn_L13_Msk                          (0x01UL << SCT_CAPCTRL4_CAPCONn_L13_Pos)                  /*!< SCT CAPCTRL4: CAPCONn_L13 Mask      */
#define SCT_CAPCTRL4_CAPCONn_L14_Pos                          14                                                        /*!< SCT CAPCTRL4: CAPCONn_L14 Position  */
#define SCT_CAPCTRL4_CAPCONn_L14_Msk                          (0x01UL << SCT_CAPCTRL4_CAPCONn_L14_Pos)                  /*!< SCT CAPCTRL4: CAPCONn_L14 Mask      */
#define SCT_CAPCTRL4_CAPCONn_L15_Pos                          15                                                        /*!< SCT CAPCTRL4: CAPCONn_L15 Position  */
#define SCT_CAPCTRL4_CAPCONn_L15_Msk                          (0x01UL << SCT_CAPCTRL4_CAPCONn_L15_Pos)                  /*!< SCT CAPCTRL4: CAPCONn_L15 Mask      */
#define SCT_CAPCTRL4_CAPCONn_H_Pos                            16                                                        /*!< SCT CAPCTRL4: CAPCONn_H Position    */
#define SCT_CAPCTRL4_CAPCONn_H_Msk                            (0x0000ffffUL << SCT_CAPCTRL4_CAPCONn_H_Pos)              /*!< SCT CAPCTRL4: CAPCONn_H Mask        */

// --------------------------------------  SCT_MATCHREL4  -----------------------------------------
#define SCT_MATCHREL4_RELOADn_L_Pos                           0                                                         /*!< SCT MATCHREL4: RELOADn_L Position   */
#define SCT_MATCHREL4_RELOADn_L_Msk                           (0x0000ffffUL << SCT_MATCHREL4_RELOADn_L_Pos)             /*!< SCT MATCHREL4: RELOADn_L Mask       */
#define SCT_MATCHREL4_RELOADn_H_Pos                           16                                                        /*!< SCT MATCHREL4: RELOADn_H Position   */
#define SCT_MATCHREL4_RELOADn_H_Msk                           (0x0000ffffUL << SCT_MATCHREL4_RELOADn_H_Pos)             /*!< SCT MATCHREL4: RELOADn_H Mask       */

// --------------------------------------  SCT_CAPCTRL5  ------------------------------------------
#define SCT_CAPCTRL5_CAPCONn_L0_Pos                           0                                                         /*!< SCT CAPCTRL5: CAPCONn_L0 Position   */
#define SCT_CAPCTRL5_CAPCONn_L0_Msk                           (0x01UL << SCT_CAPCTRL5_CAPCONn_L0_Pos)                   /*!< SCT CAPCTRL5: CAPCONn_L0 Mask       */
#define SCT_CAPCTRL5_CAPCONn_L1_Pos                           1                                                         /*!< SCT CAPCTRL5: CAPCONn_L1 Position   */
#define SCT_CAPCTRL5_CAPCONn_L1_Msk                           (0x01UL << SCT_CAPCTRL5_CAPCONn_L1_Pos)                   /*!< SCT CAPCTRL5: CAPCONn_L1 Mask       */
#define SCT_CAPCTRL5_CAPCONn_L2_Pos                           2                                                         /*!< SCT CAPCTRL5: CAPCONn_L2 Position   */
#define SCT_CAPCTRL5_CAPCONn_L2_Msk                           (0x01UL << SCT_CAPCTRL5_CAPCONn_L2_Pos)                   /*!< SCT CAPCTRL5: CAPCONn_L2 Mask       */
#define SCT_CAPCTRL5_CAPCONn_L3_Pos                           3                                                         /*!< SCT CAPCTRL5: CAPCONn_L3 Position   */
#define SCT_CAPCTRL5_CAPCONn_L3_Msk                           (0x01UL << SCT_CAPCTRL5_CAPCONn_L3_Pos)                   /*!< SCT CAPCTRL5: CAPCONn_L3 Mask       */
#define SCT_CAPCTRL5_CAPCONn_L4_Pos                           4                                                         /*!< SCT CAPCTRL5: CAPCONn_L4 Position   */
#define SCT_CAPCTRL5_CAPCONn_L4_Msk                           (0x01UL << SCT_CAPCTRL5_CAPCONn_L4_Pos)                   /*!< SCT CAPCTRL5: CAPCONn_L4 Mask       */
#define SCT_CAPCTRL5_CAPCONn_L5_Pos                           5                                                         /*!< SCT CAPCTRL5: CAPCONn_L5 Position   */
#define SCT_CAPCTRL5_CAPCONn_L5_Msk                           (0x01UL << SCT_CAPCTRL5_CAPCONn_L5_Pos)                   /*!< SCT CAPCTRL5: CAPCONn_L5 Mask       */
#define SCT_CAPCTRL5_CAPCONn_L6_Pos                           6                                                         /*!< SCT CAPCTRL5: CAPCONn_L6 Position   */
#define SCT_CAPCTRL5_CAPCONn_L6_Msk                           (0x01UL << SCT_CAPCTRL5_CAPCONn_L6_Pos)                   /*!< SCT CAPCTRL5: CAPCONn_L6 Mask       */
#define SCT_CAPCTRL5_CAPCONn_L7_Pos                           7                                                         /*!< SCT CAPCTRL5: CAPCONn_L7 Position   */
#define SCT_CAPCTRL5_CAPCONn_L7_Msk                           (0x01UL << SCT_CAPCTRL5_CAPCONn_L7_Pos)                   /*!< SCT CAPCTRL5: CAPCONn_L7 Mask       */
#define SCT_CAPCTRL5_CAPCONn_L8_Pos                           8                                                         /*!< SCT CAPCTRL5: CAPCONn_L8 Position   */
#define SCT_CAPCTRL5_CAPCONn_L8_Msk                           (0x01UL << SCT_CAPCTRL5_CAPCONn_L8_Pos)                   /*!< SCT CAPCTRL5: CAPCONn_L8 Mask       */
#define SCT_CAPCTRL5_CAPCONn_L9_Pos                           9                                                         /*!< SCT CAPCTRL5: CAPCONn_L9 Position   */
#define SCT_CAPCTRL5_CAPCONn_L9_Msk                           (0x01UL << SCT_CAPCTRL5_CAPCONn_L9_Pos)                   /*!< SCT CAPCTRL5: CAPCONn_L9 Mask       */
#define SCT_CAPCTRL5_CAPCONn_L10_Pos                          10                                                        /*!< SCT CAPCTRL5: CAPCONn_L10 Position  */
#define SCT_CAPCTRL5_CAPCONn_L10_Msk                          (0x01UL << SCT_CAPCTRL5_CAPCONn_L10_Pos)                  /*!< SCT CAPCTRL5: CAPCONn_L10 Mask      */
#define SCT_CAPCTRL5_CAPCONn_L11_Pos                          11                                                        /*!< SCT CAPCTRL5: CAPCONn_L11 Position  */
#define SCT_CAPCTRL5_CAPCONn_L11_Msk                          (0x01UL << SCT_CAPCTRL5_CAPCONn_L11_Pos)                  /*!< SCT CAPCTRL5: CAPCONn_L11 Mask      */
#define SCT_CAPCTRL5_CAPCONn_L12_Pos                          12                                                        /*!< SCT CAPCTRL5: CAPCONn_L12 Position  */
#define SCT_CAPCTRL5_CAPCONn_L12_Msk                          (0x01UL << SCT_CAPCTRL5_CAPCONn_L12_Pos)                  /*!< SCT CAPCTRL5: CAPCONn_L12 Mask      */
#define SCT_CAPCTRL5_CAPCONn_L13_Pos                          13                                                        /*!< SCT CAPCTRL5: CAPCONn_L13 Position  */
#define SCT_CAPCTRL5_CAPCONn_L13_Msk                          (0x01UL << SCT_CAPCTRL5_CAPCONn_L13_Pos)                  /*!< SCT CAPCTRL5: CAPCONn_L13 Mask      */
#define SCT_CAPCTRL5_CAPCONn_L14_Pos                          14                                                        /*!< SCT CAPCTRL5: CAPCONn_L14 Position  */
#define SCT_CAPCTRL5_CAPCONn_L14_Msk                          (0x01UL << SCT_CAPCTRL5_CAPCONn_L14_Pos)                  /*!< SCT CAPCTRL5: CAPCONn_L14 Mask      */
#define SCT_CAPCTRL5_CAPCONn_L15_Pos                          15                                                        /*!< SCT CAPCTRL5: CAPCONn_L15 Position  */
#define SCT_CAPCTRL5_CAPCONn_L15_Msk                          (0x01UL << SCT_CAPCTRL5_CAPCONn_L15_Pos)                  /*!< SCT CAPCTRL5: CAPCONn_L15 Mask      */
#define SCT_CAPCTRL5_CAPCONn_H_Pos                            16                                                        /*!< SCT CAPCTRL5: CAPCONn_H Position    */
#define SCT_CAPCTRL5_CAPCONn_H_Msk                            (0x0000ffffUL << SCT_CAPCTRL5_CAPCONn_H_Pos)              /*!< SCT CAPCTRL5: CAPCONn_H Mask        */

// --------------------------------------  SCT_MATCHREL5  -----------------------------------------
#define SCT_MATCHREL5_RELOADn_L_Pos                           0                                                         /*!< SCT MATCHREL5: RELOADn_L Position   */
#define SCT_MATCHREL5_RELOADn_L_Msk                           (0x0000ffffUL << SCT_MATCHREL5_RELOADn_L_Pos)             /*!< SCT MATCHREL5: RELOADn_L Mask       */
#define SCT_MATCHREL5_RELOADn_H_Pos                           16                                                        /*!< SCT MATCHREL5: RELOADn_H Position   */
#define SCT_MATCHREL5_RELOADn_H_Msk                           (0x0000ffffUL << SCT_MATCHREL5_RELOADn_H_Pos)             /*!< SCT MATCHREL5: RELOADn_H Mask       */

// --------------------------------------  SCT_MATCHREL6  -----------------------------------------
#define SCT_MATCHREL6_RELOADn_L_Pos                           0                                                         /*!< SCT MATCHREL6: RELOADn_L Position   */
#define SCT_MATCHREL6_RELOADn_L_Msk                           (0x0000ffffUL << SCT_MATCHREL6_RELOADn_L_Pos)             /*!< SCT MATCHREL6: RELOADn_L Mask       */
#define SCT_MATCHREL6_RELOADn_H_Pos                           16                                                        /*!< SCT MATCHREL6: RELOADn_H Position   */
#define SCT_MATCHREL6_RELOADn_H_Msk                           (0x0000ffffUL << SCT_MATCHREL6_RELOADn_H_Pos)             /*!< SCT MATCHREL6: RELOADn_H Mask       */

// --------------------------------------  SCT_CAPCTRL6  ------------------------------------------
#define SCT_CAPCTRL6_CAPCONn_L0_Pos                           0                                                         /*!< SCT CAPCTRL6: CAPCONn_L0 Position   */
#define SCT_CAPCTRL6_CAPCONn_L0_Msk                           (0x01UL << SCT_CAPCTRL6_CAPCONn_L0_Pos)                   /*!< SCT CAPCTRL6: CAPCONn_L0 Mask       */
#define SCT_CAPCTRL6_CAPCONn_L1_Pos                           1                                                         /*!< SCT CAPCTRL6: CAPCONn_L1 Position   */
#define SCT_CAPCTRL6_CAPCONn_L1_Msk                           (0x01UL << SCT_CAPCTRL6_CAPCONn_L1_Pos)                   /*!< SCT CAPCTRL6: CAPCONn_L1 Mask       */
#define SCT_CAPCTRL6_CAPCONn_L2_Pos                           2                                                         /*!< SCT CAPCTRL6: CAPCONn_L2 Position   */
#define SCT_CAPCTRL6_CAPCONn_L2_Msk                           (0x01UL << SCT_CAPCTRL6_CAPCONn_L2_Pos)                   /*!< SCT CAPCTRL6: CAPCONn_L2 Mask       */
#define SCT_CAPCTRL6_CAPCONn_L3_Pos                           3                                                         /*!< SCT CAPCTRL6: CAPCONn_L3 Position   */
#define SCT_CAPCTRL6_CAPCONn_L3_Msk                           (0x01UL << SCT_CAPCTRL6_CAPCONn_L3_Pos)                   /*!< SCT CAPCTRL6: CAPCONn_L3 Mask       */
#define SCT_CAPCTRL6_CAPCONn_L4_Pos                           4                                                         /*!< SCT CAPCTRL6: CAPCONn_L4 Position   */
#define SCT_CAPCTRL6_CAPCONn_L4_Msk                           (0x01UL << SCT_CAPCTRL6_CAPCONn_L4_Pos)                   /*!< SCT CAPCTRL6: CAPCONn_L4 Mask       */
#define SCT_CAPCTRL6_CAPCONn_L5_Pos                           5                                                         /*!< SCT CAPCTRL6: CAPCONn_L5 Position   */
#define SCT_CAPCTRL6_CAPCONn_L5_Msk                           (0x01UL << SCT_CAPCTRL6_CAPCONn_L5_Pos)                   /*!< SCT CAPCTRL6: CAPCONn_L5 Mask       */
#define SCT_CAPCTRL6_CAPCONn_L6_Pos                           6                                                         /*!< SCT CAPCTRL6: CAPCONn_L6 Position   */
#define SCT_CAPCTRL6_CAPCONn_L6_Msk                           (0x01UL << SCT_CAPCTRL6_CAPCONn_L6_Pos)                   /*!< SCT CAPCTRL6: CAPCONn_L6 Mask       */
#define SCT_CAPCTRL6_CAPCONn_L7_Pos                           7                                                         /*!< SCT CAPCTRL6: CAPCONn_L7 Position   */
#define SCT_CAPCTRL6_CAPCONn_L7_Msk                           (0x01UL << SCT_CAPCTRL6_CAPCONn_L7_Pos)                   /*!< SCT CAPCTRL6: CAPCONn_L7 Mask       */
#define SCT_CAPCTRL6_CAPCONn_L8_Pos                           8                                                         /*!< SCT CAPCTRL6: CAPCONn_L8 Position   */
#define SCT_CAPCTRL6_CAPCONn_L8_Msk                           (0x01UL << SCT_CAPCTRL6_CAPCONn_L8_Pos)                   /*!< SCT CAPCTRL6: CAPCONn_L8 Mask       */
#define SCT_CAPCTRL6_CAPCONn_L9_Pos                           9                                                         /*!< SCT CAPCTRL6: CAPCONn_L9 Position   */
#define SCT_CAPCTRL6_CAPCONn_L9_Msk                           (0x01UL << SCT_CAPCTRL6_CAPCONn_L9_Pos)                   /*!< SCT CAPCTRL6: CAPCONn_L9 Mask       */
#define SCT_CAPCTRL6_CAPCONn_L10_Pos                          10                                                        /*!< SCT CAPCTRL6: CAPCONn_L10 Position  */
#define SCT_CAPCTRL6_CAPCONn_L10_Msk                          (0x01UL << SCT_CAPCTRL6_CAPCONn_L10_Pos)                  /*!< SCT CAPCTRL6: CAPCONn_L10 Mask      */
#define SCT_CAPCTRL6_CAPCONn_L11_Pos                          11                                                        /*!< SCT CAPCTRL6: CAPCONn_L11 Position  */
#define SCT_CAPCTRL6_CAPCONn_L11_Msk                          (0x01UL << SCT_CAPCTRL6_CAPCONn_L11_Pos)                  /*!< SCT CAPCTRL6: CAPCONn_L11 Mask      */
#define SCT_CAPCTRL6_CAPCONn_L12_Pos                          12                                                        /*!< SCT CAPCTRL6: CAPCONn_L12 Position  */
#define SCT_CAPCTRL6_CAPCONn_L12_Msk                          (0x01UL << SCT_CAPCTRL6_CAPCONn_L12_Pos)                  /*!< SCT CAPCTRL6: CAPCONn_L12 Mask      */
#define SCT_CAPCTRL6_CAPCONn_L13_Pos                          13                                                        /*!< SCT CAPCTRL6: CAPCONn_L13 Position  */
#define SCT_CAPCTRL6_CAPCONn_L13_Msk                          (0x01UL << SCT_CAPCTRL6_CAPCONn_L13_Pos)                  /*!< SCT CAPCTRL6: CAPCONn_L13 Mask      */
#define SCT_CAPCTRL6_CAPCONn_L14_Pos                          14                                                        /*!< SCT CAPCTRL6: CAPCONn_L14 Position  */
#define SCT_CAPCTRL6_CAPCONn_L14_Msk                          (0x01UL << SCT_CAPCTRL6_CAPCONn_L14_Pos)                  /*!< SCT CAPCTRL6: CAPCONn_L14 Mask      */
#define SCT_CAPCTRL6_CAPCONn_L15_Pos                          15                                                        /*!< SCT CAPCTRL6: CAPCONn_L15 Position  */
#define SCT_CAPCTRL6_CAPCONn_L15_Msk                          (0x01UL << SCT_CAPCTRL6_CAPCONn_L15_Pos)                  /*!< SCT CAPCTRL6: CAPCONn_L15 Mask      */
#define SCT_CAPCTRL6_CAPCONn_H_Pos                            16                                                        /*!< SCT CAPCTRL6: CAPCONn_H Position    */
#define SCT_CAPCTRL6_CAPCONn_H_Msk                            (0x0000ffffUL << SCT_CAPCTRL6_CAPCONn_H_Pos)              /*!< SCT CAPCTRL6: CAPCONn_H Mask        */

// --------------------------------------  SCT_CAPCTRL7  ------------------------------------------
#define SCT_CAPCTRL7_CAPCONn_L0_Pos                           0                                                         /*!< SCT CAPCTRL7: CAPCONn_L0 Position   */
#define SCT_CAPCTRL7_CAPCONn_L0_Msk                           (0x01UL << SCT_CAPCTRL7_CAPCONn_L0_Pos)                   /*!< SCT CAPCTRL7: CAPCONn_L0 Mask       */
#define SCT_CAPCTRL7_CAPCONn_L1_Pos                           1                                                         /*!< SCT CAPCTRL7: CAPCONn_L1 Position   */
#define SCT_CAPCTRL7_CAPCONn_L1_Msk                           (0x01UL << SCT_CAPCTRL7_CAPCONn_L1_Pos)                   /*!< SCT CAPCTRL7: CAPCONn_L1 Mask       */
#define SCT_CAPCTRL7_CAPCONn_L2_Pos                           2                                                         /*!< SCT CAPCTRL7: CAPCONn_L2 Position   */
#define SCT_CAPCTRL7_CAPCONn_L2_Msk                           (0x01UL << SCT_CAPCTRL7_CAPCONn_L2_Pos)                   /*!< SCT CAPCTRL7: CAPCONn_L2 Mask       */
#define SCT_CAPCTRL7_CAPCONn_L3_Pos                           3                                                         /*!< SCT CAPCTRL7: CAPCONn_L3 Position   */
#define SCT_CAPCTRL7_CAPCONn_L3_Msk                           (0x01UL << SCT_CAPCTRL7_CAPCONn_L3_Pos)                   /*!< SCT CAPCTRL7: CAPCONn_L3 Mask       */
#define SCT_CAPCTRL7_CAPCONn_L4_Pos                           4                                                         /*!< SCT CAPCTRL7: CAPCONn_L4 Position   */
#define SCT_CAPCTRL7_CAPCONn_L4_Msk                           (0x01UL << SCT_CAPCTRL7_CAPCONn_L4_Pos)                   /*!< SCT CAPCTRL7: CAPCONn_L4 Mask       */
#define SCT_CAPCTRL7_CAPCONn_L5_Pos                           5                                                         /*!< SCT CAPCTRL7: CAPCONn_L5 Position   */
#define SCT_CAPCTRL7_CAPCONn_L5_Msk                           (0x01UL << SCT_CAPCTRL7_CAPCONn_L5_Pos)                   /*!< SCT CAPCTRL7: CAPCONn_L5 Mask       */
#define SCT_CAPCTRL7_CAPCONn_L6_Pos                           6                                                         /*!< SCT CAPCTRL7: CAPCONn_L6 Position   */
#define SCT_CAPCTRL7_CAPCONn_L6_Msk                           (0x01UL << SCT_CAPCTRL7_CAPCONn_L6_Pos)                   /*!< SCT CAPCTRL7: CAPCONn_L6 Mask       */
#define SCT_CAPCTRL7_CAPCONn_L7_Pos                           7                                                         /*!< SCT CAPCTRL7: CAPCONn_L7 Position   */
#define SCT_CAPCTRL7_CAPCONn_L7_Msk                           (0x01UL << SCT_CAPCTRL7_CAPCONn_L7_Pos)                   /*!< SCT CAPCTRL7: CAPCONn_L7 Mask       */
#define SCT_CAPCTRL7_CAPCONn_L8_Pos                           8                                                         /*!< SCT CAPCTRL7: CAPCONn_L8 Position   */
#define SCT_CAPCTRL7_CAPCONn_L8_Msk                           (0x01UL << SCT_CAPCTRL7_CAPCONn_L8_Pos)                   /*!< SCT CAPCTRL7: CAPCONn_L8 Mask       */
#define SCT_CAPCTRL7_CAPCONn_L9_Pos                           9                                                         /*!< SCT CAPCTRL7: CAPCONn_L9 Position   */
#define SCT_CAPCTRL7_CAPCONn_L9_Msk                           (0x01UL << SCT_CAPCTRL7_CAPCONn_L9_Pos)                   /*!< SCT CAPCTRL7: CAPCONn_L9 Mask       */
#define SCT_CAPCTRL7_CAPCONn_L10_Pos                          10                                                        /*!< SCT CAPCTRL7: CAPCONn_L10 Position  */
#define SCT_CAPCTRL7_CAPCONn_L10_Msk                          (0x01UL << SCT_CAPCTRL7_CAPCONn_L10_Pos)                  /*!< SCT CAPCTRL7: CAPCONn_L10 Mask      */
#define SCT_CAPCTRL7_CAPCONn_L11_Pos                          11                                                        /*!< SCT CAPCTRL7: CAPCONn_L11 Position  */
#define SCT_CAPCTRL7_CAPCONn_L11_Msk                          (0x01UL << SCT_CAPCTRL7_CAPCONn_L11_Pos)                  /*!< SCT CAPCTRL7: CAPCONn_L11 Mask      */
#define SCT_CAPCTRL7_CAPCONn_L12_Pos                          12                                                        /*!< SCT CAPCTRL7: CAPCONn_L12 Position  */
#define SCT_CAPCTRL7_CAPCONn_L12_Msk                          (0x01UL << SCT_CAPCTRL7_CAPCONn_L12_Pos)                  /*!< SCT CAPCTRL7: CAPCONn_L12 Mask      */
#define SCT_CAPCTRL7_CAPCONn_L13_Pos                          13                                                        /*!< SCT CAPCTRL7: CAPCONn_L13 Position  */
#define SCT_CAPCTRL7_CAPCONn_L13_Msk                          (0x01UL << SCT_CAPCTRL7_CAPCONn_L13_Pos)                  /*!< SCT CAPCTRL7: CAPCONn_L13 Mask      */
#define SCT_CAPCTRL7_CAPCONn_L14_Pos                          14                                                        /*!< SCT CAPCTRL7: CAPCONn_L14 Position  */
#define SCT_CAPCTRL7_CAPCONn_L14_Msk                          (0x01UL << SCT_CAPCTRL7_CAPCONn_L14_Pos)                  /*!< SCT CAPCTRL7: CAPCONn_L14 Mask      */
#define SCT_CAPCTRL7_CAPCONn_L15_Pos                          15                                                        /*!< SCT CAPCTRL7: CAPCONn_L15 Position  */
#define SCT_CAPCTRL7_CAPCONn_L15_Msk                          (0x01UL << SCT_CAPCTRL7_CAPCONn_L15_Pos)                  /*!< SCT CAPCTRL7: CAPCONn_L15 Mask      */
#define SCT_CAPCTRL7_CAPCONn_H_Pos                            16                                                        /*!< SCT CAPCTRL7: CAPCONn_H Position    */
#define SCT_CAPCTRL7_CAPCONn_H_Msk                            (0x0000ffffUL << SCT_CAPCTRL7_CAPCONn_H_Pos)              /*!< SCT CAPCTRL7: CAPCONn_H Mask        */

// --------------------------------------  SCT_MATCHREL7  -----------------------------------------
#define SCT_MATCHREL7_RELOADn_L_Pos                           0                                                         /*!< SCT MATCHREL7: RELOADn_L Position   */
#define SCT_MATCHREL7_RELOADn_L_Msk                           (0x0000ffffUL << SCT_MATCHREL7_RELOADn_L_Pos)             /*!< SCT MATCHREL7: RELOADn_L Mask       */
#define SCT_MATCHREL7_RELOADn_H_Pos                           16                                                        /*!< SCT MATCHREL7: RELOADn_H Position   */
#define SCT_MATCHREL7_RELOADn_H_Msk                           (0x0000ffffUL << SCT_MATCHREL7_RELOADn_H_Pos)             /*!< SCT MATCHREL7: RELOADn_H Mask       */

// --------------------------------------  SCT_CAPCTRL8  ------------------------------------------
#define SCT_CAPCTRL8_CAPCONn_L0_Pos                           0                                                         /*!< SCT CAPCTRL8: CAPCONn_L0 Position   */
#define SCT_CAPCTRL8_CAPCONn_L0_Msk                           (0x01UL << SCT_CAPCTRL8_CAPCONn_L0_Pos)                   /*!< SCT CAPCTRL8: CAPCONn_L0 Mask       */
#define SCT_CAPCTRL8_CAPCONn_L1_Pos                           1                                                         /*!< SCT CAPCTRL8: CAPCONn_L1 Position   */
#define SCT_CAPCTRL8_CAPCONn_L1_Msk                           (0x01UL << SCT_CAPCTRL8_CAPCONn_L1_Pos)                   /*!< SCT CAPCTRL8: CAPCONn_L1 Mask       */
#define SCT_CAPCTRL8_CAPCONn_L2_Pos                           2                                                         /*!< SCT CAPCTRL8: CAPCONn_L2 Position   */
#define SCT_CAPCTRL8_CAPCONn_L2_Msk                           (0x01UL << SCT_CAPCTRL8_CAPCONn_L2_Pos)                   /*!< SCT CAPCTRL8: CAPCONn_L2 Mask       */
#define SCT_CAPCTRL8_CAPCONn_L3_Pos                           3                                                         /*!< SCT CAPCTRL8: CAPCONn_L3 Position   */
#define SCT_CAPCTRL8_CAPCONn_L3_Msk                           (0x01UL << SCT_CAPCTRL8_CAPCONn_L3_Pos)                   /*!< SCT CAPCTRL8: CAPCONn_L3 Mask       */
#define SCT_CAPCTRL8_CAPCONn_L4_Pos                           4                                                         /*!< SCT CAPCTRL8: CAPCONn_L4 Position   */
#define SCT_CAPCTRL8_CAPCONn_L4_Msk                           (0x01UL << SCT_CAPCTRL8_CAPCONn_L4_Pos)                   /*!< SCT CAPCTRL8: CAPCONn_L4 Mask       */
#define SCT_CAPCTRL8_CAPCONn_L5_Pos                           5                                                         /*!< SCT CAPCTRL8: CAPCONn_L5 Position   */
#define SCT_CAPCTRL8_CAPCONn_L5_Msk                           (0x01UL << SCT_CAPCTRL8_CAPCONn_L5_Pos)                   /*!< SCT CAPCTRL8: CAPCONn_L5 Mask       */
#define SCT_CAPCTRL8_CAPCONn_L6_Pos                           6                                                         /*!< SCT CAPCTRL8: CAPCONn_L6 Position   */
#define SCT_CAPCTRL8_CAPCONn_L6_Msk                           (0x01UL << SCT_CAPCTRL8_CAPCONn_L6_Pos)                   /*!< SCT CAPCTRL8: CAPCONn_L6 Mask       */
#define SCT_CAPCTRL8_CAPCONn_L7_Pos                           7                                                         /*!< SCT CAPCTRL8: CAPCONn_L7 Position   */
#define SCT_CAPCTRL8_CAPCONn_L7_Msk                           (0x01UL << SCT_CAPCTRL8_CAPCONn_L7_Pos)                   /*!< SCT CAPCTRL8: CAPCONn_L7 Mask       */
#define SCT_CAPCTRL8_CAPCONn_L8_Pos                           8                                                         /*!< SCT CAPCTRL8: CAPCONn_L8 Position   */
#define SCT_CAPCTRL8_CAPCONn_L8_Msk                           (0x01UL << SCT_CAPCTRL8_CAPCONn_L8_Pos)                   /*!< SCT CAPCTRL8: CAPCONn_L8 Mask       */
#define SCT_CAPCTRL8_CAPCONn_L9_Pos                           9                                                         /*!< SCT CAPCTRL8: CAPCONn_L9 Position   */
#define SCT_CAPCTRL8_CAPCONn_L9_Msk                           (0x01UL << SCT_CAPCTRL8_CAPCONn_L9_Pos)                   /*!< SCT CAPCTRL8: CAPCONn_L9 Mask       */
#define SCT_CAPCTRL8_CAPCONn_L10_Pos                          10                                                        /*!< SCT CAPCTRL8: CAPCONn_L10 Position  */
#define SCT_CAPCTRL8_CAPCONn_L10_Msk                          (0x01UL << SCT_CAPCTRL8_CAPCONn_L10_Pos)                  /*!< SCT CAPCTRL8: CAPCONn_L10 Mask      */
#define SCT_CAPCTRL8_CAPCONn_L11_Pos                          11                                                        /*!< SCT CAPCTRL8: CAPCONn_L11 Position  */
#define SCT_CAPCTRL8_CAPCONn_L11_Msk                          (0x01UL << SCT_CAPCTRL8_CAPCONn_L11_Pos)                  /*!< SCT CAPCTRL8: CAPCONn_L11 Mask      */
#define SCT_CAPCTRL8_CAPCONn_L12_Pos                          12                                                        /*!< SCT CAPCTRL8: CAPCONn_L12 Position  */
#define SCT_CAPCTRL8_CAPCONn_L12_Msk                          (0x01UL << SCT_CAPCTRL8_CAPCONn_L12_Pos)                  /*!< SCT CAPCTRL8: CAPCONn_L12 Mask      */
#define SCT_CAPCTRL8_CAPCONn_L13_Pos                          13                                                        /*!< SCT CAPCTRL8: CAPCONn_L13 Position  */
#define SCT_CAPCTRL8_CAPCONn_L13_Msk                          (0x01UL << SCT_CAPCTRL8_CAPCONn_L13_Pos)                  /*!< SCT CAPCTRL8: CAPCONn_L13 Mask      */
#define SCT_CAPCTRL8_CAPCONn_L14_Pos                          14                                                        /*!< SCT CAPCTRL8: CAPCONn_L14 Position  */
#define SCT_CAPCTRL8_CAPCONn_L14_Msk                          (0x01UL << SCT_CAPCTRL8_CAPCONn_L14_Pos)                  /*!< SCT CAPCTRL8: CAPCONn_L14 Mask      */
#define SCT_CAPCTRL8_CAPCONn_L15_Pos                          15                                                        /*!< SCT CAPCTRL8: CAPCONn_L15 Position  */
#define SCT_CAPCTRL8_CAPCONn_L15_Msk                          (0x01UL << SCT_CAPCTRL8_CAPCONn_L15_Pos)                  /*!< SCT CAPCTRL8: CAPCONn_L15 Mask      */
#define SCT_CAPCTRL8_CAPCONn_H_Pos                            16                                                        /*!< SCT CAPCTRL8: CAPCONn_H Position    */
#define SCT_CAPCTRL8_CAPCONn_H_Msk                            (0x0000ffffUL << SCT_CAPCTRL8_CAPCONn_H_Pos)              /*!< SCT CAPCTRL8: CAPCONn_H Mask        */

// --------------------------------------  SCT_MATCHREL8  -----------------------------------------
#define SCT_MATCHREL8_RELOADn_L_Pos                           0                                                         /*!< SCT MATCHREL8: RELOADn_L Position   */
#define SCT_MATCHREL8_RELOADn_L_Msk                           (0x0000ffffUL << SCT_MATCHREL8_RELOADn_L_Pos)             /*!< SCT MATCHREL8: RELOADn_L Mask       */
#define SCT_MATCHREL8_RELOADn_H_Pos                           16                                                        /*!< SCT MATCHREL8: RELOADn_H Position   */
#define SCT_MATCHREL8_RELOADn_H_Msk                           (0x0000ffffUL << SCT_MATCHREL8_RELOADn_H_Pos)             /*!< SCT MATCHREL8: RELOADn_H Mask       */

// --------------------------------------  SCT_MATCHREL9  -----------------------------------------
#define SCT_MATCHREL9_RELOADn_L_Pos                           0                                                         /*!< SCT MATCHREL9: RELOADn_L Position   */
#define SCT_MATCHREL9_RELOADn_L_Msk                           (0x0000ffffUL << SCT_MATCHREL9_RELOADn_L_Pos)             /*!< SCT MATCHREL9: RELOADn_L Mask       */
#define SCT_MATCHREL9_RELOADn_H_Pos                           16                                                        /*!< SCT MATCHREL9: RELOADn_H Position   */
#define SCT_MATCHREL9_RELOADn_H_Msk                           (0x0000ffffUL << SCT_MATCHREL9_RELOADn_H_Pos)             /*!< SCT MATCHREL9: RELOADn_H Mask       */

// --------------------------------------  SCT_CAPCTRL9  ------------------------------------------
#define SCT_CAPCTRL9_CAPCONn_L0_Pos                           0                                                         /*!< SCT CAPCTRL9: CAPCONn_L0 Position   */
#define SCT_CAPCTRL9_CAPCONn_L0_Msk                           (0x01UL << SCT_CAPCTRL9_CAPCONn_L0_Pos)                   /*!< SCT CAPCTRL9: CAPCONn_L0 Mask       */
#define SCT_CAPCTRL9_CAPCONn_L1_Pos                           1                                                         /*!< SCT CAPCTRL9: CAPCONn_L1 Position   */
#define SCT_CAPCTRL9_CAPCONn_L1_Msk                           (0x01UL << SCT_CAPCTRL9_CAPCONn_L1_Pos)                   /*!< SCT CAPCTRL9: CAPCONn_L1 Mask       */
#define SCT_CAPCTRL9_CAPCONn_L2_Pos                           2                                                         /*!< SCT CAPCTRL9: CAPCONn_L2 Position   */
#define SCT_CAPCTRL9_CAPCONn_L2_Msk                           (0x01UL << SCT_CAPCTRL9_CAPCONn_L2_Pos)                   /*!< SCT CAPCTRL9: CAPCONn_L2 Mask       */
#define SCT_CAPCTRL9_CAPCONn_L3_Pos                           3                                                         /*!< SCT CAPCTRL9: CAPCONn_L3 Position   */
#define SCT_CAPCTRL9_CAPCONn_L3_Msk                           (0x01UL << SCT_CAPCTRL9_CAPCONn_L3_Pos)                   /*!< SCT CAPCTRL9: CAPCONn_L3 Mask       */
#define SCT_CAPCTRL9_CAPCONn_L4_Pos                           4                                                         /*!< SCT CAPCTRL9: CAPCONn_L4 Position   */
#define SCT_CAPCTRL9_CAPCONn_L4_Msk                           (0x01UL << SCT_CAPCTRL9_CAPCONn_L4_Pos)                   /*!< SCT CAPCTRL9: CAPCONn_L4 Mask       */
#define SCT_CAPCTRL9_CAPCONn_L5_Pos                           5                                                         /*!< SCT CAPCTRL9: CAPCONn_L5 Position   */
#define SCT_CAPCTRL9_CAPCONn_L5_Msk                           (0x01UL << SCT_CAPCTRL9_CAPCONn_L5_Pos)                   /*!< SCT CAPCTRL9: CAPCONn_L5 Mask       */
#define SCT_CAPCTRL9_CAPCONn_L6_Pos                           6                                                         /*!< SCT CAPCTRL9: CAPCONn_L6 Position   */
#define SCT_CAPCTRL9_CAPCONn_L6_Msk                           (0x01UL << SCT_CAPCTRL9_CAPCONn_L6_Pos)                   /*!< SCT CAPCTRL9: CAPCONn_L6 Mask       */
#define SCT_CAPCTRL9_CAPCONn_L7_Pos                           7                                                         /*!< SCT CAPCTRL9: CAPCONn_L7 Position   */
#define SCT_CAPCTRL9_CAPCONn_L7_Msk                           (0x01UL << SCT_CAPCTRL9_CAPCONn_L7_Pos)                   /*!< SCT CAPCTRL9: CAPCONn_L7 Mask       */
#define SCT_CAPCTRL9_CAPCONn_L8_Pos                           8                                                         /*!< SCT CAPCTRL9: CAPCONn_L8 Position   */
#define SCT_CAPCTRL9_CAPCONn_L8_Msk                           (0x01UL << SCT_CAPCTRL9_CAPCONn_L8_Pos)                   /*!< SCT CAPCTRL9: CAPCONn_L8 Mask       */
#define SCT_CAPCTRL9_CAPCONn_L9_Pos                           9                                                         /*!< SCT CAPCTRL9: CAPCONn_L9 Position   */
#define SCT_CAPCTRL9_CAPCONn_L9_Msk                           (0x01UL << SCT_CAPCTRL9_CAPCONn_L9_Pos)                   /*!< SCT CAPCTRL9: CAPCONn_L9 Mask       */
#define SCT_CAPCTRL9_CAPCONn_L10_Pos                          10                                                        /*!< SCT CAPCTRL9: CAPCONn_L10 Position  */
#define SCT_CAPCTRL9_CAPCONn_L10_Msk                          (0x01UL << SCT_CAPCTRL9_CAPCONn_L10_Pos)                  /*!< SCT CAPCTRL9: CAPCONn_L10 Mask      */
#define SCT_CAPCTRL9_CAPCONn_L11_Pos                          11                                                        /*!< SCT CAPCTRL9: CAPCONn_L11 Position  */
#define SCT_CAPCTRL9_CAPCONn_L11_Msk                          (0x01UL << SCT_CAPCTRL9_CAPCONn_L11_Pos)                  /*!< SCT CAPCTRL9: CAPCONn_L11 Mask      */
#define SCT_CAPCTRL9_CAPCONn_L12_Pos                          12                                                        /*!< SCT CAPCTRL9: CAPCONn_L12 Position  */
#define SCT_CAPCTRL9_CAPCONn_L12_Msk                          (0x01UL << SCT_CAPCTRL9_CAPCONn_L12_Pos)                  /*!< SCT CAPCTRL9: CAPCONn_L12 Mask      */
#define SCT_CAPCTRL9_CAPCONn_L13_Pos                          13                                                        /*!< SCT CAPCTRL9: CAPCONn_L13 Position  */
#define SCT_CAPCTRL9_CAPCONn_L13_Msk                          (0x01UL << SCT_CAPCTRL9_CAPCONn_L13_Pos)                  /*!< SCT CAPCTRL9: CAPCONn_L13 Mask      */
#define SCT_CAPCTRL9_CAPCONn_L14_Pos                          14                                                        /*!< SCT CAPCTRL9: CAPCONn_L14 Position  */
#define SCT_CAPCTRL9_CAPCONn_L14_Msk                          (0x01UL << SCT_CAPCTRL9_CAPCONn_L14_Pos)                  /*!< SCT CAPCTRL9: CAPCONn_L14 Mask      */
#define SCT_CAPCTRL9_CAPCONn_L15_Pos                          15                                                        /*!< SCT CAPCTRL9: CAPCONn_L15 Position  */
#define SCT_CAPCTRL9_CAPCONn_L15_Msk                          (0x01UL << SCT_CAPCTRL9_CAPCONn_L15_Pos)                  /*!< SCT CAPCTRL9: CAPCONn_L15 Mask      */
#define SCT_CAPCTRL9_CAPCONn_H_Pos                            16                                                        /*!< SCT CAPCTRL9: CAPCONn_H Position    */
#define SCT_CAPCTRL9_CAPCONn_H_Msk                            (0x0000ffffUL << SCT_CAPCTRL9_CAPCONn_H_Pos)              /*!< SCT CAPCTRL9: CAPCONn_H Mask        */

// -------------------------------------  SCT_MATCHREL10  -----------------------------------------
#define SCT_MATCHREL10_RELOADn_L_Pos                          0                                                         /*!< SCT MATCHREL10: RELOADn_L Position  */
#define SCT_MATCHREL10_RELOADn_L_Msk                          (0x0000ffffUL << SCT_MATCHREL10_RELOADn_L_Pos)            /*!< SCT MATCHREL10: RELOADn_L Mask      */
#define SCT_MATCHREL10_RELOADn_H_Pos                          16                                                        /*!< SCT MATCHREL10: RELOADn_H Position  */
#define SCT_MATCHREL10_RELOADn_H_Msk                          (0x0000ffffUL << SCT_MATCHREL10_RELOADn_H_Pos)            /*!< SCT MATCHREL10: RELOADn_H Mask      */

// --------------------------------------  SCT_CAPCTRL10  -----------------------------------------
#define SCT_CAPCTRL10_CAPCONn_L0_Pos                          0                                                         /*!< SCT CAPCTRL10: CAPCONn_L0 Position  */
#define SCT_CAPCTRL10_CAPCONn_L0_Msk                          (0x01UL << SCT_CAPCTRL10_CAPCONn_L0_Pos)                  /*!< SCT CAPCTRL10: CAPCONn_L0 Mask      */
#define SCT_CAPCTRL10_CAPCONn_L1_Pos                          1                                                         /*!< SCT CAPCTRL10: CAPCONn_L1 Position  */
#define SCT_CAPCTRL10_CAPCONn_L1_Msk                          (0x01UL << SCT_CAPCTRL10_CAPCONn_L1_Pos)                  /*!< SCT CAPCTRL10: CAPCONn_L1 Mask      */
#define SCT_CAPCTRL10_CAPCONn_L2_Pos                          2                                                         /*!< SCT CAPCTRL10: CAPCONn_L2 Position  */
#define SCT_CAPCTRL10_CAPCONn_L2_Msk                          (0x01UL << SCT_CAPCTRL10_CAPCONn_L2_Pos)                  /*!< SCT CAPCTRL10: CAPCONn_L2 Mask      */
#define SCT_CAPCTRL10_CAPCONn_L3_Pos                          3                                                         /*!< SCT CAPCTRL10: CAPCONn_L3 Position  */
#define SCT_CAPCTRL10_CAPCONn_L3_Msk                          (0x01UL << SCT_CAPCTRL10_CAPCONn_L3_Pos)                  /*!< SCT CAPCTRL10: CAPCONn_L3 Mask      */
#define SCT_CAPCTRL10_CAPCONn_L4_Pos                          4                                                         /*!< SCT CAPCTRL10: CAPCONn_L4 Position  */
#define SCT_CAPCTRL10_CAPCONn_L4_Msk                          (0x01UL << SCT_CAPCTRL10_CAPCONn_L4_Pos)                  /*!< SCT CAPCTRL10: CAPCONn_L4 Mask      */
#define SCT_CAPCTRL10_CAPCONn_L5_Pos                          5                                                         /*!< SCT CAPCTRL10: CAPCONn_L5 Position  */
#define SCT_CAPCTRL10_CAPCONn_L5_Msk                          (0x01UL << SCT_CAPCTRL10_CAPCONn_L5_Pos)                  /*!< SCT CAPCTRL10: CAPCONn_L5 Mask      */
#define SCT_CAPCTRL10_CAPCONn_L6_Pos                          6                                                         /*!< SCT CAPCTRL10: CAPCONn_L6 Position  */
#define SCT_CAPCTRL10_CAPCONn_L6_Msk                          (0x01UL << SCT_CAPCTRL10_CAPCONn_L6_Pos)                  /*!< SCT CAPCTRL10: CAPCONn_L6 Mask      */
#define SCT_CAPCTRL10_CAPCONn_L7_Pos                          7                                                         /*!< SCT CAPCTRL10: CAPCONn_L7 Position  */
#define SCT_CAPCTRL10_CAPCONn_L7_Msk                          (0x01UL << SCT_CAPCTRL10_CAPCONn_L7_Pos)                  /*!< SCT CAPCTRL10: CAPCONn_L7 Mask      */
#define SCT_CAPCTRL10_CAPCONn_L8_Pos                          8                                                         /*!< SCT CAPCTRL10: CAPCONn_L8 Position  */
#define SCT_CAPCTRL10_CAPCONn_L8_Msk                          (0x01UL << SCT_CAPCTRL10_CAPCONn_L8_Pos)                  /*!< SCT CAPCTRL10: CAPCONn_L8 Mask      */
#define SCT_CAPCTRL10_CAPCONn_L9_Pos                          9                                                         /*!< SCT CAPCTRL10: CAPCONn_L9 Position  */
#define SCT_CAPCTRL10_CAPCONn_L9_Msk                          (0x01UL << SCT_CAPCTRL10_CAPCONn_L9_Pos)                  /*!< SCT CAPCTRL10: CAPCONn_L9 Mask      */
#define SCT_CAPCTRL10_CAPCONn_L10_Pos                         10                                                        /*!< SCT CAPCTRL10: CAPCONn_L10 Position */
#define SCT_CAPCTRL10_CAPCONn_L10_Msk                         (0x01UL << SCT_CAPCTRL10_CAPCONn_L10_Pos)                 /*!< SCT CAPCTRL10: CAPCONn_L10 Mask     */
#define SCT_CAPCTRL10_CAPCONn_L11_Pos                         11                                                        /*!< SCT CAPCTRL10: CAPCONn_L11 Position */
#define SCT_CAPCTRL10_CAPCONn_L11_Msk                         (0x01UL << SCT_CAPCTRL10_CAPCONn_L11_Pos)                 /*!< SCT CAPCTRL10: CAPCONn_L11 Mask     */
#define SCT_CAPCTRL10_CAPCONn_L12_Pos                         12                                                        /*!< SCT CAPCTRL10: CAPCONn_L12 Position */
#define SCT_CAPCTRL10_CAPCONn_L12_Msk                         (0x01UL << SCT_CAPCTRL10_CAPCONn_L12_Pos)                 /*!< SCT CAPCTRL10: CAPCONn_L12 Mask     */
#define SCT_CAPCTRL10_CAPCONn_L13_Pos                         13                                                        /*!< SCT CAPCTRL10: CAPCONn_L13 Position */
#define SCT_CAPCTRL10_CAPCONn_L13_Msk                         (0x01UL << SCT_CAPCTRL10_CAPCONn_L13_Pos)                 /*!< SCT CAPCTRL10: CAPCONn_L13 Mask     */
#define SCT_CAPCTRL10_CAPCONn_L14_Pos                         14                                                        /*!< SCT CAPCTRL10: CAPCONn_L14 Position */
#define SCT_CAPCTRL10_CAPCONn_L14_Msk                         (0x01UL << SCT_CAPCTRL10_CAPCONn_L14_Pos)                 /*!< SCT CAPCTRL10: CAPCONn_L14 Mask     */
#define SCT_CAPCTRL10_CAPCONn_L15_Pos                         15                                                        /*!< SCT CAPCTRL10: CAPCONn_L15 Position */
#define SCT_CAPCTRL10_CAPCONn_L15_Msk                         (0x01UL << SCT_CAPCTRL10_CAPCONn_L15_Pos)                 /*!< SCT CAPCTRL10: CAPCONn_L15 Mask     */
#define SCT_CAPCTRL10_CAPCONn_H_Pos                           16                                                        /*!< SCT CAPCTRL10: CAPCONn_H Position   */
#define SCT_CAPCTRL10_CAPCONn_H_Msk                           (0x0000ffffUL << SCT_CAPCTRL10_CAPCONn_H_Pos)             /*!< SCT CAPCTRL10: CAPCONn_H Mask       */

// -------------------------------------  SCT_MATCHREL11  -----------------------------------------
#define SCT_MATCHREL11_RELOADn_L_Pos                          0                                                         /*!< SCT MATCHREL11: RELOADn_L Position  */
#define SCT_MATCHREL11_RELOADn_L_Msk                          (0x0000ffffUL << SCT_MATCHREL11_RELOADn_L_Pos)            /*!< SCT MATCHREL11: RELOADn_L Mask      */
#define SCT_MATCHREL11_RELOADn_H_Pos                          16                                                        /*!< SCT MATCHREL11: RELOADn_H Position  */
#define SCT_MATCHREL11_RELOADn_H_Msk                          (0x0000ffffUL << SCT_MATCHREL11_RELOADn_H_Pos)            /*!< SCT MATCHREL11: RELOADn_H Mask      */

// --------------------------------------  SCT_CAPCTRL11  -----------------------------------------
#define SCT_CAPCTRL11_CAPCONn_L0_Pos                          0                                                         /*!< SCT CAPCTRL11: CAPCONn_L0 Position  */
#define SCT_CAPCTRL11_CAPCONn_L0_Msk                          (0x01UL << SCT_CAPCTRL11_CAPCONn_L0_Pos)                  /*!< SCT CAPCTRL11: CAPCONn_L0 Mask      */
#define SCT_CAPCTRL11_CAPCONn_L1_Pos                          1                                                         /*!< SCT CAPCTRL11: CAPCONn_L1 Position  */
#define SCT_CAPCTRL11_CAPCONn_L1_Msk                          (0x01UL << SCT_CAPCTRL11_CAPCONn_L1_Pos)                  /*!< SCT CAPCTRL11: CAPCONn_L1 Mask      */
#define SCT_CAPCTRL11_CAPCONn_L2_Pos                          2                                                         /*!< SCT CAPCTRL11: CAPCONn_L2 Position  */
#define SCT_CAPCTRL11_CAPCONn_L2_Msk                          (0x01UL << SCT_CAPCTRL11_CAPCONn_L2_Pos)                  /*!< SCT CAPCTRL11: CAPCONn_L2 Mask      */
#define SCT_CAPCTRL11_CAPCONn_L3_Pos                          3                                                         /*!< SCT CAPCTRL11: CAPCONn_L3 Position  */
#define SCT_CAPCTRL11_CAPCONn_L3_Msk                          (0x01UL << SCT_CAPCTRL11_CAPCONn_L3_Pos)                  /*!< SCT CAPCTRL11: CAPCONn_L3 Mask      */
#define SCT_CAPCTRL11_CAPCONn_L4_Pos                          4                                                         /*!< SCT CAPCTRL11: CAPCONn_L4 Position  */
#define SCT_CAPCTRL11_CAPCONn_L4_Msk                          (0x01UL << SCT_CAPCTRL11_CAPCONn_L4_Pos)                  /*!< SCT CAPCTRL11: CAPCONn_L4 Mask      */
#define SCT_CAPCTRL11_CAPCONn_L5_Pos                          5                                                         /*!< SCT CAPCTRL11: CAPCONn_L5 Position  */
#define SCT_CAPCTRL11_CAPCONn_L5_Msk                          (0x01UL << SCT_CAPCTRL11_CAPCONn_L5_Pos)                  /*!< SCT CAPCTRL11: CAPCONn_L5 Mask      */
#define SCT_CAPCTRL11_CAPCONn_L6_Pos                          6                                                         /*!< SCT CAPCTRL11: CAPCONn_L6 Position  */
#define SCT_CAPCTRL11_CAPCONn_L6_Msk                          (0x01UL << SCT_CAPCTRL11_CAPCONn_L6_Pos)                  /*!< SCT CAPCTRL11: CAPCONn_L6 Mask      */
#define SCT_CAPCTRL11_CAPCONn_L7_Pos                          7                                                         /*!< SCT CAPCTRL11: CAPCONn_L7 Position  */
#define SCT_CAPCTRL11_CAPCONn_L7_Msk                          (0x01UL << SCT_CAPCTRL11_CAPCONn_L7_Pos)                  /*!< SCT CAPCTRL11: CAPCONn_L7 Mask      */
#define SCT_CAPCTRL11_CAPCONn_L8_Pos                          8                                                         /*!< SCT CAPCTRL11: CAPCONn_L8 Position  */
#define SCT_CAPCTRL11_CAPCONn_L8_Msk                          (0x01UL << SCT_CAPCTRL11_CAPCONn_L8_Pos)                  /*!< SCT CAPCTRL11: CAPCONn_L8 Mask      */
#define SCT_CAPCTRL11_CAPCONn_L9_Pos                          9                                                         /*!< SCT CAPCTRL11: CAPCONn_L9 Position  */
#define SCT_CAPCTRL11_CAPCONn_L9_Msk                          (0x01UL << SCT_CAPCTRL11_CAPCONn_L9_Pos)                  /*!< SCT CAPCTRL11: CAPCONn_L9 Mask      */
#define SCT_CAPCTRL11_CAPCONn_L10_Pos                         10                                                        /*!< SCT CAPCTRL11: CAPCONn_L10 Position */
#define SCT_CAPCTRL11_CAPCONn_L10_Msk                         (0x01UL << SCT_CAPCTRL11_CAPCONn_L10_Pos)                 /*!< SCT CAPCTRL11: CAPCONn_L10 Mask     */
#define SCT_CAPCTRL11_CAPCONn_L11_Pos                         11                                                        /*!< SCT CAPCTRL11: CAPCONn_L11 Position */
#define SCT_CAPCTRL11_CAPCONn_L11_Msk                         (0x01UL << SCT_CAPCTRL11_CAPCONn_L11_Pos)                 /*!< SCT CAPCTRL11: CAPCONn_L11 Mask     */
#define SCT_CAPCTRL11_CAPCONn_L12_Pos                         12                                                        /*!< SCT CAPCTRL11: CAPCONn_L12 Position */
#define SCT_CAPCTRL11_CAPCONn_L12_Msk                         (0x01UL << SCT_CAPCTRL11_CAPCONn_L12_Pos)                 /*!< SCT CAPCTRL11: CAPCONn_L12 Mask     */
#define SCT_CAPCTRL11_CAPCONn_L13_Pos                         13                                                        /*!< SCT CAPCTRL11: CAPCONn_L13 Position */
#define SCT_CAPCTRL11_CAPCONn_L13_Msk                         (0x01UL << SCT_CAPCTRL11_CAPCONn_L13_Pos)                 /*!< SCT CAPCTRL11: CAPCONn_L13 Mask     */
#define SCT_CAPCTRL11_CAPCONn_L14_Pos                         14                                                        /*!< SCT CAPCTRL11: CAPCONn_L14 Position */
#define SCT_CAPCTRL11_CAPCONn_L14_Msk                         (0x01UL << SCT_CAPCTRL11_CAPCONn_L14_Pos)                 /*!< SCT CAPCTRL11: CAPCONn_L14 Mask     */
#define SCT_CAPCTRL11_CAPCONn_L15_Pos                         15                                                        /*!< SCT CAPCTRL11: CAPCONn_L15 Position */
#define SCT_CAPCTRL11_CAPCONn_L15_Msk                         (0x01UL << SCT_CAPCTRL11_CAPCONn_L15_Pos)                 /*!< SCT CAPCTRL11: CAPCONn_L15 Mask     */
#define SCT_CAPCTRL11_CAPCONn_H_Pos                           16                                                        /*!< SCT CAPCTRL11: CAPCONn_H Position   */
#define SCT_CAPCTRL11_CAPCONn_H_Msk                           (0x0000ffffUL << SCT_CAPCTRL11_CAPCONn_H_Pos)             /*!< SCT CAPCTRL11: CAPCONn_H Mask       */

// -------------------------------------  SCT_MATCHREL12  -----------------------------------------
#define SCT_MATCHREL12_RELOADn_L_Pos                          0                                                         /*!< SCT MATCHREL12: RELOADn_L Position  */
#define SCT_MATCHREL12_RELOADn_L_Msk                          (0x0000ffffUL << SCT_MATCHREL12_RELOADn_L_Pos)            /*!< SCT MATCHREL12: RELOADn_L Mask      */
#define SCT_MATCHREL12_RELOADn_H_Pos                          16                                                        /*!< SCT MATCHREL12: RELOADn_H Position  */
#define SCT_MATCHREL12_RELOADn_H_Msk                          (0x0000ffffUL << SCT_MATCHREL12_RELOADn_H_Pos)            /*!< SCT MATCHREL12: RELOADn_H Mask      */

// --------------------------------------  SCT_CAPCTRL12  -----------------------------------------
#define SCT_CAPCTRL12_CAPCONn_L0_Pos                          0                                                         /*!< SCT CAPCTRL12: CAPCONn_L0 Position  */
#define SCT_CAPCTRL12_CAPCONn_L0_Msk                          (0x01UL << SCT_CAPCTRL12_CAPCONn_L0_Pos)                  /*!< SCT CAPCTRL12: CAPCONn_L0 Mask      */
#define SCT_CAPCTRL12_CAPCONn_L1_Pos                          1                                                         /*!< SCT CAPCTRL12: CAPCONn_L1 Position  */
#define SCT_CAPCTRL12_CAPCONn_L1_Msk                          (0x01UL << SCT_CAPCTRL12_CAPCONn_L1_Pos)                  /*!< SCT CAPCTRL12: CAPCONn_L1 Mask      */
#define SCT_CAPCTRL12_CAPCONn_L2_Pos                          2                                                         /*!< SCT CAPCTRL12: CAPCONn_L2 Position  */
#define SCT_CAPCTRL12_CAPCONn_L2_Msk                          (0x01UL << SCT_CAPCTRL12_CAPCONn_L2_Pos)                  /*!< SCT CAPCTRL12: CAPCONn_L2 Mask      */
#define SCT_CAPCTRL12_CAPCONn_L3_Pos                          3                                                         /*!< SCT CAPCTRL12: CAPCONn_L3 Position  */
#define SCT_CAPCTRL12_CAPCONn_L3_Msk                          (0x01UL << SCT_CAPCTRL12_CAPCONn_L3_Pos)                  /*!< SCT CAPCTRL12: CAPCONn_L3 Mask      */
#define SCT_CAPCTRL12_CAPCONn_L4_Pos                          4                                                         /*!< SCT CAPCTRL12: CAPCONn_L4 Position  */
#define SCT_CAPCTRL12_CAPCONn_L4_Msk                          (0x01UL << SCT_CAPCTRL12_CAPCONn_L4_Pos)                  /*!< SCT CAPCTRL12: CAPCONn_L4 Mask      */
#define SCT_CAPCTRL12_CAPCONn_L5_Pos                          5                                                         /*!< SCT CAPCTRL12: CAPCONn_L5 Position  */
#define SCT_CAPCTRL12_CAPCONn_L5_Msk                          (0x01UL << SCT_CAPCTRL12_CAPCONn_L5_Pos)                  /*!< SCT CAPCTRL12: CAPCONn_L5 Mask      */
#define SCT_CAPCTRL12_CAPCONn_L6_Pos                          6                                                         /*!< SCT CAPCTRL12: CAPCONn_L6 Position  */
#define SCT_CAPCTRL12_CAPCONn_L6_Msk                          (0x01UL << SCT_CAPCTRL12_CAPCONn_L6_Pos)                  /*!< SCT CAPCTRL12: CAPCONn_L6 Mask      */
#define SCT_CAPCTRL12_CAPCONn_L7_Pos                          7                                                         /*!< SCT CAPCTRL12: CAPCONn_L7 Position  */
#define SCT_CAPCTRL12_CAPCONn_L7_Msk                          (0x01UL << SCT_CAPCTRL12_CAPCONn_L7_Pos)                  /*!< SCT CAPCTRL12: CAPCONn_L7 Mask      */
#define SCT_CAPCTRL12_CAPCONn_L8_Pos                          8                                                         /*!< SCT CAPCTRL12: CAPCONn_L8 Position  */
#define SCT_CAPCTRL12_CAPCONn_L8_Msk                          (0x01UL << SCT_CAPCTRL12_CAPCONn_L8_Pos)                  /*!< SCT CAPCTRL12: CAPCONn_L8 Mask      */
#define SCT_CAPCTRL12_CAPCONn_L9_Pos                          9                                                         /*!< SCT CAPCTRL12: CAPCONn_L9 Position  */
#define SCT_CAPCTRL12_CAPCONn_L9_Msk                          (0x01UL << SCT_CAPCTRL12_CAPCONn_L9_Pos)                  /*!< SCT CAPCTRL12: CAPCONn_L9 Mask      */
#define SCT_CAPCTRL12_CAPCONn_L10_Pos                         10                                                        /*!< SCT CAPCTRL12: CAPCONn_L10 Position */
#define SCT_CAPCTRL12_CAPCONn_L10_Msk                         (0x01UL << SCT_CAPCTRL12_CAPCONn_L10_Pos)                 /*!< SCT CAPCTRL12: CAPCONn_L10 Mask     */
#define SCT_CAPCTRL12_CAPCONn_L11_Pos                         11                                                        /*!< SCT CAPCTRL12: CAPCONn_L11 Position */
#define SCT_CAPCTRL12_CAPCONn_L11_Msk                         (0x01UL << SCT_CAPCTRL12_CAPCONn_L11_Pos)                 /*!< SCT CAPCTRL12: CAPCONn_L11 Mask     */
#define SCT_CAPCTRL12_CAPCONn_L12_Pos                         12                                                        /*!< SCT CAPCTRL12: CAPCONn_L12 Position */
#define SCT_CAPCTRL12_CAPCONn_L12_Msk                         (0x01UL << SCT_CAPCTRL12_CAPCONn_L12_Pos)                 /*!< SCT CAPCTRL12: CAPCONn_L12 Mask     */
#define SCT_CAPCTRL12_CAPCONn_L13_Pos                         13                                                        /*!< SCT CAPCTRL12: CAPCONn_L13 Position */
#define SCT_CAPCTRL12_CAPCONn_L13_Msk                         (0x01UL << SCT_CAPCTRL12_CAPCONn_L13_Pos)                 /*!< SCT CAPCTRL12: CAPCONn_L13 Mask     */
#define SCT_CAPCTRL12_CAPCONn_L14_Pos                         14                                                        /*!< SCT CAPCTRL12: CAPCONn_L14 Position */
#define SCT_CAPCTRL12_CAPCONn_L14_Msk                         (0x01UL << SCT_CAPCTRL12_CAPCONn_L14_Pos)                 /*!< SCT CAPCTRL12: CAPCONn_L14 Mask     */
#define SCT_CAPCTRL12_CAPCONn_L15_Pos                         15                                                        /*!< SCT CAPCTRL12: CAPCONn_L15 Position */
#define SCT_CAPCTRL12_CAPCONn_L15_Msk                         (0x01UL << SCT_CAPCTRL12_CAPCONn_L15_Pos)                 /*!< SCT CAPCTRL12: CAPCONn_L15 Mask     */
#define SCT_CAPCTRL12_CAPCONn_H_Pos                           16                                                        /*!< SCT CAPCTRL12: CAPCONn_H Position   */
#define SCT_CAPCTRL12_CAPCONn_H_Msk                           (0x0000ffffUL << SCT_CAPCTRL12_CAPCONn_H_Pos)             /*!< SCT CAPCTRL12: CAPCONn_H Mask       */

// -------------------------------------  SCT_MATCHREL13  -----------------------------------------
#define SCT_MATCHREL13_RELOADn_L_Pos                          0                                                         /*!< SCT MATCHREL13: RELOADn_L Position  */
#define SCT_MATCHREL13_RELOADn_L_Msk                          (0x0000ffffUL << SCT_MATCHREL13_RELOADn_L_Pos)            /*!< SCT MATCHREL13: RELOADn_L Mask      */
#define SCT_MATCHREL13_RELOADn_H_Pos                          16                                                        /*!< SCT MATCHREL13: RELOADn_H Position  */
#define SCT_MATCHREL13_RELOADn_H_Msk                          (0x0000ffffUL << SCT_MATCHREL13_RELOADn_H_Pos)            /*!< SCT MATCHREL13: RELOADn_H Mask      */

// --------------------------------------  SCT_CAPCTRL13  -----------------------------------------
#define SCT_CAPCTRL13_CAPCONn_L0_Pos                          0                                                         /*!< SCT CAPCTRL13: CAPCONn_L0 Position  */
#define SCT_CAPCTRL13_CAPCONn_L0_Msk                          (0x01UL << SCT_CAPCTRL13_CAPCONn_L0_Pos)                  /*!< SCT CAPCTRL13: CAPCONn_L0 Mask      */
#define SCT_CAPCTRL13_CAPCONn_L1_Pos                          1                                                         /*!< SCT CAPCTRL13: CAPCONn_L1 Position  */
#define SCT_CAPCTRL13_CAPCONn_L1_Msk                          (0x01UL << SCT_CAPCTRL13_CAPCONn_L1_Pos)                  /*!< SCT CAPCTRL13: CAPCONn_L1 Mask      */
#define SCT_CAPCTRL13_CAPCONn_L2_Pos                          2                                                         /*!< SCT CAPCTRL13: CAPCONn_L2 Position  */
#define SCT_CAPCTRL13_CAPCONn_L2_Msk                          (0x01UL << SCT_CAPCTRL13_CAPCONn_L2_Pos)                  /*!< SCT CAPCTRL13: CAPCONn_L2 Mask      */
#define SCT_CAPCTRL13_CAPCONn_L3_Pos                          3                                                         /*!< SCT CAPCTRL13: CAPCONn_L3 Position  */
#define SCT_CAPCTRL13_CAPCONn_L3_Msk                          (0x01UL << SCT_CAPCTRL13_CAPCONn_L3_Pos)                  /*!< SCT CAPCTRL13: CAPCONn_L3 Mask      */
#define SCT_CAPCTRL13_CAPCONn_L4_Pos                          4                                                         /*!< SCT CAPCTRL13: CAPCONn_L4 Position  */
#define SCT_CAPCTRL13_CAPCONn_L4_Msk                          (0x01UL << SCT_CAPCTRL13_CAPCONn_L4_Pos)                  /*!< SCT CAPCTRL13: CAPCONn_L4 Mask      */
#define SCT_CAPCTRL13_CAPCONn_L5_Pos                          5                                                         /*!< SCT CAPCTRL13: CAPCONn_L5 Position  */
#define SCT_CAPCTRL13_CAPCONn_L5_Msk                          (0x01UL << SCT_CAPCTRL13_CAPCONn_L5_Pos)                  /*!< SCT CAPCTRL13: CAPCONn_L5 Mask      */
#define SCT_CAPCTRL13_CAPCONn_L6_Pos                          6                                                         /*!< SCT CAPCTRL13: CAPCONn_L6 Position  */
#define SCT_CAPCTRL13_CAPCONn_L6_Msk                          (0x01UL << SCT_CAPCTRL13_CAPCONn_L6_Pos)                  /*!< SCT CAPCTRL13: CAPCONn_L6 Mask      */
#define SCT_CAPCTRL13_CAPCONn_L7_Pos                          7                                                         /*!< SCT CAPCTRL13: CAPCONn_L7 Position  */
#define SCT_CAPCTRL13_CAPCONn_L7_Msk                          (0x01UL << SCT_CAPCTRL13_CAPCONn_L7_Pos)                  /*!< SCT CAPCTRL13: CAPCONn_L7 Mask      */
#define SCT_CAPCTRL13_CAPCONn_L8_Pos                          8                                                         /*!< SCT CAPCTRL13: CAPCONn_L8 Position  */
#define SCT_CAPCTRL13_CAPCONn_L8_Msk                          (0x01UL << SCT_CAPCTRL13_CAPCONn_L8_Pos)                  /*!< SCT CAPCTRL13: CAPCONn_L8 Mask      */
#define SCT_CAPCTRL13_CAPCONn_L9_Pos                          9                                                         /*!< SCT CAPCTRL13: CAPCONn_L9 Position  */
#define SCT_CAPCTRL13_CAPCONn_L9_Msk                          (0x01UL << SCT_CAPCTRL13_CAPCONn_L9_Pos)                  /*!< SCT CAPCTRL13: CAPCONn_L9 Mask      */
#define SCT_CAPCTRL13_CAPCONn_L10_Pos                         10                                                        /*!< SCT CAPCTRL13: CAPCONn_L10 Position */
#define SCT_CAPCTRL13_CAPCONn_L10_Msk                         (0x01UL << SCT_CAPCTRL13_CAPCONn_L10_Pos)                 /*!< SCT CAPCTRL13: CAPCONn_L10 Mask     */
#define SCT_CAPCTRL13_CAPCONn_L11_Pos                         11                                                        /*!< SCT CAPCTRL13: CAPCONn_L11 Position */
#define SCT_CAPCTRL13_CAPCONn_L11_Msk                         (0x01UL << SCT_CAPCTRL13_CAPCONn_L11_Pos)                 /*!< SCT CAPCTRL13: CAPCONn_L11 Mask     */
#define SCT_CAPCTRL13_CAPCONn_L12_Pos                         12                                                        /*!< SCT CAPCTRL13: CAPCONn_L12 Position */
#define SCT_CAPCTRL13_CAPCONn_L12_Msk                         (0x01UL << SCT_CAPCTRL13_CAPCONn_L12_Pos)                 /*!< SCT CAPCTRL13: CAPCONn_L12 Mask     */
#define SCT_CAPCTRL13_CAPCONn_L13_Pos                         13                                                        /*!< SCT CAPCTRL13: CAPCONn_L13 Position */
#define SCT_CAPCTRL13_CAPCONn_L13_Msk                         (0x01UL << SCT_CAPCTRL13_CAPCONn_L13_Pos)                 /*!< SCT CAPCTRL13: CAPCONn_L13 Mask     */
#define SCT_CAPCTRL13_CAPCONn_L14_Pos                         14                                                        /*!< SCT CAPCTRL13: CAPCONn_L14 Position */
#define SCT_CAPCTRL13_CAPCONn_L14_Msk                         (0x01UL << SCT_CAPCTRL13_CAPCONn_L14_Pos)                 /*!< SCT CAPCTRL13: CAPCONn_L14 Mask     */
#define SCT_CAPCTRL13_CAPCONn_L15_Pos                         15                                                        /*!< SCT CAPCTRL13: CAPCONn_L15 Position */
#define SCT_CAPCTRL13_CAPCONn_L15_Msk                         (0x01UL << SCT_CAPCTRL13_CAPCONn_L15_Pos)                 /*!< SCT CAPCTRL13: CAPCONn_L15 Mask     */
#define SCT_CAPCTRL13_CAPCONn_H_Pos                           16                                                        /*!< SCT CAPCTRL13: CAPCONn_H Position   */
#define SCT_CAPCTRL13_CAPCONn_H_Msk                           (0x0000ffffUL << SCT_CAPCTRL13_CAPCONn_H_Pos)             /*!< SCT CAPCTRL13: CAPCONn_H Mask       */

// -------------------------------------  SCT_MATCHREL14  -----------------------------------------
#define SCT_MATCHREL14_RELOADn_L_Pos                          0                                                         /*!< SCT MATCHREL14: RELOADn_L Position  */
#define SCT_MATCHREL14_RELOADn_L_Msk                          (0x0000ffffUL << SCT_MATCHREL14_RELOADn_L_Pos)            /*!< SCT MATCHREL14: RELOADn_L Mask      */
#define SCT_MATCHREL14_RELOADn_H_Pos                          16                                                        /*!< SCT MATCHREL14: RELOADn_H Position  */
#define SCT_MATCHREL14_RELOADn_H_Msk                          (0x0000ffffUL << SCT_MATCHREL14_RELOADn_H_Pos)            /*!< SCT MATCHREL14: RELOADn_H Mask      */

// --------------------------------------  SCT_CAPCTRL14  -----------------------------------------
#define SCT_CAPCTRL14_CAPCONn_L0_Pos                          0                                                         /*!< SCT CAPCTRL14: CAPCONn_L0 Position  */
#define SCT_CAPCTRL14_CAPCONn_L0_Msk                          (0x01UL << SCT_CAPCTRL14_CAPCONn_L0_Pos)                  /*!< SCT CAPCTRL14: CAPCONn_L0 Mask      */
#define SCT_CAPCTRL14_CAPCONn_L1_Pos                          1                                                         /*!< SCT CAPCTRL14: CAPCONn_L1 Position  */
#define SCT_CAPCTRL14_CAPCONn_L1_Msk                          (0x01UL << SCT_CAPCTRL14_CAPCONn_L1_Pos)                  /*!< SCT CAPCTRL14: CAPCONn_L1 Mask      */
#define SCT_CAPCTRL14_CAPCONn_L2_Pos                          2                                                         /*!< SCT CAPCTRL14: CAPCONn_L2 Position  */
#define SCT_CAPCTRL14_CAPCONn_L2_Msk                          (0x01UL << SCT_CAPCTRL14_CAPCONn_L2_Pos)                  /*!< SCT CAPCTRL14: CAPCONn_L2 Mask      */
#define SCT_CAPCTRL14_CAPCONn_L3_Pos                          3                                                         /*!< SCT CAPCTRL14: CAPCONn_L3 Position  */
#define SCT_CAPCTRL14_CAPCONn_L3_Msk                          (0x01UL << SCT_CAPCTRL14_CAPCONn_L3_Pos)                  /*!< SCT CAPCTRL14: CAPCONn_L3 Mask      */
#define SCT_CAPCTRL14_CAPCONn_L4_Pos                          4                                                         /*!< SCT CAPCTRL14: CAPCONn_L4 Position  */
#define SCT_CAPCTRL14_CAPCONn_L4_Msk                          (0x01UL << SCT_CAPCTRL14_CAPCONn_L4_Pos)                  /*!< SCT CAPCTRL14: CAPCONn_L4 Mask      */
#define SCT_CAPCTRL14_CAPCONn_L5_Pos                          5                                                         /*!< SCT CAPCTRL14: CAPCONn_L5 Position  */
#define SCT_CAPCTRL14_CAPCONn_L5_Msk                          (0x01UL << SCT_CAPCTRL14_CAPCONn_L5_Pos)                  /*!< SCT CAPCTRL14: CAPCONn_L5 Mask      */
#define SCT_CAPCTRL14_CAPCONn_L6_Pos                          6                                                         /*!< SCT CAPCTRL14: CAPCONn_L6 Position  */
#define SCT_CAPCTRL14_CAPCONn_L6_Msk                          (0x01UL << SCT_CAPCTRL14_CAPCONn_L6_Pos)                  /*!< SCT CAPCTRL14: CAPCONn_L6 Mask      */
#define SCT_CAPCTRL14_CAPCONn_L7_Pos                          7                                                         /*!< SCT CAPCTRL14: CAPCONn_L7 Position  */
#define SCT_CAPCTRL14_CAPCONn_L7_Msk                          (0x01UL << SCT_CAPCTRL14_CAPCONn_L7_Pos)                  /*!< SCT CAPCTRL14: CAPCONn_L7 Mask      */
#define SCT_CAPCTRL14_CAPCONn_L8_Pos                          8                                                         /*!< SCT CAPCTRL14: CAPCONn_L8 Position  */
#define SCT_CAPCTRL14_CAPCONn_L8_Msk                          (0x01UL << SCT_CAPCTRL14_CAPCONn_L8_Pos)                  /*!< SCT CAPCTRL14: CAPCONn_L8 Mask      */
#define SCT_CAPCTRL14_CAPCONn_L9_Pos                          9                                                         /*!< SCT CAPCTRL14: CAPCONn_L9 Position  */
#define SCT_CAPCTRL14_CAPCONn_L9_Msk                          (0x01UL << SCT_CAPCTRL14_CAPCONn_L9_Pos)                  /*!< SCT CAPCTRL14: CAPCONn_L9 Mask      */
#define SCT_CAPCTRL14_CAPCONn_L10_Pos                         10                                                        /*!< SCT CAPCTRL14: CAPCONn_L10 Position */
#define SCT_CAPCTRL14_CAPCONn_L10_Msk                         (0x01UL << SCT_CAPCTRL14_CAPCONn_L10_Pos)                 /*!< SCT CAPCTRL14: CAPCONn_L10 Mask     */
#define SCT_CAPCTRL14_CAPCONn_L11_Pos                         11                                                        /*!< SCT CAPCTRL14: CAPCONn_L11 Position */
#define SCT_CAPCTRL14_CAPCONn_L11_Msk                         (0x01UL << SCT_CAPCTRL14_CAPCONn_L11_Pos)                 /*!< SCT CAPCTRL14: CAPCONn_L11 Mask     */
#define SCT_CAPCTRL14_CAPCONn_L12_Pos                         12                                                        /*!< SCT CAPCTRL14: CAPCONn_L12 Position */
#define SCT_CAPCTRL14_CAPCONn_L12_Msk                         (0x01UL << SCT_CAPCTRL14_CAPCONn_L12_Pos)                 /*!< SCT CAPCTRL14: CAPCONn_L12 Mask     */
#define SCT_CAPCTRL14_CAPCONn_L13_Pos                         13                                                        /*!< SCT CAPCTRL14: CAPCONn_L13 Position */
#define SCT_CAPCTRL14_CAPCONn_L13_Msk                         (0x01UL << SCT_CAPCTRL14_CAPCONn_L13_Pos)                 /*!< SCT CAPCTRL14: CAPCONn_L13 Mask     */
#define SCT_CAPCTRL14_CAPCONn_L14_Pos                         14                                                        /*!< SCT CAPCTRL14: CAPCONn_L14 Position */
#define SCT_CAPCTRL14_CAPCONn_L14_Msk                         (0x01UL << SCT_CAPCTRL14_CAPCONn_L14_Pos)                 /*!< SCT CAPCTRL14: CAPCONn_L14 Mask     */
#define SCT_CAPCTRL14_CAPCONn_L15_Pos                         15                                                        /*!< SCT CAPCTRL14: CAPCONn_L15 Position */
#define SCT_CAPCTRL14_CAPCONn_L15_Msk                         (0x01UL << SCT_CAPCTRL14_CAPCONn_L15_Pos)                 /*!< SCT CAPCTRL14: CAPCONn_L15 Mask     */
#define SCT_CAPCTRL14_CAPCONn_H_Pos                           16                                                        /*!< SCT CAPCTRL14: CAPCONn_H Position   */
#define SCT_CAPCTRL14_CAPCONn_H_Msk                           (0x0000ffffUL << SCT_CAPCTRL14_CAPCONn_H_Pos)             /*!< SCT CAPCTRL14: CAPCONn_H Mask       */

// -------------------------------------  SCT_MATCHREL15  -----------------------------------------
#define SCT_MATCHREL15_RELOADn_L_Pos                          0                                                         /*!< SCT MATCHREL15: RELOADn_L Position  */
#define SCT_MATCHREL15_RELOADn_L_Msk                          (0x0000ffffUL << SCT_MATCHREL15_RELOADn_L_Pos)            /*!< SCT MATCHREL15: RELOADn_L Mask      */
#define SCT_MATCHREL15_RELOADn_H_Pos                          16                                                        /*!< SCT MATCHREL15: RELOADn_H Position  */
#define SCT_MATCHREL15_RELOADn_H_Msk                          (0x0000ffffUL << SCT_MATCHREL15_RELOADn_H_Pos)            /*!< SCT MATCHREL15: RELOADn_H Mask      */

// --------------------------------------  SCT_CAPCTRL15  -----------------------------------------
#define SCT_CAPCTRL15_CAPCONn_L0_Pos                          0                                                         /*!< SCT CAPCTRL15: CAPCONn_L0 Position  */
#define SCT_CAPCTRL15_CAPCONn_L0_Msk                          (0x01UL << SCT_CAPCTRL15_CAPCONn_L0_Pos)                  /*!< SCT CAPCTRL15: CAPCONn_L0 Mask      */
#define SCT_CAPCTRL15_CAPCONn_L1_Pos                          1                                                         /*!< SCT CAPCTRL15: CAPCONn_L1 Position  */
#define SCT_CAPCTRL15_CAPCONn_L1_Msk                          (0x01UL << SCT_CAPCTRL15_CAPCONn_L1_Pos)                  /*!< SCT CAPCTRL15: CAPCONn_L1 Mask      */
#define SCT_CAPCTRL15_CAPCONn_L2_Pos                          2                                                         /*!< SCT CAPCTRL15: CAPCONn_L2 Position  */
#define SCT_CAPCTRL15_CAPCONn_L2_Msk                          (0x01UL << SCT_CAPCTRL15_CAPCONn_L2_Pos)                  /*!< SCT CAPCTRL15: CAPCONn_L2 Mask      */
#define SCT_CAPCTRL15_CAPCONn_L3_Pos                          3                                                         /*!< SCT CAPCTRL15: CAPCONn_L3 Position  */
#define SCT_CAPCTRL15_CAPCONn_L3_Msk                          (0x01UL << SCT_CAPCTRL15_CAPCONn_L3_Pos)                  /*!< SCT CAPCTRL15: CAPCONn_L3 Mask      */
#define SCT_CAPCTRL15_CAPCONn_L4_Pos                          4                                                         /*!< SCT CAPCTRL15: CAPCONn_L4 Position  */
#define SCT_CAPCTRL15_CAPCONn_L4_Msk                          (0x01UL << SCT_CAPCTRL15_CAPCONn_L4_Pos)                  /*!< SCT CAPCTRL15: CAPCONn_L4 Mask      */
#define SCT_CAPCTRL15_CAPCONn_L5_Pos                          5                                                         /*!< SCT CAPCTRL15: CAPCONn_L5 Position  */
#define SCT_CAPCTRL15_CAPCONn_L5_Msk                          (0x01UL << SCT_CAPCTRL15_CAPCONn_L5_Pos)                  /*!< SCT CAPCTRL15: CAPCONn_L5 Mask      */
#define SCT_CAPCTRL15_CAPCONn_L6_Pos                          6                                                         /*!< SCT CAPCTRL15: CAPCONn_L6 Position  */
#define SCT_CAPCTRL15_CAPCONn_L6_Msk                          (0x01UL << SCT_CAPCTRL15_CAPCONn_L6_Pos)                  /*!< SCT CAPCTRL15: CAPCONn_L6 Mask      */
#define SCT_CAPCTRL15_CAPCONn_L7_Pos                          7                                                         /*!< SCT CAPCTRL15: CAPCONn_L7 Position  */
#define SCT_CAPCTRL15_CAPCONn_L7_Msk                          (0x01UL << SCT_CAPCTRL15_CAPCONn_L7_Pos)                  /*!< SCT CAPCTRL15: CAPCONn_L7 Mask      */
#define SCT_CAPCTRL15_CAPCONn_L8_Pos                          8                                                         /*!< SCT CAPCTRL15: CAPCONn_L8 Position  */
#define SCT_CAPCTRL15_CAPCONn_L8_Msk                          (0x01UL << SCT_CAPCTRL15_CAPCONn_L8_Pos)                  /*!< SCT CAPCTRL15: CAPCONn_L8 Mask      */
#define SCT_CAPCTRL15_CAPCONn_L9_Pos                          9                                                         /*!< SCT CAPCTRL15: CAPCONn_L9 Position  */
#define SCT_CAPCTRL15_CAPCONn_L9_Msk                          (0x01UL << SCT_CAPCTRL15_CAPCONn_L9_Pos)                  /*!< SCT CAPCTRL15: CAPCONn_L9 Mask      */
#define SCT_CAPCTRL15_CAPCONn_L10_Pos                         10                                                        /*!< SCT CAPCTRL15: CAPCONn_L10 Position */
#define SCT_CAPCTRL15_CAPCONn_L10_Msk                         (0x01UL << SCT_CAPCTRL15_CAPCONn_L10_Pos)                 /*!< SCT CAPCTRL15: CAPCONn_L10 Mask     */
#define SCT_CAPCTRL15_CAPCONn_L11_Pos                         11                                                        /*!< SCT CAPCTRL15: CAPCONn_L11 Position */
#define SCT_CAPCTRL15_CAPCONn_L11_Msk                         (0x01UL << SCT_CAPCTRL15_CAPCONn_L11_Pos)                 /*!< SCT CAPCTRL15: CAPCONn_L11 Mask     */
#define SCT_CAPCTRL15_CAPCONn_L12_Pos                         12                                                        /*!< SCT CAPCTRL15: CAPCONn_L12 Position */
#define SCT_CAPCTRL15_CAPCONn_L12_Msk                         (0x01UL << SCT_CAPCTRL15_CAPCONn_L12_Pos)                 /*!< SCT CAPCTRL15: CAPCONn_L12 Mask     */
#define SCT_CAPCTRL15_CAPCONn_L13_Pos                         13                                                        /*!< SCT CAPCTRL15: CAPCONn_L13 Position */
#define SCT_CAPCTRL15_CAPCONn_L13_Msk                         (0x01UL << SCT_CAPCTRL15_CAPCONn_L13_Pos)                 /*!< SCT CAPCTRL15: CAPCONn_L13 Mask     */
#define SCT_CAPCTRL15_CAPCONn_L14_Pos                         14                                                        /*!< SCT CAPCTRL15: CAPCONn_L14 Position */
#define SCT_CAPCTRL15_CAPCONn_L14_Msk                         (0x01UL << SCT_CAPCTRL15_CAPCONn_L14_Pos)                 /*!< SCT CAPCTRL15: CAPCONn_L14 Mask     */
#define SCT_CAPCTRL15_CAPCONn_L15_Pos                         15                                                        /*!< SCT CAPCTRL15: CAPCONn_L15 Position */
#define SCT_CAPCTRL15_CAPCONn_L15_Msk                         (0x01UL << SCT_CAPCTRL15_CAPCONn_L15_Pos)                 /*!< SCT CAPCTRL15: CAPCONn_L15 Mask     */
#define SCT_CAPCTRL15_CAPCONn_H_Pos                           16                                                        /*!< SCT CAPCTRL15: CAPCONn_H Position   */
#define SCT_CAPCTRL15_CAPCONn_H_Msk                           (0x0000ffffUL << SCT_CAPCTRL15_CAPCONn_H_Pos)             /*!< SCT CAPCTRL15: CAPCONn_H Mask       */

// -------------------------------------  SCT_EVSTATEMSK0  ----------------------------------------
#define SCT_EVSTATEMSK0_STATEMSKn0_Pos                        0                                                         /*!< SCT EVSTATEMSK0: STATEMSKn0 Position */
#define SCT_EVSTATEMSK0_STATEMSKn0_Msk                        (0x01UL << SCT_EVSTATEMSK0_STATEMSKn0_Pos)                /*!< SCT EVSTATEMSK0: STATEMSKn0 Mask    */
#define SCT_EVSTATEMSK0_STATEMSKn1_Pos                        1                                                         /*!< SCT EVSTATEMSK0: STATEMSKn1 Position */
#define SCT_EVSTATEMSK0_STATEMSKn1_Msk                        (0x01UL << SCT_EVSTATEMSK0_STATEMSKn1_Pos)                /*!< SCT EVSTATEMSK0: STATEMSKn1 Mask    */
#define SCT_EVSTATEMSK0_STATEMSKn2_Pos                        2                                                         /*!< SCT EVSTATEMSK0: STATEMSKn2 Position */
#define SCT_EVSTATEMSK0_STATEMSKn2_Msk                        (0x01UL << SCT_EVSTATEMSK0_STATEMSKn2_Pos)                /*!< SCT EVSTATEMSK0: STATEMSKn2 Mask    */
#define SCT_EVSTATEMSK0_STATEMSKn3_Pos                        3                                                         /*!< SCT EVSTATEMSK0: STATEMSKn3 Position */
#define SCT_EVSTATEMSK0_STATEMSKn3_Msk                        (0x01UL << SCT_EVSTATEMSK0_STATEMSKn3_Pos)                /*!< SCT EVSTATEMSK0: STATEMSKn3 Mask    */
#define SCT_EVSTATEMSK0_STATEMSKn4_Pos                        4                                                         /*!< SCT EVSTATEMSK0: STATEMSKn4 Position */
#define SCT_EVSTATEMSK0_STATEMSKn4_Msk                        (0x01UL << SCT_EVSTATEMSK0_STATEMSKn4_Pos)                /*!< SCT EVSTATEMSK0: STATEMSKn4 Mask    */
#define SCT_EVSTATEMSK0_STATEMSKn5_Pos                        5                                                         /*!< SCT EVSTATEMSK0: STATEMSKn5 Position */
#define SCT_EVSTATEMSK0_STATEMSKn5_Msk                        (0x01UL << SCT_EVSTATEMSK0_STATEMSKn5_Pos)                /*!< SCT EVSTATEMSK0: STATEMSKn5 Mask    */
#define SCT_EVSTATEMSK0_STATEMSKn6_Pos                        6                                                         /*!< SCT EVSTATEMSK0: STATEMSKn6 Position */
#define SCT_EVSTATEMSK0_STATEMSKn6_Msk                        (0x01UL << SCT_EVSTATEMSK0_STATEMSKn6_Pos)                /*!< SCT EVSTATEMSK0: STATEMSKn6 Mask    */
#define SCT_EVSTATEMSK0_STATEMSKn7_Pos                        7                                                         /*!< SCT EVSTATEMSK0: STATEMSKn7 Position */
#define SCT_EVSTATEMSK0_STATEMSKn7_Msk                        (0x01UL << SCT_EVSTATEMSK0_STATEMSKn7_Pos)                /*!< SCT EVSTATEMSK0: STATEMSKn7 Mask    */
#define SCT_EVSTATEMSK0_STATEMSKn8_Pos                        8                                                         /*!< SCT EVSTATEMSK0: STATEMSKn8 Position */
#define SCT_EVSTATEMSK0_STATEMSKn8_Msk                        (0x01UL << SCT_EVSTATEMSK0_STATEMSKn8_Pos)                /*!< SCT EVSTATEMSK0: STATEMSKn8 Mask    */
#define SCT_EVSTATEMSK0_STATEMSKn9_Pos                        9                                                         /*!< SCT EVSTATEMSK0: STATEMSKn9 Position */
#define SCT_EVSTATEMSK0_STATEMSKn9_Msk                        (0x01UL << SCT_EVSTATEMSK0_STATEMSKn9_Pos)                /*!< SCT EVSTATEMSK0: STATEMSKn9 Mask    */
#define SCT_EVSTATEMSK0_STATEMSKn10_Pos                       10                                                        /*!< SCT EVSTATEMSK0: STATEMSKn10 Position */
#define SCT_EVSTATEMSK0_STATEMSKn10_Msk                       (0x01UL << SCT_EVSTATEMSK0_STATEMSKn10_Pos)               /*!< SCT EVSTATEMSK0: STATEMSKn10 Mask   */
#define SCT_EVSTATEMSK0_STATEMSKn11_Pos                       11                                                        /*!< SCT EVSTATEMSK0: STATEMSKn11 Position */
#define SCT_EVSTATEMSK0_STATEMSKn11_Msk                       (0x01UL << SCT_EVSTATEMSK0_STATEMSKn11_Pos)               /*!< SCT EVSTATEMSK0: STATEMSKn11 Mask   */
#define SCT_EVSTATEMSK0_STATEMSKn12_Pos                       12                                                        /*!< SCT EVSTATEMSK0: STATEMSKn12 Position */
#define SCT_EVSTATEMSK0_STATEMSKn12_Msk                       (0x01UL << SCT_EVSTATEMSK0_STATEMSKn12_Pos)               /*!< SCT EVSTATEMSK0: STATEMSKn12 Mask   */
#define SCT_EVSTATEMSK0_STATEMSKn13_Pos                       13                                                        /*!< SCT EVSTATEMSK0: STATEMSKn13 Position */
#define SCT_EVSTATEMSK0_STATEMSKn13_Msk                       (0x01UL << SCT_EVSTATEMSK0_STATEMSKn13_Pos)               /*!< SCT EVSTATEMSK0: STATEMSKn13 Mask   */
#define SCT_EVSTATEMSK0_STATEMSKn14_Pos                       14                                                        /*!< SCT EVSTATEMSK0: STATEMSKn14 Position */
#define SCT_EVSTATEMSK0_STATEMSKn14_Msk                       (0x01UL << SCT_EVSTATEMSK0_STATEMSKn14_Pos)               /*!< SCT EVSTATEMSK0: STATEMSKn14 Mask   */
#define SCT_EVSTATEMSK0_STATEMSKn15_Pos                       15                                                        /*!< SCT EVSTATEMSK0: STATEMSKn15 Position */
#define SCT_EVSTATEMSK0_STATEMSKn15_Msk                       (0x01UL << SCT_EVSTATEMSK0_STATEMSKn15_Pos)               /*!< SCT EVSTATEMSK0: STATEMSKn15 Mask   */
#define SCT_EVSTATEMSK0_STATEMSKn16_Pos                       16                                                        /*!< SCT EVSTATEMSK0: STATEMSKn16 Position */
#define SCT_EVSTATEMSK0_STATEMSKn16_Msk                       (0x01UL << SCT_EVSTATEMSK0_STATEMSKn16_Pos)               /*!< SCT EVSTATEMSK0: STATEMSKn16 Mask   */
#define SCT_EVSTATEMSK0_STATEMSKn17_Pos                       17                                                        /*!< SCT EVSTATEMSK0: STATEMSKn17 Position */
#define SCT_EVSTATEMSK0_STATEMSKn17_Msk                       (0x01UL << SCT_EVSTATEMSK0_STATEMSKn17_Pos)               /*!< SCT EVSTATEMSK0: STATEMSKn17 Mask   */
#define SCT_EVSTATEMSK0_STATEMSKn18_Pos                       18                                                        /*!< SCT EVSTATEMSK0: STATEMSKn18 Position */
#define SCT_EVSTATEMSK0_STATEMSKn18_Msk                       (0x01UL << SCT_EVSTATEMSK0_STATEMSKn18_Pos)               /*!< SCT EVSTATEMSK0: STATEMSKn18 Mask   */
#define SCT_EVSTATEMSK0_STATEMSKn19_Pos                       19                                                        /*!< SCT EVSTATEMSK0: STATEMSKn19 Position */
#define SCT_EVSTATEMSK0_STATEMSKn19_Msk                       (0x01UL << SCT_EVSTATEMSK0_STATEMSKn19_Pos)               /*!< SCT EVSTATEMSK0: STATEMSKn19 Mask   */
#define SCT_EVSTATEMSK0_STATEMSKn20_Pos                       20                                                        /*!< SCT EVSTATEMSK0: STATEMSKn20 Position */
#define SCT_EVSTATEMSK0_STATEMSKn20_Msk                       (0x01UL << SCT_EVSTATEMSK0_STATEMSKn20_Pos)               /*!< SCT EVSTATEMSK0: STATEMSKn20 Mask   */
#define SCT_EVSTATEMSK0_STATEMSKn21_Pos                       21                                                        /*!< SCT EVSTATEMSK0: STATEMSKn21 Position */
#define SCT_EVSTATEMSK0_STATEMSKn21_Msk                       (0x01UL << SCT_EVSTATEMSK0_STATEMSKn21_Pos)               /*!< SCT EVSTATEMSK0: STATEMSKn21 Mask   */
#define SCT_EVSTATEMSK0_STATEMSKn22_Pos                       22                                                        /*!< SCT EVSTATEMSK0: STATEMSKn22 Position */
#define SCT_EVSTATEMSK0_STATEMSKn22_Msk                       (0x01UL << SCT_EVSTATEMSK0_STATEMSKn22_Pos)               /*!< SCT EVSTATEMSK0: STATEMSKn22 Mask   */
#define SCT_EVSTATEMSK0_STATEMSKn23_Pos                       23                                                        /*!< SCT EVSTATEMSK0: STATEMSKn23 Position */
#define SCT_EVSTATEMSK0_STATEMSKn23_Msk                       (0x01UL << SCT_EVSTATEMSK0_STATEMSKn23_Pos)               /*!< SCT EVSTATEMSK0: STATEMSKn23 Mask   */
#define SCT_EVSTATEMSK0_STATEMSKn24_Pos                       24                                                        /*!< SCT EVSTATEMSK0: STATEMSKn24 Position */
#define SCT_EVSTATEMSK0_STATEMSKn24_Msk                       (0x01UL << SCT_EVSTATEMSK0_STATEMSKn24_Pos)               /*!< SCT EVSTATEMSK0: STATEMSKn24 Mask   */
#define SCT_EVSTATEMSK0_STATEMSKn25_Pos                       25                                                        /*!< SCT EVSTATEMSK0: STATEMSKn25 Position */
#define SCT_EVSTATEMSK0_STATEMSKn25_Msk                       (0x01UL << SCT_EVSTATEMSK0_STATEMSKn25_Pos)               /*!< SCT EVSTATEMSK0: STATEMSKn25 Mask   */
#define SCT_EVSTATEMSK0_STATEMSKn26_Pos                       26                                                        /*!< SCT EVSTATEMSK0: STATEMSKn26 Position */
#define SCT_EVSTATEMSK0_STATEMSKn26_Msk                       (0x01UL << SCT_EVSTATEMSK0_STATEMSKn26_Pos)               /*!< SCT EVSTATEMSK0: STATEMSKn26 Mask   */
#define SCT_EVSTATEMSK0_STATEMSKn27_Pos                       27                                                        /*!< SCT EVSTATEMSK0: STATEMSKn27 Position */
#define SCT_EVSTATEMSK0_STATEMSKn27_Msk                       (0x01UL << SCT_EVSTATEMSK0_STATEMSKn27_Pos)               /*!< SCT EVSTATEMSK0: STATEMSKn27 Mask   */
#define SCT_EVSTATEMSK0_STATEMSKn28_Pos                       28                                                        /*!< SCT EVSTATEMSK0: STATEMSKn28 Position */
#define SCT_EVSTATEMSK0_STATEMSKn28_Msk                       (0x01UL << SCT_EVSTATEMSK0_STATEMSKn28_Pos)               /*!< SCT EVSTATEMSK0: STATEMSKn28 Mask   */
#define SCT_EVSTATEMSK0_STATEMSKn29_Pos                       29                                                        /*!< SCT EVSTATEMSK0: STATEMSKn29 Position */
#define SCT_EVSTATEMSK0_STATEMSKn29_Msk                       (0x01UL << SCT_EVSTATEMSK0_STATEMSKn29_Pos)               /*!< SCT EVSTATEMSK0: STATEMSKn29 Mask   */
#define SCT_EVSTATEMSK0_STATEMSKn30_Pos                       30                                                        /*!< SCT EVSTATEMSK0: STATEMSKn30 Position */
#define SCT_EVSTATEMSK0_STATEMSKn30_Msk                       (0x01UL << SCT_EVSTATEMSK0_STATEMSKn30_Pos)               /*!< SCT EVSTATEMSK0: STATEMSKn30 Mask   */
#define SCT_EVSTATEMSK0_STATEMSKn31_Pos                       31                                                        /*!< SCT EVSTATEMSK0: STATEMSKn31 Position */
#define SCT_EVSTATEMSK0_STATEMSKn31_Msk                       (0x01UL << SCT_EVSTATEMSK0_STATEMSKn31_Pos)               /*!< SCT EVSTATEMSK0: STATEMSKn31 Mask   */

// ---------------------------------------  SCT_EVCTRL0  ------------------------------------------
#define SCT_EVCTRL0_MATCHSEL_Pos                              0                                                         /*!< SCT EVCTRL0: MATCHSEL Position      */
#define SCT_EVCTRL0_MATCHSEL_Msk                              (0x0fUL << SCT_EVCTRL0_MATCHSEL_Pos)                      /*!< SCT EVCTRL0: MATCHSEL Mask          */
#define SCT_EVCTRL0_HEVENT_Pos                                4                                                         /*!< SCT EVCTRL0: HEVENT Position        */
#define SCT_EVCTRL0_HEVENT_Msk                                (0x01UL << SCT_EVCTRL0_HEVENT_Pos)                        /*!< SCT EVCTRL0: HEVENT Mask            */
#define SCT_EVCTRL0_OUTSEL_Pos                                5                                                         /*!< SCT EVCTRL0: OUTSEL Position        */
#define SCT_EVCTRL0_OUTSEL_Msk                                (0x01UL << SCT_EVCTRL0_OUTSEL_Pos)                        /*!< SCT EVCTRL0: OUTSEL Mask            */
#define SCT_EVCTRL0_IOSEL_Pos                                 6                                                         /*!< SCT EVCTRL0: IOSEL Position         */
#define SCT_EVCTRL0_IOSEL_Msk                                 (0x0fUL << SCT_EVCTRL0_IOSEL_Pos)                         /*!< SCT EVCTRL0: IOSEL Mask             */
#define SCT_EVCTRL0_IOCOND_Pos                                10                                                        /*!< SCT EVCTRL0: IOCOND Position        */
#define SCT_EVCTRL0_IOCOND_Msk                                (0x03UL << SCT_EVCTRL0_IOCOND_Pos)                        /*!< SCT EVCTRL0: IOCOND Mask            */
#define SCT_EVCTRL0_COMBMODE_Pos                              12                                                        /*!< SCT EVCTRL0: COMBMODE Position      */
#define SCT_EVCTRL0_COMBMODE_Msk                              (0x03UL << SCT_EVCTRL0_COMBMODE_Pos)                      /*!< SCT EVCTRL0: COMBMODE Mask          */
#define SCT_EVCTRL0_STATELD_Pos                               14                                                        /*!< SCT EVCTRL0: STATELD Position       */
#define SCT_EVCTRL0_STATELD_Msk                               (0x01UL << SCT_EVCTRL0_STATELD_Pos)                       /*!< SCT EVCTRL0: STATELD Mask           */
#define SCT_EVCTRL0_STATEV_Pos                                15                                                        /*!< SCT EVCTRL0: STATEV Position        */
#define SCT_EVCTRL0_STATEV_Msk                                (0x1fUL << SCT_EVCTRL0_STATEV_Pos)                        /*!< SCT EVCTRL0: STATEV Mask            */

// -------------------------------------  SCT_EVSTATEMSK1  ----------------------------------------
#define SCT_EVSTATEMSK1_STATEMSKn0_Pos                        0                                                         /*!< SCT EVSTATEMSK1: STATEMSKn0 Position */
#define SCT_EVSTATEMSK1_STATEMSKn0_Msk                        (0x01UL << SCT_EVSTATEMSK1_STATEMSKn0_Pos)                /*!< SCT EVSTATEMSK1: STATEMSKn0 Mask    */
#define SCT_EVSTATEMSK1_STATEMSKn1_Pos                        1                                                         /*!< SCT EVSTATEMSK1: STATEMSKn1 Position */
#define SCT_EVSTATEMSK1_STATEMSKn1_Msk                        (0x01UL << SCT_EVSTATEMSK1_STATEMSKn1_Pos)                /*!< SCT EVSTATEMSK1: STATEMSKn1 Mask    */
#define SCT_EVSTATEMSK1_STATEMSKn2_Pos                        2                                                         /*!< SCT EVSTATEMSK1: STATEMSKn2 Position */
#define SCT_EVSTATEMSK1_STATEMSKn2_Msk                        (0x01UL << SCT_EVSTATEMSK1_STATEMSKn2_Pos)                /*!< SCT EVSTATEMSK1: STATEMSKn2 Mask    */
#define SCT_EVSTATEMSK1_STATEMSKn3_Pos                        3                                                         /*!< SCT EVSTATEMSK1: STATEMSKn3 Position */
#define SCT_EVSTATEMSK1_STATEMSKn3_Msk                        (0x01UL << SCT_EVSTATEMSK1_STATEMSKn3_Pos)                /*!< SCT EVSTATEMSK1: STATEMSKn3 Mask    */
#define SCT_EVSTATEMSK1_STATEMSKn4_Pos                        4                                                         /*!< SCT EVSTATEMSK1: STATEMSKn4 Position */
#define SCT_EVSTATEMSK1_STATEMSKn4_Msk                        (0x01UL << SCT_EVSTATEMSK1_STATEMSKn4_Pos)                /*!< SCT EVSTATEMSK1: STATEMSKn4 Mask    */
#define SCT_EVSTATEMSK1_STATEMSKn5_Pos                        5                                                         /*!< SCT EVSTATEMSK1: STATEMSKn5 Position */
#define SCT_EVSTATEMSK1_STATEMSKn5_Msk                        (0x01UL << SCT_EVSTATEMSK1_STATEMSKn5_Pos)                /*!< SCT EVSTATEMSK1: STATEMSKn5 Mask    */
#define SCT_EVSTATEMSK1_STATEMSKn6_Pos                        6                                                         /*!< SCT EVSTATEMSK1: STATEMSKn6 Position */
#define SCT_EVSTATEMSK1_STATEMSKn6_Msk                        (0x01UL << SCT_EVSTATEMSK1_STATEMSKn6_Pos)                /*!< SCT EVSTATEMSK1: STATEMSKn6 Mask    */
#define SCT_EVSTATEMSK1_STATEMSKn7_Pos                        7                                                         /*!< SCT EVSTATEMSK1: STATEMSKn7 Position */
#define SCT_EVSTATEMSK1_STATEMSKn7_Msk                        (0x01UL << SCT_EVSTATEMSK1_STATEMSKn7_Pos)                /*!< SCT EVSTATEMSK1: STATEMSKn7 Mask    */
#define SCT_EVSTATEMSK1_STATEMSKn8_Pos                        8                                                         /*!< SCT EVSTATEMSK1: STATEMSKn8 Position */
#define SCT_EVSTATEMSK1_STATEMSKn8_Msk                        (0x01UL << SCT_EVSTATEMSK1_STATEMSKn8_Pos)                /*!< SCT EVSTATEMSK1: STATEMSKn8 Mask    */
#define SCT_EVSTATEMSK1_STATEMSKn9_Pos                        9                                                         /*!< SCT EVSTATEMSK1: STATEMSKn9 Position */
#define SCT_EVSTATEMSK1_STATEMSKn9_Msk                        (0x01UL << SCT_EVSTATEMSK1_STATEMSKn9_Pos)                /*!< SCT EVSTATEMSK1: STATEMSKn9 Mask    */
#define SCT_EVSTATEMSK1_STATEMSKn10_Pos                       10                                                        /*!< SCT EVSTATEMSK1: STATEMSKn10 Position */
#define SCT_EVSTATEMSK1_STATEMSKn10_Msk                       (0x01UL << SCT_EVSTATEMSK1_STATEMSKn10_Pos)               /*!< SCT EVSTATEMSK1: STATEMSKn10 Mask   */
#define SCT_EVSTATEMSK1_STATEMSKn11_Pos                       11                                                        /*!< SCT EVSTATEMSK1: STATEMSKn11 Position */
#define SCT_EVSTATEMSK1_STATEMSKn11_Msk                       (0x01UL << SCT_EVSTATEMSK1_STATEMSKn11_Pos)               /*!< SCT EVSTATEMSK1: STATEMSKn11 Mask   */
#define SCT_EVSTATEMSK1_STATEMSKn12_Pos                       12                                                        /*!< SCT EVSTATEMSK1: STATEMSKn12 Position */
#define SCT_EVSTATEMSK1_STATEMSKn12_Msk                       (0x01UL << SCT_EVSTATEMSK1_STATEMSKn12_Pos)               /*!< SCT EVSTATEMSK1: STATEMSKn12 Mask   */
#define SCT_EVSTATEMSK1_STATEMSKn13_Pos                       13                                                        /*!< SCT EVSTATEMSK1: STATEMSKn13 Position */
#define SCT_EVSTATEMSK1_STATEMSKn13_Msk                       (0x01UL << SCT_EVSTATEMSK1_STATEMSKn13_Pos)               /*!< SCT EVSTATEMSK1: STATEMSKn13 Mask   */
#define SCT_EVSTATEMSK1_STATEMSKn14_Pos                       14                                                        /*!< SCT EVSTATEMSK1: STATEMSKn14 Position */
#define SCT_EVSTATEMSK1_STATEMSKn14_Msk                       (0x01UL << SCT_EVSTATEMSK1_STATEMSKn14_Pos)               /*!< SCT EVSTATEMSK1: STATEMSKn14 Mask   */
#define SCT_EVSTATEMSK1_STATEMSKn15_Pos                       15                                                        /*!< SCT EVSTATEMSK1: STATEMSKn15 Position */
#define SCT_EVSTATEMSK1_STATEMSKn15_Msk                       (0x01UL << SCT_EVSTATEMSK1_STATEMSKn15_Pos)               /*!< SCT EVSTATEMSK1: STATEMSKn15 Mask   */
#define SCT_EVSTATEMSK1_STATEMSKn16_Pos                       16                                                        /*!< SCT EVSTATEMSK1: STATEMSKn16 Position */
#define SCT_EVSTATEMSK1_STATEMSKn16_Msk                       (0x01UL << SCT_EVSTATEMSK1_STATEMSKn16_Pos)               /*!< SCT EVSTATEMSK1: STATEMSKn16 Mask   */
#define SCT_EVSTATEMSK1_STATEMSKn17_Pos                       17                                                        /*!< SCT EVSTATEMSK1: STATEMSKn17 Position */
#define SCT_EVSTATEMSK1_STATEMSKn17_Msk                       (0x01UL << SCT_EVSTATEMSK1_STATEMSKn17_Pos)               /*!< SCT EVSTATEMSK1: STATEMSKn17 Mask   */
#define SCT_EVSTATEMSK1_STATEMSKn18_Pos                       18                                                        /*!< SCT EVSTATEMSK1: STATEMSKn18 Position */
#define SCT_EVSTATEMSK1_STATEMSKn18_Msk                       (0x01UL << SCT_EVSTATEMSK1_STATEMSKn18_Pos)               /*!< SCT EVSTATEMSK1: STATEMSKn18 Mask   */
#define SCT_EVSTATEMSK1_STATEMSKn19_Pos                       19                                                        /*!< SCT EVSTATEMSK1: STATEMSKn19 Position */
#define SCT_EVSTATEMSK1_STATEMSKn19_Msk                       (0x01UL << SCT_EVSTATEMSK1_STATEMSKn19_Pos)               /*!< SCT EVSTATEMSK1: STATEMSKn19 Mask   */
#define SCT_EVSTATEMSK1_STATEMSKn20_Pos                       20                                                        /*!< SCT EVSTATEMSK1: STATEMSKn20 Position */
#define SCT_EVSTATEMSK1_STATEMSKn20_Msk                       (0x01UL << SCT_EVSTATEMSK1_STATEMSKn20_Pos)               /*!< SCT EVSTATEMSK1: STATEMSKn20 Mask   */
#define SCT_EVSTATEMSK1_STATEMSKn21_Pos                       21                                                        /*!< SCT EVSTATEMSK1: STATEMSKn21 Position */
#define SCT_EVSTATEMSK1_STATEMSKn21_Msk                       (0x01UL << SCT_EVSTATEMSK1_STATEMSKn21_Pos)               /*!< SCT EVSTATEMSK1: STATEMSKn21 Mask   */
#define SCT_EVSTATEMSK1_STATEMSKn22_Pos                       22                                                        /*!< SCT EVSTATEMSK1: STATEMSKn22 Position */
#define SCT_EVSTATEMSK1_STATEMSKn22_Msk                       (0x01UL << SCT_EVSTATEMSK1_STATEMSKn22_Pos)               /*!< SCT EVSTATEMSK1: STATEMSKn22 Mask   */
#define SCT_EVSTATEMSK1_STATEMSKn23_Pos                       23                                                        /*!< SCT EVSTATEMSK1: STATEMSKn23 Position */
#define SCT_EVSTATEMSK1_STATEMSKn23_Msk                       (0x01UL << SCT_EVSTATEMSK1_STATEMSKn23_Pos)               /*!< SCT EVSTATEMSK1: STATEMSKn23 Mask   */
#define SCT_EVSTATEMSK1_STATEMSKn24_Pos                       24                                                        /*!< SCT EVSTATEMSK1: STATEMSKn24 Position */
#define SCT_EVSTATEMSK1_STATEMSKn24_Msk                       (0x01UL << SCT_EVSTATEMSK1_STATEMSKn24_Pos)               /*!< SCT EVSTATEMSK1: STATEMSKn24 Mask   */
#define SCT_EVSTATEMSK1_STATEMSKn25_Pos                       25                                                        /*!< SCT EVSTATEMSK1: STATEMSKn25 Position */
#define SCT_EVSTATEMSK1_STATEMSKn25_Msk                       (0x01UL << SCT_EVSTATEMSK1_STATEMSKn25_Pos)               /*!< SCT EVSTATEMSK1: STATEMSKn25 Mask   */
#define SCT_EVSTATEMSK1_STATEMSKn26_Pos                       26                                                        /*!< SCT EVSTATEMSK1: STATEMSKn26 Position */
#define SCT_EVSTATEMSK1_STATEMSKn26_Msk                       (0x01UL << SCT_EVSTATEMSK1_STATEMSKn26_Pos)               /*!< SCT EVSTATEMSK1: STATEMSKn26 Mask   */
#define SCT_EVSTATEMSK1_STATEMSKn27_Pos                       27                                                        /*!< SCT EVSTATEMSK1: STATEMSKn27 Position */
#define SCT_EVSTATEMSK1_STATEMSKn27_Msk                       (0x01UL << SCT_EVSTATEMSK1_STATEMSKn27_Pos)               /*!< SCT EVSTATEMSK1: STATEMSKn27 Mask   */
#define SCT_EVSTATEMSK1_STATEMSKn28_Pos                       28                                                        /*!< SCT EVSTATEMSK1: STATEMSKn28 Position */
#define SCT_EVSTATEMSK1_STATEMSKn28_Msk                       (0x01UL << SCT_EVSTATEMSK1_STATEMSKn28_Pos)               /*!< SCT EVSTATEMSK1: STATEMSKn28 Mask   */
#define SCT_EVSTATEMSK1_STATEMSKn29_Pos                       29                                                        /*!< SCT EVSTATEMSK1: STATEMSKn29 Position */
#define SCT_EVSTATEMSK1_STATEMSKn29_Msk                       (0x01UL << SCT_EVSTATEMSK1_STATEMSKn29_Pos)               /*!< SCT EVSTATEMSK1: STATEMSKn29 Mask   */
#define SCT_EVSTATEMSK1_STATEMSKn30_Pos                       30                                                        /*!< SCT EVSTATEMSK1: STATEMSKn30 Position */
#define SCT_EVSTATEMSK1_STATEMSKn30_Msk                       (0x01UL << SCT_EVSTATEMSK1_STATEMSKn30_Pos)               /*!< SCT EVSTATEMSK1: STATEMSKn30 Mask   */
#define SCT_EVSTATEMSK1_STATEMSKn31_Pos                       31                                                        /*!< SCT EVSTATEMSK1: STATEMSKn31 Position */
#define SCT_EVSTATEMSK1_STATEMSKn31_Msk                       (0x01UL << SCT_EVSTATEMSK1_STATEMSKn31_Pos)               /*!< SCT EVSTATEMSK1: STATEMSKn31 Mask   */

// ---------------------------------------  SCT_EVCTRL1  ------------------------------------------
#define SCT_EVCTRL1_MATCHSEL_Pos                              0                                                         /*!< SCT EVCTRL1: MATCHSEL Position      */
#define SCT_EVCTRL1_MATCHSEL_Msk                              (0x0fUL << SCT_EVCTRL1_MATCHSEL_Pos)                      /*!< SCT EVCTRL1: MATCHSEL Mask          */
#define SCT_EVCTRL1_HEVENT_Pos                                4                                                         /*!< SCT EVCTRL1: HEVENT Position        */
#define SCT_EVCTRL1_HEVENT_Msk                                (0x01UL << SCT_EVCTRL1_HEVENT_Pos)                        /*!< SCT EVCTRL1: HEVENT Mask            */
#define SCT_EVCTRL1_OUTSEL_Pos                                5                                                         /*!< SCT EVCTRL1: OUTSEL Position        */
#define SCT_EVCTRL1_OUTSEL_Msk                                (0x01UL << SCT_EVCTRL1_OUTSEL_Pos)                        /*!< SCT EVCTRL1: OUTSEL Mask            */
#define SCT_EVCTRL1_IOSEL_Pos                                 6                                                         /*!< SCT EVCTRL1: IOSEL Position         */
#define SCT_EVCTRL1_IOSEL_Msk                                 (0x0fUL << SCT_EVCTRL1_IOSEL_Pos)                         /*!< SCT EVCTRL1: IOSEL Mask             */
#define SCT_EVCTRL1_IOCOND_Pos                                10                                                        /*!< SCT EVCTRL1: IOCOND Position        */
#define SCT_EVCTRL1_IOCOND_Msk                                (0x03UL << SCT_EVCTRL1_IOCOND_Pos)                        /*!< SCT EVCTRL1: IOCOND Mask            */
#define SCT_EVCTRL1_COMBMODE_Pos                              12                                                        /*!< SCT EVCTRL1: COMBMODE Position      */
#define SCT_EVCTRL1_COMBMODE_Msk                              (0x03UL << SCT_EVCTRL1_COMBMODE_Pos)                      /*!< SCT EVCTRL1: COMBMODE Mask          */
#define SCT_EVCTRL1_STATELD_Pos                               14                                                        /*!< SCT EVCTRL1: STATELD Position       */
#define SCT_EVCTRL1_STATELD_Msk                               (0x01UL << SCT_EVCTRL1_STATELD_Pos)                       /*!< SCT EVCTRL1: STATELD Mask           */
#define SCT_EVCTRL1_STATEV_Pos                                15                                                        /*!< SCT EVCTRL1: STATEV Position        */
#define SCT_EVCTRL1_STATEV_Msk                                (0x1fUL << SCT_EVCTRL1_STATEV_Pos)                        /*!< SCT EVCTRL1: STATEV Mask            */

// -------------------------------------  SCT_EVSTATEMSK2  ----------------------------------------
#define SCT_EVSTATEMSK2_STATEMSKn0_Pos                        0                                                         /*!< SCT EVSTATEMSK2: STATEMSKn0 Position */
#define SCT_EVSTATEMSK2_STATEMSKn0_Msk                        (0x01UL << SCT_EVSTATEMSK2_STATEMSKn0_Pos)                /*!< SCT EVSTATEMSK2: STATEMSKn0 Mask    */
#define SCT_EVSTATEMSK2_STATEMSKn1_Pos                        1                                                         /*!< SCT EVSTATEMSK2: STATEMSKn1 Position */
#define SCT_EVSTATEMSK2_STATEMSKn1_Msk                        (0x01UL << SCT_EVSTATEMSK2_STATEMSKn1_Pos)                /*!< SCT EVSTATEMSK2: STATEMSKn1 Mask    */
#define SCT_EVSTATEMSK2_STATEMSKn2_Pos                        2                                                         /*!< SCT EVSTATEMSK2: STATEMSKn2 Position */
#define SCT_EVSTATEMSK2_STATEMSKn2_Msk                        (0x01UL << SCT_EVSTATEMSK2_STATEMSKn2_Pos)                /*!< SCT EVSTATEMSK2: STATEMSKn2 Mask    */
#define SCT_EVSTATEMSK2_STATEMSKn3_Pos                        3                                                         /*!< SCT EVSTATEMSK2: STATEMSKn3 Position */
#define SCT_EVSTATEMSK2_STATEMSKn3_Msk                        (0x01UL << SCT_EVSTATEMSK2_STATEMSKn3_Pos)                /*!< SCT EVSTATEMSK2: STATEMSKn3 Mask    */
#define SCT_EVSTATEMSK2_STATEMSKn4_Pos                        4                                                         /*!< SCT EVSTATEMSK2: STATEMSKn4 Position */
#define SCT_EVSTATEMSK2_STATEMSKn4_Msk                        (0x01UL << SCT_EVSTATEMSK2_STATEMSKn4_Pos)                /*!< SCT EVSTATEMSK2: STATEMSKn4 Mask    */
#define SCT_EVSTATEMSK2_STATEMSKn5_Pos                        5                                                         /*!< SCT EVSTATEMSK2: STATEMSKn5 Position */
#define SCT_EVSTATEMSK2_STATEMSKn5_Msk                        (0x01UL << SCT_EVSTATEMSK2_STATEMSKn5_Pos)                /*!< SCT EVSTATEMSK2: STATEMSKn5 Mask    */
#define SCT_EVSTATEMSK2_STATEMSKn6_Pos                        6                                                         /*!< SCT EVSTATEMSK2: STATEMSKn6 Position */
#define SCT_EVSTATEMSK2_STATEMSKn6_Msk                        (0x01UL << SCT_EVSTATEMSK2_STATEMSKn6_Pos)                /*!< SCT EVSTATEMSK2: STATEMSKn6 Mask    */
#define SCT_EVSTATEMSK2_STATEMSKn7_Pos                        7                                                         /*!< SCT EVSTATEMSK2: STATEMSKn7 Position */
#define SCT_EVSTATEMSK2_STATEMSKn7_Msk                        (0x01UL << SCT_EVSTATEMSK2_STATEMSKn7_Pos)                /*!< SCT EVSTATEMSK2: STATEMSKn7 Mask    */
#define SCT_EVSTATEMSK2_STATEMSKn8_Pos                        8                                                         /*!< SCT EVSTATEMSK2: STATEMSKn8 Position */
#define SCT_EVSTATEMSK2_STATEMSKn8_Msk                        (0x01UL << SCT_EVSTATEMSK2_STATEMSKn8_Pos)                /*!< SCT EVSTATEMSK2: STATEMSKn8 Mask    */
#define SCT_EVSTATEMSK2_STATEMSKn9_Pos                        9                                                         /*!< SCT EVSTATEMSK2: STATEMSKn9 Position */
#define SCT_EVSTATEMSK2_STATEMSKn9_Msk                        (0x01UL << SCT_EVSTATEMSK2_STATEMSKn9_Pos)                /*!< SCT EVSTATEMSK2: STATEMSKn9 Mask    */
#define SCT_EVSTATEMSK2_STATEMSKn10_Pos                       10                                                        /*!< SCT EVSTATEMSK2: STATEMSKn10 Position */
#define SCT_EVSTATEMSK2_STATEMSKn10_Msk                       (0x01UL << SCT_EVSTATEMSK2_STATEMSKn10_Pos)               /*!< SCT EVSTATEMSK2: STATEMSKn10 Mask   */
#define SCT_EVSTATEMSK2_STATEMSKn11_Pos                       11                                                        /*!< SCT EVSTATEMSK2: STATEMSKn11 Position */
#define SCT_EVSTATEMSK2_STATEMSKn11_Msk                       (0x01UL << SCT_EVSTATEMSK2_STATEMSKn11_Pos)               /*!< SCT EVSTATEMSK2: STATEMSKn11 Mask   */
#define SCT_EVSTATEMSK2_STATEMSKn12_Pos                       12                                                        /*!< SCT EVSTATEMSK2: STATEMSKn12 Position */
#define SCT_EVSTATEMSK2_STATEMSKn12_Msk                       (0x01UL << SCT_EVSTATEMSK2_STATEMSKn12_Pos)               /*!< SCT EVSTATEMSK2: STATEMSKn12 Mask   */
#define SCT_EVSTATEMSK2_STATEMSKn13_Pos                       13                                                        /*!< SCT EVSTATEMSK2: STATEMSKn13 Position */
#define SCT_EVSTATEMSK2_STATEMSKn13_Msk                       (0x01UL << SCT_EVSTATEMSK2_STATEMSKn13_Pos)               /*!< SCT EVSTATEMSK2: STATEMSKn13 Mask   */
#define SCT_EVSTATEMSK2_STATEMSKn14_Pos                       14                                                        /*!< SCT EVSTATEMSK2: STATEMSKn14 Position */
#define SCT_EVSTATEMSK2_STATEMSKn14_Msk                       (0x01UL << SCT_EVSTATEMSK2_STATEMSKn14_Pos)               /*!< SCT EVSTATEMSK2: STATEMSKn14 Mask   */
#define SCT_EVSTATEMSK2_STATEMSKn15_Pos                       15                                                        /*!< SCT EVSTATEMSK2: STATEMSKn15 Position */
#define SCT_EVSTATEMSK2_STATEMSKn15_Msk                       (0x01UL << SCT_EVSTATEMSK2_STATEMSKn15_Pos)               /*!< SCT EVSTATEMSK2: STATEMSKn15 Mask   */
#define SCT_EVSTATEMSK2_STATEMSKn16_Pos                       16                                                        /*!< SCT EVSTATEMSK2: STATEMSKn16 Position */
#define SCT_EVSTATEMSK2_STATEMSKn16_Msk                       (0x01UL << SCT_EVSTATEMSK2_STATEMSKn16_Pos)               /*!< SCT EVSTATEMSK2: STATEMSKn16 Mask   */
#define SCT_EVSTATEMSK2_STATEMSKn17_Pos                       17                                                        /*!< SCT EVSTATEMSK2: STATEMSKn17 Position */
#define SCT_EVSTATEMSK2_STATEMSKn17_Msk                       (0x01UL << SCT_EVSTATEMSK2_STATEMSKn17_Pos)               /*!< SCT EVSTATEMSK2: STATEMSKn17 Mask   */
#define SCT_EVSTATEMSK2_STATEMSKn18_Pos                       18                                                        /*!< SCT EVSTATEMSK2: STATEMSKn18 Position */
#define SCT_EVSTATEMSK2_STATEMSKn18_Msk                       (0x01UL << SCT_EVSTATEMSK2_STATEMSKn18_Pos)               /*!< SCT EVSTATEMSK2: STATEMSKn18 Mask   */
#define SCT_EVSTATEMSK2_STATEMSKn19_Pos                       19                                                        /*!< SCT EVSTATEMSK2: STATEMSKn19 Position */
#define SCT_EVSTATEMSK2_STATEMSKn19_Msk                       (0x01UL << SCT_EVSTATEMSK2_STATEMSKn19_Pos)               /*!< SCT EVSTATEMSK2: STATEMSKn19 Mask   */
#define SCT_EVSTATEMSK2_STATEMSKn20_Pos                       20                                                        /*!< SCT EVSTATEMSK2: STATEMSKn20 Position */
#define SCT_EVSTATEMSK2_STATEMSKn20_Msk                       (0x01UL << SCT_EVSTATEMSK2_STATEMSKn20_Pos)               /*!< SCT EVSTATEMSK2: STATEMSKn20 Mask   */
#define SCT_EVSTATEMSK2_STATEMSKn21_Pos                       21                                                        /*!< SCT EVSTATEMSK2: STATEMSKn21 Position */
#define SCT_EVSTATEMSK2_STATEMSKn21_Msk                       (0x01UL << SCT_EVSTATEMSK2_STATEMSKn21_Pos)               /*!< SCT EVSTATEMSK2: STATEMSKn21 Mask   */
#define SCT_EVSTATEMSK2_STATEMSKn22_Pos                       22                                                        /*!< SCT EVSTATEMSK2: STATEMSKn22 Position */
#define SCT_EVSTATEMSK2_STATEMSKn22_Msk                       (0x01UL << SCT_EVSTATEMSK2_STATEMSKn22_Pos)               /*!< SCT EVSTATEMSK2: STATEMSKn22 Mask   */
#define SCT_EVSTATEMSK2_STATEMSKn23_Pos                       23                                                        /*!< SCT EVSTATEMSK2: STATEMSKn23 Position */
#define SCT_EVSTATEMSK2_STATEMSKn23_Msk                       (0x01UL << SCT_EVSTATEMSK2_STATEMSKn23_Pos)               /*!< SCT EVSTATEMSK2: STATEMSKn23 Mask   */
#define SCT_EVSTATEMSK2_STATEMSKn24_Pos                       24                                                        /*!< SCT EVSTATEMSK2: STATEMSKn24 Position */
#define SCT_EVSTATEMSK2_STATEMSKn24_Msk                       (0x01UL << SCT_EVSTATEMSK2_STATEMSKn24_Pos)               /*!< SCT EVSTATEMSK2: STATEMSKn24 Mask   */
#define SCT_EVSTATEMSK2_STATEMSKn25_Pos                       25                                                        /*!< SCT EVSTATEMSK2: STATEMSKn25 Position */
#define SCT_EVSTATEMSK2_STATEMSKn25_Msk                       (0x01UL << SCT_EVSTATEMSK2_STATEMSKn25_Pos)               /*!< SCT EVSTATEMSK2: STATEMSKn25 Mask   */
#define SCT_EVSTATEMSK2_STATEMSKn26_Pos                       26                                                        /*!< SCT EVSTATEMSK2: STATEMSKn26 Position */
#define SCT_EVSTATEMSK2_STATEMSKn26_Msk                       (0x01UL << SCT_EVSTATEMSK2_STATEMSKn26_Pos)               /*!< SCT EVSTATEMSK2: STATEMSKn26 Mask   */
#define SCT_EVSTATEMSK2_STATEMSKn27_Pos                       27                                                        /*!< SCT EVSTATEMSK2: STATEMSKn27 Position */
#define SCT_EVSTATEMSK2_STATEMSKn27_Msk                       (0x01UL << SCT_EVSTATEMSK2_STATEMSKn27_Pos)               /*!< SCT EVSTATEMSK2: STATEMSKn27 Mask   */
#define SCT_EVSTATEMSK2_STATEMSKn28_Pos                       28                                                        /*!< SCT EVSTATEMSK2: STATEMSKn28 Position */
#define SCT_EVSTATEMSK2_STATEMSKn28_Msk                       (0x01UL << SCT_EVSTATEMSK2_STATEMSKn28_Pos)               /*!< SCT EVSTATEMSK2: STATEMSKn28 Mask   */
#define SCT_EVSTATEMSK2_STATEMSKn29_Pos                       29                                                        /*!< SCT EVSTATEMSK2: STATEMSKn29 Position */
#define SCT_EVSTATEMSK2_STATEMSKn29_Msk                       (0x01UL << SCT_EVSTATEMSK2_STATEMSKn29_Pos)               /*!< SCT EVSTATEMSK2: STATEMSKn29 Mask   */
#define SCT_EVSTATEMSK2_STATEMSKn30_Pos                       30                                                        /*!< SCT EVSTATEMSK2: STATEMSKn30 Position */
#define SCT_EVSTATEMSK2_STATEMSKn30_Msk                       (0x01UL << SCT_EVSTATEMSK2_STATEMSKn30_Pos)               /*!< SCT EVSTATEMSK2: STATEMSKn30 Mask   */
#define SCT_EVSTATEMSK2_STATEMSKn31_Pos                       31                                                        /*!< SCT EVSTATEMSK2: STATEMSKn31 Position */
#define SCT_EVSTATEMSK2_STATEMSKn31_Msk                       (0x01UL << SCT_EVSTATEMSK2_STATEMSKn31_Pos)               /*!< SCT EVSTATEMSK2: STATEMSKn31 Mask   */

// ---------------------------------------  SCT_EVCTRL2  ------------------------------------------
#define SCT_EVCTRL2_MATCHSEL_Pos                              0                                                         /*!< SCT EVCTRL2: MATCHSEL Position      */
#define SCT_EVCTRL2_MATCHSEL_Msk                              (0x0fUL << SCT_EVCTRL2_MATCHSEL_Pos)                      /*!< SCT EVCTRL2: MATCHSEL Mask          */
#define SCT_EVCTRL2_HEVENT_Pos                                4                                                         /*!< SCT EVCTRL2: HEVENT Position        */
#define SCT_EVCTRL2_HEVENT_Msk                                (0x01UL << SCT_EVCTRL2_HEVENT_Pos)                        /*!< SCT EVCTRL2: HEVENT Mask            */
#define SCT_EVCTRL2_OUTSEL_Pos                                5                                                         /*!< SCT EVCTRL2: OUTSEL Position        */
#define SCT_EVCTRL2_OUTSEL_Msk                                (0x01UL << SCT_EVCTRL2_OUTSEL_Pos)                        /*!< SCT EVCTRL2: OUTSEL Mask            */
#define SCT_EVCTRL2_IOSEL_Pos                                 6                                                         /*!< SCT EVCTRL2: IOSEL Position         */
#define SCT_EVCTRL2_IOSEL_Msk                                 (0x0fUL << SCT_EVCTRL2_IOSEL_Pos)                         /*!< SCT EVCTRL2: IOSEL Mask             */
#define SCT_EVCTRL2_IOCOND_Pos                                10                                                        /*!< SCT EVCTRL2: IOCOND Position        */
#define SCT_EVCTRL2_IOCOND_Msk                                (0x03UL << SCT_EVCTRL2_IOCOND_Pos)                        /*!< SCT EVCTRL2: IOCOND Mask            */
#define SCT_EVCTRL2_COMBMODE_Pos                              12                                                        /*!< SCT EVCTRL2: COMBMODE Position      */
#define SCT_EVCTRL2_COMBMODE_Msk                              (0x03UL << SCT_EVCTRL2_COMBMODE_Pos)                      /*!< SCT EVCTRL2: COMBMODE Mask          */
#define SCT_EVCTRL2_STATELD_Pos                               14                                                        /*!< SCT EVCTRL2: STATELD Position       */
#define SCT_EVCTRL2_STATELD_Msk                               (0x01UL << SCT_EVCTRL2_STATELD_Pos)                       /*!< SCT EVCTRL2: STATELD Mask           */
#define SCT_EVCTRL2_STATEV_Pos                                15                                                        /*!< SCT EVCTRL2: STATEV Position        */
#define SCT_EVCTRL2_STATEV_Msk                                (0x1fUL << SCT_EVCTRL2_STATEV_Pos)                        /*!< SCT EVCTRL2: STATEV Mask            */

// -------------------------------------  SCT_EVSTATEMSK3  ----------------------------------------
#define SCT_EVSTATEMSK3_STATEMSKn0_Pos                        0                                                         /*!< SCT EVSTATEMSK3: STATEMSKn0 Position */
#define SCT_EVSTATEMSK3_STATEMSKn0_Msk                        (0x01UL << SCT_EVSTATEMSK3_STATEMSKn0_Pos)                /*!< SCT EVSTATEMSK3: STATEMSKn0 Mask    */
#define SCT_EVSTATEMSK3_STATEMSKn1_Pos                        1                                                         /*!< SCT EVSTATEMSK3: STATEMSKn1 Position */
#define SCT_EVSTATEMSK3_STATEMSKn1_Msk                        (0x01UL << SCT_EVSTATEMSK3_STATEMSKn1_Pos)                /*!< SCT EVSTATEMSK3: STATEMSKn1 Mask    */
#define SCT_EVSTATEMSK3_STATEMSKn2_Pos                        2                                                         /*!< SCT EVSTATEMSK3: STATEMSKn2 Position */
#define SCT_EVSTATEMSK3_STATEMSKn2_Msk                        (0x01UL << SCT_EVSTATEMSK3_STATEMSKn2_Pos)                /*!< SCT EVSTATEMSK3: STATEMSKn2 Mask    */
#define SCT_EVSTATEMSK3_STATEMSKn3_Pos                        3                                                         /*!< SCT EVSTATEMSK3: STATEMSKn3 Position */
#define SCT_EVSTATEMSK3_STATEMSKn3_Msk                        (0x01UL << SCT_EVSTATEMSK3_STATEMSKn3_Pos)                /*!< SCT EVSTATEMSK3: STATEMSKn3 Mask    */
#define SCT_EVSTATEMSK3_STATEMSKn4_Pos                        4                                                         /*!< SCT EVSTATEMSK3: STATEMSKn4 Position */
#define SCT_EVSTATEMSK3_STATEMSKn4_Msk                        (0x01UL << SCT_EVSTATEMSK3_STATEMSKn4_Pos)                /*!< SCT EVSTATEMSK3: STATEMSKn4 Mask    */
#define SCT_EVSTATEMSK3_STATEMSKn5_Pos                        5                                                         /*!< SCT EVSTATEMSK3: STATEMSKn5 Position */
#define SCT_EVSTATEMSK3_STATEMSKn5_Msk                        (0x01UL << SCT_EVSTATEMSK3_STATEMSKn5_Pos)                /*!< SCT EVSTATEMSK3: STATEMSKn5 Mask    */
#define SCT_EVSTATEMSK3_STATEMSKn6_Pos                        6                                                         /*!< SCT EVSTATEMSK3: STATEMSKn6 Position */
#define SCT_EVSTATEMSK3_STATEMSKn6_Msk                        (0x01UL << SCT_EVSTATEMSK3_STATEMSKn6_Pos)                /*!< SCT EVSTATEMSK3: STATEMSKn6 Mask    */
#define SCT_EVSTATEMSK3_STATEMSKn7_Pos                        7                                                         /*!< SCT EVSTATEMSK3: STATEMSKn7 Position */
#define SCT_EVSTATEMSK3_STATEMSKn7_Msk                        (0x01UL << SCT_EVSTATEMSK3_STATEMSKn7_Pos)                /*!< SCT EVSTATEMSK3: STATEMSKn7 Mask    */
#define SCT_EVSTATEMSK3_STATEMSKn8_Pos                        8                                                         /*!< SCT EVSTATEMSK3: STATEMSKn8 Position */
#define SCT_EVSTATEMSK3_STATEMSKn8_Msk                        (0x01UL << SCT_EVSTATEMSK3_STATEMSKn8_Pos)                /*!< SCT EVSTATEMSK3: STATEMSKn8 Mask    */
#define SCT_EVSTATEMSK3_STATEMSKn9_Pos                        9                                                         /*!< SCT EVSTATEMSK3: STATEMSKn9 Position */
#define SCT_EVSTATEMSK3_STATEMSKn9_Msk                        (0x01UL << SCT_EVSTATEMSK3_STATEMSKn9_Pos)                /*!< SCT EVSTATEMSK3: STATEMSKn9 Mask    */
#define SCT_EVSTATEMSK3_STATEMSKn10_Pos                       10                                                        /*!< SCT EVSTATEMSK3: STATEMSKn10 Position */
#define SCT_EVSTATEMSK3_STATEMSKn10_Msk                       (0x01UL << SCT_EVSTATEMSK3_STATEMSKn10_Pos)               /*!< SCT EVSTATEMSK3: STATEMSKn10 Mask   */
#define SCT_EVSTATEMSK3_STATEMSKn11_Pos                       11                                                        /*!< SCT EVSTATEMSK3: STATEMSKn11 Position */
#define SCT_EVSTATEMSK3_STATEMSKn11_Msk                       (0x01UL << SCT_EVSTATEMSK3_STATEMSKn11_Pos)               /*!< SCT EVSTATEMSK3: STATEMSKn11 Mask   */
#define SCT_EVSTATEMSK3_STATEMSKn12_Pos                       12                                                        /*!< SCT EVSTATEMSK3: STATEMSKn12 Position */
#define SCT_EVSTATEMSK3_STATEMSKn12_Msk                       (0x01UL << SCT_EVSTATEMSK3_STATEMSKn12_Pos)               /*!< SCT EVSTATEMSK3: STATEMSKn12 Mask   */
#define SCT_EVSTATEMSK3_STATEMSKn13_Pos                       13                                                        /*!< SCT EVSTATEMSK3: STATEMSKn13 Position */
#define SCT_EVSTATEMSK3_STATEMSKn13_Msk                       (0x01UL << SCT_EVSTATEMSK3_STATEMSKn13_Pos)               /*!< SCT EVSTATEMSK3: STATEMSKn13 Mask   */
#define SCT_EVSTATEMSK3_STATEMSKn14_Pos                       14                                                        /*!< SCT EVSTATEMSK3: STATEMSKn14 Position */
#define SCT_EVSTATEMSK3_STATEMSKn14_Msk                       (0x01UL << SCT_EVSTATEMSK3_STATEMSKn14_Pos)               /*!< SCT EVSTATEMSK3: STATEMSKn14 Mask   */
#define SCT_EVSTATEMSK3_STATEMSKn15_Pos                       15                                                        /*!< SCT EVSTATEMSK3: STATEMSKn15 Position */
#define SCT_EVSTATEMSK3_STATEMSKn15_Msk                       (0x01UL << SCT_EVSTATEMSK3_STATEMSKn15_Pos)               /*!< SCT EVSTATEMSK3: STATEMSKn15 Mask   */
#define SCT_EVSTATEMSK3_STATEMSKn16_Pos                       16                                                        /*!< SCT EVSTATEMSK3: STATEMSKn16 Position */
#define SCT_EVSTATEMSK3_STATEMSKn16_Msk                       (0x01UL << SCT_EVSTATEMSK3_STATEMSKn16_Pos)               /*!< SCT EVSTATEMSK3: STATEMSKn16 Mask   */
#define SCT_EVSTATEMSK3_STATEMSKn17_Pos                       17                                                        /*!< SCT EVSTATEMSK3: STATEMSKn17 Position */
#define SCT_EVSTATEMSK3_STATEMSKn17_Msk                       (0x01UL << SCT_EVSTATEMSK3_STATEMSKn17_Pos)               /*!< SCT EVSTATEMSK3: STATEMSKn17 Mask   */
#define SCT_EVSTATEMSK3_STATEMSKn18_Pos                       18                                                        /*!< SCT EVSTATEMSK3: STATEMSKn18 Position */
#define SCT_EVSTATEMSK3_STATEMSKn18_Msk                       (0x01UL << SCT_EVSTATEMSK3_STATEMSKn18_Pos)               /*!< SCT EVSTATEMSK3: STATEMSKn18 Mask   */
#define SCT_EVSTATEMSK3_STATEMSKn19_Pos                       19                                                        /*!< SCT EVSTATEMSK3: STATEMSKn19 Position */
#define SCT_EVSTATEMSK3_STATEMSKn19_Msk                       (0x01UL << SCT_EVSTATEMSK3_STATEMSKn19_Pos)               /*!< SCT EVSTATEMSK3: STATEMSKn19 Mask   */
#define SCT_EVSTATEMSK3_STATEMSKn20_Pos                       20                                                        /*!< SCT EVSTATEMSK3: STATEMSKn20 Position */
#define SCT_EVSTATEMSK3_STATEMSKn20_Msk                       (0x01UL << SCT_EVSTATEMSK3_STATEMSKn20_Pos)               /*!< SCT EVSTATEMSK3: STATEMSKn20 Mask   */
#define SCT_EVSTATEMSK3_STATEMSKn21_Pos                       21                                                        /*!< SCT EVSTATEMSK3: STATEMSKn21 Position */
#define SCT_EVSTATEMSK3_STATEMSKn21_Msk                       (0x01UL << SCT_EVSTATEMSK3_STATEMSKn21_Pos)               /*!< SCT EVSTATEMSK3: STATEMSKn21 Mask   */
#define SCT_EVSTATEMSK3_STATEMSKn22_Pos                       22                                                        /*!< SCT EVSTATEMSK3: STATEMSKn22 Position */
#define SCT_EVSTATEMSK3_STATEMSKn22_Msk                       (0x01UL << SCT_EVSTATEMSK3_STATEMSKn22_Pos)               /*!< SCT EVSTATEMSK3: STATEMSKn22 Mask   */
#define SCT_EVSTATEMSK3_STATEMSKn23_Pos                       23                                                        /*!< SCT EVSTATEMSK3: STATEMSKn23 Position */
#define SCT_EVSTATEMSK3_STATEMSKn23_Msk                       (0x01UL << SCT_EVSTATEMSK3_STATEMSKn23_Pos)               /*!< SCT EVSTATEMSK3: STATEMSKn23 Mask   */
#define SCT_EVSTATEMSK3_STATEMSKn24_Pos                       24                                                        /*!< SCT EVSTATEMSK3: STATEMSKn24 Position */
#define SCT_EVSTATEMSK3_STATEMSKn24_Msk                       (0x01UL << SCT_EVSTATEMSK3_STATEMSKn24_Pos)               /*!< SCT EVSTATEMSK3: STATEMSKn24 Mask   */
#define SCT_EVSTATEMSK3_STATEMSKn25_Pos                       25                                                        /*!< SCT EVSTATEMSK3: STATEMSKn25 Position */
#define SCT_EVSTATEMSK3_STATEMSKn25_Msk                       (0x01UL << SCT_EVSTATEMSK3_STATEMSKn25_Pos)               /*!< SCT EVSTATEMSK3: STATEMSKn25 Mask   */
#define SCT_EVSTATEMSK3_STATEMSKn26_Pos                       26                                                        /*!< SCT EVSTATEMSK3: STATEMSKn26 Position */
#define SCT_EVSTATEMSK3_STATEMSKn26_Msk                       (0x01UL << SCT_EVSTATEMSK3_STATEMSKn26_Pos)               /*!< SCT EVSTATEMSK3: STATEMSKn26 Mask   */
#define SCT_EVSTATEMSK3_STATEMSKn27_Pos                       27                                                        /*!< SCT EVSTATEMSK3: STATEMSKn27 Position */
#define SCT_EVSTATEMSK3_STATEMSKn27_Msk                       (0x01UL << SCT_EVSTATEMSK3_STATEMSKn27_Pos)               /*!< SCT EVSTATEMSK3: STATEMSKn27 Mask   */
#define SCT_EVSTATEMSK3_STATEMSKn28_Pos                       28                                                        /*!< SCT EVSTATEMSK3: STATEMSKn28 Position */
#define SCT_EVSTATEMSK3_STATEMSKn28_Msk                       (0x01UL << SCT_EVSTATEMSK3_STATEMSKn28_Pos)               /*!< SCT EVSTATEMSK3: STATEMSKn28 Mask   */
#define SCT_EVSTATEMSK3_STATEMSKn29_Pos                       29                                                        /*!< SCT EVSTATEMSK3: STATEMSKn29 Position */
#define SCT_EVSTATEMSK3_STATEMSKn29_Msk                       (0x01UL << SCT_EVSTATEMSK3_STATEMSKn29_Pos)               /*!< SCT EVSTATEMSK3: STATEMSKn29 Mask   */
#define SCT_EVSTATEMSK3_STATEMSKn30_Pos                       30                                                        /*!< SCT EVSTATEMSK3: STATEMSKn30 Position */
#define SCT_EVSTATEMSK3_STATEMSKn30_Msk                       (0x01UL << SCT_EVSTATEMSK3_STATEMSKn30_Pos)               /*!< SCT EVSTATEMSK3: STATEMSKn30 Mask   */
#define SCT_EVSTATEMSK3_STATEMSKn31_Pos                       31                                                        /*!< SCT EVSTATEMSK3: STATEMSKn31 Position */
#define SCT_EVSTATEMSK3_STATEMSKn31_Msk                       (0x01UL << SCT_EVSTATEMSK3_STATEMSKn31_Pos)               /*!< SCT EVSTATEMSK3: STATEMSKn31 Mask   */

// ---------------------------------------  SCT_EVCTRL3  ------------------------------------------
#define SCT_EVCTRL3_MATCHSEL_Pos                              0                                                         /*!< SCT EVCTRL3: MATCHSEL Position      */
#define SCT_EVCTRL3_MATCHSEL_Msk                              (0x0fUL << SCT_EVCTRL3_MATCHSEL_Pos)                      /*!< SCT EVCTRL3: MATCHSEL Mask          */
#define SCT_EVCTRL3_HEVENT_Pos                                4                                                         /*!< SCT EVCTRL3: HEVENT Position        */
#define SCT_EVCTRL3_HEVENT_Msk                                (0x01UL << SCT_EVCTRL3_HEVENT_Pos)                        /*!< SCT EVCTRL3: HEVENT Mask            */
#define SCT_EVCTRL3_OUTSEL_Pos                                5                                                         /*!< SCT EVCTRL3: OUTSEL Position        */
#define SCT_EVCTRL3_OUTSEL_Msk                                (0x01UL << SCT_EVCTRL3_OUTSEL_Pos)                        /*!< SCT EVCTRL3: OUTSEL Mask            */
#define SCT_EVCTRL3_IOSEL_Pos                                 6                                                         /*!< SCT EVCTRL3: IOSEL Position         */
#define SCT_EVCTRL3_IOSEL_Msk                                 (0x0fUL << SCT_EVCTRL3_IOSEL_Pos)                         /*!< SCT EVCTRL3: IOSEL Mask             */
#define SCT_EVCTRL3_IOCOND_Pos                                10                                                        /*!< SCT EVCTRL3: IOCOND Position        */
#define SCT_EVCTRL3_IOCOND_Msk                                (0x03UL << SCT_EVCTRL3_IOCOND_Pos)                        /*!< SCT EVCTRL3: IOCOND Mask            */
#define SCT_EVCTRL3_COMBMODE_Pos                              12                                                        /*!< SCT EVCTRL3: COMBMODE Position      */
#define SCT_EVCTRL3_COMBMODE_Msk                              (0x03UL << SCT_EVCTRL3_COMBMODE_Pos)                      /*!< SCT EVCTRL3: COMBMODE Mask          */
#define SCT_EVCTRL3_STATELD_Pos                               14                                                        /*!< SCT EVCTRL3: STATELD Position       */
#define SCT_EVCTRL3_STATELD_Msk                               (0x01UL << SCT_EVCTRL3_STATELD_Pos)                       /*!< SCT EVCTRL3: STATELD Mask           */
#define SCT_EVCTRL3_STATEV_Pos                                15                                                        /*!< SCT EVCTRL3: STATEV Position        */
#define SCT_EVCTRL3_STATEV_Msk                                (0x1fUL << SCT_EVCTRL3_STATEV_Pos)                        /*!< SCT EVCTRL3: STATEV Mask            */

// -------------------------------------  SCT_EVSTATEMSK4  ----------------------------------------
#define SCT_EVSTATEMSK4_STATEMSKn0_Pos                        0                                                         /*!< SCT EVSTATEMSK4: STATEMSKn0 Position */
#define SCT_EVSTATEMSK4_STATEMSKn0_Msk                        (0x01UL << SCT_EVSTATEMSK4_STATEMSKn0_Pos)                /*!< SCT EVSTATEMSK4: STATEMSKn0 Mask    */
#define SCT_EVSTATEMSK4_STATEMSKn1_Pos                        1                                                         /*!< SCT EVSTATEMSK4: STATEMSKn1 Position */
#define SCT_EVSTATEMSK4_STATEMSKn1_Msk                        (0x01UL << SCT_EVSTATEMSK4_STATEMSKn1_Pos)                /*!< SCT EVSTATEMSK4: STATEMSKn1 Mask    */
#define SCT_EVSTATEMSK4_STATEMSKn2_Pos                        2                                                         /*!< SCT EVSTATEMSK4: STATEMSKn2 Position */
#define SCT_EVSTATEMSK4_STATEMSKn2_Msk                        (0x01UL << SCT_EVSTATEMSK4_STATEMSKn2_Pos)                /*!< SCT EVSTATEMSK4: STATEMSKn2 Mask    */
#define SCT_EVSTATEMSK4_STATEMSKn3_Pos                        3                                                         /*!< SCT EVSTATEMSK4: STATEMSKn3 Position */
#define SCT_EVSTATEMSK4_STATEMSKn3_Msk                        (0x01UL << SCT_EVSTATEMSK4_STATEMSKn3_Pos)                /*!< SCT EVSTATEMSK4: STATEMSKn3 Mask    */
#define SCT_EVSTATEMSK4_STATEMSKn4_Pos                        4                                                         /*!< SCT EVSTATEMSK4: STATEMSKn4 Position */
#define SCT_EVSTATEMSK4_STATEMSKn4_Msk                        (0x01UL << SCT_EVSTATEMSK4_STATEMSKn4_Pos)                /*!< SCT EVSTATEMSK4: STATEMSKn4 Mask    */
#define SCT_EVSTATEMSK4_STATEMSKn5_Pos                        5                                                         /*!< SCT EVSTATEMSK4: STATEMSKn5 Position */
#define SCT_EVSTATEMSK4_STATEMSKn5_Msk                        (0x01UL << SCT_EVSTATEMSK4_STATEMSKn5_Pos)                /*!< SCT EVSTATEMSK4: STATEMSKn5 Mask    */
#define SCT_EVSTATEMSK4_STATEMSKn6_Pos                        6                                                         /*!< SCT EVSTATEMSK4: STATEMSKn6 Position */
#define SCT_EVSTATEMSK4_STATEMSKn6_Msk                        (0x01UL << SCT_EVSTATEMSK4_STATEMSKn6_Pos)                /*!< SCT EVSTATEMSK4: STATEMSKn6 Mask    */
#define SCT_EVSTATEMSK4_STATEMSKn7_Pos                        7                                                         /*!< SCT EVSTATEMSK4: STATEMSKn7 Position */
#define SCT_EVSTATEMSK4_STATEMSKn7_Msk                        (0x01UL << SCT_EVSTATEMSK4_STATEMSKn7_Pos)                /*!< SCT EVSTATEMSK4: STATEMSKn7 Mask    */
#define SCT_EVSTATEMSK4_STATEMSKn8_Pos                        8                                                         /*!< SCT EVSTATEMSK4: STATEMSKn8 Position */
#define SCT_EVSTATEMSK4_STATEMSKn8_Msk                        (0x01UL << SCT_EVSTATEMSK4_STATEMSKn8_Pos)                /*!< SCT EVSTATEMSK4: STATEMSKn8 Mask    */
#define SCT_EVSTATEMSK4_STATEMSKn9_Pos                        9                                                         /*!< SCT EVSTATEMSK4: STATEMSKn9 Position */
#define SCT_EVSTATEMSK4_STATEMSKn9_Msk                        (0x01UL << SCT_EVSTATEMSK4_STATEMSKn9_Pos)                /*!< SCT EVSTATEMSK4: STATEMSKn9 Mask    */
#define SCT_EVSTATEMSK4_STATEMSKn10_Pos                       10                                                        /*!< SCT EVSTATEMSK4: STATEMSKn10 Position */
#define SCT_EVSTATEMSK4_STATEMSKn10_Msk                       (0x01UL << SCT_EVSTATEMSK4_STATEMSKn10_Pos)               /*!< SCT EVSTATEMSK4: STATEMSKn10 Mask   */
#define SCT_EVSTATEMSK4_STATEMSKn11_Pos                       11                                                        /*!< SCT EVSTATEMSK4: STATEMSKn11 Position */
#define SCT_EVSTATEMSK4_STATEMSKn11_Msk                       (0x01UL << SCT_EVSTATEMSK4_STATEMSKn11_Pos)               /*!< SCT EVSTATEMSK4: STATEMSKn11 Mask   */
#define SCT_EVSTATEMSK4_STATEMSKn12_Pos                       12                                                        /*!< SCT EVSTATEMSK4: STATEMSKn12 Position */
#define SCT_EVSTATEMSK4_STATEMSKn12_Msk                       (0x01UL << SCT_EVSTATEMSK4_STATEMSKn12_Pos)               /*!< SCT EVSTATEMSK4: STATEMSKn12 Mask   */
#define SCT_EVSTATEMSK4_STATEMSKn13_Pos                       13                                                        /*!< SCT EVSTATEMSK4: STATEMSKn13 Position */
#define SCT_EVSTATEMSK4_STATEMSKn13_Msk                       (0x01UL << SCT_EVSTATEMSK4_STATEMSKn13_Pos)               /*!< SCT EVSTATEMSK4: STATEMSKn13 Mask   */
#define SCT_EVSTATEMSK4_STATEMSKn14_Pos                       14                                                        /*!< SCT EVSTATEMSK4: STATEMSKn14 Position */
#define SCT_EVSTATEMSK4_STATEMSKn14_Msk                       (0x01UL << SCT_EVSTATEMSK4_STATEMSKn14_Pos)               /*!< SCT EVSTATEMSK4: STATEMSKn14 Mask   */
#define SCT_EVSTATEMSK4_STATEMSKn15_Pos                       15                                                        /*!< SCT EVSTATEMSK4: STATEMSKn15 Position */
#define SCT_EVSTATEMSK4_STATEMSKn15_Msk                       (0x01UL << SCT_EVSTATEMSK4_STATEMSKn15_Pos)               /*!< SCT EVSTATEMSK4: STATEMSKn15 Mask   */
#define SCT_EVSTATEMSK4_STATEMSKn16_Pos                       16                                                        /*!< SCT EVSTATEMSK4: STATEMSKn16 Position */
#define SCT_EVSTATEMSK4_STATEMSKn16_Msk                       (0x01UL << SCT_EVSTATEMSK4_STATEMSKn16_Pos)               /*!< SCT EVSTATEMSK4: STATEMSKn16 Mask   */
#define SCT_EVSTATEMSK4_STATEMSKn17_Pos                       17                                                        /*!< SCT EVSTATEMSK4: STATEMSKn17 Position */
#define SCT_EVSTATEMSK4_STATEMSKn17_Msk                       (0x01UL << SCT_EVSTATEMSK4_STATEMSKn17_Pos)               /*!< SCT EVSTATEMSK4: STATEMSKn17 Mask   */
#define SCT_EVSTATEMSK4_STATEMSKn18_Pos                       18                                                        /*!< SCT EVSTATEMSK4: STATEMSKn18 Position */
#define SCT_EVSTATEMSK4_STATEMSKn18_Msk                       (0x01UL << SCT_EVSTATEMSK4_STATEMSKn18_Pos)               /*!< SCT EVSTATEMSK4: STATEMSKn18 Mask   */
#define SCT_EVSTATEMSK4_STATEMSKn19_Pos                       19                                                        /*!< SCT EVSTATEMSK4: STATEMSKn19 Position */
#define SCT_EVSTATEMSK4_STATEMSKn19_Msk                       (0x01UL << SCT_EVSTATEMSK4_STATEMSKn19_Pos)               /*!< SCT EVSTATEMSK4: STATEMSKn19 Mask   */
#define SCT_EVSTATEMSK4_STATEMSKn20_Pos                       20                                                        /*!< SCT EVSTATEMSK4: STATEMSKn20 Position */
#define SCT_EVSTATEMSK4_STATEMSKn20_Msk                       (0x01UL << SCT_EVSTATEMSK4_STATEMSKn20_Pos)               /*!< SCT EVSTATEMSK4: STATEMSKn20 Mask   */
#define SCT_EVSTATEMSK4_STATEMSKn21_Pos                       21                                                        /*!< SCT EVSTATEMSK4: STATEMSKn21 Position */
#define SCT_EVSTATEMSK4_STATEMSKn21_Msk                       (0x01UL << SCT_EVSTATEMSK4_STATEMSKn21_Pos)               /*!< SCT EVSTATEMSK4: STATEMSKn21 Mask   */
#define SCT_EVSTATEMSK4_STATEMSKn22_Pos                       22                                                        /*!< SCT EVSTATEMSK4: STATEMSKn22 Position */
#define SCT_EVSTATEMSK4_STATEMSKn22_Msk                       (0x01UL << SCT_EVSTATEMSK4_STATEMSKn22_Pos)               /*!< SCT EVSTATEMSK4: STATEMSKn22 Mask   */
#define SCT_EVSTATEMSK4_STATEMSKn23_Pos                       23                                                        /*!< SCT EVSTATEMSK4: STATEMSKn23 Position */
#define SCT_EVSTATEMSK4_STATEMSKn23_Msk                       (0x01UL << SCT_EVSTATEMSK4_STATEMSKn23_Pos)               /*!< SCT EVSTATEMSK4: STATEMSKn23 Mask   */
#define SCT_EVSTATEMSK4_STATEMSKn24_Pos                       24                                                        /*!< SCT EVSTATEMSK4: STATEMSKn24 Position */
#define SCT_EVSTATEMSK4_STATEMSKn24_Msk                       (0x01UL << SCT_EVSTATEMSK4_STATEMSKn24_Pos)               /*!< SCT EVSTATEMSK4: STATEMSKn24 Mask   */
#define SCT_EVSTATEMSK4_STATEMSKn25_Pos                       25                                                        /*!< SCT EVSTATEMSK4: STATEMSKn25 Position */
#define SCT_EVSTATEMSK4_STATEMSKn25_Msk                       (0x01UL << SCT_EVSTATEMSK4_STATEMSKn25_Pos)               /*!< SCT EVSTATEMSK4: STATEMSKn25 Mask   */
#define SCT_EVSTATEMSK4_STATEMSKn26_Pos                       26                                                        /*!< SCT EVSTATEMSK4: STATEMSKn26 Position */
#define SCT_EVSTATEMSK4_STATEMSKn26_Msk                       (0x01UL << SCT_EVSTATEMSK4_STATEMSKn26_Pos)               /*!< SCT EVSTATEMSK4: STATEMSKn26 Mask   */
#define SCT_EVSTATEMSK4_STATEMSKn27_Pos                       27                                                        /*!< SCT EVSTATEMSK4: STATEMSKn27 Position */
#define SCT_EVSTATEMSK4_STATEMSKn27_Msk                       (0x01UL << SCT_EVSTATEMSK4_STATEMSKn27_Pos)               /*!< SCT EVSTATEMSK4: STATEMSKn27 Mask   */
#define SCT_EVSTATEMSK4_STATEMSKn28_Pos                       28                                                        /*!< SCT EVSTATEMSK4: STATEMSKn28 Position */
#define SCT_EVSTATEMSK4_STATEMSKn28_Msk                       (0x01UL << SCT_EVSTATEMSK4_STATEMSKn28_Pos)               /*!< SCT EVSTATEMSK4: STATEMSKn28 Mask   */
#define SCT_EVSTATEMSK4_STATEMSKn29_Pos                       29                                                        /*!< SCT EVSTATEMSK4: STATEMSKn29 Position */
#define SCT_EVSTATEMSK4_STATEMSKn29_Msk                       (0x01UL << SCT_EVSTATEMSK4_STATEMSKn29_Pos)               /*!< SCT EVSTATEMSK4: STATEMSKn29 Mask   */
#define SCT_EVSTATEMSK4_STATEMSKn30_Pos                       30                                                        /*!< SCT EVSTATEMSK4: STATEMSKn30 Position */
#define SCT_EVSTATEMSK4_STATEMSKn30_Msk                       (0x01UL << SCT_EVSTATEMSK4_STATEMSKn30_Pos)               /*!< SCT EVSTATEMSK4: STATEMSKn30 Mask   */
#define SCT_EVSTATEMSK4_STATEMSKn31_Pos                       31                                                        /*!< SCT EVSTATEMSK4: STATEMSKn31 Position */
#define SCT_EVSTATEMSK4_STATEMSKn31_Msk                       (0x01UL << SCT_EVSTATEMSK4_STATEMSKn31_Pos)               /*!< SCT EVSTATEMSK4: STATEMSKn31 Mask   */

// ---------------------------------------  SCT_EVCTRL4  ------------------------------------------
#define SCT_EVCTRL4_MATCHSEL_Pos                              0                                                         /*!< SCT EVCTRL4: MATCHSEL Position      */
#define SCT_EVCTRL4_MATCHSEL_Msk                              (0x0fUL << SCT_EVCTRL4_MATCHSEL_Pos)                      /*!< SCT EVCTRL4: MATCHSEL Mask          */
#define SCT_EVCTRL4_HEVENT_Pos                                4                                                         /*!< SCT EVCTRL4: HEVENT Position        */
#define SCT_EVCTRL4_HEVENT_Msk                                (0x01UL << SCT_EVCTRL4_HEVENT_Pos)                        /*!< SCT EVCTRL4: HEVENT Mask            */
#define SCT_EVCTRL4_OUTSEL_Pos                                5                                                         /*!< SCT EVCTRL4: OUTSEL Position        */
#define SCT_EVCTRL4_OUTSEL_Msk                                (0x01UL << SCT_EVCTRL4_OUTSEL_Pos)                        /*!< SCT EVCTRL4: OUTSEL Mask            */
#define SCT_EVCTRL4_IOSEL_Pos                                 6                                                         /*!< SCT EVCTRL4: IOSEL Position         */
#define SCT_EVCTRL4_IOSEL_Msk                                 (0x0fUL << SCT_EVCTRL4_IOSEL_Pos)                         /*!< SCT EVCTRL4: IOSEL Mask             */
#define SCT_EVCTRL4_IOCOND_Pos                                10                                                        /*!< SCT EVCTRL4: IOCOND Position        */
#define SCT_EVCTRL4_IOCOND_Msk                                (0x03UL << SCT_EVCTRL4_IOCOND_Pos)                        /*!< SCT EVCTRL4: IOCOND Mask            */
#define SCT_EVCTRL4_COMBMODE_Pos                              12                                                        /*!< SCT EVCTRL4: COMBMODE Position      */
#define SCT_EVCTRL4_COMBMODE_Msk                              (0x03UL << SCT_EVCTRL4_COMBMODE_Pos)                      /*!< SCT EVCTRL4: COMBMODE Mask          */
#define SCT_EVCTRL4_STATELD_Pos                               14                                                        /*!< SCT EVCTRL4: STATELD Position       */
#define SCT_EVCTRL4_STATELD_Msk                               (0x01UL << SCT_EVCTRL4_STATELD_Pos)                       /*!< SCT EVCTRL4: STATELD Mask           */
#define SCT_EVCTRL4_STATEV_Pos                                15                                                        /*!< SCT EVCTRL4: STATEV Position        */
#define SCT_EVCTRL4_STATEV_Msk                                (0x1fUL << SCT_EVCTRL4_STATEV_Pos)                        /*!< SCT EVCTRL4: STATEV Mask            */

// -------------------------------------  SCT_EVSTATEMSK5  ----------------------------------------
#define SCT_EVSTATEMSK5_STATEMSKn0_Pos                        0                                                         /*!< SCT EVSTATEMSK5: STATEMSKn0 Position */
#define SCT_EVSTATEMSK5_STATEMSKn0_Msk                        (0x01UL << SCT_EVSTATEMSK5_STATEMSKn0_Pos)                /*!< SCT EVSTATEMSK5: STATEMSKn0 Mask    */
#define SCT_EVSTATEMSK5_STATEMSKn1_Pos                        1                                                         /*!< SCT EVSTATEMSK5: STATEMSKn1 Position */
#define SCT_EVSTATEMSK5_STATEMSKn1_Msk                        (0x01UL << SCT_EVSTATEMSK5_STATEMSKn1_Pos)                /*!< SCT EVSTATEMSK5: STATEMSKn1 Mask    */
#define SCT_EVSTATEMSK5_STATEMSKn2_Pos                        2                                                         /*!< SCT EVSTATEMSK5: STATEMSKn2 Position */
#define SCT_EVSTATEMSK5_STATEMSKn2_Msk                        (0x01UL << SCT_EVSTATEMSK5_STATEMSKn2_Pos)                /*!< SCT EVSTATEMSK5: STATEMSKn2 Mask    */
#define SCT_EVSTATEMSK5_STATEMSKn3_Pos                        3                                                         /*!< SCT EVSTATEMSK5: STATEMSKn3 Position */
#define SCT_EVSTATEMSK5_STATEMSKn3_Msk                        (0x01UL << SCT_EVSTATEMSK5_STATEMSKn3_Pos)                /*!< SCT EVSTATEMSK5: STATEMSKn3 Mask    */
#define SCT_EVSTATEMSK5_STATEMSKn4_Pos                        4                                                         /*!< SCT EVSTATEMSK5: STATEMSKn4 Position */
#define SCT_EVSTATEMSK5_STATEMSKn4_Msk                        (0x01UL << SCT_EVSTATEMSK5_STATEMSKn4_Pos)                /*!< SCT EVSTATEMSK5: STATEMSKn4 Mask    */
#define SCT_EVSTATEMSK5_STATEMSKn5_Pos                        5                                                         /*!< SCT EVSTATEMSK5: STATEMSKn5 Position */
#define SCT_EVSTATEMSK5_STATEMSKn5_Msk                        (0x01UL << SCT_EVSTATEMSK5_STATEMSKn5_Pos)                /*!< SCT EVSTATEMSK5: STATEMSKn5 Mask    */
#define SCT_EVSTATEMSK5_STATEMSKn6_Pos                        6                                                         /*!< SCT EVSTATEMSK5: STATEMSKn6 Position */
#define SCT_EVSTATEMSK5_STATEMSKn6_Msk                        (0x01UL << SCT_EVSTATEMSK5_STATEMSKn6_Pos)                /*!< SCT EVSTATEMSK5: STATEMSKn6 Mask    */
#define SCT_EVSTATEMSK5_STATEMSKn7_Pos                        7                                                         /*!< SCT EVSTATEMSK5: STATEMSKn7 Position */
#define SCT_EVSTATEMSK5_STATEMSKn7_Msk                        (0x01UL << SCT_EVSTATEMSK5_STATEMSKn7_Pos)                /*!< SCT EVSTATEMSK5: STATEMSKn7 Mask    */
#define SCT_EVSTATEMSK5_STATEMSKn8_Pos                        8                                                         /*!< SCT EVSTATEMSK5: STATEMSKn8 Position */
#define SCT_EVSTATEMSK5_STATEMSKn8_Msk                        (0x01UL << SCT_EVSTATEMSK5_STATEMSKn8_Pos)                /*!< SCT EVSTATEMSK5: STATEMSKn8 Mask    */
#define SCT_EVSTATEMSK5_STATEMSKn9_Pos                        9                                                         /*!< SCT EVSTATEMSK5: STATEMSKn9 Position */
#define SCT_EVSTATEMSK5_STATEMSKn9_Msk                        (0x01UL << SCT_EVSTATEMSK5_STATEMSKn9_Pos)                /*!< SCT EVSTATEMSK5: STATEMSKn9 Mask    */
#define SCT_EVSTATEMSK5_STATEMSKn10_Pos                       10                                                        /*!< SCT EVSTATEMSK5: STATEMSKn10 Position */
#define SCT_EVSTATEMSK5_STATEMSKn10_Msk                       (0x01UL << SCT_EVSTATEMSK5_STATEMSKn10_Pos)               /*!< SCT EVSTATEMSK5: STATEMSKn10 Mask   */
#define SCT_EVSTATEMSK5_STATEMSKn11_Pos                       11                                                        /*!< SCT EVSTATEMSK5: STATEMSKn11 Position */
#define SCT_EVSTATEMSK5_STATEMSKn11_Msk                       (0x01UL << SCT_EVSTATEMSK5_STATEMSKn11_Pos)               /*!< SCT EVSTATEMSK5: STATEMSKn11 Mask   */
#define SCT_EVSTATEMSK5_STATEMSKn12_Pos                       12                                                        /*!< SCT EVSTATEMSK5: STATEMSKn12 Position */
#define SCT_EVSTATEMSK5_STATEMSKn12_Msk                       (0x01UL << SCT_EVSTATEMSK5_STATEMSKn12_Pos)               /*!< SCT EVSTATEMSK5: STATEMSKn12 Mask   */
#define SCT_EVSTATEMSK5_STATEMSKn13_Pos                       13                                                        /*!< SCT EVSTATEMSK5: STATEMSKn13 Position */
#define SCT_EVSTATEMSK5_STATEMSKn13_Msk                       (0x01UL << SCT_EVSTATEMSK5_STATEMSKn13_Pos)               /*!< SCT EVSTATEMSK5: STATEMSKn13 Mask   */
#define SCT_EVSTATEMSK5_STATEMSKn14_Pos                       14                                                        /*!< SCT EVSTATEMSK5: STATEMSKn14 Position */
#define SCT_EVSTATEMSK5_STATEMSKn14_Msk                       (0x01UL << SCT_EVSTATEMSK5_STATEMSKn14_Pos)               /*!< SCT EVSTATEMSK5: STATEMSKn14 Mask   */
#define SCT_EVSTATEMSK5_STATEMSKn15_Pos                       15                                                        /*!< SCT EVSTATEMSK5: STATEMSKn15 Position */
#define SCT_EVSTATEMSK5_STATEMSKn15_Msk                       (0x01UL << SCT_EVSTATEMSK5_STATEMSKn15_Pos)               /*!< SCT EVSTATEMSK5: STATEMSKn15 Mask   */
#define SCT_EVSTATEMSK5_STATEMSKn16_Pos                       16                                                        /*!< SCT EVSTATEMSK5: STATEMSKn16 Position */
#define SCT_EVSTATEMSK5_STATEMSKn16_Msk                       (0x01UL << SCT_EVSTATEMSK5_STATEMSKn16_Pos)               /*!< SCT EVSTATEMSK5: STATEMSKn16 Mask   */
#define SCT_EVSTATEMSK5_STATEMSKn17_Pos                       17                                                        /*!< SCT EVSTATEMSK5: STATEMSKn17 Position */
#define SCT_EVSTATEMSK5_STATEMSKn17_Msk                       (0x01UL << SCT_EVSTATEMSK5_STATEMSKn17_Pos)               /*!< SCT EVSTATEMSK5: STATEMSKn17 Mask   */
#define SCT_EVSTATEMSK5_STATEMSKn18_Pos                       18                                                        /*!< SCT EVSTATEMSK5: STATEMSKn18 Position */
#define SCT_EVSTATEMSK5_STATEMSKn18_Msk                       (0x01UL << SCT_EVSTATEMSK5_STATEMSKn18_Pos)               /*!< SCT EVSTATEMSK5: STATEMSKn18 Mask   */
#define SCT_EVSTATEMSK5_STATEMSKn19_Pos                       19                                                        /*!< SCT EVSTATEMSK5: STATEMSKn19 Position */
#define SCT_EVSTATEMSK5_STATEMSKn19_Msk                       (0x01UL << SCT_EVSTATEMSK5_STATEMSKn19_Pos)               /*!< SCT EVSTATEMSK5: STATEMSKn19 Mask   */
#define SCT_EVSTATEMSK5_STATEMSKn20_Pos                       20                                                        /*!< SCT EVSTATEMSK5: STATEMSKn20 Position */
#define SCT_EVSTATEMSK5_STATEMSKn20_Msk                       (0x01UL << SCT_EVSTATEMSK5_STATEMSKn20_Pos)               /*!< SCT EVSTATEMSK5: STATEMSKn20 Mask   */
#define SCT_EVSTATEMSK5_STATEMSKn21_Pos                       21                                                        /*!< SCT EVSTATEMSK5: STATEMSKn21 Position */
#define SCT_EVSTATEMSK5_STATEMSKn21_Msk                       (0x01UL << SCT_EVSTATEMSK5_STATEMSKn21_Pos)               /*!< SCT EVSTATEMSK5: STATEMSKn21 Mask   */
#define SCT_EVSTATEMSK5_STATEMSKn22_Pos                       22                                                        /*!< SCT EVSTATEMSK5: STATEMSKn22 Position */
#define SCT_EVSTATEMSK5_STATEMSKn22_Msk                       (0x01UL << SCT_EVSTATEMSK5_STATEMSKn22_Pos)               /*!< SCT EVSTATEMSK5: STATEMSKn22 Mask   */
#define SCT_EVSTATEMSK5_STATEMSKn23_Pos                       23                                                        /*!< SCT EVSTATEMSK5: STATEMSKn23 Position */
#define SCT_EVSTATEMSK5_STATEMSKn23_Msk                       (0x01UL << SCT_EVSTATEMSK5_STATEMSKn23_Pos)               /*!< SCT EVSTATEMSK5: STATEMSKn23 Mask   */
#define SCT_EVSTATEMSK5_STATEMSKn24_Pos                       24                                                        /*!< SCT EVSTATEMSK5: STATEMSKn24 Position */
#define SCT_EVSTATEMSK5_STATEMSKn24_Msk                       (0x01UL << SCT_EVSTATEMSK5_STATEMSKn24_Pos)               /*!< SCT EVSTATEMSK5: STATEMSKn24 Mask   */
#define SCT_EVSTATEMSK5_STATEMSKn25_Pos                       25                                                        /*!< SCT EVSTATEMSK5: STATEMSKn25 Position */
#define SCT_EVSTATEMSK5_STATEMSKn25_Msk                       (0x01UL << SCT_EVSTATEMSK5_STATEMSKn25_Pos)               /*!< SCT EVSTATEMSK5: STATEMSKn25 Mask   */
#define SCT_EVSTATEMSK5_STATEMSKn26_Pos                       26                                                        /*!< SCT EVSTATEMSK5: STATEMSKn26 Position */
#define SCT_EVSTATEMSK5_STATEMSKn26_Msk                       (0x01UL << SCT_EVSTATEMSK5_STATEMSKn26_Pos)               /*!< SCT EVSTATEMSK5: STATEMSKn26 Mask   */
#define SCT_EVSTATEMSK5_STATEMSKn27_Pos                       27                                                        /*!< SCT EVSTATEMSK5: STATEMSKn27 Position */
#define SCT_EVSTATEMSK5_STATEMSKn27_Msk                       (0x01UL << SCT_EVSTATEMSK5_STATEMSKn27_Pos)               /*!< SCT EVSTATEMSK5: STATEMSKn27 Mask   */
#define SCT_EVSTATEMSK5_STATEMSKn28_Pos                       28                                                        /*!< SCT EVSTATEMSK5: STATEMSKn28 Position */
#define SCT_EVSTATEMSK5_STATEMSKn28_Msk                       (0x01UL << SCT_EVSTATEMSK5_STATEMSKn28_Pos)               /*!< SCT EVSTATEMSK5: STATEMSKn28 Mask   */
#define SCT_EVSTATEMSK5_STATEMSKn29_Pos                       29                                                        /*!< SCT EVSTATEMSK5: STATEMSKn29 Position */
#define SCT_EVSTATEMSK5_STATEMSKn29_Msk                       (0x01UL << SCT_EVSTATEMSK5_STATEMSKn29_Pos)               /*!< SCT EVSTATEMSK5: STATEMSKn29 Mask   */
#define SCT_EVSTATEMSK5_STATEMSKn30_Pos                       30                                                        /*!< SCT EVSTATEMSK5: STATEMSKn30 Position */
#define SCT_EVSTATEMSK5_STATEMSKn30_Msk                       (0x01UL << SCT_EVSTATEMSK5_STATEMSKn30_Pos)               /*!< SCT EVSTATEMSK5: STATEMSKn30 Mask   */
#define SCT_EVSTATEMSK5_STATEMSKn31_Pos                       31                                                        /*!< SCT EVSTATEMSK5: STATEMSKn31 Position */
#define SCT_EVSTATEMSK5_STATEMSKn31_Msk                       (0x01UL << SCT_EVSTATEMSK5_STATEMSKn31_Pos)               /*!< SCT EVSTATEMSK5: STATEMSKn31 Mask   */

// ---------------------------------------  SCT_EVCTRL5  ------------------------------------------
#define SCT_EVCTRL5_MATCHSEL_Pos                              0                                                         /*!< SCT EVCTRL5: MATCHSEL Position      */
#define SCT_EVCTRL5_MATCHSEL_Msk                              (0x0fUL << SCT_EVCTRL5_MATCHSEL_Pos)                      /*!< SCT EVCTRL5: MATCHSEL Mask          */
#define SCT_EVCTRL5_HEVENT_Pos                                4                                                         /*!< SCT EVCTRL5: HEVENT Position        */
#define SCT_EVCTRL5_HEVENT_Msk                                (0x01UL << SCT_EVCTRL5_HEVENT_Pos)                        /*!< SCT EVCTRL5: HEVENT Mask            */
#define SCT_EVCTRL5_OUTSEL_Pos                                5                                                         /*!< SCT EVCTRL5: OUTSEL Position        */
#define SCT_EVCTRL5_OUTSEL_Msk                                (0x01UL << SCT_EVCTRL5_OUTSEL_Pos)                        /*!< SCT EVCTRL5: OUTSEL Mask            */
#define SCT_EVCTRL5_IOSEL_Pos                                 6                                                         /*!< SCT EVCTRL5: IOSEL Position         */
#define SCT_EVCTRL5_IOSEL_Msk                                 (0x0fUL << SCT_EVCTRL5_IOSEL_Pos)                         /*!< SCT EVCTRL5: IOSEL Mask             */
#define SCT_EVCTRL5_IOCOND_Pos                                10                                                        /*!< SCT EVCTRL5: IOCOND Position        */
#define SCT_EVCTRL5_IOCOND_Msk                                (0x03UL << SCT_EVCTRL5_IOCOND_Pos)                        /*!< SCT EVCTRL5: IOCOND Mask            */
#define SCT_EVCTRL5_COMBMODE_Pos                              12                                                        /*!< SCT EVCTRL5: COMBMODE Position      */
#define SCT_EVCTRL5_COMBMODE_Msk                              (0x03UL << SCT_EVCTRL5_COMBMODE_Pos)                      /*!< SCT EVCTRL5: COMBMODE Mask          */
#define SCT_EVCTRL5_STATELD_Pos                               14                                                        /*!< SCT EVCTRL5: STATELD Position       */
#define SCT_EVCTRL5_STATELD_Msk                               (0x01UL << SCT_EVCTRL5_STATELD_Pos)                       /*!< SCT EVCTRL5: STATELD Mask           */
#define SCT_EVCTRL5_STATEV_Pos                                15                                                        /*!< SCT EVCTRL5: STATEV Position        */
#define SCT_EVCTRL5_STATEV_Msk                                (0x1fUL << SCT_EVCTRL5_STATEV_Pos)                        /*!< SCT EVCTRL5: STATEV Mask            */

// -------------------------------------  SCT_EVSTATEMSK6  ----------------------------------------
#define SCT_EVSTATEMSK6_STATEMSKn0_Pos                        0                                                         /*!< SCT EVSTATEMSK6: STATEMSKn0 Position */
#define SCT_EVSTATEMSK6_STATEMSKn0_Msk                        (0x01UL << SCT_EVSTATEMSK6_STATEMSKn0_Pos)                /*!< SCT EVSTATEMSK6: STATEMSKn0 Mask    */
#define SCT_EVSTATEMSK6_STATEMSKn1_Pos                        1                                                         /*!< SCT EVSTATEMSK6: STATEMSKn1 Position */
#define SCT_EVSTATEMSK6_STATEMSKn1_Msk                        (0x01UL << SCT_EVSTATEMSK6_STATEMSKn1_Pos)                /*!< SCT EVSTATEMSK6: STATEMSKn1 Mask    */
#define SCT_EVSTATEMSK6_STATEMSKn2_Pos                        2                                                         /*!< SCT EVSTATEMSK6: STATEMSKn2 Position */
#define SCT_EVSTATEMSK6_STATEMSKn2_Msk                        (0x01UL << SCT_EVSTATEMSK6_STATEMSKn2_Pos)                /*!< SCT EVSTATEMSK6: STATEMSKn2 Mask    */
#define SCT_EVSTATEMSK6_STATEMSKn3_Pos                        3                                                         /*!< SCT EVSTATEMSK6: STATEMSKn3 Position */
#define SCT_EVSTATEMSK6_STATEMSKn3_Msk                        (0x01UL << SCT_EVSTATEMSK6_STATEMSKn3_Pos)                /*!< SCT EVSTATEMSK6: STATEMSKn3 Mask    */
#define SCT_EVSTATEMSK6_STATEMSKn4_Pos                        4                                                         /*!< SCT EVSTATEMSK6: STATEMSKn4 Position */
#define SCT_EVSTATEMSK6_STATEMSKn4_Msk                        (0x01UL << SCT_EVSTATEMSK6_STATEMSKn4_Pos)                /*!< SCT EVSTATEMSK6: STATEMSKn4 Mask    */
#define SCT_EVSTATEMSK6_STATEMSKn5_Pos                        5                                                         /*!< SCT EVSTATEMSK6: STATEMSKn5 Position */
#define SCT_EVSTATEMSK6_STATEMSKn5_Msk                        (0x01UL << SCT_EVSTATEMSK6_STATEMSKn5_Pos)                /*!< SCT EVSTATEMSK6: STATEMSKn5 Mask    */
#define SCT_EVSTATEMSK6_STATEMSKn6_Pos                        6                                                         /*!< SCT EVSTATEMSK6: STATEMSKn6 Position */
#define SCT_EVSTATEMSK6_STATEMSKn6_Msk                        (0x01UL << SCT_EVSTATEMSK6_STATEMSKn6_Pos)                /*!< SCT EVSTATEMSK6: STATEMSKn6 Mask    */
#define SCT_EVSTATEMSK6_STATEMSKn7_Pos                        7                                                         /*!< SCT EVSTATEMSK6: STATEMSKn7 Position */
#define SCT_EVSTATEMSK6_STATEMSKn7_Msk                        (0x01UL << SCT_EVSTATEMSK6_STATEMSKn7_Pos)                /*!< SCT EVSTATEMSK6: STATEMSKn7 Mask    */
#define SCT_EVSTATEMSK6_STATEMSKn8_Pos                        8                                                         /*!< SCT EVSTATEMSK6: STATEMSKn8 Position */
#define SCT_EVSTATEMSK6_STATEMSKn8_Msk                        (0x01UL << SCT_EVSTATEMSK6_STATEMSKn8_Pos)                /*!< SCT EVSTATEMSK6: STATEMSKn8 Mask    */
#define SCT_EVSTATEMSK6_STATEMSKn9_Pos                        9                                                         /*!< SCT EVSTATEMSK6: STATEMSKn9 Position */
#define SCT_EVSTATEMSK6_STATEMSKn9_Msk                        (0x01UL << SCT_EVSTATEMSK6_STATEMSKn9_Pos)                /*!< SCT EVSTATEMSK6: STATEMSKn9 Mask    */
#define SCT_EVSTATEMSK6_STATEMSKn10_Pos                       10                                                        /*!< SCT EVSTATEMSK6: STATEMSKn10 Position */
#define SCT_EVSTATEMSK6_STATEMSKn10_Msk                       (0x01UL << SCT_EVSTATEMSK6_STATEMSKn10_Pos)               /*!< SCT EVSTATEMSK6: STATEMSKn10 Mask   */
#define SCT_EVSTATEMSK6_STATEMSKn11_Pos                       11                                                        /*!< SCT EVSTATEMSK6: STATEMSKn11 Position */
#define SCT_EVSTATEMSK6_STATEMSKn11_Msk                       (0x01UL << SCT_EVSTATEMSK6_STATEMSKn11_Pos)               /*!< SCT EVSTATEMSK6: STATEMSKn11 Mask   */
#define SCT_EVSTATEMSK6_STATEMSKn12_Pos                       12                                                        /*!< SCT EVSTATEMSK6: STATEMSKn12 Position */
#define SCT_EVSTATEMSK6_STATEMSKn12_Msk                       (0x01UL << SCT_EVSTATEMSK6_STATEMSKn12_Pos)               /*!< SCT EVSTATEMSK6: STATEMSKn12 Mask   */
#define SCT_EVSTATEMSK6_STATEMSKn13_Pos                       13                                                        /*!< SCT EVSTATEMSK6: STATEMSKn13 Position */
#define SCT_EVSTATEMSK6_STATEMSKn13_Msk                       (0x01UL << SCT_EVSTATEMSK6_STATEMSKn13_Pos)               /*!< SCT EVSTATEMSK6: STATEMSKn13 Mask   */
#define SCT_EVSTATEMSK6_STATEMSKn14_Pos                       14                                                        /*!< SCT EVSTATEMSK6: STATEMSKn14 Position */
#define SCT_EVSTATEMSK6_STATEMSKn14_Msk                       (0x01UL << SCT_EVSTATEMSK6_STATEMSKn14_Pos)               /*!< SCT EVSTATEMSK6: STATEMSKn14 Mask   */
#define SCT_EVSTATEMSK6_STATEMSKn15_Pos                       15                                                        /*!< SCT EVSTATEMSK6: STATEMSKn15 Position */
#define SCT_EVSTATEMSK6_STATEMSKn15_Msk                       (0x01UL << SCT_EVSTATEMSK6_STATEMSKn15_Pos)               /*!< SCT EVSTATEMSK6: STATEMSKn15 Mask   */
#define SCT_EVSTATEMSK6_STATEMSKn16_Pos                       16                                                        /*!< SCT EVSTATEMSK6: STATEMSKn16 Position */
#define SCT_EVSTATEMSK6_STATEMSKn16_Msk                       (0x01UL << SCT_EVSTATEMSK6_STATEMSKn16_Pos)               /*!< SCT EVSTATEMSK6: STATEMSKn16 Mask   */
#define SCT_EVSTATEMSK6_STATEMSKn17_Pos                       17                                                        /*!< SCT EVSTATEMSK6: STATEMSKn17 Position */
#define SCT_EVSTATEMSK6_STATEMSKn17_Msk                       (0x01UL << SCT_EVSTATEMSK6_STATEMSKn17_Pos)               /*!< SCT EVSTATEMSK6: STATEMSKn17 Mask   */
#define SCT_EVSTATEMSK6_STATEMSKn18_Pos                       18                                                        /*!< SCT EVSTATEMSK6: STATEMSKn18 Position */
#define SCT_EVSTATEMSK6_STATEMSKn18_Msk                       (0x01UL << SCT_EVSTATEMSK6_STATEMSKn18_Pos)               /*!< SCT EVSTATEMSK6: STATEMSKn18 Mask   */
#define SCT_EVSTATEMSK6_STATEMSKn19_Pos                       19                                                        /*!< SCT EVSTATEMSK6: STATEMSKn19 Position */
#define SCT_EVSTATEMSK6_STATEMSKn19_Msk                       (0x01UL << SCT_EVSTATEMSK6_STATEMSKn19_Pos)               /*!< SCT EVSTATEMSK6: STATEMSKn19 Mask   */
#define SCT_EVSTATEMSK6_STATEMSKn20_Pos                       20                                                        /*!< SCT EVSTATEMSK6: STATEMSKn20 Position */
#define SCT_EVSTATEMSK6_STATEMSKn20_Msk                       (0x01UL << SCT_EVSTATEMSK6_STATEMSKn20_Pos)               /*!< SCT EVSTATEMSK6: STATEMSKn20 Mask   */
#define SCT_EVSTATEMSK6_STATEMSKn21_Pos                       21                                                        /*!< SCT EVSTATEMSK6: STATEMSKn21 Position */
#define SCT_EVSTATEMSK6_STATEMSKn21_Msk                       (0x01UL << SCT_EVSTATEMSK6_STATEMSKn21_Pos)               /*!< SCT EVSTATEMSK6: STATEMSKn21 Mask   */
#define SCT_EVSTATEMSK6_STATEMSKn22_Pos                       22                                                        /*!< SCT EVSTATEMSK6: STATEMSKn22 Position */
#define SCT_EVSTATEMSK6_STATEMSKn22_Msk                       (0x01UL << SCT_EVSTATEMSK6_STATEMSKn22_Pos)               /*!< SCT EVSTATEMSK6: STATEMSKn22 Mask   */
#define SCT_EVSTATEMSK6_STATEMSKn23_Pos                       23                                                        /*!< SCT EVSTATEMSK6: STATEMSKn23 Position */
#define SCT_EVSTATEMSK6_STATEMSKn23_Msk                       (0x01UL << SCT_EVSTATEMSK6_STATEMSKn23_Pos)               /*!< SCT EVSTATEMSK6: STATEMSKn23 Mask   */
#define SCT_EVSTATEMSK6_STATEMSKn24_Pos                       24                                                        /*!< SCT EVSTATEMSK6: STATEMSKn24 Position */
#define SCT_EVSTATEMSK6_STATEMSKn24_Msk                       (0x01UL << SCT_EVSTATEMSK6_STATEMSKn24_Pos)               /*!< SCT EVSTATEMSK6: STATEMSKn24 Mask   */
#define SCT_EVSTATEMSK6_STATEMSKn25_Pos                       25                                                        /*!< SCT EVSTATEMSK6: STATEMSKn25 Position */
#define SCT_EVSTATEMSK6_STATEMSKn25_Msk                       (0x01UL << SCT_EVSTATEMSK6_STATEMSKn25_Pos)               /*!< SCT EVSTATEMSK6: STATEMSKn25 Mask   */
#define SCT_EVSTATEMSK6_STATEMSKn26_Pos                       26                                                        /*!< SCT EVSTATEMSK6: STATEMSKn26 Position */
#define SCT_EVSTATEMSK6_STATEMSKn26_Msk                       (0x01UL << SCT_EVSTATEMSK6_STATEMSKn26_Pos)               /*!< SCT EVSTATEMSK6: STATEMSKn26 Mask   */
#define SCT_EVSTATEMSK6_STATEMSKn27_Pos                       27                                                        /*!< SCT EVSTATEMSK6: STATEMSKn27 Position */
#define SCT_EVSTATEMSK6_STATEMSKn27_Msk                       (0x01UL << SCT_EVSTATEMSK6_STATEMSKn27_Pos)               /*!< SCT EVSTATEMSK6: STATEMSKn27 Mask   */
#define SCT_EVSTATEMSK6_STATEMSKn28_Pos                       28                                                        /*!< SCT EVSTATEMSK6: STATEMSKn28 Position */
#define SCT_EVSTATEMSK6_STATEMSKn28_Msk                       (0x01UL << SCT_EVSTATEMSK6_STATEMSKn28_Pos)               /*!< SCT EVSTATEMSK6: STATEMSKn28 Mask   */
#define SCT_EVSTATEMSK6_STATEMSKn29_Pos                       29                                                        /*!< SCT EVSTATEMSK6: STATEMSKn29 Position */
#define SCT_EVSTATEMSK6_STATEMSKn29_Msk                       (0x01UL << SCT_EVSTATEMSK6_STATEMSKn29_Pos)               /*!< SCT EVSTATEMSK6: STATEMSKn29 Mask   */
#define SCT_EVSTATEMSK6_STATEMSKn30_Pos                       30                                                        /*!< SCT EVSTATEMSK6: STATEMSKn30 Position */
#define SCT_EVSTATEMSK6_STATEMSKn30_Msk                       (0x01UL << SCT_EVSTATEMSK6_STATEMSKn30_Pos)               /*!< SCT EVSTATEMSK6: STATEMSKn30 Mask   */
#define SCT_EVSTATEMSK6_STATEMSKn31_Pos                       31                                                        /*!< SCT EVSTATEMSK6: STATEMSKn31 Position */
#define SCT_EVSTATEMSK6_STATEMSKn31_Msk                       (0x01UL << SCT_EVSTATEMSK6_STATEMSKn31_Pos)               /*!< SCT EVSTATEMSK6: STATEMSKn31 Mask   */

// ---------------------------------------  SCT_EVCTRL6  ------------------------------------------
#define SCT_EVCTRL6_MATCHSEL_Pos                              0                                                         /*!< SCT EVCTRL6: MATCHSEL Position      */
#define SCT_EVCTRL6_MATCHSEL_Msk                              (0x0fUL << SCT_EVCTRL6_MATCHSEL_Pos)                      /*!< SCT EVCTRL6: MATCHSEL Mask          */
#define SCT_EVCTRL6_HEVENT_Pos                                4                                                         /*!< SCT EVCTRL6: HEVENT Position        */
#define SCT_EVCTRL6_HEVENT_Msk                                (0x01UL << SCT_EVCTRL6_HEVENT_Pos)                        /*!< SCT EVCTRL6: HEVENT Mask            */
#define SCT_EVCTRL6_OUTSEL_Pos                                5                                                         /*!< SCT EVCTRL6: OUTSEL Position        */
#define SCT_EVCTRL6_OUTSEL_Msk                                (0x01UL << SCT_EVCTRL6_OUTSEL_Pos)                        /*!< SCT EVCTRL6: OUTSEL Mask            */
#define SCT_EVCTRL6_IOSEL_Pos                                 6                                                         /*!< SCT EVCTRL6: IOSEL Position         */
#define SCT_EVCTRL6_IOSEL_Msk                                 (0x0fUL << SCT_EVCTRL6_IOSEL_Pos)                         /*!< SCT EVCTRL6: IOSEL Mask             */
#define SCT_EVCTRL6_IOCOND_Pos                                10                                                        /*!< SCT EVCTRL6: IOCOND Position        */
#define SCT_EVCTRL6_IOCOND_Msk                                (0x03UL << SCT_EVCTRL6_IOCOND_Pos)                        /*!< SCT EVCTRL6: IOCOND Mask            */
#define SCT_EVCTRL6_COMBMODE_Pos                              12                                                        /*!< SCT EVCTRL6: COMBMODE Position      */
#define SCT_EVCTRL6_COMBMODE_Msk                              (0x03UL << SCT_EVCTRL6_COMBMODE_Pos)                      /*!< SCT EVCTRL6: COMBMODE Mask          */
#define SCT_EVCTRL6_STATELD_Pos                               14                                                        /*!< SCT EVCTRL6: STATELD Position       */
#define SCT_EVCTRL6_STATELD_Msk                               (0x01UL << SCT_EVCTRL6_STATELD_Pos)                       /*!< SCT EVCTRL6: STATELD Mask           */
#define SCT_EVCTRL6_STATEV_Pos                                15                                                        /*!< SCT EVCTRL6: STATEV Position        */
#define SCT_EVCTRL6_STATEV_Msk                                (0x1fUL << SCT_EVCTRL6_STATEV_Pos)                        /*!< SCT EVCTRL6: STATEV Mask            */

// -------------------------------------  SCT_EVSTATEMSK7  ----------------------------------------
#define SCT_EVSTATEMSK7_STATEMSKn0_Pos                        0                                                         /*!< SCT EVSTATEMSK7: STATEMSKn0 Position */
#define SCT_EVSTATEMSK7_STATEMSKn0_Msk                        (0x01UL << SCT_EVSTATEMSK7_STATEMSKn0_Pos)                /*!< SCT EVSTATEMSK7: STATEMSKn0 Mask    */
#define SCT_EVSTATEMSK7_STATEMSKn1_Pos                        1                                                         /*!< SCT EVSTATEMSK7: STATEMSKn1 Position */
#define SCT_EVSTATEMSK7_STATEMSKn1_Msk                        (0x01UL << SCT_EVSTATEMSK7_STATEMSKn1_Pos)                /*!< SCT EVSTATEMSK7: STATEMSKn1 Mask    */
#define SCT_EVSTATEMSK7_STATEMSKn2_Pos                        2                                                         /*!< SCT EVSTATEMSK7: STATEMSKn2 Position */
#define SCT_EVSTATEMSK7_STATEMSKn2_Msk                        (0x01UL << SCT_EVSTATEMSK7_STATEMSKn2_Pos)                /*!< SCT EVSTATEMSK7: STATEMSKn2 Mask    */
#define SCT_EVSTATEMSK7_STATEMSKn3_Pos                        3                                                         /*!< SCT EVSTATEMSK7: STATEMSKn3 Position */
#define SCT_EVSTATEMSK7_STATEMSKn3_Msk                        (0x01UL << SCT_EVSTATEMSK7_STATEMSKn3_Pos)                /*!< SCT EVSTATEMSK7: STATEMSKn3 Mask    */
#define SCT_EVSTATEMSK7_STATEMSKn4_Pos                        4                                                         /*!< SCT EVSTATEMSK7: STATEMSKn4 Position */
#define SCT_EVSTATEMSK7_STATEMSKn4_Msk                        (0x01UL << SCT_EVSTATEMSK7_STATEMSKn4_Pos)                /*!< SCT EVSTATEMSK7: STATEMSKn4 Mask    */
#define SCT_EVSTATEMSK7_STATEMSKn5_Pos                        5                                                         /*!< SCT EVSTATEMSK7: STATEMSKn5 Position */
#define SCT_EVSTATEMSK7_STATEMSKn5_Msk                        (0x01UL << SCT_EVSTATEMSK7_STATEMSKn5_Pos)                /*!< SCT EVSTATEMSK7: STATEMSKn5 Mask    */
#define SCT_EVSTATEMSK7_STATEMSKn6_Pos                        6                                                         /*!< SCT EVSTATEMSK7: STATEMSKn6 Position */
#define SCT_EVSTATEMSK7_STATEMSKn6_Msk                        (0x01UL << SCT_EVSTATEMSK7_STATEMSKn6_Pos)                /*!< SCT EVSTATEMSK7: STATEMSKn6 Mask    */
#define SCT_EVSTATEMSK7_STATEMSKn7_Pos                        7                                                         /*!< SCT EVSTATEMSK7: STATEMSKn7 Position */
#define SCT_EVSTATEMSK7_STATEMSKn7_Msk                        (0x01UL << SCT_EVSTATEMSK7_STATEMSKn7_Pos)                /*!< SCT EVSTATEMSK7: STATEMSKn7 Mask    */
#define SCT_EVSTATEMSK7_STATEMSKn8_Pos                        8                                                         /*!< SCT EVSTATEMSK7: STATEMSKn8 Position */
#define SCT_EVSTATEMSK7_STATEMSKn8_Msk                        (0x01UL << SCT_EVSTATEMSK7_STATEMSKn8_Pos)                /*!< SCT EVSTATEMSK7: STATEMSKn8 Mask    */
#define SCT_EVSTATEMSK7_STATEMSKn9_Pos                        9                                                         /*!< SCT EVSTATEMSK7: STATEMSKn9 Position */
#define SCT_EVSTATEMSK7_STATEMSKn9_Msk                        (0x01UL << SCT_EVSTATEMSK7_STATEMSKn9_Pos)                /*!< SCT EVSTATEMSK7: STATEMSKn9 Mask    */
#define SCT_EVSTATEMSK7_STATEMSKn10_Pos                       10                                                        /*!< SCT EVSTATEMSK7: STATEMSKn10 Position */
#define SCT_EVSTATEMSK7_STATEMSKn10_Msk                       (0x01UL << SCT_EVSTATEMSK7_STATEMSKn10_Pos)               /*!< SCT EVSTATEMSK7: STATEMSKn10 Mask   */
#define SCT_EVSTATEMSK7_STATEMSKn11_Pos                       11                                                        /*!< SCT EVSTATEMSK7: STATEMSKn11 Position */
#define SCT_EVSTATEMSK7_STATEMSKn11_Msk                       (0x01UL << SCT_EVSTATEMSK7_STATEMSKn11_Pos)               /*!< SCT EVSTATEMSK7: STATEMSKn11 Mask   */
#define SCT_EVSTATEMSK7_STATEMSKn12_Pos                       12                                                        /*!< SCT EVSTATEMSK7: STATEMSKn12 Position */
#define SCT_EVSTATEMSK7_STATEMSKn12_Msk                       (0x01UL << SCT_EVSTATEMSK7_STATEMSKn12_Pos)               /*!< SCT EVSTATEMSK7: STATEMSKn12 Mask   */
#define SCT_EVSTATEMSK7_STATEMSKn13_Pos                       13                                                        /*!< SCT EVSTATEMSK7: STATEMSKn13 Position */
#define SCT_EVSTATEMSK7_STATEMSKn13_Msk                       (0x01UL << SCT_EVSTATEMSK7_STATEMSKn13_Pos)               /*!< SCT EVSTATEMSK7: STATEMSKn13 Mask   */
#define SCT_EVSTATEMSK7_STATEMSKn14_Pos                       14                                                        /*!< SCT EVSTATEMSK7: STATEMSKn14 Position */
#define SCT_EVSTATEMSK7_STATEMSKn14_Msk                       (0x01UL << SCT_EVSTATEMSK7_STATEMSKn14_Pos)               /*!< SCT EVSTATEMSK7: STATEMSKn14 Mask   */
#define SCT_EVSTATEMSK7_STATEMSKn15_Pos                       15                                                        /*!< SCT EVSTATEMSK7: STATEMSKn15 Position */
#define SCT_EVSTATEMSK7_STATEMSKn15_Msk                       (0x01UL << SCT_EVSTATEMSK7_STATEMSKn15_Pos)               /*!< SCT EVSTATEMSK7: STATEMSKn15 Mask   */
#define SCT_EVSTATEMSK7_STATEMSKn16_Pos                       16                                                        /*!< SCT EVSTATEMSK7: STATEMSKn16 Position */
#define SCT_EVSTATEMSK7_STATEMSKn16_Msk                       (0x01UL << SCT_EVSTATEMSK7_STATEMSKn16_Pos)               /*!< SCT EVSTATEMSK7: STATEMSKn16 Mask   */
#define SCT_EVSTATEMSK7_STATEMSKn17_Pos                       17                                                        /*!< SCT EVSTATEMSK7: STATEMSKn17 Position */
#define SCT_EVSTATEMSK7_STATEMSKn17_Msk                       (0x01UL << SCT_EVSTATEMSK7_STATEMSKn17_Pos)               /*!< SCT EVSTATEMSK7: STATEMSKn17 Mask   */
#define SCT_EVSTATEMSK7_STATEMSKn18_Pos                       18                                                        /*!< SCT EVSTATEMSK7: STATEMSKn18 Position */
#define SCT_EVSTATEMSK7_STATEMSKn18_Msk                       (0x01UL << SCT_EVSTATEMSK7_STATEMSKn18_Pos)               /*!< SCT EVSTATEMSK7: STATEMSKn18 Mask   */
#define SCT_EVSTATEMSK7_STATEMSKn19_Pos                       19                                                        /*!< SCT EVSTATEMSK7: STATEMSKn19 Position */
#define SCT_EVSTATEMSK7_STATEMSKn19_Msk                       (0x01UL << SCT_EVSTATEMSK7_STATEMSKn19_Pos)               /*!< SCT EVSTATEMSK7: STATEMSKn19 Mask   */
#define SCT_EVSTATEMSK7_STATEMSKn20_Pos                       20                                                        /*!< SCT EVSTATEMSK7: STATEMSKn20 Position */
#define SCT_EVSTATEMSK7_STATEMSKn20_Msk                       (0x01UL << SCT_EVSTATEMSK7_STATEMSKn20_Pos)               /*!< SCT EVSTATEMSK7: STATEMSKn20 Mask   */
#define SCT_EVSTATEMSK7_STATEMSKn21_Pos                       21                                                        /*!< SCT EVSTATEMSK7: STATEMSKn21 Position */
#define SCT_EVSTATEMSK7_STATEMSKn21_Msk                       (0x01UL << SCT_EVSTATEMSK7_STATEMSKn21_Pos)               /*!< SCT EVSTATEMSK7: STATEMSKn21 Mask   */
#define SCT_EVSTATEMSK7_STATEMSKn22_Pos                       22                                                        /*!< SCT EVSTATEMSK7: STATEMSKn22 Position */
#define SCT_EVSTATEMSK7_STATEMSKn22_Msk                       (0x01UL << SCT_EVSTATEMSK7_STATEMSKn22_Pos)               /*!< SCT EVSTATEMSK7: STATEMSKn22 Mask   */
#define SCT_EVSTATEMSK7_STATEMSKn23_Pos                       23                                                        /*!< SCT EVSTATEMSK7: STATEMSKn23 Position */
#define SCT_EVSTATEMSK7_STATEMSKn23_Msk                       (0x01UL << SCT_EVSTATEMSK7_STATEMSKn23_Pos)               /*!< SCT EVSTATEMSK7: STATEMSKn23 Mask   */
#define SCT_EVSTATEMSK7_STATEMSKn24_Pos                       24                                                        /*!< SCT EVSTATEMSK7: STATEMSKn24 Position */
#define SCT_EVSTATEMSK7_STATEMSKn24_Msk                       (0x01UL << SCT_EVSTATEMSK7_STATEMSKn24_Pos)               /*!< SCT EVSTATEMSK7: STATEMSKn24 Mask   */
#define SCT_EVSTATEMSK7_STATEMSKn25_Pos                       25                                                        /*!< SCT EVSTATEMSK7: STATEMSKn25 Position */
#define SCT_EVSTATEMSK7_STATEMSKn25_Msk                       (0x01UL << SCT_EVSTATEMSK7_STATEMSKn25_Pos)               /*!< SCT EVSTATEMSK7: STATEMSKn25 Mask   */
#define SCT_EVSTATEMSK7_STATEMSKn26_Pos                       26                                                        /*!< SCT EVSTATEMSK7: STATEMSKn26 Position */
#define SCT_EVSTATEMSK7_STATEMSKn26_Msk                       (0x01UL << SCT_EVSTATEMSK7_STATEMSKn26_Pos)               /*!< SCT EVSTATEMSK7: STATEMSKn26 Mask   */
#define SCT_EVSTATEMSK7_STATEMSKn27_Pos                       27                                                        /*!< SCT EVSTATEMSK7: STATEMSKn27 Position */
#define SCT_EVSTATEMSK7_STATEMSKn27_Msk                       (0x01UL << SCT_EVSTATEMSK7_STATEMSKn27_Pos)               /*!< SCT EVSTATEMSK7: STATEMSKn27 Mask   */
#define SCT_EVSTATEMSK7_STATEMSKn28_Pos                       28                                                        /*!< SCT EVSTATEMSK7: STATEMSKn28 Position */
#define SCT_EVSTATEMSK7_STATEMSKn28_Msk                       (0x01UL << SCT_EVSTATEMSK7_STATEMSKn28_Pos)               /*!< SCT EVSTATEMSK7: STATEMSKn28 Mask   */
#define SCT_EVSTATEMSK7_STATEMSKn29_Pos                       29                                                        /*!< SCT EVSTATEMSK7: STATEMSKn29 Position */
#define SCT_EVSTATEMSK7_STATEMSKn29_Msk                       (0x01UL << SCT_EVSTATEMSK7_STATEMSKn29_Pos)               /*!< SCT EVSTATEMSK7: STATEMSKn29 Mask   */
#define SCT_EVSTATEMSK7_STATEMSKn30_Pos                       30                                                        /*!< SCT EVSTATEMSK7: STATEMSKn30 Position */
#define SCT_EVSTATEMSK7_STATEMSKn30_Msk                       (0x01UL << SCT_EVSTATEMSK7_STATEMSKn30_Pos)               /*!< SCT EVSTATEMSK7: STATEMSKn30 Mask   */
#define SCT_EVSTATEMSK7_STATEMSKn31_Pos                       31                                                        /*!< SCT EVSTATEMSK7: STATEMSKn31 Position */
#define SCT_EVSTATEMSK7_STATEMSKn31_Msk                       (0x01UL << SCT_EVSTATEMSK7_STATEMSKn31_Pos)               /*!< SCT EVSTATEMSK7: STATEMSKn31 Mask   */

// ---------------------------------------  SCT_EVCTRL7  ------------------------------------------
#define SCT_EVCTRL7_MATCHSEL_Pos                              0                                                         /*!< SCT EVCTRL7: MATCHSEL Position      */
#define SCT_EVCTRL7_MATCHSEL_Msk                              (0x0fUL << SCT_EVCTRL7_MATCHSEL_Pos)                      /*!< SCT EVCTRL7: MATCHSEL Mask          */
#define SCT_EVCTRL7_HEVENT_Pos                                4                                                         /*!< SCT EVCTRL7: HEVENT Position        */
#define SCT_EVCTRL7_HEVENT_Msk                                (0x01UL << SCT_EVCTRL7_HEVENT_Pos)                        /*!< SCT EVCTRL7: HEVENT Mask            */
#define SCT_EVCTRL7_OUTSEL_Pos                                5                                                         /*!< SCT EVCTRL7: OUTSEL Position        */
#define SCT_EVCTRL7_OUTSEL_Msk                                (0x01UL << SCT_EVCTRL7_OUTSEL_Pos)                        /*!< SCT EVCTRL7: OUTSEL Mask            */
#define SCT_EVCTRL7_IOSEL_Pos                                 6                                                         /*!< SCT EVCTRL7: IOSEL Position         */
#define SCT_EVCTRL7_IOSEL_Msk                                 (0x0fUL << SCT_EVCTRL7_IOSEL_Pos)                         /*!< SCT EVCTRL7: IOSEL Mask             */
#define SCT_EVCTRL7_IOCOND_Pos                                10                                                        /*!< SCT EVCTRL7: IOCOND Position        */
#define SCT_EVCTRL7_IOCOND_Msk                                (0x03UL << SCT_EVCTRL7_IOCOND_Pos)                        /*!< SCT EVCTRL7: IOCOND Mask            */
#define SCT_EVCTRL7_COMBMODE_Pos                              12                                                        /*!< SCT EVCTRL7: COMBMODE Position      */
#define SCT_EVCTRL7_COMBMODE_Msk                              (0x03UL << SCT_EVCTRL7_COMBMODE_Pos)                      /*!< SCT EVCTRL7: COMBMODE Mask          */
#define SCT_EVCTRL7_STATELD_Pos                               14                                                        /*!< SCT EVCTRL7: STATELD Position       */
#define SCT_EVCTRL7_STATELD_Msk                               (0x01UL << SCT_EVCTRL7_STATELD_Pos)                       /*!< SCT EVCTRL7: STATELD Mask           */
#define SCT_EVCTRL7_STATEV_Pos                                15                                                        /*!< SCT EVCTRL7: STATEV Position        */
#define SCT_EVCTRL7_STATEV_Msk                                (0x1fUL << SCT_EVCTRL7_STATEV_Pos)                        /*!< SCT EVCTRL7: STATEV Mask            */

// -------------------------------------  SCT_EVSTATEMSK8  ----------------------------------------
#define SCT_EVSTATEMSK8_STATEMSKn0_Pos                        0                                                         /*!< SCT EVSTATEMSK8: STATEMSKn0 Position */
#define SCT_EVSTATEMSK8_STATEMSKn0_Msk                        (0x01UL << SCT_EVSTATEMSK8_STATEMSKn0_Pos)                /*!< SCT EVSTATEMSK8: STATEMSKn0 Mask    */
#define SCT_EVSTATEMSK8_STATEMSKn1_Pos                        1                                                         /*!< SCT EVSTATEMSK8: STATEMSKn1 Position */
#define SCT_EVSTATEMSK8_STATEMSKn1_Msk                        (0x01UL << SCT_EVSTATEMSK8_STATEMSKn1_Pos)                /*!< SCT EVSTATEMSK8: STATEMSKn1 Mask    */
#define SCT_EVSTATEMSK8_STATEMSKn2_Pos                        2                                                         /*!< SCT EVSTATEMSK8: STATEMSKn2 Position */
#define SCT_EVSTATEMSK8_STATEMSKn2_Msk                        (0x01UL << SCT_EVSTATEMSK8_STATEMSKn2_Pos)                /*!< SCT EVSTATEMSK8: STATEMSKn2 Mask    */
#define SCT_EVSTATEMSK8_STATEMSKn3_Pos                        3                                                         /*!< SCT EVSTATEMSK8: STATEMSKn3 Position */
#define SCT_EVSTATEMSK8_STATEMSKn3_Msk                        (0x01UL << SCT_EVSTATEMSK8_STATEMSKn3_Pos)                /*!< SCT EVSTATEMSK8: STATEMSKn3 Mask    */
#define SCT_EVSTATEMSK8_STATEMSKn4_Pos                        4                                                         /*!< SCT EVSTATEMSK8: STATEMSKn4 Position */
#define SCT_EVSTATEMSK8_STATEMSKn4_Msk                        (0x01UL << SCT_EVSTATEMSK8_STATEMSKn4_Pos)                /*!< SCT EVSTATEMSK8: STATEMSKn4 Mask    */
#define SCT_EVSTATEMSK8_STATEMSKn5_Pos                        5                                                         /*!< SCT EVSTATEMSK8: STATEMSKn5 Position */
#define SCT_EVSTATEMSK8_STATEMSKn5_Msk                        (0x01UL << SCT_EVSTATEMSK8_STATEMSKn5_Pos)                /*!< SCT EVSTATEMSK8: STATEMSKn5 Mask    */
#define SCT_EVSTATEMSK8_STATEMSKn6_Pos                        6                                                         /*!< SCT EVSTATEMSK8: STATEMSKn6 Position */
#define SCT_EVSTATEMSK8_STATEMSKn6_Msk                        (0x01UL << SCT_EVSTATEMSK8_STATEMSKn6_Pos)                /*!< SCT EVSTATEMSK8: STATEMSKn6 Mask    */
#define SCT_EVSTATEMSK8_STATEMSKn7_Pos                        7                                                         /*!< SCT EVSTATEMSK8: STATEMSKn7 Position */
#define SCT_EVSTATEMSK8_STATEMSKn7_Msk                        (0x01UL << SCT_EVSTATEMSK8_STATEMSKn7_Pos)                /*!< SCT EVSTATEMSK8: STATEMSKn7 Mask    */
#define SCT_EVSTATEMSK8_STATEMSKn8_Pos                        8                                                         /*!< SCT EVSTATEMSK8: STATEMSKn8 Position */
#define SCT_EVSTATEMSK8_STATEMSKn8_Msk                        (0x01UL << SCT_EVSTATEMSK8_STATEMSKn8_Pos)                /*!< SCT EVSTATEMSK8: STATEMSKn8 Mask    */
#define SCT_EVSTATEMSK8_STATEMSKn9_Pos                        9                                                         /*!< SCT EVSTATEMSK8: STATEMSKn9 Position */
#define SCT_EVSTATEMSK8_STATEMSKn9_Msk                        (0x01UL << SCT_EVSTATEMSK8_STATEMSKn9_Pos)                /*!< SCT EVSTATEMSK8: STATEMSKn9 Mask    */
#define SCT_EVSTATEMSK8_STATEMSKn10_Pos                       10                                                        /*!< SCT EVSTATEMSK8: STATEMSKn10 Position */
#define SCT_EVSTATEMSK8_STATEMSKn10_Msk                       (0x01UL << SCT_EVSTATEMSK8_STATEMSKn10_Pos)               /*!< SCT EVSTATEMSK8: STATEMSKn10 Mask   */
#define SCT_EVSTATEMSK8_STATEMSKn11_Pos                       11                                                        /*!< SCT EVSTATEMSK8: STATEMSKn11 Position */
#define SCT_EVSTATEMSK8_STATEMSKn11_Msk                       (0x01UL << SCT_EVSTATEMSK8_STATEMSKn11_Pos)               /*!< SCT EVSTATEMSK8: STATEMSKn11 Mask   */
#define SCT_EVSTATEMSK8_STATEMSKn12_Pos                       12                                                        /*!< SCT EVSTATEMSK8: STATEMSKn12 Position */
#define SCT_EVSTATEMSK8_STATEMSKn12_Msk                       (0x01UL << SCT_EVSTATEMSK8_STATEMSKn12_Pos)               /*!< SCT EVSTATEMSK8: STATEMSKn12 Mask   */
#define SCT_EVSTATEMSK8_STATEMSKn13_Pos                       13                                                        /*!< SCT EVSTATEMSK8: STATEMSKn13 Position */
#define SCT_EVSTATEMSK8_STATEMSKn13_Msk                       (0x01UL << SCT_EVSTATEMSK8_STATEMSKn13_Pos)               /*!< SCT EVSTATEMSK8: STATEMSKn13 Mask   */
#define SCT_EVSTATEMSK8_STATEMSKn14_Pos                       14                                                        /*!< SCT EVSTATEMSK8: STATEMSKn14 Position */
#define SCT_EVSTATEMSK8_STATEMSKn14_Msk                       (0x01UL << SCT_EVSTATEMSK8_STATEMSKn14_Pos)               /*!< SCT EVSTATEMSK8: STATEMSKn14 Mask   */
#define SCT_EVSTATEMSK8_STATEMSKn15_Pos                       15                                                        /*!< SCT EVSTATEMSK8: STATEMSKn15 Position */
#define SCT_EVSTATEMSK8_STATEMSKn15_Msk                       (0x01UL << SCT_EVSTATEMSK8_STATEMSKn15_Pos)               /*!< SCT EVSTATEMSK8: STATEMSKn15 Mask   */
#define SCT_EVSTATEMSK8_STATEMSKn16_Pos                       16                                                        /*!< SCT EVSTATEMSK8: STATEMSKn16 Position */
#define SCT_EVSTATEMSK8_STATEMSKn16_Msk                       (0x01UL << SCT_EVSTATEMSK8_STATEMSKn16_Pos)               /*!< SCT EVSTATEMSK8: STATEMSKn16 Mask   */
#define SCT_EVSTATEMSK8_STATEMSKn17_Pos                       17                                                        /*!< SCT EVSTATEMSK8: STATEMSKn17 Position */
#define SCT_EVSTATEMSK8_STATEMSKn17_Msk                       (0x01UL << SCT_EVSTATEMSK8_STATEMSKn17_Pos)               /*!< SCT EVSTATEMSK8: STATEMSKn17 Mask   */
#define SCT_EVSTATEMSK8_STATEMSKn18_Pos                       18                                                        /*!< SCT EVSTATEMSK8: STATEMSKn18 Position */
#define SCT_EVSTATEMSK8_STATEMSKn18_Msk                       (0x01UL << SCT_EVSTATEMSK8_STATEMSKn18_Pos)               /*!< SCT EVSTATEMSK8: STATEMSKn18 Mask   */
#define SCT_EVSTATEMSK8_STATEMSKn19_Pos                       19                                                        /*!< SCT EVSTATEMSK8: STATEMSKn19 Position */
#define SCT_EVSTATEMSK8_STATEMSKn19_Msk                       (0x01UL << SCT_EVSTATEMSK8_STATEMSKn19_Pos)               /*!< SCT EVSTATEMSK8: STATEMSKn19 Mask   */
#define SCT_EVSTATEMSK8_STATEMSKn20_Pos                       20                                                        /*!< SCT EVSTATEMSK8: STATEMSKn20 Position */
#define SCT_EVSTATEMSK8_STATEMSKn20_Msk                       (0x01UL << SCT_EVSTATEMSK8_STATEMSKn20_Pos)               /*!< SCT EVSTATEMSK8: STATEMSKn20 Mask   */
#define SCT_EVSTATEMSK8_STATEMSKn21_Pos                       21                                                        /*!< SCT EVSTATEMSK8: STATEMSKn21 Position */
#define SCT_EVSTATEMSK8_STATEMSKn21_Msk                       (0x01UL << SCT_EVSTATEMSK8_STATEMSKn21_Pos)               /*!< SCT EVSTATEMSK8: STATEMSKn21 Mask   */
#define SCT_EVSTATEMSK8_STATEMSKn22_Pos                       22                                                        /*!< SCT EVSTATEMSK8: STATEMSKn22 Position */
#define SCT_EVSTATEMSK8_STATEMSKn22_Msk                       (0x01UL << SCT_EVSTATEMSK8_STATEMSKn22_Pos)               /*!< SCT EVSTATEMSK8: STATEMSKn22 Mask   */
#define SCT_EVSTATEMSK8_STATEMSKn23_Pos                       23                                                        /*!< SCT EVSTATEMSK8: STATEMSKn23 Position */
#define SCT_EVSTATEMSK8_STATEMSKn23_Msk                       (0x01UL << SCT_EVSTATEMSK8_STATEMSKn23_Pos)               /*!< SCT EVSTATEMSK8: STATEMSKn23 Mask   */
#define SCT_EVSTATEMSK8_STATEMSKn24_Pos                       24                                                        /*!< SCT EVSTATEMSK8: STATEMSKn24 Position */
#define SCT_EVSTATEMSK8_STATEMSKn24_Msk                       (0x01UL << SCT_EVSTATEMSK8_STATEMSKn24_Pos)               /*!< SCT EVSTATEMSK8: STATEMSKn24 Mask   */
#define SCT_EVSTATEMSK8_STATEMSKn25_Pos                       25                                                        /*!< SCT EVSTATEMSK8: STATEMSKn25 Position */
#define SCT_EVSTATEMSK8_STATEMSKn25_Msk                       (0x01UL << SCT_EVSTATEMSK8_STATEMSKn25_Pos)               /*!< SCT EVSTATEMSK8: STATEMSKn25 Mask   */
#define SCT_EVSTATEMSK8_STATEMSKn26_Pos                       26                                                        /*!< SCT EVSTATEMSK8: STATEMSKn26 Position */
#define SCT_EVSTATEMSK8_STATEMSKn26_Msk                       (0x01UL << SCT_EVSTATEMSK8_STATEMSKn26_Pos)               /*!< SCT EVSTATEMSK8: STATEMSKn26 Mask   */
#define SCT_EVSTATEMSK8_STATEMSKn27_Pos                       27                                                        /*!< SCT EVSTATEMSK8: STATEMSKn27 Position */
#define SCT_EVSTATEMSK8_STATEMSKn27_Msk                       (0x01UL << SCT_EVSTATEMSK8_STATEMSKn27_Pos)               /*!< SCT EVSTATEMSK8: STATEMSKn27 Mask   */
#define SCT_EVSTATEMSK8_STATEMSKn28_Pos                       28                                                        /*!< SCT EVSTATEMSK8: STATEMSKn28 Position */
#define SCT_EVSTATEMSK8_STATEMSKn28_Msk                       (0x01UL << SCT_EVSTATEMSK8_STATEMSKn28_Pos)               /*!< SCT EVSTATEMSK8: STATEMSKn28 Mask   */
#define SCT_EVSTATEMSK8_STATEMSKn29_Pos                       29                                                        /*!< SCT EVSTATEMSK8: STATEMSKn29 Position */
#define SCT_EVSTATEMSK8_STATEMSKn29_Msk                       (0x01UL << SCT_EVSTATEMSK8_STATEMSKn29_Pos)               /*!< SCT EVSTATEMSK8: STATEMSKn29 Mask   */
#define SCT_EVSTATEMSK8_STATEMSKn30_Pos                       30                                                        /*!< SCT EVSTATEMSK8: STATEMSKn30 Position */
#define SCT_EVSTATEMSK8_STATEMSKn30_Msk                       (0x01UL << SCT_EVSTATEMSK8_STATEMSKn30_Pos)               /*!< SCT EVSTATEMSK8: STATEMSKn30 Mask   */
#define SCT_EVSTATEMSK8_STATEMSKn31_Pos                       31                                                        /*!< SCT EVSTATEMSK8: STATEMSKn31 Position */
#define SCT_EVSTATEMSK8_STATEMSKn31_Msk                       (0x01UL << SCT_EVSTATEMSK8_STATEMSKn31_Pos)               /*!< SCT EVSTATEMSK8: STATEMSKn31 Mask   */

// ---------------------------------------  SCT_EVCTRL8  ------------------------------------------
#define SCT_EVCTRL8_MATCHSEL_Pos                              0                                                         /*!< SCT EVCTRL8: MATCHSEL Position      */
#define SCT_EVCTRL8_MATCHSEL_Msk                              (0x0fUL << SCT_EVCTRL8_MATCHSEL_Pos)                      /*!< SCT EVCTRL8: MATCHSEL Mask          */
#define SCT_EVCTRL8_HEVENT_Pos                                4                                                         /*!< SCT EVCTRL8: HEVENT Position        */
#define SCT_EVCTRL8_HEVENT_Msk                                (0x01UL << SCT_EVCTRL8_HEVENT_Pos)                        /*!< SCT EVCTRL8: HEVENT Mask            */
#define SCT_EVCTRL8_OUTSEL_Pos                                5                                                         /*!< SCT EVCTRL8: OUTSEL Position        */
#define SCT_EVCTRL8_OUTSEL_Msk                                (0x01UL << SCT_EVCTRL8_OUTSEL_Pos)                        /*!< SCT EVCTRL8: OUTSEL Mask            */
#define SCT_EVCTRL8_IOSEL_Pos                                 6                                                         /*!< SCT EVCTRL8: IOSEL Position         */
#define SCT_EVCTRL8_IOSEL_Msk                                 (0x0fUL << SCT_EVCTRL8_IOSEL_Pos)                         /*!< SCT EVCTRL8: IOSEL Mask             */
#define SCT_EVCTRL8_IOCOND_Pos                                10                                                        /*!< SCT EVCTRL8: IOCOND Position        */
#define SCT_EVCTRL8_IOCOND_Msk                                (0x03UL << SCT_EVCTRL8_IOCOND_Pos)                        /*!< SCT EVCTRL8: IOCOND Mask            */
#define SCT_EVCTRL8_COMBMODE_Pos                              12                                                        /*!< SCT EVCTRL8: COMBMODE Position      */
#define SCT_EVCTRL8_COMBMODE_Msk                              (0x03UL << SCT_EVCTRL8_COMBMODE_Pos)                      /*!< SCT EVCTRL8: COMBMODE Mask          */
#define SCT_EVCTRL8_STATELD_Pos                               14                                                        /*!< SCT EVCTRL8: STATELD Position       */
#define SCT_EVCTRL8_STATELD_Msk                               (0x01UL << SCT_EVCTRL8_STATELD_Pos)                       /*!< SCT EVCTRL8: STATELD Mask           */
#define SCT_EVCTRL8_STATEV_Pos                                15                                                        /*!< SCT EVCTRL8: STATEV Position        */
#define SCT_EVCTRL8_STATEV_Msk                                (0x1fUL << SCT_EVCTRL8_STATEV_Pos)                        /*!< SCT EVCTRL8: STATEV Mask            */

// -------------------------------------  SCT_EVSTATEMSK9  ----------------------------------------
#define SCT_EVSTATEMSK9_STATEMSKn0_Pos                        0                                                         /*!< SCT EVSTATEMSK9: STATEMSKn0 Position */
#define SCT_EVSTATEMSK9_STATEMSKn0_Msk                        (0x01UL << SCT_EVSTATEMSK9_STATEMSKn0_Pos)                /*!< SCT EVSTATEMSK9: STATEMSKn0 Mask    */
#define SCT_EVSTATEMSK9_STATEMSKn1_Pos                        1                                                         /*!< SCT EVSTATEMSK9: STATEMSKn1 Position */
#define SCT_EVSTATEMSK9_STATEMSKn1_Msk                        (0x01UL << SCT_EVSTATEMSK9_STATEMSKn1_Pos)                /*!< SCT EVSTATEMSK9: STATEMSKn1 Mask    */
#define SCT_EVSTATEMSK9_STATEMSKn2_Pos                        2                                                         /*!< SCT EVSTATEMSK9: STATEMSKn2 Position */
#define SCT_EVSTATEMSK9_STATEMSKn2_Msk                        (0x01UL << SCT_EVSTATEMSK9_STATEMSKn2_Pos)                /*!< SCT EVSTATEMSK9: STATEMSKn2 Mask    */
#define SCT_EVSTATEMSK9_STATEMSKn3_Pos                        3                                                         /*!< SCT EVSTATEMSK9: STATEMSKn3 Position */
#define SCT_EVSTATEMSK9_STATEMSKn3_Msk                        (0x01UL << SCT_EVSTATEMSK9_STATEMSKn3_Pos)                /*!< SCT EVSTATEMSK9: STATEMSKn3 Mask    */
#define SCT_EVSTATEMSK9_STATEMSKn4_Pos                        4                                                         /*!< SCT EVSTATEMSK9: STATEMSKn4 Position */
#define SCT_EVSTATEMSK9_STATEMSKn4_Msk                        (0x01UL << SCT_EVSTATEMSK9_STATEMSKn4_Pos)                /*!< SCT EVSTATEMSK9: STATEMSKn4 Mask    */
#define SCT_EVSTATEMSK9_STATEMSKn5_Pos                        5                                                         /*!< SCT EVSTATEMSK9: STATEMSKn5 Position */
#define SCT_EVSTATEMSK9_STATEMSKn5_Msk                        (0x01UL << SCT_EVSTATEMSK9_STATEMSKn5_Pos)                /*!< SCT EVSTATEMSK9: STATEMSKn5 Mask    */
#define SCT_EVSTATEMSK9_STATEMSKn6_Pos                        6                                                         /*!< SCT EVSTATEMSK9: STATEMSKn6 Position */
#define SCT_EVSTATEMSK9_STATEMSKn6_Msk                        (0x01UL << SCT_EVSTATEMSK9_STATEMSKn6_Pos)                /*!< SCT EVSTATEMSK9: STATEMSKn6 Mask    */
#define SCT_EVSTATEMSK9_STATEMSKn7_Pos                        7                                                         /*!< SCT EVSTATEMSK9: STATEMSKn7 Position */
#define SCT_EVSTATEMSK9_STATEMSKn7_Msk                        (0x01UL << SCT_EVSTATEMSK9_STATEMSKn7_Pos)                /*!< SCT EVSTATEMSK9: STATEMSKn7 Mask    */
#define SCT_EVSTATEMSK9_STATEMSKn8_Pos                        8                                                         /*!< SCT EVSTATEMSK9: STATEMSKn8 Position */
#define SCT_EVSTATEMSK9_STATEMSKn8_Msk                        (0x01UL << SCT_EVSTATEMSK9_STATEMSKn8_Pos)                /*!< SCT EVSTATEMSK9: STATEMSKn8 Mask    */
#define SCT_EVSTATEMSK9_STATEMSKn9_Pos                        9                                                         /*!< SCT EVSTATEMSK9: STATEMSKn9 Position */
#define SCT_EVSTATEMSK9_STATEMSKn9_Msk                        (0x01UL << SCT_EVSTATEMSK9_STATEMSKn9_Pos)                /*!< SCT EVSTATEMSK9: STATEMSKn9 Mask    */
#define SCT_EVSTATEMSK9_STATEMSKn10_Pos                       10                                                        /*!< SCT EVSTATEMSK9: STATEMSKn10 Position */
#define SCT_EVSTATEMSK9_STATEMSKn10_Msk                       (0x01UL << SCT_EVSTATEMSK9_STATEMSKn10_Pos)               /*!< SCT EVSTATEMSK9: STATEMSKn10 Mask   */
#define SCT_EVSTATEMSK9_STATEMSKn11_Pos                       11                                                        /*!< SCT EVSTATEMSK9: STATEMSKn11 Position */
#define SCT_EVSTATEMSK9_STATEMSKn11_Msk                       (0x01UL << SCT_EVSTATEMSK9_STATEMSKn11_Pos)               /*!< SCT EVSTATEMSK9: STATEMSKn11 Mask   */
#define SCT_EVSTATEMSK9_STATEMSKn12_Pos                       12                                                        /*!< SCT EVSTATEMSK9: STATEMSKn12 Position */
#define SCT_EVSTATEMSK9_STATEMSKn12_Msk                       (0x01UL << SCT_EVSTATEMSK9_STATEMSKn12_Pos)               /*!< SCT EVSTATEMSK9: STATEMSKn12 Mask   */
#define SCT_EVSTATEMSK9_STATEMSKn13_Pos                       13                                                        /*!< SCT EVSTATEMSK9: STATEMSKn13 Position */
#define SCT_EVSTATEMSK9_STATEMSKn13_Msk                       (0x01UL << SCT_EVSTATEMSK9_STATEMSKn13_Pos)               /*!< SCT EVSTATEMSK9: STATEMSKn13 Mask   */
#define SCT_EVSTATEMSK9_STATEMSKn14_Pos                       14                                                        /*!< SCT EVSTATEMSK9: STATEMSKn14 Position */
#define SCT_EVSTATEMSK9_STATEMSKn14_Msk                       (0x01UL << SCT_EVSTATEMSK9_STATEMSKn14_Pos)               /*!< SCT EVSTATEMSK9: STATEMSKn14 Mask   */
#define SCT_EVSTATEMSK9_STATEMSKn15_Pos                       15                                                        /*!< SCT EVSTATEMSK9: STATEMSKn15 Position */
#define SCT_EVSTATEMSK9_STATEMSKn15_Msk                       (0x01UL << SCT_EVSTATEMSK9_STATEMSKn15_Pos)               /*!< SCT EVSTATEMSK9: STATEMSKn15 Mask   */
#define SCT_EVSTATEMSK9_STATEMSKn16_Pos                       16                                                        /*!< SCT EVSTATEMSK9: STATEMSKn16 Position */
#define SCT_EVSTATEMSK9_STATEMSKn16_Msk                       (0x01UL << SCT_EVSTATEMSK9_STATEMSKn16_Pos)               /*!< SCT EVSTATEMSK9: STATEMSKn16 Mask   */
#define SCT_EVSTATEMSK9_STATEMSKn17_Pos                       17                                                        /*!< SCT EVSTATEMSK9: STATEMSKn17 Position */
#define SCT_EVSTATEMSK9_STATEMSKn17_Msk                       (0x01UL << SCT_EVSTATEMSK9_STATEMSKn17_Pos)               /*!< SCT EVSTATEMSK9: STATEMSKn17 Mask   */
#define SCT_EVSTATEMSK9_STATEMSKn18_Pos                       18                                                        /*!< SCT EVSTATEMSK9: STATEMSKn18 Position */
#define SCT_EVSTATEMSK9_STATEMSKn18_Msk                       (0x01UL << SCT_EVSTATEMSK9_STATEMSKn18_Pos)               /*!< SCT EVSTATEMSK9: STATEMSKn18 Mask   */
#define SCT_EVSTATEMSK9_STATEMSKn19_Pos                       19                                                        /*!< SCT EVSTATEMSK9: STATEMSKn19 Position */
#define SCT_EVSTATEMSK9_STATEMSKn19_Msk                       (0x01UL << SCT_EVSTATEMSK9_STATEMSKn19_Pos)               /*!< SCT EVSTATEMSK9: STATEMSKn19 Mask   */
#define SCT_EVSTATEMSK9_STATEMSKn20_Pos                       20                                                        /*!< SCT EVSTATEMSK9: STATEMSKn20 Position */
#define SCT_EVSTATEMSK9_STATEMSKn20_Msk                       (0x01UL << SCT_EVSTATEMSK9_STATEMSKn20_Pos)               /*!< SCT EVSTATEMSK9: STATEMSKn20 Mask   */
#define SCT_EVSTATEMSK9_STATEMSKn21_Pos                       21                                                        /*!< SCT EVSTATEMSK9: STATEMSKn21 Position */
#define SCT_EVSTATEMSK9_STATEMSKn21_Msk                       (0x01UL << SCT_EVSTATEMSK9_STATEMSKn21_Pos)               /*!< SCT EVSTATEMSK9: STATEMSKn21 Mask   */
#define SCT_EVSTATEMSK9_STATEMSKn22_Pos                       22                                                        /*!< SCT EVSTATEMSK9: STATEMSKn22 Position */
#define SCT_EVSTATEMSK9_STATEMSKn22_Msk                       (0x01UL << SCT_EVSTATEMSK9_STATEMSKn22_Pos)               /*!< SCT EVSTATEMSK9: STATEMSKn22 Mask   */
#define SCT_EVSTATEMSK9_STATEMSKn23_Pos                       23                                                        /*!< SCT EVSTATEMSK9: STATEMSKn23 Position */
#define SCT_EVSTATEMSK9_STATEMSKn23_Msk                       (0x01UL << SCT_EVSTATEMSK9_STATEMSKn23_Pos)               /*!< SCT EVSTATEMSK9: STATEMSKn23 Mask   */
#define SCT_EVSTATEMSK9_STATEMSKn24_Pos                       24                                                        /*!< SCT EVSTATEMSK9: STATEMSKn24 Position */
#define SCT_EVSTATEMSK9_STATEMSKn24_Msk                       (0x01UL << SCT_EVSTATEMSK9_STATEMSKn24_Pos)               /*!< SCT EVSTATEMSK9: STATEMSKn24 Mask   */
#define SCT_EVSTATEMSK9_STATEMSKn25_Pos                       25                                                        /*!< SCT EVSTATEMSK9: STATEMSKn25 Position */
#define SCT_EVSTATEMSK9_STATEMSKn25_Msk                       (0x01UL << SCT_EVSTATEMSK9_STATEMSKn25_Pos)               /*!< SCT EVSTATEMSK9: STATEMSKn25 Mask   */
#define SCT_EVSTATEMSK9_STATEMSKn26_Pos                       26                                                        /*!< SCT EVSTATEMSK9: STATEMSKn26 Position */
#define SCT_EVSTATEMSK9_STATEMSKn26_Msk                       (0x01UL << SCT_EVSTATEMSK9_STATEMSKn26_Pos)               /*!< SCT EVSTATEMSK9: STATEMSKn26 Mask   */
#define SCT_EVSTATEMSK9_STATEMSKn27_Pos                       27                                                        /*!< SCT EVSTATEMSK9: STATEMSKn27 Position */
#define SCT_EVSTATEMSK9_STATEMSKn27_Msk                       (0x01UL << SCT_EVSTATEMSK9_STATEMSKn27_Pos)               /*!< SCT EVSTATEMSK9: STATEMSKn27 Mask   */
#define SCT_EVSTATEMSK9_STATEMSKn28_Pos                       28                                                        /*!< SCT EVSTATEMSK9: STATEMSKn28 Position */
#define SCT_EVSTATEMSK9_STATEMSKn28_Msk                       (0x01UL << SCT_EVSTATEMSK9_STATEMSKn28_Pos)               /*!< SCT EVSTATEMSK9: STATEMSKn28 Mask   */
#define SCT_EVSTATEMSK9_STATEMSKn29_Pos                       29                                                        /*!< SCT EVSTATEMSK9: STATEMSKn29 Position */
#define SCT_EVSTATEMSK9_STATEMSKn29_Msk                       (0x01UL << SCT_EVSTATEMSK9_STATEMSKn29_Pos)               /*!< SCT EVSTATEMSK9: STATEMSKn29 Mask   */
#define SCT_EVSTATEMSK9_STATEMSKn30_Pos                       30                                                        /*!< SCT EVSTATEMSK9: STATEMSKn30 Position */
#define SCT_EVSTATEMSK9_STATEMSKn30_Msk                       (0x01UL << SCT_EVSTATEMSK9_STATEMSKn30_Pos)               /*!< SCT EVSTATEMSK9: STATEMSKn30 Mask   */
#define SCT_EVSTATEMSK9_STATEMSKn31_Pos                       31                                                        /*!< SCT EVSTATEMSK9: STATEMSKn31 Position */
#define SCT_EVSTATEMSK9_STATEMSKn31_Msk                       (0x01UL << SCT_EVSTATEMSK9_STATEMSKn31_Pos)               /*!< SCT EVSTATEMSK9: STATEMSKn31 Mask   */

// ---------------------------------------  SCT_EVCTRL9  ------------------------------------------
#define SCT_EVCTRL9_MATCHSEL_Pos                              0                                                         /*!< SCT EVCTRL9: MATCHSEL Position      */
#define SCT_EVCTRL9_MATCHSEL_Msk                              (0x0fUL << SCT_EVCTRL9_MATCHSEL_Pos)                      /*!< SCT EVCTRL9: MATCHSEL Mask          */
#define SCT_EVCTRL9_HEVENT_Pos                                4                                                         /*!< SCT EVCTRL9: HEVENT Position        */
#define SCT_EVCTRL9_HEVENT_Msk                                (0x01UL << SCT_EVCTRL9_HEVENT_Pos)                        /*!< SCT EVCTRL9: HEVENT Mask            */
#define SCT_EVCTRL9_OUTSEL_Pos                                5                                                         /*!< SCT EVCTRL9: OUTSEL Position        */
#define SCT_EVCTRL9_OUTSEL_Msk                                (0x01UL << SCT_EVCTRL9_OUTSEL_Pos)                        /*!< SCT EVCTRL9: OUTSEL Mask            */
#define SCT_EVCTRL9_IOSEL_Pos                                 6                                                         /*!< SCT EVCTRL9: IOSEL Position         */
#define SCT_EVCTRL9_IOSEL_Msk                                 (0x0fUL << SCT_EVCTRL9_IOSEL_Pos)                         /*!< SCT EVCTRL9: IOSEL Mask             */
#define SCT_EVCTRL9_IOCOND_Pos                                10                                                        /*!< SCT EVCTRL9: IOCOND Position        */
#define SCT_EVCTRL9_IOCOND_Msk                                (0x03UL << SCT_EVCTRL9_IOCOND_Pos)                        /*!< SCT EVCTRL9: IOCOND Mask            */
#define SCT_EVCTRL9_COMBMODE_Pos                              12                                                        /*!< SCT EVCTRL9: COMBMODE Position      */
#define SCT_EVCTRL9_COMBMODE_Msk                              (0x03UL << SCT_EVCTRL9_COMBMODE_Pos)                      /*!< SCT EVCTRL9: COMBMODE Mask          */
#define SCT_EVCTRL9_STATELD_Pos                               14                                                        /*!< SCT EVCTRL9: STATELD Position       */
#define SCT_EVCTRL9_STATELD_Msk                               (0x01UL << SCT_EVCTRL9_STATELD_Pos)                       /*!< SCT EVCTRL9: STATELD Mask           */
#define SCT_EVCTRL9_STATEV_Pos                                15                                                        /*!< SCT EVCTRL9: STATEV Position        */
#define SCT_EVCTRL9_STATEV_Msk                                (0x1fUL << SCT_EVCTRL9_STATEV_Pos)                        /*!< SCT EVCTRL9: STATEV Mask            */

// ------------------------------------  SCT_EVSTATEMSK10  ----------------------------------------
#define SCT_EVSTATEMSK10_STATEMSKn0_Pos                       0                                                         /*!< SCT EVSTATEMSK10: STATEMSKn0 Position */
#define SCT_EVSTATEMSK10_STATEMSKn0_Msk                       (0x01UL << SCT_EVSTATEMSK10_STATEMSKn0_Pos)               /*!< SCT EVSTATEMSK10: STATEMSKn0 Mask   */
#define SCT_EVSTATEMSK10_STATEMSKn1_Pos                       1                                                         /*!< SCT EVSTATEMSK10: STATEMSKn1 Position */
#define SCT_EVSTATEMSK10_STATEMSKn1_Msk                       (0x01UL << SCT_EVSTATEMSK10_STATEMSKn1_Pos)               /*!< SCT EVSTATEMSK10: STATEMSKn1 Mask   */
#define SCT_EVSTATEMSK10_STATEMSKn2_Pos                       2                                                         /*!< SCT EVSTATEMSK10: STATEMSKn2 Position */
#define SCT_EVSTATEMSK10_STATEMSKn2_Msk                       (0x01UL << SCT_EVSTATEMSK10_STATEMSKn2_Pos)               /*!< SCT EVSTATEMSK10: STATEMSKn2 Mask   */
#define SCT_EVSTATEMSK10_STATEMSKn3_Pos                       3                                                         /*!< SCT EVSTATEMSK10: STATEMSKn3 Position */
#define SCT_EVSTATEMSK10_STATEMSKn3_Msk                       (0x01UL << SCT_EVSTATEMSK10_STATEMSKn3_Pos)               /*!< SCT EVSTATEMSK10: STATEMSKn3 Mask   */
#define SCT_EVSTATEMSK10_STATEMSKn4_Pos                       4                                                         /*!< SCT EVSTATEMSK10: STATEMSKn4 Position */
#define SCT_EVSTATEMSK10_STATEMSKn4_Msk                       (0x01UL << SCT_EVSTATEMSK10_STATEMSKn4_Pos)               /*!< SCT EVSTATEMSK10: STATEMSKn4 Mask   */
#define SCT_EVSTATEMSK10_STATEMSKn5_Pos                       5                                                         /*!< SCT EVSTATEMSK10: STATEMSKn5 Position */
#define SCT_EVSTATEMSK10_STATEMSKn5_Msk                       (0x01UL << SCT_EVSTATEMSK10_STATEMSKn5_Pos)               /*!< SCT EVSTATEMSK10: STATEMSKn5 Mask   */
#define SCT_EVSTATEMSK10_STATEMSKn6_Pos                       6                                                         /*!< SCT EVSTATEMSK10: STATEMSKn6 Position */
#define SCT_EVSTATEMSK10_STATEMSKn6_Msk                       (0x01UL << SCT_EVSTATEMSK10_STATEMSKn6_Pos)               /*!< SCT EVSTATEMSK10: STATEMSKn6 Mask   */
#define SCT_EVSTATEMSK10_STATEMSKn7_Pos                       7                                                         /*!< SCT EVSTATEMSK10: STATEMSKn7 Position */
#define SCT_EVSTATEMSK10_STATEMSKn7_Msk                       (0x01UL << SCT_EVSTATEMSK10_STATEMSKn7_Pos)               /*!< SCT EVSTATEMSK10: STATEMSKn7 Mask   */
#define SCT_EVSTATEMSK10_STATEMSKn8_Pos                       8                                                         /*!< SCT EVSTATEMSK10: STATEMSKn8 Position */
#define SCT_EVSTATEMSK10_STATEMSKn8_Msk                       (0x01UL << SCT_EVSTATEMSK10_STATEMSKn8_Pos)               /*!< SCT EVSTATEMSK10: STATEMSKn8 Mask   */
#define SCT_EVSTATEMSK10_STATEMSKn9_Pos                       9                                                         /*!< SCT EVSTATEMSK10: STATEMSKn9 Position */
#define SCT_EVSTATEMSK10_STATEMSKn9_Msk                       (0x01UL << SCT_EVSTATEMSK10_STATEMSKn9_Pos)               /*!< SCT EVSTATEMSK10: STATEMSKn9 Mask   */
#define SCT_EVSTATEMSK10_STATEMSKn10_Pos                      10                                                        /*!< SCT EVSTATEMSK10: STATEMSKn10 Position */
#define SCT_EVSTATEMSK10_STATEMSKn10_Msk                      (0x01UL << SCT_EVSTATEMSK10_STATEMSKn10_Pos)              /*!< SCT EVSTATEMSK10: STATEMSKn10 Mask  */
#define SCT_EVSTATEMSK10_STATEMSKn11_Pos                      11                                                        /*!< SCT EVSTATEMSK10: STATEMSKn11 Position */
#define SCT_EVSTATEMSK10_STATEMSKn11_Msk                      (0x01UL << SCT_EVSTATEMSK10_STATEMSKn11_Pos)              /*!< SCT EVSTATEMSK10: STATEMSKn11 Mask  */
#define SCT_EVSTATEMSK10_STATEMSKn12_Pos                      12                                                        /*!< SCT EVSTATEMSK10: STATEMSKn12 Position */
#define SCT_EVSTATEMSK10_STATEMSKn12_Msk                      (0x01UL << SCT_EVSTATEMSK10_STATEMSKn12_Pos)              /*!< SCT EVSTATEMSK10: STATEMSKn12 Mask  */
#define SCT_EVSTATEMSK10_STATEMSKn13_Pos                      13                                                        /*!< SCT EVSTATEMSK10: STATEMSKn13 Position */
#define SCT_EVSTATEMSK10_STATEMSKn13_Msk                      (0x01UL << SCT_EVSTATEMSK10_STATEMSKn13_Pos)              /*!< SCT EVSTATEMSK10: STATEMSKn13 Mask  */
#define SCT_EVSTATEMSK10_STATEMSKn14_Pos                      14                                                        /*!< SCT EVSTATEMSK10: STATEMSKn14 Position */
#define SCT_EVSTATEMSK10_STATEMSKn14_Msk                      (0x01UL << SCT_EVSTATEMSK10_STATEMSKn14_Pos)              /*!< SCT EVSTATEMSK10: STATEMSKn14 Mask  */
#define SCT_EVSTATEMSK10_STATEMSKn15_Pos                      15                                                        /*!< SCT EVSTATEMSK10: STATEMSKn15 Position */
#define SCT_EVSTATEMSK10_STATEMSKn15_Msk                      (0x01UL << SCT_EVSTATEMSK10_STATEMSKn15_Pos)              /*!< SCT EVSTATEMSK10: STATEMSKn15 Mask  */
#define SCT_EVSTATEMSK10_STATEMSKn16_Pos                      16                                                        /*!< SCT EVSTATEMSK10: STATEMSKn16 Position */
#define SCT_EVSTATEMSK10_STATEMSKn16_Msk                      (0x01UL << SCT_EVSTATEMSK10_STATEMSKn16_Pos)              /*!< SCT EVSTATEMSK10: STATEMSKn16 Mask  */
#define SCT_EVSTATEMSK10_STATEMSKn17_Pos                      17                                                        /*!< SCT EVSTATEMSK10: STATEMSKn17 Position */
#define SCT_EVSTATEMSK10_STATEMSKn17_Msk                      (0x01UL << SCT_EVSTATEMSK10_STATEMSKn17_Pos)              /*!< SCT EVSTATEMSK10: STATEMSKn17 Mask  */
#define SCT_EVSTATEMSK10_STATEMSKn18_Pos                      18                                                        /*!< SCT EVSTATEMSK10: STATEMSKn18 Position */
#define SCT_EVSTATEMSK10_STATEMSKn18_Msk                      (0x01UL << SCT_EVSTATEMSK10_STATEMSKn18_Pos)              /*!< SCT EVSTATEMSK10: STATEMSKn18 Mask  */
#define SCT_EVSTATEMSK10_STATEMSKn19_Pos                      19                                                        /*!< SCT EVSTATEMSK10: STATEMSKn19 Position */
#define SCT_EVSTATEMSK10_STATEMSKn19_Msk                      (0x01UL << SCT_EVSTATEMSK10_STATEMSKn19_Pos)              /*!< SCT EVSTATEMSK10: STATEMSKn19 Mask  */
#define SCT_EVSTATEMSK10_STATEMSKn20_Pos                      20                                                        /*!< SCT EVSTATEMSK10: STATEMSKn20 Position */
#define SCT_EVSTATEMSK10_STATEMSKn20_Msk                      (0x01UL << SCT_EVSTATEMSK10_STATEMSKn20_Pos)              /*!< SCT EVSTATEMSK10: STATEMSKn20 Mask  */
#define SCT_EVSTATEMSK10_STATEMSKn21_Pos                      21                                                        /*!< SCT EVSTATEMSK10: STATEMSKn21 Position */
#define SCT_EVSTATEMSK10_STATEMSKn21_Msk                      (0x01UL << SCT_EVSTATEMSK10_STATEMSKn21_Pos)              /*!< SCT EVSTATEMSK10: STATEMSKn21 Mask  */
#define SCT_EVSTATEMSK10_STATEMSKn22_Pos                      22                                                        /*!< SCT EVSTATEMSK10: STATEMSKn22 Position */
#define SCT_EVSTATEMSK10_STATEMSKn22_Msk                      (0x01UL << SCT_EVSTATEMSK10_STATEMSKn22_Pos)              /*!< SCT EVSTATEMSK10: STATEMSKn22 Mask  */
#define SCT_EVSTATEMSK10_STATEMSKn23_Pos                      23                                                        /*!< SCT EVSTATEMSK10: STATEMSKn23 Position */
#define SCT_EVSTATEMSK10_STATEMSKn23_Msk                      (0x01UL << SCT_EVSTATEMSK10_STATEMSKn23_Pos)              /*!< SCT EVSTATEMSK10: STATEMSKn23 Mask  */
#define SCT_EVSTATEMSK10_STATEMSKn24_Pos                      24                                                        /*!< SCT EVSTATEMSK10: STATEMSKn24 Position */
#define SCT_EVSTATEMSK10_STATEMSKn24_Msk                      (0x01UL << SCT_EVSTATEMSK10_STATEMSKn24_Pos)              /*!< SCT EVSTATEMSK10: STATEMSKn24 Mask  */
#define SCT_EVSTATEMSK10_STATEMSKn25_Pos                      25                                                        /*!< SCT EVSTATEMSK10: STATEMSKn25 Position */
#define SCT_EVSTATEMSK10_STATEMSKn25_Msk                      (0x01UL << SCT_EVSTATEMSK10_STATEMSKn25_Pos)              /*!< SCT EVSTATEMSK10: STATEMSKn25 Mask  */
#define SCT_EVSTATEMSK10_STATEMSKn26_Pos                      26                                                        /*!< SCT EVSTATEMSK10: STATEMSKn26 Position */
#define SCT_EVSTATEMSK10_STATEMSKn26_Msk                      (0x01UL << SCT_EVSTATEMSK10_STATEMSKn26_Pos)              /*!< SCT EVSTATEMSK10: STATEMSKn26 Mask  */
#define SCT_EVSTATEMSK10_STATEMSKn27_Pos                      27                                                        /*!< SCT EVSTATEMSK10: STATEMSKn27 Position */
#define SCT_EVSTATEMSK10_STATEMSKn27_Msk                      (0x01UL << SCT_EVSTATEMSK10_STATEMSKn27_Pos)              /*!< SCT EVSTATEMSK10: STATEMSKn27 Mask  */
#define SCT_EVSTATEMSK10_STATEMSKn28_Pos                      28                                                        /*!< SCT EVSTATEMSK10: STATEMSKn28 Position */
#define SCT_EVSTATEMSK10_STATEMSKn28_Msk                      (0x01UL << SCT_EVSTATEMSK10_STATEMSKn28_Pos)              /*!< SCT EVSTATEMSK10: STATEMSKn28 Mask  */
#define SCT_EVSTATEMSK10_STATEMSKn29_Pos                      29                                                        /*!< SCT EVSTATEMSK10: STATEMSKn29 Position */
#define SCT_EVSTATEMSK10_STATEMSKn29_Msk                      (0x01UL << SCT_EVSTATEMSK10_STATEMSKn29_Pos)              /*!< SCT EVSTATEMSK10: STATEMSKn29 Mask  */
#define SCT_EVSTATEMSK10_STATEMSKn30_Pos                      30                                                        /*!< SCT EVSTATEMSK10: STATEMSKn30 Position */
#define SCT_EVSTATEMSK10_STATEMSKn30_Msk                      (0x01UL << SCT_EVSTATEMSK10_STATEMSKn30_Pos)              /*!< SCT EVSTATEMSK10: STATEMSKn30 Mask  */
#define SCT_EVSTATEMSK10_STATEMSKn31_Pos                      31                                                        /*!< SCT EVSTATEMSK10: STATEMSKn31 Position */
#define SCT_EVSTATEMSK10_STATEMSKn31_Msk                      (0x01UL << SCT_EVSTATEMSK10_STATEMSKn31_Pos)              /*!< SCT EVSTATEMSK10: STATEMSKn31 Mask  */

// --------------------------------------  SCT_EVCTRL10  ------------------------------------------
#define SCT_EVCTRL10_MATCHSEL_Pos                             0                                                         /*!< SCT EVCTRL10: MATCHSEL Position     */
#define SCT_EVCTRL10_MATCHSEL_Msk                             (0x0fUL << SCT_EVCTRL10_MATCHSEL_Pos)                     /*!< SCT EVCTRL10: MATCHSEL Mask         */
#define SCT_EVCTRL10_HEVENT_Pos                               4                                                         /*!< SCT EVCTRL10: HEVENT Position       */
#define SCT_EVCTRL10_HEVENT_Msk                               (0x01UL << SCT_EVCTRL10_HEVENT_Pos)                       /*!< SCT EVCTRL10: HEVENT Mask           */
#define SCT_EVCTRL10_OUTSEL_Pos                               5                                                         /*!< SCT EVCTRL10: OUTSEL Position       */
#define SCT_EVCTRL10_OUTSEL_Msk                               (0x01UL << SCT_EVCTRL10_OUTSEL_Pos)                       /*!< SCT EVCTRL10: OUTSEL Mask           */
#define SCT_EVCTRL10_IOSEL_Pos                                6                                                         /*!< SCT EVCTRL10: IOSEL Position        */
#define SCT_EVCTRL10_IOSEL_Msk                                (0x0fUL << SCT_EVCTRL10_IOSEL_Pos)                        /*!< SCT EVCTRL10: IOSEL Mask            */
#define SCT_EVCTRL10_IOCOND_Pos                               10                                                        /*!< SCT EVCTRL10: IOCOND Position       */
#define SCT_EVCTRL10_IOCOND_Msk                               (0x03UL << SCT_EVCTRL10_IOCOND_Pos)                       /*!< SCT EVCTRL10: IOCOND Mask           */
#define SCT_EVCTRL10_COMBMODE_Pos                             12                                                        /*!< SCT EVCTRL10: COMBMODE Position     */
#define SCT_EVCTRL10_COMBMODE_Msk                             (0x03UL << SCT_EVCTRL10_COMBMODE_Pos)                     /*!< SCT EVCTRL10: COMBMODE Mask         */
#define SCT_EVCTRL10_STATELD_Pos                              14                                                        /*!< SCT EVCTRL10: STATELD Position      */
#define SCT_EVCTRL10_STATELD_Msk                              (0x01UL << SCT_EVCTRL10_STATELD_Pos)                      /*!< SCT EVCTRL10: STATELD Mask          */
#define SCT_EVCTRL10_STATEV_Pos                               15                                                        /*!< SCT EVCTRL10: STATEV Position       */
#define SCT_EVCTRL10_STATEV_Msk                               (0x1fUL << SCT_EVCTRL10_STATEV_Pos)                       /*!< SCT EVCTRL10: STATEV Mask           */

// ------------------------------------  SCT_EVSTATEMSK11  ----------------------------------------
#define SCT_EVSTATEMSK11_STATEMSKn0_Pos                       0                                                         /*!< SCT EVSTATEMSK11: STATEMSKn0 Position */
#define SCT_EVSTATEMSK11_STATEMSKn0_Msk                       (0x01UL << SCT_EVSTATEMSK11_STATEMSKn0_Pos)               /*!< SCT EVSTATEMSK11: STATEMSKn0 Mask   */
#define SCT_EVSTATEMSK11_STATEMSKn1_Pos                       1                                                         /*!< SCT EVSTATEMSK11: STATEMSKn1 Position */
#define SCT_EVSTATEMSK11_STATEMSKn1_Msk                       (0x01UL << SCT_EVSTATEMSK11_STATEMSKn1_Pos)               /*!< SCT EVSTATEMSK11: STATEMSKn1 Mask   */
#define SCT_EVSTATEMSK11_STATEMSKn2_Pos                       2                                                         /*!< SCT EVSTATEMSK11: STATEMSKn2 Position */
#define SCT_EVSTATEMSK11_STATEMSKn2_Msk                       (0x01UL << SCT_EVSTATEMSK11_STATEMSKn2_Pos)               /*!< SCT EVSTATEMSK11: STATEMSKn2 Mask   */
#define SCT_EVSTATEMSK11_STATEMSKn3_Pos                       3                                                         /*!< SCT EVSTATEMSK11: STATEMSKn3 Position */
#define SCT_EVSTATEMSK11_STATEMSKn3_Msk                       (0x01UL << SCT_EVSTATEMSK11_STATEMSKn3_Pos)               /*!< SCT EVSTATEMSK11: STATEMSKn3 Mask   */
#define SCT_EVSTATEMSK11_STATEMSKn4_Pos                       4                                                         /*!< SCT EVSTATEMSK11: STATEMSKn4 Position */
#define SCT_EVSTATEMSK11_STATEMSKn4_Msk                       (0x01UL << SCT_EVSTATEMSK11_STATEMSKn4_Pos)               /*!< SCT EVSTATEMSK11: STATEMSKn4 Mask   */
#define SCT_EVSTATEMSK11_STATEMSKn5_Pos                       5                                                         /*!< SCT EVSTATEMSK11: STATEMSKn5 Position */
#define SCT_EVSTATEMSK11_STATEMSKn5_Msk                       (0x01UL << SCT_EVSTATEMSK11_STATEMSKn5_Pos)               /*!< SCT EVSTATEMSK11: STATEMSKn5 Mask   */
#define SCT_EVSTATEMSK11_STATEMSKn6_Pos                       6                                                         /*!< SCT EVSTATEMSK11: STATEMSKn6 Position */
#define SCT_EVSTATEMSK11_STATEMSKn6_Msk                       (0x01UL << SCT_EVSTATEMSK11_STATEMSKn6_Pos)               /*!< SCT EVSTATEMSK11: STATEMSKn6 Mask   */
#define SCT_EVSTATEMSK11_STATEMSKn7_Pos                       7                                                         /*!< SCT EVSTATEMSK11: STATEMSKn7 Position */
#define SCT_EVSTATEMSK11_STATEMSKn7_Msk                       (0x01UL << SCT_EVSTATEMSK11_STATEMSKn7_Pos)               /*!< SCT EVSTATEMSK11: STATEMSKn7 Mask   */
#define SCT_EVSTATEMSK11_STATEMSKn8_Pos                       8                                                         /*!< SCT EVSTATEMSK11: STATEMSKn8 Position */
#define SCT_EVSTATEMSK11_STATEMSKn8_Msk                       (0x01UL << SCT_EVSTATEMSK11_STATEMSKn8_Pos)               /*!< SCT EVSTATEMSK11: STATEMSKn8 Mask   */
#define SCT_EVSTATEMSK11_STATEMSKn9_Pos                       9                                                         /*!< SCT EVSTATEMSK11: STATEMSKn9 Position */
#define SCT_EVSTATEMSK11_STATEMSKn9_Msk                       (0x01UL << SCT_EVSTATEMSK11_STATEMSKn9_Pos)               /*!< SCT EVSTATEMSK11: STATEMSKn9 Mask   */
#define SCT_EVSTATEMSK11_STATEMSKn10_Pos                      10                                                        /*!< SCT EVSTATEMSK11: STATEMSKn10 Position */
#define SCT_EVSTATEMSK11_STATEMSKn10_Msk                      (0x01UL << SCT_EVSTATEMSK11_STATEMSKn10_Pos)              /*!< SCT EVSTATEMSK11: STATEMSKn10 Mask  */
#define SCT_EVSTATEMSK11_STATEMSKn11_Pos                      11                                                        /*!< SCT EVSTATEMSK11: STATEMSKn11 Position */
#define SCT_EVSTATEMSK11_STATEMSKn11_Msk                      (0x01UL << SCT_EVSTATEMSK11_STATEMSKn11_Pos)              /*!< SCT EVSTATEMSK11: STATEMSKn11 Mask  */
#define SCT_EVSTATEMSK11_STATEMSKn12_Pos                      12                                                        /*!< SCT EVSTATEMSK11: STATEMSKn12 Position */
#define SCT_EVSTATEMSK11_STATEMSKn12_Msk                      (0x01UL << SCT_EVSTATEMSK11_STATEMSKn12_Pos)              /*!< SCT EVSTATEMSK11: STATEMSKn12 Mask  */
#define SCT_EVSTATEMSK11_STATEMSKn13_Pos                      13                                                        /*!< SCT EVSTATEMSK11: STATEMSKn13 Position */
#define SCT_EVSTATEMSK11_STATEMSKn13_Msk                      (0x01UL << SCT_EVSTATEMSK11_STATEMSKn13_Pos)              /*!< SCT EVSTATEMSK11: STATEMSKn13 Mask  */
#define SCT_EVSTATEMSK11_STATEMSKn14_Pos                      14                                                        /*!< SCT EVSTATEMSK11: STATEMSKn14 Position */
#define SCT_EVSTATEMSK11_STATEMSKn14_Msk                      (0x01UL << SCT_EVSTATEMSK11_STATEMSKn14_Pos)              /*!< SCT EVSTATEMSK11: STATEMSKn14 Mask  */
#define SCT_EVSTATEMSK11_STATEMSKn15_Pos                      15                                                        /*!< SCT EVSTATEMSK11: STATEMSKn15 Position */
#define SCT_EVSTATEMSK11_STATEMSKn15_Msk                      (0x01UL << SCT_EVSTATEMSK11_STATEMSKn15_Pos)              /*!< SCT EVSTATEMSK11: STATEMSKn15 Mask  */
#define SCT_EVSTATEMSK11_STATEMSKn16_Pos                      16                                                        /*!< SCT EVSTATEMSK11: STATEMSKn16 Position */
#define SCT_EVSTATEMSK11_STATEMSKn16_Msk                      (0x01UL << SCT_EVSTATEMSK11_STATEMSKn16_Pos)              /*!< SCT EVSTATEMSK11: STATEMSKn16 Mask  */
#define SCT_EVSTATEMSK11_STATEMSKn17_Pos                      17                                                        /*!< SCT EVSTATEMSK11: STATEMSKn17 Position */
#define SCT_EVSTATEMSK11_STATEMSKn17_Msk                      (0x01UL << SCT_EVSTATEMSK11_STATEMSKn17_Pos)              /*!< SCT EVSTATEMSK11: STATEMSKn17 Mask  */
#define SCT_EVSTATEMSK11_STATEMSKn18_Pos                      18                                                        /*!< SCT EVSTATEMSK11: STATEMSKn18 Position */
#define SCT_EVSTATEMSK11_STATEMSKn18_Msk                      (0x01UL << SCT_EVSTATEMSK11_STATEMSKn18_Pos)              /*!< SCT EVSTATEMSK11: STATEMSKn18 Mask  */
#define SCT_EVSTATEMSK11_STATEMSKn19_Pos                      19                                                        /*!< SCT EVSTATEMSK11: STATEMSKn19 Position */
#define SCT_EVSTATEMSK11_STATEMSKn19_Msk                      (0x01UL << SCT_EVSTATEMSK11_STATEMSKn19_Pos)              /*!< SCT EVSTATEMSK11: STATEMSKn19 Mask  */
#define SCT_EVSTATEMSK11_STATEMSKn20_Pos                      20                                                        /*!< SCT EVSTATEMSK11: STATEMSKn20 Position */
#define SCT_EVSTATEMSK11_STATEMSKn20_Msk                      (0x01UL << SCT_EVSTATEMSK11_STATEMSKn20_Pos)              /*!< SCT EVSTATEMSK11: STATEMSKn20 Mask  */
#define SCT_EVSTATEMSK11_STATEMSKn21_Pos                      21                                                        /*!< SCT EVSTATEMSK11: STATEMSKn21 Position */
#define SCT_EVSTATEMSK11_STATEMSKn21_Msk                      (0x01UL << SCT_EVSTATEMSK11_STATEMSKn21_Pos)              /*!< SCT EVSTATEMSK11: STATEMSKn21 Mask  */
#define SCT_EVSTATEMSK11_STATEMSKn22_Pos                      22                                                        /*!< SCT EVSTATEMSK11: STATEMSKn22 Position */
#define SCT_EVSTATEMSK11_STATEMSKn22_Msk                      (0x01UL << SCT_EVSTATEMSK11_STATEMSKn22_Pos)              /*!< SCT EVSTATEMSK11: STATEMSKn22 Mask  */
#define SCT_EVSTATEMSK11_STATEMSKn23_Pos                      23                                                        /*!< SCT EVSTATEMSK11: STATEMSKn23 Position */
#define SCT_EVSTATEMSK11_STATEMSKn23_Msk                      (0x01UL << SCT_EVSTATEMSK11_STATEMSKn23_Pos)              /*!< SCT EVSTATEMSK11: STATEMSKn23 Mask  */
#define SCT_EVSTATEMSK11_STATEMSKn24_Pos                      24                                                        /*!< SCT EVSTATEMSK11: STATEMSKn24 Position */
#define SCT_EVSTATEMSK11_STATEMSKn24_Msk                      (0x01UL << SCT_EVSTATEMSK11_STATEMSKn24_Pos)              /*!< SCT EVSTATEMSK11: STATEMSKn24 Mask  */
#define SCT_EVSTATEMSK11_STATEMSKn25_Pos                      25                                                        /*!< SCT EVSTATEMSK11: STATEMSKn25 Position */
#define SCT_EVSTATEMSK11_STATEMSKn25_Msk                      (0x01UL << SCT_EVSTATEMSK11_STATEMSKn25_Pos)              /*!< SCT EVSTATEMSK11: STATEMSKn25 Mask  */
#define SCT_EVSTATEMSK11_STATEMSKn26_Pos                      26                                                        /*!< SCT EVSTATEMSK11: STATEMSKn26 Position */
#define SCT_EVSTATEMSK11_STATEMSKn26_Msk                      (0x01UL << SCT_EVSTATEMSK11_STATEMSKn26_Pos)              /*!< SCT EVSTATEMSK11: STATEMSKn26 Mask  */
#define SCT_EVSTATEMSK11_STATEMSKn27_Pos                      27                                                        /*!< SCT EVSTATEMSK11: STATEMSKn27 Position */
#define SCT_EVSTATEMSK11_STATEMSKn27_Msk                      (0x01UL << SCT_EVSTATEMSK11_STATEMSKn27_Pos)              /*!< SCT EVSTATEMSK11: STATEMSKn27 Mask  */
#define SCT_EVSTATEMSK11_STATEMSKn28_Pos                      28                                                        /*!< SCT EVSTATEMSK11: STATEMSKn28 Position */
#define SCT_EVSTATEMSK11_STATEMSKn28_Msk                      (0x01UL << SCT_EVSTATEMSK11_STATEMSKn28_Pos)              /*!< SCT EVSTATEMSK11: STATEMSKn28 Mask  */
#define SCT_EVSTATEMSK11_STATEMSKn29_Pos                      29                                                        /*!< SCT EVSTATEMSK11: STATEMSKn29 Position */
#define SCT_EVSTATEMSK11_STATEMSKn29_Msk                      (0x01UL << SCT_EVSTATEMSK11_STATEMSKn29_Pos)              /*!< SCT EVSTATEMSK11: STATEMSKn29 Mask  */
#define SCT_EVSTATEMSK11_STATEMSKn30_Pos                      30                                                        /*!< SCT EVSTATEMSK11: STATEMSKn30 Position */
#define SCT_EVSTATEMSK11_STATEMSKn30_Msk                      (0x01UL << SCT_EVSTATEMSK11_STATEMSKn30_Pos)              /*!< SCT EVSTATEMSK11: STATEMSKn30 Mask  */
#define SCT_EVSTATEMSK11_STATEMSKn31_Pos                      31                                                        /*!< SCT EVSTATEMSK11: STATEMSKn31 Position */
#define SCT_EVSTATEMSK11_STATEMSKn31_Msk                      (0x01UL << SCT_EVSTATEMSK11_STATEMSKn31_Pos)              /*!< SCT EVSTATEMSK11: STATEMSKn31 Mask  */

// --------------------------------------  SCT_EVCTRL11  ------------------------------------------
#define SCT_EVCTRL11_MATCHSEL_Pos                             0                                                         /*!< SCT EVCTRL11: MATCHSEL Position     */
#define SCT_EVCTRL11_MATCHSEL_Msk                             (0x0fUL << SCT_EVCTRL11_MATCHSEL_Pos)                     /*!< SCT EVCTRL11: MATCHSEL Mask         */
#define SCT_EVCTRL11_HEVENT_Pos                               4                                                         /*!< SCT EVCTRL11: HEVENT Position       */
#define SCT_EVCTRL11_HEVENT_Msk                               (0x01UL << SCT_EVCTRL11_HEVENT_Pos)                       /*!< SCT EVCTRL11: HEVENT Mask           */
#define SCT_EVCTRL11_OUTSEL_Pos                               5                                                         /*!< SCT EVCTRL11: OUTSEL Position       */
#define SCT_EVCTRL11_OUTSEL_Msk                               (0x01UL << SCT_EVCTRL11_OUTSEL_Pos)                       /*!< SCT EVCTRL11: OUTSEL Mask           */
#define SCT_EVCTRL11_IOSEL_Pos                                6                                                         /*!< SCT EVCTRL11: IOSEL Position        */
#define SCT_EVCTRL11_IOSEL_Msk                                (0x0fUL << SCT_EVCTRL11_IOSEL_Pos)                        /*!< SCT EVCTRL11: IOSEL Mask            */
#define SCT_EVCTRL11_IOCOND_Pos                               10                                                        /*!< SCT EVCTRL11: IOCOND Position       */
#define SCT_EVCTRL11_IOCOND_Msk                               (0x03UL << SCT_EVCTRL11_IOCOND_Pos)                       /*!< SCT EVCTRL11: IOCOND Mask           */
#define SCT_EVCTRL11_COMBMODE_Pos                             12                                                        /*!< SCT EVCTRL11: COMBMODE Position     */
#define SCT_EVCTRL11_COMBMODE_Msk                             (0x03UL << SCT_EVCTRL11_COMBMODE_Pos)                     /*!< SCT EVCTRL11: COMBMODE Mask         */
#define SCT_EVCTRL11_STATELD_Pos                              14                                                        /*!< SCT EVCTRL11: STATELD Position      */
#define SCT_EVCTRL11_STATELD_Msk                              (0x01UL << SCT_EVCTRL11_STATELD_Pos)                      /*!< SCT EVCTRL11: STATELD Mask          */
#define SCT_EVCTRL11_STATEV_Pos                               15                                                        /*!< SCT EVCTRL11: STATEV Position       */
#define SCT_EVCTRL11_STATEV_Msk                               (0x1fUL << SCT_EVCTRL11_STATEV_Pos)                       /*!< SCT EVCTRL11: STATEV Mask           */

// ------------------------------------  SCT_EVSTATEMSK12  ----------------------------------------
#define SCT_EVSTATEMSK12_STATEMSKn0_Pos                       0                                                         /*!< SCT EVSTATEMSK12: STATEMSKn0 Position */
#define SCT_EVSTATEMSK12_STATEMSKn0_Msk                       (0x01UL << SCT_EVSTATEMSK12_STATEMSKn0_Pos)               /*!< SCT EVSTATEMSK12: STATEMSKn0 Mask   */
#define SCT_EVSTATEMSK12_STATEMSKn1_Pos                       1                                                         /*!< SCT EVSTATEMSK12: STATEMSKn1 Position */
#define SCT_EVSTATEMSK12_STATEMSKn1_Msk                       (0x01UL << SCT_EVSTATEMSK12_STATEMSKn1_Pos)               /*!< SCT EVSTATEMSK12: STATEMSKn1 Mask   */
#define SCT_EVSTATEMSK12_STATEMSKn2_Pos                       2                                                         /*!< SCT EVSTATEMSK12: STATEMSKn2 Position */
#define SCT_EVSTATEMSK12_STATEMSKn2_Msk                       (0x01UL << SCT_EVSTATEMSK12_STATEMSKn2_Pos)               /*!< SCT EVSTATEMSK12: STATEMSKn2 Mask   */
#define SCT_EVSTATEMSK12_STATEMSKn3_Pos                       3                                                         /*!< SCT EVSTATEMSK12: STATEMSKn3 Position */
#define SCT_EVSTATEMSK12_STATEMSKn3_Msk                       (0x01UL << SCT_EVSTATEMSK12_STATEMSKn3_Pos)               /*!< SCT EVSTATEMSK12: STATEMSKn3 Mask   */
#define SCT_EVSTATEMSK12_STATEMSKn4_Pos                       4                                                         /*!< SCT EVSTATEMSK12: STATEMSKn4 Position */
#define SCT_EVSTATEMSK12_STATEMSKn4_Msk                       (0x01UL << SCT_EVSTATEMSK12_STATEMSKn4_Pos)               /*!< SCT EVSTATEMSK12: STATEMSKn4 Mask   */
#define SCT_EVSTATEMSK12_STATEMSKn5_Pos                       5                                                         /*!< SCT EVSTATEMSK12: STATEMSKn5 Position */
#define SCT_EVSTATEMSK12_STATEMSKn5_Msk                       (0x01UL << SCT_EVSTATEMSK12_STATEMSKn5_Pos)               /*!< SCT EVSTATEMSK12: STATEMSKn5 Mask   */
#define SCT_EVSTATEMSK12_STATEMSKn6_Pos                       6                                                         /*!< SCT EVSTATEMSK12: STATEMSKn6 Position */
#define SCT_EVSTATEMSK12_STATEMSKn6_Msk                       (0x01UL << SCT_EVSTATEMSK12_STATEMSKn6_Pos)               /*!< SCT EVSTATEMSK12: STATEMSKn6 Mask   */
#define SCT_EVSTATEMSK12_STATEMSKn7_Pos                       7                                                         /*!< SCT EVSTATEMSK12: STATEMSKn7 Position */
#define SCT_EVSTATEMSK12_STATEMSKn7_Msk                       (0x01UL << SCT_EVSTATEMSK12_STATEMSKn7_Pos)               /*!< SCT EVSTATEMSK12: STATEMSKn7 Mask   */
#define SCT_EVSTATEMSK12_STATEMSKn8_Pos                       8                                                         /*!< SCT EVSTATEMSK12: STATEMSKn8 Position */
#define SCT_EVSTATEMSK12_STATEMSKn8_Msk                       (0x01UL << SCT_EVSTATEMSK12_STATEMSKn8_Pos)               /*!< SCT EVSTATEMSK12: STATEMSKn8 Mask   */
#define SCT_EVSTATEMSK12_STATEMSKn9_Pos                       9                                                         /*!< SCT EVSTATEMSK12: STATEMSKn9 Position */
#define SCT_EVSTATEMSK12_STATEMSKn9_Msk                       (0x01UL << SCT_EVSTATEMSK12_STATEMSKn9_Pos)               /*!< SCT EVSTATEMSK12: STATEMSKn9 Mask   */
#define SCT_EVSTATEMSK12_STATEMSKn10_Pos                      10                                                        /*!< SCT EVSTATEMSK12: STATEMSKn10 Position */
#define SCT_EVSTATEMSK12_STATEMSKn10_Msk                      (0x01UL << SCT_EVSTATEMSK12_STATEMSKn10_Pos)              /*!< SCT EVSTATEMSK12: STATEMSKn10 Mask  */
#define SCT_EVSTATEMSK12_STATEMSKn11_Pos                      11                                                        /*!< SCT EVSTATEMSK12: STATEMSKn11 Position */
#define SCT_EVSTATEMSK12_STATEMSKn11_Msk                      (0x01UL << SCT_EVSTATEMSK12_STATEMSKn11_Pos)              /*!< SCT EVSTATEMSK12: STATEMSKn11 Mask  */
#define SCT_EVSTATEMSK12_STATEMSKn12_Pos                      12                                                        /*!< SCT EVSTATEMSK12: STATEMSKn12 Position */
#define SCT_EVSTATEMSK12_STATEMSKn12_Msk                      (0x01UL << SCT_EVSTATEMSK12_STATEMSKn12_Pos)              /*!< SCT EVSTATEMSK12: STATEMSKn12 Mask  */
#define SCT_EVSTATEMSK12_STATEMSKn13_Pos                      13                                                        /*!< SCT EVSTATEMSK12: STATEMSKn13 Position */
#define SCT_EVSTATEMSK12_STATEMSKn13_Msk                      (0x01UL << SCT_EVSTATEMSK12_STATEMSKn13_Pos)              /*!< SCT EVSTATEMSK12: STATEMSKn13 Mask  */
#define SCT_EVSTATEMSK12_STATEMSKn14_Pos                      14                                                        /*!< SCT EVSTATEMSK12: STATEMSKn14 Position */
#define SCT_EVSTATEMSK12_STATEMSKn14_Msk                      (0x01UL << SCT_EVSTATEMSK12_STATEMSKn14_Pos)              /*!< SCT EVSTATEMSK12: STATEMSKn14 Mask  */
#define SCT_EVSTATEMSK12_STATEMSKn15_Pos                      15                                                        /*!< SCT EVSTATEMSK12: STATEMSKn15 Position */
#define SCT_EVSTATEMSK12_STATEMSKn15_Msk                      (0x01UL << SCT_EVSTATEMSK12_STATEMSKn15_Pos)              /*!< SCT EVSTATEMSK12: STATEMSKn15 Mask  */
#define SCT_EVSTATEMSK12_STATEMSKn16_Pos                      16                                                        /*!< SCT EVSTATEMSK12: STATEMSKn16 Position */
#define SCT_EVSTATEMSK12_STATEMSKn16_Msk                      (0x01UL << SCT_EVSTATEMSK12_STATEMSKn16_Pos)              /*!< SCT EVSTATEMSK12: STATEMSKn16 Mask  */
#define SCT_EVSTATEMSK12_STATEMSKn17_Pos                      17                                                        /*!< SCT EVSTATEMSK12: STATEMSKn17 Position */
#define SCT_EVSTATEMSK12_STATEMSKn17_Msk                      (0x01UL << SCT_EVSTATEMSK12_STATEMSKn17_Pos)              /*!< SCT EVSTATEMSK12: STATEMSKn17 Mask  */
#define SCT_EVSTATEMSK12_STATEMSKn18_Pos                      18                                                        /*!< SCT EVSTATEMSK12: STATEMSKn18 Position */
#define SCT_EVSTATEMSK12_STATEMSKn18_Msk                      (0x01UL << SCT_EVSTATEMSK12_STATEMSKn18_Pos)              /*!< SCT EVSTATEMSK12: STATEMSKn18 Mask  */
#define SCT_EVSTATEMSK12_STATEMSKn19_Pos                      19                                                        /*!< SCT EVSTATEMSK12: STATEMSKn19 Position */
#define SCT_EVSTATEMSK12_STATEMSKn19_Msk                      (0x01UL << SCT_EVSTATEMSK12_STATEMSKn19_Pos)              /*!< SCT EVSTATEMSK12: STATEMSKn19 Mask  */
#define SCT_EVSTATEMSK12_STATEMSKn20_Pos                      20                                                        /*!< SCT EVSTATEMSK12: STATEMSKn20 Position */
#define SCT_EVSTATEMSK12_STATEMSKn20_Msk                      (0x01UL << SCT_EVSTATEMSK12_STATEMSKn20_Pos)              /*!< SCT EVSTATEMSK12: STATEMSKn20 Mask  */
#define SCT_EVSTATEMSK12_STATEMSKn21_Pos                      21                                                        /*!< SCT EVSTATEMSK12: STATEMSKn21 Position */
#define SCT_EVSTATEMSK12_STATEMSKn21_Msk                      (0x01UL << SCT_EVSTATEMSK12_STATEMSKn21_Pos)              /*!< SCT EVSTATEMSK12: STATEMSKn21 Mask  */
#define SCT_EVSTATEMSK12_STATEMSKn22_Pos                      22                                                        /*!< SCT EVSTATEMSK12: STATEMSKn22 Position */
#define SCT_EVSTATEMSK12_STATEMSKn22_Msk                      (0x01UL << SCT_EVSTATEMSK12_STATEMSKn22_Pos)              /*!< SCT EVSTATEMSK12: STATEMSKn22 Mask  */
#define SCT_EVSTATEMSK12_STATEMSKn23_Pos                      23                                                        /*!< SCT EVSTATEMSK12: STATEMSKn23 Position */
#define SCT_EVSTATEMSK12_STATEMSKn23_Msk                      (0x01UL << SCT_EVSTATEMSK12_STATEMSKn23_Pos)              /*!< SCT EVSTATEMSK12: STATEMSKn23 Mask  */
#define SCT_EVSTATEMSK12_STATEMSKn24_Pos                      24                                                        /*!< SCT EVSTATEMSK12: STATEMSKn24 Position */
#define SCT_EVSTATEMSK12_STATEMSKn24_Msk                      (0x01UL << SCT_EVSTATEMSK12_STATEMSKn24_Pos)              /*!< SCT EVSTATEMSK12: STATEMSKn24 Mask  */
#define SCT_EVSTATEMSK12_STATEMSKn25_Pos                      25                                                        /*!< SCT EVSTATEMSK12: STATEMSKn25 Position */
#define SCT_EVSTATEMSK12_STATEMSKn25_Msk                      (0x01UL << SCT_EVSTATEMSK12_STATEMSKn25_Pos)              /*!< SCT EVSTATEMSK12: STATEMSKn25 Mask  */
#define SCT_EVSTATEMSK12_STATEMSKn26_Pos                      26                                                        /*!< SCT EVSTATEMSK12: STATEMSKn26 Position */
#define SCT_EVSTATEMSK12_STATEMSKn26_Msk                      (0x01UL << SCT_EVSTATEMSK12_STATEMSKn26_Pos)              /*!< SCT EVSTATEMSK12: STATEMSKn26 Mask  */
#define SCT_EVSTATEMSK12_STATEMSKn27_Pos                      27                                                        /*!< SCT EVSTATEMSK12: STATEMSKn27 Position */
#define SCT_EVSTATEMSK12_STATEMSKn27_Msk                      (0x01UL << SCT_EVSTATEMSK12_STATEMSKn27_Pos)              /*!< SCT EVSTATEMSK12: STATEMSKn27 Mask  */
#define SCT_EVSTATEMSK12_STATEMSKn28_Pos                      28                                                        /*!< SCT EVSTATEMSK12: STATEMSKn28 Position */
#define SCT_EVSTATEMSK12_STATEMSKn28_Msk                      (0x01UL << SCT_EVSTATEMSK12_STATEMSKn28_Pos)              /*!< SCT EVSTATEMSK12: STATEMSKn28 Mask  */
#define SCT_EVSTATEMSK12_STATEMSKn29_Pos                      29                                                        /*!< SCT EVSTATEMSK12: STATEMSKn29 Position */
#define SCT_EVSTATEMSK12_STATEMSKn29_Msk                      (0x01UL << SCT_EVSTATEMSK12_STATEMSKn29_Pos)              /*!< SCT EVSTATEMSK12: STATEMSKn29 Mask  */
#define SCT_EVSTATEMSK12_STATEMSKn30_Pos                      30                                                        /*!< SCT EVSTATEMSK12: STATEMSKn30 Position */
#define SCT_EVSTATEMSK12_STATEMSKn30_Msk                      (0x01UL << SCT_EVSTATEMSK12_STATEMSKn30_Pos)              /*!< SCT EVSTATEMSK12: STATEMSKn30 Mask  */
#define SCT_EVSTATEMSK12_STATEMSKn31_Pos                      31                                                        /*!< SCT EVSTATEMSK12: STATEMSKn31 Position */
#define SCT_EVSTATEMSK12_STATEMSKn31_Msk                      (0x01UL << SCT_EVSTATEMSK12_STATEMSKn31_Pos)              /*!< SCT EVSTATEMSK12: STATEMSKn31 Mask  */

// --------------------------------------  SCT_EVCTRL12  ------------------------------------------
#define SCT_EVCTRL12_MATCHSEL_Pos                             0                                                         /*!< SCT EVCTRL12: MATCHSEL Position     */
#define SCT_EVCTRL12_MATCHSEL_Msk                             (0x0fUL << SCT_EVCTRL12_MATCHSEL_Pos)                     /*!< SCT EVCTRL12: MATCHSEL Mask         */
#define SCT_EVCTRL12_HEVENT_Pos                               4                                                         /*!< SCT EVCTRL12: HEVENT Position       */
#define SCT_EVCTRL12_HEVENT_Msk                               (0x01UL << SCT_EVCTRL12_HEVENT_Pos)                       /*!< SCT EVCTRL12: HEVENT Mask           */
#define SCT_EVCTRL12_OUTSEL_Pos                               5                                                         /*!< SCT EVCTRL12: OUTSEL Position       */
#define SCT_EVCTRL12_OUTSEL_Msk                               (0x01UL << SCT_EVCTRL12_OUTSEL_Pos)                       /*!< SCT EVCTRL12: OUTSEL Mask           */
#define SCT_EVCTRL12_IOSEL_Pos                                6                                                         /*!< SCT EVCTRL12: IOSEL Position        */
#define SCT_EVCTRL12_IOSEL_Msk                                (0x0fUL << SCT_EVCTRL12_IOSEL_Pos)                        /*!< SCT EVCTRL12: IOSEL Mask            */
#define SCT_EVCTRL12_IOCOND_Pos                               10                                                        /*!< SCT EVCTRL12: IOCOND Position       */
#define SCT_EVCTRL12_IOCOND_Msk                               (0x03UL << SCT_EVCTRL12_IOCOND_Pos)                       /*!< SCT EVCTRL12: IOCOND Mask           */
#define SCT_EVCTRL12_COMBMODE_Pos                             12                                                        /*!< SCT EVCTRL12: COMBMODE Position     */
#define SCT_EVCTRL12_COMBMODE_Msk                             (0x03UL << SCT_EVCTRL12_COMBMODE_Pos)                     /*!< SCT EVCTRL12: COMBMODE Mask         */
#define SCT_EVCTRL12_STATELD_Pos                              14                                                        /*!< SCT EVCTRL12: STATELD Position      */
#define SCT_EVCTRL12_STATELD_Msk                              (0x01UL << SCT_EVCTRL12_STATELD_Pos)                      /*!< SCT EVCTRL12: STATELD Mask          */
#define SCT_EVCTRL12_STATEV_Pos                               15                                                        /*!< SCT EVCTRL12: STATEV Position       */
#define SCT_EVCTRL12_STATEV_Msk                               (0x1fUL << SCT_EVCTRL12_STATEV_Pos)                       /*!< SCT EVCTRL12: STATEV Mask           */

// ------------------------------------  SCT_EVSTATEMSK13  ----------------------------------------
#define SCT_EVSTATEMSK13_STATEMSKn0_Pos                       0                                                         /*!< SCT EVSTATEMSK13: STATEMSKn0 Position */
#define SCT_EVSTATEMSK13_STATEMSKn0_Msk                       (0x01UL << SCT_EVSTATEMSK13_STATEMSKn0_Pos)               /*!< SCT EVSTATEMSK13: STATEMSKn0 Mask   */
#define SCT_EVSTATEMSK13_STATEMSKn1_Pos                       1                                                         /*!< SCT EVSTATEMSK13: STATEMSKn1 Position */
#define SCT_EVSTATEMSK13_STATEMSKn1_Msk                       (0x01UL << SCT_EVSTATEMSK13_STATEMSKn1_Pos)               /*!< SCT EVSTATEMSK13: STATEMSKn1 Mask   */
#define SCT_EVSTATEMSK13_STATEMSKn2_Pos                       2                                                         /*!< SCT EVSTATEMSK13: STATEMSKn2 Position */
#define SCT_EVSTATEMSK13_STATEMSKn2_Msk                       (0x01UL << SCT_EVSTATEMSK13_STATEMSKn2_Pos)               /*!< SCT EVSTATEMSK13: STATEMSKn2 Mask   */
#define SCT_EVSTATEMSK13_STATEMSKn3_Pos                       3                                                         /*!< SCT EVSTATEMSK13: STATEMSKn3 Position */
#define SCT_EVSTATEMSK13_STATEMSKn3_Msk                       (0x01UL << SCT_EVSTATEMSK13_STATEMSKn3_Pos)               /*!< SCT EVSTATEMSK13: STATEMSKn3 Mask   */
#define SCT_EVSTATEMSK13_STATEMSKn4_Pos                       4                                                         /*!< SCT EVSTATEMSK13: STATEMSKn4 Position */
#define SCT_EVSTATEMSK13_STATEMSKn4_Msk                       (0x01UL << SCT_EVSTATEMSK13_STATEMSKn4_Pos)               /*!< SCT EVSTATEMSK13: STATEMSKn4 Mask   */
#define SCT_EVSTATEMSK13_STATEMSKn5_Pos                       5                                                         /*!< SCT EVSTATEMSK13: STATEMSKn5 Position */
#define SCT_EVSTATEMSK13_STATEMSKn5_Msk                       (0x01UL << SCT_EVSTATEMSK13_STATEMSKn5_Pos)               /*!< SCT EVSTATEMSK13: STATEMSKn5 Mask   */
#define SCT_EVSTATEMSK13_STATEMSKn6_Pos                       6                                                         /*!< SCT EVSTATEMSK13: STATEMSKn6 Position */
#define SCT_EVSTATEMSK13_STATEMSKn6_Msk                       (0x01UL << SCT_EVSTATEMSK13_STATEMSKn6_Pos)               /*!< SCT EVSTATEMSK13: STATEMSKn6 Mask   */
#define SCT_EVSTATEMSK13_STATEMSKn7_Pos                       7                                                         /*!< SCT EVSTATEMSK13: STATEMSKn7 Position */
#define SCT_EVSTATEMSK13_STATEMSKn7_Msk                       (0x01UL << SCT_EVSTATEMSK13_STATEMSKn7_Pos)               /*!< SCT EVSTATEMSK13: STATEMSKn7 Mask   */
#define SCT_EVSTATEMSK13_STATEMSKn8_Pos                       8                                                         /*!< SCT EVSTATEMSK13: STATEMSKn8 Position */
#define SCT_EVSTATEMSK13_STATEMSKn8_Msk                       (0x01UL << SCT_EVSTATEMSK13_STATEMSKn8_Pos)               /*!< SCT EVSTATEMSK13: STATEMSKn8 Mask   */
#define SCT_EVSTATEMSK13_STATEMSKn9_Pos                       9                                                         /*!< SCT EVSTATEMSK13: STATEMSKn9 Position */
#define SCT_EVSTATEMSK13_STATEMSKn9_Msk                       (0x01UL << SCT_EVSTATEMSK13_STATEMSKn9_Pos)               /*!< SCT EVSTATEMSK13: STATEMSKn9 Mask   */
#define SCT_EVSTATEMSK13_STATEMSKn10_Pos                      10                                                        /*!< SCT EVSTATEMSK13: STATEMSKn10 Position */
#define SCT_EVSTATEMSK13_STATEMSKn10_Msk                      (0x01UL << SCT_EVSTATEMSK13_STATEMSKn10_Pos)              /*!< SCT EVSTATEMSK13: STATEMSKn10 Mask  */
#define SCT_EVSTATEMSK13_STATEMSKn11_Pos                      11                                                        /*!< SCT EVSTATEMSK13: STATEMSKn11 Position */
#define SCT_EVSTATEMSK13_STATEMSKn11_Msk                      (0x01UL << SCT_EVSTATEMSK13_STATEMSKn11_Pos)              /*!< SCT EVSTATEMSK13: STATEMSKn11 Mask  */
#define SCT_EVSTATEMSK13_STATEMSKn12_Pos                      12                                                        /*!< SCT EVSTATEMSK13: STATEMSKn12 Position */
#define SCT_EVSTATEMSK13_STATEMSKn12_Msk                      (0x01UL << SCT_EVSTATEMSK13_STATEMSKn12_Pos)              /*!< SCT EVSTATEMSK13: STATEMSKn12 Mask  */
#define SCT_EVSTATEMSK13_STATEMSKn13_Pos                      13                                                        /*!< SCT EVSTATEMSK13: STATEMSKn13 Position */
#define SCT_EVSTATEMSK13_STATEMSKn13_Msk                      (0x01UL << SCT_EVSTATEMSK13_STATEMSKn13_Pos)              /*!< SCT EVSTATEMSK13: STATEMSKn13 Mask  */
#define SCT_EVSTATEMSK13_STATEMSKn14_Pos                      14                                                        /*!< SCT EVSTATEMSK13: STATEMSKn14 Position */
#define SCT_EVSTATEMSK13_STATEMSKn14_Msk                      (0x01UL << SCT_EVSTATEMSK13_STATEMSKn14_Pos)              /*!< SCT EVSTATEMSK13: STATEMSKn14 Mask  */
#define SCT_EVSTATEMSK13_STATEMSKn15_Pos                      15                                                        /*!< SCT EVSTATEMSK13: STATEMSKn15 Position */
#define SCT_EVSTATEMSK13_STATEMSKn15_Msk                      (0x01UL << SCT_EVSTATEMSK13_STATEMSKn15_Pos)              /*!< SCT EVSTATEMSK13: STATEMSKn15 Mask  */
#define SCT_EVSTATEMSK13_STATEMSKn16_Pos                      16                                                        /*!< SCT EVSTATEMSK13: STATEMSKn16 Position */
#define SCT_EVSTATEMSK13_STATEMSKn16_Msk                      (0x01UL << SCT_EVSTATEMSK13_STATEMSKn16_Pos)              /*!< SCT EVSTATEMSK13: STATEMSKn16 Mask  */
#define SCT_EVSTATEMSK13_STATEMSKn17_Pos                      17                                                        /*!< SCT EVSTATEMSK13: STATEMSKn17 Position */
#define SCT_EVSTATEMSK13_STATEMSKn17_Msk                      (0x01UL << SCT_EVSTATEMSK13_STATEMSKn17_Pos)              /*!< SCT EVSTATEMSK13: STATEMSKn17 Mask  */
#define SCT_EVSTATEMSK13_STATEMSKn18_Pos                      18                                                        /*!< SCT EVSTATEMSK13: STATEMSKn18 Position */
#define SCT_EVSTATEMSK13_STATEMSKn18_Msk                      (0x01UL << SCT_EVSTATEMSK13_STATEMSKn18_Pos)              /*!< SCT EVSTATEMSK13: STATEMSKn18 Mask  */
#define SCT_EVSTATEMSK13_STATEMSKn19_Pos                      19                                                        /*!< SCT EVSTATEMSK13: STATEMSKn19 Position */
#define SCT_EVSTATEMSK13_STATEMSKn19_Msk                      (0x01UL << SCT_EVSTATEMSK13_STATEMSKn19_Pos)              /*!< SCT EVSTATEMSK13: STATEMSKn19 Mask  */
#define SCT_EVSTATEMSK13_STATEMSKn20_Pos                      20                                                        /*!< SCT EVSTATEMSK13: STATEMSKn20 Position */
#define SCT_EVSTATEMSK13_STATEMSKn20_Msk                      (0x01UL << SCT_EVSTATEMSK13_STATEMSKn20_Pos)              /*!< SCT EVSTATEMSK13: STATEMSKn20 Mask  */
#define SCT_EVSTATEMSK13_STATEMSKn21_Pos                      21                                                        /*!< SCT EVSTATEMSK13: STATEMSKn21 Position */
#define SCT_EVSTATEMSK13_STATEMSKn21_Msk                      (0x01UL << SCT_EVSTATEMSK13_STATEMSKn21_Pos)              /*!< SCT EVSTATEMSK13: STATEMSKn21 Mask  */
#define SCT_EVSTATEMSK13_STATEMSKn22_Pos                      22                                                        /*!< SCT EVSTATEMSK13: STATEMSKn22 Position */
#define SCT_EVSTATEMSK13_STATEMSKn22_Msk                      (0x01UL << SCT_EVSTATEMSK13_STATEMSKn22_Pos)              /*!< SCT EVSTATEMSK13: STATEMSKn22 Mask  */
#define SCT_EVSTATEMSK13_STATEMSKn23_Pos                      23                                                        /*!< SCT EVSTATEMSK13: STATEMSKn23 Position */
#define SCT_EVSTATEMSK13_STATEMSKn23_Msk                      (0x01UL << SCT_EVSTATEMSK13_STATEMSKn23_Pos)              /*!< SCT EVSTATEMSK13: STATEMSKn23 Mask  */
#define SCT_EVSTATEMSK13_STATEMSKn24_Pos                      24                                                        /*!< SCT EVSTATEMSK13: STATEMSKn24 Position */
#define SCT_EVSTATEMSK13_STATEMSKn24_Msk                      (0x01UL << SCT_EVSTATEMSK13_STATEMSKn24_Pos)              /*!< SCT EVSTATEMSK13: STATEMSKn24 Mask  */
#define SCT_EVSTATEMSK13_STATEMSKn25_Pos                      25                                                        /*!< SCT EVSTATEMSK13: STATEMSKn25 Position */
#define SCT_EVSTATEMSK13_STATEMSKn25_Msk                      (0x01UL << SCT_EVSTATEMSK13_STATEMSKn25_Pos)              /*!< SCT EVSTATEMSK13: STATEMSKn25 Mask  */
#define SCT_EVSTATEMSK13_STATEMSKn26_Pos                      26                                                        /*!< SCT EVSTATEMSK13: STATEMSKn26 Position */
#define SCT_EVSTATEMSK13_STATEMSKn26_Msk                      (0x01UL << SCT_EVSTATEMSK13_STATEMSKn26_Pos)              /*!< SCT EVSTATEMSK13: STATEMSKn26 Mask  */
#define SCT_EVSTATEMSK13_STATEMSKn27_Pos                      27                                                        /*!< SCT EVSTATEMSK13: STATEMSKn27 Position */
#define SCT_EVSTATEMSK13_STATEMSKn27_Msk                      (0x01UL << SCT_EVSTATEMSK13_STATEMSKn27_Pos)              /*!< SCT EVSTATEMSK13: STATEMSKn27 Mask  */
#define SCT_EVSTATEMSK13_STATEMSKn28_Pos                      28                                                        /*!< SCT EVSTATEMSK13: STATEMSKn28 Position */
#define SCT_EVSTATEMSK13_STATEMSKn28_Msk                      (0x01UL << SCT_EVSTATEMSK13_STATEMSKn28_Pos)              /*!< SCT EVSTATEMSK13: STATEMSKn28 Mask  */
#define SCT_EVSTATEMSK13_STATEMSKn29_Pos                      29                                                        /*!< SCT EVSTATEMSK13: STATEMSKn29 Position */
#define SCT_EVSTATEMSK13_STATEMSKn29_Msk                      (0x01UL << SCT_EVSTATEMSK13_STATEMSKn29_Pos)              /*!< SCT EVSTATEMSK13: STATEMSKn29 Mask  */
#define SCT_EVSTATEMSK13_STATEMSKn30_Pos                      30                                                        /*!< SCT EVSTATEMSK13: STATEMSKn30 Position */
#define SCT_EVSTATEMSK13_STATEMSKn30_Msk                      (0x01UL << SCT_EVSTATEMSK13_STATEMSKn30_Pos)              /*!< SCT EVSTATEMSK13: STATEMSKn30 Mask  */
#define SCT_EVSTATEMSK13_STATEMSKn31_Pos                      31                                                        /*!< SCT EVSTATEMSK13: STATEMSKn31 Position */
#define SCT_EVSTATEMSK13_STATEMSKn31_Msk                      (0x01UL << SCT_EVSTATEMSK13_STATEMSKn31_Pos)              /*!< SCT EVSTATEMSK13: STATEMSKn31 Mask  */

// --------------------------------------  SCT_EVCTRL13  ------------------------------------------
#define SCT_EVCTRL13_MATCHSEL_Pos                             0                                                         /*!< SCT EVCTRL13: MATCHSEL Position     */
#define SCT_EVCTRL13_MATCHSEL_Msk                             (0x0fUL << SCT_EVCTRL13_MATCHSEL_Pos)                     /*!< SCT EVCTRL13: MATCHSEL Mask         */
#define SCT_EVCTRL13_HEVENT_Pos                               4                                                         /*!< SCT EVCTRL13: HEVENT Position       */
#define SCT_EVCTRL13_HEVENT_Msk                               (0x01UL << SCT_EVCTRL13_HEVENT_Pos)                       /*!< SCT EVCTRL13: HEVENT Mask           */
#define SCT_EVCTRL13_OUTSEL_Pos                               5                                                         /*!< SCT EVCTRL13: OUTSEL Position       */
#define SCT_EVCTRL13_OUTSEL_Msk                               (0x01UL << SCT_EVCTRL13_OUTSEL_Pos)                       /*!< SCT EVCTRL13: OUTSEL Mask           */
#define SCT_EVCTRL13_IOSEL_Pos                                6                                                         /*!< SCT EVCTRL13: IOSEL Position        */
#define SCT_EVCTRL13_IOSEL_Msk                                (0x0fUL << SCT_EVCTRL13_IOSEL_Pos)                        /*!< SCT EVCTRL13: IOSEL Mask            */
#define SCT_EVCTRL13_IOCOND_Pos                               10                                                        /*!< SCT EVCTRL13: IOCOND Position       */
#define SCT_EVCTRL13_IOCOND_Msk                               (0x03UL << SCT_EVCTRL13_IOCOND_Pos)                       /*!< SCT EVCTRL13: IOCOND Mask           */
#define SCT_EVCTRL13_COMBMODE_Pos                             12                                                        /*!< SCT EVCTRL13: COMBMODE Position     */
#define SCT_EVCTRL13_COMBMODE_Msk                             (0x03UL << SCT_EVCTRL13_COMBMODE_Pos)                     /*!< SCT EVCTRL13: COMBMODE Mask         */
#define SCT_EVCTRL13_STATELD_Pos                              14                                                        /*!< SCT EVCTRL13: STATELD Position      */
#define SCT_EVCTRL13_STATELD_Msk                              (0x01UL << SCT_EVCTRL13_STATELD_Pos)                      /*!< SCT EVCTRL13: STATELD Mask          */
#define SCT_EVCTRL13_STATEV_Pos                               15                                                        /*!< SCT EVCTRL13: STATEV Position       */
#define SCT_EVCTRL13_STATEV_Msk                               (0x1fUL << SCT_EVCTRL13_STATEV_Pos)                       /*!< SCT EVCTRL13: STATEV Mask           */

// ------------------------------------  SCT_EVSTATEMSK14  ----------------------------------------
#define SCT_EVSTATEMSK14_STATEMSKn0_Pos                       0                                                         /*!< SCT EVSTATEMSK14: STATEMSKn0 Position */
#define SCT_EVSTATEMSK14_STATEMSKn0_Msk                       (0x01UL << SCT_EVSTATEMSK14_STATEMSKn0_Pos)               /*!< SCT EVSTATEMSK14: STATEMSKn0 Mask   */
#define SCT_EVSTATEMSK14_STATEMSKn1_Pos                       1                                                         /*!< SCT EVSTATEMSK14: STATEMSKn1 Position */
#define SCT_EVSTATEMSK14_STATEMSKn1_Msk                       (0x01UL << SCT_EVSTATEMSK14_STATEMSKn1_Pos)               /*!< SCT EVSTATEMSK14: STATEMSKn1 Mask   */
#define SCT_EVSTATEMSK14_STATEMSKn2_Pos                       2                                                         /*!< SCT EVSTATEMSK14: STATEMSKn2 Position */
#define SCT_EVSTATEMSK14_STATEMSKn2_Msk                       (0x01UL << SCT_EVSTATEMSK14_STATEMSKn2_Pos)               /*!< SCT EVSTATEMSK14: STATEMSKn2 Mask   */
#define SCT_EVSTATEMSK14_STATEMSKn3_Pos                       3                                                         /*!< SCT EVSTATEMSK14: STATEMSKn3 Position */
#define SCT_EVSTATEMSK14_STATEMSKn3_Msk                       (0x01UL << SCT_EVSTATEMSK14_STATEMSKn3_Pos)               /*!< SCT EVSTATEMSK14: STATEMSKn3 Mask   */
#define SCT_EVSTATEMSK14_STATEMSKn4_Pos                       4                                                         /*!< SCT EVSTATEMSK14: STATEMSKn4 Position */
#define SCT_EVSTATEMSK14_STATEMSKn4_Msk                       (0x01UL << SCT_EVSTATEMSK14_STATEMSKn4_Pos)               /*!< SCT EVSTATEMSK14: STATEMSKn4 Mask   */
#define SCT_EVSTATEMSK14_STATEMSKn5_Pos                       5                                                         /*!< SCT EVSTATEMSK14: STATEMSKn5 Position */
#define SCT_EVSTATEMSK14_STATEMSKn5_Msk                       (0x01UL << SCT_EVSTATEMSK14_STATEMSKn5_Pos)               /*!< SCT EVSTATEMSK14: STATEMSKn5 Mask   */
#define SCT_EVSTATEMSK14_STATEMSKn6_Pos                       6                                                         /*!< SCT EVSTATEMSK14: STATEMSKn6 Position */
#define SCT_EVSTATEMSK14_STATEMSKn6_Msk                       (0x01UL << SCT_EVSTATEMSK14_STATEMSKn6_Pos)               /*!< SCT EVSTATEMSK14: STATEMSKn6 Mask   */
#define SCT_EVSTATEMSK14_STATEMSKn7_Pos                       7                                                         /*!< SCT EVSTATEMSK14: STATEMSKn7 Position */
#define SCT_EVSTATEMSK14_STATEMSKn7_Msk                       (0x01UL << SCT_EVSTATEMSK14_STATEMSKn7_Pos)               /*!< SCT EVSTATEMSK14: STATEMSKn7 Mask   */
#define SCT_EVSTATEMSK14_STATEMSKn8_Pos                       8                                                         /*!< SCT EVSTATEMSK14: STATEMSKn8 Position */
#define SCT_EVSTATEMSK14_STATEMSKn8_Msk                       (0x01UL << SCT_EVSTATEMSK14_STATEMSKn8_Pos)               /*!< SCT EVSTATEMSK14: STATEMSKn8 Mask   */
#define SCT_EVSTATEMSK14_STATEMSKn9_Pos                       9                                                         /*!< SCT EVSTATEMSK14: STATEMSKn9 Position */
#define SCT_EVSTATEMSK14_STATEMSKn9_Msk                       (0x01UL << SCT_EVSTATEMSK14_STATEMSKn9_Pos)               /*!< SCT EVSTATEMSK14: STATEMSKn9 Mask   */
#define SCT_EVSTATEMSK14_STATEMSKn10_Pos                      10                                                        /*!< SCT EVSTATEMSK14: STATEMSKn10 Position */
#define SCT_EVSTATEMSK14_STATEMSKn10_Msk                      (0x01UL << SCT_EVSTATEMSK14_STATEMSKn10_Pos)              /*!< SCT EVSTATEMSK14: STATEMSKn10 Mask  */
#define SCT_EVSTATEMSK14_STATEMSKn11_Pos                      11                                                        /*!< SCT EVSTATEMSK14: STATEMSKn11 Position */
#define SCT_EVSTATEMSK14_STATEMSKn11_Msk                      (0x01UL << SCT_EVSTATEMSK14_STATEMSKn11_Pos)              /*!< SCT EVSTATEMSK14: STATEMSKn11 Mask  */
#define SCT_EVSTATEMSK14_STATEMSKn12_Pos                      12                                                        /*!< SCT EVSTATEMSK14: STATEMSKn12 Position */
#define SCT_EVSTATEMSK14_STATEMSKn12_Msk                      (0x01UL << SCT_EVSTATEMSK14_STATEMSKn12_Pos)              /*!< SCT EVSTATEMSK14: STATEMSKn12 Mask  */
#define SCT_EVSTATEMSK14_STATEMSKn13_Pos                      13                                                        /*!< SCT EVSTATEMSK14: STATEMSKn13 Position */
#define SCT_EVSTATEMSK14_STATEMSKn13_Msk                      (0x01UL << SCT_EVSTATEMSK14_STATEMSKn13_Pos)              /*!< SCT EVSTATEMSK14: STATEMSKn13 Mask  */
#define SCT_EVSTATEMSK14_STATEMSKn14_Pos                      14                                                        /*!< SCT EVSTATEMSK14: STATEMSKn14 Position */
#define SCT_EVSTATEMSK14_STATEMSKn14_Msk                      (0x01UL << SCT_EVSTATEMSK14_STATEMSKn14_Pos)              /*!< SCT EVSTATEMSK14: STATEMSKn14 Mask  */
#define SCT_EVSTATEMSK14_STATEMSKn15_Pos                      15                                                        /*!< SCT EVSTATEMSK14: STATEMSKn15 Position */
#define SCT_EVSTATEMSK14_STATEMSKn15_Msk                      (0x01UL << SCT_EVSTATEMSK14_STATEMSKn15_Pos)              /*!< SCT EVSTATEMSK14: STATEMSKn15 Mask  */
#define SCT_EVSTATEMSK14_STATEMSKn16_Pos                      16                                                        /*!< SCT EVSTATEMSK14: STATEMSKn16 Position */
#define SCT_EVSTATEMSK14_STATEMSKn16_Msk                      (0x01UL << SCT_EVSTATEMSK14_STATEMSKn16_Pos)              /*!< SCT EVSTATEMSK14: STATEMSKn16 Mask  */
#define SCT_EVSTATEMSK14_STATEMSKn17_Pos                      17                                                        /*!< SCT EVSTATEMSK14: STATEMSKn17 Position */
#define SCT_EVSTATEMSK14_STATEMSKn17_Msk                      (0x01UL << SCT_EVSTATEMSK14_STATEMSKn17_Pos)              /*!< SCT EVSTATEMSK14: STATEMSKn17 Mask  */
#define SCT_EVSTATEMSK14_STATEMSKn18_Pos                      18                                                        /*!< SCT EVSTATEMSK14: STATEMSKn18 Position */
#define SCT_EVSTATEMSK14_STATEMSKn18_Msk                      (0x01UL << SCT_EVSTATEMSK14_STATEMSKn18_Pos)              /*!< SCT EVSTATEMSK14: STATEMSKn18 Mask  */
#define SCT_EVSTATEMSK14_STATEMSKn19_Pos                      19                                                        /*!< SCT EVSTATEMSK14: STATEMSKn19 Position */
#define SCT_EVSTATEMSK14_STATEMSKn19_Msk                      (0x01UL << SCT_EVSTATEMSK14_STATEMSKn19_Pos)              /*!< SCT EVSTATEMSK14: STATEMSKn19 Mask  */
#define SCT_EVSTATEMSK14_STATEMSKn20_Pos                      20                                                        /*!< SCT EVSTATEMSK14: STATEMSKn20 Position */
#define SCT_EVSTATEMSK14_STATEMSKn20_Msk                      (0x01UL << SCT_EVSTATEMSK14_STATEMSKn20_Pos)              /*!< SCT EVSTATEMSK14: STATEMSKn20 Mask  */
#define SCT_EVSTATEMSK14_STATEMSKn21_Pos                      21                                                        /*!< SCT EVSTATEMSK14: STATEMSKn21 Position */
#define SCT_EVSTATEMSK14_STATEMSKn21_Msk                      (0x01UL << SCT_EVSTATEMSK14_STATEMSKn21_Pos)              /*!< SCT EVSTATEMSK14: STATEMSKn21 Mask  */
#define SCT_EVSTATEMSK14_STATEMSKn22_Pos                      22                                                        /*!< SCT EVSTATEMSK14: STATEMSKn22 Position */
#define SCT_EVSTATEMSK14_STATEMSKn22_Msk                      (0x01UL << SCT_EVSTATEMSK14_STATEMSKn22_Pos)              /*!< SCT EVSTATEMSK14: STATEMSKn22 Mask  */
#define SCT_EVSTATEMSK14_STATEMSKn23_Pos                      23                                                        /*!< SCT EVSTATEMSK14: STATEMSKn23 Position */
#define SCT_EVSTATEMSK14_STATEMSKn23_Msk                      (0x01UL << SCT_EVSTATEMSK14_STATEMSKn23_Pos)              /*!< SCT EVSTATEMSK14: STATEMSKn23 Mask  */
#define SCT_EVSTATEMSK14_STATEMSKn24_Pos                      24                                                        /*!< SCT EVSTATEMSK14: STATEMSKn24 Position */
#define SCT_EVSTATEMSK14_STATEMSKn24_Msk                      (0x01UL << SCT_EVSTATEMSK14_STATEMSKn24_Pos)              /*!< SCT EVSTATEMSK14: STATEMSKn24 Mask  */
#define SCT_EVSTATEMSK14_STATEMSKn25_Pos                      25                                                        /*!< SCT EVSTATEMSK14: STATEMSKn25 Position */
#define SCT_EVSTATEMSK14_STATEMSKn25_Msk                      (0x01UL << SCT_EVSTATEMSK14_STATEMSKn25_Pos)              /*!< SCT EVSTATEMSK14: STATEMSKn25 Mask  */
#define SCT_EVSTATEMSK14_STATEMSKn26_Pos                      26                                                        /*!< SCT EVSTATEMSK14: STATEMSKn26 Position */
#define SCT_EVSTATEMSK14_STATEMSKn26_Msk                      (0x01UL << SCT_EVSTATEMSK14_STATEMSKn26_Pos)              /*!< SCT EVSTATEMSK14: STATEMSKn26 Mask  */
#define SCT_EVSTATEMSK14_STATEMSKn27_Pos                      27                                                        /*!< SCT EVSTATEMSK14: STATEMSKn27 Position */
#define SCT_EVSTATEMSK14_STATEMSKn27_Msk                      (0x01UL << SCT_EVSTATEMSK14_STATEMSKn27_Pos)              /*!< SCT EVSTATEMSK14: STATEMSKn27 Mask  */
#define SCT_EVSTATEMSK14_STATEMSKn28_Pos                      28                                                        /*!< SCT EVSTATEMSK14: STATEMSKn28 Position */
#define SCT_EVSTATEMSK14_STATEMSKn28_Msk                      (0x01UL << SCT_EVSTATEMSK14_STATEMSKn28_Pos)              /*!< SCT EVSTATEMSK14: STATEMSKn28 Mask  */
#define SCT_EVSTATEMSK14_STATEMSKn29_Pos                      29                                                        /*!< SCT EVSTATEMSK14: STATEMSKn29 Position */
#define SCT_EVSTATEMSK14_STATEMSKn29_Msk                      (0x01UL << SCT_EVSTATEMSK14_STATEMSKn29_Pos)              /*!< SCT EVSTATEMSK14: STATEMSKn29 Mask  */
#define SCT_EVSTATEMSK14_STATEMSKn30_Pos                      30                                                        /*!< SCT EVSTATEMSK14: STATEMSKn30 Position */
#define SCT_EVSTATEMSK14_STATEMSKn30_Msk                      (0x01UL << SCT_EVSTATEMSK14_STATEMSKn30_Pos)              /*!< SCT EVSTATEMSK14: STATEMSKn30 Mask  */
#define SCT_EVSTATEMSK14_STATEMSKn31_Pos                      31                                                        /*!< SCT EVSTATEMSK14: STATEMSKn31 Position */
#define SCT_EVSTATEMSK14_STATEMSKn31_Msk                      (0x01UL << SCT_EVSTATEMSK14_STATEMSKn31_Pos)              /*!< SCT EVSTATEMSK14: STATEMSKn31 Mask  */

// --------------------------------------  SCT_EVCTRL14  ------------------------------------------
#define SCT_EVCTRL14_MATCHSEL_Pos                             0                                                         /*!< SCT EVCTRL14: MATCHSEL Position     */
#define SCT_EVCTRL14_MATCHSEL_Msk                             (0x0fUL << SCT_EVCTRL14_MATCHSEL_Pos)                     /*!< SCT EVCTRL14: MATCHSEL Mask         */
#define SCT_EVCTRL14_HEVENT_Pos                               4                                                         /*!< SCT EVCTRL14: HEVENT Position       */
#define SCT_EVCTRL14_HEVENT_Msk                               (0x01UL << SCT_EVCTRL14_HEVENT_Pos)                       /*!< SCT EVCTRL14: HEVENT Mask           */
#define SCT_EVCTRL14_OUTSEL_Pos                               5                                                         /*!< SCT EVCTRL14: OUTSEL Position       */
#define SCT_EVCTRL14_OUTSEL_Msk                               (0x01UL << SCT_EVCTRL14_OUTSEL_Pos)                       /*!< SCT EVCTRL14: OUTSEL Mask           */
#define SCT_EVCTRL14_IOSEL_Pos                                6                                                         /*!< SCT EVCTRL14: IOSEL Position        */
#define SCT_EVCTRL14_IOSEL_Msk                                (0x0fUL << SCT_EVCTRL14_IOSEL_Pos)                        /*!< SCT EVCTRL14: IOSEL Mask            */
#define SCT_EVCTRL14_IOCOND_Pos                               10                                                        /*!< SCT EVCTRL14: IOCOND Position       */
#define SCT_EVCTRL14_IOCOND_Msk                               (0x03UL << SCT_EVCTRL14_IOCOND_Pos)                       /*!< SCT EVCTRL14: IOCOND Mask           */
#define SCT_EVCTRL14_COMBMODE_Pos                             12                                                        /*!< SCT EVCTRL14: COMBMODE Position     */
#define SCT_EVCTRL14_COMBMODE_Msk                             (0x03UL << SCT_EVCTRL14_COMBMODE_Pos)                     /*!< SCT EVCTRL14: COMBMODE Mask         */
#define SCT_EVCTRL14_STATELD_Pos                              14                                                        /*!< SCT EVCTRL14: STATELD Position      */
#define SCT_EVCTRL14_STATELD_Msk                              (0x01UL << SCT_EVCTRL14_STATELD_Pos)                      /*!< SCT EVCTRL14: STATELD Mask          */
#define SCT_EVCTRL14_STATEV_Pos                               15                                                        /*!< SCT EVCTRL14: STATEV Position       */
#define SCT_EVCTRL14_STATEV_Msk                               (0x1fUL << SCT_EVCTRL14_STATEV_Pos)                       /*!< SCT EVCTRL14: STATEV Mask           */

// ------------------------------------  SCT_EVSTATEMSK15  ----------------------------------------
#define SCT_EVSTATEMSK15_STATEMSKn0_Pos                       0                                                         /*!< SCT EVSTATEMSK15: STATEMSKn0 Position */
#define SCT_EVSTATEMSK15_STATEMSKn0_Msk                       (0x01UL << SCT_EVSTATEMSK15_STATEMSKn0_Pos)               /*!< SCT EVSTATEMSK15: STATEMSKn0 Mask   */
#define SCT_EVSTATEMSK15_STATEMSKn1_Pos                       1                                                         /*!< SCT EVSTATEMSK15: STATEMSKn1 Position */
#define SCT_EVSTATEMSK15_STATEMSKn1_Msk                       (0x01UL << SCT_EVSTATEMSK15_STATEMSKn1_Pos)               /*!< SCT EVSTATEMSK15: STATEMSKn1 Mask   */
#define SCT_EVSTATEMSK15_STATEMSKn2_Pos                       2                                                         /*!< SCT EVSTATEMSK15: STATEMSKn2 Position */
#define SCT_EVSTATEMSK15_STATEMSKn2_Msk                       (0x01UL << SCT_EVSTATEMSK15_STATEMSKn2_Pos)               /*!< SCT EVSTATEMSK15: STATEMSKn2 Mask   */
#define SCT_EVSTATEMSK15_STATEMSKn3_Pos                       3                                                         /*!< SCT EVSTATEMSK15: STATEMSKn3 Position */
#define SCT_EVSTATEMSK15_STATEMSKn3_Msk                       (0x01UL << SCT_EVSTATEMSK15_STATEMSKn3_Pos)               /*!< SCT EVSTATEMSK15: STATEMSKn3 Mask   */
#define SCT_EVSTATEMSK15_STATEMSKn4_Pos                       4                                                         /*!< SCT EVSTATEMSK15: STATEMSKn4 Position */
#define SCT_EVSTATEMSK15_STATEMSKn4_Msk                       (0x01UL << SCT_EVSTATEMSK15_STATEMSKn4_Pos)               /*!< SCT EVSTATEMSK15: STATEMSKn4 Mask   */
#define SCT_EVSTATEMSK15_STATEMSKn5_Pos                       5                                                         /*!< SCT EVSTATEMSK15: STATEMSKn5 Position */
#define SCT_EVSTATEMSK15_STATEMSKn5_Msk                       (0x01UL << SCT_EVSTATEMSK15_STATEMSKn5_Pos)               /*!< SCT EVSTATEMSK15: STATEMSKn5 Mask   */
#define SCT_EVSTATEMSK15_STATEMSKn6_Pos                       6                                                         /*!< SCT EVSTATEMSK15: STATEMSKn6 Position */
#define SCT_EVSTATEMSK15_STATEMSKn6_Msk                       (0x01UL << SCT_EVSTATEMSK15_STATEMSKn6_Pos)               /*!< SCT EVSTATEMSK15: STATEMSKn6 Mask   */
#define SCT_EVSTATEMSK15_STATEMSKn7_Pos                       7                                                         /*!< SCT EVSTATEMSK15: STATEMSKn7 Position */
#define SCT_EVSTATEMSK15_STATEMSKn7_Msk                       (0x01UL << SCT_EVSTATEMSK15_STATEMSKn7_Pos)               /*!< SCT EVSTATEMSK15: STATEMSKn7 Mask   */
#define SCT_EVSTATEMSK15_STATEMSKn8_Pos                       8                                                         /*!< SCT EVSTATEMSK15: STATEMSKn8 Position */
#define SCT_EVSTATEMSK15_STATEMSKn8_Msk                       (0x01UL << SCT_EVSTATEMSK15_STATEMSKn8_Pos)               /*!< SCT EVSTATEMSK15: STATEMSKn8 Mask   */
#define SCT_EVSTATEMSK15_STATEMSKn9_Pos                       9                                                         /*!< SCT EVSTATEMSK15: STATEMSKn9 Position */
#define SCT_EVSTATEMSK15_STATEMSKn9_Msk                       (0x01UL << SCT_EVSTATEMSK15_STATEMSKn9_Pos)               /*!< SCT EVSTATEMSK15: STATEMSKn9 Mask   */
#define SCT_EVSTATEMSK15_STATEMSKn10_Pos                      10                                                        /*!< SCT EVSTATEMSK15: STATEMSKn10 Position */
#define SCT_EVSTATEMSK15_STATEMSKn10_Msk                      (0x01UL << SCT_EVSTATEMSK15_STATEMSKn10_Pos)              /*!< SCT EVSTATEMSK15: STATEMSKn10 Mask  */
#define SCT_EVSTATEMSK15_STATEMSKn11_Pos                      11                                                        /*!< SCT EVSTATEMSK15: STATEMSKn11 Position */
#define SCT_EVSTATEMSK15_STATEMSKn11_Msk                      (0x01UL << SCT_EVSTATEMSK15_STATEMSKn11_Pos)              /*!< SCT EVSTATEMSK15: STATEMSKn11 Mask  */
#define SCT_EVSTATEMSK15_STATEMSKn12_Pos                      12                                                        /*!< SCT EVSTATEMSK15: STATEMSKn12 Position */
#define SCT_EVSTATEMSK15_STATEMSKn12_Msk                      (0x01UL << SCT_EVSTATEMSK15_STATEMSKn12_Pos)              /*!< SCT EVSTATEMSK15: STATEMSKn12 Mask  */
#define SCT_EVSTATEMSK15_STATEMSKn13_Pos                      13                                                        /*!< SCT EVSTATEMSK15: STATEMSKn13 Position */
#define SCT_EVSTATEMSK15_STATEMSKn13_Msk                      (0x01UL << SCT_EVSTATEMSK15_STATEMSKn13_Pos)              /*!< SCT EVSTATEMSK15: STATEMSKn13 Mask  */
#define SCT_EVSTATEMSK15_STATEMSKn14_Pos                      14                                                        /*!< SCT EVSTATEMSK15: STATEMSKn14 Position */
#define SCT_EVSTATEMSK15_STATEMSKn14_Msk                      (0x01UL << SCT_EVSTATEMSK15_STATEMSKn14_Pos)              /*!< SCT EVSTATEMSK15: STATEMSKn14 Mask  */
#define SCT_EVSTATEMSK15_STATEMSKn15_Pos                      15                                                        /*!< SCT EVSTATEMSK15: STATEMSKn15 Position */
#define SCT_EVSTATEMSK15_STATEMSKn15_Msk                      (0x01UL << SCT_EVSTATEMSK15_STATEMSKn15_Pos)              /*!< SCT EVSTATEMSK15: STATEMSKn15 Mask  */
#define SCT_EVSTATEMSK15_STATEMSKn16_Pos                      16                                                        /*!< SCT EVSTATEMSK15: STATEMSKn16 Position */
#define SCT_EVSTATEMSK15_STATEMSKn16_Msk                      (0x01UL << SCT_EVSTATEMSK15_STATEMSKn16_Pos)              /*!< SCT EVSTATEMSK15: STATEMSKn16 Mask  */
#define SCT_EVSTATEMSK15_STATEMSKn17_Pos                      17                                                        /*!< SCT EVSTATEMSK15: STATEMSKn17 Position */
#define SCT_EVSTATEMSK15_STATEMSKn17_Msk                      (0x01UL << SCT_EVSTATEMSK15_STATEMSKn17_Pos)              /*!< SCT EVSTATEMSK15: STATEMSKn17 Mask  */
#define SCT_EVSTATEMSK15_STATEMSKn18_Pos                      18                                                        /*!< SCT EVSTATEMSK15: STATEMSKn18 Position */
#define SCT_EVSTATEMSK15_STATEMSKn18_Msk                      (0x01UL << SCT_EVSTATEMSK15_STATEMSKn18_Pos)              /*!< SCT EVSTATEMSK15: STATEMSKn18 Mask  */
#define SCT_EVSTATEMSK15_STATEMSKn19_Pos                      19                                                        /*!< SCT EVSTATEMSK15: STATEMSKn19 Position */
#define SCT_EVSTATEMSK15_STATEMSKn19_Msk                      (0x01UL << SCT_EVSTATEMSK15_STATEMSKn19_Pos)              /*!< SCT EVSTATEMSK15: STATEMSKn19 Mask  */
#define SCT_EVSTATEMSK15_STATEMSKn20_Pos                      20                                                        /*!< SCT EVSTATEMSK15: STATEMSKn20 Position */
#define SCT_EVSTATEMSK15_STATEMSKn20_Msk                      (0x01UL << SCT_EVSTATEMSK15_STATEMSKn20_Pos)              /*!< SCT EVSTATEMSK15: STATEMSKn20 Mask  */
#define SCT_EVSTATEMSK15_STATEMSKn21_Pos                      21                                                        /*!< SCT EVSTATEMSK15: STATEMSKn21 Position */
#define SCT_EVSTATEMSK15_STATEMSKn21_Msk                      (0x01UL << SCT_EVSTATEMSK15_STATEMSKn21_Pos)              /*!< SCT EVSTATEMSK15: STATEMSKn21 Mask  */
#define SCT_EVSTATEMSK15_STATEMSKn22_Pos                      22                                                        /*!< SCT EVSTATEMSK15: STATEMSKn22 Position */
#define SCT_EVSTATEMSK15_STATEMSKn22_Msk                      (0x01UL << SCT_EVSTATEMSK15_STATEMSKn22_Pos)              /*!< SCT EVSTATEMSK15: STATEMSKn22 Mask  */
#define SCT_EVSTATEMSK15_STATEMSKn23_Pos                      23                                                        /*!< SCT EVSTATEMSK15: STATEMSKn23 Position */
#define SCT_EVSTATEMSK15_STATEMSKn23_Msk                      (0x01UL << SCT_EVSTATEMSK15_STATEMSKn23_Pos)              /*!< SCT EVSTATEMSK15: STATEMSKn23 Mask  */
#define SCT_EVSTATEMSK15_STATEMSKn24_Pos                      24                                                        /*!< SCT EVSTATEMSK15: STATEMSKn24 Position */
#define SCT_EVSTATEMSK15_STATEMSKn24_Msk                      (0x01UL << SCT_EVSTATEMSK15_STATEMSKn24_Pos)              /*!< SCT EVSTATEMSK15: STATEMSKn24 Mask  */
#define SCT_EVSTATEMSK15_STATEMSKn25_Pos                      25                                                        /*!< SCT EVSTATEMSK15: STATEMSKn25 Position */
#define SCT_EVSTATEMSK15_STATEMSKn25_Msk                      (0x01UL << SCT_EVSTATEMSK15_STATEMSKn25_Pos)              /*!< SCT EVSTATEMSK15: STATEMSKn25 Mask  */
#define SCT_EVSTATEMSK15_STATEMSKn26_Pos                      26                                                        /*!< SCT EVSTATEMSK15: STATEMSKn26 Position */
#define SCT_EVSTATEMSK15_STATEMSKn26_Msk                      (0x01UL << SCT_EVSTATEMSK15_STATEMSKn26_Pos)              /*!< SCT EVSTATEMSK15: STATEMSKn26 Mask  */
#define SCT_EVSTATEMSK15_STATEMSKn27_Pos                      27                                                        /*!< SCT EVSTATEMSK15: STATEMSKn27 Position */
#define SCT_EVSTATEMSK15_STATEMSKn27_Msk                      (0x01UL << SCT_EVSTATEMSK15_STATEMSKn27_Pos)              /*!< SCT EVSTATEMSK15: STATEMSKn27 Mask  */
#define SCT_EVSTATEMSK15_STATEMSKn28_Pos                      28                                                        /*!< SCT EVSTATEMSK15: STATEMSKn28 Position */
#define SCT_EVSTATEMSK15_STATEMSKn28_Msk                      (0x01UL << SCT_EVSTATEMSK15_STATEMSKn28_Pos)              /*!< SCT EVSTATEMSK15: STATEMSKn28 Mask  */
#define SCT_EVSTATEMSK15_STATEMSKn29_Pos                      29                                                        /*!< SCT EVSTATEMSK15: STATEMSKn29 Position */
#define SCT_EVSTATEMSK15_STATEMSKn29_Msk                      (0x01UL << SCT_EVSTATEMSK15_STATEMSKn29_Pos)              /*!< SCT EVSTATEMSK15: STATEMSKn29 Mask  */
#define SCT_EVSTATEMSK15_STATEMSKn30_Pos                      30                                                        /*!< SCT EVSTATEMSK15: STATEMSKn30 Position */
#define SCT_EVSTATEMSK15_STATEMSKn30_Msk                      (0x01UL << SCT_EVSTATEMSK15_STATEMSKn30_Pos)              /*!< SCT EVSTATEMSK15: STATEMSKn30 Mask  */
#define SCT_EVSTATEMSK15_STATEMSKn31_Pos                      31                                                        /*!< SCT EVSTATEMSK15: STATEMSKn31 Position */
#define SCT_EVSTATEMSK15_STATEMSKn31_Msk                      (0x01UL << SCT_EVSTATEMSK15_STATEMSKn31_Pos)              /*!< SCT EVSTATEMSK15: STATEMSKn31 Mask  */

// --------------------------------------  SCT_EVCTRL15  ------------------------------------------
#define SCT_EVCTRL15_MATCHSEL_Pos                             0                                                         /*!< SCT EVCTRL15: MATCHSEL Position     */
#define SCT_EVCTRL15_MATCHSEL_Msk                             (0x0fUL << SCT_EVCTRL15_MATCHSEL_Pos)                     /*!< SCT EVCTRL15: MATCHSEL Mask         */
#define SCT_EVCTRL15_HEVENT_Pos                               4                                                         /*!< SCT EVCTRL15: HEVENT Position       */
#define SCT_EVCTRL15_HEVENT_Msk                               (0x01UL << SCT_EVCTRL15_HEVENT_Pos)                       /*!< SCT EVCTRL15: HEVENT Mask           */
#define SCT_EVCTRL15_OUTSEL_Pos                               5                                                         /*!< SCT EVCTRL15: OUTSEL Position       */
#define SCT_EVCTRL15_OUTSEL_Msk                               (0x01UL << SCT_EVCTRL15_OUTSEL_Pos)                       /*!< SCT EVCTRL15: OUTSEL Mask           */
#define SCT_EVCTRL15_IOSEL_Pos                                6                                                         /*!< SCT EVCTRL15: IOSEL Position        */
#define SCT_EVCTRL15_IOSEL_Msk                                (0x0fUL << SCT_EVCTRL15_IOSEL_Pos)                        /*!< SCT EVCTRL15: IOSEL Mask            */
#define SCT_EVCTRL15_IOCOND_Pos                               10                                                        /*!< SCT EVCTRL15: IOCOND Position       */
#define SCT_EVCTRL15_IOCOND_Msk                               (0x03UL << SCT_EVCTRL15_IOCOND_Pos)                       /*!< SCT EVCTRL15: IOCOND Mask           */
#define SCT_EVCTRL15_COMBMODE_Pos                             12                                                        /*!< SCT EVCTRL15: COMBMODE Position     */
#define SCT_EVCTRL15_COMBMODE_Msk                             (0x03UL << SCT_EVCTRL15_COMBMODE_Pos)                     /*!< SCT EVCTRL15: COMBMODE Mask         */
#define SCT_EVCTRL15_STATELD_Pos                              14                                                        /*!< SCT EVCTRL15: STATELD Position      */
#define SCT_EVCTRL15_STATELD_Msk                              (0x01UL << SCT_EVCTRL15_STATELD_Pos)                      /*!< SCT EVCTRL15: STATELD Mask          */
#define SCT_EVCTRL15_STATEV_Pos                               15                                                        /*!< SCT EVCTRL15: STATEV Position       */
#define SCT_EVCTRL15_STATEV_Msk                               (0x1fUL << SCT_EVCTRL15_STATEV_Pos)                       /*!< SCT EVCTRL15: STATEV Mask           */

// -------------------------------------  SCT_OUTPUTSET0  -----------------------------------------
#define SCT_OUTPUTSET0_SETn0_Pos                              0                                                         /*!< SCT OUTPUTSET0: SETn0 Position      */
#define SCT_OUTPUTSET0_SETn0_Msk                              (0x01UL << SCT_OUTPUTSET0_SETn0_Pos)                      /*!< SCT OUTPUTSET0: SETn0 Mask          */
#define SCT_OUTPUTSET0_SETn1_Pos                              1                                                         /*!< SCT OUTPUTSET0: SETn1 Position      */
#define SCT_OUTPUTSET0_SETn1_Msk                              (0x01UL << SCT_OUTPUTSET0_SETn1_Pos)                      /*!< SCT OUTPUTSET0: SETn1 Mask          */
#define SCT_OUTPUTSET0_SETn2_Pos                              2                                                         /*!< SCT OUTPUTSET0: SETn2 Position      */
#define SCT_OUTPUTSET0_SETn2_Msk                              (0x01UL << SCT_OUTPUTSET0_SETn2_Pos)                      /*!< SCT OUTPUTSET0: SETn2 Mask          */
#define SCT_OUTPUTSET0_SETn3_Pos                              3                                                         /*!< SCT OUTPUTSET0: SETn3 Position      */
#define SCT_OUTPUTSET0_SETn3_Msk                              (0x01UL << SCT_OUTPUTSET0_SETn3_Pos)                      /*!< SCT OUTPUTSET0: SETn3 Mask          */
#define SCT_OUTPUTSET0_SETn4_Pos                              4                                                         /*!< SCT OUTPUTSET0: SETn4 Position      */
#define SCT_OUTPUTSET0_SETn4_Msk                              (0x01UL << SCT_OUTPUTSET0_SETn4_Pos)                      /*!< SCT OUTPUTSET0: SETn4 Mask          */
#define SCT_OUTPUTSET0_SETn5_Pos                              5                                                         /*!< SCT OUTPUTSET0: SETn5 Position      */
#define SCT_OUTPUTSET0_SETn5_Msk                              (0x01UL << SCT_OUTPUTSET0_SETn5_Pos)                      /*!< SCT OUTPUTSET0: SETn5 Mask          */
#define SCT_OUTPUTSET0_SETn6_Pos                              6                                                         /*!< SCT OUTPUTSET0: SETn6 Position      */
#define SCT_OUTPUTSET0_SETn6_Msk                              (0x01UL << SCT_OUTPUTSET0_SETn6_Pos)                      /*!< SCT OUTPUTSET0: SETn6 Mask          */
#define SCT_OUTPUTSET0_SETn7_Pos                              7                                                         /*!< SCT OUTPUTSET0: SETn7 Position      */
#define SCT_OUTPUTSET0_SETn7_Msk                              (0x01UL << SCT_OUTPUTSET0_SETn7_Pos)                      /*!< SCT OUTPUTSET0: SETn7 Mask          */
#define SCT_OUTPUTSET0_SETn8_Pos                              8                                                         /*!< SCT OUTPUTSET0: SETn8 Position      */
#define SCT_OUTPUTSET0_SETn8_Msk                              (0x01UL << SCT_OUTPUTSET0_SETn8_Pos)                      /*!< SCT OUTPUTSET0: SETn8 Mask          */
#define SCT_OUTPUTSET0_SETn9_Pos                              9                                                         /*!< SCT OUTPUTSET0: SETn9 Position      */
#define SCT_OUTPUTSET0_SETn9_Msk                              (0x01UL << SCT_OUTPUTSET0_SETn9_Pos)                      /*!< SCT OUTPUTSET0: SETn9 Mask          */
#define SCT_OUTPUTSET0_SETn10_Pos                             10                                                        /*!< SCT OUTPUTSET0: SETn10 Position     */
#define SCT_OUTPUTSET0_SETn10_Msk                             (0x01UL << SCT_OUTPUTSET0_SETn10_Pos)                     /*!< SCT OUTPUTSET0: SETn10 Mask         */
#define SCT_OUTPUTSET0_SETn11_Pos                             11                                                        /*!< SCT OUTPUTSET0: SETn11 Position     */
#define SCT_OUTPUTSET0_SETn11_Msk                             (0x01UL << SCT_OUTPUTSET0_SETn11_Pos)                     /*!< SCT OUTPUTSET0: SETn11 Mask         */
#define SCT_OUTPUTSET0_SETn12_Pos                             12                                                        /*!< SCT OUTPUTSET0: SETn12 Position     */
#define SCT_OUTPUTSET0_SETn12_Msk                             (0x01UL << SCT_OUTPUTSET0_SETn12_Pos)                     /*!< SCT OUTPUTSET0: SETn12 Mask         */
#define SCT_OUTPUTSET0_SETn13_Pos                             13                                                        /*!< SCT OUTPUTSET0: SETn13 Position     */
#define SCT_OUTPUTSET0_SETn13_Msk                             (0x01UL << SCT_OUTPUTSET0_SETn13_Pos)                     /*!< SCT OUTPUTSET0: SETn13 Mask         */
#define SCT_OUTPUTSET0_SETn14_Pos                             14                                                        /*!< SCT OUTPUTSET0: SETn14 Position     */
#define SCT_OUTPUTSET0_SETn14_Msk                             (0x01UL << SCT_OUTPUTSET0_SETn14_Pos)                     /*!< SCT OUTPUTSET0: SETn14 Mask         */
#define SCT_OUTPUTSET0_SETn15_Pos                             15                                                        /*!< SCT OUTPUTSET0: SETn15 Position     */
#define SCT_OUTPUTSET0_SETn15_Msk                             (0x01UL << SCT_OUTPUTSET0_SETn15_Pos)                     /*!< SCT OUTPUTSET0: SETn15 Mask         */

// -------------------------------------  SCT_OUTPUTCLR0  -----------------------------------------
#define SCT_OUTPUTCLR0_CLRn0_Pos                              0                                                         /*!< SCT OUTPUTCLR0: CLRn0 Position      */
#define SCT_OUTPUTCLR0_CLRn0_Msk                              (0x01UL << SCT_OUTPUTCLR0_CLRn0_Pos)                      /*!< SCT OUTPUTCLR0: CLRn0 Mask          */
#define SCT_OUTPUTCLR0_CLRn1_Pos                              1                                                         /*!< SCT OUTPUTCLR0: CLRn1 Position      */
#define SCT_OUTPUTCLR0_CLRn1_Msk                              (0x01UL << SCT_OUTPUTCLR0_CLRn1_Pos)                      /*!< SCT OUTPUTCLR0: CLRn1 Mask          */
#define SCT_OUTPUTCLR0_CLRn2_Pos                              2                                                         /*!< SCT OUTPUTCLR0: CLRn2 Position      */
#define SCT_OUTPUTCLR0_CLRn2_Msk                              (0x01UL << SCT_OUTPUTCLR0_CLRn2_Pos)                      /*!< SCT OUTPUTCLR0: CLRn2 Mask          */
#define SCT_OUTPUTCLR0_CLRn3_Pos                              3                                                         /*!< SCT OUTPUTCLR0: CLRn3 Position      */
#define SCT_OUTPUTCLR0_CLRn3_Msk                              (0x01UL << SCT_OUTPUTCLR0_CLRn3_Pos)                      /*!< SCT OUTPUTCLR0: CLRn3 Mask          */
#define SCT_OUTPUTCLR0_CLRn4_Pos                              4                                                         /*!< SCT OUTPUTCLR0: CLRn4 Position      */
#define SCT_OUTPUTCLR0_CLRn4_Msk                              (0x01UL << SCT_OUTPUTCLR0_CLRn4_Pos)                      /*!< SCT OUTPUTCLR0: CLRn4 Mask          */
#define SCT_OUTPUTCLR0_CLRn5_Pos                              5                                                         /*!< SCT OUTPUTCLR0: CLRn5 Position      */
#define SCT_OUTPUTCLR0_CLRn5_Msk                              (0x01UL << SCT_OUTPUTCLR0_CLRn5_Pos)                      /*!< SCT OUTPUTCLR0: CLRn5 Mask          */
#define SCT_OUTPUTCLR0_CLRn6_Pos                              6                                                         /*!< SCT OUTPUTCLR0: CLRn6 Position      */
#define SCT_OUTPUTCLR0_CLRn6_Msk                              (0x01UL << SCT_OUTPUTCLR0_CLRn6_Pos)                      /*!< SCT OUTPUTCLR0: CLRn6 Mask          */
#define SCT_OUTPUTCLR0_CLRn7_Pos                              7                                                         /*!< SCT OUTPUTCLR0: CLRn7 Position      */
#define SCT_OUTPUTCLR0_CLRn7_Msk                              (0x01UL << SCT_OUTPUTCLR0_CLRn7_Pos)                      /*!< SCT OUTPUTCLR0: CLRn7 Mask          */
#define SCT_OUTPUTCLR0_CLRn8_Pos                              8                                                         /*!< SCT OUTPUTCLR0: CLRn8 Position      */
#define SCT_OUTPUTCLR0_CLRn8_Msk                              (0x01UL << SCT_OUTPUTCLR0_CLRn8_Pos)                      /*!< SCT OUTPUTCLR0: CLRn8 Mask          */
#define SCT_OUTPUTCLR0_CLRn9_Pos                              9                                                         /*!< SCT OUTPUTCLR0: CLRn9 Position      */
#define SCT_OUTPUTCLR0_CLRn9_Msk                              (0x01UL << SCT_OUTPUTCLR0_CLRn9_Pos)                      /*!< SCT OUTPUTCLR0: CLRn9 Mask          */
#define SCT_OUTPUTCLR0_CLRn10_Pos                             10                                                        /*!< SCT OUTPUTCLR0: CLRn10 Position     */
#define SCT_OUTPUTCLR0_CLRn10_Msk                             (0x01UL << SCT_OUTPUTCLR0_CLRn10_Pos)                     /*!< SCT OUTPUTCLR0: CLRn10 Mask         */
#define SCT_OUTPUTCLR0_CLRn11_Pos                             11                                                        /*!< SCT OUTPUTCLR0: CLRn11 Position     */
#define SCT_OUTPUTCLR0_CLRn11_Msk                             (0x01UL << SCT_OUTPUTCLR0_CLRn11_Pos)                     /*!< SCT OUTPUTCLR0: CLRn11 Mask         */
#define SCT_OUTPUTCLR0_CLRn12_Pos                             12                                                        /*!< SCT OUTPUTCLR0: CLRn12 Position     */
#define SCT_OUTPUTCLR0_CLRn12_Msk                             (0x01UL << SCT_OUTPUTCLR0_CLRn12_Pos)                     /*!< SCT OUTPUTCLR0: CLRn12 Mask         */
#define SCT_OUTPUTCLR0_CLRn13_Pos                             13                                                        /*!< SCT OUTPUTCLR0: CLRn13 Position     */
#define SCT_OUTPUTCLR0_CLRn13_Msk                             (0x01UL << SCT_OUTPUTCLR0_CLRn13_Pos)                     /*!< SCT OUTPUTCLR0: CLRn13 Mask         */
#define SCT_OUTPUTCLR0_CLRn14_Pos                             14                                                        /*!< SCT OUTPUTCLR0: CLRn14 Position     */
#define SCT_OUTPUTCLR0_CLRn14_Msk                             (0x01UL << SCT_OUTPUTCLR0_CLRn14_Pos)                     /*!< SCT OUTPUTCLR0: CLRn14 Mask         */
#define SCT_OUTPUTCLR0_CLRn15_Pos                             15                                                        /*!< SCT OUTPUTCLR0: CLRn15 Position     */
#define SCT_OUTPUTCLR0_CLRn15_Msk                             (0x01UL << SCT_OUTPUTCLR0_CLRn15_Pos)                     /*!< SCT OUTPUTCLR0: CLRn15 Mask         */

// -------------------------------------  SCT_OUTPUTSET1  -----------------------------------------
#define SCT_OUTPUTSET1_SETn0_Pos                              0                                                         /*!< SCT OUTPUTSET1: SETn0 Position      */
#define SCT_OUTPUTSET1_SETn0_Msk                              (0x01UL << SCT_OUTPUTSET1_SETn0_Pos)                      /*!< SCT OUTPUTSET1: SETn0 Mask          */
#define SCT_OUTPUTSET1_SETn1_Pos                              1                                                         /*!< SCT OUTPUTSET1: SETn1 Position      */
#define SCT_OUTPUTSET1_SETn1_Msk                              (0x01UL << SCT_OUTPUTSET1_SETn1_Pos)                      /*!< SCT OUTPUTSET1: SETn1 Mask          */
#define SCT_OUTPUTSET1_SETn2_Pos                              2                                                         /*!< SCT OUTPUTSET1: SETn2 Position      */
#define SCT_OUTPUTSET1_SETn2_Msk                              (0x01UL << SCT_OUTPUTSET1_SETn2_Pos)                      /*!< SCT OUTPUTSET1: SETn2 Mask          */
#define SCT_OUTPUTSET1_SETn3_Pos                              3                                                         /*!< SCT OUTPUTSET1: SETn3 Position      */
#define SCT_OUTPUTSET1_SETn3_Msk                              (0x01UL << SCT_OUTPUTSET1_SETn3_Pos)                      /*!< SCT OUTPUTSET1: SETn3 Mask          */
#define SCT_OUTPUTSET1_SETn4_Pos                              4                                                         /*!< SCT OUTPUTSET1: SETn4 Position      */
#define SCT_OUTPUTSET1_SETn4_Msk                              (0x01UL << SCT_OUTPUTSET1_SETn4_Pos)                      /*!< SCT OUTPUTSET1: SETn4 Mask          */
#define SCT_OUTPUTSET1_SETn5_Pos                              5                                                         /*!< SCT OUTPUTSET1: SETn5 Position      */
#define SCT_OUTPUTSET1_SETn5_Msk                              (0x01UL << SCT_OUTPUTSET1_SETn5_Pos)                      /*!< SCT OUTPUTSET1: SETn5 Mask          */
#define SCT_OUTPUTSET1_SETn6_Pos                              6                                                         /*!< SCT OUTPUTSET1: SETn6 Position      */
#define SCT_OUTPUTSET1_SETn6_Msk                              (0x01UL << SCT_OUTPUTSET1_SETn6_Pos)                      /*!< SCT OUTPUTSET1: SETn6 Mask          */
#define SCT_OUTPUTSET1_SETn7_Pos                              7                                                         /*!< SCT OUTPUTSET1: SETn7 Position      */
#define SCT_OUTPUTSET1_SETn7_Msk                              (0x01UL << SCT_OUTPUTSET1_SETn7_Pos)                      /*!< SCT OUTPUTSET1: SETn7 Mask          */
#define SCT_OUTPUTSET1_SETn8_Pos                              8                                                         /*!< SCT OUTPUTSET1: SETn8 Position      */
#define SCT_OUTPUTSET1_SETn8_Msk                              (0x01UL << SCT_OUTPUTSET1_SETn8_Pos)                      /*!< SCT OUTPUTSET1: SETn8 Mask          */
#define SCT_OUTPUTSET1_SETn9_Pos                              9                                                         /*!< SCT OUTPUTSET1: SETn9 Position      */
#define SCT_OUTPUTSET1_SETn9_Msk                              (0x01UL << SCT_OUTPUTSET1_SETn9_Pos)                      /*!< SCT OUTPUTSET1: SETn9 Mask          */
#define SCT_OUTPUTSET1_SETn10_Pos                             10                                                        /*!< SCT OUTPUTSET1: SETn10 Position     */
#define SCT_OUTPUTSET1_SETn10_Msk                             (0x01UL << SCT_OUTPUTSET1_SETn10_Pos)                     /*!< SCT OUTPUTSET1: SETn10 Mask         */
#define SCT_OUTPUTSET1_SETn11_Pos                             11                                                        /*!< SCT OUTPUTSET1: SETn11 Position     */
#define SCT_OUTPUTSET1_SETn11_Msk                             (0x01UL << SCT_OUTPUTSET1_SETn11_Pos)                     /*!< SCT OUTPUTSET1: SETn11 Mask         */
#define SCT_OUTPUTSET1_SETn12_Pos                             12                                                        /*!< SCT OUTPUTSET1: SETn12 Position     */
#define SCT_OUTPUTSET1_SETn12_Msk                             (0x01UL << SCT_OUTPUTSET1_SETn12_Pos)                     /*!< SCT OUTPUTSET1: SETn12 Mask         */
#define SCT_OUTPUTSET1_SETn13_Pos                             13                                                        /*!< SCT OUTPUTSET1: SETn13 Position     */
#define SCT_OUTPUTSET1_SETn13_Msk                             (0x01UL << SCT_OUTPUTSET1_SETn13_Pos)                     /*!< SCT OUTPUTSET1: SETn13 Mask         */
#define SCT_OUTPUTSET1_SETn14_Pos                             14                                                        /*!< SCT OUTPUTSET1: SETn14 Position     */
#define SCT_OUTPUTSET1_SETn14_Msk                             (0x01UL << SCT_OUTPUTSET1_SETn14_Pos)                     /*!< SCT OUTPUTSET1: SETn14 Mask         */
#define SCT_OUTPUTSET1_SETn15_Pos                             15                                                        /*!< SCT OUTPUTSET1: SETn15 Position     */
#define SCT_OUTPUTSET1_SETn15_Msk                             (0x01UL << SCT_OUTPUTSET1_SETn15_Pos)                     /*!< SCT OUTPUTSET1: SETn15 Mask         */

// -------------------------------------  SCT_OUTPUTCLR1  -----------------------------------------
#define SCT_OUTPUTCLR1_CLRn0_Pos                              0                                                         /*!< SCT OUTPUTCLR1: CLRn0 Position      */
#define SCT_OUTPUTCLR1_CLRn0_Msk                              (0x01UL << SCT_OUTPUTCLR1_CLRn0_Pos)                      /*!< SCT OUTPUTCLR1: CLRn0 Mask          */
#define SCT_OUTPUTCLR1_CLRn1_Pos                              1                                                         /*!< SCT OUTPUTCLR1: CLRn1 Position      */
#define SCT_OUTPUTCLR1_CLRn1_Msk                              (0x01UL << SCT_OUTPUTCLR1_CLRn1_Pos)                      /*!< SCT OUTPUTCLR1: CLRn1 Mask          */
#define SCT_OUTPUTCLR1_CLRn2_Pos                              2                                                         /*!< SCT OUTPUTCLR1: CLRn2 Position      */
#define SCT_OUTPUTCLR1_CLRn2_Msk                              (0x01UL << SCT_OUTPUTCLR1_CLRn2_Pos)                      /*!< SCT OUTPUTCLR1: CLRn2 Mask          */
#define SCT_OUTPUTCLR1_CLRn3_Pos                              3                                                         /*!< SCT OUTPUTCLR1: CLRn3 Position      */
#define SCT_OUTPUTCLR1_CLRn3_Msk                              (0x01UL << SCT_OUTPUTCLR1_CLRn3_Pos)                      /*!< SCT OUTPUTCLR1: CLRn3 Mask          */
#define SCT_OUTPUTCLR1_CLRn4_Pos                              4                                                         /*!< SCT OUTPUTCLR1: CLRn4 Position      */
#define SCT_OUTPUTCLR1_CLRn4_Msk                              (0x01UL << SCT_OUTPUTCLR1_CLRn4_Pos)                      /*!< SCT OUTPUTCLR1: CLRn4 Mask          */
#define SCT_OUTPUTCLR1_CLRn5_Pos                              5                                                         /*!< SCT OUTPUTCLR1: CLRn5 Position      */
#define SCT_OUTPUTCLR1_CLRn5_Msk                              (0x01UL << SCT_OUTPUTCLR1_CLRn5_Pos)                      /*!< SCT OUTPUTCLR1: CLRn5 Mask          */
#define SCT_OUTPUTCLR1_CLRn6_Pos                              6                                                         /*!< SCT OUTPUTCLR1: CLRn6 Position      */
#define SCT_OUTPUTCLR1_CLRn6_Msk                              (0x01UL << SCT_OUTPUTCLR1_CLRn6_Pos)                      /*!< SCT OUTPUTCLR1: CLRn6 Mask          */
#define SCT_OUTPUTCLR1_CLRn7_Pos                              7                                                         /*!< SCT OUTPUTCLR1: CLRn7 Position      */
#define SCT_OUTPUTCLR1_CLRn7_Msk                              (0x01UL << SCT_OUTPUTCLR1_CLRn7_Pos)                      /*!< SCT OUTPUTCLR1: CLRn7 Mask          */
#define SCT_OUTPUTCLR1_CLRn8_Pos                              8                                                         /*!< SCT OUTPUTCLR1: CLRn8 Position      */
#define SCT_OUTPUTCLR1_CLRn8_Msk                              (0x01UL << SCT_OUTPUTCLR1_CLRn8_Pos)                      /*!< SCT OUTPUTCLR1: CLRn8 Mask          */
#define SCT_OUTPUTCLR1_CLRn9_Pos                              9                                                         /*!< SCT OUTPUTCLR1: CLRn9 Position      */
#define SCT_OUTPUTCLR1_CLRn9_Msk                              (0x01UL << SCT_OUTPUTCLR1_CLRn9_Pos)                      /*!< SCT OUTPUTCLR1: CLRn9 Mask          */
#define SCT_OUTPUTCLR1_CLRn10_Pos                             10                                                        /*!< SCT OUTPUTCLR1: CLRn10 Position     */
#define SCT_OUTPUTCLR1_CLRn10_Msk                             (0x01UL << SCT_OUTPUTCLR1_CLRn10_Pos)                     /*!< SCT OUTPUTCLR1: CLRn10 Mask         */
#define SCT_OUTPUTCLR1_CLRn11_Pos                             11                                                        /*!< SCT OUTPUTCLR1: CLRn11 Position     */
#define SCT_OUTPUTCLR1_CLRn11_Msk                             (0x01UL << SCT_OUTPUTCLR1_CLRn11_Pos)                     /*!< SCT OUTPUTCLR1: CLRn11 Mask         */
#define SCT_OUTPUTCLR1_CLRn12_Pos                             12                                                        /*!< SCT OUTPUTCLR1: CLRn12 Position     */
#define SCT_OUTPUTCLR1_CLRn12_Msk                             (0x01UL << SCT_OUTPUTCLR1_CLRn12_Pos)                     /*!< SCT OUTPUTCLR1: CLRn12 Mask         */
#define SCT_OUTPUTCLR1_CLRn13_Pos                             13                                                        /*!< SCT OUTPUTCLR1: CLRn13 Position     */
#define SCT_OUTPUTCLR1_CLRn13_Msk                             (0x01UL << SCT_OUTPUTCLR1_CLRn13_Pos)                     /*!< SCT OUTPUTCLR1: CLRn13 Mask         */
#define SCT_OUTPUTCLR1_CLRn14_Pos                             14                                                        /*!< SCT OUTPUTCLR1: CLRn14 Position     */
#define SCT_OUTPUTCLR1_CLRn14_Msk                             (0x01UL << SCT_OUTPUTCLR1_CLRn14_Pos)                     /*!< SCT OUTPUTCLR1: CLRn14 Mask         */
#define SCT_OUTPUTCLR1_CLRn15_Pos                             15                                                        /*!< SCT OUTPUTCLR1: CLRn15 Position     */
#define SCT_OUTPUTCLR1_CLRn15_Msk                             (0x01UL << SCT_OUTPUTCLR1_CLRn15_Pos)                     /*!< SCT OUTPUTCLR1: CLRn15 Mask         */

// -------------------------------------  SCT_OUTPUTSET2  -----------------------------------------
#define SCT_OUTPUTSET2_SETn0_Pos                              0                                                         /*!< SCT OUTPUTSET2: SETn0 Position      */
#define SCT_OUTPUTSET2_SETn0_Msk                              (0x01UL << SCT_OUTPUTSET2_SETn0_Pos)                      /*!< SCT OUTPUTSET2: SETn0 Mask          */
#define SCT_OUTPUTSET2_SETn1_Pos                              1                                                         /*!< SCT OUTPUTSET2: SETn1 Position      */
#define SCT_OUTPUTSET2_SETn1_Msk                              (0x01UL << SCT_OUTPUTSET2_SETn1_Pos)                      /*!< SCT OUTPUTSET2: SETn1 Mask          */
#define SCT_OUTPUTSET2_SETn2_Pos                              2                                                         /*!< SCT OUTPUTSET2: SETn2 Position      */
#define SCT_OUTPUTSET2_SETn2_Msk                              (0x01UL << SCT_OUTPUTSET2_SETn2_Pos)                      /*!< SCT OUTPUTSET2: SETn2 Mask          */
#define SCT_OUTPUTSET2_SETn3_Pos                              3                                                         /*!< SCT OUTPUTSET2: SETn3 Position      */
#define SCT_OUTPUTSET2_SETn3_Msk                              (0x01UL << SCT_OUTPUTSET2_SETn3_Pos)                      /*!< SCT OUTPUTSET2: SETn3 Mask          */
#define SCT_OUTPUTSET2_SETn4_Pos                              4                                                         /*!< SCT OUTPUTSET2: SETn4 Position      */
#define SCT_OUTPUTSET2_SETn4_Msk                              (0x01UL << SCT_OUTPUTSET2_SETn4_Pos)                      /*!< SCT OUTPUTSET2: SETn4 Mask          */
#define SCT_OUTPUTSET2_SETn5_Pos                              5                                                         /*!< SCT OUTPUTSET2: SETn5 Position      */
#define SCT_OUTPUTSET2_SETn5_Msk                              (0x01UL << SCT_OUTPUTSET2_SETn5_Pos)                      /*!< SCT OUTPUTSET2: SETn5 Mask          */
#define SCT_OUTPUTSET2_SETn6_Pos                              6                                                         /*!< SCT OUTPUTSET2: SETn6 Position      */
#define SCT_OUTPUTSET2_SETn6_Msk                              (0x01UL << SCT_OUTPUTSET2_SETn6_Pos)                      /*!< SCT OUTPUTSET2: SETn6 Mask          */
#define SCT_OUTPUTSET2_SETn7_Pos                              7                                                         /*!< SCT OUTPUTSET2: SETn7 Position      */
#define SCT_OUTPUTSET2_SETn7_Msk                              (0x01UL << SCT_OUTPUTSET2_SETn7_Pos)                      /*!< SCT OUTPUTSET2: SETn7 Mask          */
#define SCT_OUTPUTSET2_SETn8_Pos                              8                                                         /*!< SCT OUTPUTSET2: SETn8 Position      */
#define SCT_OUTPUTSET2_SETn8_Msk                              (0x01UL << SCT_OUTPUTSET2_SETn8_Pos)                      /*!< SCT OUTPUTSET2: SETn8 Mask          */
#define SCT_OUTPUTSET2_SETn9_Pos                              9                                                         /*!< SCT OUTPUTSET2: SETn9 Position      */
#define SCT_OUTPUTSET2_SETn9_Msk                              (0x01UL << SCT_OUTPUTSET2_SETn9_Pos)                      /*!< SCT OUTPUTSET2: SETn9 Mask          */
#define SCT_OUTPUTSET2_SETn10_Pos                             10                                                        /*!< SCT OUTPUTSET2: SETn10 Position     */
#define SCT_OUTPUTSET2_SETn10_Msk                             (0x01UL << SCT_OUTPUTSET2_SETn10_Pos)                     /*!< SCT OUTPUTSET2: SETn10 Mask         */
#define SCT_OUTPUTSET2_SETn11_Pos                             11                                                        /*!< SCT OUTPUTSET2: SETn11 Position     */
#define SCT_OUTPUTSET2_SETn11_Msk                             (0x01UL << SCT_OUTPUTSET2_SETn11_Pos)                     /*!< SCT OUTPUTSET2: SETn11 Mask         */
#define SCT_OUTPUTSET2_SETn12_Pos                             12                                                        /*!< SCT OUTPUTSET2: SETn12 Position     */
#define SCT_OUTPUTSET2_SETn12_Msk                             (0x01UL << SCT_OUTPUTSET2_SETn12_Pos)                     /*!< SCT OUTPUTSET2: SETn12 Mask         */
#define SCT_OUTPUTSET2_SETn13_Pos                             13                                                        /*!< SCT OUTPUTSET2: SETn13 Position     */
#define SCT_OUTPUTSET2_SETn13_Msk                             (0x01UL << SCT_OUTPUTSET2_SETn13_Pos)                     /*!< SCT OUTPUTSET2: SETn13 Mask         */
#define SCT_OUTPUTSET2_SETn14_Pos                             14                                                        /*!< SCT OUTPUTSET2: SETn14 Position     */
#define SCT_OUTPUTSET2_SETn14_Msk                             (0x01UL << SCT_OUTPUTSET2_SETn14_Pos)                     /*!< SCT OUTPUTSET2: SETn14 Mask         */
#define SCT_OUTPUTSET2_SETn15_Pos                             15                                                        /*!< SCT OUTPUTSET2: SETn15 Position     */
#define SCT_OUTPUTSET2_SETn15_Msk                             (0x01UL << SCT_OUTPUTSET2_SETn15_Pos)                     /*!< SCT OUTPUTSET2: SETn15 Mask         */

// -------------------------------------  SCT_OUTPUTCLR2  -----------------------------------------
#define SCT_OUTPUTCLR2_CLRn0_Pos                              0                                                         /*!< SCT OUTPUTCLR2: CLRn0 Position      */
#define SCT_OUTPUTCLR2_CLRn0_Msk                              (0x01UL << SCT_OUTPUTCLR2_CLRn0_Pos)                      /*!< SCT OUTPUTCLR2: CLRn0 Mask          */
#define SCT_OUTPUTCLR2_CLRn1_Pos                              1                                                         /*!< SCT OUTPUTCLR2: CLRn1 Position      */
#define SCT_OUTPUTCLR2_CLRn1_Msk                              (0x01UL << SCT_OUTPUTCLR2_CLRn1_Pos)                      /*!< SCT OUTPUTCLR2: CLRn1 Mask          */
#define SCT_OUTPUTCLR2_CLRn2_Pos                              2                                                         /*!< SCT OUTPUTCLR2: CLRn2 Position      */
#define SCT_OUTPUTCLR2_CLRn2_Msk                              (0x01UL << SCT_OUTPUTCLR2_CLRn2_Pos)                      /*!< SCT OUTPUTCLR2: CLRn2 Mask          */
#define SCT_OUTPUTCLR2_CLRn3_Pos                              3                                                         /*!< SCT OUTPUTCLR2: CLRn3 Position      */
#define SCT_OUTPUTCLR2_CLRn3_Msk                              (0x01UL << SCT_OUTPUTCLR2_CLRn3_Pos)                      /*!< SCT OUTPUTCLR2: CLRn3 Mask          */
#define SCT_OUTPUTCLR2_CLRn4_Pos                              4                                                         /*!< SCT OUTPUTCLR2: CLRn4 Position      */
#define SCT_OUTPUTCLR2_CLRn4_Msk                              (0x01UL << SCT_OUTPUTCLR2_CLRn4_Pos)                      /*!< SCT OUTPUTCLR2: CLRn4 Mask          */
#define SCT_OUTPUTCLR2_CLRn5_Pos                              5                                                         /*!< SCT OUTPUTCLR2: CLRn5 Position      */
#define SCT_OUTPUTCLR2_CLRn5_Msk                              (0x01UL << SCT_OUTPUTCLR2_CLRn5_Pos)                      /*!< SCT OUTPUTCLR2: CLRn5 Mask          */
#define SCT_OUTPUTCLR2_CLRn6_Pos                              6                                                         /*!< SCT OUTPUTCLR2: CLRn6 Position      */
#define SCT_OUTPUTCLR2_CLRn6_Msk                              (0x01UL << SCT_OUTPUTCLR2_CLRn6_Pos)                      /*!< SCT OUTPUTCLR2: CLRn6 Mask          */
#define SCT_OUTPUTCLR2_CLRn7_Pos                              7                                                         /*!< SCT OUTPUTCLR2: CLRn7 Position      */
#define SCT_OUTPUTCLR2_CLRn7_Msk                              (0x01UL << SCT_OUTPUTCLR2_CLRn7_Pos)                      /*!< SCT OUTPUTCLR2: CLRn7 Mask          */
#define SCT_OUTPUTCLR2_CLRn8_Pos                              8                                                         /*!< SCT OUTPUTCLR2: CLRn8 Position      */
#define SCT_OUTPUTCLR2_CLRn8_Msk                              (0x01UL << SCT_OUTPUTCLR2_CLRn8_Pos)                      /*!< SCT OUTPUTCLR2: CLRn8 Mask          */
#define SCT_OUTPUTCLR2_CLRn9_Pos                              9                                                         /*!< SCT OUTPUTCLR2: CLRn9 Position      */
#define SCT_OUTPUTCLR2_CLRn9_Msk                              (0x01UL << SCT_OUTPUTCLR2_CLRn9_Pos)                      /*!< SCT OUTPUTCLR2: CLRn9 Mask          */
#define SCT_OUTPUTCLR2_CLRn10_Pos                             10                                                        /*!< SCT OUTPUTCLR2: CLRn10 Position     */
#define SCT_OUTPUTCLR2_CLRn10_Msk                             (0x01UL << SCT_OUTPUTCLR2_CLRn10_Pos)                     /*!< SCT OUTPUTCLR2: CLRn10 Mask         */
#define SCT_OUTPUTCLR2_CLRn11_Pos                             11                                                        /*!< SCT OUTPUTCLR2: CLRn11 Position     */
#define SCT_OUTPUTCLR2_CLRn11_Msk                             (0x01UL << SCT_OUTPUTCLR2_CLRn11_Pos)                     /*!< SCT OUTPUTCLR2: CLRn11 Mask         */
#define SCT_OUTPUTCLR2_CLRn12_Pos                             12                                                        /*!< SCT OUTPUTCLR2: CLRn12 Position     */
#define SCT_OUTPUTCLR2_CLRn12_Msk                             (0x01UL << SCT_OUTPUTCLR2_CLRn12_Pos)                     /*!< SCT OUTPUTCLR2: CLRn12 Mask         */
#define SCT_OUTPUTCLR2_CLRn13_Pos                             13                                                        /*!< SCT OUTPUTCLR2: CLRn13 Position     */
#define SCT_OUTPUTCLR2_CLRn13_Msk                             (0x01UL << SCT_OUTPUTCLR2_CLRn13_Pos)                     /*!< SCT OUTPUTCLR2: CLRn13 Mask         */
#define SCT_OUTPUTCLR2_CLRn14_Pos                             14                                                        /*!< SCT OUTPUTCLR2: CLRn14 Position     */
#define SCT_OUTPUTCLR2_CLRn14_Msk                             (0x01UL << SCT_OUTPUTCLR2_CLRn14_Pos)                     /*!< SCT OUTPUTCLR2: CLRn14 Mask         */
#define SCT_OUTPUTCLR2_CLRn15_Pos                             15                                                        /*!< SCT OUTPUTCLR2: CLRn15 Position     */
#define SCT_OUTPUTCLR2_CLRn15_Msk                             (0x01UL << SCT_OUTPUTCLR2_CLRn15_Pos)                     /*!< SCT OUTPUTCLR2: CLRn15 Mask         */

// -------------------------------------  SCT_OUTPUTSET3  -----------------------------------------
#define SCT_OUTPUTSET3_SETn0_Pos                              0                                                         /*!< SCT OUTPUTSET3: SETn0 Position      */
#define SCT_OUTPUTSET3_SETn0_Msk                              (0x01UL << SCT_OUTPUTSET3_SETn0_Pos)                      /*!< SCT OUTPUTSET3: SETn0 Mask          */
#define SCT_OUTPUTSET3_SETn1_Pos                              1                                                         /*!< SCT OUTPUTSET3: SETn1 Position      */
#define SCT_OUTPUTSET3_SETn1_Msk                              (0x01UL << SCT_OUTPUTSET3_SETn1_Pos)                      /*!< SCT OUTPUTSET3: SETn1 Mask          */
#define SCT_OUTPUTSET3_SETn2_Pos                              2                                                         /*!< SCT OUTPUTSET3: SETn2 Position      */
#define SCT_OUTPUTSET3_SETn2_Msk                              (0x01UL << SCT_OUTPUTSET3_SETn2_Pos)                      /*!< SCT OUTPUTSET3: SETn2 Mask          */
#define SCT_OUTPUTSET3_SETn3_Pos                              3                                                         /*!< SCT OUTPUTSET3: SETn3 Position      */
#define SCT_OUTPUTSET3_SETn3_Msk                              (0x01UL << SCT_OUTPUTSET3_SETn3_Pos)                      /*!< SCT OUTPUTSET3: SETn3 Mask          */
#define SCT_OUTPUTSET3_SETn4_Pos                              4                                                         /*!< SCT OUTPUTSET3: SETn4 Position      */
#define SCT_OUTPUTSET3_SETn4_Msk                              (0x01UL << SCT_OUTPUTSET3_SETn4_Pos)                      /*!< SCT OUTPUTSET3: SETn4 Mask          */
#define SCT_OUTPUTSET3_SETn5_Pos                              5                                                         /*!< SCT OUTPUTSET3: SETn5 Position      */
#define SCT_OUTPUTSET3_SETn5_Msk                              (0x01UL << SCT_OUTPUTSET3_SETn5_Pos)                      /*!< SCT OUTPUTSET3: SETn5 Mask          */
#define SCT_OUTPUTSET3_SETn6_Pos                              6                                                         /*!< SCT OUTPUTSET3: SETn6 Position      */
#define SCT_OUTPUTSET3_SETn6_Msk                              (0x01UL << SCT_OUTPUTSET3_SETn6_Pos)                      /*!< SCT OUTPUTSET3: SETn6 Mask          */
#define SCT_OUTPUTSET3_SETn7_Pos                              7                                                         /*!< SCT OUTPUTSET3: SETn7 Position      */
#define SCT_OUTPUTSET3_SETn7_Msk                              (0x01UL << SCT_OUTPUTSET3_SETn7_Pos)                      /*!< SCT OUTPUTSET3: SETn7 Mask          */
#define SCT_OUTPUTSET3_SETn8_Pos                              8                                                         /*!< SCT OUTPUTSET3: SETn8 Position      */
#define SCT_OUTPUTSET3_SETn8_Msk                              (0x01UL << SCT_OUTPUTSET3_SETn8_Pos)                      /*!< SCT OUTPUTSET3: SETn8 Mask          */
#define SCT_OUTPUTSET3_SETn9_Pos                              9                                                         /*!< SCT OUTPUTSET3: SETn9 Position      */
#define SCT_OUTPUTSET3_SETn9_Msk                              (0x01UL << SCT_OUTPUTSET3_SETn9_Pos)                      /*!< SCT OUTPUTSET3: SETn9 Mask          */
#define SCT_OUTPUTSET3_SETn10_Pos                             10                                                        /*!< SCT OUTPUTSET3: SETn10 Position     */
#define SCT_OUTPUTSET3_SETn10_Msk                             (0x01UL << SCT_OUTPUTSET3_SETn10_Pos)                     /*!< SCT OUTPUTSET3: SETn10 Mask         */
#define SCT_OUTPUTSET3_SETn11_Pos                             11                                                        /*!< SCT OUTPUTSET3: SETn11 Position     */
#define SCT_OUTPUTSET3_SETn11_Msk                             (0x01UL << SCT_OUTPUTSET3_SETn11_Pos)                     /*!< SCT OUTPUTSET3: SETn11 Mask         */
#define SCT_OUTPUTSET3_SETn12_Pos                             12                                                        /*!< SCT OUTPUTSET3: SETn12 Position     */
#define SCT_OUTPUTSET3_SETn12_Msk                             (0x01UL << SCT_OUTPUTSET3_SETn12_Pos)                     /*!< SCT OUTPUTSET3: SETn12 Mask         */
#define SCT_OUTPUTSET3_SETn13_Pos                             13                                                        /*!< SCT OUTPUTSET3: SETn13 Position     */
#define SCT_OUTPUTSET3_SETn13_Msk                             (0x01UL << SCT_OUTPUTSET3_SETn13_Pos)                     /*!< SCT OUTPUTSET3: SETn13 Mask         */
#define SCT_OUTPUTSET3_SETn14_Pos                             14                                                        /*!< SCT OUTPUTSET3: SETn14 Position     */
#define SCT_OUTPUTSET3_SETn14_Msk                             (0x01UL << SCT_OUTPUTSET3_SETn14_Pos)                     /*!< SCT OUTPUTSET3: SETn14 Mask         */
#define SCT_OUTPUTSET3_SETn15_Pos                             15                                                        /*!< SCT OUTPUTSET3: SETn15 Position     */
#define SCT_OUTPUTSET3_SETn15_Msk                             (0x01UL << SCT_OUTPUTSET3_SETn15_Pos)                     /*!< SCT OUTPUTSET3: SETn15 Mask         */

// -------------------------------------  SCT_OUTPUTCLR3  -----------------------------------------
#define SCT_OUTPUTCLR3_CLRn0_Pos                              0                                                         /*!< SCT OUTPUTCLR3: CLRn0 Position      */
#define SCT_OUTPUTCLR3_CLRn0_Msk                              (0x01UL << SCT_OUTPUTCLR3_CLRn0_Pos)                      /*!< SCT OUTPUTCLR3: CLRn0 Mask          */
#define SCT_OUTPUTCLR3_CLRn1_Pos                              1                                                         /*!< SCT OUTPUTCLR3: CLRn1 Position      */
#define SCT_OUTPUTCLR3_CLRn1_Msk                              (0x01UL << SCT_OUTPUTCLR3_CLRn1_Pos)                      /*!< SCT OUTPUTCLR3: CLRn1 Mask          */
#define SCT_OUTPUTCLR3_CLRn2_Pos                              2                                                         /*!< SCT OUTPUTCLR3: CLRn2 Position      */
#define SCT_OUTPUTCLR3_CLRn2_Msk                              (0x01UL << SCT_OUTPUTCLR3_CLRn2_Pos)                      /*!< SCT OUTPUTCLR3: CLRn2 Mask          */
#define SCT_OUTPUTCLR3_CLRn3_Pos                              3                                                         /*!< SCT OUTPUTCLR3: CLRn3 Position      */
#define SCT_OUTPUTCLR3_CLRn3_Msk                              (0x01UL << SCT_OUTPUTCLR3_CLRn3_Pos)                      /*!< SCT OUTPUTCLR3: CLRn3 Mask          */
#define SCT_OUTPUTCLR3_CLRn4_Pos                              4                                                         /*!< SCT OUTPUTCLR3: CLRn4 Position      */
#define SCT_OUTPUTCLR3_CLRn4_Msk                              (0x01UL << SCT_OUTPUTCLR3_CLRn4_Pos)                      /*!< SCT OUTPUTCLR3: CLRn4 Mask          */
#define SCT_OUTPUTCLR3_CLRn5_Pos                              5                                                         /*!< SCT OUTPUTCLR3: CLRn5 Position      */
#define SCT_OUTPUTCLR3_CLRn5_Msk                              (0x01UL << SCT_OUTPUTCLR3_CLRn5_Pos)                      /*!< SCT OUTPUTCLR3: CLRn5 Mask          */
#define SCT_OUTPUTCLR3_CLRn6_Pos                              6                                                         /*!< SCT OUTPUTCLR3: CLRn6 Position      */
#define SCT_OUTPUTCLR3_CLRn6_Msk                              (0x01UL << SCT_OUTPUTCLR3_CLRn6_Pos)                      /*!< SCT OUTPUTCLR3: CLRn6 Mask          */
#define SCT_OUTPUTCLR3_CLRn7_Pos                              7                                                         /*!< SCT OUTPUTCLR3: CLRn7 Position      */
#define SCT_OUTPUTCLR3_CLRn7_Msk                              (0x01UL << SCT_OUTPUTCLR3_CLRn7_Pos)                      /*!< SCT OUTPUTCLR3: CLRn7 Mask          */
#define SCT_OUTPUTCLR3_CLRn8_Pos                              8                                                         /*!< SCT OUTPUTCLR3: CLRn8 Position      */
#define SCT_OUTPUTCLR3_CLRn8_Msk                              (0x01UL << SCT_OUTPUTCLR3_CLRn8_Pos)                      /*!< SCT OUTPUTCLR3: CLRn8 Mask          */
#define SCT_OUTPUTCLR3_CLRn9_Pos                              9                                                         /*!< SCT OUTPUTCLR3: CLRn9 Position      */
#define SCT_OUTPUTCLR3_CLRn9_Msk                              (0x01UL << SCT_OUTPUTCLR3_CLRn9_Pos)                      /*!< SCT OUTPUTCLR3: CLRn9 Mask          */
#define SCT_OUTPUTCLR3_CLRn10_Pos                             10                                                        /*!< SCT OUTPUTCLR3: CLRn10 Position     */
#define SCT_OUTPUTCLR3_CLRn10_Msk                             (0x01UL << SCT_OUTPUTCLR3_CLRn10_Pos)                     /*!< SCT OUTPUTCLR3: CLRn10 Mask         */
#define SCT_OUTPUTCLR3_CLRn11_Pos                             11                                                        /*!< SCT OUTPUTCLR3: CLRn11 Position     */
#define SCT_OUTPUTCLR3_CLRn11_Msk                             (0x01UL << SCT_OUTPUTCLR3_CLRn11_Pos)                     /*!< SCT OUTPUTCLR3: CLRn11 Mask         */
#define SCT_OUTPUTCLR3_CLRn12_Pos                             12                                                        /*!< SCT OUTPUTCLR3: CLRn12 Position     */
#define SCT_OUTPUTCLR3_CLRn12_Msk                             (0x01UL << SCT_OUTPUTCLR3_CLRn12_Pos)                     /*!< SCT OUTPUTCLR3: CLRn12 Mask         */
#define SCT_OUTPUTCLR3_CLRn13_Pos                             13                                                        /*!< SCT OUTPUTCLR3: CLRn13 Position     */
#define SCT_OUTPUTCLR3_CLRn13_Msk                             (0x01UL << SCT_OUTPUTCLR3_CLRn13_Pos)                     /*!< SCT OUTPUTCLR3: CLRn13 Mask         */
#define SCT_OUTPUTCLR3_CLRn14_Pos                             14                                                        /*!< SCT OUTPUTCLR3: CLRn14 Position     */
#define SCT_OUTPUTCLR3_CLRn14_Msk                             (0x01UL << SCT_OUTPUTCLR3_CLRn14_Pos)                     /*!< SCT OUTPUTCLR3: CLRn14 Mask         */
#define SCT_OUTPUTCLR3_CLRn15_Pos                             15                                                        /*!< SCT OUTPUTCLR3: CLRn15 Position     */
#define SCT_OUTPUTCLR3_CLRn15_Msk                             (0x01UL << SCT_OUTPUTCLR3_CLRn15_Pos)                     /*!< SCT OUTPUTCLR3: CLRn15 Mask         */

// -------------------------------------  SCT_OUTPUTSET4  -----------------------------------------
#define SCT_OUTPUTSET4_SETn0_Pos                              0                                                         /*!< SCT OUTPUTSET4: SETn0 Position      */
#define SCT_OUTPUTSET4_SETn0_Msk                              (0x01UL << SCT_OUTPUTSET4_SETn0_Pos)                      /*!< SCT OUTPUTSET4: SETn0 Mask          */
#define SCT_OUTPUTSET4_SETn1_Pos                              1                                                         /*!< SCT OUTPUTSET4: SETn1 Position      */
#define SCT_OUTPUTSET4_SETn1_Msk                              (0x01UL << SCT_OUTPUTSET4_SETn1_Pos)                      /*!< SCT OUTPUTSET4: SETn1 Mask          */
#define SCT_OUTPUTSET4_SETn2_Pos                              2                                                         /*!< SCT OUTPUTSET4: SETn2 Position      */
#define SCT_OUTPUTSET4_SETn2_Msk                              (0x01UL << SCT_OUTPUTSET4_SETn2_Pos)                      /*!< SCT OUTPUTSET4: SETn2 Mask          */
#define SCT_OUTPUTSET4_SETn3_Pos                              3                                                         /*!< SCT OUTPUTSET4: SETn3 Position      */
#define SCT_OUTPUTSET4_SETn3_Msk                              (0x01UL << SCT_OUTPUTSET4_SETn3_Pos)                      /*!< SCT OUTPUTSET4: SETn3 Mask          */
#define SCT_OUTPUTSET4_SETn4_Pos                              4                                                         /*!< SCT OUTPUTSET4: SETn4 Position      */
#define SCT_OUTPUTSET4_SETn4_Msk                              (0x01UL << SCT_OUTPUTSET4_SETn4_Pos)                      /*!< SCT OUTPUTSET4: SETn4 Mask          */
#define SCT_OUTPUTSET4_SETn5_Pos                              5                                                         /*!< SCT OUTPUTSET4: SETn5 Position      */
#define SCT_OUTPUTSET4_SETn5_Msk                              (0x01UL << SCT_OUTPUTSET4_SETn5_Pos)                      /*!< SCT OUTPUTSET4: SETn5 Mask          */
#define SCT_OUTPUTSET4_SETn6_Pos                              6                                                         /*!< SCT OUTPUTSET4: SETn6 Position      */
#define SCT_OUTPUTSET4_SETn6_Msk                              (0x01UL << SCT_OUTPUTSET4_SETn6_Pos)                      /*!< SCT OUTPUTSET4: SETn6 Mask          */
#define SCT_OUTPUTSET4_SETn7_Pos                              7                                                         /*!< SCT OUTPUTSET4: SETn7 Position      */
#define SCT_OUTPUTSET4_SETn7_Msk                              (0x01UL << SCT_OUTPUTSET4_SETn7_Pos)                      /*!< SCT OUTPUTSET4: SETn7 Mask          */
#define SCT_OUTPUTSET4_SETn8_Pos                              8                                                         /*!< SCT OUTPUTSET4: SETn8 Position      */
#define SCT_OUTPUTSET4_SETn8_Msk                              (0x01UL << SCT_OUTPUTSET4_SETn8_Pos)                      /*!< SCT OUTPUTSET4: SETn8 Mask          */
#define SCT_OUTPUTSET4_SETn9_Pos                              9                                                         /*!< SCT OUTPUTSET4: SETn9 Position      */
#define SCT_OUTPUTSET4_SETn9_Msk                              (0x01UL << SCT_OUTPUTSET4_SETn9_Pos)                      /*!< SCT OUTPUTSET4: SETn9 Mask          */
#define SCT_OUTPUTSET4_SETn10_Pos                             10                                                        /*!< SCT OUTPUTSET4: SETn10 Position     */
#define SCT_OUTPUTSET4_SETn10_Msk                             (0x01UL << SCT_OUTPUTSET4_SETn10_Pos)                     /*!< SCT OUTPUTSET4: SETn10 Mask         */
#define SCT_OUTPUTSET4_SETn11_Pos                             11                                                        /*!< SCT OUTPUTSET4: SETn11 Position     */
#define SCT_OUTPUTSET4_SETn11_Msk                             (0x01UL << SCT_OUTPUTSET4_SETn11_Pos)                     /*!< SCT OUTPUTSET4: SETn11 Mask         */
#define SCT_OUTPUTSET4_SETn12_Pos                             12                                                        /*!< SCT OUTPUTSET4: SETn12 Position     */
#define SCT_OUTPUTSET4_SETn12_Msk                             (0x01UL << SCT_OUTPUTSET4_SETn12_Pos)                     /*!< SCT OUTPUTSET4: SETn12 Mask         */
#define SCT_OUTPUTSET4_SETn13_Pos                             13                                                        /*!< SCT OUTPUTSET4: SETn13 Position     */
#define SCT_OUTPUTSET4_SETn13_Msk                             (0x01UL << SCT_OUTPUTSET4_SETn13_Pos)                     /*!< SCT OUTPUTSET4: SETn13 Mask         */
#define SCT_OUTPUTSET4_SETn14_Pos                             14                                                        /*!< SCT OUTPUTSET4: SETn14 Position     */
#define SCT_OUTPUTSET4_SETn14_Msk                             (0x01UL << SCT_OUTPUTSET4_SETn14_Pos)                     /*!< SCT OUTPUTSET4: SETn14 Mask         */
#define SCT_OUTPUTSET4_SETn15_Pos                             15                                                        /*!< SCT OUTPUTSET4: SETn15 Position     */
#define SCT_OUTPUTSET4_SETn15_Msk                             (0x01UL << SCT_OUTPUTSET4_SETn15_Pos)                     /*!< SCT OUTPUTSET4: SETn15 Mask         */

// -------------------------------------  SCT_OUTPUTCLR4  -----------------------------------------
#define SCT_OUTPUTCLR4_CLRn0_Pos                              0                                                         /*!< SCT OUTPUTCLR4: CLRn0 Position      */
#define SCT_OUTPUTCLR4_CLRn0_Msk                              (0x01UL << SCT_OUTPUTCLR4_CLRn0_Pos)                      /*!< SCT OUTPUTCLR4: CLRn0 Mask          */
#define SCT_OUTPUTCLR4_CLRn1_Pos                              1                                                         /*!< SCT OUTPUTCLR4: CLRn1 Position      */
#define SCT_OUTPUTCLR4_CLRn1_Msk                              (0x01UL << SCT_OUTPUTCLR4_CLRn1_Pos)                      /*!< SCT OUTPUTCLR4: CLRn1 Mask          */
#define SCT_OUTPUTCLR4_CLRn2_Pos                              2                                                         /*!< SCT OUTPUTCLR4: CLRn2 Position      */
#define SCT_OUTPUTCLR4_CLRn2_Msk                              (0x01UL << SCT_OUTPUTCLR4_CLRn2_Pos)                      /*!< SCT OUTPUTCLR4: CLRn2 Mask          */
#define SCT_OUTPUTCLR4_CLRn3_Pos                              3                                                         /*!< SCT OUTPUTCLR4: CLRn3 Position      */
#define SCT_OUTPUTCLR4_CLRn3_Msk                              (0x01UL << SCT_OUTPUTCLR4_CLRn3_Pos)                      /*!< SCT OUTPUTCLR4: CLRn3 Mask          */
#define SCT_OUTPUTCLR4_CLRn4_Pos                              4                                                         /*!< SCT OUTPUTCLR4: CLRn4 Position      */
#define SCT_OUTPUTCLR4_CLRn4_Msk                              (0x01UL << SCT_OUTPUTCLR4_CLRn4_Pos)                      /*!< SCT OUTPUTCLR4: CLRn4 Mask          */
#define SCT_OUTPUTCLR4_CLRn5_Pos                              5                                                         /*!< SCT OUTPUTCLR4: CLRn5 Position      */
#define SCT_OUTPUTCLR4_CLRn5_Msk                              (0x01UL << SCT_OUTPUTCLR4_CLRn5_Pos)                      /*!< SCT OUTPUTCLR4: CLRn5 Mask          */
#define SCT_OUTPUTCLR4_CLRn6_Pos                              6                                                         /*!< SCT OUTPUTCLR4: CLRn6 Position      */
#define SCT_OUTPUTCLR4_CLRn6_Msk                              (0x01UL << SCT_OUTPUTCLR4_CLRn6_Pos)                      /*!< SCT OUTPUTCLR4: CLRn6 Mask          */
#define SCT_OUTPUTCLR4_CLRn7_Pos                              7                                                         /*!< SCT OUTPUTCLR4: CLRn7 Position      */
#define SCT_OUTPUTCLR4_CLRn7_Msk                              (0x01UL << SCT_OUTPUTCLR4_CLRn7_Pos)                      /*!< SCT OUTPUTCLR4: CLRn7 Mask          */
#define SCT_OUTPUTCLR4_CLRn8_Pos                              8                                                         /*!< SCT OUTPUTCLR4: CLRn8 Position      */
#define SCT_OUTPUTCLR4_CLRn8_Msk                              (0x01UL << SCT_OUTPUTCLR4_CLRn8_Pos)                      /*!< SCT OUTPUTCLR4: CLRn8 Mask          */
#define SCT_OUTPUTCLR4_CLRn9_Pos                              9                                                         /*!< SCT OUTPUTCLR4: CLRn9 Position      */
#define SCT_OUTPUTCLR4_CLRn9_Msk                              (0x01UL << SCT_OUTPUTCLR4_CLRn9_Pos)                      /*!< SCT OUTPUTCLR4: CLRn9 Mask          */
#define SCT_OUTPUTCLR4_CLRn10_Pos                             10                                                        /*!< SCT OUTPUTCLR4: CLRn10 Position     */
#define SCT_OUTPUTCLR4_CLRn10_Msk                             (0x01UL << SCT_OUTPUTCLR4_CLRn10_Pos)                     /*!< SCT OUTPUTCLR4: CLRn10 Mask         */
#define SCT_OUTPUTCLR4_CLRn11_Pos                             11                                                        /*!< SCT OUTPUTCLR4: CLRn11 Position     */
#define SCT_OUTPUTCLR4_CLRn11_Msk                             (0x01UL << SCT_OUTPUTCLR4_CLRn11_Pos)                     /*!< SCT OUTPUTCLR4: CLRn11 Mask         */
#define SCT_OUTPUTCLR4_CLRn12_Pos                             12                                                        /*!< SCT OUTPUTCLR4: CLRn12 Position     */
#define SCT_OUTPUTCLR4_CLRn12_Msk                             (0x01UL << SCT_OUTPUTCLR4_CLRn12_Pos)                     /*!< SCT OUTPUTCLR4: CLRn12 Mask         */
#define SCT_OUTPUTCLR4_CLRn13_Pos                             13                                                        /*!< SCT OUTPUTCLR4: CLRn13 Position     */
#define SCT_OUTPUTCLR4_CLRn13_Msk                             (0x01UL << SCT_OUTPUTCLR4_CLRn13_Pos)                     /*!< SCT OUTPUTCLR4: CLRn13 Mask         */
#define SCT_OUTPUTCLR4_CLRn14_Pos                             14                                                        /*!< SCT OUTPUTCLR4: CLRn14 Position     */
#define SCT_OUTPUTCLR4_CLRn14_Msk                             (0x01UL << SCT_OUTPUTCLR4_CLRn14_Pos)                     /*!< SCT OUTPUTCLR4: CLRn14 Mask         */
#define SCT_OUTPUTCLR4_CLRn15_Pos                             15                                                        /*!< SCT OUTPUTCLR4: CLRn15 Position     */
#define SCT_OUTPUTCLR4_CLRn15_Msk                             (0x01UL << SCT_OUTPUTCLR4_CLRn15_Pos)                     /*!< SCT OUTPUTCLR4: CLRn15 Mask         */

// -------------------------------------  SCT_OUTPUTSET5  -----------------------------------------
#define SCT_OUTPUTSET5_SETn0_Pos                              0                                                         /*!< SCT OUTPUTSET5: SETn0 Position      */
#define SCT_OUTPUTSET5_SETn0_Msk                              (0x01UL << SCT_OUTPUTSET5_SETn0_Pos)                      /*!< SCT OUTPUTSET5: SETn0 Mask          */
#define SCT_OUTPUTSET5_SETn1_Pos                              1                                                         /*!< SCT OUTPUTSET5: SETn1 Position      */
#define SCT_OUTPUTSET5_SETn1_Msk                              (0x01UL << SCT_OUTPUTSET5_SETn1_Pos)                      /*!< SCT OUTPUTSET5: SETn1 Mask          */
#define SCT_OUTPUTSET5_SETn2_Pos                              2                                                         /*!< SCT OUTPUTSET5: SETn2 Position      */
#define SCT_OUTPUTSET5_SETn2_Msk                              (0x01UL << SCT_OUTPUTSET5_SETn2_Pos)                      /*!< SCT OUTPUTSET5: SETn2 Mask          */
#define SCT_OUTPUTSET5_SETn3_Pos                              3                                                         /*!< SCT OUTPUTSET5: SETn3 Position      */
#define SCT_OUTPUTSET5_SETn3_Msk                              (0x01UL << SCT_OUTPUTSET5_SETn3_Pos)                      /*!< SCT OUTPUTSET5: SETn3 Mask          */
#define SCT_OUTPUTSET5_SETn4_Pos                              4                                                         /*!< SCT OUTPUTSET5: SETn4 Position      */
#define SCT_OUTPUTSET5_SETn4_Msk                              (0x01UL << SCT_OUTPUTSET5_SETn4_Pos)                      /*!< SCT OUTPUTSET5: SETn4 Mask          */
#define SCT_OUTPUTSET5_SETn5_Pos                              5                                                         /*!< SCT OUTPUTSET5: SETn5 Position      */
#define SCT_OUTPUTSET5_SETn5_Msk                              (0x01UL << SCT_OUTPUTSET5_SETn5_Pos)                      /*!< SCT OUTPUTSET5: SETn5 Mask          */
#define SCT_OUTPUTSET5_SETn6_Pos                              6                                                         /*!< SCT OUTPUTSET5: SETn6 Position      */
#define SCT_OUTPUTSET5_SETn6_Msk                              (0x01UL << SCT_OUTPUTSET5_SETn6_Pos)                      /*!< SCT OUTPUTSET5: SETn6 Mask          */
#define SCT_OUTPUTSET5_SETn7_Pos                              7                                                         /*!< SCT OUTPUTSET5: SETn7 Position      */
#define SCT_OUTPUTSET5_SETn7_Msk                              (0x01UL << SCT_OUTPUTSET5_SETn7_Pos)                      /*!< SCT OUTPUTSET5: SETn7 Mask          */
#define SCT_OUTPUTSET5_SETn8_Pos                              8                                                         /*!< SCT OUTPUTSET5: SETn8 Position      */
#define SCT_OUTPUTSET5_SETn8_Msk                              (0x01UL << SCT_OUTPUTSET5_SETn8_Pos)                      /*!< SCT OUTPUTSET5: SETn8 Mask          */
#define SCT_OUTPUTSET5_SETn9_Pos                              9                                                         /*!< SCT OUTPUTSET5: SETn9 Position      */
#define SCT_OUTPUTSET5_SETn9_Msk                              (0x01UL << SCT_OUTPUTSET5_SETn9_Pos)                      /*!< SCT OUTPUTSET5: SETn9 Mask          */
#define SCT_OUTPUTSET5_SETn10_Pos                             10                                                        /*!< SCT OUTPUTSET5: SETn10 Position     */
#define SCT_OUTPUTSET5_SETn10_Msk                             (0x01UL << SCT_OUTPUTSET5_SETn10_Pos)                     /*!< SCT OUTPUTSET5: SETn10 Mask         */
#define SCT_OUTPUTSET5_SETn11_Pos                             11                                                        /*!< SCT OUTPUTSET5: SETn11 Position     */
#define SCT_OUTPUTSET5_SETn11_Msk                             (0x01UL << SCT_OUTPUTSET5_SETn11_Pos)                     /*!< SCT OUTPUTSET5: SETn11 Mask         */
#define SCT_OUTPUTSET5_SETn12_Pos                             12                                                        /*!< SCT OUTPUTSET5: SETn12 Position     */
#define SCT_OUTPUTSET5_SETn12_Msk                             (0x01UL << SCT_OUTPUTSET5_SETn12_Pos)                     /*!< SCT OUTPUTSET5: SETn12 Mask         */
#define SCT_OUTPUTSET5_SETn13_Pos                             13                                                        /*!< SCT OUTPUTSET5: SETn13 Position     */
#define SCT_OUTPUTSET5_SETn13_Msk                             (0x01UL << SCT_OUTPUTSET5_SETn13_Pos)                     /*!< SCT OUTPUTSET5: SETn13 Mask         */
#define SCT_OUTPUTSET5_SETn14_Pos                             14                                                        /*!< SCT OUTPUTSET5: SETn14 Position     */
#define SCT_OUTPUTSET5_SETn14_Msk                             (0x01UL << SCT_OUTPUTSET5_SETn14_Pos)                     /*!< SCT OUTPUTSET5: SETn14 Mask         */
#define SCT_OUTPUTSET5_SETn15_Pos                             15                                                        /*!< SCT OUTPUTSET5: SETn15 Position     */
#define SCT_OUTPUTSET5_SETn15_Msk                             (0x01UL << SCT_OUTPUTSET5_SETn15_Pos)                     /*!< SCT OUTPUTSET5: SETn15 Mask         */

// -------------------------------------  SCT_OUTPUTCLR5  -----------------------------------------
#define SCT_OUTPUTCLR5_CLRn0_Pos                              0                                                         /*!< SCT OUTPUTCLR5: CLRn0 Position      */
#define SCT_OUTPUTCLR5_CLRn0_Msk                              (0x01UL << SCT_OUTPUTCLR5_CLRn0_Pos)                      /*!< SCT OUTPUTCLR5: CLRn0 Mask          */
#define SCT_OUTPUTCLR5_CLRn1_Pos                              1                                                         /*!< SCT OUTPUTCLR5: CLRn1 Position      */
#define SCT_OUTPUTCLR5_CLRn1_Msk                              (0x01UL << SCT_OUTPUTCLR5_CLRn1_Pos)                      /*!< SCT OUTPUTCLR5: CLRn1 Mask          */
#define SCT_OUTPUTCLR5_CLRn2_Pos                              2                                                         /*!< SCT OUTPUTCLR5: CLRn2 Position      */
#define SCT_OUTPUTCLR5_CLRn2_Msk                              (0x01UL << SCT_OUTPUTCLR5_CLRn2_Pos)                      /*!< SCT OUTPUTCLR5: CLRn2 Mask          */
#define SCT_OUTPUTCLR5_CLRn3_Pos                              3                                                         /*!< SCT OUTPUTCLR5: CLRn3 Position      */
#define SCT_OUTPUTCLR5_CLRn3_Msk                              (0x01UL << SCT_OUTPUTCLR5_CLRn3_Pos)                      /*!< SCT OUTPUTCLR5: CLRn3 Mask          */
#define SCT_OUTPUTCLR5_CLRn4_Pos                              4                                                         /*!< SCT OUTPUTCLR5: CLRn4 Position      */
#define SCT_OUTPUTCLR5_CLRn4_Msk                              (0x01UL << SCT_OUTPUTCLR5_CLRn4_Pos)                      /*!< SCT OUTPUTCLR5: CLRn4 Mask          */
#define SCT_OUTPUTCLR5_CLRn5_Pos                              5                                                         /*!< SCT OUTPUTCLR5: CLRn5 Position      */
#define SCT_OUTPUTCLR5_CLRn5_Msk                              (0x01UL << SCT_OUTPUTCLR5_CLRn5_Pos)                      /*!< SCT OUTPUTCLR5: CLRn5 Mask          */
#define SCT_OUTPUTCLR5_CLRn6_Pos                              6                                                         /*!< SCT OUTPUTCLR5: CLRn6 Position      */
#define SCT_OUTPUTCLR5_CLRn6_Msk                              (0x01UL << SCT_OUTPUTCLR5_CLRn6_Pos)                      /*!< SCT OUTPUTCLR5: CLRn6 Mask          */
#define SCT_OUTPUTCLR5_CLRn7_Pos                              7                                                         /*!< SCT OUTPUTCLR5: CLRn7 Position      */
#define SCT_OUTPUTCLR5_CLRn7_Msk                              (0x01UL << SCT_OUTPUTCLR5_CLRn7_Pos)                      /*!< SCT OUTPUTCLR5: CLRn7 Mask          */
#define SCT_OUTPUTCLR5_CLRn8_Pos                              8                                                         /*!< SCT OUTPUTCLR5: CLRn8 Position      */
#define SCT_OUTPUTCLR5_CLRn8_Msk                              (0x01UL << SCT_OUTPUTCLR5_CLRn8_Pos)                      /*!< SCT OUTPUTCLR5: CLRn8 Mask          */
#define SCT_OUTPUTCLR5_CLRn9_Pos                              9                                                         /*!< SCT OUTPUTCLR5: CLRn9 Position      */
#define SCT_OUTPUTCLR5_CLRn9_Msk                              (0x01UL << SCT_OUTPUTCLR5_CLRn9_Pos)                      /*!< SCT OUTPUTCLR5: CLRn9 Mask          */
#define SCT_OUTPUTCLR5_CLRn10_Pos                             10                                                        /*!< SCT OUTPUTCLR5: CLRn10 Position     */
#define SCT_OUTPUTCLR5_CLRn10_Msk                             (0x01UL << SCT_OUTPUTCLR5_CLRn10_Pos)                     /*!< SCT OUTPUTCLR5: CLRn10 Mask         */
#define SCT_OUTPUTCLR5_CLRn11_Pos                             11                                                        /*!< SCT OUTPUTCLR5: CLRn11 Position     */
#define SCT_OUTPUTCLR5_CLRn11_Msk                             (0x01UL << SCT_OUTPUTCLR5_CLRn11_Pos)                     /*!< SCT OUTPUTCLR5: CLRn11 Mask         */
#define SCT_OUTPUTCLR5_CLRn12_Pos                             12                                                        /*!< SCT OUTPUTCLR5: CLRn12 Position     */
#define SCT_OUTPUTCLR5_CLRn12_Msk                             (0x01UL << SCT_OUTPUTCLR5_CLRn12_Pos)                     /*!< SCT OUTPUTCLR5: CLRn12 Mask         */
#define SCT_OUTPUTCLR5_CLRn13_Pos                             13                                                        /*!< SCT OUTPUTCLR5: CLRn13 Position     */
#define SCT_OUTPUTCLR5_CLRn13_Msk                             (0x01UL << SCT_OUTPUTCLR5_CLRn13_Pos)                     /*!< SCT OUTPUTCLR5: CLRn13 Mask         */
#define SCT_OUTPUTCLR5_CLRn14_Pos                             14                                                        /*!< SCT OUTPUTCLR5: CLRn14 Position     */
#define SCT_OUTPUTCLR5_CLRn14_Msk                             (0x01UL << SCT_OUTPUTCLR5_CLRn14_Pos)                     /*!< SCT OUTPUTCLR5: CLRn14 Mask         */
#define SCT_OUTPUTCLR5_CLRn15_Pos                             15                                                        /*!< SCT OUTPUTCLR5: CLRn15 Position     */
#define SCT_OUTPUTCLR5_CLRn15_Msk                             (0x01UL << SCT_OUTPUTCLR5_CLRn15_Pos)                     /*!< SCT OUTPUTCLR5: CLRn15 Mask         */

// -------------------------------------  SCT_OUTPUTSET6  -----------------------------------------
#define SCT_OUTPUTSET6_SETn0_Pos                              0                                                         /*!< SCT OUTPUTSET6: SETn0 Position      */
#define SCT_OUTPUTSET6_SETn0_Msk                              (0x01UL << SCT_OUTPUTSET6_SETn0_Pos)                      /*!< SCT OUTPUTSET6: SETn0 Mask          */
#define SCT_OUTPUTSET6_SETn1_Pos                              1                                                         /*!< SCT OUTPUTSET6: SETn1 Position      */
#define SCT_OUTPUTSET6_SETn1_Msk                              (0x01UL << SCT_OUTPUTSET6_SETn1_Pos)                      /*!< SCT OUTPUTSET6: SETn1 Mask          */
#define SCT_OUTPUTSET6_SETn2_Pos                              2                                                         /*!< SCT OUTPUTSET6: SETn2 Position      */
#define SCT_OUTPUTSET6_SETn2_Msk                              (0x01UL << SCT_OUTPUTSET6_SETn2_Pos)                      /*!< SCT OUTPUTSET6: SETn2 Mask          */
#define SCT_OUTPUTSET6_SETn3_Pos                              3                                                         /*!< SCT OUTPUTSET6: SETn3 Position      */
#define SCT_OUTPUTSET6_SETn3_Msk                              (0x01UL << SCT_OUTPUTSET6_SETn3_Pos)                      /*!< SCT OUTPUTSET6: SETn3 Mask          */
#define SCT_OUTPUTSET6_SETn4_Pos                              4                                                         /*!< SCT OUTPUTSET6: SETn4 Position      */
#define SCT_OUTPUTSET6_SETn4_Msk                              (0x01UL << SCT_OUTPUTSET6_SETn4_Pos)                      /*!< SCT OUTPUTSET6: SETn4 Mask          */
#define SCT_OUTPUTSET6_SETn5_Pos                              5                                                         /*!< SCT OUTPUTSET6: SETn5 Position      */
#define SCT_OUTPUTSET6_SETn5_Msk                              (0x01UL << SCT_OUTPUTSET6_SETn5_Pos)                      /*!< SCT OUTPUTSET6: SETn5 Mask          */
#define SCT_OUTPUTSET6_SETn6_Pos                              6                                                         /*!< SCT OUTPUTSET6: SETn6 Position      */
#define SCT_OUTPUTSET6_SETn6_Msk                              (0x01UL << SCT_OUTPUTSET6_SETn6_Pos)                      /*!< SCT OUTPUTSET6: SETn6 Mask          */
#define SCT_OUTPUTSET6_SETn7_Pos                              7                                                         /*!< SCT OUTPUTSET6: SETn7 Position      */
#define SCT_OUTPUTSET6_SETn7_Msk                              (0x01UL << SCT_OUTPUTSET6_SETn7_Pos)                      /*!< SCT OUTPUTSET6: SETn7 Mask          */
#define SCT_OUTPUTSET6_SETn8_Pos                              8                                                         /*!< SCT OUTPUTSET6: SETn8 Position      */
#define SCT_OUTPUTSET6_SETn8_Msk                              (0x01UL << SCT_OUTPUTSET6_SETn8_Pos)                      /*!< SCT OUTPUTSET6: SETn8 Mask          */
#define SCT_OUTPUTSET6_SETn9_Pos                              9                                                         /*!< SCT OUTPUTSET6: SETn9 Position      */
#define SCT_OUTPUTSET6_SETn9_Msk                              (0x01UL << SCT_OUTPUTSET6_SETn9_Pos)                      /*!< SCT OUTPUTSET6: SETn9 Mask          */
#define SCT_OUTPUTSET6_SETn10_Pos                             10                                                        /*!< SCT OUTPUTSET6: SETn10 Position     */
#define SCT_OUTPUTSET6_SETn10_Msk                             (0x01UL << SCT_OUTPUTSET6_SETn10_Pos)                     /*!< SCT OUTPUTSET6: SETn10 Mask         */
#define SCT_OUTPUTSET6_SETn11_Pos                             11                                                        /*!< SCT OUTPUTSET6: SETn11 Position     */
#define SCT_OUTPUTSET6_SETn11_Msk                             (0x01UL << SCT_OUTPUTSET6_SETn11_Pos)                     /*!< SCT OUTPUTSET6: SETn11 Mask         */
#define SCT_OUTPUTSET6_SETn12_Pos                             12                                                        /*!< SCT OUTPUTSET6: SETn12 Position     */
#define SCT_OUTPUTSET6_SETn12_Msk                             (0x01UL << SCT_OUTPUTSET6_SETn12_Pos)                     /*!< SCT OUTPUTSET6: SETn12 Mask         */
#define SCT_OUTPUTSET6_SETn13_Pos                             13                                                        /*!< SCT OUTPUTSET6: SETn13 Position     */
#define SCT_OUTPUTSET6_SETn13_Msk                             (0x01UL << SCT_OUTPUTSET6_SETn13_Pos)                     /*!< SCT OUTPUTSET6: SETn13 Mask         */
#define SCT_OUTPUTSET6_SETn14_Pos                             14                                                        /*!< SCT OUTPUTSET6: SETn14 Position     */
#define SCT_OUTPUTSET6_SETn14_Msk                             (0x01UL << SCT_OUTPUTSET6_SETn14_Pos)                     /*!< SCT OUTPUTSET6: SETn14 Mask         */
#define SCT_OUTPUTSET6_SETn15_Pos                             15                                                        /*!< SCT OUTPUTSET6: SETn15 Position     */
#define SCT_OUTPUTSET6_SETn15_Msk                             (0x01UL << SCT_OUTPUTSET6_SETn15_Pos)                     /*!< SCT OUTPUTSET6: SETn15 Mask         */

// -------------------------------------  SCT_OUTPUTCLR6  -----------------------------------------
#define SCT_OUTPUTCLR6_CLRn0_Pos                              0                                                         /*!< SCT OUTPUTCLR6: CLRn0 Position      */
#define SCT_OUTPUTCLR6_CLRn0_Msk                              (0x01UL << SCT_OUTPUTCLR6_CLRn0_Pos)                      /*!< SCT OUTPUTCLR6: CLRn0 Mask          */
#define SCT_OUTPUTCLR6_CLRn1_Pos                              1                                                         /*!< SCT OUTPUTCLR6: CLRn1 Position      */
#define SCT_OUTPUTCLR6_CLRn1_Msk                              (0x01UL << SCT_OUTPUTCLR6_CLRn1_Pos)                      /*!< SCT OUTPUTCLR6: CLRn1 Mask          */
#define SCT_OUTPUTCLR6_CLRn2_Pos                              2                                                         /*!< SCT OUTPUTCLR6: CLRn2 Position      */
#define SCT_OUTPUTCLR6_CLRn2_Msk                              (0x01UL << SCT_OUTPUTCLR6_CLRn2_Pos)                      /*!< SCT OUTPUTCLR6: CLRn2 Mask          */
#define SCT_OUTPUTCLR6_CLRn3_Pos                              3                                                         /*!< SCT OUTPUTCLR6: CLRn3 Position      */
#define SCT_OUTPUTCLR6_CLRn3_Msk                              (0x01UL << SCT_OUTPUTCLR6_CLRn3_Pos)                      /*!< SCT OUTPUTCLR6: CLRn3 Mask          */
#define SCT_OUTPUTCLR6_CLRn4_Pos                              4                                                         /*!< SCT OUTPUTCLR6: CLRn4 Position      */
#define SCT_OUTPUTCLR6_CLRn4_Msk                              (0x01UL << SCT_OUTPUTCLR6_CLRn4_Pos)                      /*!< SCT OUTPUTCLR6: CLRn4 Mask          */
#define SCT_OUTPUTCLR6_CLRn5_Pos                              5                                                         /*!< SCT OUTPUTCLR6: CLRn5 Position      */
#define SCT_OUTPUTCLR6_CLRn5_Msk                              (0x01UL << SCT_OUTPUTCLR6_CLRn5_Pos)                      /*!< SCT OUTPUTCLR6: CLRn5 Mask          */
#define SCT_OUTPUTCLR6_CLRn6_Pos                              6                                                         /*!< SCT OUTPUTCLR6: CLRn6 Position      */
#define SCT_OUTPUTCLR6_CLRn6_Msk                              (0x01UL << SCT_OUTPUTCLR6_CLRn6_Pos)                      /*!< SCT OUTPUTCLR6: CLRn6 Mask          */
#define SCT_OUTPUTCLR6_CLRn7_Pos                              7                                                         /*!< SCT OUTPUTCLR6: CLRn7 Position      */
#define SCT_OUTPUTCLR6_CLRn7_Msk                              (0x01UL << SCT_OUTPUTCLR6_CLRn7_Pos)                      /*!< SCT OUTPUTCLR6: CLRn7 Mask          */
#define SCT_OUTPUTCLR6_CLRn8_Pos                              8                                                         /*!< SCT OUTPUTCLR6: CLRn8 Position      */
#define SCT_OUTPUTCLR6_CLRn8_Msk                              (0x01UL << SCT_OUTPUTCLR6_CLRn8_Pos)                      /*!< SCT OUTPUTCLR6: CLRn8 Mask          */
#define SCT_OUTPUTCLR6_CLRn9_Pos                              9                                                         /*!< SCT OUTPUTCLR6: CLRn9 Position      */
#define SCT_OUTPUTCLR6_CLRn9_Msk                              (0x01UL << SCT_OUTPUTCLR6_CLRn9_Pos)                      /*!< SCT OUTPUTCLR6: CLRn9 Mask          */
#define SCT_OUTPUTCLR6_CLRn10_Pos                             10                                                        /*!< SCT OUTPUTCLR6: CLRn10 Position     */
#define SCT_OUTPUTCLR6_CLRn10_Msk                             (0x01UL << SCT_OUTPUTCLR6_CLRn10_Pos)                     /*!< SCT OUTPUTCLR6: CLRn10 Mask         */
#define SCT_OUTPUTCLR6_CLRn11_Pos                             11                                                        /*!< SCT OUTPUTCLR6: CLRn11 Position     */
#define SCT_OUTPUTCLR6_CLRn11_Msk                             (0x01UL << SCT_OUTPUTCLR6_CLRn11_Pos)                     /*!< SCT OUTPUTCLR6: CLRn11 Mask         */
#define SCT_OUTPUTCLR6_CLRn12_Pos                             12                                                        /*!< SCT OUTPUTCLR6: CLRn12 Position     */
#define SCT_OUTPUTCLR6_CLRn12_Msk                             (0x01UL << SCT_OUTPUTCLR6_CLRn12_Pos)                     /*!< SCT OUTPUTCLR6: CLRn12 Mask         */
#define SCT_OUTPUTCLR6_CLRn13_Pos                             13                                                        /*!< SCT OUTPUTCLR6: CLRn13 Position     */
#define SCT_OUTPUTCLR6_CLRn13_Msk                             (0x01UL << SCT_OUTPUTCLR6_CLRn13_Pos)                     /*!< SCT OUTPUTCLR6: CLRn13 Mask         */
#define SCT_OUTPUTCLR6_CLRn14_Pos                             14                                                        /*!< SCT OUTPUTCLR6: CLRn14 Position     */
#define SCT_OUTPUTCLR6_CLRn14_Msk                             (0x01UL << SCT_OUTPUTCLR6_CLRn14_Pos)                     /*!< SCT OUTPUTCLR6: CLRn14 Mask         */
#define SCT_OUTPUTCLR6_CLRn15_Pos                             15                                                        /*!< SCT OUTPUTCLR6: CLRn15 Position     */
#define SCT_OUTPUTCLR6_CLRn15_Msk                             (0x01UL << SCT_OUTPUTCLR6_CLRn15_Pos)                     /*!< SCT OUTPUTCLR6: CLRn15 Mask         */

// -------------------------------------  SCT_OUTPUTSET7  -----------------------------------------
#define SCT_OUTPUTSET7_SETn0_Pos                              0                                                         /*!< SCT OUTPUTSET7: SETn0 Position      */
#define SCT_OUTPUTSET7_SETn0_Msk                              (0x01UL << SCT_OUTPUTSET7_SETn0_Pos)                      /*!< SCT OUTPUTSET7: SETn0 Mask          */
#define SCT_OUTPUTSET7_SETn1_Pos                              1                                                         /*!< SCT OUTPUTSET7: SETn1 Position      */
#define SCT_OUTPUTSET7_SETn1_Msk                              (0x01UL << SCT_OUTPUTSET7_SETn1_Pos)                      /*!< SCT OUTPUTSET7: SETn1 Mask          */
#define SCT_OUTPUTSET7_SETn2_Pos                              2                                                         /*!< SCT OUTPUTSET7: SETn2 Position      */
#define SCT_OUTPUTSET7_SETn2_Msk                              (0x01UL << SCT_OUTPUTSET7_SETn2_Pos)                      /*!< SCT OUTPUTSET7: SETn2 Mask          */
#define SCT_OUTPUTSET7_SETn3_Pos                              3                                                         /*!< SCT OUTPUTSET7: SETn3 Position      */
#define SCT_OUTPUTSET7_SETn3_Msk                              (0x01UL << SCT_OUTPUTSET7_SETn3_Pos)                      /*!< SCT OUTPUTSET7: SETn3 Mask          */
#define SCT_OUTPUTSET7_SETn4_Pos                              4                                                         /*!< SCT OUTPUTSET7: SETn4 Position      */
#define SCT_OUTPUTSET7_SETn4_Msk                              (0x01UL << SCT_OUTPUTSET7_SETn4_Pos)                      /*!< SCT OUTPUTSET7: SETn4 Mask          */
#define SCT_OUTPUTSET7_SETn5_Pos                              5                                                         /*!< SCT OUTPUTSET7: SETn5 Position      */
#define SCT_OUTPUTSET7_SETn5_Msk                              (0x01UL << SCT_OUTPUTSET7_SETn5_Pos)                      /*!< SCT OUTPUTSET7: SETn5 Mask          */
#define SCT_OUTPUTSET7_SETn6_Pos                              6                                                         /*!< SCT OUTPUTSET7: SETn6 Position      */
#define SCT_OUTPUTSET7_SETn6_Msk                              (0x01UL << SCT_OUTPUTSET7_SETn6_Pos)                      /*!< SCT OUTPUTSET7: SETn6 Mask          */
#define SCT_OUTPUTSET7_SETn7_Pos                              7                                                         /*!< SCT OUTPUTSET7: SETn7 Position      */
#define SCT_OUTPUTSET7_SETn7_Msk                              (0x01UL << SCT_OUTPUTSET7_SETn7_Pos)                      /*!< SCT OUTPUTSET7: SETn7 Mask          */
#define SCT_OUTPUTSET7_SETn8_Pos                              8                                                         /*!< SCT OUTPUTSET7: SETn8 Position      */
#define SCT_OUTPUTSET7_SETn8_Msk                              (0x01UL << SCT_OUTPUTSET7_SETn8_Pos)                      /*!< SCT OUTPUTSET7: SETn8 Mask          */
#define SCT_OUTPUTSET7_SETn9_Pos                              9                                                         /*!< SCT OUTPUTSET7: SETn9 Position      */
#define SCT_OUTPUTSET7_SETn9_Msk                              (0x01UL << SCT_OUTPUTSET7_SETn9_Pos)                      /*!< SCT OUTPUTSET7: SETn9 Mask          */
#define SCT_OUTPUTSET7_SETn10_Pos                             10                                                        /*!< SCT OUTPUTSET7: SETn10 Position     */
#define SCT_OUTPUTSET7_SETn10_Msk                             (0x01UL << SCT_OUTPUTSET7_SETn10_Pos)                     /*!< SCT OUTPUTSET7: SETn10 Mask         */
#define SCT_OUTPUTSET7_SETn11_Pos                             11                                                        /*!< SCT OUTPUTSET7: SETn11 Position     */
#define SCT_OUTPUTSET7_SETn11_Msk                             (0x01UL << SCT_OUTPUTSET7_SETn11_Pos)                     /*!< SCT OUTPUTSET7: SETn11 Mask         */
#define SCT_OUTPUTSET7_SETn12_Pos                             12                                                        /*!< SCT OUTPUTSET7: SETn12 Position     */
#define SCT_OUTPUTSET7_SETn12_Msk                             (0x01UL << SCT_OUTPUTSET7_SETn12_Pos)                     /*!< SCT OUTPUTSET7: SETn12 Mask         */
#define SCT_OUTPUTSET7_SETn13_Pos                             13                                                        /*!< SCT OUTPUTSET7: SETn13 Position     */
#define SCT_OUTPUTSET7_SETn13_Msk                             (0x01UL << SCT_OUTPUTSET7_SETn13_Pos)                     /*!< SCT OUTPUTSET7: SETn13 Mask         */
#define SCT_OUTPUTSET7_SETn14_Pos                             14                                                        /*!< SCT OUTPUTSET7: SETn14 Position     */
#define SCT_OUTPUTSET7_SETn14_Msk                             (0x01UL << SCT_OUTPUTSET7_SETn14_Pos)                     /*!< SCT OUTPUTSET7: SETn14 Mask         */
#define SCT_OUTPUTSET7_SETn15_Pos                             15                                                        /*!< SCT OUTPUTSET7: SETn15 Position     */
#define SCT_OUTPUTSET7_SETn15_Msk                             (0x01UL << SCT_OUTPUTSET7_SETn15_Pos)                     /*!< SCT OUTPUTSET7: SETn15 Mask         */

// -------------------------------------  SCT_OUTPUTCLR7  -----------------------------------------
#define SCT_OUTPUTCLR7_CLRn0_Pos                              0                                                         /*!< SCT OUTPUTCLR7: CLRn0 Position      */
#define SCT_OUTPUTCLR7_CLRn0_Msk                              (0x01UL << SCT_OUTPUTCLR7_CLRn0_Pos)                      /*!< SCT OUTPUTCLR7: CLRn0 Mask          */
#define SCT_OUTPUTCLR7_CLRn1_Pos                              1                                                         /*!< SCT OUTPUTCLR7: CLRn1 Position      */
#define SCT_OUTPUTCLR7_CLRn1_Msk                              (0x01UL << SCT_OUTPUTCLR7_CLRn1_Pos)                      /*!< SCT OUTPUTCLR7: CLRn1 Mask          */
#define SCT_OUTPUTCLR7_CLRn2_Pos                              2                                                         /*!< SCT OUTPUTCLR7: CLRn2 Position      */
#define SCT_OUTPUTCLR7_CLRn2_Msk                              (0x01UL << SCT_OUTPUTCLR7_CLRn2_Pos)                      /*!< SCT OUTPUTCLR7: CLRn2 Mask          */
#define SCT_OUTPUTCLR7_CLRn3_Pos                              3                                                         /*!< SCT OUTPUTCLR7: CLRn3 Position      */
#define SCT_OUTPUTCLR7_CLRn3_Msk                              (0x01UL << SCT_OUTPUTCLR7_CLRn3_Pos)                      /*!< SCT OUTPUTCLR7: CLRn3 Mask          */
#define SCT_OUTPUTCLR7_CLRn4_Pos                              4                                                         /*!< SCT OUTPUTCLR7: CLRn4 Position      */
#define SCT_OUTPUTCLR7_CLRn4_Msk                              (0x01UL << SCT_OUTPUTCLR7_CLRn4_Pos)                      /*!< SCT OUTPUTCLR7: CLRn4 Mask          */
#define SCT_OUTPUTCLR7_CLRn5_Pos                              5                                                         /*!< SCT OUTPUTCLR7: CLRn5 Position      */
#define SCT_OUTPUTCLR7_CLRn5_Msk                              (0x01UL << SCT_OUTPUTCLR7_CLRn5_Pos)                      /*!< SCT OUTPUTCLR7: CLRn5 Mask          */
#define SCT_OUTPUTCLR7_CLRn6_Pos                              6                                                         /*!< SCT OUTPUTCLR7: CLRn6 Position      */
#define SCT_OUTPUTCLR7_CLRn6_Msk                              (0x01UL << SCT_OUTPUTCLR7_CLRn6_Pos)                      /*!< SCT OUTPUTCLR7: CLRn6 Mask          */
#define SCT_OUTPUTCLR7_CLRn7_Pos                              7                                                         /*!< SCT OUTPUTCLR7: CLRn7 Position      */
#define SCT_OUTPUTCLR7_CLRn7_Msk                              (0x01UL << SCT_OUTPUTCLR7_CLRn7_Pos)                      /*!< SCT OUTPUTCLR7: CLRn7 Mask          */
#define SCT_OUTPUTCLR7_CLRn8_Pos                              8                                                         /*!< SCT OUTPUTCLR7: CLRn8 Position      */
#define SCT_OUTPUTCLR7_CLRn8_Msk                              (0x01UL << SCT_OUTPUTCLR7_CLRn8_Pos)                      /*!< SCT OUTPUTCLR7: CLRn8 Mask          */
#define SCT_OUTPUTCLR7_CLRn9_Pos                              9                                                         /*!< SCT OUTPUTCLR7: CLRn9 Position      */
#define SCT_OUTPUTCLR7_CLRn9_Msk                              (0x01UL << SCT_OUTPUTCLR7_CLRn9_Pos)                      /*!< SCT OUTPUTCLR7: CLRn9 Mask          */
#define SCT_OUTPUTCLR7_CLRn10_Pos                             10                                                        /*!< SCT OUTPUTCLR7: CLRn10 Position     */
#define SCT_OUTPUTCLR7_CLRn10_Msk                             (0x01UL << SCT_OUTPUTCLR7_CLRn10_Pos)                     /*!< SCT OUTPUTCLR7: CLRn10 Mask         */
#define SCT_OUTPUTCLR7_CLRn11_Pos                             11                                                        /*!< SCT OUTPUTCLR7: CLRn11 Position     */
#define SCT_OUTPUTCLR7_CLRn11_Msk                             (0x01UL << SCT_OUTPUTCLR7_CLRn11_Pos)                     /*!< SCT OUTPUTCLR7: CLRn11 Mask         */
#define SCT_OUTPUTCLR7_CLRn12_Pos                             12                                                        /*!< SCT OUTPUTCLR7: CLRn12 Position     */
#define SCT_OUTPUTCLR7_CLRn12_Msk                             (0x01UL << SCT_OUTPUTCLR7_CLRn12_Pos)                     /*!< SCT OUTPUTCLR7: CLRn12 Mask         */
#define SCT_OUTPUTCLR7_CLRn13_Pos                             13                                                        /*!< SCT OUTPUTCLR7: CLRn13 Position     */
#define SCT_OUTPUTCLR7_CLRn13_Msk                             (0x01UL << SCT_OUTPUTCLR7_CLRn13_Pos)                     /*!< SCT OUTPUTCLR7: CLRn13 Mask         */
#define SCT_OUTPUTCLR7_CLRn14_Pos                             14                                                        /*!< SCT OUTPUTCLR7: CLRn14 Position     */
#define SCT_OUTPUTCLR7_CLRn14_Msk                             (0x01UL << SCT_OUTPUTCLR7_CLRn14_Pos)                     /*!< SCT OUTPUTCLR7: CLRn14 Mask         */
#define SCT_OUTPUTCLR7_CLRn15_Pos                             15                                                        /*!< SCT OUTPUTCLR7: CLRn15 Position     */
#define SCT_OUTPUTCLR7_CLRn15_Msk                             (0x01UL << SCT_OUTPUTCLR7_CLRn15_Pos)                     /*!< SCT OUTPUTCLR7: CLRn15 Mask         */

// -------------------------------------  SCT_OUTPUTSET8  -----------------------------------------
#define SCT_OUTPUTSET8_SETn0_Pos                              0                                                         /*!< SCT OUTPUTSET8: SETn0 Position      */
#define SCT_OUTPUTSET8_SETn0_Msk                              (0x01UL << SCT_OUTPUTSET8_SETn0_Pos)                      /*!< SCT OUTPUTSET8: SETn0 Mask          */
#define SCT_OUTPUTSET8_SETn1_Pos                              1                                                         /*!< SCT OUTPUTSET8: SETn1 Position      */
#define SCT_OUTPUTSET8_SETn1_Msk                              (0x01UL << SCT_OUTPUTSET8_SETn1_Pos)                      /*!< SCT OUTPUTSET8: SETn1 Mask          */
#define SCT_OUTPUTSET8_SETn2_Pos                              2                                                         /*!< SCT OUTPUTSET8: SETn2 Position      */
#define SCT_OUTPUTSET8_SETn2_Msk                              (0x01UL << SCT_OUTPUTSET8_SETn2_Pos)                      /*!< SCT OUTPUTSET8: SETn2 Mask          */
#define SCT_OUTPUTSET8_SETn3_Pos                              3                                                         /*!< SCT OUTPUTSET8: SETn3 Position      */
#define SCT_OUTPUTSET8_SETn3_Msk                              (0x01UL << SCT_OUTPUTSET8_SETn3_Pos)                      /*!< SCT OUTPUTSET8: SETn3 Mask          */
#define SCT_OUTPUTSET8_SETn4_Pos                              4                                                         /*!< SCT OUTPUTSET8: SETn4 Position      */
#define SCT_OUTPUTSET8_SETn4_Msk                              (0x01UL << SCT_OUTPUTSET8_SETn4_Pos)                      /*!< SCT OUTPUTSET8: SETn4 Mask          */
#define SCT_OUTPUTSET8_SETn5_Pos                              5                                                         /*!< SCT OUTPUTSET8: SETn5 Position      */
#define SCT_OUTPUTSET8_SETn5_Msk                              (0x01UL << SCT_OUTPUTSET8_SETn5_Pos)                      /*!< SCT OUTPUTSET8: SETn5 Mask          */
#define SCT_OUTPUTSET8_SETn6_Pos                              6                                                         /*!< SCT OUTPUTSET8: SETn6 Position      */
#define SCT_OUTPUTSET8_SETn6_Msk                              (0x01UL << SCT_OUTPUTSET8_SETn6_Pos)                      /*!< SCT OUTPUTSET8: SETn6 Mask          */
#define SCT_OUTPUTSET8_SETn7_Pos                              7                                                         /*!< SCT OUTPUTSET8: SETn7 Position      */
#define SCT_OUTPUTSET8_SETn7_Msk                              (0x01UL << SCT_OUTPUTSET8_SETn7_Pos)                      /*!< SCT OUTPUTSET8: SETn7 Mask          */
#define SCT_OUTPUTSET8_SETn8_Pos                              8                                                         /*!< SCT OUTPUTSET8: SETn8 Position      */
#define SCT_OUTPUTSET8_SETn8_Msk                              (0x01UL << SCT_OUTPUTSET8_SETn8_Pos)                      /*!< SCT OUTPUTSET8: SETn8 Mask          */
#define SCT_OUTPUTSET8_SETn9_Pos                              9                                                         /*!< SCT OUTPUTSET8: SETn9 Position      */
#define SCT_OUTPUTSET8_SETn9_Msk                              (0x01UL << SCT_OUTPUTSET8_SETn9_Pos)                      /*!< SCT OUTPUTSET8: SETn9 Mask          */
#define SCT_OUTPUTSET8_SETn10_Pos                             10                                                        /*!< SCT OUTPUTSET8: SETn10 Position     */
#define SCT_OUTPUTSET8_SETn10_Msk                             (0x01UL << SCT_OUTPUTSET8_SETn10_Pos)                     /*!< SCT OUTPUTSET8: SETn10 Mask         */
#define SCT_OUTPUTSET8_SETn11_Pos                             11                                                        /*!< SCT OUTPUTSET8: SETn11 Position     */
#define SCT_OUTPUTSET8_SETn11_Msk                             (0x01UL << SCT_OUTPUTSET8_SETn11_Pos)                     /*!< SCT OUTPUTSET8: SETn11 Mask         */
#define SCT_OUTPUTSET8_SETn12_Pos                             12                                                        /*!< SCT OUTPUTSET8: SETn12 Position     */
#define SCT_OUTPUTSET8_SETn12_Msk                             (0x01UL << SCT_OUTPUTSET8_SETn12_Pos)                     /*!< SCT OUTPUTSET8: SETn12 Mask         */
#define SCT_OUTPUTSET8_SETn13_Pos                             13                                                        /*!< SCT OUTPUTSET8: SETn13 Position     */
#define SCT_OUTPUTSET8_SETn13_Msk                             (0x01UL << SCT_OUTPUTSET8_SETn13_Pos)                     /*!< SCT OUTPUTSET8: SETn13 Mask         */
#define SCT_OUTPUTSET8_SETn14_Pos                             14                                                        /*!< SCT OUTPUTSET8: SETn14 Position     */
#define SCT_OUTPUTSET8_SETn14_Msk                             (0x01UL << SCT_OUTPUTSET8_SETn14_Pos)                     /*!< SCT OUTPUTSET8: SETn14 Mask         */
#define SCT_OUTPUTSET8_SETn15_Pos                             15                                                        /*!< SCT OUTPUTSET8: SETn15 Position     */
#define SCT_OUTPUTSET8_SETn15_Msk                             (0x01UL << SCT_OUTPUTSET8_SETn15_Pos)                     /*!< SCT OUTPUTSET8: SETn15 Mask         */

// -------------------------------------  SCT_OUTPUTCLR8  -----------------------------------------
#define SCT_OUTPUTCLR8_CLRn0_Pos                              0                                                         /*!< SCT OUTPUTCLR8: CLRn0 Position      */
#define SCT_OUTPUTCLR8_CLRn0_Msk                              (0x01UL << SCT_OUTPUTCLR8_CLRn0_Pos)                      /*!< SCT OUTPUTCLR8: CLRn0 Mask          */
#define SCT_OUTPUTCLR8_CLRn1_Pos                              1                                                         /*!< SCT OUTPUTCLR8: CLRn1 Position      */
#define SCT_OUTPUTCLR8_CLRn1_Msk                              (0x01UL << SCT_OUTPUTCLR8_CLRn1_Pos)                      /*!< SCT OUTPUTCLR8: CLRn1 Mask          */
#define SCT_OUTPUTCLR8_CLRn2_Pos                              2                                                         /*!< SCT OUTPUTCLR8: CLRn2 Position      */
#define SCT_OUTPUTCLR8_CLRn2_Msk                              (0x01UL << SCT_OUTPUTCLR8_CLRn2_Pos)                      /*!< SCT OUTPUTCLR8: CLRn2 Mask          */
#define SCT_OUTPUTCLR8_CLRn3_Pos                              3                                                         /*!< SCT OUTPUTCLR8: CLRn3 Position      */
#define SCT_OUTPUTCLR8_CLRn3_Msk                              (0x01UL << SCT_OUTPUTCLR8_CLRn3_Pos)                      /*!< SCT OUTPUTCLR8: CLRn3 Mask          */
#define SCT_OUTPUTCLR8_CLRn4_Pos                              4                                                         /*!< SCT OUTPUTCLR8: CLRn4 Position      */
#define SCT_OUTPUTCLR8_CLRn4_Msk                              (0x01UL << SCT_OUTPUTCLR8_CLRn4_Pos)                      /*!< SCT OUTPUTCLR8: CLRn4 Mask          */
#define SCT_OUTPUTCLR8_CLRn5_Pos                              5                                                         /*!< SCT OUTPUTCLR8: CLRn5 Position      */
#define SCT_OUTPUTCLR8_CLRn5_Msk                              (0x01UL << SCT_OUTPUTCLR8_CLRn5_Pos)                      /*!< SCT OUTPUTCLR8: CLRn5 Mask          */
#define SCT_OUTPUTCLR8_CLRn6_Pos                              6                                                         /*!< SCT OUTPUTCLR8: CLRn6 Position      */
#define SCT_OUTPUTCLR8_CLRn6_Msk                              (0x01UL << SCT_OUTPUTCLR8_CLRn6_Pos)                      /*!< SCT OUTPUTCLR8: CLRn6 Mask          */
#define SCT_OUTPUTCLR8_CLRn7_Pos                              7                                                         /*!< SCT OUTPUTCLR8: CLRn7 Position      */
#define SCT_OUTPUTCLR8_CLRn7_Msk                              (0x01UL << SCT_OUTPUTCLR8_CLRn7_Pos)                      /*!< SCT OUTPUTCLR8: CLRn7 Mask          */
#define SCT_OUTPUTCLR8_CLRn8_Pos                              8                                                         /*!< SCT OUTPUTCLR8: CLRn8 Position      */
#define SCT_OUTPUTCLR8_CLRn8_Msk                              (0x01UL << SCT_OUTPUTCLR8_CLRn8_Pos)                      /*!< SCT OUTPUTCLR8: CLRn8 Mask          */
#define SCT_OUTPUTCLR8_CLRn9_Pos                              9                                                         /*!< SCT OUTPUTCLR8: CLRn9 Position      */
#define SCT_OUTPUTCLR8_CLRn9_Msk                              (0x01UL << SCT_OUTPUTCLR8_CLRn9_Pos)                      /*!< SCT OUTPUTCLR8: CLRn9 Mask          */
#define SCT_OUTPUTCLR8_CLRn10_Pos                             10                                                        /*!< SCT OUTPUTCLR8: CLRn10 Position     */
#define SCT_OUTPUTCLR8_CLRn10_Msk                             (0x01UL << SCT_OUTPUTCLR8_CLRn10_Pos)                     /*!< SCT OUTPUTCLR8: CLRn10 Mask         */
#define SCT_OUTPUTCLR8_CLRn11_Pos                             11                                                        /*!< SCT OUTPUTCLR8: CLRn11 Position     */
#define SCT_OUTPUTCLR8_CLRn11_Msk                             (0x01UL << SCT_OUTPUTCLR8_CLRn11_Pos)                     /*!< SCT OUTPUTCLR8: CLRn11 Mask         */
#define SCT_OUTPUTCLR8_CLRn12_Pos                             12                                                        /*!< SCT OUTPUTCLR8: CLRn12 Position     */
#define SCT_OUTPUTCLR8_CLRn12_Msk                             (0x01UL << SCT_OUTPUTCLR8_CLRn12_Pos)                     /*!< SCT OUTPUTCLR8: CLRn12 Mask         */
#define SCT_OUTPUTCLR8_CLRn13_Pos                             13                                                        /*!< SCT OUTPUTCLR8: CLRn13 Position     */
#define SCT_OUTPUTCLR8_CLRn13_Msk                             (0x01UL << SCT_OUTPUTCLR8_CLRn13_Pos)                     /*!< SCT OUTPUTCLR8: CLRn13 Mask         */
#define SCT_OUTPUTCLR8_CLRn14_Pos                             14                                                        /*!< SCT OUTPUTCLR8: CLRn14 Position     */
#define SCT_OUTPUTCLR8_CLRn14_Msk                             (0x01UL << SCT_OUTPUTCLR8_CLRn14_Pos)                     /*!< SCT OUTPUTCLR8: CLRn14 Mask         */
#define SCT_OUTPUTCLR8_CLRn15_Pos                             15                                                        /*!< SCT OUTPUTCLR8: CLRn15 Position     */
#define SCT_OUTPUTCLR8_CLRn15_Msk                             (0x01UL << SCT_OUTPUTCLR8_CLRn15_Pos)                     /*!< SCT OUTPUTCLR8: CLRn15 Mask         */

// -------------------------------------  SCT_OUTPUTSET9  -----------------------------------------
#define SCT_OUTPUTSET9_SETn0_Pos                              0                                                         /*!< SCT OUTPUTSET9: SETn0 Position      */
#define SCT_OUTPUTSET9_SETn0_Msk                              (0x01UL << SCT_OUTPUTSET9_SETn0_Pos)                      /*!< SCT OUTPUTSET9: SETn0 Mask          */
#define SCT_OUTPUTSET9_SETn1_Pos                              1                                                         /*!< SCT OUTPUTSET9: SETn1 Position      */
#define SCT_OUTPUTSET9_SETn1_Msk                              (0x01UL << SCT_OUTPUTSET9_SETn1_Pos)                      /*!< SCT OUTPUTSET9: SETn1 Mask          */
#define SCT_OUTPUTSET9_SETn2_Pos                              2                                                         /*!< SCT OUTPUTSET9: SETn2 Position      */
#define SCT_OUTPUTSET9_SETn2_Msk                              (0x01UL << SCT_OUTPUTSET9_SETn2_Pos)                      /*!< SCT OUTPUTSET9: SETn2 Mask          */
#define SCT_OUTPUTSET9_SETn3_Pos                              3                                                         /*!< SCT OUTPUTSET9: SETn3 Position      */
#define SCT_OUTPUTSET9_SETn3_Msk                              (0x01UL << SCT_OUTPUTSET9_SETn3_Pos)                      /*!< SCT OUTPUTSET9: SETn3 Mask          */
#define SCT_OUTPUTSET9_SETn4_Pos                              4                                                         /*!< SCT OUTPUTSET9: SETn4 Position      */
#define SCT_OUTPUTSET9_SETn4_Msk                              (0x01UL << SCT_OUTPUTSET9_SETn4_Pos)                      /*!< SCT OUTPUTSET9: SETn4 Mask          */
#define SCT_OUTPUTSET9_SETn5_Pos                              5                                                         /*!< SCT OUTPUTSET9: SETn5 Position      */
#define SCT_OUTPUTSET9_SETn5_Msk                              (0x01UL << SCT_OUTPUTSET9_SETn5_Pos)                      /*!< SCT OUTPUTSET9: SETn5 Mask          */
#define SCT_OUTPUTSET9_SETn6_Pos                              6                                                         /*!< SCT OUTPUTSET9: SETn6 Position      */
#define SCT_OUTPUTSET9_SETn6_Msk                              (0x01UL << SCT_OUTPUTSET9_SETn6_Pos)                      /*!< SCT OUTPUTSET9: SETn6 Mask          */
#define SCT_OUTPUTSET9_SETn7_Pos                              7                                                         /*!< SCT OUTPUTSET9: SETn7 Position      */
#define SCT_OUTPUTSET9_SETn7_Msk                              (0x01UL << SCT_OUTPUTSET9_SETn7_Pos)                      /*!< SCT OUTPUTSET9: SETn7 Mask          */
#define SCT_OUTPUTSET9_SETn8_Pos                              8                                                         /*!< SCT OUTPUTSET9: SETn8 Position      */
#define SCT_OUTPUTSET9_SETn8_Msk                              (0x01UL << SCT_OUTPUTSET9_SETn8_Pos)                      /*!< SCT OUTPUTSET9: SETn8 Mask          */
#define SCT_OUTPUTSET9_SETn9_Pos                              9                                                         /*!< SCT OUTPUTSET9: SETn9 Position      */
#define SCT_OUTPUTSET9_SETn9_Msk                              (0x01UL << SCT_OUTPUTSET9_SETn9_Pos)                      /*!< SCT OUTPUTSET9: SETn9 Mask          */
#define SCT_OUTPUTSET9_SETn10_Pos                             10                                                        /*!< SCT OUTPUTSET9: SETn10 Position     */
#define SCT_OUTPUTSET9_SETn10_Msk                             (0x01UL << SCT_OUTPUTSET9_SETn10_Pos)                     /*!< SCT OUTPUTSET9: SETn10 Mask         */
#define SCT_OUTPUTSET9_SETn11_Pos                             11                                                        /*!< SCT OUTPUTSET9: SETn11 Position     */
#define SCT_OUTPUTSET9_SETn11_Msk                             (0x01UL << SCT_OUTPUTSET9_SETn11_Pos)                     /*!< SCT OUTPUTSET9: SETn11 Mask         */
#define SCT_OUTPUTSET9_SETn12_Pos                             12                                                        /*!< SCT OUTPUTSET9: SETn12 Position     */
#define SCT_OUTPUTSET9_SETn12_Msk                             (0x01UL << SCT_OUTPUTSET9_SETn12_Pos)                     /*!< SCT OUTPUTSET9: SETn12 Mask         */
#define SCT_OUTPUTSET9_SETn13_Pos                             13                                                        /*!< SCT OUTPUTSET9: SETn13 Position     */
#define SCT_OUTPUTSET9_SETn13_Msk                             (0x01UL << SCT_OUTPUTSET9_SETn13_Pos)                     /*!< SCT OUTPUTSET9: SETn13 Mask         */
#define SCT_OUTPUTSET9_SETn14_Pos                             14                                                        /*!< SCT OUTPUTSET9: SETn14 Position     */
#define SCT_OUTPUTSET9_SETn14_Msk                             (0x01UL << SCT_OUTPUTSET9_SETn14_Pos)                     /*!< SCT OUTPUTSET9: SETn14 Mask         */
#define SCT_OUTPUTSET9_SETn15_Pos                             15                                                        /*!< SCT OUTPUTSET9: SETn15 Position     */
#define SCT_OUTPUTSET9_SETn15_Msk                             (0x01UL << SCT_OUTPUTSET9_SETn15_Pos)                     /*!< SCT OUTPUTSET9: SETn15 Mask         */

// -------------------------------------  SCT_OUTPUTCLR9  -----------------------------------------
#define SCT_OUTPUTCLR9_CLRn0_Pos                              0                                                         /*!< SCT OUTPUTCLR9: CLRn0 Position      */
#define SCT_OUTPUTCLR9_CLRn0_Msk                              (0x01UL << SCT_OUTPUTCLR9_CLRn0_Pos)                      /*!< SCT OUTPUTCLR9: CLRn0 Mask          */
#define SCT_OUTPUTCLR9_CLRn1_Pos                              1                                                         /*!< SCT OUTPUTCLR9: CLRn1 Position      */
#define SCT_OUTPUTCLR9_CLRn1_Msk                              (0x01UL << SCT_OUTPUTCLR9_CLRn1_Pos)                      /*!< SCT OUTPUTCLR9: CLRn1 Mask          */
#define SCT_OUTPUTCLR9_CLRn2_Pos                              2                                                         /*!< SCT OUTPUTCLR9: CLRn2 Position      */
#define SCT_OUTPUTCLR9_CLRn2_Msk                              (0x01UL << SCT_OUTPUTCLR9_CLRn2_Pos)                      /*!< SCT OUTPUTCLR9: CLRn2 Mask          */
#define SCT_OUTPUTCLR9_CLRn3_Pos                              3                                                         /*!< SCT OUTPUTCLR9: CLRn3 Position      */
#define SCT_OUTPUTCLR9_CLRn3_Msk                              (0x01UL << SCT_OUTPUTCLR9_CLRn3_Pos)                      /*!< SCT OUTPUTCLR9: CLRn3 Mask          */
#define SCT_OUTPUTCLR9_CLRn4_Pos                              4                                                         /*!< SCT OUTPUTCLR9: CLRn4 Position      */
#define SCT_OUTPUTCLR9_CLRn4_Msk                              (0x01UL << SCT_OUTPUTCLR9_CLRn4_Pos)                      /*!< SCT OUTPUTCLR9: CLRn4 Mask          */
#define SCT_OUTPUTCLR9_CLRn5_Pos                              5                                                         /*!< SCT OUTPUTCLR9: CLRn5 Position      */
#define SCT_OUTPUTCLR9_CLRn5_Msk                              (0x01UL << SCT_OUTPUTCLR9_CLRn5_Pos)                      /*!< SCT OUTPUTCLR9: CLRn5 Mask          */
#define SCT_OUTPUTCLR9_CLRn6_Pos                              6                                                         /*!< SCT OUTPUTCLR9: CLRn6 Position      */
#define SCT_OUTPUTCLR9_CLRn6_Msk                              (0x01UL << SCT_OUTPUTCLR9_CLRn6_Pos)                      /*!< SCT OUTPUTCLR9: CLRn6 Mask          */
#define SCT_OUTPUTCLR9_CLRn7_Pos                              7                                                         /*!< SCT OUTPUTCLR9: CLRn7 Position      */
#define SCT_OUTPUTCLR9_CLRn7_Msk                              (0x01UL << SCT_OUTPUTCLR9_CLRn7_Pos)                      /*!< SCT OUTPUTCLR9: CLRn7 Mask          */
#define SCT_OUTPUTCLR9_CLRn8_Pos                              8                                                         /*!< SCT OUTPUTCLR9: CLRn8 Position      */
#define SCT_OUTPUTCLR9_CLRn8_Msk                              (0x01UL << SCT_OUTPUTCLR9_CLRn8_Pos)                      /*!< SCT OUTPUTCLR9: CLRn8 Mask          */
#define SCT_OUTPUTCLR9_CLRn9_Pos                              9                                                         /*!< SCT OUTPUTCLR9: CLRn9 Position      */
#define SCT_OUTPUTCLR9_CLRn9_Msk                              (0x01UL << SCT_OUTPUTCLR9_CLRn9_Pos)                      /*!< SCT OUTPUTCLR9: CLRn9 Mask          */
#define SCT_OUTPUTCLR9_CLRn10_Pos                             10                                                        /*!< SCT OUTPUTCLR9: CLRn10 Position     */
#define SCT_OUTPUTCLR9_CLRn10_Msk                             (0x01UL << SCT_OUTPUTCLR9_CLRn10_Pos)                     /*!< SCT OUTPUTCLR9: CLRn10 Mask         */
#define SCT_OUTPUTCLR9_CLRn11_Pos                             11                                                        /*!< SCT OUTPUTCLR9: CLRn11 Position     */
#define SCT_OUTPUTCLR9_CLRn11_Msk                             (0x01UL << SCT_OUTPUTCLR9_CLRn11_Pos)                     /*!< SCT OUTPUTCLR9: CLRn11 Mask         */
#define SCT_OUTPUTCLR9_CLRn12_Pos                             12                                                        /*!< SCT OUTPUTCLR9: CLRn12 Position     */
#define SCT_OUTPUTCLR9_CLRn12_Msk                             (0x01UL << SCT_OUTPUTCLR9_CLRn12_Pos)                     /*!< SCT OUTPUTCLR9: CLRn12 Mask         */
#define SCT_OUTPUTCLR9_CLRn13_Pos                             13                                                        /*!< SCT OUTPUTCLR9: CLRn13 Position     */
#define SCT_OUTPUTCLR9_CLRn13_Msk                             (0x01UL << SCT_OUTPUTCLR9_CLRn13_Pos)                     /*!< SCT OUTPUTCLR9: CLRn13 Mask         */
#define SCT_OUTPUTCLR9_CLRn14_Pos                             14                                                        /*!< SCT OUTPUTCLR9: CLRn14 Position     */
#define SCT_OUTPUTCLR9_CLRn14_Msk                             (0x01UL << SCT_OUTPUTCLR9_CLRn14_Pos)                     /*!< SCT OUTPUTCLR9: CLRn14 Mask         */
#define SCT_OUTPUTCLR9_CLRn15_Pos                             15                                                        /*!< SCT OUTPUTCLR9: CLRn15 Position     */
#define SCT_OUTPUTCLR9_CLRn15_Msk                             (0x01UL << SCT_OUTPUTCLR9_CLRn15_Pos)                     /*!< SCT OUTPUTCLR9: CLRn15 Mask         */

// -------------------------------------  SCT_OUTPUTSET10  ----------------------------------------
#define SCT_OUTPUTSET10_SETn0_Pos                             0                                                         /*!< SCT OUTPUTSET10: SETn0 Position     */
#define SCT_OUTPUTSET10_SETn0_Msk                             (0x01UL << SCT_OUTPUTSET10_SETn0_Pos)                     /*!< SCT OUTPUTSET10: SETn0 Mask         */
#define SCT_OUTPUTSET10_SETn1_Pos                             1                                                         /*!< SCT OUTPUTSET10: SETn1 Position     */
#define SCT_OUTPUTSET10_SETn1_Msk                             (0x01UL << SCT_OUTPUTSET10_SETn1_Pos)                     /*!< SCT OUTPUTSET10: SETn1 Mask         */
#define SCT_OUTPUTSET10_SETn2_Pos                             2                                                         /*!< SCT OUTPUTSET10: SETn2 Position     */
#define SCT_OUTPUTSET10_SETn2_Msk                             (0x01UL << SCT_OUTPUTSET10_SETn2_Pos)                     /*!< SCT OUTPUTSET10: SETn2 Mask         */
#define SCT_OUTPUTSET10_SETn3_Pos                             3                                                         /*!< SCT OUTPUTSET10: SETn3 Position     */
#define SCT_OUTPUTSET10_SETn3_Msk                             (0x01UL << SCT_OUTPUTSET10_SETn3_Pos)                     /*!< SCT OUTPUTSET10: SETn3 Mask         */
#define SCT_OUTPUTSET10_SETn4_Pos                             4                                                         /*!< SCT OUTPUTSET10: SETn4 Position     */
#define SCT_OUTPUTSET10_SETn4_Msk                             (0x01UL << SCT_OUTPUTSET10_SETn4_Pos)                     /*!< SCT OUTPUTSET10: SETn4 Mask         */
#define SCT_OUTPUTSET10_SETn5_Pos                             5                                                         /*!< SCT OUTPUTSET10: SETn5 Position     */
#define SCT_OUTPUTSET10_SETn5_Msk                             (0x01UL << SCT_OUTPUTSET10_SETn5_Pos)                     /*!< SCT OUTPUTSET10: SETn5 Mask         */
#define SCT_OUTPUTSET10_SETn6_Pos                             6                                                         /*!< SCT OUTPUTSET10: SETn6 Position     */
#define SCT_OUTPUTSET10_SETn6_Msk                             (0x01UL << SCT_OUTPUTSET10_SETn6_Pos)                     /*!< SCT OUTPUTSET10: SETn6 Mask         */
#define SCT_OUTPUTSET10_SETn7_Pos                             7                                                         /*!< SCT OUTPUTSET10: SETn7 Position     */
#define SCT_OUTPUTSET10_SETn7_Msk                             (0x01UL << SCT_OUTPUTSET10_SETn7_Pos)                     /*!< SCT OUTPUTSET10: SETn7 Mask         */
#define SCT_OUTPUTSET10_SETn8_Pos                             8                                                         /*!< SCT OUTPUTSET10: SETn8 Position     */
#define SCT_OUTPUTSET10_SETn8_Msk                             (0x01UL << SCT_OUTPUTSET10_SETn8_Pos)                     /*!< SCT OUTPUTSET10: SETn8 Mask         */
#define SCT_OUTPUTSET10_SETn9_Pos                             9                                                         /*!< SCT OUTPUTSET10: SETn9 Position     */
#define SCT_OUTPUTSET10_SETn9_Msk                             (0x01UL << SCT_OUTPUTSET10_SETn9_Pos)                     /*!< SCT OUTPUTSET10: SETn9 Mask         */
#define SCT_OUTPUTSET10_SETn10_Pos                            10                                                        /*!< SCT OUTPUTSET10: SETn10 Position    */
#define SCT_OUTPUTSET10_SETn10_Msk                            (0x01UL << SCT_OUTPUTSET10_SETn10_Pos)                    /*!< SCT OUTPUTSET10: SETn10 Mask        */
#define SCT_OUTPUTSET10_SETn11_Pos                            11                                                        /*!< SCT OUTPUTSET10: SETn11 Position    */
#define SCT_OUTPUTSET10_SETn11_Msk                            (0x01UL << SCT_OUTPUTSET10_SETn11_Pos)                    /*!< SCT OUTPUTSET10: SETn11 Mask        */
#define SCT_OUTPUTSET10_SETn12_Pos                            12                                                        /*!< SCT OUTPUTSET10: SETn12 Position    */
#define SCT_OUTPUTSET10_SETn12_Msk                            (0x01UL << SCT_OUTPUTSET10_SETn12_Pos)                    /*!< SCT OUTPUTSET10: SETn12 Mask        */
#define SCT_OUTPUTSET10_SETn13_Pos                            13                                                        /*!< SCT OUTPUTSET10: SETn13 Position    */
#define SCT_OUTPUTSET10_SETn13_Msk                            (0x01UL << SCT_OUTPUTSET10_SETn13_Pos)                    /*!< SCT OUTPUTSET10: SETn13 Mask        */
#define SCT_OUTPUTSET10_SETn14_Pos                            14                                                        /*!< SCT OUTPUTSET10: SETn14 Position    */
#define SCT_OUTPUTSET10_SETn14_Msk                            (0x01UL << SCT_OUTPUTSET10_SETn14_Pos)                    /*!< SCT OUTPUTSET10: SETn14 Mask        */
#define SCT_OUTPUTSET10_SETn15_Pos                            15                                                        /*!< SCT OUTPUTSET10: SETn15 Position    */
#define SCT_OUTPUTSET10_SETn15_Msk                            (0x01UL << SCT_OUTPUTSET10_SETn15_Pos)                    /*!< SCT OUTPUTSET10: SETn15 Mask        */

// -------------------------------------  SCT_OUTPUTCLR10  ----------------------------------------
#define SCT_OUTPUTCLR10_CLRn0_Pos                             0                                                         /*!< SCT OUTPUTCLR10: CLRn0 Position     */
#define SCT_OUTPUTCLR10_CLRn0_Msk                             (0x01UL << SCT_OUTPUTCLR10_CLRn0_Pos)                     /*!< SCT OUTPUTCLR10: CLRn0 Mask         */
#define SCT_OUTPUTCLR10_CLRn1_Pos                             1                                                         /*!< SCT OUTPUTCLR10: CLRn1 Position     */
#define SCT_OUTPUTCLR10_CLRn1_Msk                             (0x01UL << SCT_OUTPUTCLR10_CLRn1_Pos)                     /*!< SCT OUTPUTCLR10: CLRn1 Mask         */
#define SCT_OUTPUTCLR10_CLRn2_Pos                             2                                                         /*!< SCT OUTPUTCLR10: CLRn2 Position     */
#define SCT_OUTPUTCLR10_CLRn2_Msk                             (0x01UL << SCT_OUTPUTCLR10_CLRn2_Pos)                     /*!< SCT OUTPUTCLR10: CLRn2 Mask         */
#define SCT_OUTPUTCLR10_CLRn3_Pos                             3                                                         /*!< SCT OUTPUTCLR10: CLRn3 Position     */
#define SCT_OUTPUTCLR10_CLRn3_Msk                             (0x01UL << SCT_OUTPUTCLR10_CLRn3_Pos)                     /*!< SCT OUTPUTCLR10: CLRn3 Mask         */
#define SCT_OUTPUTCLR10_CLRn4_Pos                             4                                                         /*!< SCT OUTPUTCLR10: CLRn4 Position     */
#define SCT_OUTPUTCLR10_CLRn4_Msk                             (0x01UL << SCT_OUTPUTCLR10_CLRn4_Pos)                     /*!< SCT OUTPUTCLR10: CLRn4 Mask         */
#define SCT_OUTPUTCLR10_CLRn5_Pos                             5                                                         /*!< SCT OUTPUTCLR10: CLRn5 Position     */
#define SCT_OUTPUTCLR10_CLRn5_Msk                             (0x01UL << SCT_OUTPUTCLR10_CLRn5_Pos)                     /*!< SCT OUTPUTCLR10: CLRn5 Mask         */
#define SCT_OUTPUTCLR10_CLRn6_Pos                             6                                                         /*!< SCT OUTPUTCLR10: CLRn6 Position     */
#define SCT_OUTPUTCLR10_CLRn6_Msk                             (0x01UL << SCT_OUTPUTCLR10_CLRn6_Pos)                     /*!< SCT OUTPUTCLR10: CLRn6 Mask         */
#define SCT_OUTPUTCLR10_CLRn7_Pos                             7                                                         /*!< SCT OUTPUTCLR10: CLRn7 Position     */
#define SCT_OUTPUTCLR10_CLRn7_Msk                             (0x01UL << SCT_OUTPUTCLR10_CLRn7_Pos)                     /*!< SCT OUTPUTCLR10: CLRn7 Mask         */
#define SCT_OUTPUTCLR10_CLRn8_Pos                             8                                                         /*!< SCT OUTPUTCLR10: CLRn8 Position     */
#define SCT_OUTPUTCLR10_CLRn8_Msk                             (0x01UL << SCT_OUTPUTCLR10_CLRn8_Pos)                     /*!< SCT OUTPUTCLR10: CLRn8 Mask         */
#define SCT_OUTPUTCLR10_CLRn9_Pos                             9                                                         /*!< SCT OUTPUTCLR10: CLRn9 Position     */
#define SCT_OUTPUTCLR10_CLRn9_Msk                             (0x01UL << SCT_OUTPUTCLR10_CLRn9_Pos)                     /*!< SCT OUTPUTCLR10: CLRn9 Mask         */
#define SCT_OUTPUTCLR10_CLRn10_Pos                            10                                                        /*!< SCT OUTPUTCLR10: CLRn10 Position    */
#define SCT_OUTPUTCLR10_CLRn10_Msk                            (0x01UL << SCT_OUTPUTCLR10_CLRn10_Pos)                    /*!< SCT OUTPUTCLR10: CLRn10 Mask        */
#define SCT_OUTPUTCLR10_CLRn11_Pos                            11                                                        /*!< SCT OUTPUTCLR10: CLRn11 Position    */
#define SCT_OUTPUTCLR10_CLRn11_Msk                            (0x01UL << SCT_OUTPUTCLR10_CLRn11_Pos)                    /*!< SCT OUTPUTCLR10: CLRn11 Mask        */
#define SCT_OUTPUTCLR10_CLRn12_Pos                            12                                                        /*!< SCT OUTPUTCLR10: CLRn12 Position    */
#define SCT_OUTPUTCLR10_CLRn12_Msk                            (0x01UL << SCT_OUTPUTCLR10_CLRn12_Pos)                    /*!< SCT OUTPUTCLR10: CLRn12 Mask        */
#define SCT_OUTPUTCLR10_CLRn13_Pos                            13                                                        /*!< SCT OUTPUTCLR10: CLRn13 Position    */
#define SCT_OUTPUTCLR10_CLRn13_Msk                            (0x01UL << SCT_OUTPUTCLR10_CLRn13_Pos)                    /*!< SCT OUTPUTCLR10: CLRn13 Mask        */
#define SCT_OUTPUTCLR10_CLRn14_Pos                            14                                                        /*!< SCT OUTPUTCLR10: CLRn14 Position    */
#define SCT_OUTPUTCLR10_CLRn14_Msk                            (0x01UL << SCT_OUTPUTCLR10_CLRn14_Pos)                    /*!< SCT OUTPUTCLR10: CLRn14 Mask        */
#define SCT_OUTPUTCLR10_CLRn15_Pos                            15                                                        /*!< SCT OUTPUTCLR10: CLRn15 Position    */
#define SCT_OUTPUTCLR10_CLRn15_Msk                            (0x01UL << SCT_OUTPUTCLR10_CLRn15_Pos)                    /*!< SCT OUTPUTCLR10: CLRn15 Mask        */

// -------------------------------------  SCT_OUTPUTSET11  ----------------------------------------
#define SCT_OUTPUTSET11_SETn0_Pos                             0                                                         /*!< SCT OUTPUTSET11: SETn0 Position     */
#define SCT_OUTPUTSET11_SETn0_Msk                             (0x01UL << SCT_OUTPUTSET11_SETn0_Pos)                     /*!< SCT OUTPUTSET11: SETn0 Mask         */
#define SCT_OUTPUTSET11_SETn1_Pos                             1                                                         /*!< SCT OUTPUTSET11: SETn1 Position     */
#define SCT_OUTPUTSET11_SETn1_Msk                             (0x01UL << SCT_OUTPUTSET11_SETn1_Pos)                     /*!< SCT OUTPUTSET11: SETn1 Mask         */
#define SCT_OUTPUTSET11_SETn2_Pos                             2                                                         /*!< SCT OUTPUTSET11: SETn2 Position     */
#define SCT_OUTPUTSET11_SETn2_Msk                             (0x01UL << SCT_OUTPUTSET11_SETn2_Pos)                     /*!< SCT OUTPUTSET11: SETn2 Mask         */
#define SCT_OUTPUTSET11_SETn3_Pos                             3                                                         /*!< SCT OUTPUTSET11: SETn3 Position     */
#define SCT_OUTPUTSET11_SETn3_Msk                             (0x01UL << SCT_OUTPUTSET11_SETn3_Pos)                     /*!< SCT OUTPUTSET11: SETn3 Mask         */
#define SCT_OUTPUTSET11_SETn4_Pos                             4                                                         /*!< SCT OUTPUTSET11: SETn4 Position     */
#define SCT_OUTPUTSET11_SETn4_Msk                             (0x01UL << SCT_OUTPUTSET11_SETn4_Pos)                     /*!< SCT OUTPUTSET11: SETn4 Mask         */
#define SCT_OUTPUTSET11_SETn5_Pos                             5                                                         /*!< SCT OUTPUTSET11: SETn5 Position     */
#define SCT_OUTPUTSET11_SETn5_Msk                             (0x01UL << SCT_OUTPUTSET11_SETn5_Pos)                     /*!< SCT OUTPUTSET11: SETn5 Mask         */
#define SCT_OUTPUTSET11_SETn6_Pos                             6                                                         /*!< SCT OUTPUTSET11: SETn6 Position     */
#define SCT_OUTPUTSET11_SETn6_Msk                             (0x01UL << SCT_OUTPUTSET11_SETn6_Pos)                     /*!< SCT OUTPUTSET11: SETn6 Mask         */
#define SCT_OUTPUTSET11_SETn7_Pos                             7                                                         /*!< SCT OUTPUTSET11: SETn7 Position     */
#define SCT_OUTPUTSET11_SETn7_Msk                             (0x01UL << SCT_OUTPUTSET11_SETn7_Pos)                     /*!< SCT OUTPUTSET11: SETn7 Mask         */
#define SCT_OUTPUTSET11_SETn8_Pos                             8                                                         /*!< SCT OUTPUTSET11: SETn8 Position     */
#define SCT_OUTPUTSET11_SETn8_Msk                             (0x01UL << SCT_OUTPUTSET11_SETn8_Pos)                     /*!< SCT OUTPUTSET11: SETn8 Mask         */
#define SCT_OUTPUTSET11_SETn9_Pos                             9                                                         /*!< SCT OUTPUTSET11: SETn9 Position     */
#define SCT_OUTPUTSET11_SETn9_Msk                             (0x01UL << SCT_OUTPUTSET11_SETn9_Pos)                     /*!< SCT OUTPUTSET11: SETn9 Mask         */
#define SCT_OUTPUTSET11_SETn10_Pos                            10                                                        /*!< SCT OUTPUTSET11: SETn10 Position    */
#define SCT_OUTPUTSET11_SETn10_Msk                            (0x01UL << SCT_OUTPUTSET11_SETn10_Pos)                    /*!< SCT OUTPUTSET11: SETn10 Mask        */
#define SCT_OUTPUTSET11_SETn11_Pos                            11                                                        /*!< SCT OUTPUTSET11: SETn11 Position    */
#define SCT_OUTPUTSET11_SETn11_Msk                            (0x01UL << SCT_OUTPUTSET11_SETn11_Pos)                    /*!< SCT OUTPUTSET11: SETn11 Mask        */
#define SCT_OUTPUTSET11_SETn12_Pos                            12                                                        /*!< SCT OUTPUTSET11: SETn12 Position    */
#define SCT_OUTPUTSET11_SETn12_Msk                            (0x01UL << SCT_OUTPUTSET11_SETn12_Pos)                    /*!< SCT OUTPUTSET11: SETn12 Mask        */
#define SCT_OUTPUTSET11_SETn13_Pos                            13                                                        /*!< SCT OUTPUTSET11: SETn13 Position    */
#define SCT_OUTPUTSET11_SETn13_Msk                            (0x01UL << SCT_OUTPUTSET11_SETn13_Pos)                    /*!< SCT OUTPUTSET11: SETn13 Mask        */
#define SCT_OUTPUTSET11_SETn14_Pos                            14                                                        /*!< SCT OUTPUTSET11: SETn14 Position    */
#define SCT_OUTPUTSET11_SETn14_Msk                            (0x01UL << SCT_OUTPUTSET11_SETn14_Pos)                    /*!< SCT OUTPUTSET11: SETn14 Mask        */
#define SCT_OUTPUTSET11_SETn15_Pos                            15                                                        /*!< SCT OUTPUTSET11: SETn15 Position    */
#define SCT_OUTPUTSET11_SETn15_Msk                            (0x01UL << SCT_OUTPUTSET11_SETn15_Pos)                    /*!< SCT OUTPUTSET11: SETn15 Mask        */

// -------------------------------------  SCT_OUTPUTCLR11  ----------------------------------------
#define SCT_OUTPUTCLR11_CLRn0_Pos                             0                                                         /*!< SCT OUTPUTCLR11: CLRn0 Position     */
#define SCT_OUTPUTCLR11_CLRn0_Msk                             (0x01UL << SCT_OUTPUTCLR11_CLRn0_Pos)                     /*!< SCT OUTPUTCLR11: CLRn0 Mask         */
#define SCT_OUTPUTCLR11_CLRn1_Pos                             1                                                         /*!< SCT OUTPUTCLR11: CLRn1 Position     */
#define SCT_OUTPUTCLR11_CLRn1_Msk                             (0x01UL << SCT_OUTPUTCLR11_CLRn1_Pos)                     /*!< SCT OUTPUTCLR11: CLRn1 Mask         */
#define SCT_OUTPUTCLR11_CLRn2_Pos                             2                                                         /*!< SCT OUTPUTCLR11: CLRn2 Position     */
#define SCT_OUTPUTCLR11_CLRn2_Msk                             (0x01UL << SCT_OUTPUTCLR11_CLRn2_Pos)                     /*!< SCT OUTPUTCLR11: CLRn2 Mask         */
#define SCT_OUTPUTCLR11_CLRn3_Pos                             3                                                         /*!< SCT OUTPUTCLR11: CLRn3 Position     */
#define SCT_OUTPUTCLR11_CLRn3_Msk                             (0x01UL << SCT_OUTPUTCLR11_CLRn3_Pos)                     /*!< SCT OUTPUTCLR11: CLRn3 Mask         */
#define SCT_OUTPUTCLR11_CLRn4_Pos                             4                                                         /*!< SCT OUTPUTCLR11: CLRn4 Position     */
#define SCT_OUTPUTCLR11_CLRn4_Msk                             (0x01UL << SCT_OUTPUTCLR11_CLRn4_Pos)                     /*!< SCT OUTPUTCLR11: CLRn4 Mask         */
#define SCT_OUTPUTCLR11_CLRn5_Pos                             5                                                         /*!< SCT OUTPUTCLR11: CLRn5 Position     */
#define SCT_OUTPUTCLR11_CLRn5_Msk                             (0x01UL << SCT_OUTPUTCLR11_CLRn5_Pos)                     /*!< SCT OUTPUTCLR11: CLRn5 Mask         */
#define SCT_OUTPUTCLR11_CLRn6_Pos                             6                                                         /*!< SCT OUTPUTCLR11: CLRn6 Position     */
#define SCT_OUTPUTCLR11_CLRn6_Msk                             (0x01UL << SCT_OUTPUTCLR11_CLRn6_Pos)                     /*!< SCT OUTPUTCLR11: CLRn6 Mask         */
#define SCT_OUTPUTCLR11_CLRn7_Pos                             7                                                         /*!< SCT OUTPUTCLR11: CLRn7 Position     */
#define SCT_OUTPUTCLR11_CLRn7_Msk                             (0x01UL << SCT_OUTPUTCLR11_CLRn7_Pos)                     /*!< SCT OUTPUTCLR11: CLRn7 Mask         */
#define SCT_OUTPUTCLR11_CLRn8_Pos                             8                                                         /*!< SCT OUTPUTCLR11: CLRn8 Position     */
#define SCT_OUTPUTCLR11_CLRn8_Msk                             (0x01UL << SCT_OUTPUTCLR11_CLRn8_Pos)                     /*!< SCT OUTPUTCLR11: CLRn8 Mask         */
#define SCT_OUTPUTCLR11_CLRn9_Pos                             9                                                         /*!< SCT OUTPUTCLR11: CLRn9 Position     */
#define SCT_OUTPUTCLR11_CLRn9_Msk                             (0x01UL << SCT_OUTPUTCLR11_CLRn9_Pos)                     /*!< SCT OUTPUTCLR11: CLRn9 Mask         */
#define SCT_OUTPUTCLR11_CLRn10_Pos                            10                                                        /*!< SCT OUTPUTCLR11: CLRn10 Position    */
#define SCT_OUTPUTCLR11_CLRn10_Msk                            (0x01UL << SCT_OUTPUTCLR11_CLRn10_Pos)                    /*!< SCT OUTPUTCLR11: CLRn10 Mask        */
#define SCT_OUTPUTCLR11_CLRn11_Pos                            11                                                        /*!< SCT OUTPUTCLR11: CLRn11 Position    */
#define SCT_OUTPUTCLR11_CLRn11_Msk                            (0x01UL << SCT_OUTPUTCLR11_CLRn11_Pos)                    /*!< SCT OUTPUTCLR11: CLRn11 Mask        */
#define SCT_OUTPUTCLR11_CLRn12_Pos                            12                                                        /*!< SCT OUTPUTCLR11: CLRn12 Position    */
#define SCT_OUTPUTCLR11_CLRn12_Msk                            (0x01UL << SCT_OUTPUTCLR11_CLRn12_Pos)                    /*!< SCT OUTPUTCLR11: CLRn12 Mask        */
#define SCT_OUTPUTCLR11_CLRn13_Pos                            13                                                        /*!< SCT OUTPUTCLR11: CLRn13 Position    */
#define SCT_OUTPUTCLR11_CLRn13_Msk                            (0x01UL << SCT_OUTPUTCLR11_CLRn13_Pos)                    /*!< SCT OUTPUTCLR11: CLRn13 Mask        */
#define SCT_OUTPUTCLR11_CLRn14_Pos                            14                                                        /*!< SCT OUTPUTCLR11: CLRn14 Position    */
#define SCT_OUTPUTCLR11_CLRn14_Msk                            (0x01UL << SCT_OUTPUTCLR11_CLRn14_Pos)                    /*!< SCT OUTPUTCLR11: CLRn14 Mask        */
#define SCT_OUTPUTCLR11_CLRn15_Pos                            15                                                        /*!< SCT OUTPUTCLR11: CLRn15 Position    */
#define SCT_OUTPUTCLR11_CLRn15_Msk                            (0x01UL << SCT_OUTPUTCLR11_CLRn15_Pos)                    /*!< SCT OUTPUTCLR11: CLRn15 Mask        */

// -------------------------------------  SCT_OUTPUTSET12  ----------------------------------------
#define SCT_OUTPUTSET12_SETn0_Pos                             0                                                         /*!< SCT OUTPUTSET12: SETn0 Position     */
#define SCT_OUTPUTSET12_SETn0_Msk                             (0x01UL << SCT_OUTPUTSET12_SETn0_Pos)                     /*!< SCT OUTPUTSET12: SETn0 Mask         */
#define SCT_OUTPUTSET12_SETn1_Pos                             1                                                         /*!< SCT OUTPUTSET12: SETn1 Position     */
#define SCT_OUTPUTSET12_SETn1_Msk                             (0x01UL << SCT_OUTPUTSET12_SETn1_Pos)                     /*!< SCT OUTPUTSET12: SETn1 Mask         */
#define SCT_OUTPUTSET12_SETn2_Pos                             2                                                         /*!< SCT OUTPUTSET12: SETn2 Position     */
#define SCT_OUTPUTSET12_SETn2_Msk                             (0x01UL << SCT_OUTPUTSET12_SETn2_Pos)                     /*!< SCT OUTPUTSET12: SETn2 Mask         */
#define SCT_OUTPUTSET12_SETn3_Pos                             3                                                         /*!< SCT OUTPUTSET12: SETn3 Position     */
#define SCT_OUTPUTSET12_SETn3_Msk                             (0x01UL << SCT_OUTPUTSET12_SETn3_Pos)                     /*!< SCT OUTPUTSET12: SETn3 Mask         */
#define SCT_OUTPUTSET12_SETn4_Pos                             4                                                         /*!< SCT OUTPUTSET12: SETn4 Position     */
#define SCT_OUTPUTSET12_SETn4_Msk                             (0x01UL << SCT_OUTPUTSET12_SETn4_Pos)                     /*!< SCT OUTPUTSET12: SETn4 Mask         */
#define SCT_OUTPUTSET12_SETn5_Pos                             5                                                         /*!< SCT OUTPUTSET12: SETn5 Position     */
#define SCT_OUTPUTSET12_SETn5_Msk                             (0x01UL << SCT_OUTPUTSET12_SETn5_Pos)                     /*!< SCT OUTPUTSET12: SETn5 Mask         */
#define SCT_OUTPUTSET12_SETn6_Pos                             6                                                         /*!< SCT OUTPUTSET12: SETn6 Position     */
#define SCT_OUTPUTSET12_SETn6_Msk                             (0x01UL << SCT_OUTPUTSET12_SETn6_Pos)                     /*!< SCT OUTPUTSET12: SETn6 Mask         */
#define SCT_OUTPUTSET12_SETn7_Pos                             7                                                         /*!< SCT OUTPUTSET12: SETn7 Position     */
#define SCT_OUTPUTSET12_SETn7_Msk                             (0x01UL << SCT_OUTPUTSET12_SETn7_Pos)                     /*!< SCT OUTPUTSET12: SETn7 Mask         */
#define SCT_OUTPUTSET12_SETn8_Pos                             8                                                         /*!< SCT OUTPUTSET12: SETn8 Position     */
#define SCT_OUTPUTSET12_SETn8_Msk                             (0x01UL << SCT_OUTPUTSET12_SETn8_Pos)                     /*!< SCT OUTPUTSET12: SETn8 Mask         */
#define SCT_OUTPUTSET12_SETn9_Pos                             9                                                         /*!< SCT OUTPUTSET12: SETn9 Position     */
#define SCT_OUTPUTSET12_SETn9_Msk                             (0x01UL << SCT_OUTPUTSET12_SETn9_Pos)                     /*!< SCT OUTPUTSET12: SETn9 Mask         */
#define SCT_OUTPUTSET12_SETn10_Pos                            10                                                        /*!< SCT OUTPUTSET12: SETn10 Position    */
#define SCT_OUTPUTSET12_SETn10_Msk                            (0x01UL << SCT_OUTPUTSET12_SETn10_Pos)                    /*!< SCT OUTPUTSET12: SETn10 Mask        */
#define SCT_OUTPUTSET12_SETn11_Pos                            11                                                        /*!< SCT OUTPUTSET12: SETn11 Position    */
#define SCT_OUTPUTSET12_SETn11_Msk                            (0x01UL << SCT_OUTPUTSET12_SETn11_Pos)                    /*!< SCT OUTPUTSET12: SETn11 Mask        */
#define SCT_OUTPUTSET12_SETn12_Pos                            12                                                        /*!< SCT OUTPUTSET12: SETn12 Position    */
#define SCT_OUTPUTSET12_SETn12_Msk                            (0x01UL << SCT_OUTPUTSET12_SETn12_Pos)                    /*!< SCT OUTPUTSET12: SETn12 Mask        */
#define SCT_OUTPUTSET12_SETn13_Pos                            13                                                        /*!< SCT OUTPUTSET12: SETn13 Position    */
#define SCT_OUTPUTSET12_SETn13_Msk                            (0x01UL << SCT_OUTPUTSET12_SETn13_Pos)                    /*!< SCT OUTPUTSET12: SETn13 Mask        */
#define SCT_OUTPUTSET12_SETn14_Pos                            14                                                        /*!< SCT OUTPUTSET12: SETn14 Position    */
#define SCT_OUTPUTSET12_SETn14_Msk                            (0x01UL << SCT_OUTPUTSET12_SETn14_Pos)                    /*!< SCT OUTPUTSET12: SETn14 Mask        */
#define SCT_OUTPUTSET12_SETn15_Pos                            15                                                        /*!< SCT OUTPUTSET12: SETn15 Position    */
#define SCT_OUTPUTSET12_SETn15_Msk                            (0x01UL << SCT_OUTPUTSET12_SETn15_Pos)                    /*!< SCT OUTPUTSET12: SETn15 Mask        */

// -------------------------------------  SCT_OUTPUTCLR12  ----------------------------------------
#define SCT_OUTPUTCLR12_CLRn0_Pos                             0                                                         /*!< SCT OUTPUTCLR12: CLRn0 Position     */
#define SCT_OUTPUTCLR12_CLRn0_Msk                             (0x01UL << SCT_OUTPUTCLR12_CLRn0_Pos)                     /*!< SCT OUTPUTCLR12: CLRn0 Mask         */
#define SCT_OUTPUTCLR12_CLRn1_Pos                             1                                                         /*!< SCT OUTPUTCLR12: CLRn1 Position     */
#define SCT_OUTPUTCLR12_CLRn1_Msk                             (0x01UL << SCT_OUTPUTCLR12_CLRn1_Pos)                     /*!< SCT OUTPUTCLR12: CLRn1 Mask         */
#define SCT_OUTPUTCLR12_CLRn2_Pos                             2                                                         /*!< SCT OUTPUTCLR12: CLRn2 Position     */
#define SCT_OUTPUTCLR12_CLRn2_Msk                             (0x01UL << SCT_OUTPUTCLR12_CLRn2_Pos)                     /*!< SCT OUTPUTCLR12: CLRn2 Mask         */
#define SCT_OUTPUTCLR12_CLRn3_Pos                             3                                                         /*!< SCT OUTPUTCLR12: CLRn3 Position     */
#define SCT_OUTPUTCLR12_CLRn3_Msk                             (0x01UL << SCT_OUTPUTCLR12_CLRn3_Pos)                     /*!< SCT OUTPUTCLR12: CLRn3 Mask         */
#define SCT_OUTPUTCLR12_CLRn4_Pos                             4                                                         /*!< SCT OUTPUTCLR12: CLRn4 Position     */
#define SCT_OUTPUTCLR12_CLRn4_Msk                             (0x01UL << SCT_OUTPUTCLR12_CLRn4_Pos)                     /*!< SCT OUTPUTCLR12: CLRn4 Mask         */
#define SCT_OUTPUTCLR12_CLRn5_Pos                             5                                                         /*!< SCT OUTPUTCLR12: CLRn5 Position     */
#define SCT_OUTPUTCLR12_CLRn5_Msk                             (0x01UL << SCT_OUTPUTCLR12_CLRn5_Pos)                     /*!< SCT OUTPUTCLR12: CLRn5 Mask         */
#define SCT_OUTPUTCLR12_CLRn6_Pos                             6                                                         /*!< SCT OUTPUTCLR12: CLRn6 Position     */
#define SCT_OUTPUTCLR12_CLRn6_Msk                             (0x01UL << SCT_OUTPUTCLR12_CLRn6_Pos)                     /*!< SCT OUTPUTCLR12: CLRn6 Mask         */
#define SCT_OUTPUTCLR12_CLRn7_Pos                             7                                                         /*!< SCT OUTPUTCLR12: CLRn7 Position     */
#define SCT_OUTPUTCLR12_CLRn7_Msk                             (0x01UL << SCT_OUTPUTCLR12_CLRn7_Pos)                     /*!< SCT OUTPUTCLR12: CLRn7 Mask         */
#define SCT_OUTPUTCLR12_CLRn8_Pos                             8                                                         /*!< SCT OUTPUTCLR12: CLRn8 Position     */
#define SCT_OUTPUTCLR12_CLRn8_Msk                             (0x01UL << SCT_OUTPUTCLR12_CLRn8_Pos)                     /*!< SCT OUTPUTCLR12: CLRn8 Mask         */
#define SCT_OUTPUTCLR12_CLRn9_Pos                             9                                                         /*!< SCT OUTPUTCLR12: CLRn9 Position     */
#define SCT_OUTPUTCLR12_CLRn9_Msk                             (0x01UL << SCT_OUTPUTCLR12_CLRn9_Pos)                     /*!< SCT OUTPUTCLR12: CLRn9 Mask         */
#define SCT_OUTPUTCLR12_CLRn10_Pos                            10                                                        /*!< SCT OUTPUTCLR12: CLRn10 Position    */
#define SCT_OUTPUTCLR12_CLRn10_Msk                            (0x01UL << SCT_OUTPUTCLR12_CLRn10_Pos)                    /*!< SCT OUTPUTCLR12: CLRn10 Mask        */
#define SCT_OUTPUTCLR12_CLRn11_Pos                            11                                                        /*!< SCT OUTPUTCLR12: CLRn11 Position    */
#define SCT_OUTPUTCLR12_CLRn11_Msk                            (0x01UL << SCT_OUTPUTCLR12_CLRn11_Pos)                    /*!< SCT OUTPUTCLR12: CLRn11 Mask        */
#define SCT_OUTPUTCLR12_CLRn12_Pos                            12                                                        /*!< SCT OUTPUTCLR12: CLRn12 Position    */
#define SCT_OUTPUTCLR12_CLRn12_Msk                            (0x01UL << SCT_OUTPUTCLR12_CLRn12_Pos)                    /*!< SCT OUTPUTCLR12: CLRn12 Mask        */
#define SCT_OUTPUTCLR12_CLRn13_Pos                            13                                                        /*!< SCT OUTPUTCLR12: CLRn13 Position    */
#define SCT_OUTPUTCLR12_CLRn13_Msk                            (0x01UL << SCT_OUTPUTCLR12_CLRn13_Pos)                    /*!< SCT OUTPUTCLR12: CLRn13 Mask        */
#define SCT_OUTPUTCLR12_CLRn14_Pos                            14                                                        /*!< SCT OUTPUTCLR12: CLRn14 Position    */
#define SCT_OUTPUTCLR12_CLRn14_Msk                            (0x01UL << SCT_OUTPUTCLR12_CLRn14_Pos)                    /*!< SCT OUTPUTCLR12: CLRn14 Mask        */
#define SCT_OUTPUTCLR12_CLRn15_Pos                            15                                                        /*!< SCT OUTPUTCLR12: CLRn15 Position    */
#define SCT_OUTPUTCLR12_CLRn15_Msk                            (0x01UL << SCT_OUTPUTCLR12_CLRn15_Pos)                    /*!< SCT OUTPUTCLR12: CLRn15 Mask        */

// -------------------------------------  SCT_OUTPUTSET13  ----------------------------------------
#define SCT_OUTPUTSET13_SETn0_Pos                             0                                                         /*!< SCT OUTPUTSET13: SETn0 Position     */
#define SCT_OUTPUTSET13_SETn0_Msk                             (0x01UL << SCT_OUTPUTSET13_SETn0_Pos)                     /*!< SCT OUTPUTSET13: SETn0 Mask         */
#define SCT_OUTPUTSET13_SETn1_Pos                             1                                                         /*!< SCT OUTPUTSET13: SETn1 Position     */
#define SCT_OUTPUTSET13_SETn1_Msk                             (0x01UL << SCT_OUTPUTSET13_SETn1_Pos)                     /*!< SCT OUTPUTSET13: SETn1 Mask         */
#define SCT_OUTPUTSET13_SETn2_Pos                             2                                                         /*!< SCT OUTPUTSET13: SETn2 Position     */
#define SCT_OUTPUTSET13_SETn2_Msk                             (0x01UL << SCT_OUTPUTSET13_SETn2_Pos)                     /*!< SCT OUTPUTSET13: SETn2 Mask         */
#define SCT_OUTPUTSET13_SETn3_Pos                             3                                                         /*!< SCT OUTPUTSET13: SETn3 Position     */
#define SCT_OUTPUTSET13_SETn3_Msk                             (0x01UL << SCT_OUTPUTSET13_SETn3_Pos)                     /*!< SCT OUTPUTSET13: SETn3 Mask         */
#define SCT_OUTPUTSET13_SETn4_Pos                             4                                                         /*!< SCT OUTPUTSET13: SETn4 Position     */
#define SCT_OUTPUTSET13_SETn4_Msk                             (0x01UL << SCT_OUTPUTSET13_SETn4_Pos)                     /*!< SCT OUTPUTSET13: SETn4 Mask         */
#define SCT_OUTPUTSET13_SETn5_Pos                             5                                                         /*!< SCT OUTPUTSET13: SETn5 Position     */
#define SCT_OUTPUTSET13_SETn5_Msk                             (0x01UL << SCT_OUTPUTSET13_SETn5_Pos)                     /*!< SCT OUTPUTSET13: SETn5 Mask         */
#define SCT_OUTPUTSET13_SETn6_Pos                             6                                                         /*!< SCT OUTPUTSET13: SETn6 Position     */
#define SCT_OUTPUTSET13_SETn6_Msk                             (0x01UL << SCT_OUTPUTSET13_SETn6_Pos)                     /*!< SCT OUTPUTSET13: SETn6 Mask         */
#define SCT_OUTPUTSET13_SETn7_Pos                             7                                                         /*!< SCT OUTPUTSET13: SETn7 Position     */
#define SCT_OUTPUTSET13_SETn7_Msk                             (0x01UL << SCT_OUTPUTSET13_SETn7_Pos)                     /*!< SCT OUTPUTSET13: SETn7 Mask         */
#define SCT_OUTPUTSET13_SETn8_Pos                             8                                                         /*!< SCT OUTPUTSET13: SETn8 Position     */
#define SCT_OUTPUTSET13_SETn8_Msk                             (0x01UL << SCT_OUTPUTSET13_SETn8_Pos)                     /*!< SCT OUTPUTSET13: SETn8 Mask         */
#define SCT_OUTPUTSET13_SETn9_Pos                             9                                                         /*!< SCT OUTPUTSET13: SETn9 Position     */
#define SCT_OUTPUTSET13_SETn9_Msk                             (0x01UL << SCT_OUTPUTSET13_SETn9_Pos)                     /*!< SCT OUTPUTSET13: SETn9 Mask         */
#define SCT_OUTPUTSET13_SETn10_Pos                            10                                                        /*!< SCT OUTPUTSET13: SETn10 Position    */
#define SCT_OUTPUTSET13_SETn10_Msk                            (0x01UL << SCT_OUTPUTSET13_SETn10_Pos)                    /*!< SCT OUTPUTSET13: SETn10 Mask        */
#define SCT_OUTPUTSET13_SETn11_Pos                            11                                                        /*!< SCT OUTPUTSET13: SETn11 Position    */
#define SCT_OUTPUTSET13_SETn11_Msk                            (0x01UL << SCT_OUTPUTSET13_SETn11_Pos)                    /*!< SCT OUTPUTSET13: SETn11 Mask        */
#define SCT_OUTPUTSET13_SETn12_Pos                            12                                                        /*!< SCT OUTPUTSET13: SETn12 Position    */
#define SCT_OUTPUTSET13_SETn12_Msk                            (0x01UL << SCT_OUTPUTSET13_SETn12_Pos)                    /*!< SCT OUTPUTSET13: SETn12 Mask        */
#define SCT_OUTPUTSET13_SETn13_Pos                            13                                                        /*!< SCT OUTPUTSET13: SETn13 Position    */
#define SCT_OUTPUTSET13_SETn13_Msk                            (0x01UL << SCT_OUTPUTSET13_SETn13_Pos)                    /*!< SCT OUTPUTSET13: SETn13 Mask        */
#define SCT_OUTPUTSET13_SETn14_Pos                            14                                                        /*!< SCT OUTPUTSET13: SETn14 Position    */
#define SCT_OUTPUTSET13_SETn14_Msk                            (0x01UL << SCT_OUTPUTSET13_SETn14_Pos)                    /*!< SCT OUTPUTSET13: SETn14 Mask        */
#define SCT_OUTPUTSET13_SETn15_Pos                            15                                                        /*!< SCT OUTPUTSET13: SETn15 Position    */
#define SCT_OUTPUTSET13_SETn15_Msk                            (0x01UL << SCT_OUTPUTSET13_SETn15_Pos)                    /*!< SCT OUTPUTSET13: SETn15 Mask        */

// -------------------------------------  SCT_OUTPUTCLR13  ----------------------------------------
#define SCT_OUTPUTCLR13_CLRn0_Pos                             0                                                         /*!< SCT OUTPUTCLR13: CLRn0 Position     */
#define SCT_OUTPUTCLR13_CLRn0_Msk                             (0x01UL << SCT_OUTPUTCLR13_CLRn0_Pos)                     /*!< SCT OUTPUTCLR13: CLRn0 Mask         */
#define SCT_OUTPUTCLR13_CLRn1_Pos                             1                                                         /*!< SCT OUTPUTCLR13: CLRn1 Position     */
#define SCT_OUTPUTCLR13_CLRn1_Msk                             (0x01UL << SCT_OUTPUTCLR13_CLRn1_Pos)                     /*!< SCT OUTPUTCLR13: CLRn1 Mask         */
#define SCT_OUTPUTCLR13_CLRn2_Pos                             2                                                         /*!< SCT OUTPUTCLR13: CLRn2 Position     */
#define SCT_OUTPUTCLR13_CLRn2_Msk                             (0x01UL << SCT_OUTPUTCLR13_CLRn2_Pos)                     /*!< SCT OUTPUTCLR13: CLRn2 Mask         */
#define SCT_OUTPUTCLR13_CLRn3_Pos                             3                                                         /*!< SCT OUTPUTCLR13: CLRn3 Position     */
#define SCT_OUTPUTCLR13_CLRn3_Msk                             (0x01UL << SCT_OUTPUTCLR13_CLRn3_Pos)                     /*!< SCT OUTPUTCLR13: CLRn3 Mask         */
#define SCT_OUTPUTCLR13_CLRn4_Pos                             4                                                         /*!< SCT OUTPUTCLR13: CLRn4 Position     */
#define SCT_OUTPUTCLR13_CLRn4_Msk                             (0x01UL << SCT_OUTPUTCLR13_CLRn4_Pos)                     /*!< SCT OUTPUTCLR13: CLRn4 Mask         */
#define SCT_OUTPUTCLR13_CLRn5_Pos                             5                                                         /*!< SCT OUTPUTCLR13: CLRn5 Position     */
#define SCT_OUTPUTCLR13_CLRn5_Msk                             (0x01UL << SCT_OUTPUTCLR13_CLRn5_Pos)                     /*!< SCT OUTPUTCLR13: CLRn5 Mask         */
#define SCT_OUTPUTCLR13_CLRn6_Pos                             6                                                         /*!< SCT OUTPUTCLR13: CLRn6 Position     */
#define SCT_OUTPUTCLR13_CLRn6_Msk                             (0x01UL << SCT_OUTPUTCLR13_CLRn6_Pos)                     /*!< SCT OUTPUTCLR13: CLRn6 Mask         */
#define SCT_OUTPUTCLR13_CLRn7_Pos                             7                                                         /*!< SCT OUTPUTCLR13: CLRn7 Position     */
#define SCT_OUTPUTCLR13_CLRn7_Msk                             (0x01UL << SCT_OUTPUTCLR13_CLRn7_Pos)                     /*!< SCT OUTPUTCLR13: CLRn7 Mask         */
#define SCT_OUTPUTCLR13_CLRn8_Pos                             8                                                         /*!< SCT OUTPUTCLR13: CLRn8 Position     */
#define SCT_OUTPUTCLR13_CLRn8_Msk                             (0x01UL << SCT_OUTPUTCLR13_CLRn8_Pos)                     /*!< SCT OUTPUTCLR13: CLRn8 Mask         */
#define SCT_OUTPUTCLR13_CLRn9_Pos                             9                                                         /*!< SCT OUTPUTCLR13: CLRn9 Position     */
#define SCT_OUTPUTCLR13_CLRn9_Msk                             (0x01UL << SCT_OUTPUTCLR13_CLRn9_Pos)                     /*!< SCT OUTPUTCLR13: CLRn9 Mask         */
#define SCT_OUTPUTCLR13_CLRn10_Pos                            10                                                        /*!< SCT OUTPUTCLR13: CLRn10 Position    */
#define SCT_OUTPUTCLR13_CLRn10_Msk                            (0x01UL << SCT_OUTPUTCLR13_CLRn10_Pos)                    /*!< SCT OUTPUTCLR13: CLRn10 Mask        */
#define SCT_OUTPUTCLR13_CLRn11_Pos                            11                                                        /*!< SCT OUTPUTCLR13: CLRn11 Position    */
#define SCT_OUTPUTCLR13_CLRn11_Msk                            (0x01UL << SCT_OUTPUTCLR13_CLRn11_Pos)                    /*!< SCT OUTPUTCLR13: CLRn11 Mask        */
#define SCT_OUTPUTCLR13_CLRn12_Pos                            12                                                        /*!< SCT OUTPUTCLR13: CLRn12 Position    */
#define SCT_OUTPUTCLR13_CLRn12_Msk                            (0x01UL << SCT_OUTPUTCLR13_CLRn12_Pos)                    /*!< SCT OUTPUTCLR13: CLRn12 Mask        */
#define SCT_OUTPUTCLR13_CLRn13_Pos                            13                                                        /*!< SCT OUTPUTCLR13: CLRn13 Position    */
#define SCT_OUTPUTCLR13_CLRn13_Msk                            (0x01UL << SCT_OUTPUTCLR13_CLRn13_Pos)                    /*!< SCT OUTPUTCLR13: CLRn13 Mask        */
#define SCT_OUTPUTCLR13_CLRn14_Pos                            14                                                        /*!< SCT OUTPUTCLR13: CLRn14 Position    */
#define SCT_OUTPUTCLR13_CLRn14_Msk                            (0x01UL << SCT_OUTPUTCLR13_CLRn14_Pos)                    /*!< SCT OUTPUTCLR13: CLRn14 Mask        */
#define SCT_OUTPUTCLR13_CLRn15_Pos                            15                                                        /*!< SCT OUTPUTCLR13: CLRn15 Position    */
#define SCT_OUTPUTCLR13_CLRn15_Msk                            (0x01UL << SCT_OUTPUTCLR13_CLRn15_Pos)                    /*!< SCT OUTPUTCLR13: CLRn15 Mask        */

// -------------------------------------  SCT_OUTPUTSET14  ----------------------------------------
#define SCT_OUTPUTSET14_SETn0_Pos                             0                                                         /*!< SCT OUTPUTSET14: SETn0 Position     */
#define SCT_OUTPUTSET14_SETn0_Msk                             (0x01UL << SCT_OUTPUTSET14_SETn0_Pos)                     /*!< SCT OUTPUTSET14: SETn0 Mask         */
#define SCT_OUTPUTSET14_SETn1_Pos                             1                                                         /*!< SCT OUTPUTSET14: SETn1 Position     */
#define SCT_OUTPUTSET14_SETn1_Msk                             (0x01UL << SCT_OUTPUTSET14_SETn1_Pos)                     /*!< SCT OUTPUTSET14: SETn1 Mask         */
#define SCT_OUTPUTSET14_SETn2_Pos                             2                                                         /*!< SCT OUTPUTSET14: SETn2 Position     */
#define SCT_OUTPUTSET14_SETn2_Msk                             (0x01UL << SCT_OUTPUTSET14_SETn2_Pos)                     /*!< SCT OUTPUTSET14: SETn2 Mask         */
#define SCT_OUTPUTSET14_SETn3_Pos                             3                                                         /*!< SCT OUTPUTSET14: SETn3 Position     */
#define SCT_OUTPUTSET14_SETn3_Msk                             (0x01UL << SCT_OUTPUTSET14_SETn3_Pos)                     /*!< SCT OUTPUTSET14: SETn3 Mask         */
#define SCT_OUTPUTSET14_SETn4_Pos                             4                                                         /*!< SCT OUTPUTSET14: SETn4 Position     */
#define SCT_OUTPUTSET14_SETn4_Msk                             (0x01UL << SCT_OUTPUTSET14_SETn4_Pos)                     /*!< SCT OUTPUTSET14: SETn4 Mask         */
#define SCT_OUTPUTSET14_SETn5_Pos                             5                                                         /*!< SCT OUTPUTSET14: SETn5 Position     */
#define SCT_OUTPUTSET14_SETn5_Msk                             (0x01UL << SCT_OUTPUTSET14_SETn5_Pos)                     /*!< SCT OUTPUTSET14: SETn5 Mask         */
#define SCT_OUTPUTSET14_SETn6_Pos                             6                                                         /*!< SCT OUTPUTSET14: SETn6 Position     */
#define SCT_OUTPUTSET14_SETn6_Msk                             (0x01UL << SCT_OUTPUTSET14_SETn6_Pos)                     /*!< SCT OUTPUTSET14: SETn6 Mask         */
#define SCT_OUTPUTSET14_SETn7_Pos                             7                                                         /*!< SCT OUTPUTSET14: SETn7 Position     */
#define SCT_OUTPUTSET14_SETn7_Msk                             (0x01UL << SCT_OUTPUTSET14_SETn7_Pos)                     /*!< SCT OUTPUTSET14: SETn7 Mask         */
#define SCT_OUTPUTSET14_SETn8_Pos                             8                                                         /*!< SCT OUTPUTSET14: SETn8 Position     */
#define SCT_OUTPUTSET14_SETn8_Msk                             (0x01UL << SCT_OUTPUTSET14_SETn8_Pos)                     /*!< SCT OUTPUTSET14: SETn8 Mask         */
#define SCT_OUTPUTSET14_SETn9_Pos                             9                                                         /*!< SCT OUTPUTSET14: SETn9 Position     */
#define SCT_OUTPUTSET14_SETn9_Msk                             (0x01UL << SCT_OUTPUTSET14_SETn9_Pos)                     /*!< SCT OUTPUTSET14: SETn9 Mask         */
#define SCT_OUTPUTSET14_SETn10_Pos                            10                                                        /*!< SCT OUTPUTSET14: SETn10 Position    */
#define SCT_OUTPUTSET14_SETn10_Msk                            (0x01UL << SCT_OUTPUTSET14_SETn10_Pos)                    /*!< SCT OUTPUTSET14: SETn10 Mask        */
#define SCT_OUTPUTSET14_SETn11_Pos                            11                                                        /*!< SCT OUTPUTSET14: SETn11 Position    */
#define SCT_OUTPUTSET14_SETn11_Msk                            (0x01UL << SCT_OUTPUTSET14_SETn11_Pos)                    /*!< SCT OUTPUTSET14: SETn11 Mask        */
#define SCT_OUTPUTSET14_SETn12_Pos                            12                                                        /*!< SCT OUTPUTSET14: SETn12 Position    */
#define SCT_OUTPUTSET14_SETn12_Msk                            (0x01UL << SCT_OUTPUTSET14_SETn12_Pos)                    /*!< SCT OUTPUTSET14: SETn12 Mask        */
#define SCT_OUTPUTSET14_SETn13_Pos                            13                                                        /*!< SCT OUTPUTSET14: SETn13 Position    */
#define SCT_OUTPUTSET14_SETn13_Msk                            (0x01UL << SCT_OUTPUTSET14_SETn13_Pos)                    /*!< SCT OUTPUTSET14: SETn13 Mask        */
#define SCT_OUTPUTSET14_SETn14_Pos                            14                                                        /*!< SCT OUTPUTSET14: SETn14 Position    */
#define SCT_OUTPUTSET14_SETn14_Msk                            (0x01UL << SCT_OUTPUTSET14_SETn14_Pos)                    /*!< SCT OUTPUTSET14: SETn14 Mask        */
#define SCT_OUTPUTSET14_SETn15_Pos                            15                                                        /*!< SCT OUTPUTSET14: SETn15 Position    */
#define SCT_OUTPUTSET14_SETn15_Msk                            (0x01UL << SCT_OUTPUTSET14_SETn15_Pos)                    /*!< SCT OUTPUTSET14: SETn15 Mask        */

// -------------------------------------  SCT_OUTPUTCLR14  ----------------------------------------
#define SCT_OUTPUTCLR14_CLRn0_Pos                             0                                                         /*!< SCT OUTPUTCLR14: CLRn0 Position     */
#define SCT_OUTPUTCLR14_CLRn0_Msk                             (0x01UL << SCT_OUTPUTCLR14_CLRn0_Pos)                     /*!< SCT OUTPUTCLR14: CLRn0 Mask         */
#define SCT_OUTPUTCLR14_CLRn1_Pos                             1                                                         /*!< SCT OUTPUTCLR14: CLRn1 Position     */
#define SCT_OUTPUTCLR14_CLRn1_Msk                             (0x01UL << SCT_OUTPUTCLR14_CLRn1_Pos)                     /*!< SCT OUTPUTCLR14: CLRn1 Mask         */
#define SCT_OUTPUTCLR14_CLRn2_Pos                             2                                                         /*!< SCT OUTPUTCLR14: CLRn2 Position     */
#define SCT_OUTPUTCLR14_CLRn2_Msk                             (0x01UL << SCT_OUTPUTCLR14_CLRn2_Pos)                     /*!< SCT OUTPUTCLR14: CLRn2 Mask         */
#define SCT_OUTPUTCLR14_CLRn3_Pos                             3                                                         /*!< SCT OUTPUTCLR14: CLRn3 Position     */
#define SCT_OUTPUTCLR14_CLRn3_Msk                             (0x01UL << SCT_OUTPUTCLR14_CLRn3_Pos)                     /*!< SCT OUTPUTCLR14: CLRn3 Mask         */
#define SCT_OUTPUTCLR14_CLRn4_Pos                             4                                                         /*!< SCT OUTPUTCLR14: CLRn4 Position     */
#define SCT_OUTPUTCLR14_CLRn4_Msk                             (0x01UL << SCT_OUTPUTCLR14_CLRn4_Pos)                     /*!< SCT OUTPUTCLR14: CLRn4 Mask         */
#define SCT_OUTPUTCLR14_CLRn5_Pos                             5                                                         /*!< SCT OUTPUTCLR14: CLRn5 Position     */
#define SCT_OUTPUTCLR14_CLRn5_Msk                             (0x01UL << SCT_OUTPUTCLR14_CLRn5_Pos)                     /*!< SCT OUTPUTCLR14: CLRn5 Mask         */
#define SCT_OUTPUTCLR14_CLRn6_Pos                             6                                                         /*!< SCT OUTPUTCLR14: CLRn6 Position     */
#define SCT_OUTPUTCLR14_CLRn6_Msk                             (0x01UL << SCT_OUTPUTCLR14_CLRn6_Pos)                     /*!< SCT OUTPUTCLR14: CLRn6 Mask         */
#define SCT_OUTPUTCLR14_CLRn7_Pos                             7                                                         /*!< SCT OUTPUTCLR14: CLRn7 Position     */
#define SCT_OUTPUTCLR14_CLRn7_Msk                             (0x01UL << SCT_OUTPUTCLR14_CLRn7_Pos)                     /*!< SCT OUTPUTCLR14: CLRn7 Mask         */
#define SCT_OUTPUTCLR14_CLRn8_Pos                             8                                                         /*!< SCT OUTPUTCLR14: CLRn8 Position     */
#define SCT_OUTPUTCLR14_CLRn8_Msk                             (0x01UL << SCT_OUTPUTCLR14_CLRn8_Pos)                     /*!< SCT OUTPUTCLR14: CLRn8 Mask         */
#define SCT_OUTPUTCLR14_CLRn9_Pos                             9                                                         /*!< SCT OUTPUTCLR14: CLRn9 Position     */
#define SCT_OUTPUTCLR14_CLRn9_Msk                             (0x01UL << SCT_OUTPUTCLR14_CLRn9_Pos)                     /*!< SCT OUTPUTCLR14: CLRn9 Mask         */
#define SCT_OUTPUTCLR14_CLRn10_Pos                            10                                                        /*!< SCT OUTPUTCLR14: CLRn10 Position    */
#define SCT_OUTPUTCLR14_CLRn10_Msk                            (0x01UL << SCT_OUTPUTCLR14_CLRn10_Pos)                    /*!< SCT OUTPUTCLR14: CLRn10 Mask        */
#define SCT_OUTPUTCLR14_CLRn11_Pos                            11                                                        /*!< SCT OUTPUTCLR14: CLRn11 Position    */
#define SCT_OUTPUTCLR14_CLRn11_Msk                            (0x01UL << SCT_OUTPUTCLR14_CLRn11_Pos)                    /*!< SCT OUTPUTCLR14: CLRn11 Mask        */
#define SCT_OUTPUTCLR14_CLRn12_Pos                            12                                                        /*!< SCT OUTPUTCLR14: CLRn12 Position    */
#define SCT_OUTPUTCLR14_CLRn12_Msk                            (0x01UL << SCT_OUTPUTCLR14_CLRn12_Pos)                    /*!< SCT OUTPUTCLR14: CLRn12 Mask        */
#define SCT_OUTPUTCLR14_CLRn13_Pos                            13                                                        /*!< SCT OUTPUTCLR14: CLRn13 Position    */
#define SCT_OUTPUTCLR14_CLRn13_Msk                            (0x01UL << SCT_OUTPUTCLR14_CLRn13_Pos)                    /*!< SCT OUTPUTCLR14: CLRn13 Mask        */
#define SCT_OUTPUTCLR14_CLRn14_Pos                            14                                                        /*!< SCT OUTPUTCLR14: CLRn14 Position    */
#define SCT_OUTPUTCLR14_CLRn14_Msk                            (0x01UL << SCT_OUTPUTCLR14_CLRn14_Pos)                    /*!< SCT OUTPUTCLR14: CLRn14 Mask        */
#define SCT_OUTPUTCLR14_CLRn15_Pos                            15                                                        /*!< SCT OUTPUTCLR14: CLRn15 Position    */
#define SCT_OUTPUTCLR14_CLRn15_Msk                            (0x01UL << SCT_OUTPUTCLR14_CLRn15_Pos)                    /*!< SCT OUTPUTCLR14: CLRn15 Mask        */

// -------------------------------------  SCT_OUTPUTSET15  ----------------------------------------
#define SCT_OUTPUTSET15_SETn0_Pos                             0                                                         /*!< SCT OUTPUTSET15: SETn0 Position     */
#define SCT_OUTPUTSET15_SETn0_Msk                             (0x01UL << SCT_OUTPUTSET15_SETn0_Pos)                     /*!< SCT OUTPUTSET15: SETn0 Mask         */
#define SCT_OUTPUTSET15_SETn1_Pos                             1                                                         /*!< SCT OUTPUTSET15: SETn1 Position     */
#define SCT_OUTPUTSET15_SETn1_Msk                             (0x01UL << SCT_OUTPUTSET15_SETn1_Pos)                     /*!< SCT OUTPUTSET15: SETn1 Mask         */
#define SCT_OUTPUTSET15_SETn2_Pos                             2                                                         /*!< SCT OUTPUTSET15: SETn2 Position     */
#define SCT_OUTPUTSET15_SETn2_Msk                             (0x01UL << SCT_OUTPUTSET15_SETn2_Pos)                     /*!< SCT OUTPUTSET15: SETn2 Mask         */
#define SCT_OUTPUTSET15_SETn3_Pos                             3                                                         /*!< SCT OUTPUTSET15: SETn3 Position     */
#define SCT_OUTPUTSET15_SETn3_Msk                             (0x01UL << SCT_OUTPUTSET15_SETn3_Pos)                     /*!< SCT OUTPUTSET15: SETn3 Mask         */
#define SCT_OUTPUTSET15_SETn4_Pos                             4                                                         /*!< SCT OUTPUTSET15: SETn4 Position     */
#define SCT_OUTPUTSET15_SETn4_Msk                             (0x01UL << SCT_OUTPUTSET15_SETn4_Pos)                     /*!< SCT OUTPUTSET15: SETn4 Mask         */
#define SCT_OUTPUTSET15_SETn5_Pos                             5                                                         /*!< SCT OUTPUTSET15: SETn5 Position     */
#define SCT_OUTPUTSET15_SETn5_Msk                             (0x01UL << SCT_OUTPUTSET15_SETn5_Pos)                     /*!< SCT OUTPUTSET15: SETn5 Mask         */
#define SCT_OUTPUTSET15_SETn6_Pos                             6                                                         /*!< SCT OUTPUTSET15: SETn6 Position     */
#define SCT_OUTPUTSET15_SETn6_Msk                             (0x01UL << SCT_OUTPUTSET15_SETn6_Pos)                     /*!< SCT OUTPUTSET15: SETn6 Mask         */
#define SCT_OUTPUTSET15_SETn7_Pos                             7                                                         /*!< SCT OUTPUTSET15: SETn7 Position     */
#define SCT_OUTPUTSET15_SETn7_Msk                             (0x01UL << SCT_OUTPUTSET15_SETn7_Pos)                     /*!< SCT OUTPUTSET15: SETn7 Mask         */
#define SCT_OUTPUTSET15_SETn8_Pos                             8                                                         /*!< SCT OUTPUTSET15: SETn8 Position     */
#define SCT_OUTPUTSET15_SETn8_Msk                             (0x01UL << SCT_OUTPUTSET15_SETn8_Pos)                     /*!< SCT OUTPUTSET15: SETn8 Mask         */
#define SCT_OUTPUTSET15_SETn9_Pos                             9                                                         /*!< SCT OUTPUTSET15: SETn9 Position     */
#define SCT_OUTPUTSET15_SETn9_Msk                             (0x01UL << SCT_OUTPUTSET15_SETn9_Pos)                     /*!< SCT OUTPUTSET15: SETn9 Mask         */
#define SCT_OUTPUTSET15_SETn10_Pos                            10                                                        /*!< SCT OUTPUTSET15: SETn10 Position    */
#define SCT_OUTPUTSET15_SETn10_Msk                            (0x01UL << SCT_OUTPUTSET15_SETn10_Pos)                    /*!< SCT OUTPUTSET15: SETn10 Mask        */
#define SCT_OUTPUTSET15_SETn11_Pos                            11                                                        /*!< SCT OUTPUTSET15: SETn11 Position    */
#define SCT_OUTPUTSET15_SETn11_Msk                            (0x01UL << SCT_OUTPUTSET15_SETn11_Pos)                    /*!< SCT OUTPUTSET15: SETn11 Mask        */
#define SCT_OUTPUTSET15_SETn12_Pos                            12                                                        /*!< SCT OUTPUTSET15: SETn12 Position    */
#define SCT_OUTPUTSET15_SETn12_Msk                            (0x01UL << SCT_OUTPUTSET15_SETn12_Pos)                    /*!< SCT OUTPUTSET15: SETn12 Mask        */
#define SCT_OUTPUTSET15_SETn13_Pos                            13                                                        /*!< SCT OUTPUTSET15: SETn13 Position    */
#define SCT_OUTPUTSET15_SETn13_Msk                            (0x01UL << SCT_OUTPUTSET15_SETn13_Pos)                    /*!< SCT OUTPUTSET15: SETn13 Mask        */
#define SCT_OUTPUTSET15_SETn14_Pos                            14                                                        /*!< SCT OUTPUTSET15: SETn14 Position    */
#define SCT_OUTPUTSET15_SETn14_Msk                            (0x01UL << SCT_OUTPUTSET15_SETn14_Pos)                    /*!< SCT OUTPUTSET15: SETn14 Mask        */
#define SCT_OUTPUTSET15_SETn15_Pos                            15                                                        /*!< SCT OUTPUTSET15: SETn15 Position    */
#define SCT_OUTPUTSET15_SETn15_Msk                            (0x01UL << SCT_OUTPUTSET15_SETn15_Pos)                    /*!< SCT OUTPUTSET15: SETn15 Mask        */

// -------------------------------------  SCT_OUTPUTCLR15  ----------------------------------------
#define SCT_OUTPUTCLR15_CLRn0_Pos                             0                                                         /*!< SCT OUTPUTCLR15: CLRn0 Position     */
#define SCT_OUTPUTCLR15_CLRn0_Msk                             (0x01UL << SCT_OUTPUTCLR15_CLRn0_Pos)                     /*!< SCT OUTPUTCLR15: CLRn0 Mask         */
#define SCT_OUTPUTCLR15_CLRn1_Pos                             1                                                         /*!< SCT OUTPUTCLR15: CLRn1 Position     */
#define SCT_OUTPUTCLR15_CLRn1_Msk                             (0x01UL << SCT_OUTPUTCLR15_CLRn1_Pos)                     /*!< SCT OUTPUTCLR15: CLRn1 Mask         */
#define SCT_OUTPUTCLR15_CLRn2_Pos                             2                                                         /*!< SCT OUTPUTCLR15: CLRn2 Position     */
#define SCT_OUTPUTCLR15_CLRn2_Msk                             (0x01UL << SCT_OUTPUTCLR15_CLRn2_Pos)                     /*!< SCT OUTPUTCLR15: CLRn2 Mask         */
#define SCT_OUTPUTCLR15_CLRn3_Pos                             3                                                         /*!< SCT OUTPUTCLR15: CLRn3 Position     */
#define SCT_OUTPUTCLR15_CLRn3_Msk                             (0x01UL << SCT_OUTPUTCLR15_CLRn3_Pos)                     /*!< SCT OUTPUTCLR15: CLRn3 Mask         */
#define SCT_OUTPUTCLR15_CLRn4_Pos                             4                                                         /*!< SCT OUTPUTCLR15: CLRn4 Position     */
#define SCT_OUTPUTCLR15_CLRn4_Msk                             (0x01UL << SCT_OUTPUTCLR15_CLRn4_Pos)                     /*!< SCT OUTPUTCLR15: CLRn4 Mask         */
#define SCT_OUTPUTCLR15_CLRn5_Pos                             5                                                         /*!< SCT OUTPUTCLR15: CLRn5 Position     */
#define SCT_OUTPUTCLR15_CLRn5_Msk                             (0x01UL << SCT_OUTPUTCLR15_CLRn5_Pos)                     /*!< SCT OUTPUTCLR15: CLRn5 Mask         */
#define SCT_OUTPUTCLR15_CLRn6_Pos                             6                                                         /*!< SCT OUTPUTCLR15: CLRn6 Position     */
#define SCT_OUTPUTCLR15_CLRn6_Msk                             (0x01UL << SCT_OUTPUTCLR15_CLRn6_Pos)                     /*!< SCT OUTPUTCLR15: CLRn6 Mask         */
#define SCT_OUTPUTCLR15_CLRn7_Pos                             7                                                         /*!< SCT OUTPUTCLR15: CLRn7 Position     */
#define SCT_OUTPUTCLR15_CLRn7_Msk                             (0x01UL << SCT_OUTPUTCLR15_CLRn7_Pos)                     /*!< SCT OUTPUTCLR15: CLRn7 Mask         */
#define SCT_OUTPUTCLR15_CLRn8_Pos                             8                                                         /*!< SCT OUTPUTCLR15: CLRn8 Position     */
#define SCT_OUTPUTCLR15_CLRn8_Msk                             (0x01UL << SCT_OUTPUTCLR15_CLRn8_Pos)                     /*!< SCT OUTPUTCLR15: CLRn8 Mask         */
#define SCT_OUTPUTCLR15_CLRn9_Pos                             9                                                         /*!< SCT OUTPUTCLR15: CLRn9 Position     */
#define SCT_OUTPUTCLR15_CLRn9_Msk                             (0x01UL << SCT_OUTPUTCLR15_CLRn9_Pos)                     /*!< SCT OUTPUTCLR15: CLRn9 Mask         */
#define SCT_OUTPUTCLR15_CLRn10_Pos                            10                                                        /*!< SCT OUTPUTCLR15: CLRn10 Position    */
#define SCT_OUTPUTCLR15_CLRn10_Msk                            (0x01UL << SCT_OUTPUTCLR15_CLRn10_Pos)                    /*!< SCT OUTPUTCLR15: CLRn10 Mask        */
#define SCT_OUTPUTCLR15_CLRn11_Pos                            11                                                        /*!< SCT OUTPUTCLR15: CLRn11 Position    */
#define SCT_OUTPUTCLR15_CLRn11_Msk                            (0x01UL << SCT_OUTPUTCLR15_CLRn11_Pos)                    /*!< SCT OUTPUTCLR15: CLRn11 Mask        */
#define SCT_OUTPUTCLR15_CLRn12_Pos                            12                                                        /*!< SCT OUTPUTCLR15: CLRn12 Position    */
#define SCT_OUTPUTCLR15_CLRn12_Msk                            (0x01UL << SCT_OUTPUTCLR15_CLRn12_Pos)                    /*!< SCT OUTPUTCLR15: CLRn12 Mask        */
#define SCT_OUTPUTCLR15_CLRn13_Pos                            13                                                        /*!< SCT OUTPUTCLR15: CLRn13 Position    */
#define SCT_OUTPUTCLR15_CLRn13_Msk                            (0x01UL << SCT_OUTPUTCLR15_CLRn13_Pos)                    /*!< SCT OUTPUTCLR15: CLRn13 Mask        */
#define SCT_OUTPUTCLR15_CLRn14_Pos                            14                                                        /*!< SCT OUTPUTCLR15: CLRn14 Position    */
#define SCT_OUTPUTCLR15_CLRn14_Msk                            (0x01UL << SCT_OUTPUTCLR15_CLRn14_Pos)                    /*!< SCT OUTPUTCLR15: CLRn14 Mask        */
#define SCT_OUTPUTCLR15_CLRn15_Pos                            15                                                        /*!< SCT OUTPUTCLR15: CLRn15 Position    */
#define SCT_OUTPUTCLR15_CLRn15_Msk                            (0x01UL << SCT_OUTPUTCLR15_CLRn15_Pos)                    /*!< SCT OUTPUTCLR15: CLRn15 Mask        */


// ------------------------------------------------------------------------------------------------
// -----                                 GPDMA Position & Mask                                -----
// ------------------------------------------------------------------------------------------------


// --------------------------------------  GPDMA_INTSTAT  -----------------------------------------
#define GPDMA_INTSTAT_INTSTAT0_Pos                            0                                                         /*!< GPDMA INTSTAT: INTSTAT0 Position    */
#define GPDMA_INTSTAT_INTSTAT0_Msk                            (0x01UL << GPDMA_INTSTAT_INTSTAT0_Pos)                    /*!< GPDMA INTSTAT: INTSTAT0 Mask        */
#define GPDMA_INTSTAT_INTSTAT1_Pos                            1                                                         /*!< GPDMA INTSTAT: INTSTAT1 Position    */
#define GPDMA_INTSTAT_INTSTAT1_Msk                            (0x01UL << GPDMA_INTSTAT_INTSTAT1_Pos)                    /*!< GPDMA INTSTAT: INTSTAT1 Mask        */
#define GPDMA_INTSTAT_INTSTAT2_Pos                            2                                                         /*!< GPDMA INTSTAT: INTSTAT2 Position    */
#define GPDMA_INTSTAT_INTSTAT2_Msk                            (0x01UL << GPDMA_INTSTAT_INTSTAT2_Pos)                    /*!< GPDMA INTSTAT: INTSTAT2 Mask        */
#define GPDMA_INTSTAT_INTSTAT3_Pos                            3                                                         /*!< GPDMA INTSTAT: INTSTAT3 Position    */
#define GPDMA_INTSTAT_INTSTAT3_Msk                            (0x01UL << GPDMA_INTSTAT_INTSTAT3_Pos)                    /*!< GPDMA INTSTAT: INTSTAT3 Mask        */
#define GPDMA_INTSTAT_INTSTAT4_Pos                            4                                                         /*!< GPDMA INTSTAT: INTSTAT4 Position    */
#define GPDMA_INTSTAT_INTSTAT4_Msk                            (0x01UL << GPDMA_INTSTAT_INTSTAT4_Pos)                    /*!< GPDMA INTSTAT: INTSTAT4 Mask        */
#define GPDMA_INTSTAT_INTSTAT5_Pos                            5                                                         /*!< GPDMA INTSTAT: INTSTAT5 Position    */
#define GPDMA_INTSTAT_INTSTAT5_Msk                            (0x01UL << GPDMA_INTSTAT_INTSTAT5_Pos)                    /*!< GPDMA INTSTAT: INTSTAT5 Mask        */
#define GPDMA_INTSTAT_INTSTAT6_Pos                            6                                                         /*!< GPDMA INTSTAT: INTSTAT6 Position    */
#define GPDMA_INTSTAT_INTSTAT6_Msk                            (0x01UL << GPDMA_INTSTAT_INTSTAT6_Pos)                    /*!< GPDMA INTSTAT: INTSTAT6 Mask        */
#define GPDMA_INTSTAT_INTSTAT7_Pos                            7                                                         /*!< GPDMA INTSTAT: INTSTAT7 Position    */
#define GPDMA_INTSTAT_INTSTAT7_Msk                            (0x01UL << GPDMA_INTSTAT_INTSTAT7_Pos)                    /*!< GPDMA INTSTAT: INTSTAT7 Mask        */

// -------------------------------------  GPDMA_INTTCSTAT  ----------------------------------------
#define GPDMA_INTTCSTAT_INTTCSTAT0_Pos                        0                                                         /*!< GPDMA INTTCSTAT: INTTCSTAT0 Position */
#define GPDMA_INTTCSTAT_INTTCSTAT0_Msk                        (0x01UL << GPDMA_INTTCSTAT_INTTCSTAT0_Pos)                /*!< GPDMA INTTCSTAT: INTTCSTAT0 Mask    */
#define GPDMA_INTTCSTAT_INTTCSTAT1_Pos                        1                                                         /*!< GPDMA INTTCSTAT: INTTCSTAT1 Position */
#define GPDMA_INTTCSTAT_INTTCSTAT1_Msk                        (0x01UL << GPDMA_INTTCSTAT_INTTCSTAT1_Pos)                /*!< GPDMA INTTCSTAT: INTTCSTAT1 Mask    */
#define GPDMA_INTTCSTAT_INTTCSTAT2_Pos                        2                                                         /*!< GPDMA INTTCSTAT: INTTCSTAT2 Position */
#define GPDMA_INTTCSTAT_INTTCSTAT2_Msk                        (0x01UL << GPDMA_INTTCSTAT_INTTCSTAT2_Pos)                /*!< GPDMA INTTCSTAT: INTTCSTAT2 Mask    */
#define GPDMA_INTTCSTAT_INTTCSTAT3_Pos                        3                                                         /*!< GPDMA INTTCSTAT: INTTCSTAT3 Position */
#define GPDMA_INTTCSTAT_INTTCSTAT3_Msk                        (0x01UL << GPDMA_INTTCSTAT_INTTCSTAT3_Pos)                /*!< GPDMA INTTCSTAT: INTTCSTAT3 Mask    */
#define GPDMA_INTTCSTAT_INTTCSTAT4_Pos                        4                                                         /*!< GPDMA INTTCSTAT: INTTCSTAT4 Position */
#define GPDMA_INTTCSTAT_INTTCSTAT4_Msk                        (0x01UL << GPDMA_INTTCSTAT_INTTCSTAT4_Pos)                /*!< GPDMA INTTCSTAT: INTTCSTAT4 Mask    */
#define GPDMA_INTTCSTAT_INTTCSTAT5_Pos                        5                                                         /*!< GPDMA INTTCSTAT: INTTCSTAT5 Position */
#define GPDMA_INTTCSTAT_INTTCSTAT5_Msk                        (0x01UL << GPDMA_INTTCSTAT_INTTCSTAT5_Pos)                /*!< GPDMA INTTCSTAT: INTTCSTAT5 Mask    */
#define GPDMA_INTTCSTAT_INTTCSTAT6_Pos                        6                                                         /*!< GPDMA INTTCSTAT: INTTCSTAT6 Position */
#define GPDMA_INTTCSTAT_INTTCSTAT6_Msk                        (0x01UL << GPDMA_INTTCSTAT_INTTCSTAT6_Pos)                /*!< GPDMA INTTCSTAT: INTTCSTAT6 Mask    */
#define GPDMA_INTTCSTAT_INTTCSTAT7_Pos                        7                                                         /*!< GPDMA INTTCSTAT: INTTCSTAT7 Position */
#define GPDMA_INTTCSTAT_INTTCSTAT7_Msk                        (0x01UL << GPDMA_INTTCSTAT_INTTCSTAT7_Pos)                /*!< GPDMA INTTCSTAT: INTTCSTAT7 Mask    */

// ------------------------------------  GPDMA_INTTCCLEAR  ----------------------------------------
#define GPDMA_INTTCCLEAR_INTTCCLEAR0_Pos                      0                                                         /*!< GPDMA INTTCCLEAR: INTTCCLEAR0 Position */
#define GPDMA_INTTCCLEAR_INTTCCLEAR0_Msk                      (0x01UL << GPDMA_INTTCCLEAR_INTTCCLEAR0_Pos)              /*!< GPDMA INTTCCLEAR: INTTCCLEAR0 Mask  */
#define GPDMA_INTTCCLEAR_INTTCCLEAR1_Pos                      1                                                         /*!< GPDMA INTTCCLEAR: INTTCCLEAR1 Position */
#define GPDMA_INTTCCLEAR_INTTCCLEAR1_Msk                      (0x01UL << GPDMA_INTTCCLEAR_INTTCCLEAR1_Pos)              /*!< GPDMA INTTCCLEAR: INTTCCLEAR1 Mask  */
#define GPDMA_INTTCCLEAR_INTTCCLEAR2_Pos                      2                                                         /*!< GPDMA INTTCCLEAR: INTTCCLEAR2 Position */
#define GPDMA_INTTCCLEAR_INTTCCLEAR2_Msk                      (0x01UL << GPDMA_INTTCCLEAR_INTTCCLEAR2_Pos)              /*!< GPDMA INTTCCLEAR: INTTCCLEAR2 Mask  */
#define GPDMA_INTTCCLEAR_INTTCCLEAR3_Pos                      3                                                         /*!< GPDMA INTTCCLEAR: INTTCCLEAR3 Position */
#define GPDMA_INTTCCLEAR_INTTCCLEAR3_Msk                      (0x01UL << GPDMA_INTTCCLEAR_INTTCCLEAR3_Pos)              /*!< GPDMA INTTCCLEAR: INTTCCLEAR3 Mask  */
#define GPDMA_INTTCCLEAR_INTTCCLEAR4_Pos                      4                                                         /*!< GPDMA INTTCCLEAR: INTTCCLEAR4 Position */
#define GPDMA_INTTCCLEAR_INTTCCLEAR4_Msk                      (0x01UL << GPDMA_INTTCCLEAR_INTTCCLEAR4_Pos)              /*!< GPDMA INTTCCLEAR: INTTCCLEAR4 Mask  */
#define GPDMA_INTTCCLEAR_INTTCCLEAR5_Pos                      5                                                         /*!< GPDMA INTTCCLEAR: INTTCCLEAR5 Position */
#define GPDMA_INTTCCLEAR_INTTCCLEAR5_Msk                      (0x01UL << GPDMA_INTTCCLEAR_INTTCCLEAR5_Pos)              /*!< GPDMA INTTCCLEAR: INTTCCLEAR5 Mask  */
#define GPDMA_INTTCCLEAR_INTTCCLEAR6_Pos                      6                                                         /*!< GPDMA INTTCCLEAR: INTTCCLEAR6 Position */
#define GPDMA_INTTCCLEAR_INTTCCLEAR6_Msk                      (0x01UL << GPDMA_INTTCCLEAR_INTTCCLEAR6_Pos)              /*!< GPDMA INTTCCLEAR: INTTCCLEAR6 Mask  */
#define GPDMA_INTTCCLEAR_INTTCCLEAR7_Pos                      7                                                         /*!< GPDMA INTTCCLEAR: INTTCCLEAR7 Position */
#define GPDMA_INTTCCLEAR_INTTCCLEAR7_Msk                      (0x01UL << GPDMA_INTTCCLEAR_INTTCCLEAR7_Pos)              /*!< GPDMA INTTCCLEAR: INTTCCLEAR7 Mask  */

// ------------------------------------  GPDMA_INTERRSTAT  ----------------------------------------
#define GPDMA_INTERRSTAT_INTERRSTAT0_Pos                      0                                                         /*!< GPDMA INTERRSTAT: INTERRSTAT0 Position */
#define GPDMA_INTERRSTAT_INTERRSTAT0_Msk                      (0x01UL << GPDMA_INTERRSTAT_INTERRSTAT0_Pos)              /*!< GPDMA INTERRSTAT: INTERRSTAT0 Mask  */
#define GPDMA_INTERRSTAT_INTERRSTAT1_Pos                      1                                                         /*!< GPDMA INTERRSTAT: INTERRSTAT1 Position */
#define GPDMA_INTERRSTAT_INTERRSTAT1_Msk                      (0x01UL << GPDMA_INTERRSTAT_INTERRSTAT1_Pos)              /*!< GPDMA INTERRSTAT: INTERRSTAT1 Mask  */
#define GPDMA_INTERRSTAT_INTERRSTAT2_Pos                      2                                                         /*!< GPDMA INTERRSTAT: INTERRSTAT2 Position */
#define GPDMA_INTERRSTAT_INTERRSTAT2_Msk                      (0x01UL << GPDMA_INTERRSTAT_INTERRSTAT2_Pos)              /*!< GPDMA INTERRSTAT: INTERRSTAT2 Mask  */
#define GPDMA_INTERRSTAT_INTERRSTAT3_Pos                      3                                                         /*!< GPDMA INTERRSTAT: INTERRSTAT3 Position */
#define GPDMA_INTERRSTAT_INTERRSTAT3_Msk                      (0x01UL << GPDMA_INTERRSTAT_INTERRSTAT3_Pos)              /*!< GPDMA INTERRSTAT: INTERRSTAT3 Mask  */
#define GPDMA_INTERRSTAT_INTERRSTAT4_Pos                      4                                                         /*!< GPDMA INTERRSTAT: INTERRSTAT4 Position */
#define GPDMA_INTERRSTAT_INTERRSTAT4_Msk                      (0x01UL << GPDMA_INTERRSTAT_INTERRSTAT4_Pos)              /*!< GPDMA INTERRSTAT: INTERRSTAT4 Mask  */
#define GPDMA_INTERRSTAT_INTERRSTAT5_Pos                      5                                                         /*!< GPDMA INTERRSTAT: INTERRSTAT5 Position */
#define GPDMA_INTERRSTAT_INTERRSTAT5_Msk                      (0x01UL << GPDMA_INTERRSTAT_INTERRSTAT5_Pos)              /*!< GPDMA INTERRSTAT: INTERRSTAT5 Mask  */
#define GPDMA_INTERRSTAT_INTERRSTAT6_Pos                      6                                                         /*!< GPDMA INTERRSTAT: INTERRSTAT6 Position */
#define GPDMA_INTERRSTAT_INTERRSTAT6_Msk                      (0x01UL << GPDMA_INTERRSTAT_INTERRSTAT6_Pos)              /*!< GPDMA INTERRSTAT: INTERRSTAT6 Mask  */
#define GPDMA_INTERRSTAT_INTERRSTAT7_Pos                      7                                                         /*!< GPDMA INTERRSTAT: INTERRSTAT7 Position */
#define GPDMA_INTERRSTAT_INTERRSTAT7_Msk                      (0x01UL << GPDMA_INTERRSTAT_INTERRSTAT7_Pos)              /*!< GPDMA INTERRSTAT: INTERRSTAT7 Mask  */

// -------------------------------------  GPDMA_INTERRCLR  ----------------------------------------
#define GPDMA_INTERRCLR_INTERRCLR0_Pos                        0                                                         /*!< GPDMA INTERRCLR: INTERRCLR0 Position */
#define GPDMA_INTERRCLR_INTERRCLR0_Msk                        (0x01UL << GPDMA_INTERRCLR_INTERRCLR0_Pos)                /*!< GPDMA INTERRCLR: INTERRCLR0 Mask    */
#define GPDMA_INTERRCLR_INTERRCLR1_Pos                        1                                                         /*!< GPDMA INTERRCLR: INTERRCLR1 Position */
#define GPDMA_INTERRCLR_INTERRCLR1_Msk                        (0x01UL << GPDMA_INTERRCLR_INTERRCLR1_Pos)                /*!< GPDMA INTERRCLR: INTERRCLR1 Mask    */
#define GPDMA_INTERRCLR_INTERRCLR2_Pos                        2                                                         /*!< GPDMA INTERRCLR: INTERRCLR2 Position */
#define GPDMA_INTERRCLR_INTERRCLR2_Msk                        (0x01UL << GPDMA_INTERRCLR_INTERRCLR2_Pos)                /*!< GPDMA INTERRCLR: INTERRCLR2 Mask    */
#define GPDMA_INTERRCLR_INTERRCLR3_Pos                        3                                                         /*!< GPDMA INTERRCLR: INTERRCLR3 Position */
#define GPDMA_INTERRCLR_INTERRCLR3_Msk                        (0x01UL << GPDMA_INTERRCLR_INTERRCLR3_Pos)                /*!< GPDMA INTERRCLR: INTERRCLR3 Mask    */
#define GPDMA_INTERRCLR_INTERRCLR4_Pos                        4                                                         /*!< GPDMA INTERRCLR: INTERRCLR4 Position */
#define GPDMA_INTERRCLR_INTERRCLR4_Msk                        (0x01UL << GPDMA_INTERRCLR_INTERRCLR4_Pos)                /*!< GPDMA INTERRCLR: INTERRCLR4 Mask    */
#define GPDMA_INTERRCLR_INTERRCLR5_Pos                        5                                                         /*!< GPDMA INTERRCLR: INTERRCLR5 Position */
#define GPDMA_INTERRCLR_INTERRCLR5_Msk                        (0x01UL << GPDMA_INTERRCLR_INTERRCLR5_Pos)                /*!< GPDMA INTERRCLR: INTERRCLR5 Mask    */
#define GPDMA_INTERRCLR_INTERRCLR6_Pos                        6                                                         /*!< GPDMA INTERRCLR: INTERRCLR6 Position */
#define GPDMA_INTERRCLR_INTERRCLR6_Msk                        (0x01UL << GPDMA_INTERRCLR_INTERRCLR6_Pos)                /*!< GPDMA INTERRCLR: INTERRCLR6 Mask    */
#define GPDMA_INTERRCLR_INTERRCLR7_Pos                        7                                                         /*!< GPDMA INTERRCLR: INTERRCLR7 Position */
#define GPDMA_INTERRCLR_INTERRCLR7_Msk                        (0x01UL << GPDMA_INTERRCLR_INTERRCLR7_Pos)                /*!< GPDMA INTERRCLR: INTERRCLR7 Mask    */

// -----------------------------------  GPDMA_RAWINTTCSTAT  ---------------------------------------
#define GPDMA_RAWINTTCSTAT_RAWINTTCSTAT0_Pos                  0                                                         /*!< GPDMA RAWINTTCSTAT: RAWINTTCSTAT0 Position */
#define GPDMA_RAWINTTCSTAT_RAWINTTCSTAT0_Msk                  (0x01UL << GPDMA_RAWINTTCSTAT_RAWINTTCSTAT0_Pos)          /*!< GPDMA RAWINTTCSTAT: RAWINTTCSTAT0 Mask */
#define GPDMA_RAWINTTCSTAT_RAWINTTCSTAT1_Pos                  1                                                         /*!< GPDMA RAWINTTCSTAT: RAWINTTCSTAT1 Position */
#define GPDMA_RAWINTTCSTAT_RAWINTTCSTAT1_Msk                  (0x01UL << GPDMA_RAWINTTCSTAT_RAWINTTCSTAT1_Pos)          /*!< GPDMA RAWINTTCSTAT: RAWINTTCSTAT1 Mask */
#define GPDMA_RAWINTTCSTAT_RAWINTTCSTAT2_Pos                  2                                                         /*!< GPDMA RAWINTTCSTAT: RAWINTTCSTAT2 Position */
#define GPDMA_RAWINTTCSTAT_RAWINTTCSTAT2_Msk                  (0x01UL << GPDMA_RAWINTTCSTAT_RAWINTTCSTAT2_Pos)          /*!< GPDMA RAWINTTCSTAT: RAWINTTCSTAT2 Mask */
#define GPDMA_RAWINTTCSTAT_RAWINTTCSTAT3_Pos                  3                                                         /*!< GPDMA RAWINTTCSTAT: RAWINTTCSTAT3 Position */
#define GPDMA_RAWINTTCSTAT_RAWINTTCSTAT3_Msk                  (0x01UL << GPDMA_RAWINTTCSTAT_RAWINTTCSTAT3_Pos)          /*!< GPDMA RAWINTTCSTAT: RAWINTTCSTAT3 Mask */
#define GPDMA_RAWINTTCSTAT_RAWINTTCSTAT4_Pos                  4                                                         /*!< GPDMA RAWINTTCSTAT: RAWINTTCSTAT4 Position */
#define GPDMA_RAWINTTCSTAT_RAWINTTCSTAT4_Msk                  (0x01UL << GPDMA_RAWINTTCSTAT_RAWINTTCSTAT4_Pos)          /*!< GPDMA RAWINTTCSTAT: RAWINTTCSTAT4 Mask */
#define GPDMA_RAWINTTCSTAT_RAWINTTCSTAT5_Pos                  5                                                         /*!< GPDMA RAWINTTCSTAT: RAWINTTCSTAT5 Position */
#define GPDMA_RAWINTTCSTAT_RAWINTTCSTAT5_Msk                  (0x01UL << GPDMA_RAWINTTCSTAT_RAWINTTCSTAT5_Pos)          /*!< GPDMA RAWINTTCSTAT: RAWINTTCSTAT5 Mask */
#define GPDMA_RAWINTTCSTAT_RAWINTTCSTAT6_Pos                  6                                                         /*!< GPDMA RAWINTTCSTAT: RAWINTTCSTAT6 Position */
#define GPDMA_RAWINTTCSTAT_RAWINTTCSTAT6_Msk                  (0x01UL << GPDMA_RAWINTTCSTAT_RAWINTTCSTAT6_Pos)          /*!< GPDMA RAWINTTCSTAT: RAWINTTCSTAT6 Mask */
#define GPDMA_RAWINTTCSTAT_RAWINTTCSTAT7_Pos                  7                                                         /*!< GPDMA RAWINTTCSTAT: RAWINTTCSTAT7 Position */
#define GPDMA_RAWINTTCSTAT_RAWINTTCSTAT7_Msk                  (0x01UL << GPDMA_RAWINTTCSTAT_RAWINTTCSTAT7_Pos)          /*!< GPDMA RAWINTTCSTAT: RAWINTTCSTAT7 Mask */

// -----------------------------------  GPDMA_RAWINTERRSTAT  --------------------------------------
#define GPDMA_RAWINTERRSTAT_RAWINTERRSTAT0_Pos                0                                                         /*!< GPDMA RAWINTERRSTAT: RAWINTERRSTAT0 Position */
#define GPDMA_RAWINTERRSTAT_RAWINTERRSTAT0_Msk                (0x01UL << GPDMA_RAWINTERRSTAT_RAWINTERRSTAT0_Pos)        /*!< GPDMA RAWINTERRSTAT: RAWINTERRSTAT0 Mask */
#define GPDMA_RAWINTERRSTAT_RAWINTERRSTAT1_Pos                1                                                         /*!< GPDMA RAWINTERRSTAT: RAWINTERRSTAT1 Position */
#define GPDMA_RAWINTERRSTAT_RAWINTERRSTAT1_Msk                (0x01UL << GPDMA_RAWINTERRSTAT_RAWINTERRSTAT1_Pos)        /*!< GPDMA RAWINTERRSTAT: RAWINTERRSTAT1 Mask */
#define GPDMA_RAWINTERRSTAT_RAWINTERRSTAT2_Pos                2                                                         /*!< GPDMA RAWINTERRSTAT: RAWINTERRSTAT2 Position */
#define GPDMA_RAWINTERRSTAT_RAWINTERRSTAT2_Msk                (0x01UL << GPDMA_RAWINTERRSTAT_RAWINTERRSTAT2_Pos)        /*!< GPDMA RAWINTERRSTAT: RAWINTERRSTAT2 Mask */
#define GPDMA_RAWINTERRSTAT_RAWINTERRSTAT3_Pos                3                                                         /*!< GPDMA RAWINTERRSTAT: RAWINTERRSTAT3 Position */
#define GPDMA_RAWINTERRSTAT_RAWINTERRSTAT3_Msk                (0x01UL << GPDMA_RAWINTERRSTAT_RAWINTERRSTAT3_Pos)        /*!< GPDMA RAWINTERRSTAT: RAWINTERRSTAT3 Mask */
#define GPDMA_RAWINTERRSTAT_RAWINTERRSTAT4_Pos                4                                                         /*!< GPDMA RAWINTERRSTAT: RAWINTERRSTAT4 Position */
#define GPDMA_RAWINTERRSTAT_RAWINTERRSTAT4_Msk                (0x01UL << GPDMA_RAWINTERRSTAT_RAWINTERRSTAT4_Pos)        /*!< GPDMA RAWINTERRSTAT: RAWINTERRSTAT4 Mask */
#define GPDMA_RAWINTERRSTAT_RAWINTERRSTAT5_Pos                5                                                         /*!< GPDMA RAWINTERRSTAT: RAWINTERRSTAT5 Position */
#define GPDMA_RAWINTERRSTAT_RAWINTERRSTAT5_Msk                (0x01UL << GPDMA_RAWINTERRSTAT_RAWINTERRSTAT5_Pos)        /*!< GPDMA RAWINTERRSTAT: RAWINTERRSTAT5 Mask */
#define GPDMA_RAWINTERRSTAT_RAWINTERRSTAT6_Pos                6                                                         /*!< GPDMA RAWINTERRSTAT: RAWINTERRSTAT6 Position */
#define GPDMA_RAWINTERRSTAT_RAWINTERRSTAT6_Msk                (0x01UL << GPDMA_RAWINTERRSTAT_RAWINTERRSTAT6_Pos)        /*!< GPDMA RAWINTERRSTAT: RAWINTERRSTAT6 Mask */
#define GPDMA_RAWINTERRSTAT_RAWINTERRSTAT7_Pos                7                                                         /*!< GPDMA RAWINTERRSTAT: RAWINTERRSTAT7 Position */
#define GPDMA_RAWINTERRSTAT_RAWINTERRSTAT7_Msk                (0x01UL << GPDMA_RAWINTERRSTAT_RAWINTERRSTAT7_Pos)        /*!< GPDMA RAWINTERRSTAT: RAWINTERRSTAT7 Mask */

// -------------------------------------  GPDMA_ENBLDCHNS  ----------------------------------------
#define GPDMA_ENBLDCHNS_ENABLEDCHANNELS0_Pos                  0                                                         /*!< GPDMA ENBLDCHNS: ENABLEDCHANNELS0 Position */
#define GPDMA_ENBLDCHNS_ENABLEDCHANNELS0_Msk                  (0x01UL << GPDMA_ENBLDCHNS_ENABLEDCHANNELS0_Pos)          /*!< GPDMA ENBLDCHNS: ENABLEDCHANNELS0 Mask */
#define GPDMA_ENBLDCHNS_ENABLEDCHANNELS1_Pos                  1                                                         /*!< GPDMA ENBLDCHNS: ENABLEDCHANNELS1 Position */
#define GPDMA_ENBLDCHNS_ENABLEDCHANNELS1_Msk                  (0x01UL << GPDMA_ENBLDCHNS_ENABLEDCHANNELS1_Pos)          /*!< GPDMA ENBLDCHNS: ENABLEDCHANNELS1 Mask */
#define GPDMA_ENBLDCHNS_ENABLEDCHANNELS2_Pos                  2                                                         /*!< GPDMA ENBLDCHNS: ENABLEDCHANNELS2 Position */
#define GPDMA_ENBLDCHNS_ENABLEDCHANNELS2_Msk                  (0x01UL << GPDMA_ENBLDCHNS_ENABLEDCHANNELS2_Pos)          /*!< GPDMA ENBLDCHNS: ENABLEDCHANNELS2 Mask */
#define GPDMA_ENBLDCHNS_ENABLEDCHANNELS3_Pos                  3                                                         /*!< GPDMA ENBLDCHNS: ENABLEDCHANNELS3 Position */
#define GPDMA_ENBLDCHNS_ENABLEDCHANNELS3_Msk                  (0x01UL << GPDMA_ENBLDCHNS_ENABLEDCHANNELS3_Pos)          /*!< GPDMA ENBLDCHNS: ENABLEDCHANNELS3 Mask */
#define GPDMA_ENBLDCHNS_ENABLEDCHANNELS4_Pos                  4                                                         /*!< GPDMA ENBLDCHNS: ENABLEDCHANNELS4 Position */
#define GPDMA_ENBLDCHNS_ENABLEDCHANNELS4_Msk                  (0x01UL << GPDMA_ENBLDCHNS_ENABLEDCHANNELS4_Pos)          /*!< GPDMA ENBLDCHNS: ENABLEDCHANNELS4 Mask */
#define GPDMA_ENBLDCHNS_ENABLEDCHANNELS5_Pos                  5                                                         /*!< GPDMA ENBLDCHNS: ENABLEDCHANNELS5 Position */
#define GPDMA_ENBLDCHNS_ENABLEDCHANNELS5_Msk                  (0x01UL << GPDMA_ENBLDCHNS_ENABLEDCHANNELS5_Pos)          /*!< GPDMA ENBLDCHNS: ENABLEDCHANNELS5 Mask */
#define GPDMA_ENBLDCHNS_ENABLEDCHANNELS6_Pos                  6                                                         /*!< GPDMA ENBLDCHNS: ENABLEDCHANNELS6 Position */
#define GPDMA_ENBLDCHNS_ENABLEDCHANNELS6_Msk                  (0x01UL << GPDMA_ENBLDCHNS_ENABLEDCHANNELS6_Pos)          /*!< GPDMA ENBLDCHNS: ENABLEDCHANNELS6 Mask */
#define GPDMA_ENBLDCHNS_ENABLEDCHANNELS7_Pos                  7                                                         /*!< GPDMA ENBLDCHNS: ENABLEDCHANNELS7 Position */
#define GPDMA_ENBLDCHNS_ENABLEDCHANNELS7_Msk                  (0x01UL << GPDMA_ENBLDCHNS_ENABLEDCHANNELS7_Pos)          /*!< GPDMA ENBLDCHNS: ENABLEDCHANNELS7 Mask */

// -------------------------------------  GPDMA_SOFTBREQ  -----------------------------------------
#define GPDMA_SOFTBREQ_SOFTBREQ0_Pos                          0                                                         /*!< GPDMA SOFTBREQ: SOFTBREQ0 Position  */
#define GPDMA_SOFTBREQ_SOFTBREQ0_Msk                          (0x01UL << GPDMA_SOFTBREQ_SOFTBREQ0_Pos)                  /*!< GPDMA SOFTBREQ: SOFTBREQ0 Mask      */
#define GPDMA_SOFTBREQ_SOFTBREQ1_Pos                          1                                                         /*!< GPDMA SOFTBREQ: SOFTBREQ1 Position  */
#define GPDMA_SOFTBREQ_SOFTBREQ1_Msk                          (0x01UL << GPDMA_SOFTBREQ_SOFTBREQ1_Pos)                  /*!< GPDMA SOFTBREQ: SOFTBREQ1 Mask      */
#define GPDMA_SOFTBREQ_SOFTBREQ2_Pos                          2                                                         /*!< GPDMA SOFTBREQ: SOFTBREQ2 Position  */
#define GPDMA_SOFTBREQ_SOFTBREQ2_Msk                          (0x01UL << GPDMA_SOFTBREQ_SOFTBREQ2_Pos)                  /*!< GPDMA SOFTBREQ: SOFTBREQ2 Mask      */
#define GPDMA_SOFTBREQ_SOFTBREQ3_Pos                          3                                                         /*!< GPDMA SOFTBREQ: SOFTBREQ3 Position  */
#define GPDMA_SOFTBREQ_SOFTBREQ3_Msk                          (0x01UL << GPDMA_SOFTBREQ_SOFTBREQ3_Pos)                  /*!< GPDMA SOFTBREQ: SOFTBREQ3 Mask      */
#define GPDMA_SOFTBREQ_SOFTBREQ4_Pos                          4                                                         /*!< GPDMA SOFTBREQ: SOFTBREQ4 Position  */
#define GPDMA_SOFTBREQ_SOFTBREQ4_Msk                          (0x01UL << GPDMA_SOFTBREQ_SOFTBREQ4_Pos)                  /*!< GPDMA SOFTBREQ: SOFTBREQ4 Mask      */
#define GPDMA_SOFTBREQ_SOFTBREQ5_Pos                          5                                                         /*!< GPDMA SOFTBREQ: SOFTBREQ5 Position  */
#define GPDMA_SOFTBREQ_SOFTBREQ5_Msk                          (0x01UL << GPDMA_SOFTBREQ_SOFTBREQ5_Pos)                  /*!< GPDMA SOFTBREQ: SOFTBREQ5 Mask      */
#define GPDMA_SOFTBREQ_SOFTBREQ6_Pos                          6                                                         /*!< GPDMA SOFTBREQ: SOFTBREQ6 Position  */
#define GPDMA_SOFTBREQ_SOFTBREQ6_Msk                          (0x01UL << GPDMA_SOFTBREQ_SOFTBREQ6_Pos)                  /*!< GPDMA SOFTBREQ: SOFTBREQ6 Mask      */
#define GPDMA_SOFTBREQ_SOFTBREQ7_Pos                          7                                                         /*!< GPDMA SOFTBREQ: SOFTBREQ7 Position  */
#define GPDMA_SOFTBREQ_SOFTBREQ7_Msk                          (0x01UL << GPDMA_SOFTBREQ_SOFTBREQ7_Pos)                  /*!< GPDMA SOFTBREQ: SOFTBREQ7 Mask      */
#define GPDMA_SOFTBREQ_SOFTBREQ8_Pos                          8                                                         /*!< GPDMA SOFTBREQ: SOFTBREQ8 Position  */
#define GPDMA_SOFTBREQ_SOFTBREQ8_Msk                          (0x01UL << GPDMA_SOFTBREQ_SOFTBREQ8_Pos)                  /*!< GPDMA SOFTBREQ: SOFTBREQ8 Mask      */
#define GPDMA_SOFTBREQ_SOFTBREQ9_Pos                          9                                                         /*!< GPDMA SOFTBREQ: SOFTBREQ9 Position  */
#define GPDMA_SOFTBREQ_SOFTBREQ9_Msk                          (0x01UL << GPDMA_SOFTBREQ_SOFTBREQ9_Pos)                  /*!< GPDMA SOFTBREQ: SOFTBREQ9 Mask      */
#define GPDMA_SOFTBREQ_SOFTBREQ10_Pos                         10                                                        /*!< GPDMA SOFTBREQ: SOFTBREQ10 Position */
#define GPDMA_SOFTBREQ_SOFTBREQ10_Msk                         (0x01UL << GPDMA_SOFTBREQ_SOFTBREQ10_Pos)                 /*!< GPDMA SOFTBREQ: SOFTBREQ10 Mask     */
#define GPDMA_SOFTBREQ_SOFTBREQ11_Pos                         11                                                        /*!< GPDMA SOFTBREQ: SOFTBREQ11 Position */
#define GPDMA_SOFTBREQ_SOFTBREQ11_Msk                         (0x01UL << GPDMA_SOFTBREQ_SOFTBREQ11_Pos)                 /*!< GPDMA SOFTBREQ: SOFTBREQ11 Mask     */
#define GPDMA_SOFTBREQ_SOFTBREQ12_Pos                         12                                                        /*!< GPDMA SOFTBREQ: SOFTBREQ12 Position */
#define GPDMA_SOFTBREQ_SOFTBREQ12_Msk                         (0x01UL << GPDMA_SOFTBREQ_SOFTBREQ12_Pos)                 /*!< GPDMA SOFTBREQ: SOFTBREQ12 Mask     */
#define GPDMA_SOFTBREQ_SOFTBREQ13_Pos                         13                                                        /*!< GPDMA SOFTBREQ: SOFTBREQ13 Position */
#define GPDMA_SOFTBREQ_SOFTBREQ13_Msk                         (0x01UL << GPDMA_SOFTBREQ_SOFTBREQ13_Pos)                 /*!< GPDMA SOFTBREQ: SOFTBREQ13 Mask     */
#define GPDMA_SOFTBREQ_SOFTBREQ14_Pos                         14                                                        /*!< GPDMA SOFTBREQ: SOFTBREQ14 Position */
#define GPDMA_SOFTBREQ_SOFTBREQ14_Msk                         (0x01UL << GPDMA_SOFTBREQ_SOFTBREQ14_Pos)                 /*!< GPDMA SOFTBREQ: SOFTBREQ14 Mask     */
#define GPDMA_SOFTBREQ_SOFTBREQ15_Pos                         15                                                        /*!< GPDMA SOFTBREQ: SOFTBREQ15 Position */
#define GPDMA_SOFTBREQ_SOFTBREQ15_Msk                         (0x01UL << GPDMA_SOFTBREQ_SOFTBREQ15_Pos)                 /*!< GPDMA SOFTBREQ: SOFTBREQ15 Mask     */

// -------------------------------------  GPDMA_SOFTSREQ  -----------------------------------------
#define GPDMA_SOFTSREQ_SOFTSREQ0_Pos                          0                                                         /*!< GPDMA SOFTSREQ: SOFTSREQ0 Position  */
#define GPDMA_SOFTSREQ_SOFTSREQ0_Msk                          (0x01UL << GPDMA_SOFTSREQ_SOFTSREQ0_Pos)                  /*!< GPDMA SOFTSREQ: SOFTSREQ0 Mask      */
#define GPDMA_SOFTSREQ_SOFTSREQ1_Pos                          1                                                         /*!< GPDMA SOFTSREQ: SOFTSREQ1 Position  */
#define GPDMA_SOFTSREQ_SOFTSREQ1_Msk                          (0x01UL << GPDMA_SOFTSREQ_SOFTSREQ1_Pos)                  /*!< GPDMA SOFTSREQ: SOFTSREQ1 Mask      */
#define GPDMA_SOFTSREQ_SOFTSREQ2_Pos                          2                                                         /*!< GPDMA SOFTSREQ: SOFTSREQ2 Position  */
#define GPDMA_SOFTSREQ_SOFTSREQ2_Msk                          (0x01UL << GPDMA_SOFTSREQ_SOFTSREQ2_Pos)                  /*!< GPDMA SOFTSREQ: SOFTSREQ2 Mask      */
#define GPDMA_SOFTSREQ_SOFTSREQ3_Pos                          3                                                         /*!< GPDMA SOFTSREQ: SOFTSREQ3 Position  */
#define GPDMA_SOFTSREQ_SOFTSREQ3_Msk                          (0x01UL << GPDMA_SOFTSREQ_SOFTSREQ3_Pos)                  /*!< GPDMA SOFTSREQ: SOFTSREQ3 Mask      */
#define GPDMA_SOFTSREQ_SOFTSREQ4_Pos                          4                                                         /*!< GPDMA SOFTSREQ: SOFTSREQ4 Position  */
#define GPDMA_SOFTSREQ_SOFTSREQ4_Msk                          (0x01UL << GPDMA_SOFTSREQ_SOFTSREQ4_Pos)                  /*!< GPDMA SOFTSREQ: SOFTSREQ4 Mask      */
#define GPDMA_SOFTSREQ_SOFTSREQ5_Pos                          5                                                         /*!< GPDMA SOFTSREQ: SOFTSREQ5 Position  */
#define GPDMA_SOFTSREQ_SOFTSREQ5_Msk                          (0x01UL << GPDMA_SOFTSREQ_SOFTSREQ5_Pos)                  /*!< GPDMA SOFTSREQ: SOFTSREQ5 Mask      */
#define GPDMA_SOFTSREQ_SOFTSREQ6_Pos                          6                                                         /*!< GPDMA SOFTSREQ: SOFTSREQ6 Position  */
#define GPDMA_SOFTSREQ_SOFTSREQ6_Msk                          (0x01UL << GPDMA_SOFTSREQ_SOFTSREQ6_Pos)                  /*!< GPDMA SOFTSREQ: SOFTSREQ6 Mask      */
#define GPDMA_SOFTSREQ_SOFTSREQ7_Pos                          7                                                         /*!< GPDMA SOFTSREQ: SOFTSREQ7 Position  */
#define GPDMA_SOFTSREQ_SOFTSREQ7_Msk                          (0x01UL << GPDMA_SOFTSREQ_SOFTSREQ7_Pos)                  /*!< GPDMA SOFTSREQ: SOFTSREQ7 Mask      */
#define GPDMA_SOFTSREQ_SOFTSREQ8_Pos                          8                                                         /*!< GPDMA SOFTSREQ: SOFTSREQ8 Position  */
#define GPDMA_SOFTSREQ_SOFTSREQ8_Msk                          (0x01UL << GPDMA_SOFTSREQ_SOFTSREQ8_Pos)                  /*!< GPDMA SOFTSREQ: SOFTSREQ8 Mask      */
#define GPDMA_SOFTSREQ_SOFTSREQ9_Pos                          9                                                         /*!< GPDMA SOFTSREQ: SOFTSREQ9 Position  */
#define GPDMA_SOFTSREQ_SOFTSREQ9_Msk                          (0x01UL << GPDMA_SOFTSREQ_SOFTSREQ9_Pos)                  /*!< GPDMA SOFTSREQ: SOFTSREQ9 Mask      */
#define GPDMA_SOFTSREQ_SOFTSREQ10_Pos                         10                                                        /*!< GPDMA SOFTSREQ: SOFTSREQ10 Position */
#define GPDMA_SOFTSREQ_SOFTSREQ10_Msk                         (0x01UL << GPDMA_SOFTSREQ_SOFTSREQ10_Pos)                 /*!< GPDMA SOFTSREQ: SOFTSREQ10 Mask     */
#define GPDMA_SOFTSREQ_SOFTSREQ11_Pos                         11                                                        /*!< GPDMA SOFTSREQ: SOFTSREQ11 Position */
#define GPDMA_SOFTSREQ_SOFTSREQ11_Msk                         (0x01UL << GPDMA_SOFTSREQ_SOFTSREQ11_Pos)                 /*!< GPDMA SOFTSREQ: SOFTSREQ11 Mask     */
#define GPDMA_SOFTSREQ_SOFTSREQ12_Pos                         12                                                        /*!< GPDMA SOFTSREQ: SOFTSREQ12 Position */
#define GPDMA_SOFTSREQ_SOFTSREQ12_Msk                         (0x01UL << GPDMA_SOFTSREQ_SOFTSREQ12_Pos)                 /*!< GPDMA SOFTSREQ: SOFTSREQ12 Mask     */
#define GPDMA_SOFTSREQ_SOFTSREQ13_Pos                         13                                                        /*!< GPDMA SOFTSREQ: SOFTSREQ13 Position */
#define GPDMA_SOFTSREQ_SOFTSREQ13_Msk                         (0x01UL << GPDMA_SOFTSREQ_SOFTSREQ13_Pos)                 /*!< GPDMA SOFTSREQ: SOFTSREQ13 Mask     */
#define GPDMA_SOFTSREQ_SOFTSREQ14_Pos                         14                                                        /*!< GPDMA SOFTSREQ: SOFTSREQ14 Position */
#define GPDMA_SOFTSREQ_SOFTSREQ14_Msk                         (0x01UL << GPDMA_SOFTSREQ_SOFTSREQ14_Pos)                 /*!< GPDMA SOFTSREQ: SOFTSREQ14 Mask     */
#define GPDMA_SOFTSREQ_SOFTSREQ15_Pos                         15                                                        /*!< GPDMA SOFTSREQ: SOFTSREQ15 Position */
#define GPDMA_SOFTSREQ_SOFTSREQ15_Msk                         (0x01UL << GPDMA_SOFTSREQ_SOFTSREQ15_Pos)                 /*!< GPDMA SOFTSREQ: SOFTSREQ15 Mask     */

// -------------------------------------  GPDMA_SOFTLBREQ  ----------------------------------------
#define GPDMA_SOFTLBREQ_SOFTLBREQ0_Pos                        0                                                         /*!< GPDMA SOFTLBREQ: SOFTLBREQ0 Position */
#define GPDMA_SOFTLBREQ_SOFTLBREQ0_Msk                        (0x01UL << GPDMA_SOFTLBREQ_SOFTLBREQ0_Pos)                /*!< GPDMA SOFTLBREQ: SOFTLBREQ0 Mask    */
#define GPDMA_SOFTLBREQ_SOFTLBREQ1_Pos                        1                                                         /*!< GPDMA SOFTLBREQ: SOFTLBREQ1 Position */
#define GPDMA_SOFTLBREQ_SOFTLBREQ1_Msk                        (0x01UL << GPDMA_SOFTLBREQ_SOFTLBREQ1_Pos)                /*!< GPDMA SOFTLBREQ: SOFTLBREQ1 Mask    */
#define GPDMA_SOFTLBREQ_SOFTLBREQ2_Pos                        2                                                         /*!< GPDMA SOFTLBREQ: SOFTLBREQ2 Position */
#define GPDMA_SOFTLBREQ_SOFTLBREQ2_Msk                        (0x01UL << GPDMA_SOFTLBREQ_SOFTLBREQ2_Pos)                /*!< GPDMA SOFTLBREQ: SOFTLBREQ2 Mask    */
#define GPDMA_SOFTLBREQ_SOFTLBREQ3_Pos                        3                                                         /*!< GPDMA SOFTLBREQ: SOFTLBREQ3 Position */
#define GPDMA_SOFTLBREQ_SOFTLBREQ3_Msk                        (0x01UL << GPDMA_SOFTLBREQ_SOFTLBREQ3_Pos)                /*!< GPDMA SOFTLBREQ: SOFTLBREQ3 Mask    */
#define GPDMA_SOFTLBREQ_SOFTLBREQ4_Pos                        4                                                         /*!< GPDMA SOFTLBREQ: SOFTLBREQ4 Position */
#define GPDMA_SOFTLBREQ_SOFTLBREQ4_Msk                        (0x01UL << GPDMA_SOFTLBREQ_SOFTLBREQ4_Pos)                /*!< GPDMA SOFTLBREQ: SOFTLBREQ4 Mask    */
#define GPDMA_SOFTLBREQ_SOFTLBREQ5_Pos                        5                                                         /*!< GPDMA SOFTLBREQ: SOFTLBREQ5 Position */
#define GPDMA_SOFTLBREQ_SOFTLBREQ5_Msk                        (0x01UL << GPDMA_SOFTLBREQ_SOFTLBREQ5_Pos)                /*!< GPDMA SOFTLBREQ: SOFTLBREQ5 Mask    */
#define GPDMA_SOFTLBREQ_SOFTLBREQ6_Pos                        6                                                         /*!< GPDMA SOFTLBREQ: SOFTLBREQ6 Position */
#define GPDMA_SOFTLBREQ_SOFTLBREQ6_Msk                        (0x01UL << GPDMA_SOFTLBREQ_SOFTLBREQ6_Pos)                /*!< GPDMA SOFTLBREQ: SOFTLBREQ6 Mask    */
#define GPDMA_SOFTLBREQ_SOFTLBREQ7_Pos                        7                                                         /*!< GPDMA SOFTLBREQ: SOFTLBREQ7 Position */
#define GPDMA_SOFTLBREQ_SOFTLBREQ7_Msk                        (0x01UL << GPDMA_SOFTLBREQ_SOFTLBREQ7_Pos)                /*!< GPDMA SOFTLBREQ: SOFTLBREQ7 Mask    */
#define GPDMA_SOFTLBREQ_SOFTLBREQ8_Pos                        8                                                         /*!< GPDMA SOFTLBREQ: SOFTLBREQ8 Position */
#define GPDMA_SOFTLBREQ_SOFTLBREQ8_Msk                        (0x01UL << GPDMA_SOFTLBREQ_SOFTLBREQ8_Pos)                /*!< GPDMA SOFTLBREQ: SOFTLBREQ8 Mask    */
#define GPDMA_SOFTLBREQ_SOFTLBREQ9_Pos                        9                                                         /*!< GPDMA SOFTLBREQ: SOFTLBREQ9 Position */
#define GPDMA_SOFTLBREQ_SOFTLBREQ9_Msk                        (0x01UL << GPDMA_SOFTLBREQ_SOFTLBREQ9_Pos)                /*!< GPDMA SOFTLBREQ: SOFTLBREQ9 Mask    */
#define GPDMA_SOFTLBREQ_SOFTLBREQ10_Pos                       10                                                        /*!< GPDMA SOFTLBREQ: SOFTLBREQ10 Position */
#define GPDMA_SOFTLBREQ_SOFTLBREQ10_Msk                       (0x01UL << GPDMA_SOFTLBREQ_SOFTLBREQ10_Pos)               /*!< GPDMA SOFTLBREQ: SOFTLBREQ10 Mask   */
#define GPDMA_SOFTLBREQ_SOFTLBREQ11_Pos                       11                                                        /*!< GPDMA SOFTLBREQ: SOFTLBREQ11 Position */
#define GPDMA_SOFTLBREQ_SOFTLBREQ11_Msk                       (0x01UL << GPDMA_SOFTLBREQ_SOFTLBREQ11_Pos)               /*!< GPDMA SOFTLBREQ: SOFTLBREQ11 Mask   */
#define GPDMA_SOFTLBREQ_SOFTLBREQ12_Pos                       12                                                        /*!< GPDMA SOFTLBREQ: SOFTLBREQ12 Position */
#define GPDMA_SOFTLBREQ_SOFTLBREQ12_Msk                       (0x01UL << GPDMA_SOFTLBREQ_SOFTLBREQ12_Pos)               /*!< GPDMA SOFTLBREQ: SOFTLBREQ12 Mask   */
#define GPDMA_SOFTLBREQ_SOFTLBREQ13_Pos                       13                                                        /*!< GPDMA SOFTLBREQ: SOFTLBREQ13 Position */
#define GPDMA_SOFTLBREQ_SOFTLBREQ13_Msk                       (0x01UL << GPDMA_SOFTLBREQ_SOFTLBREQ13_Pos)               /*!< GPDMA SOFTLBREQ: SOFTLBREQ13 Mask   */
#define GPDMA_SOFTLBREQ_SOFTLBREQ14_Pos                       14                                                        /*!< GPDMA SOFTLBREQ: SOFTLBREQ14 Position */
#define GPDMA_SOFTLBREQ_SOFTLBREQ14_Msk                       (0x01UL << GPDMA_SOFTLBREQ_SOFTLBREQ14_Pos)               /*!< GPDMA SOFTLBREQ: SOFTLBREQ14 Mask   */
#define GPDMA_SOFTLBREQ_SOFTLBREQ15_Pos                       15                                                        /*!< GPDMA SOFTLBREQ: SOFTLBREQ15 Position */
#define GPDMA_SOFTLBREQ_SOFTLBREQ15_Msk                       (0x01UL << GPDMA_SOFTLBREQ_SOFTLBREQ15_Pos)               /*!< GPDMA SOFTLBREQ: SOFTLBREQ15 Mask   */

// -------------------------------------  GPDMA_SOFTLSREQ  ----------------------------------------
#define GPDMA_SOFTLSREQ_SOFTLSREQ0_Pos                        0                                                         /*!< GPDMA SOFTLSREQ: SOFTLSREQ0 Position */
#define GPDMA_SOFTLSREQ_SOFTLSREQ0_Msk                        (0x01UL << GPDMA_SOFTLSREQ_SOFTLSREQ0_Pos)                /*!< GPDMA SOFTLSREQ: SOFTLSREQ0 Mask    */
#define GPDMA_SOFTLSREQ_SOFTLSREQ1_Pos                        1                                                         /*!< GPDMA SOFTLSREQ: SOFTLSREQ1 Position */
#define GPDMA_SOFTLSREQ_SOFTLSREQ1_Msk                        (0x01UL << GPDMA_SOFTLSREQ_SOFTLSREQ1_Pos)                /*!< GPDMA SOFTLSREQ: SOFTLSREQ1 Mask    */
#define GPDMA_SOFTLSREQ_SOFTLSREQ2_Pos                        2                                                         /*!< GPDMA SOFTLSREQ: SOFTLSREQ2 Position */
#define GPDMA_SOFTLSREQ_SOFTLSREQ2_Msk                        (0x01UL << GPDMA_SOFTLSREQ_SOFTLSREQ2_Pos)                /*!< GPDMA SOFTLSREQ: SOFTLSREQ2 Mask    */
#define GPDMA_SOFTLSREQ_SOFTLSREQ3_Pos                        3                                                         /*!< GPDMA SOFTLSREQ: SOFTLSREQ3 Position */
#define GPDMA_SOFTLSREQ_SOFTLSREQ3_Msk                        (0x01UL << GPDMA_SOFTLSREQ_SOFTLSREQ3_Pos)                /*!< GPDMA SOFTLSREQ: SOFTLSREQ3 Mask    */
#define GPDMA_SOFTLSREQ_SOFTLSREQ4_Pos                        4                                                         /*!< GPDMA SOFTLSREQ: SOFTLSREQ4 Position */
#define GPDMA_SOFTLSREQ_SOFTLSREQ4_Msk                        (0x01UL << GPDMA_SOFTLSREQ_SOFTLSREQ4_Pos)                /*!< GPDMA SOFTLSREQ: SOFTLSREQ4 Mask    */
#define GPDMA_SOFTLSREQ_SOFTLSREQ5_Pos                        5                                                         /*!< GPDMA SOFTLSREQ: SOFTLSREQ5 Position */
#define GPDMA_SOFTLSREQ_SOFTLSREQ5_Msk                        (0x01UL << GPDMA_SOFTLSREQ_SOFTLSREQ5_Pos)                /*!< GPDMA SOFTLSREQ: SOFTLSREQ5 Mask    */
#define GPDMA_SOFTLSREQ_SOFTLSREQ6_Pos                        6                                                         /*!< GPDMA SOFTLSREQ: SOFTLSREQ6 Position */
#define GPDMA_SOFTLSREQ_SOFTLSREQ6_Msk                        (0x01UL << GPDMA_SOFTLSREQ_SOFTLSREQ6_Pos)                /*!< GPDMA SOFTLSREQ: SOFTLSREQ6 Mask    */
#define GPDMA_SOFTLSREQ_SOFTLSREQ7_Pos                        7                                                         /*!< GPDMA SOFTLSREQ: SOFTLSREQ7 Position */
#define GPDMA_SOFTLSREQ_SOFTLSREQ7_Msk                        (0x01UL << GPDMA_SOFTLSREQ_SOFTLSREQ7_Pos)                /*!< GPDMA SOFTLSREQ: SOFTLSREQ7 Mask    */
#define GPDMA_SOFTLSREQ_SOFTLSREQ8_Pos                        8                                                         /*!< GPDMA SOFTLSREQ: SOFTLSREQ8 Position */
#define GPDMA_SOFTLSREQ_SOFTLSREQ8_Msk                        (0x01UL << GPDMA_SOFTLSREQ_SOFTLSREQ8_Pos)                /*!< GPDMA SOFTLSREQ: SOFTLSREQ8 Mask    */
#define GPDMA_SOFTLSREQ_SOFTLSREQ9_Pos                        9                                                         /*!< GPDMA SOFTLSREQ: SOFTLSREQ9 Position */
#define GPDMA_SOFTLSREQ_SOFTLSREQ9_Msk                        (0x01UL << GPDMA_SOFTLSREQ_SOFTLSREQ9_Pos)                /*!< GPDMA SOFTLSREQ: SOFTLSREQ9 Mask    */
#define GPDMA_SOFTLSREQ_SOFTLSREQ10_Pos                       10                                                        /*!< GPDMA SOFTLSREQ: SOFTLSREQ10 Position */
#define GPDMA_SOFTLSREQ_SOFTLSREQ10_Msk                       (0x01UL << GPDMA_SOFTLSREQ_SOFTLSREQ10_Pos)               /*!< GPDMA SOFTLSREQ: SOFTLSREQ10 Mask   */
#define GPDMA_SOFTLSREQ_SOFTLSREQ11_Pos                       11                                                        /*!< GPDMA SOFTLSREQ: SOFTLSREQ11 Position */
#define GPDMA_SOFTLSREQ_SOFTLSREQ11_Msk                       (0x01UL << GPDMA_SOFTLSREQ_SOFTLSREQ11_Pos)               /*!< GPDMA SOFTLSREQ: SOFTLSREQ11 Mask   */
#define GPDMA_SOFTLSREQ_SOFTLSREQ12_Pos                       12                                                        /*!< GPDMA SOFTLSREQ: SOFTLSREQ12 Position */
#define GPDMA_SOFTLSREQ_SOFTLSREQ12_Msk                       (0x01UL << GPDMA_SOFTLSREQ_SOFTLSREQ12_Pos)               /*!< GPDMA SOFTLSREQ: SOFTLSREQ12 Mask   */
#define GPDMA_SOFTLSREQ_SOFTLSREQ13_Pos                       13                                                        /*!< GPDMA SOFTLSREQ: SOFTLSREQ13 Position */
#define GPDMA_SOFTLSREQ_SOFTLSREQ13_Msk                       (0x01UL << GPDMA_SOFTLSREQ_SOFTLSREQ13_Pos)               /*!< GPDMA SOFTLSREQ: SOFTLSREQ13 Mask   */
#define GPDMA_SOFTLSREQ_SOFTLSREQ14_Pos                       14                                                        /*!< GPDMA SOFTLSREQ: SOFTLSREQ14 Position */
#define GPDMA_SOFTLSREQ_SOFTLSREQ14_Msk                       (0x01UL << GPDMA_SOFTLSREQ_SOFTLSREQ14_Pos)               /*!< GPDMA SOFTLSREQ: SOFTLSREQ14 Mask   */
#define GPDMA_SOFTLSREQ_SOFTLSREQ15_Pos                       15                                                        /*!< GPDMA SOFTLSREQ: SOFTLSREQ15 Position */
#define GPDMA_SOFTLSREQ_SOFTLSREQ15_Msk                       (0x01UL << GPDMA_SOFTLSREQ_SOFTLSREQ15_Pos)               /*!< GPDMA SOFTLSREQ: SOFTLSREQ15 Mask   */

// --------------------------------------  GPDMA_CONFIG  ------------------------------------------
#define GPDMA_CONFIG_E_Pos                                    0                                                         /*!< GPDMA CONFIG: E Position            */
#define GPDMA_CONFIG_E_Msk                                    (0x01UL << GPDMA_CONFIG_E_Pos)                            /*!< GPDMA CONFIG: E Mask                */
#define GPDMA_CONFIG_M0_Pos                                   1                                                         /*!< GPDMA CONFIG: M0 Position           */
#define GPDMA_CONFIG_M0_Msk                                   (0x01UL << GPDMA_CONFIG_M0_Pos)                           /*!< GPDMA CONFIG: M0 Mask               */
#define GPDMA_CONFIG_M1_Pos                                   2                                                         /*!< GPDMA CONFIG: M1 Position           */
#define GPDMA_CONFIG_M1_Msk                                   (0x01UL << GPDMA_CONFIG_M1_Pos)                           /*!< GPDMA CONFIG: M1 Mask               */

// ---------------------------------------  GPDMA_SYNC  -------------------------------------------
#define GPDMA_SYNC_DMACSYNC0_Pos                              0                                                         /*!< GPDMA SYNC: DMACSYNC0 Position      */
#define GPDMA_SYNC_DMACSYNC0_Msk                              (0x01UL << GPDMA_SYNC_DMACSYNC0_Pos)                      /*!< GPDMA SYNC: DMACSYNC0 Mask          */
#define GPDMA_SYNC_DMACSYNC1_Pos                              1                                                         /*!< GPDMA SYNC: DMACSYNC1 Position      */
#define GPDMA_SYNC_DMACSYNC1_Msk                              (0x01UL << GPDMA_SYNC_DMACSYNC1_Pos)                      /*!< GPDMA SYNC: DMACSYNC1 Mask          */
#define GPDMA_SYNC_DMACSYNC2_Pos                              2                                                         /*!< GPDMA SYNC: DMACSYNC2 Position      */
#define GPDMA_SYNC_DMACSYNC2_Msk                              (0x01UL << GPDMA_SYNC_DMACSYNC2_Pos)                      /*!< GPDMA SYNC: DMACSYNC2 Mask          */
#define GPDMA_SYNC_DMACSYNC3_Pos                              3                                                         /*!< GPDMA SYNC: DMACSYNC3 Position      */
#define GPDMA_SYNC_DMACSYNC3_Msk                              (0x01UL << GPDMA_SYNC_DMACSYNC3_Pos)                      /*!< GPDMA SYNC: DMACSYNC3 Mask          */
#define GPDMA_SYNC_DMACSYNC4_Pos                              4                                                         /*!< GPDMA SYNC: DMACSYNC4 Position      */
#define GPDMA_SYNC_DMACSYNC4_Msk                              (0x01UL << GPDMA_SYNC_DMACSYNC4_Pos)                      /*!< GPDMA SYNC: DMACSYNC4 Mask          */
#define GPDMA_SYNC_DMACSYNC5_Pos                              5                                                         /*!< GPDMA SYNC: DMACSYNC5 Position      */
#define GPDMA_SYNC_DMACSYNC5_Msk                              (0x01UL << GPDMA_SYNC_DMACSYNC5_Pos)                      /*!< GPDMA SYNC: DMACSYNC5 Mask          */
#define GPDMA_SYNC_DMACSYNC6_Pos                              6                                                         /*!< GPDMA SYNC: DMACSYNC6 Position      */
#define GPDMA_SYNC_DMACSYNC6_Msk                              (0x01UL << GPDMA_SYNC_DMACSYNC6_Pos)                      /*!< GPDMA SYNC: DMACSYNC6 Mask          */
#define GPDMA_SYNC_DMACSYNC7_Pos                              7                                                         /*!< GPDMA SYNC: DMACSYNC7 Position      */
#define GPDMA_SYNC_DMACSYNC7_Msk                              (0x01UL << GPDMA_SYNC_DMACSYNC7_Pos)                      /*!< GPDMA SYNC: DMACSYNC7 Mask          */
#define GPDMA_SYNC_DMACSYNC8_Pos                              8                                                         /*!< GPDMA SYNC: DMACSYNC8 Position      */
#define GPDMA_SYNC_DMACSYNC8_Msk                              (0x01UL << GPDMA_SYNC_DMACSYNC8_Pos)                      /*!< GPDMA SYNC: DMACSYNC8 Mask          */
#define GPDMA_SYNC_DMACSYNC9_Pos                              9                                                         /*!< GPDMA SYNC: DMACSYNC9 Position      */
#define GPDMA_SYNC_DMACSYNC9_Msk                              (0x01UL << GPDMA_SYNC_DMACSYNC9_Pos)                      /*!< GPDMA SYNC: DMACSYNC9 Mask          */
#define GPDMA_SYNC_DMACSYNC10_Pos                             10                                                        /*!< GPDMA SYNC: DMACSYNC10 Position     */
#define GPDMA_SYNC_DMACSYNC10_Msk                             (0x01UL << GPDMA_SYNC_DMACSYNC10_Pos)                     /*!< GPDMA SYNC: DMACSYNC10 Mask         */
#define GPDMA_SYNC_DMACSYNC11_Pos                             11                                                        /*!< GPDMA SYNC: DMACSYNC11 Position     */
#define GPDMA_SYNC_DMACSYNC11_Msk                             (0x01UL << GPDMA_SYNC_DMACSYNC11_Pos)                     /*!< GPDMA SYNC: DMACSYNC11 Mask         */
#define GPDMA_SYNC_DMACSYNC12_Pos                             12                                                        /*!< GPDMA SYNC: DMACSYNC12 Position     */
#define GPDMA_SYNC_DMACSYNC12_Msk                             (0x01UL << GPDMA_SYNC_DMACSYNC12_Pos)                     /*!< GPDMA SYNC: DMACSYNC12 Mask         */
#define GPDMA_SYNC_DMACSYNC13_Pos                             13                                                        /*!< GPDMA SYNC: DMACSYNC13 Position     */
#define GPDMA_SYNC_DMACSYNC13_Msk                             (0x01UL << GPDMA_SYNC_DMACSYNC13_Pos)                     /*!< GPDMA SYNC: DMACSYNC13 Mask         */
#define GPDMA_SYNC_DMACSYNC14_Pos                             14                                                        /*!< GPDMA SYNC: DMACSYNC14 Position     */
#define GPDMA_SYNC_DMACSYNC14_Msk                             (0x01UL << GPDMA_SYNC_DMACSYNC14_Pos)                     /*!< GPDMA SYNC: DMACSYNC14 Mask         */
#define GPDMA_SYNC_DMACSYNC15_Pos                             15                                                        /*!< GPDMA SYNC: DMACSYNC15 Position     */
#define GPDMA_SYNC_DMACSYNC15_Msk                             (0x01UL << GPDMA_SYNC_DMACSYNC15_Pos)                     /*!< GPDMA SYNC: DMACSYNC15 Mask         */

// -------------------------------------  GPDMA_C0SRCADDR  ----------------------------------------
#define GPDMA_C0SRCADDR_SRCADDR_Pos                           0                                                         /*!< GPDMA C0SRCADDR: SRCADDR Position   */
#define GPDMA_C0SRCADDR_SRCADDR_Msk                           (0xffffffffUL << GPDMA_C0SRCADDR_SRCADDR_Pos)             /*!< GPDMA C0SRCADDR: SRCADDR Mask       */

// ------------------------------------  GPDMA_C0DESTADDR  ----------------------------------------
#define GPDMA_C0DESTADDR_DESTADDR_Pos                         0                                                         /*!< GPDMA C0DESTADDR: DESTADDR Position */
#define GPDMA_C0DESTADDR_DESTADDR_Msk                         (0xffffffffUL << GPDMA_C0DESTADDR_DESTADDR_Pos)           /*!< GPDMA C0DESTADDR: DESTADDR Mask     */

// ---------------------------------------  GPDMA_C0LLI  ------------------------------------------
#define GPDMA_C0LLI_LM_Pos                                    0                                                         /*!< GPDMA C0LLI: LM Position            */
#define GPDMA_C0LLI_LM_Msk                                    (0x01UL << GPDMA_C0LLI_LM_Pos)                            /*!< GPDMA C0LLI: LM Mask                */
#define GPDMA_C0LLI_R_Pos                                     1                                                         /*!< GPDMA C0LLI: R Position             */
#define GPDMA_C0LLI_R_Msk                                     (0x01UL << GPDMA_C0LLI_R_Pos)                             /*!< GPDMA C0LLI: R Mask                 */
#define GPDMA_C0LLI_LLI_Pos                                   2                                                         /*!< GPDMA C0LLI: LLI Position           */
#define GPDMA_C0LLI_LLI_Msk                                   (0x3fffffffUL << GPDMA_C0LLI_LLI_Pos)                     /*!< GPDMA C0LLI: LLI Mask               */

// -------------------------------------  GPDMA_C0CONTROL  ----------------------------------------
#define GPDMA_C0CONTROL_TRANSFERSIZE_Pos                      0                                                         /*!< GPDMA C0CONTROL: TRANSFERSIZE Position */
#define GPDMA_C0CONTROL_TRANSFERSIZE_Msk                      (0x00000fffUL << GPDMA_C0CONTROL_TRANSFERSIZE_Pos)        /*!< GPDMA C0CONTROL: TRANSFERSIZE Mask  */
#define GPDMA_C0CONTROL_SBSIZE_Pos                            12                                                        /*!< GPDMA C0CONTROL: SBSIZE Position    */
#define GPDMA_C0CONTROL_SBSIZE_Msk                            (0x07UL << GPDMA_C0CONTROL_SBSIZE_Pos)                    /*!< GPDMA C0CONTROL: SBSIZE Mask        */
#define GPDMA_C0CONTROL_DBSIZE_Pos                            15                                                        /*!< GPDMA C0CONTROL: DBSIZE Position    */
#define GPDMA_C0CONTROL_DBSIZE_Msk                            (0x07UL << GPDMA_C0CONTROL_DBSIZE_Pos)                    /*!< GPDMA C0CONTROL: DBSIZE Mask        */
#define GPDMA_C0CONTROL_SWIDTH_Pos                            18                                                        /*!< GPDMA C0CONTROL: SWIDTH Position    */
#define GPDMA_C0CONTROL_SWIDTH_Msk                            (0x07UL << GPDMA_C0CONTROL_SWIDTH_Pos)                    /*!< GPDMA C0CONTROL: SWIDTH Mask        */
#define GPDMA_C0CONTROL_DWIDTH_Pos                            21                                                        /*!< GPDMA C0CONTROL: DWIDTH Position    */
#define GPDMA_C0CONTROL_DWIDTH_Msk                            (0x07UL << GPDMA_C0CONTROL_DWIDTH_Pos)                    /*!< GPDMA C0CONTROL: DWIDTH Mask        */
#define GPDMA_C0CONTROL_S_Pos                                 24                                                        /*!< GPDMA C0CONTROL: S Position         */
#define GPDMA_C0CONTROL_S_Msk                                 (0x01UL << GPDMA_C0CONTROL_S_Pos)                         /*!< GPDMA C0CONTROL: S Mask             */
#define GPDMA_C0CONTROL_D_Pos                                 25                                                        /*!< GPDMA C0CONTROL: D Position         */
#define GPDMA_C0CONTROL_D_Msk                                 (0x01UL << GPDMA_C0CONTROL_D_Pos)                         /*!< GPDMA C0CONTROL: D Mask             */
#define GPDMA_C0CONTROL_SI_Pos                                26                                                        /*!< GPDMA C0CONTROL: SI Position        */
#define GPDMA_C0CONTROL_SI_Msk                                (0x01UL << GPDMA_C0CONTROL_SI_Pos)                        /*!< GPDMA C0CONTROL: SI Mask            */
#define GPDMA_C0CONTROL_DI_Pos                                27                                                        /*!< GPDMA C0CONTROL: DI Position        */
#define GPDMA_C0CONTROL_DI_Msk                                (0x01UL << GPDMA_C0CONTROL_DI_Pos)                        /*!< GPDMA C0CONTROL: DI Mask            */
#define GPDMA_C0CONTROL_PROT1_Pos                             28                                                        /*!< GPDMA C0CONTROL: PROT1 Position     */
#define GPDMA_C0CONTROL_PROT1_Msk                             (0x01UL << GPDMA_C0CONTROL_PROT1_Pos)                     /*!< GPDMA C0CONTROL: PROT1 Mask         */
#define GPDMA_C0CONTROL_PROT2_Pos                             29                                                        /*!< GPDMA C0CONTROL: PROT2 Position     */
#define GPDMA_C0CONTROL_PROT2_Msk                             (0x01UL << GPDMA_C0CONTROL_PROT2_Pos)                     /*!< GPDMA C0CONTROL: PROT2 Mask         */
#define GPDMA_C0CONTROL_PROT3_Pos                             30                                                        /*!< GPDMA C0CONTROL: PROT3 Position     */
#define GPDMA_C0CONTROL_PROT3_Msk                             (0x01UL << GPDMA_C0CONTROL_PROT3_Pos)                     /*!< GPDMA C0CONTROL: PROT3 Mask         */
#define GPDMA_C0CONTROL_I_Pos                                 31                                                        /*!< GPDMA C0CONTROL: I Position         */
#define GPDMA_C0CONTROL_I_Msk                                 (0x01UL << GPDMA_C0CONTROL_I_Pos)                         /*!< GPDMA C0CONTROL: I Mask             */

// -------------------------------------  GPDMA_C0CONFIG  -----------------------------------------
#define GPDMA_C0CONFIG_E_Pos                                  0                                                         /*!< GPDMA C0CONFIG: E Position          */
#define GPDMA_C0CONFIG_E_Msk                                  (0x01UL << GPDMA_C0CONFIG_E_Pos)                          /*!< GPDMA C0CONFIG: E Mask              */
#define GPDMA_C0CONFIG_SRCPERIPHERAL_Pos                      1                                                         /*!< GPDMA C0CONFIG: SRCPERIPHERAL Position */
#define GPDMA_C0CONFIG_SRCPERIPHERAL_Msk                      (0x1fUL << GPDMA_C0CONFIG_SRCPERIPHERAL_Pos)              /*!< GPDMA C0CONFIG: SRCPERIPHERAL Mask  */
#define GPDMA_C0CONFIG_DESTPERIPHERAL_Pos                     6                                                         /*!< GPDMA C0CONFIG: DESTPERIPHERAL Position */
#define GPDMA_C0CONFIG_DESTPERIPHERAL_Msk                     (0x1fUL << GPDMA_C0CONFIG_DESTPERIPHERAL_Pos)             /*!< GPDMA C0CONFIG: DESTPERIPHERAL Mask */
#define GPDMA_C0CONFIG_FLOWCNTRL_Pos                          11                                                        /*!< GPDMA C0CONFIG: FLOWCNTRL Position  */
#define GPDMA_C0CONFIG_FLOWCNTRL_Msk                          (0x07UL << GPDMA_C0CONFIG_FLOWCNTRL_Pos)                  /*!< GPDMA C0CONFIG: FLOWCNTRL Mask      */
#define GPDMA_C0CONFIG_IE_Pos                                 14                                                        /*!< GPDMA C0CONFIG: IE Position         */
#define GPDMA_C0CONFIG_IE_Msk                                 (0x01UL << GPDMA_C0CONFIG_IE_Pos)                         /*!< GPDMA C0CONFIG: IE Mask             */
#define GPDMA_C0CONFIG_ITC_Pos                                15                                                        /*!< GPDMA C0CONFIG: ITC Position        */
#define GPDMA_C0CONFIG_ITC_Msk                                (0x01UL << GPDMA_C0CONFIG_ITC_Pos)                        /*!< GPDMA C0CONFIG: ITC Mask            */
#define GPDMA_C0CONFIG_L_Pos                                  16                                                        /*!< GPDMA C0CONFIG: L Position          */
#define GPDMA_C0CONFIG_L_Msk                                  (0x01UL << GPDMA_C0CONFIG_L_Pos)                          /*!< GPDMA C0CONFIG: L Mask              */
#define GPDMA_C0CONFIG_A_Pos                                  17                                                        /*!< GPDMA C0CONFIG: A Position          */
#define GPDMA_C0CONFIG_A_Msk                                  (0x01UL << GPDMA_C0CONFIG_A_Pos)                          /*!< GPDMA C0CONFIG: A Mask              */
#define GPDMA_C0CONFIG_H_Pos                                  18                                                        /*!< GPDMA C0CONFIG: H Position          */
#define GPDMA_C0CONFIG_H_Msk                                  (0x01UL << GPDMA_C0CONFIG_H_Pos)                          /*!< GPDMA C0CONFIG: H Mask              */

// -------------------------------------  GPDMA_C1SRCADDR  ----------------------------------------
#define GPDMA_C1SRCADDR_SRCADDR_Pos                           0                                                         /*!< GPDMA C1SRCADDR: SRCADDR Position   */
#define GPDMA_C1SRCADDR_SRCADDR_Msk                           (0xffffffffUL << GPDMA_C1SRCADDR_SRCADDR_Pos)             /*!< GPDMA C1SRCADDR: SRCADDR Mask       */

// ------------------------------------  GPDMA_C1DESTADDR  ----------------------------------------
#define GPDMA_C1DESTADDR_DESTADDR_Pos                         0                                                         /*!< GPDMA C1DESTADDR: DESTADDR Position */
#define GPDMA_C1DESTADDR_DESTADDR_Msk                         (0xffffffffUL << GPDMA_C1DESTADDR_DESTADDR_Pos)           /*!< GPDMA C1DESTADDR: DESTADDR Mask     */

// ---------------------------------------  GPDMA_C1LLI  ------------------------------------------
#define GPDMA_C1LLI_LM_Pos                                    0                                                         /*!< GPDMA C1LLI: LM Position            */
#define GPDMA_C1LLI_LM_Msk                                    (0x01UL << GPDMA_C1LLI_LM_Pos)                            /*!< GPDMA C1LLI: LM Mask                */
#define GPDMA_C1LLI_R_Pos                                     1                                                         /*!< GPDMA C1LLI: R Position             */
#define GPDMA_C1LLI_R_Msk                                     (0x01UL << GPDMA_C1LLI_R_Pos)                             /*!< GPDMA C1LLI: R Mask                 */
#define GPDMA_C1LLI_LLI_Pos                                   2                                                         /*!< GPDMA C1LLI: LLI Position           */
#define GPDMA_C1LLI_LLI_Msk                                   (0x3fffffffUL << GPDMA_C1LLI_LLI_Pos)                     /*!< GPDMA C1LLI: LLI Mask               */

// -------------------------------------  GPDMA_C1CONTROL  ----------------------------------------
#define GPDMA_C1CONTROL_TRANSFERSIZE_Pos                      0                                                         /*!< GPDMA C1CONTROL: TRANSFERSIZE Position */
#define GPDMA_C1CONTROL_TRANSFERSIZE_Msk                      (0x00000fffUL << GPDMA_C1CONTROL_TRANSFERSIZE_Pos)        /*!< GPDMA C1CONTROL: TRANSFERSIZE Mask  */
#define GPDMA_C1CONTROL_SBSIZE_Pos                            12                                                        /*!< GPDMA C1CONTROL: SBSIZE Position    */
#define GPDMA_C1CONTROL_SBSIZE_Msk                            (0x07UL << GPDMA_C1CONTROL_SBSIZE_Pos)                    /*!< GPDMA C1CONTROL: SBSIZE Mask        */
#define GPDMA_C1CONTROL_DBSIZE_Pos                            15                                                        /*!< GPDMA C1CONTROL: DBSIZE Position    */
#define GPDMA_C1CONTROL_DBSIZE_Msk                            (0x07UL << GPDMA_C1CONTROL_DBSIZE_Pos)                    /*!< GPDMA C1CONTROL: DBSIZE Mask        */
#define GPDMA_C1CONTROL_SWIDTH_Pos                            18                                                        /*!< GPDMA C1CONTROL: SWIDTH Position    */
#define GPDMA_C1CONTROL_SWIDTH_Msk                            (0x07UL << GPDMA_C1CONTROL_SWIDTH_Pos)                    /*!< GPDMA C1CONTROL: SWIDTH Mask        */
#define GPDMA_C1CONTROL_DWIDTH_Pos                            21                                                        /*!< GPDMA C1CONTROL: DWIDTH Position    */
#define GPDMA_C1CONTROL_DWIDTH_Msk                            (0x07UL << GPDMA_C1CONTROL_DWIDTH_Pos)                    /*!< GPDMA C1CONTROL: DWIDTH Mask        */
#define GPDMA_C1CONTROL_S_Pos                                 24                                                        /*!< GPDMA C1CONTROL: S Position         */
#define GPDMA_C1CONTROL_S_Msk                                 (0x01UL << GPDMA_C1CONTROL_S_Pos)                         /*!< GPDMA C1CONTROL: S Mask             */
#define GPDMA_C1CONTROL_D_Pos                                 25                                                        /*!< GPDMA C1CONTROL: D Position         */
#define GPDMA_C1CONTROL_D_Msk                                 (0x01UL << GPDMA_C1CONTROL_D_Pos)                         /*!< GPDMA C1CONTROL: D Mask             */
#define GPDMA_C1CONTROL_SI_Pos                                26                                                        /*!< GPDMA C1CONTROL: SI Position        */
#define GPDMA_C1CONTROL_SI_Msk                                (0x01UL << GPDMA_C1CONTROL_SI_Pos)                        /*!< GPDMA C1CONTROL: SI Mask            */
#define GPDMA_C1CONTROL_DI_Pos                                27                                                        /*!< GPDMA C1CONTROL: DI Position        */
#define GPDMA_C1CONTROL_DI_Msk                                (0x01UL << GPDMA_C1CONTROL_DI_Pos)                        /*!< GPDMA C1CONTROL: DI Mask            */
#define GPDMA_C1CONTROL_PROT1_Pos                             28                                                        /*!< GPDMA C1CONTROL: PROT1 Position     */
#define GPDMA_C1CONTROL_PROT1_Msk                             (0x01UL << GPDMA_C1CONTROL_PROT1_Pos)                     /*!< GPDMA C1CONTROL: PROT1 Mask         */
#define GPDMA_C1CONTROL_PROT2_Pos                             29                                                        /*!< GPDMA C1CONTROL: PROT2 Position     */
#define GPDMA_C1CONTROL_PROT2_Msk                             (0x01UL << GPDMA_C1CONTROL_PROT2_Pos)                     /*!< GPDMA C1CONTROL: PROT2 Mask         */
#define GPDMA_C1CONTROL_PROT3_Pos                             30                                                        /*!< GPDMA C1CONTROL: PROT3 Position     */
#define GPDMA_C1CONTROL_PROT3_Msk                             (0x01UL << GPDMA_C1CONTROL_PROT3_Pos)                     /*!< GPDMA C1CONTROL: PROT3 Mask         */
#define GPDMA_C1CONTROL_I_Pos                                 31                                                        /*!< GPDMA C1CONTROL: I Position         */
#define GPDMA_C1CONTROL_I_Msk                                 (0x01UL << GPDMA_C1CONTROL_I_Pos)                         /*!< GPDMA C1CONTROL: I Mask             */

// -------------------------------------  GPDMA_C1CONFIG  -----------------------------------------
#define GPDMA_C1CONFIG_E_Pos                                  0                                                         /*!< GPDMA C1CONFIG: E Position          */
#define GPDMA_C1CONFIG_E_Msk                                  (0x01UL << GPDMA_C1CONFIG_E_Pos)                          /*!< GPDMA C1CONFIG: E Mask              */
#define GPDMA_C1CONFIG_SRCPERIPHERAL_Pos                      1                                                         /*!< GPDMA C1CONFIG: SRCPERIPHERAL Position */
#define GPDMA_C1CONFIG_SRCPERIPHERAL_Msk                      (0x1fUL << GPDMA_C1CONFIG_SRCPERIPHERAL_Pos)              /*!< GPDMA C1CONFIG: SRCPERIPHERAL Mask  */
#define GPDMA_C1CONFIG_DESTPERIPHERAL_Pos                     6                                                         /*!< GPDMA C1CONFIG: DESTPERIPHERAL Position */
#define GPDMA_C1CONFIG_DESTPERIPHERAL_Msk                     (0x1fUL << GPDMA_C1CONFIG_DESTPERIPHERAL_Pos)             /*!< GPDMA C1CONFIG: DESTPERIPHERAL Mask */
#define GPDMA_C1CONFIG_FLOWCNTRL_Pos                          11                                                        /*!< GPDMA C1CONFIG: FLOWCNTRL Position  */
#define GPDMA_C1CONFIG_FLOWCNTRL_Msk                          (0x07UL << GPDMA_C1CONFIG_FLOWCNTRL_Pos)                  /*!< GPDMA C1CONFIG: FLOWCNTRL Mask      */
#define GPDMA_C1CONFIG_IE_Pos                                 14                                                        /*!< GPDMA C1CONFIG: IE Position         */
#define GPDMA_C1CONFIG_IE_Msk                                 (0x01UL << GPDMA_C1CONFIG_IE_Pos)                         /*!< GPDMA C1CONFIG: IE Mask             */
#define GPDMA_C1CONFIG_ITC_Pos                                15                                                        /*!< GPDMA C1CONFIG: ITC Position        */
#define GPDMA_C1CONFIG_ITC_Msk                                (0x01UL << GPDMA_C1CONFIG_ITC_Pos)                        /*!< GPDMA C1CONFIG: ITC Mask            */
#define GPDMA_C1CONFIG_L_Pos                                  16                                                        /*!< GPDMA C1CONFIG: L Position          */
#define GPDMA_C1CONFIG_L_Msk                                  (0x01UL << GPDMA_C1CONFIG_L_Pos)                          /*!< GPDMA C1CONFIG: L Mask              */
#define GPDMA_C1CONFIG_A_Pos                                  17                                                        /*!< GPDMA C1CONFIG: A Position          */
#define GPDMA_C1CONFIG_A_Msk                                  (0x01UL << GPDMA_C1CONFIG_A_Pos)                          /*!< GPDMA C1CONFIG: A Mask              */
#define GPDMA_C1CONFIG_H_Pos                                  18                                                        /*!< GPDMA C1CONFIG: H Position          */
#define GPDMA_C1CONFIG_H_Msk                                  (0x01UL << GPDMA_C1CONFIG_H_Pos)                          /*!< GPDMA C1CONFIG: H Mask              */

// -------------------------------------  GPDMA_C2SRCADDR  ----------------------------------------
#define GPDMA_C2SRCADDR_SRCADDR_Pos                           0                                                         /*!< GPDMA C2SRCADDR: SRCADDR Position   */
#define GPDMA_C2SRCADDR_SRCADDR_Msk                           (0xffffffffUL << GPDMA_C2SRCADDR_SRCADDR_Pos)             /*!< GPDMA C2SRCADDR: SRCADDR Mask       */

// ------------------------------------  GPDMA_C2DESTADDR  ----------------------------------------
#define GPDMA_C2DESTADDR_DESTADDR_Pos                         0                                                         /*!< GPDMA C2DESTADDR: DESTADDR Position */
#define GPDMA_C2DESTADDR_DESTADDR_Msk                         (0xffffffffUL << GPDMA_C2DESTADDR_DESTADDR_Pos)           /*!< GPDMA C2DESTADDR: DESTADDR Mask     */

// ---------------------------------------  GPDMA_C2LLI  ------------------------------------------
#define GPDMA_C2LLI_LM_Pos                                    0                                                         /*!< GPDMA C2LLI: LM Position            */
#define GPDMA_C2LLI_LM_Msk                                    (0x01UL << GPDMA_C2LLI_LM_Pos)                            /*!< GPDMA C2LLI: LM Mask                */
#define GPDMA_C2LLI_R_Pos                                     1                                                         /*!< GPDMA C2LLI: R Position             */
#define GPDMA_C2LLI_R_Msk                                     (0x01UL << GPDMA_C2LLI_R_Pos)                             /*!< GPDMA C2LLI: R Mask                 */
#define GPDMA_C2LLI_LLI_Pos                                   2                                                         /*!< GPDMA C2LLI: LLI Position           */
#define GPDMA_C2LLI_LLI_Msk                                   (0x3fffffffUL << GPDMA_C2LLI_LLI_Pos)                     /*!< GPDMA C2LLI: LLI Mask               */

// -------------------------------------  GPDMA_C2CONTROL  ----------------------------------------
#define GPDMA_C2CONTROL_TRANSFERSIZE_Pos                      0                                                         /*!< GPDMA C2CONTROL: TRANSFERSIZE Position */
#define GPDMA_C2CONTROL_TRANSFERSIZE_Msk                      (0x00000fffUL << GPDMA_C2CONTROL_TRANSFERSIZE_Pos)        /*!< GPDMA C2CONTROL: TRANSFERSIZE Mask  */
#define GPDMA_C2CONTROL_SBSIZE_Pos                            12                                                        /*!< GPDMA C2CONTROL: SBSIZE Position    */
#define GPDMA_C2CONTROL_SBSIZE_Msk                            (0x07UL << GPDMA_C2CONTROL_SBSIZE_Pos)                    /*!< GPDMA C2CONTROL: SBSIZE Mask        */
#define GPDMA_C2CONTROL_DBSIZE_Pos                            15                                                        /*!< GPDMA C2CONTROL: DBSIZE Position    */
#define GPDMA_C2CONTROL_DBSIZE_Msk                            (0x07UL << GPDMA_C2CONTROL_DBSIZE_Pos)                    /*!< GPDMA C2CONTROL: DBSIZE Mask        */
#define GPDMA_C2CONTROL_SWIDTH_Pos                            18                                                        /*!< GPDMA C2CONTROL: SWIDTH Position    */
#define GPDMA_C2CONTROL_SWIDTH_Msk                            (0x07UL << GPDMA_C2CONTROL_SWIDTH_Pos)                    /*!< GPDMA C2CONTROL: SWIDTH Mask        */
#define GPDMA_C2CONTROL_DWIDTH_Pos                            21                                                        /*!< GPDMA C2CONTROL: DWIDTH Position    */
#define GPDMA_C2CONTROL_DWIDTH_Msk                            (0x07UL << GPDMA_C2CONTROL_DWIDTH_Pos)                    /*!< GPDMA C2CONTROL: DWIDTH Mask        */
#define GPDMA_C2CONTROL_S_Pos                                 24                                                        /*!< GPDMA C2CONTROL: S Position         */
#define GPDMA_C2CONTROL_S_Msk                                 (0x01UL << GPDMA_C2CONTROL_S_Pos)                         /*!< GPDMA C2CONTROL: S Mask             */
#define GPDMA_C2CONTROL_D_Pos                                 25                                                        /*!< GPDMA C2CONTROL: D Position         */
#define GPDMA_C2CONTROL_D_Msk                                 (0x01UL << GPDMA_C2CONTROL_D_Pos)                         /*!< GPDMA C2CONTROL: D Mask             */
#define GPDMA_C2CONTROL_SI_Pos                                26                                                        /*!< GPDMA C2CONTROL: SI Position        */
#define GPDMA_C2CONTROL_SI_Msk                                (0x01UL << GPDMA_C2CONTROL_SI_Pos)                        /*!< GPDMA C2CONTROL: SI Mask            */
#define GPDMA_C2CONTROL_DI_Pos                                27                                                        /*!< GPDMA C2CONTROL: DI Position        */
#define GPDMA_C2CONTROL_DI_Msk                                (0x01UL << GPDMA_C2CONTROL_DI_Pos)                        /*!< GPDMA C2CONTROL: DI Mask            */
#define GPDMA_C2CONTROL_PROT1_Pos                             28                                                        /*!< GPDMA C2CONTROL: PROT1 Position     */
#define GPDMA_C2CONTROL_PROT1_Msk                             (0x01UL << GPDMA_C2CONTROL_PROT1_Pos)                     /*!< GPDMA C2CONTROL: PROT1 Mask         */
#define GPDMA_C2CONTROL_PROT2_Pos                             29                                                        /*!< GPDMA C2CONTROL: PROT2 Position     */
#define GPDMA_C2CONTROL_PROT2_Msk                             (0x01UL << GPDMA_C2CONTROL_PROT2_Pos)                     /*!< GPDMA C2CONTROL: PROT2 Mask         */
#define GPDMA_C2CONTROL_PROT3_Pos                             30                                                        /*!< GPDMA C2CONTROL: PROT3 Position     */
#define GPDMA_C2CONTROL_PROT3_Msk                             (0x01UL << GPDMA_C2CONTROL_PROT3_Pos)                     /*!< GPDMA C2CONTROL: PROT3 Mask         */
#define GPDMA_C2CONTROL_I_Pos                                 31                                                        /*!< GPDMA C2CONTROL: I Position         */
#define GPDMA_C2CONTROL_I_Msk                                 (0x01UL << GPDMA_C2CONTROL_I_Pos)                         /*!< GPDMA C2CONTROL: I Mask             */

// -------------------------------------  GPDMA_C2CONFIG  -----------------------------------------
#define GPDMA_C2CONFIG_E_Pos                                  0                                                         /*!< GPDMA C2CONFIG: E Position          */
#define GPDMA_C2CONFIG_E_Msk                                  (0x01UL << GPDMA_C2CONFIG_E_Pos)                          /*!< GPDMA C2CONFIG: E Mask              */
#define GPDMA_C2CONFIG_SRCPERIPHERAL_Pos                      1                                                         /*!< GPDMA C2CONFIG: SRCPERIPHERAL Position */
#define GPDMA_C2CONFIG_SRCPERIPHERAL_Msk                      (0x1fUL << GPDMA_C2CONFIG_SRCPERIPHERAL_Pos)              /*!< GPDMA C2CONFIG: SRCPERIPHERAL Mask  */
#define GPDMA_C2CONFIG_DESTPERIPHERAL_Pos                     6                                                         /*!< GPDMA C2CONFIG: DESTPERIPHERAL Position */
#define GPDMA_C2CONFIG_DESTPERIPHERAL_Msk                     (0x1fUL << GPDMA_C2CONFIG_DESTPERIPHERAL_Pos)             /*!< GPDMA C2CONFIG: DESTPERIPHERAL Mask */
#define GPDMA_C2CONFIG_FLOWCNTRL_Pos                          11                                                        /*!< GPDMA C2CONFIG: FLOWCNTRL Position  */
#define GPDMA_C2CONFIG_FLOWCNTRL_Msk                          (0x07UL << GPDMA_C2CONFIG_FLOWCNTRL_Pos)                  /*!< GPDMA C2CONFIG: FLOWCNTRL Mask      */
#define GPDMA_C2CONFIG_IE_Pos                                 14                                                        /*!< GPDMA C2CONFIG: IE Position         */
#define GPDMA_C2CONFIG_IE_Msk                                 (0x01UL << GPDMA_C2CONFIG_IE_Pos)                         /*!< GPDMA C2CONFIG: IE Mask             */
#define GPDMA_C2CONFIG_ITC_Pos                                15                                                        /*!< GPDMA C2CONFIG: ITC Position        */
#define GPDMA_C2CONFIG_ITC_Msk                                (0x01UL << GPDMA_C2CONFIG_ITC_Pos)                        /*!< GPDMA C2CONFIG: ITC Mask            */
#define GPDMA_C2CONFIG_L_Pos                                  16                                                        /*!< GPDMA C2CONFIG: L Position          */
#define GPDMA_C2CONFIG_L_Msk                                  (0x01UL << GPDMA_C2CONFIG_L_Pos)                          /*!< GPDMA C2CONFIG: L Mask              */
#define GPDMA_C2CONFIG_A_Pos                                  17                                                        /*!< GPDMA C2CONFIG: A Position          */
#define GPDMA_C2CONFIG_A_Msk                                  (0x01UL << GPDMA_C2CONFIG_A_Pos)                          /*!< GPDMA C2CONFIG: A Mask              */
#define GPDMA_C2CONFIG_H_Pos                                  18                                                        /*!< GPDMA C2CONFIG: H Position          */
#define GPDMA_C2CONFIG_H_Msk                                  (0x01UL << GPDMA_C2CONFIG_H_Pos)                          /*!< GPDMA C2CONFIG: H Mask              */

// -------------------------------------  GPDMA_C3SRCADDR  ----------------------------------------
#define GPDMA_C3SRCADDR_SRCADDR_Pos                           0                                                         /*!< GPDMA C3SRCADDR: SRCADDR Position   */
#define GPDMA_C3SRCADDR_SRCADDR_Msk                           (0xffffffffUL << GPDMA_C3SRCADDR_SRCADDR_Pos)             /*!< GPDMA C3SRCADDR: SRCADDR Mask       */

// ------------------------------------  GPDMA_C3DESTADDR  ----------------------------------------
#define GPDMA_C3DESTADDR_DESTADDR_Pos                         0                                                         /*!< GPDMA C3DESTADDR: DESTADDR Position */
#define GPDMA_C3DESTADDR_DESTADDR_Msk                         (0xffffffffUL << GPDMA_C3DESTADDR_DESTADDR_Pos)           /*!< GPDMA C3DESTADDR: DESTADDR Mask     */

// ---------------------------------------  GPDMA_C3LLI  ------------------------------------------
#define GPDMA_C3LLI_LM_Pos                                    0                                                         /*!< GPDMA C3LLI: LM Position            */
#define GPDMA_C3LLI_LM_Msk                                    (0x01UL << GPDMA_C3LLI_LM_Pos)                            /*!< GPDMA C3LLI: LM Mask                */
#define GPDMA_C3LLI_R_Pos                                     1                                                         /*!< GPDMA C3LLI: R Position             */
#define GPDMA_C3LLI_R_Msk                                     (0x01UL << GPDMA_C3LLI_R_Pos)                             /*!< GPDMA C3LLI: R Mask                 */
#define GPDMA_C3LLI_LLI_Pos                                   2                                                         /*!< GPDMA C3LLI: LLI Position           */
#define GPDMA_C3LLI_LLI_Msk                                   (0x3fffffffUL << GPDMA_C3LLI_LLI_Pos)                     /*!< GPDMA C3LLI: LLI Mask               */

// -------------------------------------  GPDMA_C3CONTROL  ----------------------------------------
#define GPDMA_C3CONTROL_TRANSFERSIZE_Pos                      0                                                         /*!< GPDMA C3CONTROL: TRANSFERSIZE Position */
#define GPDMA_C3CONTROL_TRANSFERSIZE_Msk                      (0x00000fffUL << GPDMA_C3CONTROL_TRANSFERSIZE_Pos)        /*!< GPDMA C3CONTROL: TRANSFERSIZE Mask  */
#define GPDMA_C3CONTROL_SBSIZE_Pos                            12                                                        /*!< GPDMA C3CONTROL: SBSIZE Position    */
#define GPDMA_C3CONTROL_SBSIZE_Msk                            (0x07UL << GPDMA_C3CONTROL_SBSIZE_Pos)                    /*!< GPDMA C3CONTROL: SBSIZE Mask        */
#define GPDMA_C3CONTROL_DBSIZE_Pos                            15                                                        /*!< GPDMA C3CONTROL: DBSIZE Position    */
#define GPDMA_C3CONTROL_DBSIZE_Msk                            (0x07UL << GPDMA_C3CONTROL_DBSIZE_Pos)                    /*!< GPDMA C3CONTROL: DBSIZE Mask        */
#define GPDMA_C3CONTROL_SWIDTH_Pos                            18                                                        /*!< GPDMA C3CONTROL: SWIDTH Position    */
#define GPDMA_C3CONTROL_SWIDTH_Msk                            (0x07UL << GPDMA_C3CONTROL_SWIDTH_Pos)                    /*!< GPDMA C3CONTROL: SWIDTH Mask        */
#define GPDMA_C3CONTROL_DWIDTH_Pos                            21                                                        /*!< GPDMA C3CONTROL: DWIDTH Position    */
#define GPDMA_C3CONTROL_DWIDTH_Msk                            (0x07UL << GPDMA_C3CONTROL_DWIDTH_Pos)                    /*!< GPDMA C3CONTROL: DWIDTH Mask        */
#define GPDMA_C3CONTROL_S_Pos                                 24                                                        /*!< GPDMA C3CONTROL: S Position         */
#define GPDMA_C3CONTROL_S_Msk                                 (0x01UL << GPDMA_C3CONTROL_S_Pos)                         /*!< GPDMA C3CONTROL: S Mask             */
#define GPDMA_C3CONTROL_D_Pos                                 25                                                        /*!< GPDMA C3CONTROL: D Position         */
#define GPDMA_C3CONTROL_D_Msk                                 (0x01UL << GPDMA_C3CONTROL_D_Pos)                         /*!< GPDMA C3CONTROL: D Mask             */
#define GPDMA_C3CONTROL_SI_Pos                                26                                                        /*!< GPDMA C3CONTROL: SI Position        */
#define GPDMA_C3CONTROL_SI_Msk                                (0x01UL << GPDMA_C3CONTROL_SI_Pos)                        /*!< GPDMA C3CONTROL: SI Mask            */
#define GPDMA_C3CONTROL_DI_Pos                                27                                                        /*!< GPDMA C3CONTROL: DI Position        */
#define GPDMA_C3CONTROL_DI_Msk                                (0x01UL << GPDMA_C3CONTROL_DI_Pos)                        /*!< GPDMA C3CONTROL: DI Mask            */
#define GPDMA_C3CONTROL_PROT1_Pos                             28                                                        /*!< GPDMA C3CONTROL: PROT1 Position     */
#define GPDMA_C3CONTROL_PROT1_Msk                             (0x01UL << GPDMA_C3CONTROL_PROT1_Pos)                     /*!< GPDMA C3CONTROL: PROT1 Mask         */
#define GPDMA_C3CONTROL_PROT2_Pos                             29                                                        /*!< GPDMA C3CONTROL: PROT2 Position     */
#define GPDMA_C3CONTROL_PROT2_Msk                             (0x01UL << GPDMA_C3CONTROL_PROT2_Pos)                     /*!< GPDMA C3CONTROL: PROT2 Mask         */
#define GPDMA_C3CONTROL_PROT3_Pos                             30                                                        /*!< GPDMA C3CONTROL: PROT3 Position     */
#define GPDMA_C3CONTROL_PROT3_Msk                             (0x01UL << GPDMA_C3CONTROL_PROT3_Pos)                     /*!< GPDMA C3CONTROL: PROT3 Mask         */
#define GPDMA_C3CONTROL_I_Pos                                 31                                                        /*!< GPDMA C3CONTROL: I Position         */
#define GPDMA_C3CONTROL_I_Msk                                 (0x01UL << GPDMA_C3CONTROL_I_Pos)                         /*!< GPDMA C3CONTROL: I Mask             */

// -------------------------------------  GPDMA_C3CONFIG  -----------------------------------------
#define GPDMA_C3CONFIG_E_Pos                                  0                                                         /*!< GPDMA C3CONFIG: E Position          */
#define GPDMA_C3CONFIG_E_Msk                                  (0x01UL << GPDMA_C3CONFIG_E_Pos)                          /*!< GPDMA C3CONFIG: E Mask              */
#define GPDMA_C3CONFIG_SRCPERIPHERAL_Pos                      1                                                         /*!< GPDMA C3CONFIG: SRCPERIPHERAL Position */
#define GPDMA_C3CONFIG_SRCPERIPHERAL_Msk                      (0x1fUL << GPDMA_C3CONFIG_SRCPERIPHERAL_Pos)              /*!< GPDMA C3CONFIG: SRCPERIPHERAL Mask  */
#define GPDMA_C3CONFIG_DESTPERIPHERAL_Pos                     6                                                         /*!< GPDMA C3CONFIG: DESTPERIPHERAL Position */
#define GPDMA_C3CONFIG_DESTPERIPHERAL_Msk                     (0x1fUL << GPDMA_C3CONFIG_DESTPERIPHERAL_Pos)             /*!< GPDMA C3CONFIG: DESTPERIPHERAL Mask */
#define GPDMA_C3CONFIG_FLOWCNTRL_Pos                          11                                                        /*!< GPDMA C3CONFIG: FLOWCNTRL Position  */
#define GPDMA_C3CONFIG_FLOWCNTRL_Msk                          (0x07UL << GPDMA_C3CONFIG_FLOWCNTRL_Pos)                  /*!< GPDMA C3CONFIG: FLOWCNTRL Mask      */
#define GPDMA_C3CONFIG_IE_Pos                                 14                                                        /*!< GPDMA C3CONFIG: IE Position         */
#define GPDMA_C3CONFIG_IE_Msk                                 (0x01UL << GPDMA_C3CONFIG_IE_Pos)                         /*!< GPDMA C3CONFIG: IE Mask             */
#define GPDMA_C3CONFIG_ITC_Pos                                15                                                        /*!< GPDMA C3CONFIG: ITC Position        */
#define GPDMA_C3CONFIG_ITC_Msk                                (0x01UL << GPDMA_C3CONFIG_ITC_Pos)                        /*!< GPDMA C3CONFIG: ITC Mask            */
#define GPDMA_C3CONFIG_L_Pos                                  16                                                        /*!< GPDMA C3CONFIG: L Position          */
#define GPDMA_C3CONFIG_L_Msk                                  (0x01UL << GPDMA_C3CONFIG_L_Pos)                          /*!< GPDMA C3CONFIG: L Mask              */
#define GPDMA_C3CONFIG_A_Pos                                  17                                                        /*!< GPDMA C3CONFIG: A Position          */
#define GPDMA_C3CONFIG_A_Msk                                  (0x01UL << GPDMA_C3CONFIG_A_Pos)                          /*!< GPDMA C3CONFIG: A Mask              */
#define GPDMA_C3CONFIG_H_Pos                                  18                                                        /*!< GPDMA C3CONFIG: H Position          */
#define GPDMA_C3CONFIG_H_Msk                                  (0x01UL << GPDMA_C3CONFIG_H_Pos)                          /*!< GPDMA C3CONFIG: H Mask              */

// -------------------------------------  GPDMA_C4SRCADDR  ----------------------------------------
#define GPDMA_C4SRCADDR_SRCADDR_Pos                           0                                                         /*!< GPDMA C4SRCADDR: SRCADDR Position   */
#define GPDMA_C4SRCADDR_SRCADDR_Msk                           (0xffffffffUL << GPDMA_C4SRCADDR_SRCADDR_Pos)             /*!< GPDMA C4SRCADDR: SRCADDR Mask       */

// ------------------------------------  GPDMA_C4DESTADDR  ----------------------------------------
#define GPDMA_C4DESTADDR_DESTADDR_Pos                         0                                                         /*!< GPDMA C4DESTADDR: DESTADDR Position */
#define GPDMA_C4DESTADDR_DESTADDR_Msk                         (0xffffffffUL << GPDMA_C4DESTADDR_DESTADDR_Pos)           /*!< GPDMA C4DESTADDR: DESTADDR Mask     */

// ---------------------------------------  GPDMA_C4LLI  ------------------------------------------
#define GPDMA_C4LLI_LM_Pos                                    0                                                         /*!< GPDMA C4LLI: LM Position            */
#define GPDMA_C4LLI_LM_Msk                                    (0x01UL << GPDMA_C4LLI_LM_Pos)                            /*!< GPDMA C4LLI: LM Mask                */
#define GPDMA_C4LLI_R_Pos                                     1                                                         /*!< GPDMA C4LLI: R Position             */
#define GPDMA_C4LLI_R_Msk                                     (0x01UL << GPDMA_C4LLI_R_Pos)                             /*!< GPDMA C4LLI: R Mask                 */
#define GPDMA_C4LLI_LLI_Pos                                   2                                                         /*!< GPDMA C4LLI: LLI Position           */
#define GPDMA_C4LLI_LLI_Msk                                   (0x3fffffffUL << GPDMA_C4LLI_LLI_Pos)                     /*!< GPDMA C4LLI: LLI Mask               */

// -------------------------------------  GPDMA_C4CONTROL  ----------------------------------------
#define GPDMA_C4CONTROL_TRANSFERSIZE_Pos                      0                                                         /*!< GPDMA C4CONTROL: TRANSFERSIZE Position */
#define GPDMA_C4CONTROL_TRANSFERSIZE_Msk                      (0x00000fffUL << GPDMA_C4CONTROL_TRANSFERSIZE_Pos)        /*!< GPDMA C4CONTROL: TRANSFERSIZE Mask  */
#define GPDMA_C4CONTROL_SBSIZE_Pos                            12                                                        /*!< GPDMA C4CONTROL: SBSIZE Position    */
#define GPDMA_C4CONTROL_SBSIZE_Msk                            (0x07UL << GPDMA_C4CONTROL_SBSIZE_Pos)                    /*!< GPDMA C4CONTROL: SBSIZE Mask        */
#define GPDMA_C4CONTROL_DBSIZE_Pos                            15                                                        /*!< GPDMA C4CONTROL: DBSIZE Position    */
#define GPDMA_C4CONTROL_DBSIZE_Msk                            (0x07UL << GPDMA_C4CONTROL_DBSIZE_Pos)                    /*!< GPDMA C4CONTROL: DBSIZE Mask        */
#define GPDMA_C4CONTROL_SWIDTH_Pos                            18                                                        /*!< GPDMA C4CONTROL: SWIDTH Position    */
#define GPDMA_C4CONTROL_SWIDTH_Msk                            (0x07UL << GPDMA_C4CONTROL_SWIDTH_Pos)                    /*!< GPDMA C4CONTROL: SWIDTH Mask        */
#define GPDMA_C4CONTROL_DWIDTH_Pos                            21                                                        /*!< GPDMA C4CONTROL: DWIDTH Position    */
#define GPDMA_C4CONTROL_DWIDTH_Msk                            (0x07UL << GPDMA_C4CONTROL_DWIDTH_Pos)                    /*!< GPDMA C4CONTROL: DWIDTH Mask        */
#define GPDMA_C4CONTROL_S_Pos                                 24                                                        /*!< GPDMA C4CONTROL: S Position         */
#define GPDMA_C4CONTROL_S_Msk                                 (0x01UL << GPDMA_C4CONTROL_S_Pos)                         /*!< GPDMA C4CONTROL: S Mask             */
#define GPDMA_C4CONTROL_D_Pos                                 25                                                        /*!< GPDMA C4CONTROL: D Position         */
#define GPDMA_C4CONTROL_D_Msk                                 (0x01UL << GPDMA_C4CONTROL_D_Pos)                         /*!< GPDMA C4CONTROL: D Mask             */
#define GPDMA_C4CONTROL_SI_Pos                                26                                                        /*!< GPDMA C4CONTROL: SI Position        */
#define GPDMA_C4CONTROL_SI_Msk                                (0x01UL << GPDMA_C4CONTROL_SI_Pos)                        /*!< GPDMA C4CONTROL: SI Mask            */
#define GPDMA_C4CONTROL_DI_Pos                                27                                                        /*!< GPDMA C4CONTROL: DI Position        */
#define GPDMA_C4CONTROL_DI_Msk                                (0x01UL << GPDMA_C4CONTROL_DI_Pos)                        /*!< GPDMA C4CONTROL: DI Mask            */
#define GPDMA_C4CONTROL_PROT1_Pos                             28                                                        /*!< GPDMA C4CONTROL: PROT1 Position     */
#define GPDMA_C4CONTROL_PROT1_Msk                             (0x01UL << GPDMA_C4CONTROL_PROT1_Pos)                     /*!< GPDMA C4CONTROL: PROT1 Mask         */
#define GPDMA_C4CONTROL_PROT2_Pos                             29                                                        /*!< GPDMA C4CONTROL: PROT2 Position     */
#define GPDMA_C4CONTROL_PROT2_Msk                             (0x01UL << GPDMA_C4CONTROL_PROT2_Pos)                     /*!< GPDMA C4CONTROL: PROT2 Mask         */
#define GPDMA_C4CONTROL_PROT3_Pos                             30                                                        /*!< GPDMA C4CONTROL: PROT3 Position     */
#define GPDMA_C4CONTROL_PROT3_Msk                             (0x01UL << GPDMA_C4CONTROL_PROT3_Pos)                     /*!< GPDMA C4CONTROL: PROT3 Mask         */
#define GPDMA_C4CONTROL_I_Pos                                 31                                                        /*!< GPDMA C4CONTROL: I Position         */
#define GPDMA_C4CONTROL_I_Msk                                 (0x01UL << GPDMA_C4CONTROL_I_Pos)                         /*!< GPDMA C4CONTROL: I Mask             */

// -------------------------------------  GPDMA_C4CONFIG  -----------------------------------------
#define GPDMA_C4CONFIG_E_Pos                                  0                                                         /*!< GPDMA C4CONFIG: E Position          */
#define GPDMA_C4CONFIG_E_Msk                                  (0x01UL << GPDMA_C4CONFIG_E_Pos)                          /*!< GPDMA C4CONFIG: E Mask              */
#define GPDMA_C4CONFIG_SRCPERIPHERAL_Pos                      1                                                         /*!< GPDMA C4CONFIG: SRCPERIPHERAL Position */
#define GPDMA_C4CONFIG_SRCPERIPHERAL_Msk                      (0x1fUL << GPDMA_C4CONFIG_SRCPERIPHERAL_Pos)              /*!< GPDMA C4CONFIG: SRCPERIPHERAL Mask  */
#define GPDMA_C4CONFIG_DESTPERIPHERAL_Pos                     6                                                         /*!< GPDMA C4CONFIG: DESTPERIPHERAL Position */
#define GPDMA_C4CONFIG_DESTPERIPHERAL_Msk                     (0x1fUL << GPDMA_C4CONFIG_DESTPERIPHERAL_Pos)             /*!< GPDMA C4CONFIG: DESTPERIPHERAL Mask */
#define GPDMA_C4CONFIG_FLOWCNTRL_Pos                          11                                                        /*!< GPDMA C4CONFIG: FLOWCNTRL Position  */
#define GPDMA_C4CONFIG_FLOWCNTRL_Msk                          (0x07UL << GPDMA_C4CONFIG_FLOWCNTRL_Pos)                  /*!< GPDMA C4CONFIG: FLOWCNTRL Mask      */
#define GPDMA_C4CONFIG_IE_Pos                                 14                                                        /*!< GPDMA C4CONFIG: IE Position         */
#define GPDMA_C4CONFIG_IE_Msk                                 (0x01UL << GPDMA_C4CONFIG_IE_Pos)                         /*!< GPDMA C4CONFIG: IE Mask             */
#define GPDMA_C4CONFIG_ITC_Pos                                15                                                        /*!< GPDMA C4CONFIG: ITC Position        */
#define GPDMA_C4CONFIG_ITC_Msk                                (0x01UL << GPDMA_C4CONFIG_ITC_Pos)                        /*!< GPDMA C4CONFIG: ITC Mask            */
#define GPDMA_C4CONFIG_L_Pos                                  16                                                        /*!< GPDMA C4CONFIG: L Position          */
#define GPDMA_C4CONFIG_L_Msk                                  (0x01UL << GPDMA_C4CONFIG_L_Pos)                          /*!< GPDMA C4CONFIG: L Mask              */
#define GPDMA_C4CONFIG_A_Pos                                  17                                                        /*!< GPDMA C4CONFIG: A Position          */
#define GPDMA_C4CONFIG_A_Msk                                  (0x01UL << GPDMA_C4CONFIG_A_Pos)                          /*!< GPDMA C4CONFIG: A Mask              */
#define GPDMA_C4CONFIG_H_Pos                                  18                                                        /*!< GPDMA C4CONFIG: H Position          */
#define GPDMA_C4CONFIG_H_Msk                                  (0x01UL << GPDMA_C4CONFIG_H_Pos)                          /*!< GPDMA C4CONFIG: H Mask              */

// -------------------------------------  GPDMA_C5SRCADDR  ----------------------------------------
#define GPDMA_C5SRCADDR_SRCADDR_Pos                           0                                                         /*!< GPDMA C5SRCADDR: SRCADDR Position   */
#define GPDMA_C5SRCADDR_SRCADDR_Msk                           (0xffffffffUL << GPDMA_C5SRCADDR_SRCADDR_Pos)             /*!< GPDMA C5SRCADDR: SRCADDR Mask       */

// ------------------------------------  GPDMA_C5DESTADDR  ----------------------------------------
#define GPDMA_C5DESTADDR_DESTADDR_Pos                         0                                                         /*!< GPDMA C5DESTADDR: DESTADDR Position */
#define GPDMA_C5DESTADDR_DESTADDR_Msk                         (0xffffffffUL << GPDMA_C5DESTADDR_DESTADDR_Pos)           /*!< GPDMA C5DESTADDR: DESTADDR Mask     */

// ---------------------------------------  GPDMA_C5LLI  ------------------------------------------
#define GPDMA_C5LLI_LM_Pos                                    0                                                         /*!< GPDMA C5LLI: LM Position            */
#define GPDMA_C5LLI_LM_Msk                                    (0x01UL << GPDMA_C5LLI_LM_Pos)                            /*!< GPDMA C5LLI: LM Mask                */
#define GPDMA_C5LLI_R_Pos                                     1                                                         /*!< GPDMA C5LLI: R Position             */
#define GPDMA_C5LLI_R_Msk                                     (0x01UL << GPDMA_C5LLI_R_Pos)                             /*!< GPDMA C5LLI: R Mask                 */
#define GPDMA_C5LLI_LLI_Pos                                   2                                                         /*!< GPDMA C5LLI: LLI Position           */
#define GPDMA_C5LLI_LLI_Msk                                   (0x3fffffffUL << GPDMA_C5LLI_LLI_Pos)                     /*!< GPDMA C5LLI: LLI Mask               */

// -------------------------------------  GPDMA_C5CONTROL  ----------------------------------------
#define GPDMA_C5CONTROL_TRANSFERSIZE_Pos                      0                                                         /*!< GPDMA C5CONTROL: TRANSFERSIZE Position */
#define GPDMA_C5CONTROL_TRANSFERSIZE_Msk                      (0x00000fffUL << GPDMA_C5CONTROL_TRANSFERSIZE_Pos)        /*!< GPDMA C5CONTROL: TRANSFERSIZE Mask  */
#define GPDMA_C5CONTROL_SBSIZE_Pos                            12                                                        /*!< GPDMA C5CONTROL: SBSIZE Position    */
#define GPDMA_C5CONTROL_SBSIZE_Msk                            (0x07UL << GPDMA_C5CONTROL_SBSIZE_Pos)                    /*!< GPDMA C5CONTROL: SBSIZE Mask        */
#define GPDMA_C5CONTROL_DBSIZE_Pos                            15                                                        /*!< GPDMA C5CONTROL: DBSIZE Position    */
#define GPDMA_C5CONTROL_DBSIZE_Msk                            (0x07UL << GPDMA_C5CONTROL_DBSIZE_Pos)                    /*!< GPDMA C5CONTROL: DBSIZE Mask        */
#define GPDMA_C5CONTROL_SWIDTH_Pos                            18                                                        /*!< GPDMA C5CONTROL: SWIDTH Position    */
#define GPDMA_C5CONTROL_SWIDTH_Msk                            (0x07UL << GPDMA_C5CONTROL_SWIDTH_Pos)                    /*!< GPDMA C5CONTROL: SWIDTH Mask        */
#define GPDMA_C5CONTROL_DWIDTH_Pos                            21                                                        /*!< GPDMA C5CONTROL: DWIDTH Position    */
#define GPDMA_C5CONTROL_DWIDTH_Msk                            (0x07UL << GPDMA_C5CONTROL_DWIDTH_Pos)                    /*!< GPDMA C5CONTROL: DWIDTH Mask        */
#define GPDMA_C5CONTROL_S_Pos                                 24                                                        /*!< GPDMA C5CONTROL: S Position         */
#define GPDMA_C5CONTROL_S_Msk                                 (0x01UL << GPDMA_C5CONTROL_S_Pos)                         /*!< GPDMA C5CONTROL: S Mask             */
#define GPDMA_C5CONTROL_D_Pos                                 25                                                        /*!< GPDMA C5CONTROL: D Position         */
#define GPDMA_C5CONTROL_D_Msk                                 (0x01UL << GPDMA_C5CONTROL_D_Pos)                         /*!< GPDMA C5CONTROL: D Mask             */
#define GPDMA_C5CONTROL_SI_Pos                                26                                                        /*!< GPDMA C5CONTROL: SI Position        */
#define GPDMA_C5CONTROL_SI_Msk                                (0x01UL << GPDMA_C5CONTROL_SI_Pos)                        /*!< GPDMA C5CONTROL: SI Mask            */
#define GPDMA_C5CONTROL_DI_Pos                                27                                                        /*!< GPDMA C5CONTROL: DI Position        */
#define GPDMA_C5CONTROL_DI_Msk                                (0x01UL << GPDMA_C5CONTROL_DI_Pos)                        /*!< GPDMA C5CONTROL: DI Mask            */
#define GPDMA_C5CONTROL_PROT1_Pos                             28                                                        /*!< GPDMA C5CONTROL: PROT1 Position     */
#define GPDMA_C5CONTROL_PROT1_Msk                             (0x01UL << GPDMA_C5CONTROL_PROT1_Pos)                     /*!< GPDMA C5CONTROL: PROT1 Mask         */
#define GPDMA_C5CONTROL_PROT2_Pos                             29                                                        /*!< GPDMA C5CONTROL: PROT2 Position     */
#define GPDMA_C5CONTROL_PROT2_Msk                             (0x01UL << GPDMA_C5CONTROL_PROT2_Pos)                     /*!< GPDMA C5CONTROL: PROT2 Mask         */
#define GPDMA_C5CONTROL_PROT3_Pos                             30                                                        /*!< GPDMA C5CONTROL: PROT3 Position     */
#define GPDMA_C5CONTROL_PROT3_Msk                             (0x01UL << GPDMA_C5CONTROL_PROT3_Pos)                     /*!< GPDMA C5CONTROL: PROT3 Mask         */
#define GPDMA_C5CONTROL_I_Pos                                 31                                                        /*!< GPDMA C5CONTROL: I Position         */
#define GPDMA_C5CONTROL_I_Msk                                 (0x01UL << GPDMA_C5CONTROL_I_Pos)                         /*!< GPDMA C5CONTROL: I Mask             */

// -------------------------------------  GPDMA_C5CONFIG  -----------------------------------------
#define GPDMA_C5CONFIG_E_Pos                                  0                                                         /*!< GPDMA C5CONFIG: E Position          */
#define GPDMA_C5CONFIG_E_Msk                                  (0x01UL << GPDMA_C5CONFIG_E_Pos)                          /*!< GPDMA C5CONFIG: E Mask              */
#define GPDMA_C5CONFIG_SRCPERIPHERAL_Pos                      1                                                         /*!< GPDMA C5CONFIG: SRCPERIPHERAL Position */
#define GPDMA_C5CONFIG_SRCPERIPHERAL_Msk                      (0x1fUL << GPDMA_C5CONFIG_SRCPERIPHERAL_Pos)              /*!< GPDMA C5CONFIG: SRCPERIPHERAL Mask  */
#define GPDMA_C5CONFIG_DESTPERIPHERAL_Pos                     6                                                         /*!< GPDMA C5CONFIG: DESTPERIPHERAL Position */
#define GPDMA_C5CONFIG_DESTPERIPHERAL_Msk                     (0x1fUL << GPDMA_C5CONFIG_DESTPERIPHERAL_Pos)             /*!< GPDMA C5CONFIG: DESTPERIPHERAL Mask */
#define GPDMA_C5CONFIG_FLOWCNTRL_Pos                          11                                                        /*!< GPDMA C5CONFIG: FLOWCNTRL Position  */
#define GPDMA_C5CONFIG_FLOWCNTRL_Msk                          (0x07UL << GPDMA_C5CONFIG_FLOWCNTRL_Pos)                  /*!< GPDMA C5CONFIG: FLOWCNTRL Mask      */
#define GPDMA_C5CONFIG_IE_Pos                                 14                                                        /*!< GPDMA C5CONFIG: IE Position         */
#define GPDMA_C5CONFIG_IE_Msk                                 (0x01UL << GPDMA_C5CONFIG_IE_Pos)                         /*!< GPDMA C5CONFIG: IE Mask             */
#define GPDMA_C5CONFIG_ITC_Pos                                15                                                        /*!< GPDMA C5CONFIG: ITC Position        */
#define GPDMA_C5CONFIG_ITC_Msk                                (0x01UL << GPDMA_C5CONFIG_ITC_Pos)                        /*!< GPDMA C5CONFIG: ITC Mask            */
#define GPDMA_C5CONFIG_L_Pos                                  16                                                        /*!< GPDMA C5CONFIG: L Position          */
#define GPDMA_C5CONFIG_L_Msk                                  (0x01UL << GPDMA_C5CONFIG_L_Pos)                          /*!< GPDMA C5CONFIG: L Mask              */
#define GPDMA_C5CONFIG_A_Pos                                  17                                                        /*!< GPDMA C5CONFIG: A Position          */
#define GPDMA_C5CONFIG_A_Msk                                  (0x01UL << GPDMA_C5CONFIG_A_Pos)                          /*!< GPDMA C5CONFIG: A Mask              */
#define GPDMA_C5CONFIG_H_Pos                                  18                                                        /*!< GPDMA C5CONFIG: H Position          */
#define GPDMA_C5CONFIG_H_Msk                                  (0x01UL << GPDMA_C5CONFIG_H_Pos)                          /*!< GPDMA C5CONFIG: H Mask              */

// -------------------------------------  GPDMA_C6SRCADDR  ----------------------------------------
#define GPDMA_C6SRCADDR_SRCADDR_Pos                           0                                                         /*!< GPDMA C6SRCADDR: SRCADDR Position   */
#define GPDMA_C6SRCADDR_SRCADDR_Msk                           (0xffffffffUL << GPDMA_C6SRCADDR_SRCADDR_Pos)             /*!< GPDMA C6SRCADDR: SRCADDR Mask       */

// ------------------------------------  GPDMA_C6DESTADDR  ----------------------------------------
#define GPDMA_C6DESTADDR_DESTADDR_Pos                         0                                                         /*!< GPDMA C6DESTADDR: DESTADDR Position */
#define GPDMA_C6DESTADDR_DESTADDR_Msk                         (0xffffffffUL << GPDMA_C6DESTADDR_DESTADDR_Pos)           /*!< GPDMA C6DESTADDR: DESTADDR Mask     */

// ---------------------------------------  GPDMA_C6LLI  ------------------------------------------
#define GPDMA_C6LLI_LM_Pos                                    0                                                         /*!< GPDMA C6LLI: LM Position            */
#define GPDMA_C6LLI_LM_Msk                                    (0x01UL << GPDMA_C6LLI_LM_Pos)                            /*!< GPDMA C6LLI: LM Mask                */
#define GPDMA_C6LLI_R_Pos                                     1                                                         /*!< GPDMA C6LLI: R Position             */
#define GPDMA_C6LLI_R_Msk                                     (0x01UL << GPDMA_C6LLI_R_Pos)                             /*!< GPDMA C6LLI: R Mask                 */
#define GPDMA_C6LLI_LLI_Pos                                   2                                                         /*!< GPDMA C6LLI: LLI Position           */
#define GPDMA_C6LLI_LLI_Msk                                   (0x3fffffffUL << GPDMA_C6LLI_LLI_Pos)                     /*!< GPDMA C6LLI: LLI Mask               */

// -------------------------------------  GPDMA_C6CONTROL  ----------------------------------------
#define GPDMA_C6CONTROL_TRANSFERSIZE_Pos                      0                                                         /*!< GPDMA C6CONTROL: TRANSFERSIZE Position */
#define GPDMA_C6CONTROL_TRANSFERSIZE_Msk                      (0x00000fffUL << GPDMA_C6CONTROL_TRANSFERSIZE_Pos)        /*!< GPDMA C6CONTROL: TRANSFERSIZE Mask  */
#define GPDMA_C6CONTROL_SBSIZE_Pos                            12                                                        /*!< GPDMA C6CONTROL: SBSIZE Position    */
#define GPDMA_C6CONTROL_SBSIZE_Msk                            (0x07UL << GPDMA_C6CONTROL_SBSIZE_Pos)                    /*!< GPDMA C6CONTROL: SBSIZE Mask        */
#define GPDMA_C6CONTROL_DBSIZE_Pos                            15                                                        /*!< GPDMA C6CONTROL: DBSIZE Position    */
#define GPDMA_C6CONTROL_DBSIZE_Msk                            (0x07UL << GPDMA_C6CONTROL_DBSIZE_Pos)                    /*!< GPDMA C6CONTROL: DBSIZE Mask        */
#define GPDMA_C6CONTROL_SWIDTH_Pos                            18                                                        /*!< GPDMA C6CONTROL: SWIDTH Position    */
#define GPDMA_C6CONTROL_SWIDTH_Msk                            (0x07UL << GPDMA_C6CONTROL_SWIDTH_Pos)                    /*!< GPDMA C6CONTROL: SWIDTH Mask        */
#define GPDMA_C6CONTROL_DWIDTH_Pos                            21                                                        /*!< GPDMA C6CONTROL: DWIDTH Position    */
#define GPDMA_C6CONTROL_DWIDTH_Msk                            (0x07UL << GPDMA_C6CONTROL_DWIDTH_Pos)                    /*!< GPDMA C6CONTROL: DWIDTH Mask        */
#define GPDMA_C6CONTROL_S_Pos                                 24                                                        /*!< GPDMA C6CONTROL: S Position         */
#define GPDMA_C6CONTROL_S_Msk                                 (0x01UL << GPDMA_C6CONTROL_S_Pos)                         /*!< GPDMA C6CONTROL: S Mask             */
#define GPDMA_C6CONTROL_D_Pos                                 25                                                        /*!< GPDMA C6CONTROL: D Position         */
#define GPDMA_C6CONTROL_D_Msk                                 (0x01UL << GPDMA_C6CONTROL_D_Pos)                         /*!< GPDMA C6CONTROL: D Mask             */
#define GPDMA_C6CONTROL_SI_Pos                                26                                                        /*!< GPDMA C6CONTROL: SI Position        */
#define GPDMA_C6CONTROL_SI_Msk                                (0x01UL << GPDMA_C6CONTROL_SI_Pos)                        /*!< GPDMA C6CONTROL: SI Mask            */
#define GPDMA_C6CONTROL_DI_Pos                                27                                                        /*!< GPDMA C6CONTROL: DI Position        */
#define GPDMA_C6CONTROL_DI_Msk                                (0x01UL << GPDMA_C6CONTROL_DI_Pos)                        /*!< GPDMA C6CONTROL: DI Mask            */
#define GPDMA_C6CONTROL_PROT1_Pos                             28                                                        /*!< GPDMA C6CONTROL: PROT1 Position     */
#define GPDMA_C6CONTROL_PROT1_Msk                             (0x01UL << GPDMA_C6CONTROL_PROT1_Pos)                     /*!< GPDMA C6CONTROL: PROT1 Mask         */
#define GPDMA_C6CONTROL_PROT2_Pos                             29                                                        /*!< GPDMA C6CONTROL: PROT2 Position     */
#define GPDMA_C6CONTROL_PROT2_Msk                             (0x01UL << GPDMA_C6CONTROL_PROT2_Pos)                     /*!< GPDMA C6CONTROL: PROT2 Mask         */
#define GPDMA_C6CONTROL_PROT3_Pos                             30                                                        /*!< GPDMA C6CONTROL: PROT3 Position     */
#define GPDMA_C6CONTROL_PROT3_Msk                             (0x01UL << GPDMA_C6CONTROL_PROT3_Pos)                     /*!< GPDMA C6CONTROL: PROT3 Mask         */
#define GPDMA_C6CONTROL_I_Pos                                 31                                                        /*!< GPDMA C6CONTROL: I Position         */
#define GPDMA_C6CONTROL_I_Msk                                 (0x01UL << GPDMA_C6CONTROL_I_Pos)                         /*!< GPDMA C6CONTROL: I Mask             */

// -------------------------------------  GPDMA_C6CONFIG  -----------------------------------------
#define GPDMA_C6CONFIG_E_Pos                                  0                                                         /*!< GPDMA C6CONFIG: E Position          */
#define GPDMA_C6CONFIG_E_Msk                                  (0x01UL << GPDMA_C6CONFIG_E_Pos)                          /*!< GPDMA C6CONFIG: E Mask              */
#define GPDMA_C6CONFIG_SRCPERIPHERAL_Pos                      1                                                         /*!< GPDMA C6CONFIG: SRCPERIPHERAL Position */
#define GPDMA_C6CONFIG_SRCPERIPHERAL_Msk                      (0x1fUL << GPDMA_C6CONFIG_SRCPERIPHERAL_Pos)              /*!< GPDMA C6CONFIG: SRCPERIPHERAL Mask  */
#define GPDMA_C6CONFIG_DESTPERIPHERAL_Pos                     6                                                         /*!< GPDMA C6CONFIG: DESTPERIPHERAL Position */
#define GPDMA_C6CONFIG_DESTPERIPHERAL_Msk                     (0x1fUL << GPDMA_C6CONFIG_DESTPERIPHERAL_Pos)             /*!< GPDMA C6CONFIG: DESTPERIPHERAL Mask */
#define GPDMA_C6CONFIG_FLOWCNTRL_Pos                          11                                                        /*!< GPDMA C6CONFIG: FLOWCNTRL Position  */
#define GPDMA_C6CONFIG_FLOWCNTRL_Msk                          (0x07UL << GPDMA_C6CONFIG_FLOWCNTRL_Pos)                  /*!< GPDMA C6CONFIG: FLOWCNTRL Mask      */
#define GPDMA_C6CONFIG_IE_Pos                                 14                                                        /*!< GPDMA C6CONFIG: IE Position         */
#define GPDMA_C6CONFIG_IE_Msk                                 (0x01UL << GPDMA_C6CONFIG_IE_Pos)                         /*!< GPDMA C6CONFIG: IE Mask             */
#define GPDMA_C6CONFIG_ITC_Pos                                15                                                        /*!< GPDMA C6CONFIG: ITC Position        */
#define GPDMA_C6CONFIG_ITC_Msk                                (0x01UL << GPDMA_C6CONFIG_ITC_Pos)                        /*!< GPDMA C6CONFIG: ITC Mask            */
#define GPDMA_C6CONFIG_L_Pos                                  16                                                        /*!< GPDMA C6CONFIG: L Position          */
#define GPDMA_C6CONFIG_L_Msk                                  (0x01UL << GPDMA_C6CONFIG_L_Pos)                          /*!< GPDMA C6CONFIG: L Mask              */
#define GPDMA_C6CONFIG_A_Pos                                  17                                                        /*!< GPDMA C6CONFIG: A Position          */
#define GPDMA_C6CONFIG_A_Msk                                  (0x01UL << GPDMA_C6CONFIG_A_Pos)                          /*!< GPDMA C6CONFIG: A Mask              */
#define GPDMA_C6CONFIG_H_Pos                                  18                                                        /*!< GPDMA C6CONFIG: H Position          */
#define GPDMA_C6CONFIG_H_Msk                                  (0x01UL << GPDMA_C6CONFIG_H_Pos)                          /*!< GPDMA C6CONFIG: H Mask              */

// -------------------------------------  GPDMA_C7SRCADDR  ----------------------------------------
#define GPDMA_C7SRCADDR_SRCADDR_Pos                           0                                                         /*!< GPDMA C7SRCADDR: SRCADDR Position   */
#define GPDMA_C7SRCADDR_SRCADDR_Msk                           (0xffffffffUL << GPDMA_C7SRCADDR_SRCADDR_Pos)             /*!< GPDMA C7SRCADDR: SRCADDR Mask       */

// ------------------------------------  GPDMA_C7DESTADDR  ----------------------------------------
#define GPDMA_C7DESTADDR_DESTADDR_Pos                         0                                                         /*!< GPDMA C7DESTADDR: DESTADDR Position */
#define GPDMA_C7DESTADDR_DESTADDR_Msk                         (0xffffffffUL << GPDMA_C7DESTADDR_DESTADDR_Pos)           /*!< GPDMA C7DESTADDR: DESTADDR Mask     */

// ---------------------------------------  GPDMA_C7LLI  ------------------------------------------
#define GPDMA_C7LLI_LM_Pos                                    0                                                         /*!< GPDMA C7LLI: LM Position            */
#define GPDMA_C7LLI_LM_Msk                                    (0x01UL << GPDMA_C7LLI_LM_Pos)                            /*!< GPDMA C7LLI: LM Mask                */
#define GPDMA_C7LLI_R_Pos                                     1                                                         /*!< GPDMA C7LLI: R Position             */
#define GPDMA_C7LLI_R_Msk                                     (0x01UL << GPDMA_C7LLI_R_Pos)                             /*!< GPDMA C7LLI: R Mask                 */
#define GPDMA_C7LLI_LLI_Pos                                   2                                                         /*!< GPDMA C7LLI: LLI Position           */
#define GPDMA_C7LLI_LLI_Msk                                   (0x3fffffffUL << GPDMA_C7LLI_LLI_Pos)                     /*!< GPDMA C7LLI: LLI Mask               */

// -------------------------------------  GPDMA_C7CONTROL  ----------------------------------------
#define GPDMA_C7CONTROL_TRANSFERSIZE_Pos                      0                                                         /*!< GPDMA C7CONTROL: TRANSFERSIZE Position */
#define GPDMA_C7CONTROL_TRANSFERSIZE_Msk                      (0x00000fffUL << GPDMA_C7CONTROL_TRANSFERSIZE_Pos)        /*!< GPDMA C7CONTROL: TRANSFERSIZE Mask  */
#define GPDMA_C7CONTROL_SBSIZE_Pos                            12                                                        /*!< GPDMA C7CONTROL: SBSIZE Position    */
#define GPDMA_C7CONTROL_SBSIZE_Msk                            (0x07UL << GPDMA_C7CONTROL_SBSIZE_Pos)                    /*!< GPDMA C7CONTROL: SBSIZE Mask        */
#define GPDMA_C7CONTROL_DBSIZE_Pos                            15                                                        /*!< GPDMA C7CONTROL: DBSIZE Position    */
#define GPDMA_C7CONTROL_DBSIZE_Msk                            (0x07UL << GPDMA_C7CONTROL_DBSIZE_Pos)                    /*!< GPDMA C7CONTROL: DBSIZE Mask        */
#define GPDMA_C7CONTROL_SWIDTH_Pos                            18                                                        /*!< GPDMA C7CONTROL: SWIDTH Position    */
#define GPDMA_C7CONTROL_SWIDTH_Msk                            (0x07UL << GPDMA_C7CONTROL_SWIDTH_Pos)                    /*!< GPDMA C7CONTROL: SWIDTH Mask        */
#define GPDMA_C7CONTROL_DWIDTH_Pos                            21                                                        /*!< GPDMA C7CONTROL: DWIDTH Position    */
#define GPDMA_C7CONTROL_DWIDTH_Msk                            (0x07UL << GPDMA_C7CONTROL_DWIDTH_Pos)                    /*!< GPDMA C7CONTROL: DWIDTH Mask        */
#define GPDMA_C7CONTROL_S_Pos                                 24                                                        /*!< GPDMA C7CONTROL: S Position         */
#define GPDMA_C7CONTROL_S_Msk                                 (0x01UL << GPDMA_C7CONTROL_S_Pos)                         /*!< GPDMA C7CONTROL: S Mask             */
#define GPDMA_C7CONTROL_D_Pos                                 25                                                        /*!< GPDMA C7CONTROL: D Position         */
#define GPDMA_C7CONTROL_D_Msk                                 (0x01UL << GPDMA_C7CONTROL_D_Pos)                         /*!< GPDMA C7CONTROL: D Mask             */
#define GPDMA_C7CONTROL_SI_Pos                                26                                                        /*!< GPDMA C7CONTROL: SI Position        */
#define GPDMA_C7CONTROL_SI_Msk                                (0x01UL << GPDMA_C7CONTROL_SI_Pos)                        /*!< GPDMA C7CONTROL: SI Mask            */
#define GPDMA_C7CONTROL_DI_Pos                                27                                                        /*!< GPDMA C7CONTROL: DI Position        */
#define GPDMA_C7CONTROL_DI_Msk                                (0x01UL << GPDMA_C7CONTROL_DI_Pos)                        /*!< GPDMA C7CONTROL: DI Mask            */
#define GPDMA_C7CONTROL_PROT1_Pos                             28                                                        /*!< GPDMA C7CONTROL: PROT1 Position     */
#define GPDMA_C7CONTROL_PROT1_Msk                             (0x01UL << GPDMA_C7CONTROL_PROT1_Pos)                     /*!< GPDMA C7CONTROL: PROT1 Mask         */
#define GPDMA_C7CONTROL_PROT2_Pos                             29                                                        /*!< GPDMA C7CONTROL: PROT2 Position     */
#define GPDMA_C7CONTROL_PROT2_Msk                             (0x01UL << GPDMA_C7CONTROL_PROT2_Pos)                     /*!< GPDMA C7CONTROL: PROT2 Mask         */
#define GPDMA_C7CONTROL_PROT3_Pos                             30                                                        /*!< GPDMA C7CONTROL: PROT3 Position     */
#define GPDMA_C7CONTROL_PROT3_Msk                             (0x01UL << GPDMA_C7CONTROL_PROT3_Pos)                     /*!< GPDMA C7CONTROL: PROT3 Mask         */
#define GPDMA_C7CONTROL_I_Pos                                 31                                                        /*!< GPDMA C7CONTROL: I Position         */
#define GPDMA_C7CONTROL_I_Msk                                 (0x01UL << GPDMA_C7CONTROL_I_Pos)                         /*!< GPDMA C7CONTROL: I Mask             */

// -------------------------------------  GPDMA_C7CONFIG  -----------------------------------------
#define GPDMA_C7CONFIG_E_Pos                                  0                                                         /*!< GPDMA C7CONFIG: E Position          */
#define GPDMA_C7CONFIG_E_Msk                                  (0x01UL << GPDMA_C7CONFIG_E_Pos)                          /*!< GPDMA C7CONFIG: E Mask              */
#define GPDMA_C7CONFIG_SRCPERIPHERAL_Pos                      1                                                         /*!< GPDMA C7CONFIG: SRCPERIPHERAL Position */
#define GPDMA_C7CONFIG_SRCPERIPHERAL_Msk                      (0x1fUL << GPDMA_C7CONFIG_SRCPERIPHERAL_Pos)              /*!< GPDMA C7CONFIG: SRCPERIPHERAL Mask  */
#define GPDMA_C7CONFIG_DESTPERIPHERAL_Pos                     6                                                         /*!< GPDMA C7CONFIG: DESTPERIPHERAL Position */
#define GPDMA_C7CONFIG_DESTPERIPHERAL_Msk                     (0x1fUL << GPDMA_C7CONFIG_DESTPERIPHERAL_Pos)             /*!< GPDMA C7CONFIG: DESTPERIPHERAL Mask */
#define GPDMA_C7CONFIG_FLOWCNTRL_Pos                          11                                                        /*!< GPDMA C7CONFIG: FLOWCNTRL Position  */
#define GPDMA_C7CONFIG_FLOWCNTRL_Msk                          (0x07UL << GPDMA_C7CONFIG_FLOWCNTRL_Pos)                  /*!< GPDMA C7CONFIG: FLOWCNTRL Mask      */
#define GPDMA_C7CONFIG_IE_Pos                                 14                                                        /*!< GPDMA C7CONFIG: IE Position         */
#define GPDMA_C7CONFIG_IE_Msk                                 (0x01UL << GPDMA_C7CONFIG_IE_Pos)                         /*!< GPDMA C7CONFIG: IE Mask             */
#define GPDMA_C7CONFIG_ITC_Pos                                15                                                        /*!< GPDMA C7CONFIG: ITC Position        */
#define GPDMA_C7CONFIG_ITC_Msk                                (0x01UL << GPDMA_C7CONFIG_ITC_Pos)                        /*!< GPDMA C7CONFIG: ITC Mask            */
#define GPDMA_C7CONFIG_L_Pos                                  16                                                        /*!< GPDMA C7CONFIG: L Position          */
#define GPDMA_C7CONFIG_L_Msk                                  (0x01UL << GPDMA_C7CONFIG_L_Pos)                          /*!< GPDMA C7CONFIG: L Mask              */
#define GPDMA_C7CONFIG_A_Pos                                  17                                                        /*!< GPDMA C7CONFIG: A Position          */
#define GPDMA_C7CONFIG_A_Msk                                  (0x01UL << GPDMA_C7CONFIG_A_Pos)                          /*!< GPDMA C7CONFIG: A Mask              */
#define GPDMA_C7CONFIG_H_Pos                                  18                                                        /*!< GPDMA C7CONFIG: H Position          */
#define GPDMA_C7CONFIG_H_Msk                                  (0x01UL << GPDMA_C7CONFIG_H_Pos)                          /*!< GPDMA C7CONFIG: H Mask              */


// ------------------------------------------------------------------------------------------------
// -----                                 SDMMC Position & Mask                                -----
// ------------------------------------------------------------------------------------------------


// ---------------------------------------  SDMMC_CTRL  -------------------------------------------
#define SDMMC_CTRL_CONTROLLER_RESET_Pos                       0                                                         /*!< SDMMC CTRL: CONTROLLER_RESET Position */
#define SDMMC_CTRL_CONTROLLER_RESET_Msk                       (0x01UL << SDMMC_CTRL_CONTROLLER_RESET_Pos)               /*!< SDMMC CTRL: CONTROLLER_RESET Mask   */
#define SDMMC_CTRL_FIFO_RESET_Pos                             1                                                         /*!< SDMMC CTRL: FIFO_RESET Position     */
#define SDMMC_CTRL_FIFO_RESET_Msk                             (0x01UL << SDMMC_CTRL_FIFO_RESET_Pos)                     /*!< SDMMC CTRL: FIFO_RESET Mask         */
#define SDMMC_CTRL_DMA_RESET_Pos                              2                                                         /*!< SDMMC CTRL: DMA_RESET Position      */
#define SDMMC_CTRL_DMA_RESET_Msk                              (0x01UL << SDMMC_CTRL_DMA_RESET_Pos)                      /*!< SDMMC CTRL: DMA_RESET Mask          */
#define SDMMC_CTRL_INT_ENABLE_Pos                             4                                                         /*!< SDMMC CTRL: INT_ENABLE Position     */
#define SDMMC_CTRL_INT_ENABLE_Msk                             (0x01UL << SDMMC_CTRL_INT_ENABLE_Pos)                     /*!< SDMMC CTRL: INT_ENABLE Mask         */
#define SDMMC_CTRL_DMA_ENABLE_Pos                             5                                                         /*!< SDMMC CTRL: DMA_ENABLE Position     */
#define SDMMC_CTRL_DMA_ENABLE_Msk                             (0x01UL << SDMMC_CTRL_DMA_ENABLE_Pos)                     /*!< SDMMC CTRL: DMA_ENABLE Mask         */
#define SDMMC_CTRL_READ_WAIT_Pos                              6                                                         /*!< SDMMC CTRL: READ_WAIT Position      */
#define SDMMC_CTRL_READ_WAIT_Msk                              (0x01UL << SDMMC_CTRL_READ_WAIT_Pos)                      /*!< SDMMC CTRL: READ_WAIT Mask          */
#define SDMMC_CTRL_SEND_IRQ_RESPONSE_Pos                      7                                                         /*!< SDMMC CTRL: SEND_IRQ_RESPONSE Position */
#define SDMMC_CTRL_SEND_IRQ_RESPONSE_Msk                      (0x01UL << SDMMC_CTRL_SEND_IRQ_RESPONSE_Pos)              /*!< SDMMC CTRL: SEND_IRQ_RESPONSE Mask  */
#define SDMMC_CTRL_ABORT_READ_DATA_Pos                        8                                                         /*!< SDMMC CTRL: ABORT_READ_DATA Position */
#define SDMMC_CTRL_ABORT_READ_DATA_Msk                        (0x01UL << SDMMC_CTRL_ABORT_READ_DATA_Pos)                /*!< SDMMC CTRL: ABORT_READ_DATA Mask    */
#define SDMMC_CTRL_SEND_CCSD_Pos                              9                                                         /*!< SDMMC CTRL: SEND_CCSD Position      */
#define SDMMC_CTRL_SEND_CCSD_Msk                              (0x01UL << SDMMC_CTRL_SEND_CCSD_Pos)                      /*!< SDMMC CTRL: SEND_CCSD Mask          */
#define SDMMC_CTRL_SEND_AUTO_STOP_CCSD_Pos                    10                                                        /*!< SDMMC CTRL: SEND_AUTO_STOP_CCSD Position */
#define SDMMC_CTRL_SEND_AUTO_STOP_CCSD_Msk                    (0x01UL << SDMMC_CTRL_SEND_AUTO_STOP_CCSD_Pos)            /*!< SDMMC CTRL: SEND_AUTO_STOP_CCSD Mask */
#define SDMMC_CTRL_CEATA_DEVICE_INTERRUPT_STATUS_Pos          11                                                        /*!< SDMMC CTRL: CEATA_DEVICE_INTERRUPT_STATUS Position */
#define SDMMC_CTRL_CEATA_DEVICE_INTERRUPT_STATUS_Msk          (0x01UL << SDMMC_CTRL_CEATA_DEVICE_INTERRUPT_STATUS_Pos)  /*!< SDMMC CTRL: CEATA_DEVICE_INTERRUPT_STATUS Mask */
#define SDMMC_CTRL_CARD_VOLTAGE_A_Pos                         16                                                        /*!< SDMMC CTRL: CARD_VOLTAGE_A Position */
#define SDMMC_CTRL_CARD_VOLTAGE_A_Msk                         (0x0fUL << SDMMC_CTRL_CARD_VOLTAGE_A_Pos)                 /*!< SDMMC CTRL: CARD_VOLTAGE_A Mask     */
#define SDMMC_CTRL_CARD_VOLTAGE_B_Pos                         20                                                        /*!< SDMMC CTRL: CARD_VOLTAGE_B Position */
#define SDMMC_CTRL_CARD_VOLTAGE_B_Msk                         (0x0fUL << SDMMC_CTRL_CARD_VOLTAGE_B_Pos)                 /*!< SDMMC CTRL: CARD_VOLTAGE_B Mask     */
#define SDMMC_CTRL_ENABLE_OD_PULLUP_Pos                       24                                                        /*!< SDMMC CTRL: ENABLE_OD_PULLUP Position */
#define SDMMC_CTRL_ENABLE_OD_PULLUP_Msk                       (0x01UL << SDMMC_CTRL_ENABLE_OD_PULLUP_Pos)               /*!< SDMMC CTRL: ENABLE_OD_PULLUP Mask   */
#define SDMMC_CTRL_USE_INTERNAL_DMAC_Pos                      25                                                        /*!< SDMMC CTRL: USE_INTERNAL_DMAC Position */
#define SDMMC_CTRL_USE_INTERNAL_DMAC_Msk                      (0x01UL << SDMMC_CTRL_USE_INTERNAL_DMAC_Pos)              /*!< SDMMC CTRL: USE_INTERNAL_DMAC Mask  */

// ---------------------------------------  SDMMC_PWREN  ------------------------------------------
#define SDMMC_PWREN_POWER_ENABLE_Pos                          0                                                         /*!< SDMMC PWREN: POWER_ENABLE Position  */
#define SDMMC_PWREN_POWER_ENABLE_Msk                          (0x3fffffffUL << SDMMC_PWREN_POWER_ENABLE_Pos)            /*!< SDMMC PWREN: POWER_ENABLE Mask      */

// --------------------------------------  SDMMC_CLKDIV  ------------------------------------------
#define SDMMC_CLKDIV_CLK_DIVIDER0_Pos                         0                                                         /*!< SDMMC CLKDIV: CLK_DIVIDER0 Position */
#define SDMMC_CLKDIV_CLK_DIVIDER0_Msk                         (0x000000ffUL << SDMMC_CLKDIV_CLK_DIVIDER0_Pos)           /*!< SDMMC CLKDIV: CLK_DIVIDER0 Mask     */
#define SDMMC_CLKDIV_CLK_DIVIDER1_Pos                         8                                                         /*!< SDMMC CLKDIV: CLK_DIVIDER1 Position */
#define SDMMC_CLKDIV_CLK_DIVIDER1_Msk                         (0x000000ffUL << SDMMC_CLKDIV_CLK_DIVIDER1_Pos)           /*!< SDMMC CLKDIV: CLK_DIVIDER1 Mask     */
#define SDMMC_CLKDIV_CLK_DIVIDER2_Pos                         16                                                        /*!< SDMMC CLKDIV: CLK_DIVIDER2 Position */
#define SDMMC_CLKDIV_CLK_DIVIDER2_Msk                         (0x000000ffUL << SDMMC_CLKDIV_CLK_DIVIDER2_Pos)           /*!< SDMMC CLKDIV: CLK_DIVIDER2 Mask     */
#define SDMMC_CLKDIV_CLK_DIVIDER3_Pos                         24                                                        /*!< SDMMC CLKDIV: CLK_DIVIDER3 Position */
#define SDMMC_CLKDIV_CLK_DIVIDER3_Msk                         (0x000000ffUL << SDMMC_CLKDIV_CLK_DIVIDER3_Pos)           /*!< SDMMC CLKDIV: CLK_DIVIDER3 Mask     */

// --------------------------------------  SDMMC_CLKSRC  ------------------------------------------
#define SDMMC_CLKSRC_CLK_SOURCE_Pos                           0                                                         /*!< SDMMC CLKSRC: CLK_SOURCE Position   */
#define SDMMC_CLKSRC_CLK_SOURCE_Msk                           (0xffffffffUL << SDMMC_CLKSRC_CLK_SOURCE_Pos)             /*!< SDMMC CLKSRC: CLK_SOURCE Mask       */

// --------------------------------------  SDMMC_CLKENA  ------------------------------------------
#define SDMMC_CLKENA_CCLK_ENABLE_Pos                          0                                                         /*!< SDMMC CLKENA: CCLK_ENABLE Position  */
#define SDMMC_CLKENA_CCLK_ENABLE_Msk                          (0x0000ffffUL << SDMMC_CLKENA_CCLK_ENABLE_Pos)            /*!< SDMMC CLKENA: CCLK_ENABLE Mask      */
#define SDMMC_CLKENA_CCLK_LOW_POWER_Pos                       16                                                        /*!< SDMMC CLKENA: CCLK_LOW_POWER Position */
#define SDMMC_CLKENA_CCLK_LOW_POWER_Msk                       (0x0000ffffUL << SDMMC_CLKENA_CCLK_LOW_POWER_Pos)         /*!< SDMMC CLKENA: CCLK_LOW_POWER Mask   */

// ---------------------------------------  SDMMC_TMOUT  ------------------------------------------
#define SDMMC_TMOUT_RESPONSE_TIMEOUT_Pos                      0                                                         /*!< SDMMC TMOUT: RESPONSE_TIMEOUT Position */
#define SDMMC_TMOUT_RESPONSE_TIMEOUT_Msk                      (0x000000ffUL << SDMMC_TMOUT_RESPONSE_TIMEOUT_Pos)        /*!< SDMMC TMOUT: RESPONSE_TIMEOUT Mask  */
#define SDMMC_TMOUT_DATA_TIMEOUT_Pos                          8                                                         /*!< SDMMC TMOUT: DATA_TIMEOUT Position  */
#define SDMMC_TMOUT_DATA_TIMEOUT_Msk                          (0x00ffffffUL << SDMMC_TMOUT_DATA_TIMEOUT_Pos)            /*!< SDMMC TMOUT: DATA_TIMEOUT Mask      */

// ---------------------------------------  SDMMC_CTYPE  ------------------------------------------
#define SDMMC_CTYPE_CARD_WIDTH0_Pos                           0                                                         /*!< SDMMC CTYPE: CARD_WIDTH0 Position   */
#define SDMMC_CTYPE_CARD_WIDTH0_Msk                           (0x0000ffffUL << SDMMC_CTYPE_CARD_WIDTH0_Pos)             /*!< SDMMC CTYPE: CARD_WIDTH0 Mask       */
#define SDMMC_CTYPE_CARD_WIDTH1_Pos                           16                                                        /*!< SDMMC CTYPE: CARD_WIDTH1 Position   */
#define SDMMC_CTYPE_CARD_WIDTH1_Msk                           (0x0000ffffUL << SDMMC_CTYPE_CARD_WIDTH1_Pos)             /*!< SDMMC CTYPE: CARD_WIDTH1 Mask       */

// --------------------------------------  SDMMC_BLKSIZ  ------------------------------------------
#define SDMMC_BLKSIZ_BLOCK_SIZE_Pos                           0                                                         /*!< SDMMC BLKSIZ: BLOCK_SIZE Position   */
#define SDMMC_BLKSIZ_BLOCK_SIZE_Msk                           (0x0000ffffUL << SDMMC_BLKSIZ_BLOCK_SIZE_Pos)             /*!< SDMMC BLKSIZ: BLOCK_SIZE Mask       */

// --------------------------------------  SDMMC_BYTCNT  ------------------------------------------
#define SDMMC_BYTCNT_BYTE_COUNT_Pos                           0                                                         /*!< SDMMC BYTCNT: BYTE_COUNT Position   */
#define SDMMC_BYTCNT_BYTE_COUNT_Msk                           (0xffffffffUL << SDMMC_BYTCNT_BYTE_COUNT_Pos)             /*!< SDMMC BYTCNT: BYTE_COUNT Mask       */

// --------------------------------------  SDMMC_INTMASK  -----------------------------------------
#define SDMMC_INTMASK_CDET_Pos                                0                                                         /*!< SDMMC INTMASK: CDET Position        */
#define SDMMC_INTMASK_CDET_Msk                                (0x01UL << SDMMC_INTMASK_CDET_Pos)                        /*!< SDMMC INTMASK: CDET Mask            */
#define SDMMC_INTMASK_RE_Pos                                  1                                                         /*!< SDMMC INTMASK: RE Position          */
#define SDMMC_INTMASK_RE_Msk                                  (0x01UL << SDMMC_INTMASK_RE_Pos)                          /*!< SDMMC INTMASK: RE Mask              */
#define SDMMC_INTMASK_CDONE_Pos                               2                                                         /*!< SDMMC INTMASK: CDONE Position       */
#define SDMMC_INTMASK_CDONE_Msk                               (0x01UL << SDMMC_INTMASK_CDONE_Pos)                       /*!< SDMMC INTMASK: CDONE Mask           */
#define SDMMC_INTMASK_DTO_Pos                                 3                                                         /*!< SDMMC INTMASK: DTO Position         */
#define SDMMC_INTMASK_DTO_Msk                                 (0x01UL << SDMMC_INTMASK_DTO_Pos)                         /*!< SDMMC INTMASK: DTO Mask             */
#define SDMMC_INTMASK_TXDR_Pos                                4                                                         /*!< SDMMC INTMASK: TXDR Position        */
#define SDMMC_INTMASK_TXDR_Msk                                (0x01UL << SDMMC_INTMASK_TXDR_Pos)                        /*!< SDMMC INTMASK: TXDR Mask            */
#define SDMMC_INTMASK_RXDR_Pos                                5                                                         /*!< SDMMC INTMASK: RXDR Position        */
#define SDMMC_INTMASK_RXDR_Msk                                (0x01UL << SDMMC_INTMASK_RXDR_Pos)                        /*!< SDMMC INTMASK: RXDR Mask            */
#define SDMMC_INTMASK_RCRC_Pos                                6                                                         /*!< SDMMC INTMASK: RCRC Position        */
#define SDMMC_INTMASK_RCRC_Msk                                (0x01UL << SDMMC_INTMASK_RCRC_Pos)                        /*!< SDMMC INTMASK: RCRC Mask            */
#define SDMMC_INTMASK_DCRC_Pos                                7                                                         /*!< SDMMC INTMASK: DCRC Position        */
#define SDMMC_INTMASK_DCRC_Msk                                (0x01UL << SDMMC_INTMASK_DCRC_Pos)                        /*!< SDMMC INTMASK: DCRC Mask            */
#define SDMMC_INTMASK_RTO_Pos                                 8                                                         /*!< SDMMC INTMASK: RTO Position         */
#define SDMMC_INTMASK_RTO_Msk                                 (0x01UL << SDMMC_INTMASK_RTO_Pos)                         /*!< SDMMC INTMASK: RTO Mask             */
#define SDMMC_INTMASK_DRTO_Pos                                9                                                         /*!< SDMMC INTMASK: DRTO Position        */
#define SDMMC_INTMASK_DRTO_Msk                                (0x01UL << SDMMC_INTMASK_DRTO_Pos)                        /*!< SDMMC INTMASK: DRTO Mask            */
#define SDMMC_INTMASK_HTO_Pos                                 10                                                        /*!< SDMMC INTMASK: HTO Position         */
#define SDMMC_INTMASK_HTO_Msk                                 (0x01UL << SDMMC_INTMASK_HTO_Pos)                         /*!< SDMMC INTMASK: HTO Mask             */
#define SDMMC_INTMASK_FRUN_Pos                                11                                                        /*!< SDMMC INTMASK: FRUN Position        */
#define SDMMC_INTMASK_FRUN_Msk                                (0x01UL << SDMMC_INTMASK_FRUN_Pos)                        /*!< SDMMC INTMASK: FRUN Mask            */
#define SDMMC_INTMASK_HLE_Pos                                 12                                                        /*!< SDMMC INTMASK: HLE Position         */
#define SDMMC_INTMASK_HLE_Msk                                 (0x01UL << SDMMC_INTMASK_HLE_Pos)                         /*!< SDMMC INTMASK: HLE Mask             */
#define SDMMC_INTMASK_SBE_Pos                                 13                                                        /*!< SDMMC INTMASK: SBE Position         */
#define SDMMC_INTMASK_SBE_Msk                                 (0x01UL << SDMMC_INTMASK_SBE_Pos)                         /*!< SDMMC INTMASK: SBE Mask             */
#define SDMMC_INTMASK_ACD_Pos                                 14                                                        /*!< SDMMC INTMASK: ACD Position         */
#define SDMMC_INTMASK_ACD_Msk                                 (0x01UL << SDMMC_INTMASK_ACD_Pos)                         /*!< SDMMC INTMASK: ACD Mask             */
#define SDMMC_INTMASK_EBE_Pos                                 15                                                        /*!< SDMMC INTMASK: EBE Position         */
#define SDMMC_INTMASK_EBE_Msk                                 (0x01UL << SDMMC_INTMASK_EBE_Pos)                         /*!< SDMMC INTMASK: EBE Mask             */
#define SDMMC_INTMASK_SDIO_INT_MASK_Pos                       16                                                        /*!< SDMMC INTMASK: SDIO_INT_MASK Position */
#define SDMMC_INTMASK_SDIO_INT_MASK_Msk                       (0x0000ffffUL << SDMMC_INTMASK_SDIO_INT_MASK_Pos)         /*!< SDMMC INTMASK: SDIO_INT_MASK Mask   */

// --------------------------------------  SDMMC_CMDARG  ------------------------------------------
#define SDMMC_CMDARG_CMD_ARG_Pos                              0                                                         /*!< SDMMC CMDARG: CMD_ARG Position      */
#define SDMMC_CMDARG_CMD_ARG_Msk                              (0xffffffffUL << SDMMC_CMDARG_CMD_ARG_Pos)                /*!< SDMMC CMDARG: CMD_ARG Mask          */

// ----------------------------------------  SDMMC_CMD  -------------------------------------------
#define SDMMC_CMD_CMD_INDEX_Pos                               0                                                         /*!< SDMMC CMD: CMD_INDEX Position       */
#define SDMMC_CMD_CMD_INDEX_Msk                               (0x3fUL << SDMMC_CMD_CMD_INDEX_Pos)                       /*!< SDMMC CMD: CMD_INDEX Mask           */
#define SDMMC_CMD_RESPONSE_EXPECT_Pos                         6                                                         /*!< SDMMC CMD: RESPONSE_EXPECT Position */
#define SDMMC_CMD_RESPONSE_EXPECT_Msk                         (0x01UL << SDMMC_CMD_RESPONSE_EXPECT_Pos)                 /*!< SDMMC CMD: RESPONSE_EXPECT Mask     */
#define SDMMC_CMD_RESPONSE_LENGTH_Pos                         7                                                         /*!< SDMMC CMD: RESPONSE_LENGTH Position */
#define SDMMC_CMD_RESPONSE_LENGTH_Msk                         (0x01UL << SDMMC_CMD_RESPONSE_LENGTH_Pos)                 /*!< SDMMC CMD: RESPONSE_LENGTH Mask     */
#define SDMMC_CMD_CHECK_RESPONSE_CRC_Pos                      8                                                         /*!< SDMMC CMD: CHECK_RESPONSE_CRC Position */
#define SDMMC_CMD_CHECK_RESPONSE_CRC_Msk                      (0x01UL << SDMMC_CMD_CHECK_RESPONSE_CRC_Pos)              /*!< SDMMC CMD: CHECK_RESPONSE_CRC Mask  */
#define SDMMC_CMD_DATA_EXPECTED_Pos                           9                                                         /*!< SDMMC CMD: DATA_EXPECTED Position   */
#define SDMMC_CMD_DATA_EXPECTED_Msk                           (0x01UL << SDMMC_CMD_DATA_EXPECTED_Pos)                   /*!< SDMMC CMD: DATA_EXPECTED Mask       */
#define SDMMC_CMD_READ_WRITE_Pos                              10                                                        /*!< SDMMC CMD: READ_WRITE Position      */
#define SDMMC_CMD_READ_WRITE_Msk                              (0x01UL << SDMMC_CMD_READ_WRITE_Pos)                      /*!< SDMMC CMD: READ_WRITE Mask          */
#define SDMMC_CMD_TRANSFER_MODE_Pos                           11                                                        /*!< SDMMC CMD: TRANSFER_MODE Position   */
#define SDMMC_CMD_TRANSFER_MODE_Msk                           (0x01UL << SDMMC_CMD_TRANSFER_MODE_Pos)                   /*!< SDMMC CMD: TRANSFER_MODE Mask       */
#define SDMMC_CMD_SEND_AUTO_STOP_Pos                          12                                                        /*!< SDMMC CMD: SEND_AUTO_STOP Position  */
#define SDMMC_CMD_SEND_AUTO_STOP_Msk                          (0x01UL << SDMMC_CMD_SEND_AUTO_STOP_Pos)                  /*!< SDMMC CMD: SEND_AUTO_STOP Mask      */
#define SDMMC_CMD_WAIT_PRVDATA_COMPLETE_Pos                   13                                                        /*!< SDMMC CMD: WAIT_PRVDATA_COMPLETE Position */
#define SDMMC_CMD_WAIT_PRVDATA_COMPLETE_Msk                   (0x01UL << SDMMC_CMD_WAIT_PRVDATA_COMPLETE_Pos)           /*!< SDMMC CMD: WAIT_PRVDATA_COMPLETE Mask */
#define SDMMC_CMD_STOP_ABORT_CMd_Pos                          14                                                        /*!< SDMMC CMD: STOP_ABORT_CMd Position  */
#define SDMMC_CMD_STOP_ABORT_CMd_Msk                          (0x01UL << SDMMC_CMD_STOP_ABORT_CMd_Pos)                  /*!< SDMMC CMD: STOP_ABORT_CMd Mask      */
#define SDMMC_CMD_SEND_INITIALIZATION_Pos                     15                                                        /*!< SDMMC CMD: SEND_INITIALIZATION Position */
#define SDMMC_CMD_SEND_INITIALIZATION_Msk                     (0x01UL << SDMMC_CMD_SEND_INITIALIZATION_Pos)             /*!< SDMMC CMD: SEND_INITIALIZATION Mask */
#define SDMMC_CMD_CARD_NUMBER_Pos                             16                                                        /*!< SDMMC CMD: CARD_NUMBER Position     */
#define SDMMC_CMD_CARD_NUMBER_Msk                             (0x1fUL << SDMMC_CMD_CARD_NUMBER_Pos)                     /*!< SDMMC CMD: CARD_NUMBER Mask         */
#define SDMMC_CMD_UPDATE_CLOCK_REGISTERS_ONLY_Pos             21                                                        /*!< SDMMC CMD: UPDATE_CLOCK_REGISTERS_ONLY Position */
#define SDMMC_CMD_UPDATE_CLOCK_REGISTERS_ONLY_Msk             (0x01UL << SDMMC_CMD_UPDATE_CLOCK_REGISTERS_ONLY_Pos)     /*!< SDMMC CMD: UPDATE_CLOCK_REGISTERS_ONLY Mask */
#define SDMMC_CMD_READ_CEATA_DEVICE_Pos                       22                                                        /*!< SDMMC CMD: READ_CEATA_DEVICE Position */
#define SDMMC_CMD_READ_CEATA_DEVICE_Msk                       (0x01UL << SDMMC_CMD_READ_CEATA_DEVICE_Pos)               /*!< SDMMC CMD: READ_CEATA_DEVICE Mask   */
#define SDMMC_CMD_CCS_EXPECTED_Pos                            23                                                        /*!< SDMMC CMD: CCS_EXPECTED Position    */
#define SDMMC_CMD_CCS_EXPECTED_Msk                            (0x01UL << SDMMC_CMD_CCS_EXPECTED_Pos)                    /*!< SDMMC CMD: CCS_EXPECTED Mask        */
#define SDMMC_CMD_ENABLE_BOOT_Pos                             24                                                        /*!< SDMMC CMD: ENABLE_BOOT Position     */
#define SDMMC_CMD_ENABLE_BOOT_Msk                             (0x01UL << SDMMC_CMD_ENABLE_BOOT_Pos)                     /*!< SDMMC CMD: ENABLE_BOOT Mask         */
#define SDMMC_CMD_EXPECT_BOOT_ACK_Pos                         25                                                        /*!< SDMMC CMD: EXPECT_BOOT_ACK Position */
#define SDMMC_CMD_EXPECT_BOOT_ACK_Msk                         (0x01UL << SDMMC_CMD_EXPECT_BOOT_ACK_Pos)                 /*!< SDMMC CMD: EXPECT_BOOT_ACK Mask     */
#define SDMMC_CMD_DISABLE_BOOT_Pos                            26                                                        /*!< SDMMC CMD: DISABLE_BOOT Position    */
#define SDMMC_CMD_DISABLE_BOOT_Msk                            (0x01UL << SDMMC_CMD_DISABLE_BOOT_Pos)                    /*!< SDMMC CMD: DISABLE_BOOT Mask        */
#define SDMMC_CMD_BOOT_MODE_Pos                               27                                                        /*!< SDMMC CMD: BOOT_MODE Position       */
#define SDMMC_CMD_BOOT_MODE_Msk                               (0x01UL << SDMMC_CMD_BOOT_MODE_Pos)                       /*!< SDMMC CMD: BOOT_MODE Mask           */
#define SDMMC_CMD_VOLT_SWITCH_Pos                             28                                                        /*!< SDMMC CMD: VOLT_SWITCH Position     */
#define SDMMC_CMD_VOLT_SWITCH_Msk                             (0x01UL << SDMMC_CMD_VOLT_SWITCH_Pos)                     /*!< SDMMC CMD: VOLT_SWITCH Mask         */
#define SDMMC_CMD_START_CMD_Pos                               31                                                        /*!< SDMMC CMD: START_CMD Position       */
#define SDMMC_CMD_START_CMD_Msk                               (0x01UL << SDMMC_CMD_START_CMD_Pos)                       /*!< SDMMC CMD: START_CMD Mask           */

// ---------------------------------------  SDMMC_RESP0  ------------------------------------------
#define SDMMC_RESP0_RESPONSE0_Pos                             0                                                         /*!< SDMMC RESP0: RESPONSE0 Position     */
#define SDMMC_RESP0_RESPONSE0_Msk                             (0xffffffffUL << SDMMC_RESP0_RESPONSE0_Pos)               /*!< SDMMC RESP0: RESPONSE0 Mask         */

// ---------------------------------------  SDMMC_RESP1  ------------------------------------------
#define SDMMC_RESP1_RESPONSE1_Pos                             0                                                         /*!< SDMMC RESP1: RESPONSE1 Position     */
#define SDMMC_RESP1_RESPONSE1_Msk                             (0xffffffffUL << SDMMC_RESP1_RESPONSE1_Pos)               /*!< SDMMC RESP1: RESPONSE1 Mask         */

// ---------------------------------------  SDMMC_RESP2  ------------------------------------------
#define SDMMC_RESP2_RESPONSE2_Pos                             0                                                         /*!< SDMMC RESP2: RESPONSE2 Position     */
#define SDMMC_RESP2_RESPONSE2_Msk                             (0xffffffffUL << SDMMC_RESP2_RESPONSE2_Pos)               /*!< SDMMC RESP2: RESPONSE2 Mask         */

// ---------------------------------------  SDMMC_RESP3  ------------------------------------------
#define SDMMC_RESP3_RESPONSE3_Pos                             0                                                         /*!< SDMMC RESP3: RESPONSE3 Position     */
#define SDMMC_RESP3_RESPONSE3_Msk                             (0xffffffffUL << SDMMC_RESP3_RESPONSE3_Pos)               /*!< SDMMC RESP3: RESPONSE3 Mask         */

// --------------------------------------  SDMMC_MINTSTS  -----------------------------------------
#define SDMMC_MINTSTS_CDET_Pos                                0                                                         /*!< SDMMC MINTSTS: CDET Position        */
#define SDMMC_MINTSTS_CDET_Msk                                (0x01UL << SDMMC_MINTSTS_CDET_Pos)                        /*!< SDMMC MINTSTS: CDET Mask            */
#define SDMMC_MINTSTS_RE_Pos                                  1                                                         /*!< SDMMC MINTSTS: RE Position          */
#define SDMMC_MINTSTS_RE_Msk                                  (0x01UL << SDMMC_MINTSTS_RE_Pos)                          /*!< SDMMC MINTSTS: RE Mask              */
#define SDMMC_MINTSTS_CDONE_Pos                               2                                                         /*!< SDMMC MINTSTS: CDONE Position       */
#define SDMMC_MINTSTS_CDONE_Msk                               (0x01UL << SDMMC_MINTSTS_CDONE_Pos)                       /*!< SDMMC MINTSTS: CDONE Mask           */
#define SDMMC_MINTSTS_DTO_Pos                                 3                                                         /*!< SDMMC MINTSTS: DTO Position         */
#define SDMMC_MINTSTS_DTO_Msk                                 (0x01UL << SDMMC_MINTSTS_DTO_Pos)                         /*!< SDMMC MINTSTS: DTO Mask             */
#define SDMMC_MINTSTS_TXDR_Pos                                4                                                         /*!< SDMMC MINTSTS: TXDR Position        */
#define SDMMC_MINTSTS_TXDR_Msk                                (0x01UL << SDMMC_MINTSTS_TXDR_Pos)                        /*!< SDMMC MINTSTS: TXDR Mask            */
#define SDMMC_MINTSTS_RXDR_Pos                                5                                                         /*!< SDMMC MINTSTS: RXDR Position        */
#define SDMMC_MINTSTS_RXDR_Msk                                (0x01UL << SDMMC_MINTSTS_RXDR_Pos)                        /*!< SDMMC MINTSTS: RXDR Mask            */
#define SDMMC_MINTSTS_RCRC_Pos                                6                                                         /*!< SDMMC MINTSTS: RCRC Position        */
#define SDMMC_MINTSTS_RCRC_Msk                                (0x01UL << SDMMC_MINTSTS_RCRC_Pos)                        /*!< SDMMC MINTSTS: RCRC Mask            */
#define SDMMC_MINTSTS_DCRC_Pos                                7                                                         /*!< SDMMC MINTSTS: DCRC Position        */
#define SDMMC_MINTSTS_DCRC_Msk                                (0x01UL << SDMMC_MINTSTS_DCRC_Pos)                        /*!< SDMMC MINTSTS: DCRC Mask            */
#define SDMMC_MINTSTS_RTO_Pos                                 8                                                         /*!< SDMMC MINTSTS: RTO Position         */
#define SDMMC_MINTSTS_RTO_Msk                                 (0x01UL << SDMMC_MINTSTS_RTO_Pos)                         /*!< SDMMC MINTSTS: RTO Mask             */
#define SDMMC_MINTSTS_DRTO_Pos                                9                                                         /*!< SDMMC MINTSTS: DRTO Position        */
#define SDMMC_MINTSTS_DRTO_Msk                                (0x01UL << SDMMC_MINTSTS_DRTO_Pos)                        /*!< SDMMC MINTSTS: DRTO Mask            */
#define SDMMC_MINTSTS_HTO_Pos                                 10                                                        /*!< SDMMC MINTSTS: HTO Position         */
#define SDMMC_MINTSTS_HTO_Msk                                 (0x01UL << SDMMC_MINTSTS_HTO_Pos)                         /*!< SDMMC MINTSTS: HTO Mask             */
#define SDMMC_MINTSTS_FRUN_Pos                                11                                                        /*!< SDMMC MINTSTS: FRUN Position        */
#define SDMMC_MINTSTS_FRUN_Msk                                (0x01UL << SDMMC_MINTSTS_FRUN_Pos)                        /*!< SDMMC MINTSTS: FRUN Mask            */
#define SDMMC_MINTSTS_HLE_Pos                                 12                                                        /*!< SDMMC MINTSTS: HLE Position         */
#define SDMMC_MINTSTS_HLE_Msk                                 (0x01UL << SDMMC_MINTSTS_HLE_Pos)                         /*!< SDMMC MINTSTS: HLE Mask             */
#define SDMMC_MINTSTS_SBE_Pos                                 13                                                        /*!< SDMMC MINTSTS: SBE Position         */
#define SDMMC_MINTSTS_SBE_Msk                                 (0x01UL << SDMMC_MINTSTS_SBE_Pos)                         /*!< SDMMC MINTSTS: SBE Mask             */
#define SDMMC_MINTSTS_ACD_Pos                                 14                                                        /*!< SDMMC MINTSTS: ACD Position         */
#define SDMMC_MINTSTS_ACD_Msk                                 (0x01UL << SDMMC_MINTSTS_ACD_Pos)                         /*!< SDMMC MINTSTS: ACD Mask             */
#define SDMMC_MINTSTS_EBE_Pos                                 15                                                        /*!< SDMMC MINTSTS: EBE Position         */
#define SDMMC_MINTSTS_EBE_Msk                                 (0x01UL << SDMMC_MINTSTS_EBE_Pos)                         /*!< SDMMC MINTSTS: EBE Mask             */
#define SDMMC_MINTSTS_SDIO_INTERRUPT_Pos                      16                                                        /*!< SDMMC MINTSTS: SDIO_INTERRUPT Position */
#define SDMMC_MINTSTS_SDIO_INTERRUPT_Msk                      (0x0000ffffUL << SDMMC_MINTSTS_SDIO_INTERRUPT_Pos)        /*!< SDMMC MINTSTS: SDIO_INTERRUPT Mask  */

// --------------------------------------  SDMMC_RINTSTS  -----------------------------------------
#define SDMMC_RINTSTS_CDET_Pos                                0                                                         /*!< SDMMC RINTSTS: CDET Position        */
#define SDMMC_RINTSTS_CDET_Msk                                (0x01UL << SDMMC_RINTSTS_CDET_Pos)                        /*!< SDMMC RINTSTS: CDET Mask            */
#define SDMMC_RINTSTS_RE_Pos                                  1                                                         /*!< SDMMC RINTSTS: RE Position          */
#define SDMMC_RINTSTS_RE_Msk                                  (0x01UL << SDMMC_RINTSTS_RE_Pos)                          /*!< SDMMC RINTSTS: RE Mask              */
#define SDMMC_RINTSTS_CDONE_Pos                               2                                                         /*!< SDMMC RINTSTS: CDONE Position       */
#define SDMMC_RINTSTS_CDONE_Msk                               (0x01UL << SDMMC_RINTSTS_CDONE_Pos)                       /*!< SDMMC RINTSTS: CDONE Mask           */
#define SDMMC_RINTSTS_DTO_Pos                                 3                                                         /*!< SDMMC RINTSTS: DTO Position         */
#define SDMMC_RINTSTS_DTO_Msk                                 (0x01UL << SDMMC_RINTSTS_DTO_Pos)                         /*!< SDMMC RINTSTS: DTO Mask             */
#define SDMMC_RINTSTS_TXDR_Pos                                4                                                         /*!< SDMMC RINTSTS: TXDR Position        */
#define SDMMC_RINTSTS_TXDR_Msk                                (0x01UL << SDMMC_RINTSTS_TXDR_Pos)                        /*!< SDMMC RINTSTS: TXDR Mask            */
#define SDMMC_RINTSTS_RXDR_Pos                                5                                                         /*!< SDMMC RINTSTS: RXDR Position        */
#define SDMMC_RINTSTS_RXDR_Msk                                (0x01UL << SDMMC_RINTSTS_RXDR_Pos)                        /*!< SDMMC RINTSTS: RXDR Mask            */
#define SDMMC_RINTSTS_RCRC_Pos                                6                                                         /*!< SDMMC RINTSTS: RCRC Position        */
#define SDMMC_RINTSTS_RCRC_Msk                                (0x01UL << SDMMC_RINTSTS_RCRC_Pos)                        /*!< SDMMC RINTSTS: RCRC Mask            */
#define SDMMC_RINTSTS_DCRC_Pos                                7                                                         /*!< SDMMC RINTSTS: DCRC Position        */
#define SDMMC_RINTSTS_DCRC_Msk                                (0x01UL << SDMMC_RINTSTS_DCRC_Pos)                        /*!< SDMMC RINTSTS: DCRC Mask            */
#define SDMMC_RINTSTS_RTO_BAR_Pos                             8                                                         /*!< SDMMC RINTSTS: RTO_BAR Position     */
#define SDMMC_RINTSTS_RTO_BAR_Msk                             (0x01UL << SDMMC_RINTSTS_RTO_BAR_Pos)                     /*!< SDMMC RINTSTS: RTO_BAR Mask         */
#define SDMMC_RINTSTS_DRTO_BDS_Pos                            9                                                         /*!< SDMMC RINTSTS: DRTO_BDS Position    */
#define SDMMC_RINTSTS_DRTO_BDS_Msk                            (0x01UL << SDMMC_RINTSTS_DRTO_BDS_Pos)                    /*!< SDMMC RINTSTS: DRTO_BDS Mask        */
#define SDMMC_RINTSTS_HTO_Pos                                 10                                                        /*!< SDMMC RINTSTS: HTO Position         */
#define SDMMC_RINTSTS_HTO_Msk                                 (0x01UL << SDMMC_RINTSTS_HTO_Pos)                         /*!< SDMMC RINTSTS: HTO Mask             */
#define SDMMC_RINTSTS_FRUN_Pos                                11                                                        /*!< SDMMC RINTSTS: FRUN Position        */
#define SDMMC_RINTSTS_FRUN_Msk                                (0x01UL << SDMMC_RINTSTS_FRUN_Pos)                        /*!< SDMMC RINTSTS: FRUN Mask            */
#define SDMMC_RINTSTS_HLE_Pos                                 12                                                        /*!< SDMMC RINTSTS: HLE Position         */
#define SDMMC_RINTSTS_HLE_Msk                                 (0x01UL << SDMMC_RINTSTS_HLE_Pos)                         /*!< SDMMC RINTSTS: HLE Mask             */
#define SDMMC_RINTSTS_SBE_Pos                                 13                                                        /*!< SDMMC RINTSTS: SBE Position         */
#define SDMMC_RINTSTS_SBE_Msk                                 (0x01UL << SDMMC_RINTSTS_SBE_Pos)                         /*!< SDMMC RINTSTS: SBE Mask             */
#define SDMMC_RINTSTS_ACD_Pos                                 14                                                        /*!< SDMMC RINTSTS: ACD Position         */
#define SDMMC_RINTSTS_ACD_Msk                                 (0x01UL << SDMMC_RINTSTS_ACD_Pos)                         /*!< SDMMC RINTSTS: ACD Mask             */
#define SDMMC_RINTSTS_EBE_Pos                                 15                                                        /*!< SDMMC RINTSTS: EBE Position         */
#define SDMMC_RINTSTS_EBE_Msk                                 (0x01UL << SDMMC_RINTSTS_EBE_Pos)                         /*!< SDMMC RINTSTS: EBE Mask             */
#define SDMMC_RINTSTS_SDIO_INTERRUPT_Pos                      16                                                        /*!< SDMMC RINTSTS: SDIO_INTERRUPT Position */
#define SDMMC_RINTSTS_SDIO_INTERRUPT_Msk                      (0x0000ffffUL << SDMMC_RINTSTS_SDIO_INTERRUPT_Pos)        /*!< SDMMC RINTSTS: SDIO_INTERRUPT Mask  */

// --------------------------------------  SDMMC_STATUS  ------------------------------------------
#define SDMMC_STATUS_FIFO_RX_WATERMARK_Pos                    0                                                         /*!< SDMMC STATUS: FIFO_RX_WATERMARK Position */
#define SDMMC_STATUS_FIFO_RX_WATERMARK_Msk                    (0x01UL << SDMMC_STATUS_FIFO_RX_WATERMARK_Pos)            /*!< SDMMC STATUS: FIFO_RX_WATERMARK Mask */
#define SDMMC_STATUS_FIFO_TX_WATERMARK_Pos                    1                                                         /*!< SDMMC STATUS: FIFO_TX_WATERMARK Position */
#define SDMMC_STATUS_FIFO_TX_WATERMARK_Msk                    (0x01UL << SDMMC_STATUS_FIFO_TX_WATERMARK_Pos)            /*!< SDMMC STATUS: FIFO_TX_WATERMARK Mask */
#define SDMMC_STATUS_FIFO_EMPTY_Pos                           2                                                         /*!< SDMMC STATUS: FIFO_EMPTY Position   */
#define SDMMC_STATUS_FIFO_EMPTY_Msk                           (0x01UL << SDMMC_STATUS_FIFO_EMPTY_Pos)                   /*!< SDMMC STATUS: FIFO_EMPTY Mask       */
#define SDMMC_STATUS_FIFO_FULL_Pos                            3                                                         /*!< SDMMC STATUS: FIFO_FULL Position    */
#define SDMMC_STATUS_FIFO_FULL_Msk                            (0x01UL << SDMMC_STATUS_FIFO_FULL_Pos)                    /*!< SDMMC STATUS: FIFO_FULL Mask        */
#define SDMMC_STATUS_CMDFSMSTATES_Pos                         4                                                         /*!< SDMMC STATUS: CMDFSMSTATES Position */
#define SDMMC_STATUS_CMDFSMSTATES_Msk                         (0x0fUL << SDMMC_STATUS_CMDFSMSTATES_Pos)                 /*!< SDMMC STATUS: CMDFSMSTATES Mask     */
#define SDMMC_STATUS_DATA_3_STATUS_Pos                        8                                                         /*!< SDMMC STATUS: DATA_3_STATUS Position */
#define SDMMC_STATUS_DATA_3_STATUS_Msk                        (0x01UL << SDMMC_STATUS_DATA_3_STATUS_Pos)                /*!< SDMMC STATUS: DATA_3_STATUS Mask    */
#define SDMMC_STATUS_DATA_BUSY_Pos                            9                                                         /*!< SDMMC STATUS: DATA_BUSY Position    */
#define SDMMC_STATUS_DATA_BUSY_Msk                            (0x01UL << SDMMC_STATUS_DATA_BUSY_Pos)                    /*!< SDMMC STATUS: DATA_BUSY Mask        */
#define SDMMC_STATUS_DATA_STATE_MC_BUSY_Pos                   10                                                        /*!< SDMMC STATUS: DATA_STATE_MC_BUSY Position */
#define SDMMC_STATUS_DATA_STATE_MC_BUSY_Msk                   (0x01UL << SDMMC_STATUS_DATA_STATE_MC_BUSY_Pos)           /*!< SDMMC STATUS: DATA_STATE_MC_BUSY Mask */
#define SDMMC_STATUS_RESPONSE_INDEX_Pos                       11                                                        /*!< SDMMC STATUS: RESPONSE_INDEX Position */
#define SDMMC_STATUS_RESPONSE_INDEX_Msk                       (0x3fUL << SDMMC_STATUS_RESPONSE_INDEX_Pos)               /*!< SDMMC STATUS: RESPONSE_INDEX Mask   */
#define SDMMC_STATUS_FIFO_COUNT_Pos                           17                                                        /*!< SDMMC STATUS: FIFO_COUNT Position   */
#define SDMMC_STATUS_FIFO_COUNT_Msk                           (0x00001fffUL << SDMMC_STATUS_FIFO_COUNT_Pos)             /*!< SDMMC STATUS: FIFO_COUNT Mask       */
#define SDMMC_STATUS_DMA_ACK_Pos                              30                                                        /*!< SDMMC STATUS: DMA_ACK Position      */
#define SDMMC_STATUS_DMA_ACK_Msk                              (0x01UL << SDMMC_STATUS_DMA_ACK_Pos)                      /*!< SDMMC STATUS: DMA_ACK Mask          */
#define SDMMC_STATUS_DMA_REQ_Pos                              31                                                        /*!< SDMMC STATUS: DMA_REQ Position      */
#define SDMMC_STATUS_DMA_REQ_Msk                              (0x01UL << SDMMC_STATUS_DMA_REQ_Pos)                      /*!< SDMMC STATUS: DMA_REQ Mask          */

// --------------------------------------  SDMMC_FIFOTH  ------------------------------------------
#define SDMMC_FIFOTH_TX_WMARK_Pos                             0                                                         /*!< SDMMC FIFOTH: TX_WMARK Position     */
#define SDMMC_FIFOTH_TX_WMARK_Msk                             (0x00000fffUL << SDMMC_FIFOTH_TX_WMARK_Pos)               /*!< SDMMC FIFOTH: TX_WMARK Mask         */
#define SDMMC_FIFOTH_RX_WMARK_Pos                             16                                                        /*!< SDMMC FIFOTH: RX_WMARK Position     */
#define SDMMC_FIFOTH_RX_WMARK_Msk                             (0x00000fffUL << SDMMC_FIFOTH_RX_WMARK_Pos)               /*!< SDMMC FIFOTH: RX_WMARK Mask         */
#define SDMMC_FIFOTH_DW_DMA_MUTIPLE_TRANSACTION_SIZE_Pos      28                                                        /*!< SDMMC FIFOTH: DW_DMA_MUTIPLE_TRANSACTION_SIZE Position */
#define SDMMC_FIFOTH_DW_DMA_MUTIPLE_TRANSACTION_SIZE_Msk      (0x07UL << SDMMC_FIFOTH_DW_DMA_MUTIPLE_TRANSACTION_SIZE_Pos)/*!< SDMMC FIFOTH: DW_DMA_MUTIPLE_TRANSACTION_SIZE Mask */

// --------------------------------------  SDMMC_CDETECT  -----------------------------------------
#define SDMMC_CDETECT_CARD_DETECT_N_Pos                       0                                                         /*!< SDMMC CDETECT: CARD_DETECT_N Position */
#define SDMMC_CDETECT_CARD_DETECT_N_Msk                       (0x3fffffffUL << SDMMC_CDETECT_CARD_DETECT_N_Pos)         /*!< SDMMC CDETECT: CARD_DETECT_N Mask   */

// --------------------------------------  SDMMC_WRTPRT  ------------------------------------------
#define SDMMC_WRTPRT_WRITE_PROTECT_Pos                        0                                                         /*!< SDMMC WRTPRT: WRITE_PROTECT Position */
#define SDMMC_WRTPRT_WRITE_PROTECT_Msk                        (0x3fffffffUL << SDMMC_WRTPRT_WRITE_PROTECT_Pos)          /*!< SDMMC WRTPRT: WRITE_PROTECT Mask    */

// ---------------------------------------  SDMMC_GPIO  -------------------------------------------
#define SDMMC_GPIO_GPI_Pos                                    0                                                         /*!< SDMMC GPIO: GPI Position            */
#define SDMMC_GPIO_GPI_Msk                                    (0x000000ffUL << SDMMC_GPIO_GPI_Pos)                      /*!< SDMMC GPIO: GPI Mask                */
#define SDMMC_GPIO_GPO_Pos                                    8                                                         /*!< SDMMC GPIO: GPO Position            */
#define SDMMC_GPIO_GPO_Msk                                    (0x0000ffffUL << SDMMC_GPIO_GPO_Pos)                      /*!< SDMMC GPIO: GPO Mask                */

// --------------------------------------  SDMMC_TCBCNT  ------------------------------------------
#define SDMMC_TCBCNT_TRANS_CARD_BYTE_COUNT_Pos                0                                                         /*!< SDMMC TCBCNT: TRANS_CARD_BYTE_COUNT Position */
#define SDMMC_TCBCNT_TRANS_CARD_BYTE_COUNT_Msk                (0xffffffffUL << SDMMC_TCBCNT_TRANS_CARD_BYTE_COUNT_Pos)  /*!< SDMMC TCBCNT: TRANS_CARD_BYTE_COUNT Mask */

// --------------------------------------  SDMMC_TBBCNT  ------------------------------------------
#define SDMMC_TBBCNT_TRANS_FIFO_BYTE_COUNT_Pos                0                                                         /*!< SDMMC TBBCNT: TRANS_FIFO_BYTE_COUNT Position */
#define SDMMC_TBBCNT_TRANS_FIFO_BYTE_COUNT_Msk                (0xffffffffUL << SDMMC_TBBCNT_TRANS_FIFO_BYTE_COUNT_Pos)  /*!< SDMMC TBBCNT: TRANS_FIFO_BYTE_COUNT Mask */

// --------------------------------------  SDMMC_DEBNCE  ------------------------------------------
#define SDMMC_DEBNCE_DEBOUNCE_COUNT_Pos                       0                                                         /*!< SDMMC DEBNCE: DEBOUNCE_COUNT Position */
#define SDMMC_DEBNCE_DEBOUNCE_COUNT_Msk                       (0x00ffffffUL << SDMMC_DEBNCE_DEBOUNCE_COUNT_Pos)         /*!< SDMMC DEBNCE: DEBOUNCE_COUNT Mask   */

// ---------------------------------------  SDMMC_USRID  ------------------------------------------
#define SDMMC_USRID_USRID_Pos                                 0                                                         /*!< SDMMC USRID: USRID Position         */
#define SDMMC_USRID_USRID_Msk                                 (0xffffffffUL << SDMMC_USRID_USRID_Pos)                   /*!< SDMMC USRID: USRID Mask             */

// ---------------------------------------  SDMMC_VERID  ------------------------------------------
#define SDMMC_VERID_VERID_Pos                                 0                                                         /*!< SDMMC VERID: VERID Position         */
#define SDMMC_VERID_VERID_Msk                                 (0xffffffffUL << SDMMC_VERID_VERID_Pos)                   /*!< SDMMC VERID: VERID Mask             */

// --------------------------------------  SDMMC_UHS_REG  -----------------------------------------
#define SDMMC_UHS_REG_VOLT_REG_Pos                            0                                                         /*!< SDMMC UHS_REG: VOLT_REG Position    */
#define SDMMC_UHS_REG_VOLT_REG_Msk                            (0x0000ffffUL << SDMMC_UHS_REG_VOLT_REG_Pos)              /*!< SDMMC UHS_REG: VOLT_REG Mask        */
#define SDMMC_UHS_REG_DDR_REG_Pos                             16                                                        /*!< SDMMC UHS_REG: DDR_REG Position     */
#define SDMMC_UHS_REG_DDR_REG_Msk                             (0x0000ffffUL << SDMMC_UHS_REG_DDR_REG_Pos)               /*!< SDMMC UHS_REG: DDR_REG Mask         */

// ---------------------------------------  SDMMC_RST_N  ------------------------------------------
#define SDMMC_RST_N_CARD_RESET_Pos                            0                                                         /*!< SDMMC RST_N: CARD_RESET Position    */
#define SDMMC_RST_N_CARD_RESET_Msk                            (0x0000ffffUL << SDMMC_RST_N_CARD_RESET_Pos)              /*!< SDMMC RST_N: CARD_RESET Mask        */

// ---------------------------------------  SDMMC_BMOD  -------------------------------------------
#define SDMMC_BMOD_SWR_Pos                                    0                                                         /*!< SDMMC BMOD: SWR Position            */
#define SDMMC_BMOD_SWR_Msk                                    (0x01UL << SDMMC_BMOD_SWR_Pos)                            /*!< SDMMC BMOD: SWR Mask                */
#define SDMMC_BMOD_FB_Pos                                     1                                                         /*!< SDMMC BMOD: FB Position             */
#define SDMMC_BMOD_FB_Msk                                     (0x01UL << SDMMC_BMOD_FB_Pos)                             /*!< SDMMC BMOD: FB Mask                 */
#define SDMMC_BMOD_DSL_Pos                                    2                                                         /*!< SDMMC BMOD: DSL Position            */
#define SDMMC_BMOD_DSL_Msk                                    (0x1fUL << SDMMC_BMOD_DSL_Pos)                            /*!< SDMMC BMOD: DSL Mask                */
#define SDMMC_BMOD_DE_Pos                                     7                                                         /*!< SDMMC BMOD: DE Position             */
#define SDMMC_BMOD_DE_Msk                                     (0x01UL << SDMMC_BMOD_DE_Pos)                             /*!< SDMMC BMOD: DE Mask                 */
#define SDMMC_BMOD_PBL_Pos                                    8                                                         /*!< SDMMC BMOD: PBL Position            */
#define SDMMC_BMOD_PBL_Msk                                    (0x07UL << SDMMC_BMOD_PBL_Pos)                            /*!< SDMMC BMOD: PBL Mask                */

// --------------------------------------  SDMMC_PLDMND  ------------------------------------------
#define SDMMC_PLDMND_PD_Pos                                   0                                                         /*!< SDMMC PLDMND: PD Position           */
#define SDMMC_PLDMND_PD_Msk                                   (0xffffffffUL << SDMMC_PLDMND_PD_Pos)                     /*!< SDMMC PLDMND: PD Mask               */

// --------------------------------------  SDMMC_DBADDR  ------------------------------------------
#define SDMMC_DBADDR_SDL_Pos                                  0                                                         /*!< SDMMC DBADDR: SDL Position          */
#define SDMMC_DBADDR_SDL_Msk                                  (0xffffffffUL << SDMMC_DBADDR_SDL_Pos)                    /*!< SDMMC DBADDR: SDL Mask              */

// ---------------------------------------  SDMMC_IDSTS  ------------------------------------------
#define SDMMC_IDSTS_TI_Pos                                    0                                                         /*!< SDMMC IDSTS: TI Position            */
#define SDMMC_IDSTS_TI_Msk                                    (0x01UL << SDMMC_IDSTS_TI_Pos)                            /*!< SDMMC IDSTS: TI Mask                */
#define SDMMC_IDSTS_RI_Pos                                    1                                                         /*!< SDMMC IDSTS: RI Position            */
#define SDMMC_IDSTS_RI_Msk                                    (0x01UL << SDMMC_IDSTS_RI_Pos)                            /*!< SDMMC IDSTS: RI Mask                */
#define SDMMC_IDSTS_FBE_Pos                                   2                                                         /*!< SDMMC IDSTS: FBE Position           */
#define SDMMC_IDSTS_FBE_Msk                                   (0x01UL << SDMMC_IDSTS_FBE_Pos)                           /*!< SDMMC IDSTS: FBE Mask               */
#define SDMMC_IDSTS_DU_Pos                                    4                                                         /*!< SDMMC IDSTS: DU Position            */
#define SDMMC_IDSTS_DU_Msk                                    (0x01UL << SDMMC_IDSTS_DU_Pos)                            /*!< SDMMC IDSTS: DU Mask                */
#define SDMMC_IDSTS_CES_Pos                                   5                                                         /*!< SDMMC IDSTS: CES Position           */
#define SDMMC_IDSTS_CES_Msk                                   (0x01UL << SDMMC_IDSTS_CES_Pos)                           /*!< SDMMC IDSTS: CES Mask               */
#define SDMMC_IDSTS_NIS_Pos                                   8                                                         /*!< SDMMC IDSTS: NIS Position           */
#define SDMMC_IDSTS_NIS_Msk                                   (0x01UL << SDMMC_IDSTS_NIS_Pos)                           /*!< SDMMC IDSTS: NIS Mask               */
#define SDMMC_IDSTS_AIS_Pos                                   9                                                         /*!< SDMMC IDSTS: AIS Position           */
#define SDMMC_IDSTS_AIS_Msk                                   (0x01UL << SDMMC_IDSTS_AIS_Pos)                           /*!< SDMMC IDSTS: AIS Mask               */
#define SDMMC_IDSTS_EB_Pos                                    10                                                        /*!< SDMMC IDSTS: EB Position            */
#define SDMMC_IDSTS_EB_Msk                                    (0x07UL << SDMMC_IDSTS_EB_Pos)                            /*!< SDMMC IDSTS: EB Mask                */
#define SDMMC_IDSTS_FSM_Pos                                   13                                                        /*!< SDMMC IDSTS: FSM Position           */
#define SDMMC_IDSTS_FSM_Msk                                   (0x0fUL << SDMMC_IDSTS_FSM_Pos)                           /*!< SDMMC IDSTS: FSM Mask               */

// --------------------------------------  SDMMC_IDINTEN  -----------------------------------------
#define SDMMC_IDINTEN_TI_Pos                                  0                                                         /*!< SDMMC IDINTEN: TI Position          */
#define SDMMC_IDINTEN_TI_Msk                                  (0x01UL << SDMMC_IDINTEN_TI_Pos)                          /*!< SDMMC IDINTEN: TI Mask              */
#define SDMMC_IDINTEN_RI_Pos                                  1                                                         /*!< SDMMC IDINTEN: RI Position          */
#define SDMMC_IDINTEN_RI_Msk                                  (0x01UL << SDMMC_IDINTEN_RI_Pos)                          /*!< SDMMC IDINTEN: RI Mask              */
#define SDMMC_IDINTEN_FBE_Pos                                 2                                                         /*!< SDMMC IDINTEN: FBE Position         */
#define SDMMC_IDINTEN_FBE_Msk                                 (0x01UL << SDMMC_IDINTEN_FBE_Pos)                         /*!< SDMMC IDINTEN: FBE Mask             */
#define SDMMC_IDINTEN_DU_Pos                                  4                                                         /*!< SDMMC IDINTEN: DU Position          */
#define SDMMC_IDINTEN_DU_Msk                                  (0x01UL << SDMMC_IDINTEN_DU_Pos)                          /*!< SDMMC IDINTEN: DU Mask              */
#define SDMMC_IDINTEN_CES_Pos                                 5                                                         /*!< SDMMC IDINTEN: CES Position         */
#define SDMMC_IDINTEN_CES_Msk                                 (0x01UL << SDMMC_IDINTEN_CES_Pos)                         /*!< SDMMC IDINTEN: CES Mask             */
#define SDMMC_IDINTEN_NIS_Pos                                 8                                                         /*!< SDMMC IDINTEN: NIS Position         */
#define SDMMC_IDINTEN_NIS_Msk                                 (0x01UL << SDMMC_IDINTEN_NIS_Pos)                         /*!< SDMMC IDINTEN: NIS Mask             */
#define SDMMC_IDINTEN_AIS_Pos                                 9                                                         /*!< SDMMC IDINTEN: AIS Position         */
#define SDMMC_IDINTEN_AIS_Msk                                 (0x01UL << SDMMC_IDINTEN_AIS_Pos)                         /*!< SDMMC IDINTEN: AIS Mask             */

// --------------------------------------  SDMMC_DSCADDR  -----------------------------------------
#define SDMMC_DSCADDR_HDA_Pos                                 0                                                         /*!< SDMMC DSCADDR: HDA Position         */
#define SDMMC_DSCADDR_HDA_Msk                                 (0xffffffffUL << SDMMC_DSCADDR_HDA_Pos)                   /*!< SDMMC DSCADDR: HDA Mask             */

// --------------------------------------  SDMMC_BUFADDR  -----------------------------------------
#define SDMMC_BUFADDR_HBA_Pos                                 0                                                         /*!< SDMMC BUFADDR: HBA Position         */
#define SDMMC_BUFADDR_HBA_Msk                                 (0xffffffffUL << SDMMC_BUFADDR_HBA_Pos)                   /*!< SDMMC BUFADDR: HBA Mask             */


// ------------------------------------------------------------------------------------------------
// -----                                  EMC Position & Mask                                 -----
// ------------------------------------------------------------------------------------------------


// ---------------------------------------  EMC_CONTROL  ------------------------------------------
#define EMC_CONTROL_E_Pos                                     0                                                         /*!< EMC CONTROL: E Position             */
#define EMC_CONTROL_E_Msk                                     (0x01UL << EMC_CONTROL_E_Pos)                             /*!< EMC CONTROL: E Mask                 */
#define EMC_CONTROL_M_Pos                                     1                                                         /*!< EMC CONTROL: M Position             */
#define EMC_CONTROL_M_Msk                                     (0x01UL << EMC_CONTROL_M_Pos)                             /*!< EMC CONTROL: M Mask                 */
#define EMC_CONTROL_L_Pos                                     2                                                         /*!< EMC CONTROL: L Position             */
#define EMC_CONTROL_L_Msk                                     (0x01UL << EMC_CONTROL_L_Pos)                             /*!< EMC CONTROL: L Mask                 */

// ---------------------------------------  EMC_STATUS  -------------------------------------------
#define EMC_STATUS_B_Pos                                      0                                                         /*!< EMC STATUS: B Position              */
#define EMC_STATUS_B_Msk                                      (0x01UL << EMC_STATUS_B_Pos)                              /*!< EMC STATUS: B Mask                  */
#define EMC_STATUS_S_Pos                                      1                                                         /*!< EMC STATUS: S Position              */
#define EMC_STATUS_S_Msk                                      (0x01UL << EMC_STATUS_S_Pos)                              /*!< EMC STATUS: S Mask                  */
#define EMC_STATUS_SA_Pos                                     2                                                         /*!< EMC STATUS: SA Position             */
#define EMC_STATUS_SA_Msk                                     (0x01UL << EMC_STATUS_SA_Pos)                             /*!< EMC STATUS: SA Mask                 */

// ---------------------------------------  EMC_CONFIG  -------------------------------------------
#define EMC_CONFIG_EM_Pos                                     0                                                         /*!< EMC CONFIG: EM Position             */
#define EMC_CONFIG_EM_Msk                                     (0x01UL << EMC_CONFIG_EM_Pos)                             /*!< EMC CONFIG: EM Mask                 */
#define EMC_CONFIG_CR_Pos                                     8                                                         /*!< EMC CONFIG: CR Position             */
#define EMC_CONFIG_CR_Msk                                     (0x01UL << EMC_CONFIG_CR_Pos)                             /*!< EMC CONFIG: CR Mask                 */

// -----------------------------------  EMC_DYNAMICCONTROL  ---------------------------------------
#define EMC_DYNAMICCONTROL_CE_Pos                             0                                                         /*!< EMC DYNAMICCONTROL: CE Position     */
#define EMC_DYNAMICCONTROL_CE_Msk                             (0x01UL << EMC_DYNAMICCONTROL_CE_Pos)                     /*!< EMC DYNAMICCONTROL: CE Mask         */
#define EMC_DYNAMICCONTROL_CS_Pos                             1                                                         /*!< EMC DYNAMICCONTROL: CS Position     */
#define EMC_DYNAMICCONTROL_CS_Msk                             (0x01UL << EMC_DYNAMICCONTROL_CS_Pos)                     /*!< EMC DYNAMICCONTROL: CS Mask         */
#define EMC_DYNAMICCONTROL_SR_Pos                             2                                                         /*!< EMC DYNAMICCONTROL: SR Position     */
#define EMC_DYNAMICCONTROL_SR_Msk                             (0x01UL << EMC_DYNAMICCONTROL_SR_Pos)                     /*!< EMC DYNAMICCONTROL: SR Mask         */
#define EMC_DYNAMICCONTROL_MMC_Pos                            5                                                         /*!< EMC DYNAMICCONTROL: MMC Position    */
#define EMC_DYNAMICCONTROL_MMC_Msk                            (0x01UL << EMC_DYNAMICCONTROL_MMC_Pos)                    /*!< EMC DYNAMICCONTROL: MMC Mask        */
#define EMC_DYNAMICCONTROL_I_Pos                              7                                                         /*!< EMC DYNAMICCONTROL: I Position      */
#define EMC_DYNAMICCONTROL_I_Msk                              (0x03UL << EMC_DYNAMICCONTROL_I_Pos)                      /*!< EMC DYNAMICCONTROL: I Mask          */
#define EMC_DYNAMICCONTROL_DP_Pos                             13                                                        /*!< EMC DYNAMICCONTROL: DP Position     */
#define EMC_DYNAMICCONTROL_DP_Msk                             (0x01UL << EMC_DYNAMICCONTROL_DP_Pos)                     /*!< EMC DYNAMICCONTROL: DP Mask         */

// -----------------------------------  EMC_DYNAMICREFRESH  ---------------------------------------
#define EMC_DYNAMICREFRESH_REFRESH_Pos                        0                                                         /*!< EMC DYNAMICREFRESH: REFRESH Position */
#define EMC_DYNAMICREFRESH_REFRESH_Msk                        (0x000007ffUL << EMC_DYNAMICREFRESH_REFRESH_Pos)          /*!< EMC DYNAMICREFRESH: REFRESH Mask    */

// ----------------------------------  EMC_DYNAMICREADCONFIG  -------------------------------------
#define EMC_DYNAMICREADCONFIG_RD_Pos                          0                                                         /*!< EMC DYNAMICREADCONFIG: RD Position  */
#define EMC_DYNAMICREADCONFIG_RD_Msk                          (0x03UL << EMC_DYNAMICREADCONFIG_RD_Pos)                  /*!< EMC DYNAMICREADCONFIG: RD Mask      */

// --------------------------------------  EMC_DYNAMICRP  -----------------------------------------
#define EMC_DYNAMICRP_tRP_Pos                                 0                                                         /*!< EMC DYNAMICRP: tRP Position         */
#define EMC_DYNAMICRP_tRP_Msk                                 (0x0fUL << EMC_DYNAMICRP_tRP_Pos)                         /*!< EMC DYNAMICRP: tRP Mask             */

// -------------------------------------  EMC_DYNAMICRAS  -----------------------------------------
#define EMC_DYNAMICRAS_tRAS_Pos                               0                                                         /*!< EMC DYNAMICRAS: tRAS Position       */
#define EMC_DYNAMICRAS_tRAS_Msk                               (0x0fUL << EMC_DYNAMICRAS_tRAS_Pos)                       /*!< EMC DYNAMICRAS: tRAS Mask           */

// -------------------------------------  EMC_DYNAMICSREX  ----------------------------------------
#define EMC_DYNAMICSREX_tSREX_Pos                             0                                                         /*!< EMC DYNAMICSREX: tSREX Position     */
#define EMC_DYNAMICSREX_tSREX_Msk                             (0x0fUL << EMC_DYNAMICSREX_tSREX_Pos)                     /*!< EMC DYNAMICSREX: tSREX Mask         */

// -------------------------------------  EMC_DYNAMICAPR  -----------------------------------------
#define EMC_DYNAMICAPR_tAPR_Pos                               0                                                         /*!< EMC DYNAMICAPR: tAPR Position       */
#define EMC_DYNAMICAPR_tAPR_Msk                               (0x0fUL << EMC_DYNAMICAPR_tAPR_Pos)                       /*!< EMC DYNAMICAPR: tAPR Mask           */

// -------------------------------------  EMC_DYNAMICDAL  -----------------------------------------
#define EMC_DYNAMICDAL_tDAL_Pos                               0                                                         /*!< EMC DYNAMICDAL: tDAL Position       */
#define EMC_DYNAMICDAL_tDAL_Msk                               (0x0fUL << EMC_DYNAMICDAL_tDAL_Pos)                       /*!< EMC DYNAMICDAL: tDAL Mask           */

// --------------------------------------  EMC_DYNAMICWR  -----------------------------------------
#define EMC_DYNAMICWR_tWR_Pos                                 0                                                         /*!< EMC DYNAMICWR: tWR Position         */
#define EMC_DYNAMICWR_tWR_Msk                                 (0x0fUL << EMC_DYNAMICWR_tWR_Pos)                         /*!< EMC DYNAMICWR: tWR Mask             */

// --------------------------------------  EMC_DYNAMICRC  -----------------------------------------
#define EMC_DYNAMICRC_tRC_Pos                                 0                                                         /*!< EMC DYNAMICRC: tRC Position         */
#define EMC_DYNAMICRC_tRC_Msk                                 (0x1fUL << EMC_DYNAMICRC_tRC_Pos)                         /*!< EMC DYNAMICRC: tRC Mask             */

// -------------------------------------  EMC_DYNAMICRFC  -----------------------------------------
#define EMC_DYNAMICRFC_tRFC_Pos                               0                                                         /*!< EMC DYNAMICRFC: tRFC Position       */
#define EMC_DYNAMICRFC_tRFC_Msk                               (0x1fUL << EMC_DYNAMICRFC_tRFC_Pos)                       /*!< EMC DYNAMICRFC: tRFC Mask           */

// -------------------------------------  EMC_DYNAMICXSR  -----------------------------------------
#define EMC_DYNAMICXSR_tXSR_Pos                               0                                                         /*!< EMC DYNAMICXSR: tXSR Position       */
#define EMC_DYNAMICXSR_tXSR_Msk                               (0x1fUL << EMC_DYNAMICXSR_tXSR_Pos)                       /*!< EMC DYNAMICXSR: tXSR Mask           */

// -------------------------------------  EMC_DYNAMICRRD  -----------------------------------------
#define EMC_DYNAMICRRD_tRRD_Pos                               0                                                         /*!< EMC DYNAMICRRD: tRRD Position       */
#define EMC_DYNAMICRRD_tRRD_Msk                               (0x0fUL << EMC_DYNAMICRRD_tRRD_Pos)                       /*!< EMC DYNAMICRRD: tRRD Mask           */

// -------------------------------------  EMC_DYNAMICMRD  -----------------------------------------
#define EMC_DYNAMICMRD_tMRD_Pos                               0                                                         /*!< EMC DYNAMICMRD: tMRD Position       */
#define EMC_DYNAMICMRD_tMRD_Msk                               (0x0fUL << EMC_DYNAMICMRD_tMRD_Pos)                       /*!< EMC DYNAMICMRD: tMRD Mask           */

// ---------------------------------  EMC_STATICEXTENDEDWAIT  -------------------------------------
#define EMC_STATICEXTENDEDWAIT_EXTENDEDWAIT_Pos               0                                                         /*!< EMC STATICEXTENDEDWAIT: EXTENDEDWAIT Position */
#define EMC_STATICEXTENDEDWAIT_EXTENDEDWAIT_Msk               (0x000003ffUL << EMC_STATICEXTENDEDWAIT_EXTENDEDWAIT_Pos) /*!< EMC STATICEXTENDEDWAIT: EXTENDEDWAIT Mask */

// -----------------------------------  EMC_DYNAMICCONFIG0  ---------------------------------------
#define EMC_DYNAMICCONFIG0_MD_Pos                             3                                                         /*!< EMC DYNAMICCONFIG0: MD Position     */
#define EMC_DYNAMICCONFIG0_MD_Msk                             (0x03UL << EMC_DYNAMICCONFIG0_MD_Pos)                     /*!< EMC DYNAMICCONFIG0: MD Mask         */
#define EMC_DYNAMICCONFIG0_AM0_Pos                            7                                                         /*!< EMC DYNAMICCONFIG0: AM0 Position    */
#define EMC_DYNAMICCONFIG0_AM0_Msk                            (0x3fUL << EMC_DYNAMICCONFIG0_AM0_Pos)                    /*!< EMC DYNAMICCONFIG0: AM0 Mask        */
#define EMC_DYNAMICCONFIG0_AM1_Pos                            14                                                        /*!< EMC DYNAMICCONFIG0: AM1 Position    */
#define EMC_DYNAMICCONFIG0_AM1_Msk                            (0x01UL << EMC_DYNAMICCONFIG0_AM1_Pos)                    /*!< EMC DYNAMICCONFIG0: AM1 Mask        */
#define EMC_DYNAMICCONFIG0_B_Pos                              19                                                        /*!< EMC DYNAMICCONFIG0: B Position      */
#define EMC_DYNAMICCONFIG0_B_Msk                              (0x01UL << EMC_DYNAMICCONFIG0_B_Pos)                      /*!< EMC DYNAMICCONFIG0: B Mask          */
#define EMC_DYNAMICCONFIG0_P_Pos                              20                                                        /*!< EMC DYNAMICCONFIG0: P Position      */
#define EMC_DYNAMICCONFIG0_P_Msk                              (0x01UL << EMC_DYNAMICCONFIG0_P_Pos)                      /*!< EMC DYNAMICCONFIG0: P Mask          */

// -----------------------------------  EMC_DYNAMICRASCAS0  ---------------------------------------
#define EMC_DYNAMICRASCAS0_RAS_Pos                            0                                                         /*!< EMC DYNAMICRASCAS0: RAS Position    */
#define EMC_DYNAMICRASCAS0_RAS_Msk                            (0x03UL << EMC_DYNAMICRASCAS0_RAS_Pos)                    /*!< EMC DYNAMICRASCAS0: RAS Mask        */
#define EMC_DYNAMICRASCAS0_CAS_Pos                            8                                                         /*!< EMC DYNAMICRASCAS0: CAS Position    */
#define EMC_DYNAMICRASCAS0_CAS_Msk                            (0x03UL << EMC_DYNAMICRASCAS0_CAS_Pos)                    /*!< EMC DYNAMICRASCAS0: CAS Mask        */

// -----------------------------------  EMC_DYNAMICCONFIG1  ---------------------------------------
#define EMC_DYNAMICCONFIG1_MD_Pos                             3                                                         /*!< EMC DYNAMICCONFIG1: MD Position     */
#define EMC_DYNAMICCONFIG1_MD_Msk                             (0x03UL << EMC_DYNAMICCONFIG1_MD_Pos)                     /*!< EMC DYNAMICCONFIG1: MD Mask         */
#define EMC_DYNAMICCONFIG1_AM0_Pos                            7                                                         /*!< EMC DYNAMICCONFIG1: AM0 Position    */
#define EMC_DYNAMICCONFIG1_AM0_Msk                            (0x3fUL << EMC_DYNAMICCONFIG1_AM0_Pos)                    /*!< EMC DYNAMICCONFIG1: AM0 Mask        */
#define EMC_DYNAMICCONFIG1_AM1_Pos                            14                                                        /*!< EMC DYNAMICCONFIG1: AM1 Position    */
#define EMC_DYNAMICCONFIG1_AM1_Msk                            (0x01UL << EMC_DYNAMICCONFIG1_AM1_Pos)                    /*!< EMC DYNAMICCONFIG1: AM1 Mask        */
#define EMC_DYNAMICCONFIG1_B_Pos                              19                                                        /*!< EMC DYNAMICCONFIG1: B Position      */
#define EMC_DYNAMICCONFIG1_B_Msk                              (0x01UL << EMC_DYNAMICCONFIG1_B_Pos)                      /*!< EMC DYNAMICCONFIG1: B Mask          */
#define EMC_DYNAMICCONFIG1_P_Pos                              20                                                        /*!< EMC DYNAMICCONFIG1: P Position      */
#define EMC_DYNAMICCONFIG1_P_Msk                              (0x01UL << EMC_DYNAMICCONFIG1_P_Pos)                      /*!< EMC DYNAMICCONFIG1: P Mask          */

// -----------------------------------  EMC_DYNAMICRASCAS1  ---------------------------------------
#define EMC_DYNAMICRASCAS1_RAS_Pos                            0                                                         /*!< EMC DYNAMICRASCAS1: RAS Position    */
#define EMC_DYNAMICRASCAS1_RAS_Msk                            (0x03UL << EMC_DYNAMICRASCAS1_RAS_Pos)                    /*!< EMC DYNAMICRASCAS1: RAS Mask        */
#define EMC_DYNAMICRASCAS1_CAS_Pos                            8                                                         /*!< EMC DYNAMICRASCAS1: CAS Position    */
#define EMC_DYNAMICRASCAS1_CAS_Msk                            (0x03UL << EMC_DYNAMICRASCAS1_CAS_Pos)                    /*!< EMC DYNAMICRASCAS1: CAS Mask        */

// -----------------------------------  EMC_DYNAMICCONFIG2  ---------------------------------------
#define EMC_DYNAMICCONFIG2_MD_Pos                             3                                                         /*!< EMC DYNAMICCONFIG2: MD Position     */
#define EMC_DYNAMICCONFIG2_MD_Msk                             (0x03UL << EMC_DYNAMICCONFIG2_MD_Pos)                     /*!< EMC DYNAMICCONFIG2: MD Mask         */
#define EMC_DYNAMICCONFIG2_AM0_Pos                            7                                                         /*!< EMC DYNAMICCONFIG2: AM0 Position    */
#define EMC_DYNAMICCONFIG2_AM0_Msk                            (0x3fUL << EMC_DYNAMICCONFIG2_AM0_Pos)                    /*!< EMC DYNAMICCONFIG2: AM0 Mask        */
#define EMC_DYNAMICCONFIG2_AM1_Pos                            14                                                        /*!< EMC DYNAMICCONFIG2: AM1 Position    */
#define EMC_DYNAMICCONFIG2_AM1_Msk                            (0x01UL << EMC_DYNAMICCONFIG2_AM1_Pos)                    /*!< EMC DYNAMICCONFIG2: AM1 Mask        */
#define EMC_DYNAMICCONFIG2_B_Pos                              19                                                        /*!< EMC DYNAMICCONFIG2: B Position      */
#define EMC_DYNAMICCONFIG2_B_Msk                              (0x01UL << EMC_DYNAMICCONFIG2_B_Pos)                      /*!< EMC DYNAMICCONFIG2: B Mask          */
#define EMC_DYNAMICCONFIG2_P_Pos                              20                                                        /*!< EMC DYNAMICCONFIG2: P Position      */
#define EMC_DYNAMICCONFIG2_P_Msk                              (0x01UL << EMC_DYNAMICCONFIG2_P_Pos)                      /*!< EMC DYNAMICCONFIG2: P Mask          */

// -----------------------------------  EMC_DYNAMICRASCAS2  ---------------------------------------
#define EMC_DYNAMICRASCAS2_RAS_Pos                            0                                                         /*!< EMC DYNAMICRASCAS2: RAS Position    */
#define EMC_DYNAMICRASCAS2_RAS_Msk                            (0x03UL << EMC_DYNAMICRASCAS2_RAS_Pos)                    /*!< EMC DYNAMICRASCAS2: RAS Mask        */
#define EMC_DYNAMICRASCAS2_CAS_Pos                            8                                                         /*!< EMC DYNAMICRASCAS2: CAS Position    */
#define EMC_DYNAMICRASCAS2_CAS_Msk                            (0x03UL << EMC_DYNAMICRASCAS2_CAS_Pos)                    /*!< EMC DYNAMICRASCAS2: CAS Mask        */

// -----------------------------------  EMC_DYNAMICCONFIG3  ---------------------------------------
#define EMC_DYNAMICCONFIG3_MD_Pos                             3                                                         /*!< EMC DYNAMICCONFIG3: MD Position     */
#define EMC_DYNAMICCONFIG3_MD_Msk                             (0x03UL << EMC_DYNAMICCONFIG3_MD_Pos)                     /*!< EMC DYNAMICCONFIG3: MD Mask         */
#define EMC_DYNAMICCONFIG3_AM0_Pos                            7                                                         /*!< EMC DYNAMICCONFIG3: AM0 Position    */
#define EMC_DYNAMICCONFIG3_AM0_Msk                            (0x3fUL << EMC_DYNAMICCONFIG3_AM0_Pos)                    /*!< EMC DYNAMICCONFIG3: AM0 Mask        */
#define EMC_DYNAMICCONFIG3_AM1_Pos                            14                                                        /*!< EMC DYNAMICCONFIG3: AM1 Position    */
#define EMC_DYNAMICCONFIG3_AM1_Msk                            (0x01UL << EMC_DYNAMICCONFIG3_AM1_Pos)                    /*!< EMC DYNAMICCONFIG3: AM1 Mask        */
#define EMC_DYNAMICCONFIG3_B_Pos                              19                                                        /*!< EMC DYNAMICCONFIG3: B Position      */
#define EMC_DYNAMICCONFIG3_B_Msk                              (0x01UL << EMC_DYNAMICCONFIG3_B_Pos)                      /*!< EMC DYNAMICCONFIG3: B Mask          */
#define EMC_DYNAMICCONFIG3_P_Pos                              20                                                        /*!< EMC DYNAMICCONFIG3: P Position      */
#define EMC_DYNAMICCONFIG3_P_Msk                              (0x01UL << EMC_DYNAMICCONFIG3_P_Pos)                      /*!< EMC DYNAMICCONFIG3: P Mask          */

// -----------------------------------  EMC_DYNAMICRASCAS3  ---------------------------------------
#define EMC_DYNAMICRASCAS3_RAS_Pos                            0                                                         /*!< EMC DYNAMICRASCAS3: RAS Position    */
#define EMC_DYNAMICRASCAS3_RAS_Msk                            (0x03UL << EMC_DYNAMICRASCAS3_RAS_Pos)                    /*!< EMC DYNAMICRASCAS3: RAS Mask        */
#define EMC_DYNAMICRASCAS3_CAS_Pos                            8                                                         /*!< EMC DYNAMICRASCAS3: CAS Position    */
#define EMC_DYNAMICRASCAS3_CAS_Msk                            (0x03UL << EMC_DYNAMICRASCAS3_CAS_Pos)                    /*!< EMC DYNAMICRASCAS3: CAS Mask        */

// ------------------------------------  EMC_STATICCONFIG0  ---------------------------------------
#define EMC_STATICCONFIG0_MW_Pos                              0                                                         /*!< EMC STATICCONFIG0: MW Position      */
#define EMC_STATICCONFIG0_MW_Msk                              (0x03UL << EMC_STATICCONFIG0_MW_Pos)                      /*!< EMC STATICCONFIG0: MW Mask          */
#define EMC_STATICCONFIG0_PM_Pos                              3                                                         /*!< EMC STATICCONFIG0: PM Position      */
#define EMC_STATICCONFIG0_PM_Msk                              (0x01UL << EMC_STATICCONFIG0_PM_Pos)                      /*!< EMC STATICCONFIG0: PM Mask          */
#define EMC_STATICCONFIG0_PC_Pos                              6                                                         /*!< EMC STATICCONFIG0: PC Position      */
#define EMC_STATICCONFIG0_PC_Msk                              (0x01UL << EMC_STATICCONFIG0_PC_Pos)                      /*!< EMC STATICCONFIG0: PC Mask          */
#define EMC_STATICCONFIG0_PB_Pos                              7                                                         /*!< EMC STATICCONFIG0: PB Position      */
#define EMC_STATICCONFIG0_PB_Msk                              (0x01UL << EMC_STATICCONFIG0_PB_Pos)                      /*!< EMC STATICCONFIG0: PB Mask          */
#define EMC_STATICCONFIG0_EW_Pos                              8                                                         /*!< EMC STATICCONFIG0: EW Position      */
#define EMC_STATICCONFIG0_EW_Msk                              (0x01UL << EMC_STATICCONFIG0_EW_Pos)                      /*!< EMC STATICCONFIG0: EW Mask          */
#define EMC_STATICCONFIG0_B_Pos                               19                                                        /*!< EMC STATICCONFIG0: B Position       */
#define EMC_STATICCONFIG0_B_Msk                               (0x01UL << EMC_STATICCONFIG0_B_Pos)                       /*!< EMC STATICCONFIG0: B Mask           */
#define EMC_STATICCONFIG0_P_Pos                               20                                                        /*!< EMC STATICCONFIG0: P Position       */
#define EMC_STATICCONFIG0_P_Msk                               (0x01UL << EMC_STATICCONFIG0_P_Pos)                       /*!< EMC STATICCONFIG0: P Mask           */

// -----------------------------------  EMC_STATICWAITWEN0  ---------------------------------------
#define EMC_STATICWAITWEN0_WAITWEN_Pos                        0                                                         /*!< EMC STATICWAITWEN0: WAITWEN Position */
#define EMC_STATICWAITWEN0_WAITWEN_Msk                        (0x0fUL << EMC_STATICWAITWEN0_WAITWEN_Pos)                /*!< EMC STATICWAITWEN0: WAITWEN Mask    */

// -----------------------------------  EMC_STATICWAITOEN0  ---------------------------------------
#define EMC_STATICWAITOEN0_WAITOEN_Pos                        0                                                         /*!< EMC STATICWAITOEN0: WAITOEN Position */
#define EMC_STATICWAITOEN0_WAITOEN_Msk                        (0x0fUL << EMC_STATICWAITOEN0_WAITOEN_Pos)                /*!< EMC STATICWAITOEN0: WAITOEN Mask    */

// ------------------------------------  EMC_STATICWAITRD0  ---------------------------------------
#define EMC_STATICWAITRD0_WAITRD_Pos                          0                                                         /*!< EMC STATICWAITRD0: WAITRD Position  */
#define EMC_STATICWAITRD0_WAITRD_Msk                          (0x1fUL << EMC_STATICWAITRD0_WAITRD_Pos)                  /*!< EMC STATICWAITRD0: WAITRD Mask      */

// -----------------------------------  EMC_STATICWAITPAG0  ---------------------------------------
#define EMC_STATICWAITPAG0_WAITPAGE_Pos                       0                                                         /*!< EMC STATICWAITPAG0: WAITPAGE Position */
#define EMC_STATICWAITPAG0_WAITPAGE_Msk                       (0x1fUL << EMC_STATICWAITPAG0_WAITPAGE_Pos)               /*!< EMC STATICWAITPAG0: WAITPAGE Mask   */

// ------------------------------------  EMC_STATICWAITWR0  ---------------------------------------
#define EMC_STATICWAITWR0_WAITWR_Pos                          0                                                         /*!< EMC STATICWAITWR0: WAITWR Position  */
#define EMC_STATICWAITWR0_WAITWR_Msk                          (0x1fUL << EMC_STATICWAITWR0_WAITWR_Pos)                  /*!< EMC STATICWAITWR0: WAITWR Mask      */

// -----------------------------------  EMC_STATICWAITTURN0  --------------------------------------
#define EMC_STATICWAITTURN0_WAITTURN_Pos                      0                                                         /*!< EMC STATICWAITTURN0: WAITTURN Position */
#define EMC_STATICWAITTURN0_WAITTURN_Msk                      (0x0fUL << EMC_STATICWAITTURN0_WAITTURN_Pos)              /*!< EMC STATICWAITTURN0: WAITTURN Mask  */

// ------------------------------------  EMC_STATICCONFIG1  ---------------------------------------
#define EMC_STATICCONFIG1_MW_Pos                              0                                                         /*!< EMC STATICCONFIG1: MW Position      */
#define EMC_STATICCONFIG1_MW_Msk                              (0x03UL << EMC_STATICCONFIG1_MW_Pos)                      /*!< EMC STATICCONFIG1: MW Mask          */
#define EMC_STATICCONFIG1_PM_Pos                              3                                                         /*!< EMC STATICCONFIG1: PM Position      */
#define EMC_STATICCONFIG1_PM_Msk                              (0x01UL << EMC_STATICCONFIG1_PM_Pos)                      /*!< EMC STATICCONFIG1: PM Mask          */
#define EMC_STATICCONFIG1_PC_Pos                              6                                                         /*!< EMC STATICCONFIG1: PC Position      */
#define EMC_STATICCONFIG1_PC_Msk                              (0x01UL << EMC_STATICCONFIG1_PC_Pos)                      /*!< EMC STATICCONFIG1: PC Mask          */
#define EMC_STATICCONFIG1_PB_Pos                              7                                                         /*!< EMC STATICCONFIG1: PB Position      */
#define EMC_STATICCONFIG1_PB_Msk                              (0x01UL << EMC_STATICCONFIG1_PB_Pos)                      /*!< EMC STATICCONFIG1: PB Mask          */
#define EMC_STATICCONFIG1_EW_Pos                              8                                                         /*!< EMC STATICCONFIG1: EW Position      */
#define EMC_STATICCONFIG1_EW_Msk                              (0x01UL << EMC_STATICCONFIG1_EW_Pos)                      /*!< EMC STATICCONFIG1: EW Mask          */
#define EMC_STATICCONFIG1_B_Pos                               19                                                        /*!< EMC STATICCONFIG1: B Position       */
#define EMC_STATICCONFIG1_B_Msk                               (0x01UL << EMC_STATICCONFIG1_B_Pos)                       /*!< EMC STATICCONFIG1: B Mask           */
#define EMC_STATICCONFIG1_P_Pos                               20                                                        /*!< EMC STATICCONFIG1: P Position       */
#define EMC_STATICCONFIG1_P_Msk                               (0x01UL << EMC_STATICCONFIG1_P_Pos)                       /*!< EMC STATICCONFIG1: P Mask           */

// -----------------------------------  EMC_STATICWAITWEN1  ---------------------------------------
#define EMC_STATICWAITWEN1_WAITWEN_Pos                        0                                                         /*!< EMC STATICWAITWEN1: WAITWEN Position */
#define EMC_STATICWAITWEN1_WAITWEN_Msk                        (0x0fUL << EMC_STATICWAITWEN1_WAITWEN_Pos)                /*!< EMC STATICWAITWEN1: WAITWEN Mask    */

// -----------------------------------  EMC_STATICWAITOEN1  ---------------------------------------
#define EMC_STATICWAITOEN1_WAITOEN_Pos                        0                                                         /*!< EMC STATICWAITOEN1: WAITOEN Position */
#define EMC_STATICWAITOEN1_WAITOEN_Msk                        (0x0fUL << EMC_STATICWAITOEN1_WAITOEN_Pos)                /*!< EMC STATICWAITOEN1: WAITOEN Mask    */

// ------------------------------------  EMC_STATICWAITRD1  ---------------------------------------
#define EMC_STATICWAITRD1_WAITRD_Pos                          0                                                         /*!< EMC STATICWAITRD1: WAITRD Position  */
#define EMC_STATICWAITRD1_WAITRD_Msk                          (0x1fUL << EMC_STATICWAITRD1_WAITRD_Pos)                  /*!< EMC STATICWAITRD1: WAITRD Mask      */

// -----------------------------------  EMC_STATICWAITPAG1  ---------------------------------------
#define EMC_STATICWAITPAG1_WAITPAGE_Pos                       0                                                         /*!< EMC STATICWAITPAG1: WAITPAGE Position */
#define EMC_STATICWAITPAG1_WAITPAGE_Msk                       (0x1fUL << EMC_STATICWAITPAG1_WAITPAGE_Pos)               /*!< EMC STATICWAITPAG1: WAITPAGE Mask   */

// ------------------------------------  EMC_STATICWAITWR1  ---------------------------------------
#define EMC_STATICWAITWR1_WAITWR_Pos                          0                                                         /*!< EMC STATICWAITWR1: WAITWR Position  */
#define EMC_STATICWAITWR1_WAITWR_Msk                          (0x1fUL << EMC_STATICWAITWR1_WAITWR_Pos)                  /*!< EMC STATICWAITWR1: WAITWR Mask      */

// -----------------------------------  EMC_STATICWAITTURN1  --------------------------------------
#define EMC_STATICWAITTURN1_WAITTURN_Pos                      0                                                         /*!< EMC STATICWAITTURN1: WAITTURN Position */
#define EMC_STATICWAITTURN1_WAITTURN_Msk                      (0x0fUL << EMC_STATICWAITTURN1_WAITTURN_Pos)              /*!< EMC STATICWAITTURN1: WAITTURN Mask  */

// ------------------------------------  EMC_STATICCONFIG2  ---------------------------------------
#define EMC_STATICCONFIG2_MW_Pos                              0                                                         /*!< EMC STATICCONFIG2: MW Position      */
#define EMC_STATICCONFIG2_MW_Msk                              (0x03UL << EMC_STATICCONFIG2_MW_Pos)                      /*!< EMC STATICCONFIG2: MW Mask          */
#define EMC_STATICCONFIG2_PM_Pos                              3                                                         /*!< EMC STATICCONFIG2: PM Position      */
#define EMC_STATICCONFIG2_PM_Msk                              (0x01UL << EMC_STATICCONFIG2_PM_Pos)                      /*!< EMC STATICCONFIG2: PM Mask          */
#define EMC_STATICCONFIG2_PC_Pos                              6                                                         /*!< EMC STATICCONFIG2: PC Position      */
#define EMC_STATICCONFIG2_PC_Msk                              (0x01UL << EMC_STATICCONFIG2_PC_Pos)                      /*!< EMC STATICCONFIG2: PC Mask          */
#define EMC_STATICCONFIG2_PB_Pos                              7                                                         /*!< EMC STATICCONFIG2: PB Position      */
#define EMC_STATICCONFIG2_PB_Msk                              (0x01UL << EMC_STATICCONFIG2_PB_Pos)                      /*!< EMC STATICCONFIG2: PB Mask          */
#define EMC_STATICCONFIG2_EW_Pos                              8                                                         /*!< EMC STATICCONFIG2: EW Position      */
#define EMC_STATICCONFIG2_EW_Msk                              (0x01UL << EMC_STATICCONFIG2_EW_Pos)                      /*!< EMC STATICCONFIG2: EW Mask          */
#define EMC_STATICCONFIG2_B_Pos                               19                                                        /*!< EMC STATICCONFIG2: B Position       */
#define EMC_STATICCONFIG2_B_Msk                               (0x01UL << EMC_STATICCONFIG2_B_Pos)                       /*!< EMC STATICCONFIG2: B Mask           */
#define EMC_STATICCONFIG2_P_Pos                               20                                                        /*!< EMC STATICCONFIG2: P Position       */
#define EMC_STATICCONFIG2_P_Msk                               (0x01UL << EMC_STATICCONFIG2_P_Pos)                       /*!< EMC STATICCONFIG2: P Mask           */

// -----------------------------------  EMC_STATICWAITWEN2  ---------------------------------------
#define EMC_STATICWAITWEN2_WAITWEN_Pos                        0                                                         /*!< EMC STATICWAITWEN2: WAITWEN Position */
#define EMC_STATICWAITWEN2_WAITWEN_Msk                        (0x0fUL << EMC_STATICWAITWEN2_WAITWEN_Pos)                /*!< EMC STATICWAITWEN2: WAITWEN Mask    */

// -----------------------------------  EMC_STATICWAITOEN2  ---------------------------------------
#define EMC_STATICWAITOEN2_WAITOEN_Pos                        0                                                         /*!< EMC STATICWAITOEN2: WAITOEN Position */
#define EMC_STATICWAITOEN2_WAITOEN_Msk                        (0x0fUL << EMC_STATICWAITOEN2_WAITOEN_Pos)                /*!< EMC STATICWAITOEN2: WAITOEN Mask    */

// ------------------------------------  EMC_STATICWAITRD2  ---------------------------------------
#define EMC_STATICWAITRD2_WAITRD_Pos                          0                                                         /*!< EMC STATICWAITRD2: WAITRD Position  */
#define EMC_STATICWAITRD2_WAITRD_Msk                          (0x1fUL << EMC_STATICWAITRD2_WAITRD_Pos)                  /*!< EMC STATICWAITRD2: WAITRD Mask      */

// -----------------------------------  EMC_STATICWAITPAG2  ---------------------------------------
#define EMC_STATICWAITPAG2_WAITPAGE_Pos                       0                                                         /*!< EMC STATICWAITPAG2: WAITPAGE Position */
#define EMC_STATICWAITPAG2_WAITPAGE_Msk                       (0x1fUL << EMC_STATICWAITPAG2_WAITPAGE_Pos)               /*!< EMC STATICWAITPAG2: WAITPAGE Mask   */

// ------------------------------------  EMC_STATICWAITWR2  ---------------------------------------
#define EMC_STATICWAITWR2_WAITWR_Pos                          0                                                         /*!< EMC STATICWAITWR2: WAITWR Position  */
#define EMC_STATICWAITWR2_WAITWR_Msk                          (0x1fUL << EMC_STATICWAITWR2_WAITWR_Pos)                  /*!< EMC STATICWAITWR2: WAITWR Mask      */

// -----------------------------------  EMC_STATICWAITTURN2  --------------------------------------
#define EMC_STATICWAITTURN2_WAITTURN_Pos                      0                                                         /*!< EMC STATICWAITTURN2: WAITTURN Position */
#define EMC_STATICWAITTURN2_WAITTURN_Msk                      (0x0fUL << EMC_STATICWAITTURN2_WAITTURN_Pos)              /*!< EMC STATICWAITTURN2: WAITTURN Mask  */

// ------------------------------------  EMC_STATICCONFIG3  ---------------------------------------
#define EMC_STATICCONFIG3_MW_Pos                              0                                                         /*!< EMC STATICCONFIG3: MW Position      */
#define EMC_STATICCONFIG3_MW_Msk                              (0x03UL << EMC_STATICCONFIG3_MW_Pos)                      /*!< EMC STATICCONFIG3: MW Mask          */
#define EMC_STATICCONFIG3_PM_Pos                              3                                                         /*!< EMC STATICCONFIG3: PM Position      */
#define EMC_STATICCONFIG3_PM_Msk                              (0x01UL << EMC_STATICCONFIG3_PM_Pos)                      /*!< EMC STATICCONFIG3: PM Mask          */
#define EMC_STATICCONFIG3_PC_Pos                              6                                                         /*!< EMC STATICCONFIG3: PC Position      */
#define EMC_STATICCONFIG3_PC_Msk                              (0x01UL << EMC_STATICCONFIG3_PC_Pos)                      /*!< EMC STATICCONFIG3: PC Mask          */
#define EMC_STATICCONFIG3_PB_Pos                              7                                                         /*!< EMC STATICCONFIG3: PB Position      */
#define EMC_STATICCONFIG3_PB_Msk                              (0x01UL << EMC_STATICCONFIG3_PB_Pos)                      /*!< EMC STATICCONFIG3: PB Mask          */
#define EMC_STATICCONFIG3_EW_Pos                              8                                                         /*!< EMC STATICCONFIG3: EW Position      */
#define EMC_STATICCONFIG3_EW_Msk                              (0x01UL << EMC_STATICCONFIG3_EW_Pos)                      /*!< EMC STATICCONFIG3: EW Mask          */
#define EMC_STATICCONFIG3_B_Pos                               19                                                        /*!< EMC STATICCONFIG3: B Position       */
#define EMC_STATICCONFIG3_B_Msk                               (0x01UL << EMC_STATICCONFIG3_B_Pos)                       /*!< EMC STATICCONFIG3: B Mask           */
#define EMC_STATICCONFIG3_P_Pos                               20                                                        /*!< EMC STATICCONFIG3: P Position       */
#define EMC_STATICCONFIG3_P_Msk                               (0x01UL << EMC_STATICCONFIG3_P_Pos)                       /*!< EMC STATICCONFIG3: P Mask           */

// -----------------------------------  EMC_STATICWAITWEN3  ---------------------------------------
#define EMC_STATICWAITWEN3_WAITWEN_Pos                        0                                                         /*!< EMC STATICWAITWEN3: WAITWEN Position */
#define EMC_STATICWAITWEN3_WAITWEN_Msk                        (0x0fUL << EMC_STATICWAITWEN3_WAITWEN_Pos)                /*!< EMC STATICWAITWEN3: WAITWEN Mask    */

// -----------------------------------  EMC_STATICWAITOEN3  ---------------------------------------
#define EMC_STATICWAITOEN3_WAITOEN_Pos                        0                                                         /*!< EMC STATICWAITOEN3: WAITOEN Position */
#define EMC_STATICWAITOEN3_WAITOEN_Msk                        (0x0fUL << EMC_STATICWAITOEN3_WAITOEN_Pos)                /*!< EMC STATICWAITOEN3: WAITOEN Mask    */

// ------------------------------------  EMC_STATICWAITRD3  ---------------------------------------
#define EMC_STATICWAITRD3_WAITRD_Pos                          0                                                         /*!< EMC STATICWAITRD3: WAITRD Position  */
#define EMC_STATICWAITRD3_WAITRD_Msk                          (0x1fUL << EMC_STATICWAITRD3_WAITRD_Pos)                  /*!< EMC STATICWAITRD3: WAITRD Mask      */

// -----------------------------------  EMC_STATICWAITPAG3  ---------------------------------------
#define EMC_STATICWAITPAG3_WAITPAGE_Pos                       0                                                         /*!< EMC STATICWAITPAG3: WAITPAGE Position */
#define EMC_STATICWAITPAG3_WAITPAGE_Msk                       (0x1fUL << EMC_STATICWAITPAG3_WAITPAGE_Pos)               /*!< EMC STATICWAITPAG3: WAITPAGE Mask   */

// ------------------------------------  EMC_STATICWAITWR3  ---------------------------------------
#define EMC_STATICWAITWR3_WAITWR_Pos                          0                                                         /*!< EMC STATICWAITWR3: WAITWR Position  */
#define EMC_STATICWAITWR3_WAITWR_Msk                          (0x1fUL << EMC_STATICWAITWR3_WAITWR_Pos)                  /*!< EMC STATICWAITWR3: WAITWR Mask      */

// -----------------------------------  EMC_STATICWAITTURN3  --------------------------------------
#define EMC_STATICWAITTURN3_WAITTURN_Pos                      0                                                         /*!< EMC STATICWAITTURN3: WAITTURN Position */
#define EMC_STATICWAITTURN3_WAITTURN_Msk                      (0x0fUL << EMC_STATICWAITTURN3_WAITTURN_Pos)              /*!< EMC STATICWAITTURN3: WAITTURN Mask  */


// ------------------------------------------------------------------------------------------------
// -----                                 USB0 Position & Mask                                 -----
// ------------------------------------------------------------------------------------------------


// -------------------------------------  USB0_CAPLENGTH  -----------------------------------------
#define USB0_CAPLENGTH_CAPLENGTH_Pos                          0                                                         /*!< USB0 CAPLENGTH: CAPLENGTH Position  */
#define USB0_CAPLENGTH_CAPLENGTH_Msk                          (0x000000ffUL << USB0_CAPLENGTH_CAPLENGTH_Pos)            /*!< USB0 CAPLENGTH: CAPLENGTH Mask      */
#define USB0_CAPLENGTH_HCIVERSION_Pos                         8                                                         /*!< USB0 CAPLENGTH: HCIVERSION Position */
#define USB0_CAPLENGTH_HCIVERSION_Msk                         (0x0000ffffUL << USB0_CAPLENGTH_HCIVERSION_Pos)           /*!< USB0 CAPLENGTH: HCIVERSION Mask     */

// -------------------------------------  USB0_HCSPARAMS  -----------------------------------------
#define USB0_HCSPARAMS_N_PORTS_Pos                            0                                                         /*!< USB0 HCSPARAMS: N_PORTS Position    */
#define USB0_HCSPARAMS_N_PORTS_Msk                            (0x0fUL << USB0_HCSPARAMS_N_PORTS_Pos)                    /*!< USB0 HCSPARAMS: N_PORTS Mask        */
#define USB0_HCSPARAMS_PPC_Pos                                4                                                         /*!< USB0 HCSPARAMS: PPC Position        */
#define USB0_HCSPARAMS_PPC_Msk                                (0x01UL << USB0_HCSPARAMS_PPC_Pos)                        /*!< USB0 HCSPARAMS: PPC Mask            */
#define USB0_HCSPARAMS_N_PCC_Pos                              8                                                         /*!< USB0 HCSPARAMS: N_PCC Position      */
#define USB0_HCSPARAMS_N_PCC_Msk                              (0x0fUL << USB0_HCSPARAMS_N_PCC_Pos)                      /*!< USB0 HCSPARAMS: N_PCC Mask          */
#define USB0_HCSPARAMS_N_CC_Pos                               12                                                        /*!< USB0 HCSPARAMS: N_CC Position       */
#define USB0_HCSPARAMS_N_CC_Msk                               (0x0fUL << USB0_HCSPARAMS_N_CC_Pos)                       /*!< USB0 HCSPARAMS: N_CC Mask           */
#define USB0_HCSPARAMS_PI_Pos                                 16                                                        /*!< USB0 HCSPARAMS: PI Position         */
#define USB0_HCSPARAMS_PI_Msk                                 (0x01UL << USB0_HCSPARAMS_PI_Pos)                         /*!< USB0 HCSPARAMS: PI Mask             */
#define USB0_HCSPARAMS_N_PTT_Pos                              20                                                        /*!< USB0 HCSPARAMS: N_PTT Position      */
#define USB0_HCSPARAMS_N_PTT_Msk                              (0x0fUL << USB0_HCSPARAMS_N_PTT_Pos)                      /*!< USB0 HCSPARAMS: N_PTT Mask          */
#define USB0_HCSPARAMS_N_TT_Pos                               24                                                        /*!< USB0 HCSPARAMS: N_TT Position       */
#define USB0_HCSPARAMS_N_TT_Msk                               (0x0fUL << USB0_HCSPARAMS_N_TT_Pos)                       /*!< USB0 HCSPARAMS: N_TT Mask           */

// -------------------------------------  USB0_HCCPARAMS  -----------------------------------------
#define USB0_HCCPARAMS_ADC_Pos                                0                                                         /*!< USB0 HCCPARAMS: ADC Position        */
#define USB0_HCCPARAMS_ADC_Msk                                (0x01UL << USB0_HCCPARAMS_ADC_Pos)                        /*!< USB0 HCCPARAMS: ADC Mask            */
#define USB0_HCCPARAMS_PFL_Pos                                1                                                         /*!< USB0 HCCPARAMS: PFL Position        */
#define USB0_HCCPARAMS_PFL_Msk                                (0x01UL << USB0_HCCPARAMS_PFL_Pos)                        /*!< USB0 HCCPARAMS: PFL Mask            */
#define USB0_HCCPARAMS_ASP_Pos                                2                                                         /*!< USB0 HCCPARAMS: ASP Position        */
#define USB0_HCCPARAMS_ASP_Msk                                (0x01UL << USB0_HCCPARAMS_ASP_Pos)                        /*!< USB0 HCCPARAMS: ASP Mask            */
#define USB0_HCCPARAMS_IST_Pos                                4                                                         /*!< USB0 HCCPARAMS: IST Position        */
#define USB0_HCCPARAMS_IST_Msk                                (0x0fUL << USB0_HCCPARAMS_IST_Pos)                        /*!< USB0 HCCPARAMS: IST Mask            */
#define USB0_HCCPARAMS_EECP_Pos                               8                                                         /*!< USB0 HCCPARAMS: EECP Position       */
#define USB0_HCCPARAMS_EECP_Msk                               (0x000000ffUL << USB0_HCCPARAMS_EECP_Pos)                 /*!< USB0 HCCPARAMS: EECP Mask           */

// -------------------------------------  USB0_DCIVERSION  ----------------------------------------
#define USB0_DCIVERSION_DCIVERSION_Pos                        0                                                         /*!< USB0 DCIVERSION: DCIVERSION Position */
#define USB0_DCIVERSION_DCIVERSION_Msk                        (0x0000ffffUL << USB0_DCIVERSION_DCIVERSION_Pos)          /*!< USB0 DCIVERSION: DCIVERSION Mask    */

// --------------------------------------  USB0_USBCMD_D  -----------------------------------------
#define USB0_USBCMD_D_RS_Pos                                  0                                                         /*!< USB0 USBCMD_D: RS Position          */
#define USB0_USBCMD_D_RS_Msk                                  (0x01UL << USB0_USBCMD_D_RS_Pos)                          /*!< USB0 USBCMD_D: RS Mask              */
#define USB0_USBCMD_D_RST_Pos                                 1                                                         /*!< USB0 USBCMD_D: RST Position         */
#define USB0_USBCMD_D_RST_Msk                                 (0x01UL << USB0_USBCMD_D_RST_Pos)                         /*!< USB0 USBCMD_D: RST Mask             */
#define USB0_USBCMD_D_SUTW_Pos                                13                                                        /*!< USB0 USBCMD_D: SUTW Position        */
#define USB0_USBCMD_D_SUTW_Msk                                (0x01UL << USB0_USBCMD_D_SUTW_Pos)                        /*!< USB0 USBCMD_D: SUTW Mask            */
#define USB0_USBCMD_D_ATDTW_Pos                               14                                                        /*!< USB0 USBCMD_D: ATDTW Position       */
#define USB0_USBCMD_D_ATDTW_Msk                               (0x01UL << USB0_USBCMD_D_ATDTW_Pos)                       /*!< USB0 USBCMD_D: ATDTW Mask           */
#define USB0_USBCMD_D_ITC_Pos                                 16                                                        /*!< USB0 USBCMD_D: ITC Position         */
#define USB0_USBCMD_D_ITC_Msk                                 (0x000000ffUL << USB0_USBCMD_D_ITC_Pos)                   /*!< USB0 USBCMD_D: ITC Mask             */

// --------------------------------------  USB0_USBCMD_H  -----------------------------------------
#define USB0_USBCMD_H_RS_Pos                                  0                                                         /*!< USB0 USBCMD_H: RS Position          */
#define USB0_USBCMD_H_RS_Msk                                  (0x01UL << USB0_USBCMD_H_RS_Pos)                          /*!< USB0 USBCMD_H: RS Mask              */
#define USB0_USBCMD_H_RST_Pos                                 1                                                         /*!< USB0 USBCMD_H: RST Position         */
#define USB0_USBCMD_H_RST_Msk                                 (0x01UL << USB0_USBCMD_H_RST_Pos)                         /*!< USB0 USBCMD_H: RST Mask             */
#define USB0_USBCMD_H_FS0_Pos                                 2                                                         /*!< USB0 USBCMD_H: FS0 Position         */
#define USB0_USBCMD_H_FS0_Msk                                 (0x01UL << USB0_USBCMD_H_FS0_Pos)                         /*!< USB0 USBCMD_H: FS0 Mask             */
#define USB0_USBCMD_H_FS1_Pos                                 3                                                         /*!< USB0 USBCMD_H: FS1 Position         */
#define USB0_USBCMD_H_FS1_Msk                                 (0x01UL << USB0_USBCMD_H_FS1_Pos)                         /*!< USB0 USBCMD_H: FS1 Mask             */
#define USB0_USBCMD_H_PSE_Pos                                 4                                                         /*!< USB0 USBCMD_H: PSE Position         */
#define USB0_USBCMD_H_PSE_Msk                                 (0x01UL << USB0_USBCMD_H_PSE_Pos)                         /*!< USB0 USBCMD_H: PSE Mask             */
#define USB0_USBCMD_H_ASE_Pos                                 5                                                         /*!< USB0 USBCMD_H: ASE Position         */
#define USB0_USBCMD_H_ASE_Msk                                 (0x01UL << USB0_USBCMD_H_ASE_Pos)                         /*!< USB0 USBCMD_H: ASE Mask             */
#define USB0_USBCMD_H_IAA_Pos                                 6                                                         /*!< USB0 USBCMD_H: IAA Position         */
#define USB0_USBCMD_H_IAA_Msk                                 (0x01UL << USB0_USBCMD_H_IAA_Pos)                         /*!< USB0 USBCMD_H: IAA Mask             */
#define USB0_USBCMD_H_ASP1_0_Pos                              8                                                         /*!< USB0 USBCMD_H: ASP1_0 Position      */
#define USB0_USBCMD_H_ASP1_0_Msk                              (0x03UL << USB0_USBCMD_H_ASP1_0_Pos)                      /*!< USB0 USBCMD_H: ASP1_0 Mask          */
#define USB0_USBCMD_H_ASPE_Pos                                11                                                        /*!< USB0 USBCMD_H: ASPE Position        */
#define USB0_USBCMD_H_ASPE_Msk                                (0x01UL << USB0_USBCMD_H_ASPE_Pos)                        /*!< USB0 USBCMD_H: ASPE Mask            */
#define USB0_USBCMD_H_FS2_Pos                                 15                                                        /*!< USB0 USBCMD_H: FS2 Position         */
#define USB0_USBCMD_H_FS2_Msk                                 (0x01UL << USB0_USBCMD_H_FS2_Pos)                         /*!< USB0 USBCMD_H: FS2 Mask             */
#define USB0_USBCMD_H_ITC_Pos                                 16                                                        /*!< USB0 USBCMD_H: ITC Position         */
#define USB0_USBCMD_H_ITC_Msk                                 (0x000000ffUL << USB0_USBCMD_H_ITC_Pos)                   /*!< USB0 USBCMD_H: ITC Mask             */

// --------------------------------------  USB0_USBSTS_D  -----------------------------------------
#define USB0_USBSTS_D_UI_Pos                                  0                                                         /*!< USB0 USBSTS_D: UI Position          */
#define USB0_USBSTS_D_UI_Msk                                  (0x01UL << USB0_USBSTS_D_UI_Pos)                          /*!< USB0 USBSTS_D: UI Mask              */
#define USB0_USBSTS_D_UEI_Pos                                 1                                                         /*!< USB0 USBSTS_D: UEI Position         */
#define USB0_USBSTS_D_UEI_Msk                                 (0x01UL << USB0_USBSTS_D_UEI_Pos)                         /*!< USB0 USBSTS_D: UEI Mask             */
#define USB0_USBSTS_D_PCI_Pos                                 2                                                         /*!< USB0 USBSTS_D: PCI Position         */
#define USB0_USBSTS_D_PCI_Msk                                 (0x01UL << USB0_USBSTS_D_PCI_Pos)                         /*!< USB0 USBSTS_D: PCI Mask             */
#define USB0_USBSTS_D_AAI_Pos                                 5                                                         /*!< USB0 USBSTS_D: AAI Position         */
#define USB0_USBSTS_D_AAI_Msk                                 (0x01UL << USB0_USBSTS_D_AAI_Pos)                         /*!< USB0 USBSTS_D: AAI Mask             */
#define USB0_USBSTS_D_URI_Pos                                 6                                                         /*!< USB0 USBSTS_D: URI Position         */
#define USB0_USBSTS_D_URI_Msk                                 (0x01UL << USB0_USBSTS_D_URI_Pos)                         /*!< USB0 USBSTS_D: URI Mask             */
#define USB0_USBSTS_D_SRI_Pos                                 7                                                         /*!< USB0 USBSTS_D: SRI Position         */
#define USB0_USBSTS_D_SRI_Msk                                 (0x01UL << USB0_USBSTS_D_SRI_Pos)                         /*!< USB0 USBSTS_D: SRI Mask             */
#define USB0_USBSTS_D_SLI_Pos                                 8                                                         /*!< USB0 USBSTS_D: SLI Position         */
#define USB0_USBSTS_D_SLI_Msk                                 (0x01UL << USB0_USBSTS_D_SLI_Pos)                         /*!< USB0 USBSTS_D: SLI Mask             */
#define USB0_USBSTS_D_NAKI_Pos                                16                                                        /*!< USB0 USBSTS_D: NAKI Position        */
#define USB0_USBSTS_D_NAKI_Msk                                (0x01UL << USB0_USBSTS_D_NAKI_Pos)                        /*!< USB0 USBSTS_D: NAKI Mask            */

// --------------------------------------  USB0_USBSTS_H  -----------------------------------------
#define USB0_USBSTS_H_UI_Pos                                  0                                                         /*!< USB0 USBSTS_H: UI Position          */
#define USB0_USBSTS_H_UI_Msk                                  (0x01UL << USB0_USBSTS_H_UI_Pos)                          /*!< USB0 USBSTS_H: UI Mask              */
#define USB0_USBSTS_H_UEI_Pos                                 1                                                         /*!< USB0 USBSTS_H: UEI Position         */
#define USB0_USBSTS_H_UEI_Msk                                 (0x01UL << USB0_USBSTS_H_UEI_Pos)                         /*!< USB0 USBSTS_H: UEI Mask             */
#define USB0_USBSTS_H_PCI_Pos                                 2                                                         /*!< USB0 USBSTS_H: PCI Position         */
#define USB0_USBSTS_H_PCI_Msk                                 (0x01UL << USB0_USBSTS_H_PCI_Pos)                         /*!< USB0 USBSTS_H: PCI Mask             */
#define USB0_USBSTS_H_FRI_Pos                                 3                                                         /*!< USB0 USBSTS_H: FRI Position         */
#define USB0_USBSTS_H_FRI_Msk                                 (0x01UL << USB0_USBSTS_H_FRI_Pos)                         /*!< USB0 USBSTS_H: FRI Mask             */
#define USB0_USBSTS_H_AAI_Pos                                 5                                                         /*!< USB0 USBSTS_H: AAI Position         */
#define USB0_USBSTS_H_AAI_Msk                                 (0x01UL << USB0_USBSTS_H_AAI_Pos)                         /*!< USB0 USBSTS_H: AAI Mask             */
#define USB0_USBSTS_H_SRI_Pos                                 7                                                         /*!< USB0 USBSTS_H: SRI Position         */
#define USB0_USBSTS_H_SRI_Msk                                 (0x01UL << USB0_USBSTS_H_SRI_Pos)                         /*!< USB0 USBSTS_H: SRI Mask             */
#define USB0_USBSTS_H_HCH_Pos                                 12                                                        /*!< USB0 USBSTS_H: HCH Position         */
#define USB0_USBSTS_H_HCH_Msk                                 (0x01UL << USB0_USBSTS_H_HCH_Pos)                         /*!< USB0 USBSTS_H: HCH Mask             */
#define USB0_USBSTS_H_RCL_Pos                                 13                                                        /*!< USB0 USBSTS_H: RCL Position         */
#define USB0_USBSTS_H_RCL_Msk                                 (0x01UL << USB0_USBSTS_H_RCL_Pos)                         /*!< USB0 USBSTS_H: RCL Mask             */
#define USB0_USBSTS_H_PS_Pos                                  14                                                        /*!< USB0 USBSTS_H: PS Position          */
#define USB0_USBSTS_H_PS_Msk                                  (0x01UL << USB0_USBSTS_H_PS_Pos)                          /*!< USB0 USBSTS_H: PS Mask              */
#define USB0_USBSTS_H_AS_Pos                                  15                                                        /*!< USB0 USBSTS_H: AS Position          */
#define USB0_USBSTS_H_AS_Msk                                  (0x01UL << USB0_USBSTS_H_AS_Pos)                          /*!< USB0 USBSTS_H: AS Mask              */
#define USB0_USBSTS_H_UAI_Pos                                 18                                                        /*!< USB0 USBSTS_H: UAI Position         */
#define USB0_USBSTS_H_UAI_Msk                                 (0x01UL << USB0_USBSTS_H_UAI_Pos)                         /*!< USB0 USBSTS_H: UAI Mask             */
#define USB0_USBSTS_H_UPI_Pos                                 19                                                        /*!< USB0 USBSTS_H: UPI Position         */
#define USB0_USBSTS_H_UPI_Msk                                 (0x01UL << USB0_USBSTS_H_UPI_Pos)                         /*!< USB0 USBSTS_H: UPI Mask             */

// -------------------------------------  USB0_USBINTR_D  -----------------------------------------
#define USB0_USBINTR_D_UE_Pos                                 0                                                         /*!< USB0 USBINTR_D: UE Position         */
#define USB0_USBINTR_D_UE_Msk                                 (0x01UL << USB0_USBINTR_D_UE_Pos)                         /*!< USB0 USBINTR_D: UE Mask             */
#define USB0_USBINTR_D_UEE_Pos                                1                                                         /*!< USB0 USBINTR_D: UEE Position        */
#define USB0_USBINTR_D_UEE_Msk                                (0x01UL << USB0_USBINTR_D_UEE_Pos)                        /*!< USB0 USBINTR_D: UEE Mask            */
#define USB0_USBINTR_D_PCE_Pos                                2                                                         /*!< USB0 USBINTR_D: PCE Position        */
#define USB0_USBINTR_D_PCE_Msk                                (0x01UL << USB0_USBINTR_D_PCE_Pos)                        /*!< USB0 USBINTR_D: PCE Mask            */
#define USB0_USBINTR_D_URE_Pos                                6                                                         /*!< USB0 USBINTR_D: URE Position        */
#define USB0_USBINTR_D_URE_Msk                                (0x01UL << USB0_USBINTR_D_URE_Pos)                        /*!< USB0 USBINTR_D: URE Mask            */
#define USB0_USBINTR_D_SRE_Pos                                7                                                         /*!< USB0 USBINTR_D: SRE Position        */
#define USB0_USBINTR_D_SRE_Msk                                (0x01UL << USB0_USBINTR_D_SRE_Pos)                        /*!< USB0 USBINTR_D: SRE Mask            */
#define USB0_USBINTR_D_SLE_Pos                                8                                                         /*!< USB0 USBINTR_D: SLE Position        */
#define USB0_USBINTR_D_SLE_Msk                                (0x01UL << USB0_USBINTR_D_SLE_Pos)                        /*!< USB0 USBINTR_D: SLE Mask            */
#define USB0_USBINTR_D_NAKE_Pos                               16                                                        /*!< USB0 USBINTR_D: NAKE Position       */
#define USB0_USBINTR_D_NAKE_Msk                               (0x01UL << USB0_USBINTR_D_NAKE_Pos)                       /*!< USB0 USBINTR_D: NAKE Mask           */

// -------------------------------------  USB0_USBINTR_H  -----------------------------------------
#define USB0_USBINTR_H_UE_Pos                                 0                                                         /*!< USB0 USBINTR_H: UE Position         */
#define USB0_USBINTR_H_UE_Msk                                 (0x01UL << USB0_USBINTR_H_UE_Pos)                         /*!< USB0 USBINTR_H: UE Mask             */
#define USB0_USBINTR_H_UEE_Pos                                1                                                         /*!< USB0 USBINTR_H: UEE Position        */
#define USB0_USBINTR_H_UEE_Msk                                (0x01UL << USB0_USBINTR_H_UEE_Pos)                        /*!< USB0 USBINTR_H: UEE Mask            */
#define USB0_USBINTR_H_PCE_Pos                                2                                                         /*!< USB0 USBINTR_H: PCE Position        */
#define USB0_USBINTR_H_PCE_Msk                                (0x01UL << USB0_USBINTR_H_PCE_Pos)                        /*!< USB0 USBINTR_H: PCE Mask            */
#define USB0_USBINTR_H_FRE_Pos                                3                                                         /*!< USB0 USBINTR_H: FRE Position        */
#define USB0_USBINTR_H_FRE_Msk                                (0x01UL << USB0_USBINTR_H_FRE_Pos)                        /*!< USB0 USBINTR_H: FRE Mask            */
#define USB0_USBINTR_H_AAE_Pos                                5                                                         /*!< USB0 USBINTR_H: AAE Position        */
#define USB0_USBINTR_H_AAE_Msk                                (0x01UL << USB0_USBINTR_H_AAE_Pos)                        /*!< USB0 USBINTR_H: AAE Mask            */
#define USB0_USBINTR_H_SRE_Pos                                7                                                         /*!< USB0 USBINTR_H: SRE Position        */
#define USB0_USBINTR_H_SRE_Msk                                (0x01UL << USB0_USBINTR_H_SRE_Pos)                        /*!< USB0 USBINTR_H: SRE Mask            */
#define USB0_USBINTR_H_UAIE_Pos                               18                                                        /*!< USB0 USBINTR_H: UAIE Position       */
#define USB0_USBINTR_H_UAIE_Msk                               (0x01UL << USB0_USBINTR_H_UAIE_Pos)                       /*!< USB0 USBINTR_H: UAIE Mask           */
#define USB0_USBINTR_H_UPIA_Pos                               19                                                        /*!< USB0 USBINTR_H: UPIA Position       */
#define USB0_USBINTR_H_UPIA_Msk                               (0x01UL << USB0_USBINTR_H_UPIA_Pos)                       /*!< USB0 USBINTR_H: UPIA Mask           */

// -------------------------------------  USB0_FRINDEX_D  -----------------------------------------
#define USB0_FRINDEX_D_FRINDEX2_0_Pos                         0                                                         /*!< USB0 FRINDEX_D: FRINDEX2_0 Position */
#define USB0_FRINDEX_D_FRINDEX2_0_Msk                         (0x07UL << USB0_FRINDEX_D_FRINDEX2_0_Pos)                 /*!< USB0 FRINDEX_D: FRINDEX2_0 Mask     */
#define USB0_FRINDEX_D_FRINDEX13_3_Pos                        3                                                         /*!< USB0 FRINDEX_D: FRINDEX13_3 Position */
#define USB0_FRINDEX_D_FRINDEX13_3_Msk                        (0x000007ffUL << USB0_FRINDEX_D_FRINDEX13_3_Pos)          /*!< USB0 FRINDEX_D: FRINDEX13_3 Mask    */

// -------------------------------------  USB0_FRINDEX_H  -----------------------------------------
#define USB0_FRINDEX_H_FRINDEX2_0_Pos                         0                                                         /*!< USB0 FRINDEX_H: FRINDEX2_0 Position */
#define USB0_FRINDEX_H_FRINDEX2_0_Msk                         (0x07UL << USB0_FRINDEX_H_FRINDEX2_0_Pos)                 /*!< USB0 FRINDEX_H: FRINDEX2_0 Mask     */
#define USB0_FRINDEX_H_FRINDEX12_3_Pos                        3                                                         /*!< USB0 FRINDEX_H: FRINDEX12_3 Position */
#define USB0_FRINDEX_H_FRINDEX12_3_Msk                        (0x000003ffUL << USB0_FRINDEX_H_FRINDEX12_3_Pos)          /*!< USB0 FRINDEX_H: FRINDEX12_3 Mask    */

// -------------------------------------  USB0_DEVICEADDR  ----------------------------------------
#define USB0_DEVICEADDR_USBADRA_Pos                           24                                                        /*!< USB0 DEVICEADDR: USBADRA Position   */
#define USB0_DEVICEADDR_USBADRA_Msk                           (0x01UL << USB0_DEVICEADDR_USBADRA_Pos)                   /*!< USB0 DEVICEADDR: USBADRA Mask       */
#define USB0_DEVICEADDR_USBADR_Pos                            25                                                        /*!< USB0 DEVICEADDR: USBADR Position    */
#define USB0_DEVICEADDR_USBADR_Msk                            (0x7fUL << USB0_DEVICEADDR_USBADR_Pos)                    /*!< USB0 DEVICEADDR: USBADR Mask        */

// ----------------------------------  USB0_PERIODICLISTBASE  -------------------------------------
#define USB0_PERIODICLISTBASE_PERBASE31_12_Pos                12                                                        /*!< USB0 PERIODICLISTBASE: PERBASE31_12 Position */
#define USB0_PERIODICLISTBASE_PERBASE31_12_Msk                (0x000fffffUL << USB0_PERIODICLISTBASE_PERBASE31_12_Pos)  /*!< USB0 PERIODICLISTBASE: PERBASE31_12 Mask */

// ----------------------------------  USB0_ENDPOINTLISTADDR  -------------------------------------
#define USB0_ENDPOINTLISTADDR_EPBASE31_11_Pos                 11                                                        /*!< USB0 ENDPOINTLISTADDR: EPBASE31_11 Position */
#define USB0_ENDPOINTLISTADDR_EPBASE31_11_Msk                 (0x001fffffUL << USB0_ENDPOINTLISTADDR_EPBASE31_11_Pos)   /*!< USB0 ENDPOINTLISTADDR: EPBASE31_11 Mask */

// -----------------------------------  USB0_ASYNCLISTADDR  ---------------------------------------
#define USB0_ASYNCLISTADDR_ASYBASE31_5_Pos                    5                                                         /*!< USB0 ASYNCLISTADDR: ASYBASE31_5 Position */
#define USB0_ASYNCLISTADDR_ASYBASE31_5_Msk                    (0x07ffffffUL << USB0_ASYNCLISTADDR_ASYBASE31_5_Pos)      /*!< USB0 ASYNCLISTADDR: ASYBASE31_5 Mask */

// ---------------------------------------  USB0_TTCTRL  ------------------------------------------
#define USB0_TTCTRL_TTHA_Pos                                  24                                                        /*!< USB0 TTCTRL: TTHA Position          */
#define USB0_TTCTRL_TTHA_Msk                                  (0x7fUL << USB0_TTCTRL_TTHA_Pos)                          /*!< USB0 TTCTRL: TTHA Mask              */

// -------------------------------------  USB0_BURSTSIZE  -----------------------------------------
#define USB0_BURSTSIZE_RXPBURST_Pos                           0                                                         /*!< USB0 BURSTSIZE: RXPBURST Position   */
#define USB0_BURSTSIZE_RXPBURST_Msk                           (0x000000ffUL << USB0_BURSTSIZE_RXPBURST_Pos)             /*!< USB0 BURSTSIZE: RXPBURST Mask       */
#define USB0_BURSTSIZE_TXPBURST_Pos                           8                                                         /*!< USB0 BURSTSIZE: TXPBURST Position   */
#define USB0_BURSTSIZE_TXPBURST_Msk                           (0x000000ffUL << USB0_BURSTSIZE_TXPBURST_Pos)             /*!< USB0 BURSTSIZE: TXPBURST Mask       */

// ------------------------------------  USB0_TXFILLTUNING  ---------------------------------------
#define USB0_TXFILLTUNING_TXSCHOH_Pos                         0                                                         /*!< USB0 TXFILLTUNING: TXSCHOH Position */
#define USB0_TXFILLTUNING_TXSCHOH_Msk                         (0x000000ffUL << USB0_TXFILLTUNING_TXSCHOH_Pos)           /*!< USB0 TXFILLTUNING: TXSCHOH Mask     */
#define USB0_TXFILLTUNING_TXSCHEATLTH_Pos                     8                                                         /*!< USB0 TXFILLTUNING: TXSCHEATLTH Position */
#define USB0_TXFILLTUNING_TXSCHEATLTH_Msk                     (0x1fUL << USB0_TXFILLTUNING_TXSCHEATLTH_Pos)             /*!< USB0 TXFILLTUNING: TXSCHEATLTH Mask */
#define USB0_TXFILLTUNING_TXFIFOTHRES_Pos                     16                                                        /*!< USB0 TXFILLTUNING: TXFIFOTHRES Position */
#define USB0_TXFILLTUNING_TXFIFOTHRES_Msk                     (0x3fUL << USB0_TXFILLTUNING_TXFIFOTHRES_Pos)             /*!< USB0 TXFILLTUNING: TXFIFOTHRES Mask */

// -------------------------------------  USB0_BINTERVAL  -----------------------------------------
#define USB0_BINTERVAL_BINT_Pos                               0                                                         /*!< USB0 BINTERVAL: BINT Position       */
#define USB0_BINTERVAL_BINT_Msk                               (0x0fUL << USB0_BINTERVAL_BINT_Pos)                       /*!< USB0 BINTERVAL: BINT Mask           */

// --------------------------------------  USB0_ENDPTNAK  -----------------------------------------
#define USB0_ENDPTNAK_EPRN0_Pos                               0                                                         /*!< USB0 ENDPTNAK: EPRN0 Position       */
#define USB0_ENDPTNAK_EPRN0_Msk                               (0x01UL << USB0_ENDPTNAK_EPRN0_Pos)                       /*!< USB0 ENDPTNAK: EPRN0 Mask           */
#define USB0_ENDPTNAK_EPRN1_Pos                               1                                                         /*!< USB0 ENDPTNAK: EPRN1 Position       */
#define USB0_ENDPTNAK_EPRN1_Msk                               (0x01UL << USB0_ENDPTNAK_EPRN1_Pos)                       /*!< USB0 ENDPTNAK: EPRN1 Mask           */
#define USB0_ENDPTNAK_EPRN2_Pos                               2                                                         /*!< USB0 ENDPTNAK: EPRN2 Position       */
#define USB0_ENDPTNAK_EPRN2_Msk                               (0x01UL << USB0_ENDPTNAK_EPRN2_Pos)                       /*!< USB0 ENDPTNAK: EPRN2 Mask           */
#define USB0_ENDPTNAK_EPRN3_Pos                               3                                                         /*!< USB0 ENDPTNAK: EPRN3 Position       */
#define USB0_ENDPTNAK_EPRN3_Msk                               (0x01UL << USB0_ENDPTNAK_EPRN3_Pos)                       /*!< USB0 ENDPTNAK: EPRN3 Mask           */
#define USB0_ENDPTNAK_EPRN4_Pos                               4                                                         /*!< USB0 ENDPTNAK: EPRN4 Position       */
#define USB0_ENDPTNAK_EPRN4_Msk                               (0x01UL << USB0_ENDPTNAK_EPRN4_Pos)                       /*!< USB0 ENDPTNAK: EPRN4 Mask           */
#define USB0_ENDPTNAK_EPRN5_Pos                               5                                                         /*!< USB0 ENDPTNAK: EPRN5 Position       */
#define USB0_ENDPTNAK_EPRN5_Msk                               (0x01UL << USB0_ENDPTNAK_EPRN5_Pos)                       /*!< USB0 ENDPTNAK: EPRN5 Mask           */
#define USB0_ENDPTNAK_EPTN0_Pos                               16                                                        /*!< USB0 ENDPTNAK: EPTN0 Position       */
#define USB0_ENDPTNAK_EPTN0_Msk                               (0x01UL << USB0_ENDPTNAK_EPTN0_Pos)                       /*!< USB0 ENDPTNAK: EPTN0 Mask           */
#define USB0_ENDPTNAK_EPTN1_Pos                               17                                                        /*!< USB0 ENDPTNAK: EPTN1 Position       */
#define USB0_ENDPTNAK_EPTN1_Msk                               (0x01UL << USB0_ENDPTNAK_EPTN1_Pos)                       /*!< USB0 ENDPTNAK: EPTN1 Mask           */
#define USB0_ENDPTNAK_EPTN2_Pos                               18                                                        /*!< USB0 ENDPTNAK: EPTN2 Position       */
#define USB0_ENDPTNAK_EPTN2_Msk                               (0x01UL << USB0_ENDPTNAK_EPTN2_Pos)                       /*!< USB0 ENDPTNAK: EPTN2 Mask           */
#define USB0_ENDPTNAK_EPTN3_Pos                               19                                                        /*!< USB0 ENDPTNAK: EPTN3 Position       */
#define USB0_ENDPTNAK_EPTN3_Msk                               (0x01UL << USB0_ENDPTNAK_EPTN3_Pos)                       /*!< USB0 ENDPTNAK: EPTN3 Mask           */
#define USB0_ENDPTNAK_EPTN4_Pos                               20                                                        /*!< USB0 ENDPTNAK: EPTN4 Position       */
#define USB0_ENDPTNAK_EPTN4_Msk                               (0x01UL << USB0_ENDPTNAK_EPTN4_Pos)                       /*!< USB0 ENDPTNAK: EPTN4 Mask           */
#define USB0_ENDPTNAK_EPTN5_Pos                               21                                                        /*!< USB0 ENDPTNAK: EPTN5 Position       */
#define USB0_ENDPTNAK_EPTN5_Msk                               (0x01UL << USB0_ENDPTNAK_EPTN5_Pos)                       /*!< USB0 ENDPTNAK: EPTN5 Mask           */

// -------------------------------------  USB0_ENDPTNAKEN  ----------------------------------------
#define USB0_ENDPTNAKEN_EPRNE0_Pos                            0                                                         /*!< USB0 ENDPTNAKEN: EPRNE0 Position    */
#define USB0_ENDPTNAKEN_EPRNE0_Msk                            (0x01UL << USB0_ENDPTNAKEN_EPRNE0_Pos)                    /*!< USB0 ENDPTNAKEN: EPRNE0 Mask        */
#define USB0_ENDPTNAKEN_EPRNE1_Pos                            1                                                         /*!< USB0 ENDPTNAKEN: EPRNE1 Position    */
#define USB0_ENDPTNAKEN_EPRNE1_Msk                            (0x01UL << USB0_ENDPTNAKEN_EPRNE1_Pos)                    /*!< USB0 ENDPTNAKEN: EPRNE1 Mask        */
#define USB0_ENDPTNAKEN_EPRNE2_Pos                            2                                                         /*!< USB0 ENDPTNAKEN: EPRNE2 Position    */
#define USB0_ENDPTNAKEN_EPRNE2_Msk                            (0x01UL << USB0_ENDPTNAKEN_EPRNE2_Pos)                    /*!< USB0 ENDPTNAKEN: EPRNE2 Mask        */
#define USB0_ENDPTNAKEN_EPRNE3_Pos                            3                                                         /*!< USB0 ENDPTNAKEN: EPRNE3 Position    */
#define USB0_ENDPTNAKEN_EPRNE3_Msk                            (0x01UL << USB0_ENDPTNAKEN_EPRNE3_Pos)                    /*!< USB0 ENDPTNAKEN: EPRNE3 Mask        */
#define USB0_ENDPTNAKEN_EPRNE4_Pos                            4                                                         /*!< USB0 ENDPTNAKEN: EPRNE4 Position    */
#define USB0_ENDPTNAKEN_EPRNE4_Msk                            (0x01UL << USB0_ENDPTNAKEN_EPRNE4_Pos)                    /*!< USB0 ENDPTNAKEN: EPRNE4 Mask        */
#define USB0_ENDPTNAKEN_EPRNE5_Pos                            5                                                         /*!< USB0 ENDPTNAKEN: EPRNE5 Position    */
#define USB0_ENDPTNAKEN_EPRNE5_Msk                            (0x01UL << USB0_ENDPTNAKEN_EPRNE5_Pos)                    /*!< USB0 ENDPTNAKEN: EPRNE5 Mask        */
#define USB0_ENDPTNAKEN_EPTNE0_Pos                            16                                                        /*!< USB0 ENDPTNAKEN: EPTNE0 Position    */
#define USB0_ENDPTNAKEN_EPTNE0_Msk                            (0x01UL << USB0_ENDPTNAKEN_EPTNE0_Pos)                    /*!< USB0 ENDPTNAKEN: EPTNE0 Mask        */
#define USB0_ENDPTNAKEN_EPTNE1_Pos                            17                                                        /*!< USB0 ENDPTNAKEN: EPTNE1 Position    */
#define USB0_ENDPTNAKEN_EPTNE1_Msk                            (0x01UL << USB0_ENDPTNAKEN_EPTNE1_Pos)                    /*!< USB0 ENDPTNAKEN: EPTNE1 Mask        */
#define USB0_ENDPTNAKEN_EPTNE2_Pos                            18                                                        /*!< USB0 ENDPTNAKEN: EPTNE2 Position    */
#define USB0_ENDPTNAKEN_EPTNE2_Msk                            (0x01UL << USB0_ENDPTNAKEN_EPTNE2_Pos)                    /*!< USB0 ENDPTNAKEN: EPTNE2 Mask        */
#define USB0_ENDPTNAKEN_EPTNE3_Pos                            19                                                        /*!< USB0 ENDPTNAKEN: EPTNE3 Position    */
#define USB0_ENDPTNAKEN_EPTNE3_Msk                            (0x01UL << USB0_ENDPTNAKEN_EPTNE3_Pos)                    /*!< USB0 ENDPTNAKEN: EPTNE3 Mask        */
#define USB0_ENDPTNAKEN_EPTNE4_Pos                            20                                                        /*!< USB0 ENDPTNAKEN: EPTNE4 Position    */
#define USB0_ENDPTNAKEN_EPTNE4_Msk                            (0x01UL << USB0_ENDPTNAKEN_EPTNE4_Pos)                    /*!< USB0 ENDPTNAKEN: EPTNE4 Mask        */
#define USB0_ENDPTNAKEN_EPTNE5_Pos                            21                                                        /*!< USB0 ENDPTNAKEN: EPTNE5 Position    */
#define USB0_ENDPTNAKEN_EPTNE5_Msk                            (0x01UL << USB0_ENDPTNAKEN_EPTNE5_Pos)                    /*!< USB0 ENDPTNAKEN: EPTNE5 Mask        */

// -------------------------------------  USB0_PORTSC1_D  -----------------------------------------
#define USB0_PORTSC1_D_CCS_Pos                                0                                                         /*!< USB0 PORTSC1_D: CCS Position        */
#define USB0_PORTSC1_D_CCS_Msk                                (0x01UL << USB0_PORTSC1_D_CCS_Pos)                        /*!< USB0 PORTSC1_D: CCS Mask            */
#define USB0_PORTSC1_D_PE_Pos                                 2                                                         /*!< USB0 PORTSC1_D: PE Position         */
#define USB0_PORTSC1_D_PE_Msk                                 (0x01UL << USB0_PORTSC1_D_PE_Pos)                         /*!< USB0 PORTSC1_D: PE Mask             */
#define USB0_PORTSC1_D_PEC_Pos                                3                                                         /*!< USB0 PORTSC1_D: PEC Position        */
#define USB0_PORTSC1_D_PEC_Msk                                (0x01UL << USB0_PORTSC1_D_PEC_Pos)                        /*!< USB0 PORTSC1_D: PEC Mask            */
#define USB0_PORTSC1_D_FPR_Pos                                6                                                         /*!< USB0 PORTSC1_D: FPR Position        */
#define USB0_PORTSC1_D_FPR_Msk                                (0x01UL << USB0_PORTSC1_D_FPR_Pos)                        /*!< USB0 PORTSC1_D: FPR Mask            */
#define USB0_PORTSC1_D_SUSP_Pos                               7                                                         /*!< USB0 PORTSC1_D: SUSP Position       */
#define USB0_PORTSC1_D_SUSP_Msk                               (0x01UL << USB0_PORTSC1_D_SUSP_Pos)                       /*!< USB0 PORTSC1_D: SUSP Mask           */
#define USB0_PORTSC1_D_PR_Pos                                 8                                                         /*!< USB0 PORTSC1_D: PR Position         */
#define USB0_PORTSC1_D_PR_Msk                                 (0x01UL << USB0_PORTSC1_D_PR_Pos)                         /*!< USB0 PORTSC1_D: PR Mask             */
#define USB0_PORTSC1_D_HSP_Pos                                9                                                         /*!< USB0 PORTSC1_D: HSP Position        */
#define USB0_PORTSC1_D_HSP_Msk                                (0x01UL << USB0_PORTSC1_D_HSP_Pos)                        /*!< USB0 PORTSC1_D: HSP Mask            */
#define USB0_PORTSC1_D_PIC1_0_Pos                             14                                                        /*!< USB0 PORTSC1_D: PIC1_0 Position     */
#define USB0_PORTSC1_D_PIC1_0_Msk                             (0x03UL << USB0_PORTSC1_D_PIC1_0_Pos)                     /*!< USB0 PORTSC1_D: PIC1_0 Mask         */
#define USB0_PORTSC1_D_PTC3_0_Pos                             16                                                        /*!< USB0 PORTSC1_D: PTC3_0 Position     */
#define USB0_PORTSC1_D_PTC3_0_Msk                             (0x0fUL << USB0_PORTSC1_D_PTC3_0_Pos)                     /*!< USB0 PORTSC1_D: PTC3_0 Mask         */
#define USB0_PORTSC1_D_PHCD_Pos                               23                                                        /*!< USB0 PORTSC1_D: PHCD Position       */
#define USB0_PORTSC1_D_PHCD_Msk                               (0x01UL << USB0_PORTSC1_D_PHCD_Pos)                       /*!< USB0 PORTSC1_D: PHCD Mask           */
#define USB0_PORTSC1_D_PFSC_Pos                               24                                                        /*!< USB0 PORTSC1_D: PFSC Position       */
#define USB0_PORTSC1_D_PFSC_Msk                               (0x01UL << USB0_PORTSC1_D_PFSC_Pos)                       /*!< USB0 PORTSC1_D: PFSC Mask           */
#define USB0_PORTSC1_D_PSPD_Pos                               26                                                        /*!< USB0 PORTSC1_D: PSPD Position       */
#define USB0_PORTSC1_D_PSPD_Msk                               (0x03UL << USB0_PORTSC1_D_PSPD_Pos)                       /*!< USB0 PORTSC1_D: PSPD Mask           */

// -------------------------------------  USB0_PORTSC1_H  -----------------------------------------
#define USB0_PORTSC1_H_CCS_Pos                                0                                                         /*!< USB0 PORTSC1_H: CCS Position        */
#define USB0_PORTSC1_H_CCS_Msk                                (0x01UL << USB0_PORTSC1_H_CCS_Pos)                        /*!< USB0 PORTSC1_H: CCS Mask            */
#define USB0_PORTSC1_H_CSC_Pos                                1                                                         /*!< USB0 PORTSC1_H: CSC Position        */
#define USB0_PORTSC1_H_CSC_Msk                                (0x01UL << USB0_PORTSC1_H_CSC_Pos)                        /*!< USB0 PORTSC1_H: CSC Mask            */
#define USB0_PORTSC1_H_PE_Pos                                 2                                                         /*!< USB0 PORTSC1_H: PE Position         */
#define USB0_PORTSC1_H_PE_Msk                                 (0x01UL << USB0_PORTSC1_H_PE_Pos)                         /*!< USB0 PORTSC1_H: PE Mask             */
#define USB0_PORTSC1_H_PEC_Pos                                3                                                         /*!< USB0 PORTSC1_H: PEC Position        */
#define USB0_PORTSC1_H_PEC_Msk                                (0x01UL << USB0_PORTSC1_H_PEC_Pos)                        /*!< USB0 PORTSC1_H: PEC Mask            */
#define USB0_PORTSC1_H_OCA_Pos                                4                                                         /*!< USB0 PORTSC1_H: OCA Position        */
#define USB0_PORTSC1_H_OCA_Msk                                (0x01UL << USB0_PORTSC1_H_OCA_Pos)                        /*!< USB0 PORTSC1_H: OCA Mask            */
#define USB0_PORTSC1_H_OCC_Pos                                5                                                         /*!< USB0 PORTSC1_H: OCC Position        */
#define USB0_PORTSC1_H_OCC_Msk                                (0x01UL << USB0_PORTSC1_H_OCC_Pos)                        /*!< USB0 PORTSC1_H: OCC Mask            */
#define USB0_PORTSC1_H_FPR_Pos                                6                                                         /*!< USB0 PORTSC1_H: FPR Position        */
#define USB0_PORTSC1_H_FPR_Msk                                (0x01UL << USB0_PORTSC1_H_FPR_Pos)                        /*!< USB0 PORTSC1_H: FPR Mask            */
#define USB0_PORTSC1_H_SUSP_Pos                               7                                                         /*!< USB0 PORTSC1_H: SUSP Position       */
#define USB0_PORTSC1_H_SUSP_Msk                               (0x01UL << USB0_PORTSC1_H_SUSP_Pos)                       /*!< USB0 PORTSC1_H: SUSP Mask           */
#define USB0_PORTSC1_H_PR_Pos                                 8                                                         /*!< USB0 PORTSC1_H: PR Position         */
#define USB0_PORTSC1_H_PR_Msk                                 (0x01UL << USB0_PORTSC1_H_PR_Pos)                         /*!< USB0 PORTSC1_H: PR Mask             */
#define USB0_PORTSC1_H_HSP_Pos                                9                                                         /*!< USB0 PORTSC1_H: HSP Position        */
#define USB0_PORTSC1_H_HSP_Msk                                (0x01UL << USB0_PORTSC1_H_HSP_Pos)                        /*!< USB0 PORTSC1_H: HSP Mask            */
#define USB0_PORTSC1_H_LS_Pos                                 10                                                        /*!< USB0 PORTSC1_H: LS Position         */
#define USB0_PORTSC1_H_LS_Msk                                 (0x03UL << USB0_PORTSC1_H_LS_Pos)                         /*!< USB0 PORTSC1_H: LS Mask             */
#define USB0_PORTSC1_H_PP_Pos                                 12                                                        /*!< USB0 PORTSC1_H: PP Position         */
#define USB0_PORTSC1_H_PP_Msk                                 (0x01UL << USB0_PORTSC1_H_PP_Pos)                         /*!< USB0 PORTSC1_H: PP Mask             */
#define USB0_PORTSC1_H_PIC1_0_Pos                             14                                                        /*!< USB0 PORTSC1_H: PIC1_0 Position     */
#define USB0_PORTSC1_H_PIC1_0_Msk                             (0x03UL << USB0_PORTSC1_H_PIC1_0_Pos)                     /*!< USB0 PORTSC1_H: PIC1_0 Mask         */
#define USB0_PORTSC1_H_PTC3_0_Pos                             16                                                        /*!< USB0 PORTSC1_H: PTC3_0 Position     */
#define USB0_PORTSC1_H_PTC3_0_Msk                             (0x0fUL << USB0_PORTSC1_H_PTC3_0_Pos)                     /*!< USB0 PORTSC1_H: PTC3_0 Mask         */
#define USB0_PORTSC1_H_WKCN_Pos                               20                                                        /*!< USB0 PORTSC1_H: WKCN Position       */
#define USB0_PORTSC1_H_WKCN_Msk                               (0x01UL << USB0_PORTSC1_H_WKCN_Pos)                       /*!< USB0 PORTSC1_H: WKCN Mask           */
#define USB0_PORTSC1_H_WKDC_Pos                               21                                                        /*!< USB0 PORTSC1_H: WKDC Position       */
#define USB0_PORTSC1_H_WKDC_Msk                               (0x01UL << USB0_PORTSC1_H_WKDC_Pos)                       /*!< USB0 PORTSC1_H: WKDC Mask           */
#define USB0_PORTSC1_H_WKOC_Pos                               22                                                        /*!< USB0 PORTSC1_H: WKOC Position       */
#define USB0_PORTSC1_H_WKOC_Msk                               (0x01UL << USB0_PORTSC1_H_WKOC_Pos)                       /*!< USB0 PORTSC1_H: WKOC Mask           */
#define USB0_PORTSC1_H_PHCD_Pos                               23                                                        /*!< USB0 PORTSC1_H: PHCD Position       */
#define USB0_PORTSC1_H_PHCD_Msk                               (0x01UL << USB0_PORTSC1_H_PHCD_Pos)                       /*!< USB0 PORTSC1_H: PHCD Mask           */
#define USB0_PORTSC1_H_PFSC_Pos                               24                                                        /*!< USB0 PORTSC1_H: PFSC Position       */
#define USB0_PORTSC1_H_PFSC_Msk                               (0x01UL << USB0_PORTSC1_H_PFSC_Pos)                       /*!< USB0 PORTSC1_H: PFSC Mask           */
#define USB0_PORTSC1_H_PSPD_Pos                               26                                                        /*!< USB0 PORTSC1_H: PSPD Position       */
#define USB0_PORTSC1_H_PSPD_Msk                               (0x03UL << USB0_PORTSC1_H_PSPD_Pos)                       /*!< USB0 PORTSC1_H: PSPD Mask           */

// ---------------------------------------  USB0_OTGSC  -------------------------------------------
#define USB0_OTGSC_VD_Pos                                     0                                                         /*!< USB0 OTGSC: VD Position             */
#define USB0_OTGSC_VD_Msk                                     (0x01UL << USB0_OTGSC_VD_Pos)                             /*!< USB0 OTGSC: VD Mask                 */
#define USB0_OTGSC_VC_Pos                                     1                                                         /*!< USB0 OTGSC: VC Position             */
#define USB0_OTGSC_VC_Msk                                     (0x01UL << USB0_OTGSC_VC_Pos)                             /*!< USB0 OTGSC: VC Mask                 */
#define USB0_OTGSC_HAAR_Pos                                   2                                                         /*!< USB0 OTGSC: HAAR Position           */
#define USB0_OTGSC_HAAR_Msk                                   (0x01UL << USB0_OTGSC_HAAR_Pos)                           /*!< USB0 OTGSC: HAAR Mask               */
#define USB0_OTGSC_OT_Pos                                     3                                                         /*!< USB0 OTGSC: OT Position             */
#define USB0_OTGSC_OT_Msk                                     (0x01UL << USB0_OTGSC_OT_Pos)                             /*!< USB0 OTGSC: OT Mask                 */
#define USB0_OTGSC_DP_Pos                                     4                                                         /*!< USB0 OTGSC: DP Position             */
#define USB0_OTGSC_DP_Msk                                     (0x01UL << USB0_OTGSC_DP_Pos)                             /*!< USB0 OTGSC: DP Mask                 */
#define USB0_OTGSC_IDPU_Pos                                   5                                                         /*!< USB0 OTGSC: IDPU Position           */
#define USB0_OTGSC_IDPU_Msk                                   (0x01UL << USB0_OTGSC_IDPU_Pos)                           /*!< USB0 OTGSC: IDPU Mask               */
#define USB0_OTGSC_HADP_Pos                                   6                                                         /*!< USB0 OTGSC: HADP Position           */
#define USB0_OTGSC_HADP_Msk                                   (0x01UL << USB0_OTGSC_HADP_Pos)                           /*!< USB0 OTGSC: HADP Mask               */
#define USB0_OTGSC_HABA_Pos                                   7                                                         /*!< USB0 OTGSC: HABA Position           */
#define USB0_OTGSC_HABA_Msk                                   (0x01UL << USB0_OTGSC_HABA_Pos)                           /*!< USB0 OTGSC: HABA Mask               */
#define USB0_OTGSC_ID_Pos                                     8                                                         /*!< USB0 OTGSC: ID Position             */
#define USB0_OTGSC_ID_Msk                                     (0x01UL << USB0_OTGSC_ID_Pos)                             /*!< USB0 OTGSC: ID Mask                 */
#define USB0_OTGSC_AVV_Pos                                    9                                                         /*!< USB0 OTGSC: AVV Position            */
#define USB0_OTGSC_AVV_Msk                                    (0x01UL << USB0_OTGSC_AVV_Pos)                            /*!< USB0 OTGSC: AVV Mask                */
#define USB0_OTGSC_ASV_Pos                                    10                                                        /*!< USB0 OTGSC: ASV Position            */
#define USB0_OTGSC_ASV_Msk                                    (0x01UL << USB0_OTGSC_ASV_Pos)                            /*!< USB0 OTGSC: ASV Mask                */
#define USB0_OTGSC_BSV_Pos                                    11                                                        /*!< USB0 OTGSC: BSV Position            */
#define USB0_OTGSC_BSV_Msk                                    (0x01UL << USB0_OTGSC_BSV_Pos)                            /*!< USB0 OTGSC: BSV Mask                */
#define USB0_OTGSC_BSE_Pos                                    12                                                        /*!< USB0 OTGSC: BSE Position            */
#define USB0_OTGSC_BSE_Msk                                    (0x01UL << USB0_OTGSC_BSE_Pos)                            /*!< USB0 OTGSC: BSE Mask                */
#define USB0_OTGSC_MS1T_Pos                                   13                                                        /*!< USB0 OTGSC: MS1T Position           */
#define USB0_OTGSC_MS1T_Msk                                   (0x01UL << USB0_OTGSC_MS1T_Pos)                           /*!< USB0 OTGSC: MS1T Mask               */
#define USB0_OTGSC_DPS_Pos                                    14                                                        /*!< USB0 OTGSC: DPS Position            */
#define USB0_OTGSC_DPS_Msk                                    (0x01UL << USB0_OTGSC_DPS_Pos)                            /*!< USB0 OTGSC: DPS Mask                */
#define USB0_OTGSC_IDIS_Pos                                   16                                                        /*!< USB0 OTGSC: IDIS Position           */
#define USB0_OTGSC_IDIS_Msk                                   (0x01UL << USB0_OTGSC_IDIS_Pos)                           /*!< USB0 OTGSC: IDIS Mask               */
#define USB0_OTGSC_AVVIS_Pos                                  17                                                        /*!< USB0 OTGSC: AVVIS Position          */
#define USB0_OTGSC_AVVIS_Msk                                  (0x01UL << USB0_OTGSC_AVVIS_Pos)                          /*!< USB0 OTGSC: AVVIS Mask              */
#define USB0_OTGSC_ASVIS_Pos                                  18                                                        /*!< USB0 OTGSC: ASVIS Position          */
#define USB0_OTGSC_ASVIS_Msk                                  (0x01UL << USB0_OTGSC_ASVIS_Pos)                          /*!< USB0 OTGSC: ASVIS Mask              */
#define USB0_OTGSC_BSVIS_Pos                                  19                                                        /*!< USB0 OTGSC: BSVIS Position          */
#define USB0_OTGSC_BSVIS_Msk                                  (0x01UL << USB0_OTGSC_BSVIS_Pos)                          /*!< USB0 OTGSC: BSVIS Mask              */
#define USB0_OTGSC_BSEIS_Pos                                  20                                                        /*!< USB0 OTGSC: BSEIS Position          */
#define USB0_OTGSC_BSEIS_Msk                                  (0x01UL << USB0_OTGSC_BSEIS_Pos)                          /*!< USB0 OTGSC: BSEIS Mask              */
#define USB0_OTGSC_ms1S_Pos                                   21                                                        /*!< USB0 OTGSC: ms1S Position           */
#define USB0_OTGSC_ms1S_Msk                                   (0x01UL << USB0_OTGSC_ms1S_Pos)                           /*!< USB0 OTGSC: ms1S Mask               */
#define USB0_OTGSC_DPIS_Pos                                   22                                                        /*!< USB0 OTGSC: DPIS Position           */
#define USB0_OTGSC_DPIS_Msk                                   (0x01UL << USB0_OTGSC_DPIS_Pos)                           /*!< USB0 OTGSC: DPIS Mask               */
#define USB0_OTGSC_IDIE_Pos                                   24                                                        /*!< USB0 OTGSC: IDIE Position           */
#define USB0_OTGSC_IDIE_Msk                                   (0x01UL << USB0_OTGSC_IDIE_Pos)                           /*!< USB0 OTGSC: IDIE Mask               */
#define USB0_OTGSC_AVVIE_Pos                                  25                                                        /*!< USB0 OTGSC: AVVIE Position          */
#define USB0_OTGSC_AVVIE_Msk                                  (0x01UL << USB0_OTGSC_AVVIE_Pos)                          /*!< USB0 OTGSC: AVVIE Mask              */
#define USB0_OTGSC_ASVIE_Pos                                  26                                                        /*!< USB0 OTGSC: ASVIE Position          */
#define USB0_OTGSC_ASVIE_Msk                                  (0x01UL << USB0_OTGSC_ASVIE_Pos)                          /*!< USB0 OTGSC: ASVIE Mask              */
#define USB0_OTGSC_BSVIE_Pos                                  27                                                        /*!< USB0 OTGSC: BSVIE Position          */
#define USB0_OTGSC_BSVIE_Msk                                  (0x01UL << USB0_OTGSC_BSVIE_Pos)                          /*!< USB0 OTGSC: BSVIE Mask              */
#define USB0_OTGSC_BSEIE_Pos                                  28                                                        /*!< USB0 OTGSC: BSEIE Position          */
#define USB0_OTGSC_BSEIE_Msk                                  (0x01UL << USB0_OTGSC_BSEIE_Pos)                          /*!< USB0 OTGSC: BSEIE Mask              */
#define USB0_OTGSC_MS1E_Pos                                   29                                                        /*!< USB0 OTGSC: MS1E Position           */
#define USB0_OTGSC_MS1E_Msk                                   (0x01UL << USB0_OTGSC_MS1E_Pos)                           /*!< USB0 OTGSC: MS1E Mask               */
#define USB0_OTGSC_DPIE_Pos                                   30                                                        /*!< USB0 OTGSC: DPIE Position           */
#define USB0_OTGSC_DPIE_Msk                                   (0x01UL << USB0_OTGSC_DPIE_Pos)                           /*!< USB0 OTGSC: DPIE Mask               */

// -------------------------------------  USB0_USBMODE_D  -----------------------------------------
#define USB0_USBMODE_D_CM1_0_Pos                              0                                                         /*!< USB0 USBMODE_D: CM1_0 Position      */
#define USB0_USBMODE_D_CM1_0_Msk                              (0x03UL << USB0_USBMODE_D_CM1_0_Pos)                      /*!< USB0 USBMODE_D: CM1_0 Mask          */
#define USB0_USBMODE_D_ES_Pos                                 2                                                         /*!< USB0 USBMODE_D: ES Position         */
#define USB0_USBMODE_D_ES_Msk                                 (0x01UL << USB0_USBMODE_D_ES_Pos)                         /*!< USB0 USBMODE_D: ES Mask             */
#define USB0_USBMODE_D_SLOM_Pos                               3                                                         /*!< USB0 USBMODE_D: SLOM Position       */
#define USB0_USBMODE_D_SLOM_Msk                               (0x01UL << USB0_USBMODE_D_SLOM_Pos)                       /*!< USB0 USBMODE_D: SLOM Mask           */
#define USB0_USBMODE_D_SDIS_Pos                               4                                                         /*!< USB0 USBMODE_D: SDIS Position       */
#define USB0_USBMODE_D_SDIS_Msk                               (0x01UL << USB0_USBMODE_D_SDIS_Pos)                       /*!< USB0 USBMODE_D: SDIS Mask           */

// -------------------------------------  USB0_USBMODE_H  -----------------------------------------
#define USB0_USBMODE_H_CM_Pos                                 0                                                         /*!< USB0 USBMODE_H: CM Position         */
#define USB0_USBMODE_H_CM_Msk                                 (0x03UL << USB0_USBMODE_H_CM_Pos)                         /*!< USB0 USBMODE_H: CM Mask             */
#define USB0_USBMODE_H_ES_Pos                                 2                                                         /*!< USB0 USBMODE_H: ES Position         */
#define USB0_USBMODE_H_ES_Msk                                 (0x01UL << USB0_USBMODE_H_ES_Pos)                         /*!< USB0 USBMODE_H: ES Mask             */
#define USB0_USBMODE_H_SDIS_Pos                               4                                                         /*!< USB0 USBMODE_H: SDIS Position       */
#define USB0_USBMODE_H_SDIS_Msk                               (0x01UL << USB0_USBMODE_H_SDIS_Pos)                       /*!< USB0 USBMODE_H: SDIS Mask           */
#define USB0_USBMODE_H_VBPS_Pos                               5                                                         /*!< USB0 USBMODE_H: VBPS Position       */
#define USB0_USBMODE_H_VBPS_Msk                               (0x01UL << USB0_USBMODE_H_VBPS_Pos)                       /*!< USB0 USBMODE_H: VBPS Mask           */

// -----------------------------------  USB0_ENDPTSETUPSTAT  --------------------------------------
#define USB0_ENDPTSETUPSTAT_ENDPTSETUPSTAT0_Pos               0                                                         /*!< USB0 ENDPTSETUPSTAT: ENDPTSETUPSTAT0 Position */
#define USB0_ENDPTSETUPSTAT_ENDPTSETUPSTAT0_Msk               (0x01UL << USB0_ENDPTSETUPSTAT_ENDPTSETUPSTAT0_Pos)       /*!< USB0 ENDPTSETUPSTAT: ENDPTSETUPSTAT0 Mask */
#define USB0_ENDPTSETUPSTAT_ENDPTSETUPSTAT1_Pos               1                                                         /*!< USB0 ENDPTSETUPSTAT: ENDPTSETUPSTAT1 Position */
#define USB0_ENDPTSETUPSTAT_ENDPTSETUPSTAT1_Msk               (0x01UL << USB0_ENDPTSETUPSTAT_ENDPTSETUPSTAT1_Pos)       /*!< USB0 ENDPTSETUPSTAT: ENDPTSETUPSTAT1 Mask */
#define USB0_ENDPTSETUPSTAT_ENDPTSETUPSTAT2_Pos               2                                                         /*!< USB0 ENDPTSETUPSTAT: ENDPTSETUPSTAT2 Position */
#define USB0_ENDPTSETUPSTAT_ENDPTSETUPSTAT2_Msk               (0x01UL << USB0_ENDPTSETUPSTAT_ENDPTSETUPSTAT2_Pos)       /*!< USB0 ENDPTSETUPSTAT: ENDPTSETUPSTAT2 Mask */
#define USB0_ENDPTSETUPSTAT_ENDPTSETUPSTAT3_Pos               3                                                         /*!< USB0 ENDPTSETUPSTAT: ENDPTSETUPSTAT3 Position */
#define USB0_ENDPTSETUPSTAT_ENDPTSETUPSTAT3_Msk               (0x01UL << USB0_ENDPTSETUPSTAT_ENDPTSETUPSTAT3_Pos)       /*!< USB0 ENDPTSETUPSTAT: ENDPTSETUPSTAT3 Mask */
#define USB0_ENDPTSETUPSTAT_ENDPTSETUPSTAT4_Pos               4                                                         /*!< USB0 ENDPTSETUPSTAT: ENDPTSETUPSTAT4 Position */
#define USB0_ENDPTSETUPSTAT_ENDPTSETUPSTAT4_Msk               (0x01UL << USB0_ENDPTSETUPSTAT_ENDPTSETUPSTAT4_Pos)       /*!< USB0 ENDPTSETUPSTAT: ENDPTSETUPSTAT4 Mask */
#define USB0_ENDPTSETUPSTAT_ENDPTSETUPSTAT5_Pos               5                                                         /*!< USB0 ENDPTSETUPSTAT: ENDPTSETUPSTAT5 Position */
#define USB0_ENDPTSETUPSTAT_ENDPTSETUPSTAT5_Msk               (0x01UL << USB0_ENDPTSETUPSTAT_ENDPTSETUPSTAT5_Pos)       /*!< USB0 ENDPTSETUPSTAT: ENDPTSETUPSTAT5 Mask */

// -------------------------------------  USB0_ENDPTPRIME  ----------------------------------------
#define USB0_ENDPTPRIME_PERB0_Pos                             0                                                         /*!< USB0 ENDPTPRIME: PERB0 Position     */
#define USB0_ENDPTPRIME_PERB0_Msk                             (0x01UL << USB0_ENDPTPRIME_PERB0_Pos)                     /*!< USB0 ENDPTPRIME: PERB0 Mask         */
#define USB0_ENDPTPRIME_PERB1_Pos                             1                                                         /*!< USB0 ENDPTPRIME: PERB1 Position     */
#define USB0_ENDPTPRIME_PERB1_Msk                             (0x01UL << USB0_ENDPTPRIME_PERB1_Pos)                     /*!< USB0 ENDPTPRIME: PERB1 Mask         */
#define USB0_ENDPTPRIME_PERB2_Pos                             2                                                         /*!< USB0 ENDPTPRIME: PERB2 Position     */
#define USB0_ENDPTPRIME_PERB2_Msk                             (0x01UL << USB0_ENDPTPRIME_PERB2_Pos)                     /*!< USB0 ENDPTPRIME: PERB2 Mask         */
#define USB0_ENDPTPRIME_PERB3_Pos                             3                                                         /*!< USB0 ENDPTPRIME: PERB3 Position     */
#define USB0_ENDPTPRIME_PERB3_Msk                             (0x01UL << USB0_ENDPTPRIME_PERB3_Pos)                     /*!< USB0 ENDPTPRIME: PERB3 Mask         */
#define USB0_ENDPTPRIME_PERB4_Pos                             4                                                         /*!< USB0 ENDPTPRIME: PERB4 Position     */
#define USB0_ENDPTPRIME_PERB4_Msk                             (0x01UL << USB0_ENDPTPRIME_PERB4_Pos)                     /*!< USB0 ENDPTPRIME: PERB4 Mask         */
#define USB0_ENDPTPRIME_PERB5_Pos                             5                                                         /*!< USB0 ENDPTPRIME: PERB5 Position     */
#define USB0_ENDPTPRIME_PERB5_Msk                             (0x01UL << USB0_ENDPTPRIME_PERB5_Pos)                     /*!< USB0 ENDPTPRIME: PERB5 Mask         */
#define USB0_ENDPTPRIME_PETB0_Pos                             16                                                        /*!< USB0 ENDPTPRIME: PETB0 Position     */
#define USB0_ENDPTPRIME_PETB0_Msk                             (0x01UL << USB0_ENDPTPRIME_PETB0_Pos)                     /*!< USB0 ENDPTPRIME: PETB0 Mask         */
#define USB0_ENDPTPRIME_PETB1_Pos                             17                                                        /*!< USB0 ENDPTPRIME: PETB1 Position     */
#define USB0_ENDPTPRIME_PETB1_Msk                             (0x01UL << USB0_ENDPTPRIME_PETB1_Pos)                     /*!< USB0 ENDPTPRIME: PETB1 Mask         */
#define USB0_ENDPTPRIME_PETB2_Pos                             18                                                        /*!< USB0 ENDPTPRIME: PETB2 Position     */
#define USB0_ENDPTPRIME_PETB2_Msk                             (0x01UL << USB0_ENDPTPRIME_PETB2_Pos)                     /*!< USB0 ENDPTPRIME: PETB2 Mask         */
#define USB0_ENDPTPRIME_PETB3_Pos                             19                                                        /*!< USB0 ENDPTPRIME: PETB3 Position     */
#define USB0_ENDPTPRIME_PETB3_Msk                             (0x01UL << USB0_ENDPTPRIME_PETB3_Pos)                     /*!< USB0 ENDPTPRIME: PETB3 Mask         */
#define USB0_ENDPTPRIME_PETB4_Pos                             20                                                        /*!< USB0 ENDPTPRIME: PETB4 Position     */
#define USB0_ENDPTPRIME_PETB4_Msk                             (0x01UL << USB0_ENDPTPRIME_PETB4_Pos)                     /*!< USB0 ENDPTPRIME: PETB4 Mask         */
#define USB0_ENDPTPRIME_PETB5_Pos                             21                                                        /*!< USB0 ENDPTPRIME: PETB5 Position     */
#define USB0_ENDPTPRIME_PETB5_Msk                             (0x01UL << USB0_ENDPTPRIME_PETB5_Pos)                     /*!< USB0 ENDPTPRIME: PETB5 Mask         */

// -------------------------------------  USB0_ENDPTFLUSH  ----------------------------------------
#define USB0_ENDPTFLUSH_FERB0_Pos                             0                                                         /*!< USB0 ENDPTFLUSH: FERB0 Position     */
#define USB0_ENDPTFLUSH_FERB0_Msk                             (0x01UL << USB0_ENDPTFLUSH_FERB0_Pos)                     /*!< USB0 ENDPTFLUSH: FERB0 Mask         */
#define USB0_ENDPTFLUSH_FERB1_Pos                             1                                                         /*!< USB0 ENDPTFLUSH: FERB1 Position     */
#define USB0_ENDPTFLUSH_FERB1_Msk                             (0x01UL << USB0_ENDPTFLUSH_FERB1_Pos)                     /*!< USB0 ENDPTFLUSH: FERB1 Mask         */
#define USB0_ENDPTFLUSH_FERB2_Pos                             2                                                         /*!< USB0 ENDPTFLUSH: FERB2 Position     */
#define USB0_ENDPTFLUSH_FERB2_Msk                             (0x01UL << USB0_ENDPTFLUSH_FERB2_Pos)                     /*!< USB0 ENDPTFLUSH: FERB2 Mask         */
#define USB0_ENDPTFLUSH_FERB3_Pos                             3                                                         /*!< USB0 ENDPTFLUSH: FERB3 Position     */
#define USB0_ENDPTFLUSH_FERB3_Msk                             (0x01UL << USB0_ENDPTFLUSH_FERB3_Pos)                     /*!< USB0 ENDPTFLUSH: FERB3 Mask         */
#define USB0_ENDPTFLUSH_FERB4_Pos                             4                                                         /*!< USB0 ENDPTFLUSH: FERB4 Position     */
#define USB0_ENDPTFLUSH_FERB4_Msk                             (0x01UL << USB0_ENDPTFLUSH_FERB4_Pos)                     /*!< USB0 ENDPTFLUSH: FERB4 Mask         */
#define USB0_ENDPTFLUSH_FERB5_Pos                             5                                                         /*!< USB0 ENDPTFLUSH: FERB5 Position     */
#define USB0_ENDPTFLUSH_FERB5_Msk                             (0x01UL << USB0_ENDPTFLUSH_FERB5_Pos)                     /*!< USB0 ENDPTFLUSH: FERB5 Mask         */
#define USB0_ENDPTFLUSH_FETB0_Pos                             16                                                        /*!< USB0 ENDPTFLUSH: FETB0 Position     */
#define USB0_ENDPTFLUSH_FETB0_Msk                             (0x01UL << USB0_ENDPTFLUSH_FETB0_Pos)                     /*!< USB0 ENDPTFLUSH: FETB0 Mask         */
#define USB0_ENDPTFLUSH_FETB1_Pos                             17                                                        /*!< USB0 ENDPTFLUSH: FETB1 Position     */
#define USB0_ENDPTFLUSH_FETB1_Msk                             (0x01UL << USB0_ENDPTFLUSH_FETB1_Pos)                     /*!< USB0 ENDPTFLUSH: FETB1 Mask         */
#define USB0_ENDPTFLUSH_FETB2_Pos                             18                                                        /*!< USB0 ENDPTFLUSH: FETB2 Position     */
#define USB0_ENDPTFLUSH_FETB2_Msk                             (0x01UL << USB0_ENDPTFLUSH_FETB2_Pos)                     /*!< USB0 ENDPTFLUSH: FETB2 Mask         */
#define USB0_ENDPTFLUSH_FETB3_Pos                             19                                                        /*!< USB0 ENDPTFLUSH: FETB3 Position     */
#define USB0_ENDPTFLUSH_FETB3_Msk                             (0x01UL << USB0_ENDPTFLUSH_FETB3_Pos)                     /*!< USB0 ENDPTFLUSH: FETB3 Mask         */
#define USB0_ENDPTFLUSH_FETB4_Pos                             20                                                        /*!< USB0 ENDPTFLUSH: FETB4 Position     */
#define USB0_ENDPTFLUSH_FETB4_Msk                             (0x01UL << USB0_ENDPTFLUSH_FETB4_Pos)                     /*!< USB0 ENDPTFLUSH: FETB4 Mask         */
#define USB0_ENDPTFLUSH_FETB5_Pos                             21                                                        /*!< USB0 ENDPTFLUSH: FETB5 Position     */
#define USB0_ENDPTFLUSH_FETB5_Msk                             (0x01UL << USB0_ENDPTFLUSH_FETB5_Pos)                     /*!< USB0 ENDPTFLUSH: FETB5 Mask         */

// -------------------------------------  USB0_ENDPTSTAT  -----------------------------------------
#define USB0_ENDPTSTAT_ERBR0_Pos                              0                                                         /*!< USB0 ENDPTSTAT: ERBR0 Position      */
#define USB0_ENDPTSTAT_ERBR0_Msk                              (0x01UL << USB0_ENDPTSTAT_ERBR0_Pos)                      /*!< USB0 ENDPTSTAT: ERBR0 Mask          */
#define USB0_ENDPTSTAT_ERBR1_Pos                              1                                                         /*!< USB0 ENDPTSTAT: ERBR1 Position      */
#define USB0_ENDPTSTAT_ERBR1_Msk                              (0x01UL << USB0_ENDPTSTAT_ERBR1_Pos)                      /*!< USB0 ENDPTSTAT: ERBR1 Mask          */
#define USB0_ENDPTSTAT_ERBR2_Pos                              2                                                         /*!< USB0 ENDPTSTAT: ERBR2 Position      */
#define USB0_ENDPTSTAT_ERBR2_Msk                              (0x01UL << USB0_ENDPTSTAT_ERBR2_Pos)                      /*!< USB0 ENDPTSTAT: ERBR2 Mask          */
#define USB0_ENDPTSTAT_ERBR3_Pos                              3                                                         /*!< USB0 ENDPTSTAT: ERBR3 Position      */
#define USB0_ENDPTSTAT_ERBR3_Msk                              (0x01UL << USB0_ENDPTSTAT_ERBR3_Pos)                      /*!< USB0 ENDPTSTAT: ERBR3 Mask          */
#define USB0_ENDPTSTAT_ERBR4_Pos                              4                                                         /*!< USB0 ENDPTSTAT: ERBR4 Position      */
#define USB0_ENDPTSTAT_ERBR4_Msk                              (0x01UL << USB0_ENDPTSTAT_ERBR4_Pos)                      /*!< USB0 ENDPTSTAT: ERBR4 Mask          */
#define USB0_ENDPTSTAT_ERBR5_Pos                              5                                                         /*!< USB0 ENDPTSTAT: ERBR5 Position      */
#define USB0_ENDPTSTAT_ERBR5_Msk                              (0x01UL << USB0_ENDPTSTAT_ERBR5_Pos)                      /*!< USB0 ENDPTSTAT: ERBR5 Mask          */
#define USB0_ENDPTSTAT_ETBR0_Pos                              16                                                        /*!< USB0 ENDPTSTAT: ETBR0 Position      */
#define USB0_ENDPTSTAT_ETBR0_Msk                              (0x01UL << USB0_ENDPTSTAT_ETBR0_Pos)                      /*!< USB0 ENDPTSTAT: ETBR0 Mask          */
#define USB0_ENDPTSTAT_ETBR1_Pos                              17                                                        /*!< USB0 ENDPTSTAT: ETBR1 Position      */
#define USB0_ENDPTSTAT_ETBR1_Msk                              (0x01UL << USB0_ENDPTSTAT_ETBR1_Pos)                      /*!< USB0 ENDPTSTAT: ETBR1 Mask          */
#define USB0_ENDPTSTAT_ETBR2_Pos                              18                                                        /*!< USB0 ENDPTSTAT: ETBR2 Position      */
#define USB0_ENDPTSTAT_ETBR2_Msk                              (0x01UL << USB0_ENDPTSTAT_ETBR2_Pos)                      /*!< USB0 ENDPTSTAT: ETBR2 Mask          */
#define USB0_ENDPTSTAT_ETBR3_Pos                              19                                                        /*!< USB0 ENDPTSTAT: ETBR3 Position      */
#define USB0_ENDPTSTAT_ETBR3_Msk                              (0x01UL << USB0_ENDPTSTAT_ETBR3_Pos)                      /*!< USB0 ENDPTSTAT: ETBR3 Mask          */
#define USB0_ENDPTSTAT_ETBR4_Pos                              20                                                        /*!< USB0 ENDPTSTAT: ETBR4 Position      */
#define USB0_ENDPTSTAT_ETBR4_Msk                              (0x01UL << USB0_ENDPTSTAT_ETBR4_Pos)                      /*!< USB0 ENDPTSTAT: ETBR4 Mask          */
#define USB0_ENDPTSTAT_ETBR5_Pos                              21                                                        /*!< USB0 ENDPTSTAT: ETBR5 Position      */
#define USB0_ENDPTSTAT_ETBR5_Msk                              (0x01UL << USB0_ENDPTSTAT_ETBR5_Pos)                      /*!< USB0 ENDPTSTAT: ETBR5 Mask          */

// -----------------------------------  USB0_ENDPTCOMPLETE  ---------------------------------------
#define USB0_ENDPTCOMPLETE_ERCE0_Pos                          0                                                         /*!< USB0 ENDPTCOMPLETE: ERCE0 Position  */
#define USB0_ENDPTCOMPLETE_ERCE0_Msk                          (0x01UL << USB0_ENDPTCOMPLETE_ERCE0_Pos)                  /*!< USB0 ENDPTCOMPLETE: ERCE0 Mask      */
#define USB0_ENDPTCOMPLETE_ERCE1_Pos                          1                                                         /*!< USB0 ENDPTCOMPLETE: ERCE1 Position  */
#define USB0_ENDPTCOMPLETE_ERCE1_Msk                          (0x01UL << USB0_ENDPTCOMPLETE_ERCE1_Pos)                  /*!< USB0 ENDPTCOMPLETE: ERCE1 Mask      */
#define USB0_ENDPTCOMPLETE_ERCE2_Pos                          2                                                         /*!< USB0 ENDPTCOMPLETE: ERCE2 Position  */
#define USB0_ENDPTCOMPLETE_ERCE2_Msk                          (0x01UL << USB0_ENDPTCOMPLETE_ERCE2_Pos)                  /*!< USB0 ENDPTCOMPLETE: ERCE2 Mask      */
#define USB0_ENDPTCOMPLETE_ERCE3_Pos                          3                                                         /*!< USB0 ENDPTCOMPLETE: ERCE3 Position  */
#define USB0_ENDPTCOMPLETE_ERCE3_Msk                          (0x01UL << USB0_ENDPTCOMPLETE_ERCE3_Pos)                  /*!< USB0 ENDPTCOMPLETE: ERCE3 Mask      */
#define USB0_ENDPTCOMPLETE_ERCE4_Pos                          4                                                         /*!< USB0 ENDPTCOMPLETE: ERCE4 Position  */
#define USB0_ENDPTCOMPLETE_ERCE4_Msk                          (0x01UL << USB0_ENDPTCOMPLETE_ERCE4_Pos)                  /*!< USB0 ENDPTCOMPLETE: ERCE4 Mask      */
#define USB0_ENDPTCOMPLETE_ERCE5_Pos                          5                                                         /*!< USB0 ENDPTCOMPLETE: ERCE5 Position  */
#define USB0_ENDPTCOMPLETE_ERCE5_Msk                          (0x01UL << USB0_ENDPTCOMPLETE_ERCE5_Pos)                  /*!< USB0 ENDPTCOMPLETE: ERCE5 Mask      */
#define USB0_ENDPTCOMPLETE_ETCE0_Pos                          16                                                        /*!< USB0 ENDPTCOMPLETE: ETCE0 Position  */
#define USB0_ENDPTCOMPLETE_ETCE0_Msk                          (0x01UL << USB0_ENDPTCOMPLETE_ETCE0_Pos)                  /*!< USB0 ENDPTCOMPLETE: ETCE0 Mask      */
#define USB0_ENDPTCOMPLETE_ETCE1_Pos                          17                                                        /*!< USB0 ENDPTCOMPLETE: ETCE1 Position  */
#define USB0_ENDPTCOMPLETE_ETCE1_Msk                          (0x01UL << USB0_ENDPTCOMPLETE_ETCE1_Pos)                  /*!< USB0 ENDPTCOMPLETE: ETCE1 Mask      */
#define USB0_ENDPTCOMPLETE_ETCE2_Pos                          18                                                        /*!< USB0 ENDPTCOMPLETE: ETCE2 Position  */
#define USB0_ENDPTCOMPLETE_ETCE2_Msk                          (0x01UL << USB0_ENDPTCOMPLETE_ETCE2_Pos)                  /*!< USB0 ENDPTCOMPLETE: ETCE2 Mask      */
#define USB0_ENDPTCOMPLETE_ETCE3_Pos                          19                                                        /*!< USB0 ENDPTCOMPLETE: ETCE3 Position  */
#define USB0_ENDPTCOMPLETE_ETCE3_Msk                          (0x01UL << USB0_ENDPTCOMPLETE_ETCE3_Pos)                  /*!< USB0 ENDPTCOMPLETE: ETCE3 Mask      */
#define USB0_ENDPTCOMPLETE_ETCE4_Pos                          20                                                        /*!< USB0 ENDPTCOMPLETE: ETCE4 Position  */
#define USB0_ENDPTCOMPLETE_ETCE4_Msk                          (0x01UL << USB0_ENDPTCOMPLETE_ETCE4_Pos)                  /*!< USB0 ENDPTCOMPLETE: ETCE4 Mask      */
#define USB0_ENDPTCOMPLETE_ETCE5_Pos                          21                                                        /*!< USB0 ENDPTCOMPLETE: ETCE5 Position  */
#define USB0_ENDPTCOMPLETE_ETCE5_Msk                          (0x01UL << USB0_ENDPTCOMPLETE_ETCE5_Pos)                  /*!< USB0 ENDPTCOMPLETE: ETCE5 Mask      */

// -------------------------------------  USB0_ENDPTCTRL0  ----------------------------------------
#define USB0_ENDPTCTRL0_RXS_Pos                               0                                                         /*!< USB0 ENDPTCTRL0: RXS Position       */
#define USB0_ENDPTCTRL0_RXS_Msk                               (0x01UL << USB0_ENDPTCTRL0_RXS_Pos)                       /*!< USB0 ENDPTCTRL0: RXS Mask           */
#define USB0_ENDPTCTRL0_RXT1_0_Pos                            2                                                         /*!< USB0 ENDPTCTRL0: RXT1_0 Position    */
#define USB0_ENDPTCTRL0_RXT1_0_Msk                            (0x03UL << USB0_ENDPTCTRL0_RXT1_0_Pos)                    /*!< USB0 ENDPTCTRL0: RXT1_0 Mask        */
#define USB0_ENDPTCTRL0_RXE_Pos                               7                                                         /*!< USB0 ENDPTCTRL0: RXE Position       */
#define USB0_ENDPTCTRL0_RXE_Msk                               (0x01UL << USB0_ENDPTCTRL0_RXE_Pos)                       /*!< USB0 ENDPTCTRL0: RXE Mask           */
#define USB0_ENDPTCTRL0_TXS_Pos                               16                                                        /*!< USB0 ENDPTCTRL0: TXS Position       */
#define USB0_ENDPTCTRL0_TXS_Msk                               (0x01UL << USB0_ENDPTCTRL0_TXS_Pos)                       /*!< USB0 ENDPTCTRL0: TXS Mask           */
#define USB0_ENDPTCTRL0_TXT1_0_Pos                            18                                                        /*!< USB0 ENDPTCTRL0: TXT1_0 Position    */
#define USB0_ENDPTCTRL0_TXT1_0_Msk                            (0x03UL << USB0_ENDPTCTRL0_TXT1_0_Pos)                    /*!< USB0 ENDPTCTRL0: TXT1_0 Mask        */
#define USB0_ENDPTCTRL0_TXE_Pos                               23                                                        /*!< USB0 ENDPTCTRL0: TXE Position       */
#define USB0_ENDPTCTRL0_TXE_Msk                               (0x01UL << USB0_ENDPTCTRL0_TXE_Pos)                       /*!< USB0 ENDPTCTRL0: TXE Mask           */

// -------------------------------------  USB0_ENDPTCTRL1  ----------------------------------------
#define USB0_ENDPTCTRL1_RXS_Pos                               0                                                         /*!< USB0 ENDPTCTRL1: RXS Position       */
#define USB0_ENDPTCTRL1_RXS_Msk                               (0x01UL << USB0_ENDPTCTRL1_RXS_Pos)                       /*!< USB0 ENDPTCTRL1: RXS Mask           */
#define USB0_ENDPTCTRL1_RXT_Pos                               2                                                         /*!< USB0 ENDPTCTRL1: RXT Position       */
#define USB0_ENDPTCTRL1_RXT_Msk                               (0x03UL << USB0_ENDPTCTRL1_RXT_Pos)                       /*!< USB0 ENDPTCTRL1: RXT Mask           */
#define USB0_ENDPTCTRL1_RXI_Pos                               5                                                         /*!< USB0 ENDPTCTRL1: RXI Position       */
#define USB0_ENDPTCTRL1_RXI_Msk                               (0x01UL << USB0_ENDPTCTRL1_RXI_Pos)                       /*!< USB0 ENDPTCTRL1: RXI Mask           */
#define USB0_ENDPTCTRL1_RXR_Pos                               6                                                         /*!< USB0 ENDPTCTRL1: RXR Position       */
#define USB0_ENDPTCTRL1_RXR_Msk                               (0x01UL << USB0_ENDPTCTRL1_RXR_Pos)                       /*!< USB0 ENDPTCTRL1: RXR Mask           */
#define USB0_ENDPTCTRL1_RXE_Pos                               7                                                         /*!< USB0 ENDPTCTRL1: RXE Position       */
#define USB0_ENDPTCTRL1_RXE_Msk                               (0x01UL << USB0_ENDPTCTRL1_RXE_Pos)                       /*!< USB0 ENDPTCTRL1: RXE Mask           */
#define USB0_ENDPTCTRL1_TXS_Pos                               16                                                        /*!< USB0 ENDPTCTRL1: TXS Position       */
#define USB0_ENDPTCTRL1_TXS_Msk                               (0x01UL << USB0_ENDPTCTRL1_TXS_Pos)                       /*!< USB0 ENDPTCTRL1: TXS Mask           */
#define USB0_ENDPTCTRL1_TXT1_0_Pos                            18                                                        /*!< USB0 ENDPTCTRL1: TXT1_0 Position    */
#define USB0_ENDPTCTRL1_TXT1_0_Msk                            (0x03UL << USB0_ENDPTCTRL1_TXT1_0_Pos)                    /*!< USB0 ENDPTCTRL1: TXT1_0 Mask        */
#define USB0_ENDPTCTRL1_TXI_Pos                               21                                                        /*!< USB0 ENDPTCTRL1: TXI Position       */
#define USB0_ENDPTCTRL1_TXI_Msk                               (0x01UL << USB0_ENDPTCTRL1_TXI_Pos)                       /*!< USB0 ENDPTCTRL1: TXI Mask           */
#define USB0_ENDPTCTRL1_TXR_Pos                               22                                                        /*!< USB0 ENDPTCTRL1: TXR Position       */
#define USB0_ENDPTCTRL1_TXR_Msk                               (0x01UL << USB0_ENDPTCTRL1_TXR_Pos)                       /*!< USB0 ENDPTCTRL1: TXR Mask           */
#define USB0_ENDPTCTRL1_TXE_Pos                               23                                                        /*!< USB0 ENDPTCTRL1: TXE Position       */
#define USB0_ENDPTCTRL1_TXE_Msk                               (0x01UL << USB0_ENDPTCTRL1_TXE_Pos)                       /*!< USB0 ENDPTCTRL1: TXE Mask           */

// -------------------------------------  USB0_ENDPTCTRL2  ----------------------------------------
#define USB0_ENDPTCTRL2_RXS_Pos                               0                                                         /*!< USB0 ENDPTCTRL2: RXS Position       */
#define USB0_ENDPTCTRL2_RXS_Msk                               (0x01UL << USB0_ENDPTCTRL2_RXS_Pos)                       /*!< USB0 ENDPTCTRL2: RXS Mask           */
#define USB0_ENDPTCTRL2_RXT_Pos                               2                                                         /*!< USB0 ENDPTCTRL2: RXT Position       */
#define USB0_ENDPTCTRL2_RXT_Msk                               (0x03UL << USB0_ENDPTCTRL2_RXT_Pos)                       /*!< USB0 ENDPTCTRL2: RXT Mask           */
#define USB0_ENDPTCTRL2_RXI_Pos                               5                                                         /*!< USB0 ENDPTCTRL2: RXI Position       */
#define USB0_ENDPTCTRL2_RXI_Msk                               (0x01UL << USB0_ENDPTCTRL2_RXI_Pos)                       /*!< USB0 ENDPTCTRL2: RXI Mask           */
#define USB0_ENDPTCTRL2_RXR_Pos                               6                                                         /*!< USB0 ENDPTCTRL2: RXR Position       */
#define USB0_ENDPTCTRL2_RXR_Msk                               (0x01UL << USB0_ENDPTCTRL2_RXR_Pos)                       /*!< USB0 ENDPTCTRL2: RXR Mask           */
#define USB0_ENDPTCTRL2_RXE_Pos                               7                                                         /*!< USB0 ENDPTCTRL2: RXE Position       */
#define USB0_ENDPTCTRL2_RXE_Msk                               (0x01UL << USB0_ENDPTCTRL2_RXE_Pos)                       /*!< USB0 ENDPTCTRL2: RXE Mask           */
#define USB0_ENDPTCTRL2_TXS_Pos                               16                                                        /*!< USB0 ENDPTCTRL2: TXS Position       */
#define USB0_ENDPTCTRL2_TXS_Msk                               (0x01UL << USB0_ENDPTCTRL2_TXS_Pos)                       /*!< USB0 ENDPTCTRL2: TXS Mask           */
#define USB0_ENDPTCTRL2_TXT1_0_Pos                            18                                                        /*!< USB0 ENDPTCTRL2: TXT1_0 Position    */
#define USB0_ENDPTCTRL2_TXT1_0_Msk                            (0x03UL << USB0_ENDPTCTRL2_TXT1_0_Pos)                    /*!< USB0 ENDPTCTRL2: TXT1_0 Mask        */
#define USB0_ENDPTCTRL2_TXI_Pos                               21                                                        /*!< USB0 ENDPTCTRL2: TXI Position       */
#define USB0_ENDPTCTRL2_TXI_Msk                               (0x01UL << USB0_ENDPTCTRL2_TXI_Pos)                       /*!< USB0 ENDPTCTRL2: TXI Mask           */
#define USB0_ENDPTCTRL2_TXR_Pos                               22                                                        /*!< USB0 ENDPTCTRL2: TXR Position       */
#define USB0_ENDPTCTRL2_TXR_Msk                               (0x01UL << USB0_ENDPTCTRL2_TXR_Pos)                       /*!< USB0 ENDPTCTRL2: TXR Mask           */
#define USB0_ENDPTCTRL2_TXE_Pos                               23                                                        /*!< USB0 ENDPTCTRL2: TXE Position       */
#define USB0_ENDPTCTRL2_TXE_Msk                               (0x01UL << USB0_ENDPTCTRL2_TXE_Pos)                       /*!< USB0 ENDPTCTRL2: TXE Mask           */

// -------------------------------------  USB0_ENDPTCTRL3  ----------------------------------------
#define USB0_ENDPTCTRL3_RXS_Pos                               0                                                         /*!< USB0 ENDPTCTRL3: RXS Position       */
#define USB0_ENDPTCTRL3_RXS_Msk                               (0x01UL << USB0_ENDPTCTRL3_RXS_Pos)                       /*!< USB0 ENDPTCTRL3: RXS Mask           */
#define USB0_ENDPTCTRL3_RXT_Pos                               2                                                         /*!< USB0 ENDPTCTRL3: RXT Position       */
#define USB0_ENDPTCTRL3_RXT_Msk                               (0x03UL << USB0_ENDPTCTRL3_RXT_Pos)                       /*!< USB0 ENDPTCTRL3: RXT Mask           */
#define USB0_ENDPTCTRL3_RXI_Pos                               5                                                         /*!< USB0 ENDPTCTRL3: RXI Position       */
#define USB0_ENDPTCTRL3_RXI_Msk                               (0x01UL << USB0_ENDPTCTRL3_RXI_Pos)                       /*!< USB0 ENDPTCTRL3: RXI Mask           */
#define USB0_ENDPTCTRL3_RXR_Pos                               6                                                         /*!< USB0 ENDPTCTRL3: RXR Position       */
#define USB0_ENDPTCTRL3_RXR_Msk                               (0x01UL << USB0_ENDPTCTRL3_RXR_Pos)                       /*!< USB0 ENDPTCTRL3: RXR Mask           */
#define USB0_ENDPTCTRL3_RXE_Pos                               7                                                         /*!< USB0 ENDPTCTRL3: RXE Position       */
#define USB0_ENDPTCTRL3_RXE_Msk                               (0x01UL << USB0_ENDPTCTRL3_RXE_Pos)                       /*!< USB0 ENDPTCTRL3: RXE Mask           */
#define USB0_ENDPTCTRL3_TXS_Pos                               16                                                        /*!< USB0 ENDPTCTRL3: TXS Position       */
#define USB0_ENDPTCTRL3_TXS_Msk                               (0x01UL << USB0_ENDPTCTRL3_TXS_Pos)                       /*!< USB0 ENDPTCTRL3: TXS Mask           */
#define USB0_ENDPTCTRL3_TXT1_0_Pos                            18                                                        /*!< USB0 ENDPTCTRL3: TXT1_0 Position    */
#define USB0_ENDPTCTRL3_TXT1_0_Msk                            (0x03UL << USB0_ENDPTCTRL3_TXT1_0_Pos)                    /*!< USB0 ENDPTCTRL3: TXT1_0 Mask        */
#define USB0_ENDPTCTRL3_TXI_Pos                               21                                                        /*!< USB0 ENDPTCTRL3: TXI Position       */
#define USB0_ENDPTCTRL3_TXI_Msk                               (0x01UL << USB0_ENDPTCTRL3_TXI_Pos)                       /*!< USB0 ENDPTCTRL3: TXI Mask           */
#define USB0_ENDPTCTRL3_TXR_Pos                               22                                                        /*!< USB0 ENDPTCTRL3: TXR Position       */
#define USB0_ENDPTCTRL3_TXR_Msk                               (0x01UL << USB0_ENDPTCTRL3_TXR_Pos)                       /*!< USB0 ENDPTCTRL3: TXR Mask           */
#define USB0_ENDPTCTRL3_TXE_Pos                               23                                                        /*!< USB0 ENDPTCTRL3: TXE Position       */
#define USB0_ENDPTCTRL3_TXE_Msk                               (0x01UL << USB0_ENDPTCTRL3_TXE_Pos)                       /*!< USB0 ENDPTCTRL3: TXE Mask           */

// -------------------------------------  USB0_ENDPTCTRL4  ----------------------------------------
#define USB0_ENDPTCTRL4_RXS_Pos                               0                                                         /*!< USB0 ENDPTCTRL4: RXS Position       */
#define USB0_ENDPTCTRL4_RXS_Msk                               (0x01UL << USB0_ENDPTCTRL4_RXS_Pos)                       /*!< USB0 ENDPTCTRL4: RXS Mask           */
#define USB0_ENDPTCTRL4_RXT_Pos                               2                                                         /*!< USB0 ENDPTCTRL4: RXT Position       */
#define USB0_ENDPTCTRL4_RXT_Msk                               (0x03UL << USB0_ENDPTCTRL4_RXT_Pos)                       /*!< USB0 ENDPTCTRL4: RXT Mask           */
#define USB0_ENDPTCTRL4_RXI_Pos                               5                                                         /*!< USB0 ENDPTCTRL4: RXI Position       */
#define USB0_ENDPTCTRL4_RXI_Msk                               (0x01UL << USB0_ENDPTCTRL4_RXI_Pos)                       /*!< USB0 ENDPTCTRL4: RXI Mask           */
#define USB0_ENDPTCTRL4_RXR_Pos                               6                                                         /*!< USB0 ENDPTCTRL4: RXR Position       */
#define USB0_ENDPTCTRL4_RXR_Msk                               (0x01UL << USB0_ENDPTCTRL4_RXR_Pos)                       /*!< USB0 ENDPTCTRL4: RXR Mask           */
#define USB0_ENDPTCTRL4_RXE_Pos                               7                                                         /*!< USB0 ENDPTCTRL4: RXE Position       */
#define USB0_ENDPTCTRL4_RXE_Msk                               (0x01UL << USB0_ENDPTCTRL4_RXE_Pos)                       /*!< USB0 ENDPTCTRL4: RXE Mask           */
#define USB0_ENDPTCTRL4_TXS_Pos                               16                                                        /*!< USB0 ENDPTCTRL4: TXS Position       */
#define USB0_ENDPTCTRL4_TXS_Msk                               (0x01UL << USB0_ENDPTCTRL4_TXS_Pos)                       /*!< USB0 ENDPTCTRL4: TXS Mask           */
#define USB0_ENDPTCTRL4_TXT1_0_Pos                            18                                                        /*!< USB0 ENDPTCTRL4: TXT1_0 Position    */
#define USB0_ENDPTCTRL4_TXT1_0_Msk                            (0x03UL << USB0_ENDPTCTRL4_TXT1_0_Pos)                    /*!< USB0 ENDPTCTRL4: TXT1_0 Mask        */
#define USB0_ENDPTCTRL4_TXI_Pos                               21                                                        /*!< USB0 ENDPTCTRL4: TXI Position       */
#define USB0_ENDPTCTRL4_TXI_Msk                               (0x01UL << USB0_ENDPTCTRL4_TXI_Pos)                       /*!< USB0 ENDPTCTRL4: TXI Mask           */
#define USB0_ENDPTCTRL4_TXR_Pos                               22                                                        /*!< USB0 ENDPTCTRL4: TXR Position       */
#define USB0_ENDPTCTRL4_TXR_Msk                               (0x01UL << USB0_ENDPTCTRL4_TXR_Pos)                       /*!< USB0 ENDPTCTRL4: TXR Mask           */
#define USB0_ENDPTCTRL4_TXE_Pos                               23                                                        /*!< USB0 ENDPTCTRL4: TXE Position       */
#define USB0_ENDPTCTRL4_TXE_Msk                               (0x01UL << USB0_ENDPTCTRL4_TXE_Pos)                       /*!< USB0 ENDPTCTRL4: TXE Mask           */

// -------------------------------------  USB0_ENDPTCTRL5  ----------------------------------------
#define USB0_ENDPTCTRL5_RXS_Pos                               0                                                         /*!< USB0 ENDPTCTRL5: RXS Position       */
#define USB0_ENDPTCTRL5_RXS_Msk                               (0x01UL << USB0_ENDPTCTRL5_RXS_Pos)                       /*!< USB0 ENDPTCTRL5: RXS Mask           */
#define USB0_ENDPTCTRL5_RXT_Pos                               2                                                         /*!< USB0 ENDPTCTRL5: RXT Position       */
#define USB0_ENDPTCTRL5_RXT_Msk                               (0x03UL << USB0_ENDPTCTRL5_RXT_Pos)                       /*!< USB0 ENDPTCTRL5: RXT Mask           */
#define USB0_ENDPTCTRL5_RXI_Pos                               5                                                         /*!< USB0 ENDPTCTRL5: RXI Position       */
#define USB0_ENDPTCTRL5_RXI_Msk                               (0x01UL << USB0_ENDPTCTRL5_RXI_Pos)                       /*!< USB0 ENDPTCTRL5: RXI Mask           */
#define USB0_ENDPTCTRL5_RXR_Pos                               6                                                         /*!< USB0 ENDPTCTRL5: RXR Position       */
#define USB0_ENDPTCTRL5_RXR_Msk                               (0x01UL << USB0_ENDPTCTRL5_RXR_Pos)                       /*!< USB0 ENDPTCTRL5: RXR Mask           */
#define USB0_ENDPTCTRL5_RXE_Pos                               7                                                         /*!< USB0 ENDPTCTRL5: RXE Position       */
#define USB0_ENDPTCTRL5_RXE_Msk                               (0x01UL << USB0_ENDPTCTRL5_RXE_Pos)                       /*!< USB0 ENDPTCTRL5: RXE Mask           */
#define USB0_ENDPTCTRL5_TXS_Pos                               16                                                        /*!< USB0 ENDPTCTRL5: TXS Position       */
#define USB0_ENDPTCTRL5_TXS_Msk                               (0x01UL << USB0_ENDPTCTRL5_TXS_Pos)                       /*!< USB0 ENDPTCTRL5: TXS Mask           */
#define USB0_ENDPTCTRL5_TXT1_0_Pos                            18                                                        /*!< USB0 ENDPTCTRL5: TXT1_0 Position    */
#define USB0_ENDPTCTRL5_TXT1_0_Msk                            (0x03UL << USB0_ENDPTCTRL5_TXT1_0_Pos)                    /*!< USB0 ENDPTCTRL5: TXT1_0 Mask        */
#define USB0_ENDPTCTRL5_TXI_Pos                               21                                                        /*!< USB0 ENDPTCTRL5: TXI Position       */
#define USB0_ENDPTCTRL5_TXI_Msk                               (0x01UL << USB0_ENDPTCTRL5_TXI_Pos)                       /*!< USB0 ENDPTCTRL5: TXI Mask           */
#define USB0_ENDPTCTRL5_TXR_Pos                               22                                                        /*!< USB0 ENDPTCTRL5: TXR Position       */
#define USB0_ENDPTCTRL5_TXR_Msk                               (0x01UL << USB0_ENDPTCTRL5_TXR_Pos)                       /*!< USB0 ENDPTCTRL5: TXR Mask           */
#define USB0_ENDPTCTRL5_TXE_Pos                               23                                                        /*!< USB0 ENDPTCTRL5: TXE Position       */
#define USB0_ENDPTCTRL5_TXE_Msk                               (0x01UL << USB0_ENDPTCTRL5_TXE_Pos)                       /*!< USB0 ENDPTCTRL5: TXE Mask           */


// ------------------------------------------------------------------------------------------------
// -----                                 USB1 Position & Mask                                 -----
// ------------------------------------------------------------------------------------------------


// -------------------------------------  USB1_CAPLENGTH  -----------------------------------------
#define USB1_CAPLENGTH_CAPLENGTH_Pos                          0                                                         /*!< USB1 CAPLENGTH: CAPLENGTH Position  */
#define USB1_CAPLENGTH_CAPLENGTH_Msk                          (0x000000ffUL << USB1_CAPLENGTH_CAPLENGTH_Pos)            /*!< USB1 CAPLENGTH: CAPLENGTH Mask      */
#define USB1_CAPLENGTH_HCIVERSION_Pos                         8                                                         /*!< USB1 CAPLENGTH: HCIVERSION Position */
#define USB1_CAPLENGTH_HCIVERSION_Msk                         (0x0000ffffUL << USB1_CAPLENGTH_HCIVERSION_Pos)           /*!< USB1 CAPLENGTH: HCIVERSION Mask     */

// -------------------------------------  USB1_HCSPARAMS  -----------------------------------------
#define USB1_HCSPARAMS_N_PORTS_Pos                            0                                                         /*!< USB1 HCSPARAMS: N_PORTS Position    */
#define USB1_HCSPARAMS_N_PORTS_Msk                            (0x0fUL << USB1_HCSPARAMS_N_PORTS_Pos)                    /*!< USB1 HCSPARAMS: N_PORTS Mask        */
#define USB1_HCSPARAMS_PPC_Pos                                4                                                         /*!< USB1 HCSPARAMS: PPC Position        */
#define USB1_HCSPARAMS_PPC_Msk                                (0x01UL << USB1_HCSPARAMS_PPC_Pos)                        /*!< USB1 HCSPARAMS: PPC Mask            */
#define USB1_HCSPARAMS_N_PCC_Pos                              8                                                         /*!< USB1 HCSPARAMS: N_PCC Position      */
#define USB1_HCSPARAMS_N_PCC_Msk                              (0x0fUL << USB1_HCSPARAMS_N_PCC_Pos)                      /*!< USB1 HCSPARAMS: N_PCC Mask          */
#define USB1_HCSPARAMS_N_CC_Pos                               12                                                        /*!< USB1 HCSPARAMS: N_CC Position       */
#define USB1_HCSPARAMS_N_CC_Msk                               (0x0fUL << USB1_HCSPARAMS_N_CC_Pos)                       /*!< USB1 HCSPARAMS: N_CC Mask           */
#define USB1_HCSPARAMS_PI_Pos                                 16                                                        /*!< USB1 HCSPARAMS: PI Position         */
#define USB1_HCSPARAMS_PI_Msk                                 (0x01UL << USB1_HCSPARAMS_PI_Pos)                         /*!< USB1 HCSPARAMS: PI Mask             */
#define USB1_HCSPARAMS_N_PTT_Pos                              20                                                        /*!< USB1 HCSPARAMS: N_PTT Position      */
#define USB1_HCSPARAMS_N_PTT_Msk                              (0x0fUL << USB1_HCSPARAMS_N_PTT_Pos)                      /*!< USB1 HCSPARAMS: N_PTT Mask          */
#define USB1_HCSPARAMS_N_TT_Pos                               24                                                        /*!< USB1 HCSPARAMS: N_TT Position       */
#define USB1_HCSPARAMS_N_TT_Msk                               (0x0fUL << USB1_HCSPARAMS_N_TT_Pos)                       /*!< USB1 HCSPARAMS: N_TT Mask           */

// -------------------------------------  USB1_HCCPARAMS  -----------------------------------------
#define USB1_HCCPARAMS_ADC_Pos                                0                                                         /*!< USB1 HCCPARAMS: ADC Position        */
#define USB1_HCCPARAMS_ADC_Msk                                (0x01UL << USB1_HCCPARAMS_ADC_Pos)                        /*!< USB1 HCCPARAMS: ADC Mask            */
#define USB1_HCCPARAMS_PFL_Pos                                1                                                         /*!< USB1 HCCPARAMS: PFL Position        */
#define USB1_HCCPARAMS_PFL_Msk                                (0x01UL << USB1_HCCPARAMS_PFL_Pos)                        /*!< USB1 HCCPARAMS: PFL Mask            */
#define USB1_HCCPARAMS_ASP_Pos                                2                                                         /*!< USB1 HCCPARAMS: ASP Position        */
#define USB1_HCCPARAMS_ASP_Msk                                (0x01UL << USB1_HCCPARAMS_ASP_Pos)                        /*!< USB1 HCCPARAMS: ASP Mask            */
#define USB1_HCCPARAMS_IST_Pos                                4                                                         /*!< USB1 HCCPARAMS: IST Position        */
#define USB1_HCCPARAMS_IST_Msk                                (0x0fUL << USB1_HCCPARAMS_IST_Pos)                        /*!< USB1 HCCPARAMS: IST Mask            */
#define USB1_HCCPARAMS_EECP_Pos                               8                                                         /*!< USB1 HCCPARAMS: EECP Position       */
#define USB1_HCCPARAMS_EECP_Msk                               (0x000000ffUL << USB1_HCCPARAMS_EECP_Pos)                 /*!< USB1 HCCPARAMS: EECP Mask           */

// -------------------------------------  USB1_DCIVERSION  ----------------------------------------
#define USB1_DCIVERSION_DCIVERSION_Pos                        0                                                         /*!< USB1 DCIVERSION: DCIVERSION Position */
#define USB1_DCIVERSION_DCIVERSION_Msk                        (0x0000ffffUL << USB1_DCIVERSION_DCIVERSION_Pos)          /*!< USB1 DCIVERSION: DCIVERSION Mask    */

// --------------------------------------  USB1_USBCMD_D  -----------------------------------------
#define USB1_USBCMD_D_RS_Pos                                  0                                                         /*!< USB1 USBCMD_D: RS Position          */
#define USB1_USBCMD_D_RS_Msk                                  (0x01UL << USB1_USBCMD_D_RS_Pos)                          /*!< USB1 USBCMD_D: RS Mask              */
#define USB1_USBCMD_D_RST_Pos                                 1                                                         /*!< USB1 USBCMD_D: RST Position         */
#define USB1_USBCMD_D_RST_Msk                                 (0x01UL << USB1_USBCMD_D_RST_Pos)                         /*!< USB1 USBCMD_D: RST Mask             */
#define USB1_USBCMD_D_SUTW_Pos                                13                                                        /*!< USB1 USBCMD_D: SUTW Position        */
#define USB1_USBCMD_D_SUTW_Msk                                (0x01UL << USB1_USBCMD_D_SUTW_Pos)                        /*!< USB1 USBCMD_D: SUTW Mask            */
#define USB1_USBCMD_D_ATDTW_Pos                               14                                                        /*!< USB1 USBCMD_D: ATDTW Position       */
#define USB1_USBCMD_D_ATDTW_Msk                               (0x01UL << USB1_USBCMD_D_ATDTW_Pos)                       /*!< USB1 USBCMD_D: ATDTW Mask           */
#define USB1_USBCMD_D_FS2_Pos                                 15                                                        /*!< USB1 USBCMD_D: FS2 Position         */
#define USB1_USBCMD_D_FS2_Msk                                 (0x01UL << USB1_USBCMD_D_FS2_Pos)                         /*!< USB1 USBCMD_D: FS2 Mask             */
#define USB1_USBCMD_D_ITC_Pos                                 16                                                        /*!< USB1 USBCMD_D: ITC Position         */
#define USB1_USBCMD_D_ITC_Msk                                 (0x000000ffUL << USB1_USBCMD_D_ITC_Pos)                   /*!< USB1 USBCMD_D: ITC Mask             */

// --------------------------------------  USB1_USBCMD_H  -----------------------------------------
#define USB1_USBCMD_H_RS_Pos                                  0                                                         /*!< USB1 USBCMD_H: RS Position          */
#define USB1_USBCMD_H_RS_Msk                                  (0x01UL << USB1_USBCMD_H_RS_Pos)                          /*!< USB1 USBCMD_H: RS Mask              */
#define USB1_USBCMD_H_RST_Pos                                 1                                                         /*!< USB1 USBCMD_H: RST Position         */
#define USB1_USBCMD_H_RST_Msk                                 (0x01UL << USB1_USBCMD_H_RST_Pos)                         /*!< USB1 USBCMD_H: RST Mask             */
#define USB1_USBCMD_H_FS0_Pos                                 2                                                         /*!< USB1 USBCMD_H: FS0 Position         */
#define USB1_USBCMD_H_FS0_Msk                                 (0x01UL << USB1_USBCMD_H_FS0_Pos)                         /*!< USB1 USBCMD_H: FS0 Mask             */
#define USB1_USBCMD_H_FS1_Pos                                 3                                                         /*!< USB1 USBCMD_H: FS1 Position         */
#define USB1_USBCMD_H_FS1_Msk                                 (0x01UL << USB1_USBCMD_H_FS1_Pos)                         /*!< USB1 USBCMD_H: FS1 Mask             */
#define USB1_USBCMD_H_PSE_Pos                                 4                                                         /*!< USB1 USBCMD_H: PSE Position         */
#define USB1_USBCMD_H_PSE_Msk                                 (0x01UL << USB1_USBCMD_H_PSE_Pos)                         /*!< USB1 USBCMD_H: PSE Mask             */
#define USB1_USBCMD_H_ASE_Pos                                 5                                                         /*!< USB1 USBCMD_H: ASE Position         */
#define USB1_USBCMD_H_ASE_Msk                                 (0x01UL << USB1_USBCMD_H_ASE_Pos)                         /*!< USB1 USBCMD_H: ASE Mask             */
#define USB1_USBCMD_H_IAA_Pos                                 6                                                         /*!< USB1 USBCMD_H: IAA Position         */
#define USB1_USBCMD_H_IAA_Msk                                 (0x01UL << USB1_USBCMD_H_IAA_Pos)                         /*!< USB1 USBCMD_H: IAA Mask             */
#define USB1_USBCMD_H_ASP1_0_Pos                              8                                                         /*!< USB1 USBCMD_H: ASP1_0 Position      */
#define USB1_USBCMD_H_ASP1_0_Msk                              (0x03UL << USB1_USBCMD_H_ASP1_0_Pos)                      /*!< USB1 USBCMD_H: ASP1_0 Mask          */
#define USB1_USBCMD_H_ASPE_Pos                                11                                                        /*!< USB1 USBCMD_H: ASPE Position        */
#define USB1_USBCMD_H_ASPE_Msk                                (0x01UL << USB1_USBCMD_H_ASPE_Pos)                        /*!< USB1 USBCMD_H: ASPE Mask            */
#define USB1_USBCMD_H_FS2_Pos                                 15                                                        /*!< USB1 USBCMD_H: FS2 Position         */
#define USB1_USBCMD_H_FS2_Msk                                 (0x01UL << USB1_USBCMD_H_FS2_Pos)                         /*!< USB1 USBCMD_H: FS2 Mask             */
#define USB1_USBCMD_H_ITC_Pos                                 16                                                        /*!< USB1 USBCMD_H: ITC Position         */
#define USB1_USBCMD_H_ITC_Msk                                 (0x000000ffUL << USB1_USBCMD_H_ITC_Pos)                   /*!< USB1 USBCMD_H: ITC Mask             */

// --------------------------------------  USB1_USBSTS_D  -----------------------------------------
#define USB1_USBSTS_D_UI_Pos                                  0                                                         /*!< USB1 USBSTS_D: UI Position          */
#define USB1_USBSTS_D_UI_Msk                                  (0x01UL << USB1_USBSTS_D_UI_Pos)                          /*!< USB1 USBSTS_D: UI Mask              */
#define USB1_USBSTS_D_UEI_Pos                                 1                                                         /*!< USB1 USBSTS_D: UEI Position         */
#define USB1_USBSTS_D_UEI_Msk                                 (0x01UL << USB1_USBSTS_D_UEI_Pos)                         /*!< USB1 USBSTS_D: UEI Mask             */
#define USB1_USBSTS_D_PCI_Pos                                 2                                                         /*!< USB1 USBSTS_D: PCI Position         */
#define USB1_USBSTS_D_PCI_Msk                                 (0x01UL << USB1_USBSTS_D_PCI_Pos)                         /*!< USB1 USBSTS_D: PCI Mask             */
#define USB1_USBSTS_D_URI_Pos                                 6                                                         /*!< USB1 USBSTS_D: URI Position         */
#define USB1_USBSTS_D_URI_Msk                                 (0x01UL << USB1_USBSTS_D_URI_Pos)                         /*!< USB1 USBSTS_D: URI Mask             */
#define USB1_USBSTS_D_SRI_Pos                                 7                                                         /*!< USB1 USBSTS_D: SRI Position         */
#define USB1_USBSTS_D_SRI_Msk                                 (0x01UL << USB1_USBSTS_D_SRI_Pos)                         /*!< USB1 USBSTS_D: SRI Mask             */
#define USB1_USBSTS_D_SLI_Pos                                 8                                                         /*!< USB1 USBSTS_D: SLI Position         */
#define USB1_USBSTS_D_SLI_Msk                                 (0x01UL << USB1_USBSTS_D_SLI_Pos)                         /*!< USB1 USBSTS_D: SLI Mask             */
#define USB1_USBSTS_D_NAKI_Pos                                16                                                        /*!< USB1 USBSTS_D: NAKI Position        */
#define USB1_USBSTS_D_NAKI_Msk                                (0x01UL << USB1_USBSTS_D_NAKI_Pos)                        /*!< USB1 USBSTS_D: NAKI Mask            */

// --------------------------------------  USB1_USBSTS_H  -----------------------------------------
#define USB1_USBSTS_H_UI_Pos                                  0                                                         /*!< USB1 USBSTS_H: UI Position          */
#define USB1_USBSTS_H_UI_Msk                                  (0x01UL << USB1_USBSTS_H_UI_Pos)                          /*!< USB1 USBSTS_H: UI Mask              */
#define USB1_USBSTS_H_UEI_Pos                                 1                                                         /*!< USB1 USBSTS_H: UEI Position         */
#define USB1_USBSTS_H_UEI_Msk                                 (0x01UL << USB1_USBSTS_H_UEI_Pos)                         /*!< USB1 USBSTS_H: UEI Mask             */
#define USB1_USBSTS_H_PCI_Pos                                 2                                                         /*!< USB1 USBSTS_H: PCI Position         */
#define USB1_USBSTS_H_PCI_Msk                                 (0x01UL << USB1_USBSTS_H_PCI_Pos)                         /*!< USB1 USBSTS_H: PCI Mask             */
#define USB1_USBSTS_H_FRI_Pos                                 3                                                         /*!< USB1 USBSTS_H: FRI Position         */
#define USB1_USBSTS_H_FRI_Msk                                 (0x01UL << USB1_USBSTS_H_FRI_Pos)                         /*!< USB1 USBSTS_H: FRI Mask             */
#define USB1_USBSTS_H_AAI_Pos                                 5                                                         /*!< USB1 USBSTS_H: AAI Position         */
#define USB1_USBSTS_H_AAI_Msk                                 (0x01UL << USB1_USBSTS_H_AAI_Pos)                         /*!< USB1 USBSTS_H: AAI Mask             */
#define USB1_USBSTS_H_SRI_Pos                                 7                                                         /*!< USB1 USBSTS_H: SRI Position         */
#define USB1_USBSTS_H_SRI_Msk                                 (0x01UL << USB1_USBSTS_H_SRI_Pos)                         /*!< USB1 USBSTS_H: SRI Mask             */
#define USB1_USBSTS_H_SLI_Pos                                 8                                                         /*!< USB1 USBSTS_H: SLI Position         */
#define USB1_USBSTS_H_SLI_Msk                                 (0x01UL << USB1_USBSTS_H_SLI_Pos)                         /*!< USB1 USBSTS_H: SLI Mask             */
#define USB1_USBSTS_H_HCH_Pos                                 12                                                        /*!< USB1 USBSTS_H: HCH Position         */
#define USB1_USBSTS_H_HCH_Msk                                 (0x01UL << USB1_USBSTS_H_HCH_Pos)                         /*!< USB1 USBSTS_H: HCH Mask             */
#define USB1_USBSTS_H_RCL_Pos                                 13                                                        /*!< USB1 USBSTS_H: RCL Position         */
#define USB1_USBSTS_H_RCL_Msk                                 (0x01UL << USB1_USBSTS_H_RCL_Pos)                         /*!< USB1 USBSTS_H: RCL Mask             */
#define USB1_USBSTS_H_PS_Pos                                  14                                                        /*!< USB1 USBSTS_H: PS Position          */
#define USB1_USBSTS_H_PS_Msk                                  (0x01UL << USB1_USBSTS_H_PS_Pos)                          /*!< USB1 USBSTS_H: PS Mask              */
#define USB1_USBSTS_H_AS_Pos                                  15                                                        /*!< USB1 USBSTS_H: AS Position          */
#define USB1_USBSTS_H_AS_Msk                                  (0x01UL << USB1_USBSTS_H_AS_Pos)                          /*!< USB1 USBSTS_H: AS Mask              */
#define USB1_USBSTS_H_UAI_Pos                                 18                                                        /*!< USB1 USBSTS_H: UAI Position         */
#define USB1_USBSTS_H_UAI_Msk                                 (0x01UL << USB1_USBSTS_H_UAI_Pos)                         /*!< USB1 USBSTS_H: UAI Mask             */
#define USB1_USBSTS_H_UPI_Pos                                 19                                                        /*!< USB1 USBSTS_H: UPI Position         */
#define USB1_USBSTS_H_UPI_Msk                                 (0x01UL << USB1_USBSTS_H_UPI_Pos)                         /*!< USB1 USBSTS_H: UPI Mask             */

// -------------------------------------  USB1_USBINTR_D  -----------------------------------------
#define USB1_USBINTR_D_UE_Pos                                 0                                                         /*!< USB1 USBINTR_D: UE Position         */
#define USB1_USBINTR_D_UE_Msk                                 (0x01UL << USB1_USBINTR_D_UE_Pos)                         /*!< USB1 USBINTR_D: UE Mask             */
#define USB1_USBINTR_D_UEE_Pos                                1                                                         /*!< USB1 USBINTR_D: UEE Position        */
#define USB1_USBINTR_D_UEE_Msk                                (0x01UL << USB1_USBINTR_D_UEE_Pos)                        /*!< USB1 USBINTR_D: UEE Mask            */
#define USB1_USBINTR_D_PCE_Pos                                2                                                         /*!< USB1 USBINTR_D: PCE Position        */
#define USB1_USBINTR_D_PCE_Msk                                (0x01UL << USB1_USBINTR_D_PCE_Pos)                        /*!< USB1 USBINTR_D: PCE Mask            */
#define USB1_USBINTR_D_URE_Pos                                6                                                         /*!< USB1 USBINTR_D: URE Position        */
#define USB1_USBINTR_D_URE_Msk                                (0x01UL << USB1_USBINTR_D_URE_Pos)                        /*!< USB1 USBINTR_D: URE Mask            */
#define USB1_USBINTR_D_SRE_Pos                                7                                                         /*!< USB1 USBINTR_D: SRE Position        */
#define USB1_USBINTR_D_SRE_Msk                                (0x01UL << USB1_USBINTR_D_SRE_Pos)                        /*!< USB1 USBINTR_D: SRE Mask            */
#define USB1_USBINTR_D_SLE_Pos                                8                                                         /*!< USB1 USBINTR_D: SLE Position        */
#define USB1_USBINTR_D_SLE_Msk                                (0x01UL << USB1_USBINTR_D_SLE_Pos)                        /*!< USB1 USBINTR_D: SLE Mask            */
#define USB1_USBINTR_D_NAKE_Pos                               16                                                        /*!< USB1 USBINTR_D: NAKE Position       */
#define USB1_USBINTR_D_NAKE_Msk                               (0x01UL << USB1_USBINTR_D_NAKE_Pos)                       /*!< USB1 USBINTR_D: NAKE Mask           */
#define USB1_USBINTR_D_UAIE_Pos                               18                                                        /*!< USB1 USBINTR_D: UAIE Position       */
#define USB1_USBINTR_D_UAIE_Msk                               (0x01UL << USB1_USBINTR_D_UAIE_Pos)                       /*!< USB1 USBINTR_D: UAIE Mask           */
#define USB1_USBINTR_D_UPIA_Pos                               19                                                        /*!< USB1 USBINTR_D: UPIA Position       */
#define USB1_USBINTR_D_UPIA_Msk                               (0x01UL << USB1_USBINTR_D_UPIA_Pos)                       /*!< USB1 USBINTR_D: UPIA Mask           */

// -------------------------------------  USB1_USBINTR_H  -----------------------------------------
#define USB1_USBINTR_H_UE_Pos                                 0                                                         /*!< USB1 USBINTR_H: UE Position         */
#define USB1_USBINTR_H_UE_Msk                                 (0x01UL << USB1_USBINTR_H_UE_Pos)                         /*!< USB1 USBINTR_H: UE Mask             */
#define USB1_USBINTR_H_UEE_Pos                                1                                                         /*!< USB1 USBINTR_H: UEE Position        */
#define USB1_USBINTR_H_UEE_Msk                                (0x01UL << USB1_USBINTR_H_UEE_Pos)                        /*!< USB1 USBINTR_H: UEE Mask            */
#define USB1_USBINTR_H_PCE_Pos                                2                                                         /*!< USB1 USBINTR_H: PCE Position        */
#define USB1_USBINTR_H_PCE_Msk                                (0x01UL << USB1_USBINTR_H_PCE_Pos)                        /*!< USB1 USBINTR_H: PCE Mask            */
#define USB1_USBINTR_H_FRE_Pos                                3                                                         /*!< USB1 USBINTR_H: FRE Position        */
#define USB1_USBINTR_H_FRE_Msk                                (0x01UL << USB1_USBINTR_H_FRE_Pos)                        /*!< USB1 USBINTR_H: FRE Mask            */
#define USB1_USBINTR_H_AAE_Pos                                5                                                         /*!< USB1 USBINTR_H: AAE Position        */
#define USB1_USBINTR_H_AAE_Msk                                (0x01UL << USB1_USBINTR_H_AAE_Pos)                        /*!< USB1 USBINTR_H: AAE Mask            */
#define USB1_USBINTR_H_SRE_Pos                                7                                                         /*!< USB1 USBINTR_H: SRE Position        */
#define USB1_USBINTR_H_SRE_Msk                                (0x01UL << USB1_USBINTR_H_SRE_Pos)                        /*!< USB1 USBINTR_H: SRE Mask            */
#define USB1_USBINTR_H_UAIE_Pos                               18                                                        /*!< USB1 USBINTR_H: UAIE Position       */
#define USB1_USBINTR_H_UAIE_Msk                               (0x01UL << USB1_USBINTR_H_UAIE_Pos)                       /*!< USB1 USBINTR_H: UAIE Mask           */
#define USB1_USBINTR_H_UPIA_Pos                               19                                                        /*!< USB1 USBINTR_H: UPIA Position       */
#define USB1_USBINTR_H_UPIA_Msk                               (0x01UL << USB1_USBINTR_H_UPIA_Pos)                       /*!< USB1 USBINTR_H: UPIA Mask           */

// -------------------------------------  USB1_FRINDEX_D  -----------------------------------------
#define USB1_FRINDEX_D_FRINDEX2_0_Pos                         0                                                         /*!< USB1 FRINDEX_D: FRINDEX2_0 Position */
#define USB1_FRINDEX_D_FRINDEX2_0_Msk                         (0x07UL << USB1_FRINDEX_D_FRINDEX2_0_Pos)                 /*!< USB1 FRINDEX_D: FRINDEX2_0 Mask     */
#define USB1_FRINDEX_D_FRINDEX13_3_Pos                        3                                                         /*!< USB1 FRINDEX_D: FRINDEX13_3 Position */
#define USB1_FRINDEX_D_FRINDEX13_3_Msk                        (0x000007ffUL << USB1_FRINDEX_D_FRINDEX13_3_Pos)          /*!< USB1 FRINDEX_D: FRINDEX13_3 Mask    */

// -------------------------------------  USB1_FRINDEX_H  -----------------------------------------
#define USB1_FRINDEX_H_FRINDEX2_0_Pos                         0                                                         /*!< USB1 FRINDEX_H: FRINDEX2_0 Position */
#define USB1_FRINDEX_H_FRINDEX2_0_Msk                         (0x07UL << USB1_FRINDEX_H_FRINDEX2_0_Pos)                 /*!< USB1 FRINDEX_H: FRINDEX2_0 Mask     */
#define USB1_FRINDEX_H_FRINDEX12_3_Pos                        3                                                         /*!< USB1 FRINDEX_H: FRINDEX12_3 Position */
#define USB1_FRINDEX_H_FRINDEX12_3_Msk                        (0x000003ffUL << USB1_FRINDEX_H_FRINDEX12_3_Pos)          /*!< USB1 FRINDEX_H: FRINDEX12_3 Mask    */

// -------------------------------------  USB1_DEVICEADDR  ----------------------------------------
#define USB1_DEVICEADDR_USBADRA_Pos                           24                                                        /*!< USB1 DEVICEADDR: USBADRA Position   */
#define USB1_DEVICEADDR_USBADRA_Msk                           (0x01UL << USB1_DEVICEADDR_USBADRA_Pos)                   /*!< USB1 DEVICEADDR: USBADRA Mask       */
#define USB1_DEVICEADDR_USBADR_Pos                            25                                                        /*!< USB1 DEVICEADDR: USBADR Position    */
#define USB1_DEVICEADDR_USBADR_Msk                            (0x7fUL << USB1_DEVICEADDR_USBADR_Pos)                    /*!< USB1 DEVICEADDR: USBADR Mask        */

// ----------------------------------  USB1_PERIODICLISTBASE  -------------------------------------
#define USB1_PERIODICLISTBASE_PERBASE31_12_Pos                12                                                        /*!< USB1 PERIODICLISTBASE: PERBASE31_12 Position */
#define USB1_PERIODICLISTBASE_PERBASE31_12_Msk                (0x000fffffUL << USB1_PERIODICLISTBASE_PERBASE31_12_Pos)  /*!< USB1 PERIODICLISTBASE: PERBASE31_12 Mask */

// ----------------------------------  USB1_ENDPOINTLISTADDR  -------------------------------------
#define USB1_ENDPOINTLISTADDR_EPBASE31_11_Pos                 11                                                        /*!< USB1 ENDPOINTLISTADDR: EPBASE31_11 Position */
#define USB1_ENDPOINTLISTADDR_EPBASE31_11_Msk                 (0x001fffffUL << USB1_ENDPOINTLISTADDR_EPBASE31_11_Pos)   /*!< USB1 ENDPOINTLISTADDR: EPBASE31_11 Mask */

// -----------------------------------  USB1_ASYNCLISTADDR  ---------------------------------------
#define USB1_ASYNCLISTADDR_ASYBASE31_5_Pos                    5                                                         /*!< USB1 ASYNCLISTADDR: ASYBASE31_5 Position */
#define USB1_ASYNCLISTADDR_ASYBASE31_5_Msk                    (0x07ffffffUL << USB1_ASYNCLISTADDR_ASYBASE31_5_Pos)      /*!< USB1 ASYNCLISTADDR: ASYBASE31_5 Mask */

// ---------------------------------------  USB1_TTCTRL  ------------------------------------------
#define USB1_TTCTRL_TTHA_Pos                                  24                                                        /*!< USB1 TTCTRL: TTHA Position          */
#define USB1_TTCTRL_TTHA_Msk                                  (0x7fUL << USB1_TTCTRL_TTHA_Pos)                          /*!< USB1 TTCTRL: TTHA Mask              */

// -------------------------------------  USB1_BURSTSIZE  -----------------------------------------
#define USB1_BURSTSIZE_RXPBURST_Pos                           0                                                         /*!< USB1 BURSTSIZE: RXPBURST Position   */
#define USB1_BURSTSIZE_RXPBURST_Msk                           (0x000000ffUL << USB1_BURSTSIZE_RXPBURST_Pos)             /*!< USB1 BURSTSIZE: RXPBURST Mask       */
#define USB1_BURSTSIZE_TXPBURST_Pos                           8                                                         /*!< USB1 BURSTSIZE: TXPBURST Position   */
#define USB1_BURSTSIZE_TXPBURST_Msk                           (0x000000ffUL << USB1_BURSTSIZE_TXPBURST_Pos)             /*!< USB1 BURSTSIZE: TXPBURST Mask       */

// ------------------------------------  USB1_TXFILLTUNING  ---------------------------------------
#define USB1_TXFILLTUNING_TXSCHOH_Pos                         0                                                         /*!< USB1 TXFILLTUNING: TXSCHOH Position */
#define USB1_TXFILLTUNING_TXSCHOH_Msk                         (0x000000ffUL << USB1_TXFILLTUNING_TXSCHOH_Pos)           /*!< USB1 TXFILLTUNING: TXSCHOH Mask     */
#define USB1_TXFILLTUNING_TXSCHEATLTH_Pos                     8                                                         /*!< USB1 TXFILLTUNING: TXSCHEATLTH Position */
#define USB1_TXFILLTUNING_TXSCHEATLTH_Msk                     (0x1fUL << USB1_TXFILLTUNING_TXSCHEATLTH_Pos)             /*!< USB1 TXFILLTUNING: TXSCHEATLTH Mask */
#define USB1_TXFILLTUNING_TXFIFOTHRES_Pos                     16                                                        /*!< USB1 TXFILLTUNING: TXFIFOTHRES Position */
#define USB1_TXFILLTUNING_TXFIFOTHRES_Msk                     (0x3fUL << USB1_TXFILLTUNING_TXFIFOTHRES_Pos)             /*!< USB1 TXFILLTUNING: TXFIFOTHRES Mask */

// ------------------------------------  USB1_ULPIVIEWPORT  ---------------------------------------
#define USB1_ULPIVIEWPORT_ULPIDATWR_Pos                       0                                                         /*!< USB1 ULPIVIEWPORT: ULPIDATWR Position */
#define USB1_ULPIVIEWPORT_ULPIDATWR_Msk                       (0x000000ffUL << USB1_ULPIVIEWPORT_ULPIDATWR_Pos)         /*!< USB1 ULPIVIEWPORT: ULPIDATWR Mask   */
#define USB1_ULPIVIEWPORT_ULPIDATRD_Pos                       8                                                         /*!< USB1 ULPIVIEWPORT: ULPIDATRD Position */
#define USB1_ULPIVIEWPORT_ULPIDATRD_Msk                       (0x000000ffUL << USB1_ULPIVIEWPORT_ULPIDATRD_Pos)         /*!< USB1 ULPIVIEWPORT: ULPIDATRD Mask   */
#define USB1_ULPIVIEWPORT_ULPIADDR_Pos                        16                                                        /*!< USB1 ULPIVIEWPORT: ULPIADDR Position */
#define USB1_ULPIVIEWPORT_ULPIADDR_Msk                        (0x000000ffUL << USB1_ULPIVIEWPORT_ULPIADDR_Pos)          /*!< USB1 ULPIVIEWPORT: ULPIADDR Mask    */
#define USB1_ULPIVIEWPORT_ULPIPORT_Pos                        24                                                        /*!< USB1 ULPIVIEWPORT: ULPIPORT Position */
#define USB1_ULPIVIEWPORT_ULPIPORT_Msk                        (0x07UL << USB1_ULPIVIEWPORT_ULPIPORT_Pos)                /*!< USB1 ULPIVIEWPORT: ULPIPORT Mask    */
#define USB1_ULPIVIEWPORT_ULPISS_Pos                          27                                                        /*!< USB1 ULPIVIEWPORT: ULPISS Position  */
#define USB1_ULPIVIEWPORT_ULPISS_Msk                          (0x01UL << USB1_ULPIVIEWPORT_ULPISS_Pos)                  /*!< USB1 ULPIVIEWPORT: ULPISS Mask      */
#define USB1_ULPIVIEWPORT_ULPIRW_Pos                          29                                                        /*!< USB1 ULPIVIEWPORT: ULPIRW Position  */
#define USB1_ULPIVIEWPORT_ULPIRW_Msk                          (0x01UL << USB1_ULPIVIEWPORT_ULPIRW_Pos)                  /*!< USB1 ULPIVIEWPORT: ULPIRW Mask      */
#define USB1_ULPIVIEWPORT_ULPIRUN_Pos                         30                                                        /*!< USB1 ULPIVIEWPORT: ULPIRUN Position */
#define USB1_ULPIVIEWPORT_ULPIRUN_Msk                         (0x01UL << USB1_ULPIVIEWPORT_ULPIRUN_Pos)                 /*!< USB1 ULPIVIEWPORT: ULPIRUN Mask     */
#define USB1_ULPIVIEWPORT_ULPIWU_Pos                          31                                                        /*!< USB1 ULPIVIEWPORT: ULPIWU Position  */
#define USB1_ULPIVIEWPORT_ULPIWU_Msk                          (0x01UL << USB1_ULPIVIEWPORT_ULPIWU_Pos)                  /*!< USB1 ULPIVIEWPORT: ULPIWU Mask      */

// -------------------------------------  USB1_BINTERVAL  -----------------------------------------
#define USB1_BINTERVAL_BINT_Pos                               0                                                         /*!< USB1 BINTERVAL: BINT Position       */
#define USB1_BINTERVAL_BINT_Msk                               (0x0fUL << USB1_BINTERVAL_BINT_Pos)                       /*!< USB1 BINTERVAL: BINT Mask           */

// --------------------------------------  USB1_ENDPTNAK  -----------------------------------------
#define USB1_ENDPTNAK_EPRN0_Pos                               0                                                         /*!< USB1 ENDPTNAK: EPRN0 Position       */
#define USB1_ENDPTNAK_EPRN0_Msk                               (0x01UL << USB1_ENDPTNAK_EPRN0_Pos)                       /*!< USB1 ENDPTNAK: EPRN0 Mask           */
#define USB1_ENDPTNAK_EPRN1_Pos                               1                                                         /*!< USB1 ENDPTNAK: EPRN1 Position       */
#define USB1_ENDPTNAK_EPRN1_Msk                               (0x01UL << USB1_ENDPTNAK_EPRN1_Pos)                       /*!< USB1 ENDPTNAK: EPRN1 Mask           */
#define USB1_ENDPTNAK_EPRN2_Pos                               2                                                         /*!< USB1 ENDPTNAK: EPRN2 Position       */
#define USB1_ENDPTNAK_EPRN2_Msk                               (0x01UL << USB1_ENDPTNAK_EPRN2_Pos)                       /*!< USB1 ENDPTNAK: EPRN2 Mask           */
#define USB1_ENDPTNAK_EPRN3_Pos                               3                                                         /*!< USB1 ENDPTNAK: EPRN3 Position       */
#define USB1_ENDPTNAK_EPRN3_Msk                               (0x01UL << USB1_ENDPTNAK_EPRN3_Pos)                       /*!< USB1 ENDPTNAK: EPRN3 Mask           */
#define USB1_ENDPTNAK_EPTN16_Pos                              16                                                        /*!< USB1 ENDPTNAK: EPTN16 Position      */
#define USB1_ENDPTNAK_EPTN16_Msk                              (0x01UL << USB1_ENDPTNAK_EPTN16_Pos)                      /*!< USB1 ENDPTNAK: EPTN16 Mask          */
#define USB1_ENDPTNAK_EPTN17_Pos                              17                                                        /*!< USB1 ENDPTNAK: EPTN17 Position      */
#define USB1_ENDPTNAK_EPTN17_Msk                              (0x01UL << USB1_ENDPTNAK_EPTN17_Pos)                      /*!< USB1 ENDPTNAK: EPTN17 Mask          */
#define USB1_ENDPTNAK_EPTN18_Pos                              18                                                        /*!< USB1 ENDPTNAK: EPTN18 Position      */
#define USB1_ENDPTNAK_EPTN18_Msk                              (0x01UL << USB1_ENDPTNAK_EPTN18_Pos)                      /*!< USB1 ENDPTNAK: EPTN18 Mask          */
#define USB1_ENDPTNAK_EPTN19_Pos                              19                                                        /*!< USB1 ENDPTNAK: EPTN19 Position      */
#define USB1_ENDPTNAK_EPTN19_Msk                              (0x01UL << USB1_ENDPTNAK_EPTN19_Pos)                      /*!< USB1 ENDPTNAK: EPTN19 Mask          */

// -------------------------------------  USB1_ENDPTNAKEN  ----------------------------------------
#define USB1_ENDPTNAKEN_EPRNE0_Pos                            0                                                         /*!< USB1 ENDPTNAKEN: EPRNE0 Position    */
#define USB1_ENDPTNAKEN_EPRNE0_Msk                            (0x01UL << USB1_ENDPTNAKEN_EPRNE0_Pos)                    /*!< USB1 ENDPTNAKEN: EPRNE0 Mask        */
#define USB1_ENDPTNAKEN_EPRNE1_Pos                            1                                                         /*!< USB1 ENDPTNAKEN: EPRNE1 Position    */
#define USB1_ENDPTNAKEN_EPRNE1_Msk                            (0x01UL << USB1_ENDPTNAKEN_EPRNE1_Pos)                    /*!< USB1 ENDPTNAKEN: EPRNE1 Mask        */
#define USB1_ENDPTNAKEN_EPRNE2_Pos                            2                                                         /*!< USB1 ENDPTNAKEN: EPRNE2 Position    */
#define USB1_ENDPTNAKEN_EPRNE2_Msk                            (0x01UL << USB1_ENDPTNAKEN_EPRNE2_Pos)                    /*!< USB1 ENDPTNAKEN: EPRNE2 Mask        */
#define USB1_ENDPTNAKEN_EPRNE3_Pos                            3                                                         /*!< USB1 ENDPTNAKEN: EPRNE3 Position    */
#define USB1_ENDPTNAKEN_EPRNE3_Msk                            (0x01UL << USB1_ENDPTNAKEN_EPRNE3_Pos)                    /*!< USB1 ENDPTNAKEN: EPRNE3 Mask        */
#define USB1_ENDPTNAKEN_EPTNE16_Pos                           16                                                        /*!< USB1 ENDPTNAKEN: EPTNE16 Position   */
#define USB1_ENDPTNAKEN_EPTNE16_Msk                           (0x01UL << USB1_ENDPTNAKEN_EPTNE16_Pos)                   /*!< USB1 ENDPTNAKEN: EPTNE16 Mask       */
#define USB1_ENDPTNAKEN_EPTNE17_Pos                           17                                                        /*!< USB1 ENDPTNAKEN: EPTNE17 Position   */
#define USB1_ENDPTNAKEN_EPTNE17_Msk                           (0x01UL << USB1_ENDPTNAKEN_EPTNE17_Pos)                   /*!< USB1 ENDPTNAKEN: EPTNE17 Mask       */
#define USB1_ENDPTNAKEN_EPTNE18_Pos                           18                                                        /*!< USB1 ENDPTNAKEN: EPTNE18 Position   */
#define USB1_ENDPTNAKEN_EPTNE18_Msk                           (0x01UL << USB1_ENDPTNAKEN_EPTNE18_Pos)                   /*!< USB1 ENDPTNAKEN: EPTNE18 Mask       */
#define USB1_ENDPTNAKEN_EPTNE19_Pos                           19                                                        /*!< USB1 ENDPTNAKEN: EPTNE19 Position   */
#define USB1_ENDPTNAKEN_EPTNE19_Msk                           (0x01UL << USB1_ENDPTNAKEN_EPTNE19_Pos)                   /*!< USB1 ENDPTNAKEN: EPTNE19 Mask       */

// -------------------------------------  USB1_PORTSC1_D  -----------------------------------------
#define USB1_PORTSC1_D_CCS_Pos                                0                                                         /*!< USB1 PORTSC1_D: CCS Position        */
#define USB1_PORTSC1_D_CCS_Msk                                (0x01UL << USB1_PORTSC1_D_CCS_Pos)                        /*!< USB1 PORTSC1_D: CCS Mask            */
#define USB1_PORTSC1_D_CSC_Pos                                1                                                         /*!< USB1 PORTSC1_D: CSC Position        */
#define USB1_PORTSC1_D_CSC_Msk                                (0x01UL << USB1_PORTSC1_D_CSC_Pos)                        /*!< USB1 PORTSC1_D: CSC Mask            */
#define USB1_PORTSC1_D_PE_Pos                                 2                                                         /*!< USB1 PORTSC1_D: PE Position         */
#define USB1_PORTSC1_D_PE_Msk                                 (0x01UL << USB1_PORTSC1_D_PE_Pos)                         /*!< USB1 PORTSC1_D: PE Mask             */
#define USB1_PORTSC1_D_PEC_Pos                                3                                                         /*!< USB1 PORTSC1_D: PEC Position        */
#define USB1_PORTSC1_D_PEC_Msk                                (0x01UL << USB1_PORTSC1_D_PEC_Pos)                        /*!< USB1 PORTSC1_D: PEC Mask            */
#define USB1_PORTSC1_D_FPR_Pos                                6                                                         /*!< USB1 PORTSC1_D: FPR Position        */
#define USB1_PORTSC1_D_FPR_Msk                                (0x01UL << USB1_PORTSC1_D_FPR_Pos)                        /*!< USB1 PORTSC1_D: FPR Mask            */
#define USB1_PORTSC1_D_SUSP_Pos                               7                                                         /*!< USB1 PORTSC1_D: SUSP Position       */
#define USB1_PORTSC1_D_SUSP_Msk                               (0x01UL << USB1_PORTSC1_D_SUSP_Pos)                       /*!< USB1 PORTSC1_D: SUSP Mask           */
#define USB1_PORTSC1_D_PR_Pos                                 8                                                         /*!< USB1 PORTSC1_D: PR Position         */
#define USB1_PORTSC1_D_PR_Msk                                 (0x01UL << USB1_PORTSC1_D_PR_Pos)                         /*!< USB1 PORTSC1_D: PR Mask             */
#define USB1_PORTSC1_D_HSP_Pos                                9                                                         /*!< USB1 PORTSC1_D: HSP Position        */
#define USB1_PORTSC1_D_HSP_Msk                                (0x01UL << USB1_PORTSC1_D_HSP_Pos)                        /*!< USB1 PORTSC1_D: HSP Mask            */
#define USB1_PORTSC1_D_LS_Pos                                 10                                                        /*!< USB1 PORTSC1_D: LS Position         */
#define USB1_PORTSC1_D_LS_Msk                                 (0x03UL << USB1_PORTSC1_D_LS_Pos)                         /*!< USB1 PORTSC1_D: LS Mask             */
#define USB1_PORTSC1_D_PP_Pos                                 12                                                        /*!< USB1 PORTSC1_D: PP Position         */
#define USB1_PORTSC1_D_PP_Msk                                 (0x01UL << USB1_PORTSC1_D_PP_Pos)                         /*!< USB1 PORTSC1_D: PP Mask             */
#define USB1_PORTSC1_D_PIC1_0_Pos                             14                                                        /*!< USB1 PORTSC1_D: PIC1_0 Position     */
#define USB1_PORTSC1_D_PIC1_0_Msk                             (0x03UL << USB1_PORTSC1_D_PIC1_0_Pos)                     /*!< USB1 PORTSC1_D: PIC1_0 Mask         */
#define USB1_PORTSC1_D_PTC3_0_Pos                             16                                                        /*!< USB1 PORTSC1_D: PTC3_0 Position     */
#define USB1_PORTSC1_D_PTC3_0_Msk                             (0x0fUL << USB1_PORTSC1_D_PTC3_0_Pos)                     /*!< USB1 PORTSC1_D: PTC3_0 Mask         */
#define USB1_PORTSC1_D_PHCD_Pos                               23                                                        /*!< USB1 PORTSC1_D: PHCD Position       */
#define USB1_PORTSC1_D_PHCD_Msk                               (0x01UL << USB1_PORTSC1_D_PHCD_Pos)                       /*!< USB1 PORTSC1_D: PHCD Mask           */
#define USB1_PORTSC1_D_PFSC_Pos                               24                                                        /*!< USB1 PORTSC1_D: PFSC Position       */
#define USB1_PORTSC1_D_PFSC_Msk                               (0x01UL << USB1_PORTSC1_D_PFSC_Pos)                       /*!< USB1 PORTSC1_D: PFSC Mask           */
#define USB1_PORTSC1_D_PSPD_Pos                               26                                                        /*!< USB1 PORTSC1_D: PSPD Position       */
#define USB1_PORTSC1_D_PSPD_Msk                               (0x03UL << USB1_PORTSC1_D_PSPD_Pos)                       /*!< USB1 PORTSC1_D: PSPD Mask           */
#define USB1_PORTSC1_D_PTS_Pos                                30                                                        /*!< USB1 PORTSC1_D: PTS Position        */
#define USB1_PORTSC1_D_PTS_Msk                                (0x03UL << USB1_PORTSC1_D_PTS_Pos)                        /*!< USB1 PORTSC1_D: PTS Mask            */

// -------------------------------------  USB1_PORTSC1_H  -----------------------------------------
#define USB1_PORTSC1_H_CCS_Pos                                0                                                         /*!< USB1 PORTSC1_H: CCS Position        */
#define USB1_PORTSC1_H_CCS_Msk                                (0x01UL << USB1_PORTSC1_H_CCS_Pos)                        /*!< USB1 PORTSC1_H: CCS Mask            */
#define USB1_PORTSC1_H_CSC_Pos                                1                                                         /*!< USB1 PORTSC1_H: CSC Position        */
#define USB1_PORTSC1_H_CSC_Msk                                (0x01UL << USB1_PORTSC1_H_CSC_Pos)                        /*!< USB1 PORTSC1_H: CSC Mask            */
#define USB1_PORTSC1_H_PE_Pos                                 2                                                         /*!< USB1 PORTSC1_H: PE Position         */
#define USB1_PORTSC1_H_PE_Msk                                 (0x01UL << USB1_PORTSC1_H_PE_Pos)                         /*!< USB1 PORTSC1_H: PE Mask             */
#define USB1_PORTSC1_H_PEC_Pos                                3                                                         /*!< USB1 PORTSC1_H: PEC Position        */
#define USB1_PORTSC1_H_PEC_Msk                                (0x01UL << USB1_PORTSC1_H_PEC_Pos)                        /*!< USB1 PORTSC1_H: PEC Mask            */
#define USB1_PORTSC1_H_OCA_Pos                                4                                                         /*!< USB1 PORTSC1_H: OCA Position        */
#define USB1_PORTSC1_H_OCA_Msk                                (0x01UL << USB1_PORTSC1_H_OCA_Pos)                        /*!< USB1 PORTSC1_H: OCA Mask            */
#define USB1_PORTSC1_H_OCC_Pos                                5                                                         /*!< USB1 PORTSC1_H: OCC Position        */
#define USB1_PORTSC1_H_OCC_Msk                                (0x01UL << USB1_PORTSC1_H_OCC_Pos)                        /*!< USB1 PORTSC1_H: OCC Mask            */
#define USB1_PORTSC1_H_FPR_Pos                                6                                                         /*!< USB1 PORTSC1_H: FPR Position        */
#define USB1_PORTSC1_H_FPR_Msk                                (0x01UL << USB1_PORTSC1_H_FPR_Pos)                        /*!< USB1 PORTSC1_H: FPR Mask            */
#define USB1_PORTSC1_H_SUSP_Pos                               7                                                         /*!< USB1 PORTSC1_H: SUSP Position       */
#define USB1_PORTSC1_H_SUSP_Msk                               (0x01UL << USB1_PORTSC1_H_SUSP_Pos)                       /*!< USB1 PORTSC1_H: SUSP Mask           */
#define USB1_PORTSC1_H_PR_Pos                                 8                                                         /*!< USB1 PORTSC1_H: PR Position         */
#define USB1_PORTSC1_H_PR_Msk                                 (0x01UL << USB1_PORTSC1_H_PR_Pos)                         /*!< USB1 PORTSC1_H: PR Mask             */
#define USB1_PORTSC1_H_HSP_Pos                                9                                                         /*!< USB1 PORTSC1_H: HSP Position        */
#define USB1_PORTSC1_H_HSP_Msk                                (0x01UL << USB1_PORTSC1_H_HSP_Pos)                        /*!< USB1 PORTSC1_H: HSP Mask            */
#define USB1_PORTSC1_H_LS_Pos                                 10                                                        /*!< USB1 PORTSC1_H: LS Position         */
#define USB1_PORTSC1_H_LS_Msk                                 (0x03UL << USB1_PORTSC1_H_LS_Pos)                         /*!< USB1 PORTSC1_H: LS Mask             */
#define USB1_PORTSC1_H_PP_Pos                                 12                                                        /*!< USB1 PORTSC1_H: PP Position         */
#define USB1_PORTSC1_H_PP_Msk                                 (0x01UL << USB1_PORTSC1_H_PP_Pos)                         /*!< USB1 PORTSC1_H: PP Mask             */
#define USB1_PORTSC1_H_PIC1_0_Pos                             14                                                        /*!< USB1 PORTSC1_H: PIC1_0 Position     */
#define USB1_PORTSC1_H_PIC1_0_Msk                             (0x03UL << USB1_PORTSC1_H_PIC1_0_Pos)                     /*!< USB1 PORTSC1_H: PIC1_0 Mask         */
#define USB1_PORTSC1_H_PTC3_0_Pos                             16                                                        /*!< USB1 PORTSC1_H: PTC3_0 Position     */
#define USB1_PORTSC1_H_PTC3_0_Msk                             (0x0fUL << USB1_PORTSC1_H_PTC3_0_Pos)                     /*!< USB1 PORTSC1_H: PTC3_0 Mask         */
#define USB1_PORTSC1_H_WKCN_Pos                               20                                                        /*!< USB1 PORTSC1_H: WKCN Position       */
#define USB1_PORTSC1_H_WKCN_Msk                               (0x01UL << USB1_PORTSC1_H_WKCN_Pos)                       /*!< USB1 PORTSC1_H: WKCN Mask           */
#define USB1_PORTSC1_H_WKDC_Pos                               21                                                        /*!< USB1 PORTSC1_H: WKDC Position       */
#define USB1_PORTSC1_H_WKDC_Msk                               (0x01UL << USB1_PORTSC1_H_WKDC_Pos)                       /*!< USB1 PORTSC1_H: WKDC Mask           */
#define USB1_PORTSC1_H_WKOC_Pos                               22                                                        /*!< USB1 PORTSC1_H: WKOC Position       */
#define USB1_PORTSC1_H_WKOC_Msk                               (0x01UL << USB1_PORTSC1_H_WKOC_Pos)                       /*!< USB1 PORTSC1_H: WKOC Mask           */
#define USB1_PORTSC1_H_PHCD_Pos                               23                                                        /*!< USB1 PORTSC1_H: PHCD Position       */
#define USB1_PORTSC1_H_PHCD_Msk                               (0x01UL << USB1_PORTSC1_H_PHCD_Pos)                       /*!< USB1 PORTSC1_H: PHCD Mask           */
#define USB1_PORTSC1_H_PFSC_Pos                               24                                                        /*!< USB1 PORTSC1_H: PFSC Position       */
#define USB1_PORTSC1_H_PFSC_Msk                               (0x01UL << USB1_PORTSC1_H_PFSC_Pos)                       /*!< USB1 PORTSC1_H: PFSC Mask           */
#define USB1_PORTSC1_H_PSPD_Pos                               26                                                        /*!< USB1 PORTSC1_H: PSPD Position       */
#define USB1_PORTSC1_H_PSPD_Msk                               (0x03UL << USB1_PORTSC1_H_PSPD_Pos)                       /*!< USB1 PORTSC1_H: PSPD Mask           */
#define USB1_PORTSC1_H_PTS_Pos                                30                                                        /*!< USB1 PORTSC1_H: PTS Position        */
#define USB1_PORTSC1_H_PTS_Msk                                (0x03UL << USB1_PORTSC1_H_PTS_Pos)                        /*!< USB1 PORTSC1_H: PTS Mask            */

// -------------------------------------  USB1_USBMODE_D  -----------------------------------------
#define USB1_USBMODE_D_CM1_0_Pos                              0                                                         /*!< USB1 USBMODE_D: CM1_0 Position      */
#define USB1_USBMODE_D_CM1_0_Msk                              (0x03UL << USB1_USBMODE_D_CM1_0_Pos)                      /*!< USB1 USBMODE_D: CM1_0 Mask          */
#define USB1_USBMODE_D_ES_Pos                                 2                                                         /*!< USB1 USBMODE_D: ES Position         */
#define USB1_USBMODE_D_ES_Msk                                 (0x01UL << USB1_USBMODE_D_ES_Pos)                         /*!< USB1 USBMODE_D: ES Mask             */
#define USB1_USBMODE_D_SLOM_Pos                               3                                                         /*!< USB1 USBMODE_D: SLOM Position       */
#define USB1_USBMODE_D_SLOM_Msk                               (0x01UL << USB1_USBMODE_D_SLOM_Pos)                       /*!< USB1 USBMODE_D: SLOM Mask           */
#define USB1_USBMODE_D_SDIS_Pos                               4                                                         /*!< USB1 USBMODE_D: SDIS Position       */
#define USB1_USBMODE_D_SDIS_Msk                               (0x01UL << USB1_USBMODE_D_SDIS_Pos)                       /*!< USB1 USBMODE_D: SDIS Mask           */

// -------------------------------------  USB1_USBMODE_H  -----------------------------------------
#define USB1_USBMODE_H_CM1_0_Pos                              0                                                         /*!< USB1 USBMODE_H: CM1_0 Position      */
#define USB1_USBMODE_H_CM1_0_Msk                              (0x03UL << USB1_USBMODE_H_CM1_0_Pos)                      /*!< USB1 USBMODE_H: CM1_0 Mask          */
#define USB1_USBMODE_H_ES_Pos                                 2                                                         /*!< USB1 USBMODE_H: ES Position         */
#define USB1_USBMODE_H_ES_Msk                                 (0x01UL << USB1_USBMODE_H_ES_Pos)                         /*!< USB1 USBMODE_H: ES Mask             */
#define USB1_USBMODE_H_SDIS_Pos                               4                                                         /*!< USB1 USBMODE_H: SDIS Position       */
#define USB1_USBMODE_H_SDIS_Msk                               (0x01UL << USB1_USBMODE_H_SDIS_Pos)                       /*!< USB1 USBMODE_H: SDIS Mask           */
#define USB1_USBMODE_H_VBPS_Pos                               5                                                         /*!< USB1 USBMODE_H: VBPS Position       */
#define USB1_USBMODE_H_VBPS_Msk                               (0x01UL << USB1_USBMODE_H_VBPS_Pos)                       /*!< USB1 USBMODE_H: VBPS Mask           */

// -----------------------------------  USB1_ENDPTSETUPSTAT  --------------------------------------
#define USB1_ENDPTSETUPSTAT_ENDPTSETUPSTAT0_Pos               0                                                         /*!< USB1 ENDPTSETUPSTAT: ENDPTSETUPSTAT0 Position */
#define USB1_ENDPTSETUPSTAT_ENDPTSETUPSTAT0_Msk               (0x01UL << USB1_ENDPTSETUPSTAT_ENDPTSETUPSTAT0_Pos)       /*!< USB1 ENDPTSETUPSTAT: ENDPTSETUPSTAT0 Mask */
#define USB1_ENDPTSETUPSTAT_ENDPTSETUPSTAT1_Pos               1                                                         /*!< USB1 ENDPTSETUPSTAT: ENDPTSETUPSTAT1 Position */
#define USB1_ENDPTSETUPSTAT_ENDPTSETUPSTAT1_Msk               (0x01UL << USB1_ENDPTSETUPSTAT_ENDPTSETUPSTAT1_Pos)       /*!< USB1 ENDPTSETUPSTAT: ENDPTSETUPSTAT1 Mask */
#define USB1_ENDPTSETUPSTAT_ENDPTSETUPSTAT2_Pos               2                                                         /*!< USB1 ENDPTSETUPSTAT: ENDPTSETUPSTAT2 Position */
#define USB1_ENDPTSETUPSTAT_ENDPTSETUPSTAT2_Msk               (0x01UL << USB1_ENDPTSETUPSTAT_ENDPTSETUPSTAT2_Pos)       /*!< USB1 ENDPTSETUPSTAT: ENDPTSETUPSTAT2 Mask */
#define USB1_ENDPTSETUPSTAT_ENDPTSETUPSTAT3_Pos               3                                                         /*!< USB1 ENDPTSETUPSTAT: ENDPTSETUPSTAT3 Position */
#define USB1_ENDPTSETUPSTAT_ENDPTSETUPSTAT3_Msk               (0x01UL << USB1_ENDPTSETUPSTAT_ENDPTSETUPSTAT3_Pos)       /*!< USB1 ENDPTSETUPSTAT: ENDPTSETUPSTAT3 Mask */

// -------------------------------------  USB1_ENDPTPRIME  ----------------------------------------
#define USB1_ENDPTPRIME_PERB0_Pos                             0                                                         /*!< USB1 ENDPTPRIME: PERB0 Position     */
#define USB1_ENDPTPRIME_PERB0_Msk                             (0x01UL << USB1_ENDPTPRIME_PERB0_Pos)                     /*!< USB1 ENDPTPRIME: PERB0 Mask         */
#define USB1_ENDPTPRIME_PERB1_Pos                             1                                                         /*!< USB1 ENDPTPRIME: PERB1 Position     */
#define USB1_ENDPTPRIME_PERB1_Msk                             (0x01UL << USB1_ENDPTPRIME_PERB1_Pos)                     /*!< USB1 ENDPTPRIME: PERB1 Mask         */
#define USB1_ENDPTPRIME_PERB2_Pos                             2                                                         /*!< USB1 ENDPTPRIME: PERB2 Position     */
#define USB1_ENDPTPRIME_PERB2_Msk                             (0x01UL << USB1_ENDPTPRIME_PERB2_Pos)                     /*!< USB1 ENDPTPRIME: PERB2 Mask         */
#define USB1_ENDPTPRIME_PERB3_Pos                             3                                                         /*!< USB1 ENDPTPRIME: PERB3 Position     */
#define USB1_ENDPTPRIME_PERB3_Msk                             (0x01UL << USB1_ENDPTPRIME_PERB3_Pos)                     /*!< USB1 ENDPTPRIME: PERB3 Mask         */
#define USB1_ENDPTPRIME_PETB0_Pos                             16                                                        /*!< USB1 ENDPTPRIME: PETB0 Position     */
#define USB1_ENDPTPRIME_PETB0_Msk                             (0x01UL << USB1_ENDPTPRIME_PETB0_Pos)                     /*!< USB1 ENDPTPRIME: PETB0 Mask         */
#define USB1_ENDPTPRIME_PETB1_Pos                             17                                                        /*!< USB1 ENDPTPRIME: PETB1 Position     */
#define USB1_ENDPTPRIME_PETB1_Msk                             (0x01UL << USB1_ENDPTPRIME_PETB1_Pos)                     /*!< USB1 ENDPTPRIME: PETB1 Mask         */
#define USB1_ENDPTPRIME_PETB2_Pos                             18                                                        /*!< USB1 ENDPTPRIME: PETB2 Position     */
#define USB1_ENDPTPRIME_PETB2_Msk                             (0x01UL << USB1_ENDPTPRIME_PETB2_Pos)                     /*!< USB1 ENDPTPRIME: PETB2 Mask         */
#define USB1_ENDPTPRIME_PETB3_Pos                             19                                                        /*!< USB1 ENDPTPRIME: PETB3 Position     */
#define USB1_ENDPTPRIME_PETB3_Msk                             (0x01UL << USB1_ENDPTPRIME_PETB3_Pos)                     /*!< USB1 ENDPTPRIME: PETB3 Mask         */

// -------------------------------------  USB1_ENDPTFLUSH  ----------------------------------------
#define USB1_ENDPTFLUSH_FERB0_Pos                             0                                                         /*!< USB1 ENDPTFLUSH: FERB0 Position     */
#define USB1_ENDPTFLUSH_FERB0_Msk                             (0x01UL << USB1_ENDPTFLUSH_FERB0_Pos)                     /*!< USB1 ENDPTFLUSH: FERB0 Mask         */
#define USB1_ENDPTFLUSH_FERB1_Pos                             1                                                         /*!< USB1 ENDPTFLUSH: FERB1 Position     */
#define USB1_ENDPTFLUSH_FERB1_Msk                             (0x01UL << USB1_ENDPTFLUSH_FERB1_Pos)                     /*!< USB1 ENDPTFLUSH: FERB1 Mask         */
#define USB1_ENDPTFLUSH_FERB2_Pos                             2                                                         /*!< USB1 ENDPTFLUSH: FERB2 Position     */
#define USB1_ENDPTFLUSH_FERB2_Msk                             (0x01UL << USB1_ENDPTFLUSH_FERB2_Pos)                     /*!< USB1 ENDPTFLUSH: FERB2 Mask         */
#define USB1_ENDPTFLUSH_FERB3_Pos                             3                                                         /*!< USB1 ENDPTFLUSH: FERB3 Position     */
#define USB1_ENDPTFLUSH_FERB3_Msk                             (0x01UL << USB1_ENDPTFLUSH_FERB3_Pos)                     /*!< USB1 ENDPTFLUSH: FERB3 Mask         */
#define USB1_ENDPTFLUSH_FETB0_Pos                             16                                                        /*!< USB1 ENDPTFLUSH: FETB0 Position     */
#define USB1_ENDPTFLUSH_FETB0_Msk                             (0x01UL << USB1_ENDPTFLUSH_FETB0_Pos)                     /*!< USB1 ENDPTFLUSH: FETB0 Mask         */
#define USB1_ENDPTFLUSH_FETB1_Pos                             17                                                        /*!< USB1 ENDPTFLUSH: FETB1 Position     */
#define USB1_ENDPTFLUSH_FETB1_Msk                             (0x01UL << USB1_ENDPTFLUSH_FETB1_Pos)                     /*!< USB1 ENDPTFLUSH: FETB1 Mask         */
#define USB1_ENDPTFLUSH_FETB2_Pos                             18                                                        /*!< USB1 ENDPTFLUSH: FETB2 Position     */
#define USB1_ENDPTFLUSH_FETB2_Msk                             (0x01UL << USB1_ENDPTFLUSH_FETB2_Pos)                     /*!< USB1 ENDPTFLUSH: FETB2 Mask         */
#define USB1_ENDPTFLUSH_FETB3_Pos                             19                                                        /*!< USB1 ENDPTFLUSH: FETB3 Position     */
#define USB1_ENDPTFLUSH_FETB3_Msk                             (0x01UL << USB1_ENDPTFLUSH_FETB3_Pos)                     /*!< USB1 ENDPTFLUSH: FETB3 Mask         */

// -------------------------------------  USB1_ENDPTSTAT  -----------------------------------------
#define USB1_ENDPTSTAT_ERBR0_Pos                              0                                                         /*!< USB1 ENDPTSTAT: ERBR0 Position      */
#define USB1_ENDPTSTAT_ERBR0_Msk                              (0x01UL << USB1_ENDPTSTAT_ERBR0_Pos)                      /*!< USB1 ENDPTSTAT: ERBR0 Mask          */
#define USB1_ENDPTSTAT_ERBR1_Pos                              1                                                         /*!< USB1 ENDPTSTAT: ERBR1 Position      */
#define USB1_ENDPTSTAT_ERBR1_Msk                              (0x01UL << USB1_ENDPTSTAT_ERBR1_Pos)                      /*!< USB1 ENDPTSTAT: ERBR1 Mask          */
#define USB1_ENDPTSTAT_ERBR2_Pos                              2                                                         /*!< USB1 ENDPTSTAT: ERBR2 Position      */
#define USB1_ENDPTSTAT_ERBR2_Msk                              (0x01UL << USB1_ENDPTSTAT_ERBR2_Pos)                      /*!< USB1 ENDPTSTAT: ERBR2 Mask          */
#define USB1_ENDPTSTAT_ERBR3_Pos                              3                                                         /*!< USB1 ENDPTSTAT: ERBR3 Position      */
#define USB1_ENDPTSTAT_ERBR3_Msk                              (0x01UL << USB1_ENDPTSTAT_ERBR3_Pos)                      /*!< USB1 ENDPTSTAT: ERBR3 Mask          */
#define USB1_ENDPTSTAT_ETBR0_Pos                              16                                                        /*!< USB1 ENDPTSTAT: ETBR0 Position      */
#define USB1_ENDPTSTAT_ETBR0_Msk                              (0x01UL << USB1_ENDPTSTAT_ETBR0_Pos)                      /*!< USB1 ENDPTSTAT: ETBR0 Mask          */
#define USB1_ENDPTSTAT_ETBR1_Pos                              17                                                        /*!< USB1 ENDPTSTAT: ETBR1 Position      */
#define USB1_ENDPTSTAT_ETBR1_Msk                              (0x01UL << USB1_ENDPTSTAT_ETBR1_Pos)                      /*!< USB1 ENDPTSTAT: ETBR1 Mask          */
#define USB1_ENDPTSTAT_ETBR2_Pos                              18                                                        /*!< USB1 ENDPTSTAT: ETBR2 Position      */
#define USB1_ENDPTSTAT_ETBR2_Msk                              (0x01UL << USB1_ENDPTSTAT_ETBR2_Pos)                      /*!< USB1 ENDPTSTAT: ETBR2 Mask          */
#define USB1_ENDPTSTAT_ETBR3_Pos                              19                                                        /*!< USB1 ENDPTSTAT: ETBR3 Position      */
#define USB1_ENDPTSTAT_ETBR3_Msk                              (0x01UL << USB1_ENDPTSTAT_ETBR3_Pos)                      /*!< USB1 ENDPTSTAT: ETBR3 Mask          */

// -----------------------------------  USB1_ENDPTCOMPLETE  ---------------------------------------
#define USB1_ENDPTCOMPLETE_ERCE0_Pos                          0                                                         /*!< USB1 ENDPTCOMPLETE: ERCE0 Position  */
#define USB1_ENDPTCOMPLETE_ERCE0_Msk                          (0x01UL << USB1_ENDPTCOMPLETE_ERCE0_Pos)                  /*!< USB1 ENDPTCOMPLETE: ERCE0 Mask      */
#define USB1_ENDPTCOMPLETE_ERCE1_Pos                          1                                                         /*!< USB1 ENDPTCOMPLETE: ERCE1 Position  */
#define USB1_ENDPTCOMPLETE_ERCE1_Msk                          (0x01UL << USB1_ENDPTCOMPLETE_ERCE1_Pos)                  /*!< USB1 ENDPTCOMPLETE: ERCE1 Mask      */
#define USB1_ENDPTCOMPLETE_ERCE2_Pos                          2                                                         /*!< USB1 ENDPTCOMPLETE: ERCE2 Position  */
#define USB1_ENDPTCOMPLETE_ERCE2_Msk                          (0x01UL << USB1_ENDPTCOMPLETE_ERCE2_Pos)                  /*!< USB1 ENDPTCOMPLETE: ERCE2 Mask      */
#define USB1_ENDPTCOMPLETE_ERCE3_Pos                          3                                                         /*!< USB1 ENDPTCOMPLETE: ERCE3 Position  */
#define USB1_ENDPTCOMPLETE_ERCE3_Msk                          (0x01UL << USB1_ENDPTCOMPLETE_ERCE3_Pos)                  /*!< USB1 ENDPTCOMPLETE: ERCE3 Mask      */
#define USB1_ENDPTCOMPLETE_ETCE0_Pos                          16                                                        /*!< USB1 ENDPTCOMPLETE: ETCE0 Position  */
#define USB1_ENDPTCOMPLETE_ETCE0_Msk                          (0x01UL << USB1_ENDPTCOMPLETE_ETCE0_Pos)                  /*!< USB1 ENDPTCOMPLETE: ETCE0 Mask      */
#define USB1_ENDPTCOMPLETE_ETCE1_Pos                          17                                                        /*!< USB1 ENDPTCOMPLETE: ETCE1 Position  */
#define USB1_ENDPTCOMPLETE_ETCE1_Msk                          (0x01UL << USB1_ENDPTCOMPLETE_ETCE1_Pos)                  /*!< USB1 ENDPTCOMPLETE: ETCE1 Mask      */
#define USB1_ENDPTCOMPLETE_ETCE2_Pos                          18                                                        /*!< USB1 ENDPTCOMPLETE: ETCE2 Position  */
#define USB1_ENDPTCOMPLETE_ETCE2_Msk                          (0x01UL << USB1_ENDPTCOMPLETE_ETCE2_Pos)                  /*!< USB1 ENDPTCOMPLETE: ETCE2 Mask      */
#define USB1_ENDPTCOMPLETE_ETCE3_Pos                          19                                                        /*!< USB1 ENDPTCOMPLETE: ETCE3 Position  */
#define USB1_ENDPTCOMPLETE_ETCE3_Msk                          (0x01UL << USB1_ENDPTCOMPLETE_ETCE3_Pos)                  /*!< USB1 ENDPTCOMPLETE: ETCE3 Mask      */

// -------------------------------------  USB1_ENDPTCTRL0  ----------------------------------------
#define USB1_ENDPTCTRL0_RXS_Pos                               0                                                         /*!< USB1 ENDPTCTRL0: RXS Position       */
#define USB1_ENDPTCTRL0_RXS_Msk                               (0x01UL << USB1_ENDPTCTRL0_RXS_Pos)                       /*!< USB1 ENDPTCTRL0: RXS Mask           */
#define USB1_ENDPTCTRL0_RXT_Pos                               2                                                         /*!< USB1 ENDPTCTRL0: RXT Position       */
#define USB1_ENDPTCTRL0_RXT_Msk                               (0x03UL << USB1_ENDPTCTRL0_RXT_Pos)                       /*!< USB1 ENDPTCTRL0: RXT Mask           */
#define USB1_ENDPTCTRL0_RXE_Pos                               7                                                         /*!< USB1 ENDPTCTRL0: RXE Position       */
#define USB1_ENDPTCTRL0_RXE_Msk                               (0x01UL << USB1_ENDPTCTRL0_RXE_Pos)                       /*!< USB1 ENDPTCTRL0: RXE Mask           */
#define USB1_ENDPTCTRL0_TXS_Pos                               16                                                        /*!< USB1 ENDPTCTRL0: TXS Position       */
#define USB1_ENDPTCTRL0_TXS_Msk                               (0x01UL << USB1_ENDPTCTRL0_TXS_Pos)                       /*!< USB1 ENDPTCTRL0: TXS Mask           */
#define USB1_ENDPTCTRL0_TXT_Pos                               18                                                        /*!< USB1 ENDPTCTRL0: TXT Position       */
#define USB1_ENDPTCTRL0_TXT_Msk                               (0x03UL << USB1_ENDPTCTRL0_TXT_Pos)                       /*!< USB1 ENDPTCTRL0: TXT Mask           */
#define USB1_ENDPTCTRL0_TXE_Pos                               23                                                        /*!< USB1 ENDPTCTRL0: TXE Position       */
#define USB1_ENDPTCTRL0_TXE_Msk                               (0x01UL << USB1_ENDPTCTRL0_TXE_Pos)                       /*!< USB1 ENDPTCTRL0: TXE Mask           */

// -------------------------------------  USB1_ENDPTCTRL1  ----------------------------------------
#define USB1_ENDPTCTRL1_RXS_Pos                               0                                                         /*!< USB1 ENDPTCTRL1: RXS Position       */
#define USB1_ENDPTCTRL1_RXS_Msk                               (0x01UL << USB1_ENDPTCTRL1_RXS_Pos)                       /*!< USB1 ENDPTCTRL1: RXS Mask           */
#define USB1_ENDPTCTRL1_RXT_Pos                               2                                                         /*!< USB1 ENDPTCTRL1: RXT Position       */
#define USB1_ENDPTCTRL1_RXT_Msk                               (0x03UL << USB1_ENDPTCTRL1_RXT_Pos)                       /*!< USB1 ENDPTCTRL1: RXT Mask           */
#define USB1_ENDPTCTRL1_RXI_Pos                               5                                                         /*!< USB1 ENDPTCTRL1: RXI Position       */
#define USB1_ENDPTCTRL1_RXI_Msk                               (0x01UL << USB1_ENDPTCTRL1_RXI_Pos)                       /*!< USB1 ENDPTCTRL1: RXI Mask           */
#define USB1_ENDPTCTRL1_RXR_Pos                               6                                                         /*!< USB1 ENDPTCTRL1: RXR Position       */
#define USB1_ENDPTCTRL1_RXR_Msk                               (0x01UL << USB1_ENDPTCTRL1_RXR_Pos)                       /*!< USB1 ENDPTCTRL1: RXR Mask           */
#define USB1_ENDPTCTRL1_RXE_Pos                               7                                                         /*!< USB1 ENDPTCTRL1: RXE Position       */
#define USB1_ENDPTCTRL1_RXE_Msk                               (0x01UL << USB1_ENDPTCTRL1_RXE_Pos)                       /*!< USB1 ENDPTCTRL1: RXE Mask           */
#define USB1_ENDPTCTRL1_TXS_Pos                               16                                                        /*!< USB1 ENDPTCTRL1: TXS Position       */
#define USB1_ENDPTCTRL1_TXS_Msk                               (0x01UL << USB1_ENDPTCTRL1_TXS_Pos)                       /*!< USB1 ENDPTCTRL1: TXS Mask           */
#define USB1_ENDPTCTRL1_TXT_Pos                               18                                                        /*!< USB1 ENDPTCTRL1: TXT Position       */
#define USB1_ENDPTCTRL1_TXT_Msk                               (0x03UL << USB1_ENDPTCTRL1_TXT_Pos)                       /*!< USB1 ENDPTCTRL1: TXT Mask           */
#define USB1_ENDPTCTRL1_TXI_Pos                               21                                                        /*!< USB1 ENDPTCTRL1: TXI Position       */
#define USB1_ENDPTCTRL1_TXI_Msk                               (0x01UL << USB1_ENDPTCTRL1_TXI_Pos)                       /*!< USB1 ENDPTCTRL1: TXI Mask           */
#define USB1_ENDPTCTRL1_TXR_Pos                               22                                                        /*!< USB1 ENDPTCTRL1: TXR Position       */
#define USB1_ENDPTCTRL1_TXR_Msk                               (0x01UL << USB1_ENDPTCTRL1_TXR_Pos)                       /*!< USB1 ENDPTCTRL1: TXR Mask           */
#define USB1_ENDPTCTRL1_TXE_Pos                               23                                                        /*!< USB1 ENDPTCTRL1: TXE Position       */
#define USB1_ENDPTCTRL1_TXE_Msk                               (0x01UL << USB1_ENDPTCTRL1_TXE_Pos)                       /*!< USB1 ENDPTCTRL1: TXE Mask           */

// -------------------------------------  USB1_ENDPTCTRL2  ----------------------------------------
#define USB1_ENDPTCTRL2_RXS_Pos                               0                                                         /*!< USB1 ENDPTCTRL2: RXS Position       */
#define USB1_ENDPTCTRL2_RXS_Msk                               (0x01UL << USB1_ENDPTCTRL2_RXS_Pos)                       /*!< USB1 ENDPTCTRL2: RXS Mask           */
#define USB1_ENDPTCTRL2_RXT_Pos                               2                                                         /*!< USB1 ENDPTCTRL2: RXT Position       */
#define USB1_ENDPTCTRL2_RXT_Msk                               (0x03UL << USB1_ENDPTCTRL2_RXT_Pos)                       /*!< USB1 ENDPTCTRL2: RXT Mask           */
#define USB1_ENDPTCTRL2_RXI_Pos                               5                                                         /*!< USB1 ENDPTCTRL2: RXI Position       */
#define USB1_ENDPTCTRL2_RXI_Msk                               (0x01UL << USB1_ENDPTCTRL2_RXI_Pos)                       /*!< USB1 ENDPTCTRL2: RXI Mask           */
#define USB1_ENDPTCTRL2_RXR_Pos                               6                                                         /*!< USB1 ENDPTCTRL2: RXR Position       */
#define USB1_ENDPTCTRL2_RXR_Msk                               (0x01UL << USB1_ENDPTCTRL2_RXR_Pos)                       /*!< USB1 ENDPTCTRL2: RXR Mask           */
#define USB1_ENDPTCTRL2_RXE_Pos                               7                                                         /*!< USB1 ENDPTCTRL2: RXE Position       */
#define USB1_ENDPTCTRL2_RXE_Msk                               (0x01UL << USB1_ENDPTCTRL2_RXE_Pos)                       /*!< USB1 ENDPTCTRL2: RXE Mask           */
#define USB1_ENDPTCTRL2_TXS_Pos                               16                                                        /*!< USB1 ENDPTCTRL2: TXS Position       */
#define USB1_ENDPTCTRL2_TXS_Msk                               (0x01UL << USB1_ENDPTCTRL2_TXS_Pos)                       /*!< USB1 ENDPTCTRL2: TXS Mask           */
#define USB1_ENDPTCTRL2_TXT_Pos                               18                                                        /*!< USB1 ENDPTCTRL2: TXT Position       */
#define USB1_ENDPTCTRL2_TXT_Msk                               (0x03UL << USB1_ENDPTCTRL2_TXT_Pos)                       /*!< USB1 ENDPTCTRL2: TXT Mask           */
#define USB1_ENDPTCTRL2_TXI_Pos                               21                                                        /*!< USB1 ENDPTCTRL2: TXI Position       */
#define USB1_ENDPTCTRL2_TXI_Msk                               (0x01UL << USB1_ENDPTCTRL2_TXI_Pos)                       /*!< USB1 ENDPTCTRL2: TXI Mask           */
#define USB1_ENDPTCTRL2_TXR_Pos                               22                                                        /*!< USB1 ENDPTCTRL2: TXR Position       */
#define USB1_ENDPTCTRL2_TXR_Msk                               (0x01UL << USB1_ENDPTCTRL2_TXR_Pos)                       /*!< USB1 ENDPTCTRL2: TXR Mask           */
#define USB1_ENDPTCTRL2_TXE_Pos                               23                                                        /*!< USB1 ENDPTCTRL2: TXE Position       */
#define USB1_ENDPTCTRL2_TXE_Msk                               (0x01UL << USB1_ENDPTCTRL2_TXE_Pos)                       /*!< USB1 ENDPTCTRL2: TXE Mask           */

// -------------------------------------  USB1_ENDPTCTRL3  ----------------------------------------
#define USB1_ENDPTCTRL3_RXS_Pos                               0                                                         /*!< USB1 ENDPTCTRL3: RXS Position       */
#define USB1_ENDPTCTRL3_RXS_Msk                               (0x01UL << USB1_ENDPTCTRL3_RXS_Pos)                       /*!< USB1 ENDPTCTRL3: RXS Mask           */
#define USB1_ENDPTCTRL3_RXT_Pos                               2                                                         /*!< USB1 ENDPTCTRL3: RXT Position       */
#define USB1_ENDPTCTRL3_RXT_Msk                               (0x03UL << USB1_ENDPTCTRL3_RXT_Pos)                       /*!< USB1 ENDPTCTRL3: RXT Mask           */
#define USB1_ENDPTCTRL3_RXI_Pos                               5                                                         /*!< USB1 ENDPTCTRL3: RXI Position       */
#define USB1_ENDPTCTRL3_RXI_Msk                               (0x01UL << USB1_ENDPTCTRL3_RXI_Pos)                       /*!< USB1 ENDPTCTRL3: RXI Mask           */
#define USB1_ENDPTCTRL3_RXR_Pos                               6                                                         /*!< USB1 ENDPTCTRL3: RXR Position       */
#define USB1_ENDPTCTRL3_RXR_Msk                               (0x01UL << USB1_ENDPTCTRL3_RXR_Pos)                       /*!< USB1 ENDPTCTRL3: RXR Mask           */
#define USB1_ENDPTCTRL3_RXE_Pos                               7                                                         /*!< USB1 ENDPTCTRL3: RXE Position       */
#define USB1_ENDPTCTRL3_RXE_Msk                               (0x01UL << USB1_ENDPTCTRL3_RXE_Pos)                       /*!< USB1 ENDPTCTRL3: RXE Mask           */
#define USB1_ENDPTCTRL3_TXS_Pos                               16                                                        /*!< USB1 ENDPTCTRL3: TXS Position       */
#define USB1_ENDPTCTRL3_TXS_Msk                               (0x01UL << USB1_ENDPTCTRL3_TXS_Pos)                       /*!< USB1 ENDPTCTRL3: TXS Mask           */
#define USB1_ENDPTCTRL3_TXT_Pos                               18                                                        /*!< USB1 ENDPTCTRL3: TXT Position       */
#define USB1_ENDPTCTRL3_TXT_Msk                               (0x03UL << USB1_ENDPTCTRL3_TXT_Pos)                       /*!< USB1 ENDPTCTRL3: TXT Mask           */
#define USB1_ENDPTCTRL3_TXI_Pos                               21                                                        /*!< USB1 ENDPTCTRL3: TXI Position       */
#define USB1_ENDPTCTRL3_TXI_Msk                               (0x01UL << USB1_ENDPTCTRL3_TXI_Pos)                       /*!< USB1 ENDPTCTRL3: TXI Mask           */
#define USB1_ENDPTCTRL3_TXR_Pos                               22                                                        /*!< USB1 ENDPTCTRL3: TXR Position       */
#define USB1_ENDPTCTRL3_TXR_Msk                               (0x01UL << USB1_ENDPTCTRL3_TXR_Pos)                       /*!< USB1 ENDPTCTRL3: TXR Mask           */
#define USB1_ENDPTCTRL3_TXE_Pos                               23                                                        /*!< USB1 ENDPTCTRL3: TXE Position       */
#define USB1_ENDPTCTRL3_TXE_Msk                               (0x01UL << USB1_ENDPTCTRL3_TXE_Pos)                       /*!< USB1 ENDPTCTRL3: TXE Mask           */


// ------------------------------------------------------------------------------------------------
// -----                                  LCD Position & Mask                                 -----
// ------------------------------------------------------------------------------------------------


// ----------------------------------------  LCD_TIMH  --------------------------------------------
#define LCD_TIMH_PPL_Pos                                      2                                                         /*!< LCD TIMH: PPL Position              */
#define LCD_TIMH_PPL_Msk                                      (0x3fUL << LCD_TIMH_PPL_Pos)                              /*!< LCD TIMH: PPL Mask                  */
#define LCD_TIMH_HSW_Pos                                      8                                                         /*!< LCD TIMH: HSW Position              */
#define LCD_TIMH_HSW_Msk                                      (0x000000ffUL << LCD_TIMH_HSW_Pos)                        /*!< LCD TIMH: HSW Mask                  */
#define LCD_TIMH_HFP_Pos                                      16                                                        /*!< LCD TIMH: HFP Position              */
#define LCD_TIMH_HFP_Msk                                      (0x000000ffUL << LCD_TIMH_HFP_Pos)                        /*!< LCD TIMH: HFP Mask                  */
#define LCD_TIMH_HBP_Pos                                      24                                                        /*!< LCD TIMH: HBP Position              */
#define LCD_TIMH_HBP_Msk                                      (0x000000ffUL << LCD_TIMH_HBP_Pos)                        /*!< LCD TIMH: HBP Mask                  */

// ----------------------------------------  LCD_TIMV  --------------------------------------------
#define LCD_TIMV_LPP_Pos                                      0                                                         /*!< LCD TIMV: LPP Position              */
#define LCD_TIMV_LPP_Msk                                      (0x000003ffUL << LCD_TIMV_LPP_Pos)                        /*!< LCD TIMV: LPP Mask                  */
#define LCD_TIMV_VSW_Pos                                      10                                                        /*!< LCD TIMV: VSW Position              */
#define LCD_TIMV_VSW_Msk                                      (0x3fUL << LCD_TIMV_VSW_Pos)                              /*!< LCD TIMV: VSW Mask                  */
#define LCD_TIMV_VFP_Pos                                      16                                                        /*!< LCD TIMV: VFP Position              */
#define LCD_TIMV_VFP_Msk                                      (0x000000ffUL << LCD_TIMV_VFP_Pos)                        /*!< LCD TIMV: VFP Mask                  */
#define LCD_TIMV_VBP_Pos                                      24                                                        /*!< LCD TIMV: VBP Position              */
#define LCD_TIMV_VBP_Msk                                      (0x000000ffUL << LCD_TIMV_VBP_Pos)                        /*!< LCD TIMV: VBP Mask                  */

// -----------------------------------------  LCD_POL  --------------------------------------------
#define LCD_POL_PCD_LO_Pos                                    0                                                         /*!< LCD POL: PCD_LO Position            */
#define LCD_POL_PCD_LO_Msk                                    (0x1fUL << LCD_POL_PCD_LO_Pos)                            /*!< LCD POL: PCD_LO Mask                */
#define LCD_POL_CLKSEL_Pos                                    5                                                         /*!< LCD POL: CLKSEL Position            */
#define LCD_POL_CLKSEL_Msk                                    (0x01UL << LCD_POL_CLKSEL_Pos)                            /*!< LCD POL: CLKSEL Mask                */
#define LCD_POL_ACB_Pos                                       6                                                         /*!< LCD POL: ACB Position               */
#define LCD_POL_ACB_Msk                                       (0x1fUL << LCD_POL_ACB_Pos)                               /*!< LCD POL: ACB Mask                   */
#define LCD_POL_IVS_Pos                                       11                                                        /*!< LCD POL: IVS Position               */
#define LCD_POL_IVS_Msk                                       (0x01UL << LCD_POL_IVS_Pos)                               /*!< LCD POL: IVS Mask                   */
#define LCD_POL_IHS_Pos                                       12                                                        /*!< LCD POL: IHS Position               */
#define LCD_POL_IHS_Msk                                       (0x01UL << LCD_POL_IHS_Pos)                               /*!< LCD POL: IHS Mask                   */
#define LCD_POL_IPC_Pos                                       13                                                        /*!< LCD POL: IPC Position               */
#define LCD_POL_IPC_Msk                                       (0x01UL << LCD_POL_IPC_Pos)                               /*!< LCD POL: IPC Mask                   */
#define LCD_POL_IOE_Pos                                       14                                                        /*!< LCD POL: IOE Position               */
#define LCD_POL_IOE_Msk                                       (0x01UL << LCD_POL_IOE_Pos)                               /*!< LCD POL: IOE Mask                   */
#define LCD_POL_CPL_Pos                                       16                                                        /*!< LCD POL: CPL Position               */
#define LCD_POL_CPL_Msk                                       (0x000003ffUL << LCD_POL_CPL_Pos)                         /*!< LCD POL: CPL Mask                   */
#define LCD_POL_BCD_Pos                                       26                                                        /*!< LCD POL: BCD Position               */
#define LCD_POL_BCD_Msk                                       (0x01UL << LCD_POL_BCD_Pos)                               /*!< LCD POL: BCD Mask                   */
#define LCD_POL_PCD_HI_Pos                                    27                                                        /*!< LCD POL: PCD_HI Position            */
#define LCD_POL_PCD_HI_Msk                                    (0x1fUL << LCD_POL_PCD_HI_Pos)                            /*!< LCD POL: PCD_HI Mask                */

// -----------------------------------------  LCD_LE  ---------------------------------------------
#define LCD_LE_LED_Pos                                        0                                                         /*!< LCD LE: LED Position                */
#define LCD_LE_LED_Msk                                        (0x7fUL << LCD_LE_LED_Pos)                                /*!< LCD LE: LED Mask                    */
#define LCD_LE_LEE_Pos                                        16                                                        /*!< LCD LE: LEE Position                */
#define LCD_LE_LEE_Msk                                        (0x01UL << LCD_LE_LEE_Pos)                                /*!< LCD LE: LEE Mask                    */

// ---------------------------------------  LCD_UPBASE  -------------------------------------------
#define LCD_UPBASE_LCDUPBASE_Pos                              3                                                         /*!< LCD UPBASE: LCDUPBASE Position      */
#define LCD_UPBASE_LCDUPBASE_Msk                              (0x1fffffffUL << LCD_UPBASE_LCDUPBASE_Pos)                /*!< LCD UPBASE: LCDUPBASE Mask          */

// ---------------------------------------  LCD_LPBASE  -------------------------------------------
#define LCD_LPBASE_LCDLPBASE_Pos                              3                                                         /*!< LCD LPBASE: LCDLPBASE Position      */
#define LCD_LPBASE_LCDLPBASE_Msk                              (0x1fffffffUL << LCD_LPBASE_LCDLPBASE_Pos)                /*!< LCD LPBASE: LCDLPBASE Mask          */

// ----------------------------------------  LCD_CTRL  --------------------------------------------
#define LCD_CTRL_LCDEN_Pos                                    0                                                         /*!< LCD CTRL: LCDEN Position            */
#define LCD_CTRL_LCDEN_Msk                                    (0x01UL << LCD_CTRL_LCDEN_Pos)                            /*!< LCD CTRL: LCDEN Mask                */
#define LCD_CTRL_LCDBPP_Pos                                   1                                                         /*!< LCD CTRL: LCDBPP Position           */
#define LCD_CTRL_LCDBPP_Msk                                   (0x07UL << LCD_CTRL_LCDBPP_Pos)                           /*!< LCD CTRL: LCDBPP Mask               */
#define LCD_CTRL_LCDBW_Pos                                    4                                                         /*!< LCD CTRL: LCDBW Position            */
#define LCD_CTRL_LCDBW_Msk                                    (0x01UL << LCD_CTRL_LCDBW_Pos)                            /*!< LCD CTRL: LCDBW Mask                */
#define LCD_CTRL_LCDTFT_Pos                                   5                                                         /*!< LCD CTRL: LCDTFT Position           */
#define LCD_CTRL_LCDTFT_Msk                                   (0x01UL << LCD_CTRL_LCDTFT_Pos)                           /*!< LCD CTRL: LCDTFT Mask               */
#define LCD_CTRL_LCDMONO8_Pos                                 6                                                         /*!< LCD CTRL: LCDMONO8 Position         */
#define LCD_CTRL_LCDMONO8_Msk                                 (0x01UL << LCD_CTRL_LCDMONO8_Pos)                         /*!< LCD CTRL: LCDMONO8 Mask             */
#define LCD_CTRL_LCDDUAL_Pos                                  7                                                         /*!< LCD CTRL: LCDDUAL Position          */
#define LCD_CTRL_LCDDUAL_Msk                                  (0x01UL << LCD_CTRL_LCDDUAL_Pos)                          /*!< LCD CTRL: LCDDUAL Mask              */
#define LCD_CTRL_BGR_Pos                                      8                                                         /*!< LCD CTRL: BGR Position              */
#define LCD_CTRL_BGR_Msk                                      (0x01UL << LCD_CTRL_BGR_Pos)                              /*!< LCD CTRL: BGR Mask                  */
#define LCD_CTRL_BEBO_Pos                                     9                                                         /*!< LCD CTRL: BEBO Position             */
#define LCD_CTRL_BEBO_Msk                                     (0x01UL << LCD_CTRL_BEBO_Pos)                             /*!< LCD CTRL: BEBO Mask                 */
#define LCD_CTRL_BEPO_Pos                                     10                                                        /*!< LCD CTRL: BEPO Position             */
#define LCD_CTRL_BEPO_Msk                                     (0x01UL << LCD_CTRL_BEPO_Pos)                             /*!< LCD CTRL: BEPO Mask                 */
#define LCD_CTRL_LCDPWR_Pos                                   11                                                        /*!< LCD CTRL: LCDPWR Position           */
#define LCD_CTRL_LCDPWR_Msk                                   (0x01UL << LCD_CTRL_LCDPWR_Pos)                           /*!< LCD CTRL: LCDPWR Mask               */
#define LCD_CTRL_LCDVCOMP_Pos                                 12                                                        /*!< LCD CTRL: LCDVCOMP Position         */
#define LCD_CTRL_LCDVCOMP_Msk                                 (0x03UL << LCD_CTRL_LCDVCOMP_Pos)                         /*!< LCD CTRL: LCDVCOMP Mask             */
#define LCD_CTRL_WATERMARK_Pos                                16                                                        /*!< LCD CTRL: WATERMARK Position        */
#define LCD_CTRL_WATERMARK_Msk                                (0x01UL << LCD_CTRL_WATERMARK_Pos)                        /*!< LCD CTRL: WATERMARK Mask            */

// ---------------------------------------  LCD_INTMSK  -------------------------------------------
#define LCD_INTMSK_FUFIM_Pos                                  1                                                         /*!< LCD INTMSK: FUFIM Position          */
#define LCD_INTMSK_FUFIM_Msk                                  (0x01UL << LCD_INTMSK_FUFIM_Pos)                          /*!< LCD INTMSK: FUFIM Mask              */
#define LCD_INTMSK_LNBUIM_Pos                                 2                                                         /*!< LCD INTMSK: LNBUIM Position         */
#define LCD_INTMSK_LNBUIM_Msk                                 (0x01UL << LCD_INTMSK_LNBUIM_Pos)                         /*!< LCD INTMSK: LNBUIM Mask             */
#define LCD_INTMSK_VCOMPIM_Pos                                3                                                         /*!< LCD INTMSK: VCOMPIM Position        */
#define LCD_INTMSK_VCOMPIM_Msk                                (0x01UL << LCD_INTMSK_VCOMPIM_Pos)                        /*!< LCD INTMSK: VCOMPIM Mask            */
#define LCD_INTMSK_BERIM_Pos                                  4                                                         /*!< LCD INTMSK: BERIM Position          */
#define LCD_INTMSK_BERIM_Msk                                  (0x01UL << LCD_INTMSK_BERIM_Pos)                          /*!< LCD INTMSK: BERIM Mask              */

// ---------------------------------------  LCD_INTRAW  -------------------------------------------
#define LCD_INTRAW_FUFRIS_Pos                                 1                                                         /*!< LCD INTRAW: FUFRIS Position         */
#define LCD_INTRAW_FUFRIS_Msk                                 (0x01UL << LCD_INTRAW_FUFRIS_Pos)                         /*!< LCD INTRAW: FUFRIS Mask             */
#define LCD_INTRAW_LNBURIS_Pos                                2                                                         /*!< LCD INTRAW: LNBURIS Position        */
#define LCD_INTRAW_LNBURIS_Msk                                (0x01UL << LCD_INTRAW_LNBURIS_Pos)                        /*!< LCD INTRAW: LNBURIS Mask            */
#define LCD_INTRAW_VCOMPRIS_Pos                               3                                                         /*!< LCD INTRAW: VCOMPRIS Position       */
#define LCD_INTRAW_VCOMPRIS_Msk                               (0x01UL << LCD_INTRAW_VCOMPRIS_Pos)                       /*!< LCD INTRAW: VCOMPRIS Mask           */
#define LCD_INTRAW_BERRAW_Pos                                 4                                                         /*!< LCD INTRAW: BERRAW Position         */
#define LCD_INTRAW_BERRAW_Msk                                 (0x01UL << LCD_INTRAW_BERRAW_Pos)                         /*!< LCD INTRAW: BERRAW Mask             */

// ---------------------------------------  LCD_INTSTAT  ------------------------------------------
#define LCD_INTSTAT_FUFMIS_Pos                                1                                                         /*!< LCD INTSTAT: FUFMIS Position        */
#define LCD_INTSTAT_FUFMIS_Msk                                (0x01UL << LCD_INTSTAT_FUFMIS_Pos)                        /*!< LCD INTSTAT: FUFMIS Mask            */
#define LCD_INTSTAT_LNBUMIS_Pos                               2                                                         /*!< LCD INTSTAT: LNBUMIS Position       */
#define LCD_INTSTAT_LNBUMIS_Msk                               (0x01UL << LCD_INTSTAT_LNBUMIS_Pos)                       /*!< LCD INTSTAT: LNBUMIS Mask           */
#define LCD_INTSTAT_VCOMPMIS_Pos                              3                                                         /*!< LCD INTSTAT: VCOMPMIS Position      */
#define LCD_INTSTAT_VCOMPMIS_Msk                              (0x01UL << LCD_INTSTAT_VCOMPMIS_Pos)                      /*!< LCD INTSTAT: VCOMPMIS Mask          */
#define LCD_INTSTAT_BERMIS_Pos                                4                                                         /*!< LCD INTSTAT: BERMIS Position        */
#define LCD_INTSTAT_BERMIS_Msk                                (0x01UL << LCD_INTSTAT_BERMIS_Pos)                        /*!< LCD INTSTAT: BERMIS Mask            */

// ---------------------------------------  LCD_INTCLR  -------------------------------------------
#define LCD_INTCLR_FUFIC_Pos                                  1                                                         /*!< LCD INTCLR: FUFIC Position          */
#define LCD_INTCLR_FUFIC_Msk                                  (0x01UL << LCD_INTCLR_FUFIC_Pos)                          /*!< LCD INTCLR: FUFIC Mask              */
#define LCD_INTCLR_LNBUIC_Pos                                 2                                                         /*!< LCD INTCLR: LNBUIC Position         */
#define LCD_INTCLR_LNBUIC_Msk                                 (0x01UL << LCD_INTCLR_LNBUIC_Pos)                         /*!< LCD INTCLR: LNBUIC Mask             */
#define LCD_INTCLR_VCOMPIC_Pos                                3                                                         /*!< LCD INTCLR: VCOMPIC Position        */
#define LCD_INTCLR_VCOMPIC_Msk                                (0x01UL << LCD_INTCLR_VCOMPIC_Pos)                        /*!< LCD INTCLR: VCOMPIC Mask            */
#define LCD_INTCLR_BERIC_Pos                                  4                                                         /*!< LCD INTCLR: BERIC Position          */
#define LCD_INTCLR_BERIC_Msk                                  (0x01UL << LCD_INTCLR_BERIC_Pos)                          /*!< LCD INTCLR: BERIC Mask              */

// ---------------------------------------  LCD_UPCURR  -------------------------------------------
#define LCD_UPCURR_LCDUPCURR_Pos                              0                                                         /*!< LCD UPCURR: LCDUPCURR Position      */
#define LCD_UPCURR_LCDUPCURR_Msk                              (0xffffffffUL << LCD_UPCURR_LCDUPCURR_Pos)                /*!< LCD UPCURR: LCDUPCURR Mask          */

// ---------------------------------------  LCD_LPCURR  -------------------------------------------
#define LCD_LPCURR_LCDLPCURR_Pos                              0                                                         /*!< LCD LPCURR: LCDLPCURR Position      */
#define LCD_LPCURR_LCDLPCURR_Msk                              (0xffffffffUL << LCD_LPCURR_LCDLPCURR_Pos)                /*!< LCD LPCURR: LCDLPCURR Mask          */

// ----------------------------------------  LCD_PAL0  --------------------------------------------
#define LCD_PAL0_R04_0_Pos                                    0                                                         /*!< LCD PAL0: R04_0 Position            */
#define LCD_PAL0_R04_0_Msk                                    (0x1fUL << LCD_PAL0_R04_0_Pos)                            /*!< LCD PAL0: R04_0 Mask                */
#define LCD_PAL0_G04_0_Pos                                    5                                                         /*!< LCD PAL0: G04_0 Position            */
#define LCD_PAL0_G04_0_Msk                                    (0x1fUL << LCD_PAL0_G04_0_Pos)                            /*!< LCD PAL0: G04_0 Mask                */
#define LCD_PAL0_B04_0_Pos                                    10                                                        /*!< LCD PAL0: B04_0 Position            */
#define LCD_PAL0_B04_0_Msk                                    (0x1fUL << LCD_PAL0_B04_0_Pos)                            /*!< LCD PAL0: B04_0 Mask                */
#define LCD_PAL0_I0_Pos                                       15                                                        /*!< LCD PAL0: I0 Position               */
#define LCD_PAL0_I0_Msk                                       (0x01UL << LCD_PAL0_I0_Pos)                               /*!< LCD PAL0: I0 Mask                   */
#define LCD_PAL0_R14_0_Pos                                    16                                                        /*!< LCD PAL0: R14_0 Position            */
#define LCD_PAL0_R14_0_Msk                                    (0x1fUL << LCD_PAL0_R14_0_Pos)                            /*!< LCD PAL0: R14_0 Mask                */
#define LCD_PAL0_G14_0_Pos                                    21                                                        /*!< LCD PAL0: G14_0 Position            */
#define LCD_PAL0_G14_0_Msk                                    (0x1fUL << LCD_PAL0_G14_0_Pos)                            /*!< LCD PAL0: G14_0 Mask                */
#define LCD_PAL0_B14_0_Pos                                    26                                                        /*!< LCD PAL0: B14_0 Position            */
#define LCD_PAL0_B14_0_Msk                                    (0x1fUL << LCD_PAL0_B14_0_Pos)                            /*!< LCD PAL0: B14_0 Mask                */
#define LCD_PAL0_I1_Pos                                       31                                                        /*!< LCD PAL0: I1 Position               */
#define LCD_PAL0_I1_Msk                                       (0x01UL << LCD_PAL0_I1_Pos)                               /*!< LCD PAL0: I1 Mask                   */

// ----------------------------------------  LCD_PAL1  --------------------------------------------
#define LCD_PAL1_R04_0_Pos                                    0                                                         /*!< LCD PAL1: R04_0 Position            */
#define LCD_PAL1_R04_0_Msk                                    (0x1fUL << LCD_PAL1_R04_0_Pos)                            /*!< LCD PAL1: R04_0 Mask                */
#define LCD_PAL1_G04_0_Pos                                    5                                                         /*!< LCD PAL1: G04_0 Position            */
#define LCD_PAL1_G04_0_Msk                                    (0x1fUL << LCD_PAL1_G04_0_Pos)                            /*!< LCD PAL1: G04_0 Mask                */
#define LCD_PAL1_B04_0_Pos                                    10                                                        /*!< LCD PAL1: B04_0 Position            */
#define LCD_PAL1_B04_0_Msk                                    (0x1fUL << LCD_PAL1_B04_0_Pos)                            /*!< LCD PAL1: B04_0 Mask                */
#define LCD_PAL1_I0_Pos                                       15                                                        /*!< LCD PAL1: I0 Position               */
#define LCD_PAL1_I0_Msk                                       (0x01UL << LCD_PAL1_I0_Pos)                               /*!< LCD PAL1: I0 Mask                   */
#define LCD_PAL1_R14_0_Pos                                    16                                                        /*!< LCD PAL1: R14_0 Position            */
#define LCD_PAL1_R14_0_Msk                                    (0x1fUL << LCD_PAL1_R14_0_Pos)                            /*!< LCD PAL1: R14_0 Mask                */
#define LCD_PAL1_G14_0_Pos                                    21                                                        /*!< LCD PAL1: G14_0 Position            */
#define LCD_PAL1_G14_0_Msk                                    (0x1fUL << LCD_PAL1_G14_0_Pos)                            /*!< LCD PAL1: G14_0 Mask                */
#define LCD_PAL1_B14_0_Pos                                    26                                                        /*!< LCD PAL1: B14_0 Position            */
#define LCD_PAL1_B14_0_Msk                                    (0x1fUL << LCD_PAL1_B14_0_Pos)                            /*!< LCD PAL1: B14_0 Mask                */
#define LCD_PAL1_I1_Pos                                       31                                                        /*!< LCD PAL1: I1 Position               */
#define LCD_PAL1_I1_Msk                                       (0x01UL << LCD_PAL1_I1_Pos)                               /*!< LCD PAL1: I1 Mask                   */

// ----------------------------------------  LCD_PAL2  --------------------------------------------
#define LCD_PAL2_R04_0_Pos                                    0                                                         /*!< LCD PAL2: R04_0 Position            */
#define LCD_PAL2_R04_0_Msk                                    (0x1fUL << LCD_PAL2_R04_0_Pos)                            /*!< LCD PAL2: R04_0 Mask                */
#define LCD_PAL2_G04_0_Pos                                    5                                                         /*!< LCD PAL2: G04_0 Position            */
#define LCD_PAL2_G04_0_Msk                                    (0x1fUL << LCD_PAL2_G04_0_Pos)                            /*!< LCD PAL2: G04_0 Mask                */
#define LCD_PAL2_B04_0_Pos                                    10                                                        /*!< LCD PAL2: B04_0 Position            */
#define LCD_PAL2_B04_0_Msk                                    (0x1fUL << LCD_PAL2_B04_0_Pos)                            /*!< LCD PAL2: B04_0 Mask                */
#define LCD_PAL2_I0_Pos                                       15                                                        /*!< LCD PAL2: I0 Position               */
#define LCD_PAL2_I0_Msk                                       (0x01UL << LCD_PAL2_I0_Pos)                               /*!< LCD PAL2: I0 Mask                   */
#define LCD_PAL2_R14_0_Pos                                    16                                                        /*!< LCD PAL2: R14_0 Position            */
#define LCD_PAL2_R14_0_Msk                                    (0x1fUL << LCD_PAL2_R14_0_Pos)                            /*!< LCD PAL2: R14_0 Mask                */
#define LCD_PAL2_G14_0_Pos                                    21                                                        /*!< LCD PAL2: G14_0 Position            */
#define LCD_PAL2_G14_0_Msk                                    (0x1fUL << LCD_PAL2_G14_0_Pos)                            /*!< LCD PAL2: G14_0 Mask                */
#define LCD_PAL2_B14_0_Pos                                    26                                                        /*!< LCD PAL2: B14_0 Position            */
#define LCD_PAL2_B14_0_Msk                                    (0x1fUL << LCD_PAL2_B14_0_Pos)                            /*!< LCD PAL2: B14_0 Mask                */
#define LCD_PAL2_I1_Pos                                       31                                                        /*!< LCD PAL2: I1 Position               */
#define LCD_PAL2_I1_Msk                                       (0x01UL << LCD_PAL2_I1_Pos)                               /*!< LCD PAL2: I1 Mask                   */

// ----------------------------------------  LCD_PAL3  --------------------------------------------
#define LCD_PAL3_R04_0_Pos                                    0                                                         /*!< LCD PAL3: R04_0 Position            */
#define LCD_PAL3_R04_0_Msk                                    (0x1fUL << LCD_PAL3_R04_0_Pos)                            /*!< LCD PAL3: R04_0 Mask                */
#define LCD_PAL3_G04_0_Pos                                    5                                                         /*!< LCD PAL3: G04_0 Position            */
#define LCD_PAL3_G04_0_Msk                                    (0x1fUL << LCD_PAL3_G04_0_Pos)                            /*!< LCD PAL3: G04_0 Mask                */
#define LCD_PAL3_B04_0_Pos                                    10                                                        /*!< LCD PAL3: B04_0 Position            */
#define LCD_PAL3_B04_0_Msk                                    (0x1fUL << LCD_PAL3_B04_0_Pos)                            /*!< LCD PAL3: B04_0 Mask                */
#define LCD_PAL3_I0_Pos                                       15                                                        /*!< LCD PAL3: I0 Position               */
#define LCD_PAL3_I0_Msk                                       (0x01UL << LCD_PAL3_I0_Pos)                               /*!< LCD PAL3: I0 Mask                   */
#define LCD_PAL3_R14_0_Pos                                    16                                                        /*!< LCD PAL3: R14_0 Position            */
#define LCD_PAL3_R14_0_Msk                                    (0x1fUL << LCD_PAL3_R14_0_Pos)                            /*!< LCD PAL3: R14_0 Mask                */
#define LCD_PAL3_G14_0_Pos                                    21                                                        /*!< LCD PAL3: G14_0 Position            */
#define LCD_PAL3_G14_0_Msk                                    (0x1fUL << LCD_PAL3_G14_0_Pos)                            /*!< LCD PAL3: G14_0 Mask                */
#define LCD_PAL3_B14_0_Pos                                    26                                                        /*!< LCD PAL3: B14_0 Position            */
#define LCD_PAL3_B14_0_Msk                                    (0x1fUL << LCD_PAL3_B14_0_Pos)                            /*!< LCD PAL3: B14_0 Mask                */
#define LCD_PAL3_I1_Pos                                       31                                                        /*!< LCD PAL3: I1 Position               */
#define LCD_PAL3_I1_Msk                                       (0x01UL << LCD_PAL3_I1_Pos)                               /*!< LCD PAL3: I1 Mask                   */

// ----------------------------------------  LCD_PAL4  --------------------------------------------
#define LCD_PAL4_R04_0_Pos                                    0                                                         /*!< LCD PAL4: R04_0 Position            */
#define LCD_PAL4_R04_0_Msk                                    (0x1fUL << LCD_PAL4_R04_0_Pos)                            /*!< LCD PAL4: R04_0 Mask                */
#define LCD_PAL4_G04_0_Pos                                    5                                                         /*!< LCD PAL4: G04_0 Position            */
#define LCD_PAL4_G04_0_Msk                                    (0x1fUL << LCD_PAL4_G04_0_Pos)                            /*!< LCD PAL4: G04_0 Mask                */
#define LCD_PAL4_B04_0_Pos                                    10                                                        /*!< LCD PAL4: B04_0 Position            */
#define LCD_PAL4_B04_0_Msk                                    (0x1fUL << LCD_PAL4_B04_0_Pos)                            /*!< LCD PAL4: B04_0 Mask                */
#define LCD_PAL4_I0_Pos                                       15                                                        /*!< LCD PAL4: I0 Position               */
#define LCD_PAL4_I0_Msk                                       (0x01UL << LCD_PAL4_I0_Pos)                               /*!< LCD PAL4: I0 Mask                   */
#define LCD_PAL4_R14_0_Pos                                    16                                                        /*!< LCD PAL4: R14_0 Position            */
#define LCD_PAL4_R14_0_Msk                                    (0x1fUL << LCD_PAL4_R14_0_Pos)                            /*!< LCD PAL4: R14_0 Mask                */
#define LCD_PAL4_G14_0_Pos                                    21                                                        /*!< LCD PAL4: G14_0 Position            */
#define LCD_PAL4_G14_0_Msk                                    (0x1fUL << LCD_PAL4_G14_0_Pos)                            /*!< LCD PAL4: G14_0 Mask                */
#define LCD_PAL4_B14_0_Pos                                    26                                                        /*!< LCD PAL4: B14_0 Position            */
#define LCD_PAL4_B14_0_Msk                                    (0x1fUL << LCD_PAL4_B14_0_Pos)                            /*!< LCD PAL4: B14_0 Mask                */
#define LCD_PAL4_I1_Pos                                       31                                                        /*!< LCD PAL4: I1 Position               */
#define LCD_PAL4_I1_Msk                                       (0x01UL << LCD_PAL4_I1_Pos)                               /*!< LCD PAL4: I1 Mask                   */

// ----------------------------------------  LCD_PAL5  --------------------------------------------
#define LCD_PAL5_R04_0_Pos                                    0                                                         /*!< LCD PAL5: R04_0 Position            */
#define LCD_PAL5_R04_0_Msk                                    (0x1fUL << LCD_PAL5_R04_0_Pos)                            /*!< LCD PAL5: R04_0 Mask                */
#define LCD_PAL5_G04_0_Pos                                    5                                                         /*!< LCD PAL5: G04_0 Position            */
#define LCD_PAL5_G04_0_Msk                                    (0x1fUL << LCD_PAL5_G04_0_Pos)                            /*!< LCD PAL5: G04_0 Mask                */
#define LCD_PAL5_B04_0_Pos                                    10                                                        /*!< LCD PAL5: B04_0 Position            */
#define LCD_PAL5_B04_0_Msk                                    (0x1fUL << LCD_PAL5_B04_0_Pos)                            /*!< LCD PAL5: B04_0 Mask                */
#define LCD_PAL5_I0_Pos                                       15                                                        /*!< LCD PAL5: I0 Position               */
#define LCD_PAL5_I0_Msk                                       (0x01UL << LCD_PAL5_I0_Pos)                               /*!< LCD PAL5: I0 Mask                   */
#define LCD_PAL5_R14_0_Pos                                    16                                                        /*!< LCD PAL5: R14_0 Position            */
#define LCD_PAL5_R14_0_Msk                                    (0x1fUL << LCD_PAL5_R14_0_Pos)                            /*!< LCD PAL5: R14_0 Mask                */
#define LCD_PAL5_G14_0_Pos                                    21                                                        /*!< LCD PAL5: G14_0 Position            */
#define LCD_PAL5_G14_0_Msk                                    (0x1fUL << LCD_PAL5_G14_0_Pos)                            /*!< LCD PAL5: G14_0 Mask                */
#define LCD_PAL5_B14_0_Pos                                    26                                                        /*!< LCD PAL5: B14_0 Position            */
#define LCD_PAL5_B14_0_Msk                                    (0x1fUL << LCD_PAL5_B14_0_Pos)                            /*!< LCD PAL5: B14_0 Mask                */
#define LCD_PAL5_I1_Pos                                       31                                                        /*!< LCD PAL5: I1 Position               */
#define LCD_PAL5_I1_Msk                                       (0x01UL << LCD_PAL5_I1_Pos)                               /*!< LCD PAL5: I1 Mask                   */

// ----------------------------------------  LCD_PAL6  --------------------------------------------
#define LCD_PAL6_R04_0_Pos                                    0                                                         /*!< LCD PAL6: R04_0 Position            */
#define LCD_PAL6_R04_0_Msk                                    (0x1fUL << LCD_PAL6_R04_0_Pos)                            /*!< LCD PAL6: R04_0 Mask                */
#define LCD_PAL6_G04_0_Pos                                    5                                                         /*!< LCD PAL6: G04_0 Position            */
#define LCD_PAL6_G04_0_Msk                                    (0x1fUL << LCD_PAL6_G04_0_Pos)                            /*!< LCD PAL6: G04_0 Mask                */
#define LCD_PAL6_B04_0_Pos                                    10                                                        /*!< LCD PAL6: B04_0 Position            */
#define LCD_PAL6_B04_0_Msk                                    (0x1fUL << LCD_PAL6_B04_0_Pos)                            /*!< LCD PAL6: B04_0 Mask                */
#define LCD_PAL6_I0_Pos                                       15                                                        /*!< LCD PAL6: I0 Position               */
#define LCD_PAL6_I0_Msk                                       (0x01UL << LCD_PAL6_I0_Pos)                               /*!< LCD PAL6: I0 Mask                   */
#define LCD_PAL6_R14_0_Pos                                    16                                                        /*!< LCD PAL6: R14_0 Position            */
#define LCD_PAL6_R14_0_Msk                                    (0x1fUL << LCD_PAL6_R14_0_Pos)                            /*!< LCD PAL6: R14_0 Mask                */
#define LCD_PAL6_G14_0_Pos                                    21                                                        /*!< LCD PAL6: G14_0 Position            */
#define LCD_PAL6_G14_0_Msk                                    (0x1fUL << LCD_PAL6_G14_0_Pos)                            /*!< LCD PAL6: G14_0 Mask                */
#define LCD_PAL6_B14_0_Pos                                    26                                                        /*!< LCD PAL6: B14_0 Position            */
#define LCD_PAL6_B14_0_Msk                                    (0x1fUL << LCD_PAL6_B14_0_Pos)                            /*!< LCD PAL6: B14_0 Mask                */
#define LCD_PAL6_I1_Pos                                       31                                                        /*!< LCD PAL6: I1 Position               */
#define LCD_PAL6_I1_Msk                                       (0x01UL << LCD_PAL6_I1_Pos)                               /*!< LCD PAL6: I1 Mask                   */

// ----------------------------------------  LCD_PAL7  --------------------------------------------
#define LCD_PAL7_R04_0_Pos                                    0                                                         /*!< LCD PAL7: R04_0 Position            */
#define LCD_PAL7_R04_0_Msk                                    (0x1fUL << LCD_PAL7_R04_0_Pos)                            /*!< LCD PAL7: R04_0 Mask                */
#define LCD_PAL7_G04_0_Pos                                    5                                                         /*!< LCD PAL7: G04_0 Position            */
#define LCD_PAL7_G04_0_Msk                                    (0x1fUL << LCD_PAL7_G04_0_Pos)                            /*!< LCD PAL7: G04_0 Mask                */
#define LCD_PAL7_B04_0_Pos                                    10                                                        /*!< LCD PAL7: B04_0 Position            */
#define LCD_PAL7_B04_0_Msk                                    (0x1fUL << LCD_PAL7_B04_0_Pos)                            /*!< LCD PAL7: B04_0 Mask                */
#define LCD_PAL7_I0_Pos                                       15                                                        /*!< LCD PAL7: I0 Position               */
#define LCD_PAL7_I0_Msk                                       (0x01UL << LCD_PAL7_I0_Pos)                               /*!< LCD PAL7: I0 Mask                   */
#define LCD_PAL7_R14_0_Pos                                    16                                                        /*!< LCD PAL7: R14_0 Position            */
#define LCD_PAL7_R14_0_Msk                                    (0x1fUL << LCD_PAL7_R14_0_Pos)                            /*!< LCD PAL7: R14_0 Mask                */
#define LCD_PAL7_G14_0_Pos                                    21                                                        /*!< LCD PAL7: G14_0 Position            */
#define LCD_PAL7_G14_0_Msk                                    (0x1fUL << LCD_PAL7_G14_0_Pos)                            /*!< LCD PAL7: G14_0 Mask                */
#define LCD_PAL7_B14_0_Pos                                    26                                                        /*!< LCD PAL7: B14_0 Position            */
#define LCD_PAL7_B14_0_Msk                                    (0x1fUL << LCD_PAL7_B14_0_Pos)                            /*!< LCD PAL7: B14_0 Mask                */
#define LCD_PAL7_I1_Pos                                       31                                                        /*!< LCD PAL7: I1 Position               */
#define LCD_PAL7_I1_Msk                                       (0x01UL << LCD_PAL7_I1_Pos)                               /*!< LCD PAL7: I1 Mask                   */

// ----------------------------------------  LCD_PAL8  --------------------------------------------
#define LCD_PAL8_R04_0_Pos                                    0                                                         /*!< LCD PAL8: R04_0 Position            */
#define LCD_PAL8_R04_0_Msk                                    (0x1fUL << LCD_PAL8_R04_0_Pos)                            /*!< LCD PAL8: R04_0 Mask                */
#define LCD_PAL8_G04_0_Pos                                    5                                                         /*!< LCD PAL8: G04_0 Position            */
#define LCD_PAL8_G04_0_Msk                                    (0x1fUL << LCD_PAL8_G04_0_Pos)                            /*!< LCD PAL8: G04_0 Mask                */
#define LCD_PAL8_B04_0_Pos                                    10                                                        /*!< LCD PAL8: B04_0 Position            */
#define LCD_PAL8_B04_0_Msk                                    (0x1fUL << LCD_PAL8_B04_0_Pos)                            /*!< LCD PAL8: B04_0 Mask                */
#define LCD_PAL8_I0_Pos                                       15                                                        /*!< LCD PAL8: I0 Position               */
#define LCD_PAL8_I0_Msk                                       (0x01UL << LCD_PAL8_I0_Pos)                               /*!< LCD PAL8: I0 Mask                   */
#define LCD_PAL8_R14_0_Pos                                    16                                                        /*!< LCD PAL8: R14_0 Position            */
#define LCD_PAL8_R14_0_Msk                                    (0x1fUL << LCD_PAL8_R14_0_Pos)                            /*!< LCD PAL8: R14_0 Mask                */
#define LCD_PAL8_G14_0_Pos                                    21                                                        /*!< LCD PAL8: G14_0 Position            */
#define LCD_PAL8_G14_0_Msk                                    (0x1fUL << LCD_PAL8_G14_0_Pos)                            /*!< LCD PAL8: G14_0 Mask                */
#define LCD_PAL8_B14_0_Pos                                    26                                                        /*!< LCD PAL8: B14_0 Position            */
#define LCD_PAL8_B14_0_Msk                                    (0x1fUL << LCD_PAL8_B14_0_Pos)                            /*!< LCD PAL8: B14_0 Mask                */
#define LCD_PAL8_I1_Pos                                       31                                                        /*!< LCD PAL8: I1 Position               */
#define LCD_PAL8_I1_Msk                                       (0x01UL << LCD_PAL8_I1_Pos)                               /*!< LCD PAL8: I1 Mask                   */

// ----------------------------------------  LCD_PAL9  --------------------------------------------
#define LCD_PAL9_R04_0_Pos                                    0                                                         /*!< LCD PAL9: R04_0 Position            */
#define LCD_PAL9_R04_0_Msk                                    (0x1fUL << LCD_PAL9_R04_0_Pos)                            /*!< LCD PAL9: R04_0 Mask                */
#define LCD_PAL9_G04_0_Pos                                    5                                                         /*!< LCD PAL9: G04_0 Position            */
#define LCD_PAL9_G04_0_Msk                                    (0x1fUL << LCD_PAL9_G04_0_Pos)                            /*!< LCD PAL9: G04_0 Mask                */
#define LCD_PAL9_B04_0_Pos                                    10                                                        /*!< LCD PAL9: B04_0 Position            */
#define LCD_PAL9_B04_0_Msk                                    (0x1fUL << LCD_PAL9_B04_0_Pos)                            /*!< LCD PAL9: B04_0 Mask                */
#define LCD_PAL9_I0_Pos                                       15                                                        /*!< LCD PAL9: I0 Position               */
#define LCD_PAL9_I0_Msk                                       (0x01UL << LCD_PAL9_I0_Pos)                               /*!< LCD PAL9: I0 Mask                   */
#define LCD_PAL9_R14_0_Pos                                    16                                                        /*!< LCD PAL9: R14_0 Position            */
#define LCD_PAL9_R14_0_Msk                                    (0x1fUL << LCD_PAL9_R14_0_Pos)                            /*!< LCD PAL9: R14_0 Mask                */
#define LCD_PAL9_G14_0_Pos                                    21                                                        /*!< LCD PAL9: G14_0 Position            */
#define LCD_PAL9_G14_0_Msk                                    (0x1fUL << LCD_PAL9_G14_0_Pos)                            /*!< LCD PAL9: G14_0 Mask                */
#define LCD_PAL9_B14_0_Pos                                    26                                                        /*!< LCD PAL9: B14_0 Position            */
#define LCD_PAL9_B14_0_Msk                                    (0x1fUL << LCD_PAL9_B14_0_Pos)                            /*!< LCD PAL9: B14_0 Mask                */
#define LCD_PAL9_I1_Pos                                       31                                                        /*!< LCD PAL9: I1 Position               */
#define LCD_PAL9_I1_Msk                                       (0x01UL << LCD_PAL9_I1_Pos)                               /*!< LCD PAL9: I1 Mask                   */

// ----------------------------------------  LCD_PAL10  -------------------------------------------
#define LCD_PAL10_R04_0_Pos                                   0                                                         /*!< LCD PAL10: R04_0 Position           */
#define LCD_PAL10_R04_0_Msk                                   (0x1fUL << LCD_PAL10_R04_0_Pos)                           /*!< LCD PAL10: R04_0 Mask               */
#define LCD_PAL10_G04_0_Pos                                   5                                                         /*!< LCD PAL10: G04_0 Position           */
#define LCD_PAL10_G04_0_Msk                                   (0x1fUL << LCD_PAL10_G04_0_Pos)                           /*!< LCD PAL10: G04_0 Mask               */
#define LCD_PAL10_B04_0_Pos                                   10                                                        /*!< LCD PAL10: B04_0 Position           */
#define LCD_PAL10_B04_0_Msk                                   (0x1fUL << LCD_PAL10_B04_0_Pos)                           /*!< LCD PAL10: B04_0 Mask               */
#define LCD_PAL10_I0_Pos                                      15                                                        /*!< LCD PAL10: I0 Position              */
#define LCD_PAL10_I0_Msk                                      (0x01UL << LCD_PAL10_I0_Pos)                              /*!< LCD PAL10: I0 Mask                  */
#define LCD_PAL10_R14_0_Pos                                   16                                                        /*!< LCD PAL10: R14_0 Position           */
#define LCD_PAL10_R14_0_Msk                                   (0x1fUL << LCD_PAL10_R14_0_Pos)                           /*!< LCD PAL10: R14_0 Mask               */
#define LCD_PAL10_G14_0_Pos                                   21                                                        /*!< LCD PAL10: G14_0 Position           */
#define LCD_PAL10_G14_0_Msk                                   (0x1fUL << LCD_PAL10_G14_0_Pos)                           /*!< LCD PAL10: G14_0 Mask               */
#define LCD_PAL10_B14_0_Pos                                   26                                                        /*!< LCD PAL10: B14_0 Position           */
#define LCD_PAL10_B14_0_Msk                                   (0x1fUL << LCD_PAL10_B14_0_Pos)                           /*!< LCD PAL10: B14_0 Mask               */
#define LCD_PAL10_I1_Pos                                      31                                                        /*!< LCD PAL10: I1 Position              */
#define LCD_PAL10_I1_Msk                                      (0x01UL << LCD_PAL10_I1_Pos)                              /*!< LCD PAL10: I1 Mask                  */

// ----------------------------------------  LCD_PAL11  -------------------------------------------
#define LCD_PAL11_R04_0_Pos                                   0                                                         /*!< LCD PAL11: R04_0 Position           */
#define LCD_PAL11_R04_0_Msk                                   (0x1fUL << LCD_PAL11_R04_0_Pos)                           /*!< LCD PAL11: R04_0 Mask               */
#define LCD_PAL11_G04_0_Pos                                   5                                                         /*!< LCD PAL11: G04_0 Position           */
#define LCD_PAL11_G04_0_Msk                                   (0x1fUL << LCD_PAL11_G04_0_Pos)                           /*!< LCD PAL11: G04_0 Mask               */
#define LCD_PAL11_B04_0_Pos                                   10                                                        /*!< LCD PAL11: B04_0 Position           */
#define LCD_PAL11_B04_0_Msk                                   (0x1fUL << LCD_PAL11_B04_0_Pos)                           /*!< LCD PAL11: B04_0 Mask               */
#define LCD_PAL11_I0_Pos                                      15                                                        /*!< LCD PAL11: I0 Position              */
#define LCD_PAL11_I0_Msk                                      (0x01UL << LCD_PAL11_I0_Pos)                              /*!< LCD PAL11: I0 Mask                  */
#define LCD_PAL11_R14_0_Pos                                   16                                                        /*!< LCD PAL11: R14_0 Position           */
#define LCD_PAL11_R14_0_Msk                                   (0x1fUL << LCD_PAL11_R14_0_Pos)                           /*!< LCD PAL11: R14_0 Mask               */
#define LCD_PAL11_G14_0_Pos                                   21                                                        /*!< LCD PAL11: G14_0 Position           */
#define LCD_PAL11_G14_0_Msk                                   (0x1fUL << LCD_PAL11_G14_0_Pos)                           /*!< LCD PAL11: G14_0 Mask               */
#define LCD_PAL11_B14_0_Pos                                   26                                                        /*!< LCD PAL11: B14_0 Position           */
#define LCD_PAL11_B14_0_Msk                                   (0x1fUL << LCD_PAL11_B14_0_Pos)                           /*!< LCD PAL11: B14_0 Mask               */
#define LCD_PAL11_I1_Pos                                      31                                                        /*!< LCD PAL11: I1 Position              */
#define LCD_PAL11_I1_Msk                                      (0x01UL << LCD_PAL11_I1_Pos)                              /*!< LCD PAL11: I1 Mask                  */

// ----------------------------------------  LCD_PAL12  -------------------------------------------
#define LCD_PAL12_R04_0_Pos                                   0                                                         /*!< LCD PAL12: R04_0 Position           */
#define LCD_PAL12_R04_0_Msk                                   (0x1fUL << LCD_PAL12_R04_0_Pos)                           /*!< LCD PAL12: R04_0 Mask               */
#define LCD_PAL12_G04_0_Pos                                   5                                                         /*!< LCD PAL12: G04_0 Position           */
#define LCD_PAL12_G04_0_Msk                                   (0x1fUL << LCD_PAL12_G04_0_Pos)                           /*!< LCD PAL12: G04_0 Mask               */
#define LCD_PAL12_B04_0_Pos                                   10                                                        /*!< LCD PAL12: B04_0 Position           */
#define LCD_PAL12_B04_0_Msk                                   (0x1fUL << LCD_PAL12_B04_0_Pos)                           /*!< LCD PAL12: B04_0 Mask               */
#define LCD_PAL12_I0_Pos                                      15                                                        /*!< LCD PAL12: I0 Position              */
#define LCD_PAL12_I0_Msk                                      (0x01UL << LCD_PAL12_I0_Pos)                              /*!< LCD PAL12: I0 Mask                  */
#define LCD_PAL12_R14_0_Pos                                   16                                                        /*!< LCD PAL12: R14_0 Position           */
#define LCD_PAL12_R14_0_Msk                                   (0x1fUL << LCD_PAL12_R14_0_Pos)                           /*!< LCD PAL12: R14_0 Mask               */
#define LCD_PAL12_G14_0_Pos                                   21                                                        /*!< LCD PAL12: G14_0 Position           */
#define LCD_PAL12_G14_0_Msk                                   (0x1fUL << LCD_PAL12_G14_0_Pos)                           /*!< LCD PAL12: G14_0 Mask               */
#define LCD_PAL12_B14_0_Pos                                   26                                                        /*!< LCD PAL12: B14_0 Position           */
#define LCD_PAL12_B14_0_Msk                                   (0x1fUL << LCD_PAL12_B14_0_Pos)                           /*!< LCD PAL12: B14_0 Mask               */
#define LCD_PAL12_I1_Pos                                      31                                                        /*!< LCD PAL12: I1 Position              */
#define LCD_PAL12_I1_Msk                                      (0x01UL << LCD_PAL12_I1_Pos)                              /*!< LCD PAL12: I1 Mask                  */

// ----------------------------------------  LCD_PAL13  -------------------------------------------
#define LCD_PAL13_R04_0_Pos                                   0                                                         /*!< LCD PAL13: R04_0 Position           */
#define LCD_PAL13_R04_0_Msk                                   (0x1fUL << LCD_PAL13_R04_0_Pos)                           /*!< LCD PAL13: R04_0 Mask               */
#define LCD_PAL13_G04_0_Pos                                   5                                                         /*!< LCD PAL13: G04_0 Position           */
#define LCD_PAL13_G04_0_Msk                                   (0x1fUL << LCD_PAL13_G04_0_Pos)                           /*!< LCD PAL13: G04_0 Mask               */
#define LCD_PAL13_B04_0_Pos                                   10                                                        /*!< LCD PAL13: B04_0 Position           */
#define LCD_PAL13_B04_0_Msk                                   (0x1fUL << LCD_PAL13_B04_0_Pos)                           /*!< LCD PAL13: B04_0 Mask               */
#define LCD_PAL13_I0_Pos                                      15                                                        /*!< LCD PAL13: I0 Position              */
#define LCD_PAL13_I0_Msk                                      (0x01UL << LCD_PAL13_I0_Pos)                              /*!< LCD PAL13: I0 Mask                  */
#define LCD_PAL13_R14_0_Pos                                   16                                                        /*!< LCD PAL13: R14_0 Position           */
#define LCD_PAL13_R14_0_Msk                                   (0x1fUL << LCD_PAL13_R14_0_Pos)                           /*!< LCD PAL13: R14_0 Mask               */
#define LCD_PAL13_G14_0_Pos                                   21                                                        /*!< LCD PAL13: G14_0 Position           */
#define LCD_PAL13_G14_0_Msk                                   (0x1fUL << LCD_PAL13_G14_0_Pos)                           /*!< LCD PAL13: G14_0 Mask               */
#define LCD_PAL13_B14_0_Pos                                   26                                                        /*!< LCD PAL13: B14_0 Position           */
#define LCD_PAL13_B14_0_Msk                                   (0x1fUL << LCD_PAL13_B14_0_Pos)                           /*!< LCD PAL13: B14_0 Mask               */
#define LCD_PAL13_I1_Pos                                      31                                                        /*!< LCD PAL13: I1 Position              */
#define LCD_PAL13_I1_Msk                                      (0x01UL << LCD_PAL13_I1_Pos)                              /*!< LCD PAL13: I1 Mask                  */

// ----------------------------------------  LCD_PAL14  -------------------------------------------
#define LCD_PAL14_R04_0_Pos                                   0                                                         /*!< LCD PAL14: R04_0 Position           */
#define LCD_PAL14_R04_0_Msk                                   (0x1fUL << LCD_PAL14_R04_0_Pos)                           /*!< LCD PAL14: R04_0 Mask               */
#define LCD_PAL14_G04_0_Pos                                   5                                                         /*!< LCD PAL14: G04_0 Position           */
#define LCD_PAL14_G04_0_Msk                                   (0x1fUL << LCD_PAL14_G04_0_Pos)                           /*!< LCD PAL14: G04_0 Mask               */
#define LCD_PAL14_B04_0_Pos                                   10                                                        /*!< LCD PAL14: B04_0 Position           */
#define LCD_PAL14_B04_0_Msk                                   (0x1fUL << LCD_PAL14_B04_0_Pos)                           /*!< LCD PAL14: B04_0 Mask               */
#define LCD_PAL14_I0_Pos                                      15                                                        /*!< LCD PAL14: I0 Position              */
#define LCD_PAL14_I0_Msk                                      (0x01UL << LCD_PAL14_I0_Pos)                              /*!< LCD PAL14: I0 Mask                  */
#define LCD_PAL14_R14_0_Pos                                   16                                                        /*!< LCD PAL14: R14_0 Position           */
#define LCD_PAL14_R14_0_Msk                                   (0x1fUL << LCD_PAL14_R14_0_Pos)                           /*!< LCD PAL14: R14_0 Mask               */
#define LCD_PAL14_G14_0_Pos                                   21                                                        /*!< LCD PAL14: G14_0 Position           */
#define LCD_PAL14_G14_0_Msk                                   (0x1fUL << LCD_PAL14_G14_0_Pos)                           /*!< LCD PAL14: G14_0 Mask               */
#define LCD_PAL14_B14_0_Pos                                   26                                                        /*!< LCD PAL14: B14_0 Position           */
#define LCD_PAL14_B14_0_Msk                                   (0x1fUL << LCD_PAL14_B14_0_Pos)                           /*!< LCD PAL14: B14_0 Mask               */
#define LCD_PAL14_I1_Pos                                      31                                                        /*!< LCD PAL14: I1 Position              */
#define LCD_PAL14_I1_Msk                                      (0x01UL << LCD_PAL14_I1_Pos)                              /*!< LCD PAL14: I1 Mask                  */

// ----------------------------------------  LCD_PAL15  -------------------------------------------
#define LCD_PAL15_R04_0_Pos                                   0                                                         /*!< LCD PAL15: R04_0 Position           */
#define LCD_PAL15_R04_0_Msk                                   (0x1fUL << LCD_PAL15_R04_0_Pos)                           /*!< LCD PAL15: R04_0 Mask               */
#define LCD_PAL15_G04_0_Pos                                   5                                                         /*!< LCD PAL15: G04_0 Position           */
#define LCD_PAL15_G04_0_Msk                                   (0x1fUL << LCD_PAL15_G04_0_Pos)                           /*!< LCD PAL15: G04_0 Mask               */
#define LCD_PAL15_B04_0_Pos                                   10                                                        /*!< LCD PAL15: B04_0 Position           */
#define LCD_PAL15_B04_0_Msk                                   (0x1fUL << LCD_PAL15_B04_0_Pos)                           /*!< LCD PAL15: B04_0 Mask               */
#define LCD_PAL15_I0_Pos                                      15                                                        /*!< LCD PAL15: I0 Position              */
#define LCD_PAL15_I0_Msk                                      (0x01UL << LCD_PAL15_I0_Pos)                              /*!< LCD PAL15: I0 Mask                  */
#define LCD_PAL15_R14_0_Pos                                   16                                                        /*!< LCD PAL15: R14_0 Position           */
#define LCD_PAL15_R14_0_Msk                                   (0x1fUL << LCD_PAL15_R14_0_Pos)                           /*!< LCD PAL15: R14_0 Mask               */
#define LCD_PAL15_G14_0_Pos                                   21                                                        /*!< LCD PAL15: G14_0 Position           */
#define LCD_PAL15_G14_0_Msk                                   (0x1fUL << LCD_PAL15_G14_0_Pos)                           /*!< LCD PAL15: G14_0 Mask               */
#define LCD_PAL15_B14_0_Pos                                   26                                                        /*!< LCD PAL15: B14_0 Position           */
#define LCD_PAL15_B14_0_Msk                                   (0x1fUL << LCD_PAL15_B14_0_Pos)                           /*!< LCD PAL15: B14_0 Mask               */
#define LCD_PAL15_I1_Pos                                      31                                                        /*!< LCD PAL15: I1 Position              */
#define LCD_PAL15_I1_Msk                                      (0x01UL << LCD_PAL15_I1_Pos)                              /*!< LCD PAL15: I1 Mask                  */

// ----------------------------------------  LCD_PAL16  -------------------------------------------
#define LCD_PAL16_R04_0_Pos                                   0                                                         /*!< LCD PAL16: R04_0 Position           */
#define LCD_PAL16_R04_0_Msk                                   (0x1fUL << LCD_PAL16_R04_0_Pos)                           /*!< LCD PAL16: R04_0 Mask               */
#define LCD_PAL16_G04_0_Pos                                   5                                                         /*!< LCD PAL16: G04_0 Position           */
#define LCD_PAL16_G04_0_Msk                                   (0x1fUL << LCD_PAL16_G04_0_Pos)                           /*!< LCD PAL16: G04_0 Mask               */
#define LCD_PAL16_B04_0_Pos                                   10                                                        /*!< LCD PAL16: B04_0 Position           */
#define LCD_PAL16_B04_0_Msk                                   (0x1fUL << LCD_PAL16_B04_0_Pos)                           /*!< LCD PAL16: B04_0 Mask               */
#define LCD_PAL16_I0_Pos                                      15                                                        /*!< LCD PAL16: I0 Position              */
#define LCD_PAL16_I0_Msk                                      (0x01UL << LCD_PAL16_I0_Pos)                              /*!< LCD PAL16: I0 Mask                  */
#define LCD_PAL16_R14_0_Pos                                   16                                                        /*!< LCD PAL16: R14_0 Position           */
#define LCD_PAL16_R14_0_Msk                                   (0x1fUL << LCD_PAL16_R14_0_Pos)                           /*!< LCD PAL16: R14_0 Mask               */
#define LCD_PAL16_G14_0_Pos                                   21                                                        /*!< LCD PAL16: G14_0 Position           */
#define LCD_PAL16_G14_0_Msk                                   (0x1fUL << LCD_PAL16_G14_0_Pos)                           /*!< LCD PAL16: G14_0 Mask               */
#define LCD_PAL16_B14_0_Pos                                   26                                                        /*!< LCD PAL16: B14_0 Position           */
#define LCD_PAL16_B14_0_Msk                                   (0x1fUL << LCD_PAL16_B14_0_Pos)                           /*!< LCD PAL16: B14_0 Mask               */
#define LCD_PAL16_I1_Pos                                      31                                                        /*!< LCD PAL16: I1 Position              */
#define LCD_PAL16_I1_Msk                                      (0x01UL << LCD_PAL16_I1_Pos)                              /*!< LCD PAL16: I1 Mask                  */

// ----------------------------------------  LCD_PAL17  -------------------------------------------
#define LCD_PAL17_R04_0_Pos                                   0                                                         /*!< LCD PAL17: R04_0 Position           */
#define LCD_PAL17_R04_0_Msk                                   (0x1fUL << LCD_PAL17_R04_0_Pos)                           /*!< LCD PAL17: R04_0 Mask               */
#define LCD_PAL17_G04_0_Pos                                   5                                                         /*!< LCD PAL17: G04_0 Position           */
#define LCD_PAL17_G04_0_Msk                                   (0x1fUL << LCD_PAL17_G04_0_Pos)                           /*!< LCD PAL17: G04_0 Mask               */
#define LCD_PAL17_B04_0_Pos                                   10                                                        /*!< LCD PAL17: B04_0 Position           */
#define LCD_PAL17_B04_0_Msk                                   (0x1fUL << LCD_PAL17_B04_0_Pos)                           /*!< LCD PAL17: B04_0 Mask               */
#define LCD_PAL17_I0_Pos                                      15                                                        /*!< LCD PAL17: I0 Position              */
#define LCD_PAL17_I0_Msk                                      (0x01UL << LCD_PAL17_I0_Pos)                              /*!< LCD PAL17: I0 Mask                  */
#define LCD_PAL17_R14_0_Pos                                   16                                                        /*!< LCD PAL17: R14_0 Position           */
#define LCD_PAL17_R14_0_Msk                                   (0x1fUL << LCD_PAL17_R14_0_Pos)                           /*!< LCD PAL17: R14_0 Mask               */
#define LCD_PAL17_G14_0_Pos                                   21                                                        /*!< LCD PAL17: G14_0 Position           */
#define LCD_PAL17_G14_0_Msk                                   (0x1fUL << LCD_PAL17_G14_0_Pos)                           /*!< LCD PAL17: G14_0 Mask               */
#define LCD_PAL17_B14_0_Pos                                   26                                                        /*!< LCD PAL17: B14_0 Position           */
#define LCD_PAL17_B14_0_Msk                                   (0x1fUL << LCD_PAL17_B14_0_Pos)                           /*!< LCD PAL17: B14_0 Mask               */
#define LCD_PAL17_I1_Pos                                      31                                                        /*!< LCD PAL17: I1 Position              */
#define LCD_PAL17_I1_Msk                                      (0x01UL << LCD_PAL17_I1_Pos)                              /*!< LCD PAL17: I1 Mask                  */

// ----------------------------------------  LCD_PAL18  -------------------------------------------
#define LCD_PAL18_R04_0_Pos                                   0                                                         /*!< LCD PAL18: R04_0 Position           */
#define LCD_PAL18_R04_0_Msk                                   (0x1fUL << LCD_PAL18_R04_0_Pos)                           /*!< LCD PAL18: R04_0 Mask               */
#define LCD_PAL18_G04_0_Pos                                   5                                                         /*!< LCD PAL18: G04_0 Position           */
#define LCD_PAL18_G04_0_Msk                                   (0x1fUL << LCD_PAL18_G04_0_Pos)                           /*!< LCD PAL18: G04_0 Mask               */
#define LCD_PAL18_B04_0_Pos                                   10                                                        /*!< LCD PAL18: B04_0 Position           */
#define LCD_PAL18_B04_0_Msk                                   (0x1fUL << LCD_PAL18_B04_0_Pos)                           /*!< LCD PAL18: B04_0 Mask               */
#define LCD_PAL18_I0_Pos                                      15                                                        /*!< LCD PAL18: I0 Position              */
#define LCD_PAL18_I0_Msk                                      (0x01UL << LCD_PAL18_I0_Pos)                              /*!< LCD PAL18: I0 Mask                  */
#define LCD_PAL18_R14_0_Pos                                   16                                                        /*!< LCD PAL18: R14_0 Position           */
#define LCD_PAL18_R14_0_Msk                                   (0x1fUL << LCD_PAL18_R14_0_Pos)                           /*!< LCD PAL18: R14_0 Mask               */
#define LCD_PAL18_G14_0_Pos                                   21                                                        /*!< LCD PAL18: G14_0 Position           */
#define LCD_PAL18_G14_0_Msk                                   (0x1fUL << LCD_PAL18_G14_0_Pos)                           /*!< LCD PAL18: G14_0 Mask               */
#define LCD_PAL18_B14_0_Pos                                   26                                                        /*!< LCD PAL18: B14_0 Position           */
#define LCD_PAL18_B14_0_Msk                                   (0x1fUL << LCD_PAL18_B14_0_Pos)                           /*!< LCD PAL18: B14_0 Mask               */
#define LCD_PAL18_I1_Pos                                      31                                                        /*!< LCD PAL18: I1 Position              */
#define LCD_PAL18_I1_Msk                                      (0x01UL << LCD_PAL18_I1_Pos)                              /*!< LCD PAL18: I1 Mask                  */

// ----------------------------------------  LCD_PAL19  -------------------------------------------
#define LCD_PAL19_R04_0_Pos                                   0                                                         /*!< LCD PAL19: R04_0 Position           */
#define LCD_PAL19_R04_0_Msk                                   (0x1fUL << LCD_PAL19_R04_0_Pos)                           /*!< LCD PAL19: R04_0 Mask               */
#define LCD_PAL19_G04_0_Pos                                   5                                                         /*!< LCD PAL19: G04_0 Position           */
#define LCD_PAL19_G04_0_Msk                                   (0x1fUL << LCD_PAL19_G04_0_Pos)                           /*!< LCD PAL19: G04_0 Mask               */
#define LCD_PAL19_B04_0_Pos                                   10                                                        /*!< LCD PAL19: B04_0 Position           */
#define LCD_PAL19_B04_0_Msk                                   (0x1fUL << LCD_PAL19_B04_0_Pos)                           /*!< LCD PAL19: B04_0 Mask               */
#define LCD_PAL19_I0_Pos                                      15                                                        /*!< LCD PAL19: I0 Position              */
#define LCD_PAL19_I0_Msk                                      (0x01UL << LCD_PAL19_I0_Pos)                              /*!< LCD PAL19: I0 Mask                  */
#define LCD_PAL19_R14_0_Pos                                   16                                                        /*!< LCD PAL19: R14_0 Position           */
#define LCD_PAL19_R14_0_Msk                                   (0x1fUL << LCD_PAL19_R14_0_Pos)                           /*!< LCD PAL19: R14_0 Mask               */
#define LCD_PAL19_G14_0_Pos                                   21                                                        /*!< LCD PAL19: G14_0 Position           */
#define LCD_PAL19_G14_0_Msk                                   (0x1fUL << LCD_PAL19_G14_0_Pos)                           /*!< LCD PAL19: G14_0 Mask               */
#define LCD_PAL19_B14_0_Pos                                   26                                                        /*!< LCD PAL19: B14_0 Position           */
#define LCD_PAL19_B14_0_Msk                                   (0x1fUL << LCD_PAL19_B14_0_Pos)                           /*!< LCD PAL19: B14_0 Mask               */
#define LCD_PAL19_I1_Pos                                      31                                                        /*!< LCD PAL19: I1 Position              */
#define LCD_PAL19_I1_Msk                                      (0x01UL << LCD_PAL19_I1_Pos)                              /*!< LCD PAL19: I1 Mask                  */

// ----------------------------------------  LCD_PAL20  -------------------------------------------
#define LCD_PAL20_R04_0_Pos                                   0                                                         /*!< LCD PAL20: R04_0 Position           */
#define LCD_PAL20_R04_0_Msk                                   (0x1fUL << LCD_PAL20_R04_0_Pos)                           /*!< LCD PAL20: R04_0 Mask               */
#define LCD_PAL20_G04_0_Pos                                   5                                                         /*!< LCD PAL20: G04_0 Position           */
#define LCD_PAL20_G04_0_Msk                                   (0x1fUL << LCD_PAL20_G04_0_Pos)                           /*!< LCD PAL20: G04_0 Mask               */
#define LCD_PAL20_B04_0_Pos                                   10                                                        /*!< LCD PAL20: B04_0 Position           */
#define LCD_PAL20_B04_0_Msk                                   (0x1fUL << LCD_PAL20_B04_0_Pos)                           /*!< LCD PAL20: B04_0 Mask               */
#define LCD_PAL20_I0_Pos                                      15                                                        /*!< LCD PAL20: I0 Position              */
#define LCD_PAL20_I0_Msk                                      (0x01UL << LCD_PAL20_I0_Pos)                              /*!< LCD PAL20: I0 Mask                  */
#define LCD_PAL20_R14_0_Pos                                   16                                                        /*!< LCD PAL20: R14_0 Position           */
#define LCD_PAL20_R14_0_Msk                                   (0x1fUL << LCD_PAL20_R14_0_Pos)                           /*!< LCD PAL20: R14_0 Mask               */
#define LCD_PAL20_G14_0_Pos                                   21                                                        /*!< LCD PAL20: G14_0 Position           */
#define LCD_PAL20_G14_0_Msk                                   (0x1fUL << LCD_PAL20_G14_0_Pos)                           /*!< LCD PAL20: G14_0 Mask               */
#define LCD_PAL20_B14_0_Pos                                   26                                                        /*!< LCD PAL20: B14_0 Position           */
#define LCD_PAL20_B14_0_Msk                                   (0x1fUL << LCD_PAL20_B14_0_Pos)                           /*!< LCD PAL20: B14_0 Mask               */
#define LCD_PAL20_I1_Pos                                      31                                                        /*!< LCD PAL20: I1 Position              */
#define LCD_PAL20_I1_Msk                                      (0x01UL << LCD_PAL20_I1_Pos)                              /*!< LCD PAL20: I1 Mask                  */

// ----------------------------------------  LCD_PAL21  -------------------------------------------
#define LCD_PAL21_R04_0_Pos                                   0                                                         /*!< LCD PAL21: R04_0 Position           */
#define LCD_PAL21_R04_0_Msk                                   (0x1fUL << LCD_PAL21_R04_0_Pos)                           /*!< LCD PAL21: R04_0 Mask               */
#define LCD_PAL21_G04_0_Pos                                   5                                                         /*!< LCD PAL21: G04_0 Position           */
#define LCD_PAL21_G04_0_Msk                                   (0x1fUL << LCD_PAL21_G04_0_Pos)                           /*!< LCD PAL21: G04_0 Mask               */
#define LCD_PAL21_B04_0_Pos                                   10                                                        /*!< LCD PAL21: B04_0 Position           */
#define LCD_PAL21_B04_0_Msk                                   (0x1fUL << LCD_PAL21_B04_0_Pos)                           /*!< LCD PAL21: B04_0 Mask               */
#define LCD_PAL21_I0_Pos                                      15                                                        /*!< LCD PAL21: I0 Position              */
#define LCD_PAL21_I0_Msk                                      (0x01UL << LCD_PAL21_I0_Pos)                              /*!< LCD PAL21: I0 Mask                  */
#define LCD_PAL21_R14_0_Pos                                   16                                                        /*!< LCD PAL21: R14_0 Position           */
#define LCD_PAL21_R14_0_Msk                                   (0x1fUL << LCD_PAL21_R14_0_Pos)                           /*!< LCD PAL21: R14_0 Mask               */
#define LCD_PAL21_G14_0_Pos                                   21                                                        /*!< LCD PAL21: G14_0 Position           */
#define LCD_PAL21_G14_0_Msk                                   (0x1fUL << LCD_PAL21_G14_0_Pos)                           /*!< LCD PAL21: G14_0 Mask               */
#define LCD_PAL21_B14_0_Pos                                   26                                                        /*!< LCD PAL21: B14_0 Position           */
#define LCD_PAL21_B14_0_Msk                                   (0x1fUL << LCD_PAL21_B14_0_Pos)                           /*!< LCD PAL21: B14_0 Mask               */
#define LCD_PAL21_I1_Pos                                      31                                                        /*!< LCD PAL21: I1 Position              */
#define LCD_PAL21_I1_Msk                                      (0x01UL << LCD_PAL21_I1_Pos)                              /*!< LCD PAL21: I1 Mask                  */

// ----------------------------------------  LCD_PAL22  -------------------------------------------
#define LCD_PAL22_R04_0_Pos                                   0                                                         /*!< LCD PAL22: R04_0 Position           */
#define LCD_PAL22_R04_0_Msk                                   (0x1fUL << LCD_PAL22_R04_0_Pos)                           /*!< LCD PAL22: R04_0 Mask               */
#define LCD_PAL22_G04_0_Pos                                   5                                                         /*!< LCD PAL22: G04_0 Position           */
#define LCD_PAL22_G04_0_Msk                                   (0x1fUL << LCD_PAL22_G04_0_Pos)                           /*!< LCD PAL22: G04_0 Mask               */
#define LCD_PAL22_B04_0_Pos                                   10                                                        /*!< LCD PAL22: B04_0 Position           */
#define LCD_PAL22_B04_0_Msk                                   (0x1fUL << LCD_PAL22_B04_0_Pos)                           /*!< LCD PAL22: B04_0 Mask               */
#define LCD_PAL22_I0_Pos                                      15                                                        /*!< LCD PAL22: I0 Position              */
#define LCD_PAL22_I0_Msk                                      (0x01UL << LCD_PAL22_I0_Pos)                              /*!< LCD PAL22: I0 Mask                  */
#define LCD_PAL22_R14_0_Pos                                   16                                                        /*!< LCD PAL22: R14_0 Position           */
#define LCD_PAL22_R14_0_Msk                                   (0x1fUL << LCD_PAL22_R14_0_Pos)                           /*!< LCD PAL22: R14_0 Mask               */
#define LCD_PAL22_G14_0_Pos                                   21                                                        /*!< LCD PAL22: G14_0 Position           */
#define LCD_PAL22_G14_0_Msk                                   (0x1fUL << LCD_PAL22_G14_0_Pos)                           /*!< LCD PAL22: G14_0 Mask               */
#define LCD_PAL22_B14_0_Pos                                   26                                                        /*!< LCD PAL22: B14_0 Position           */
#define LCD_PAL22_B14_0_Msk                                   (0x1fUL << LCD_PAL22_B14_0_Pos)                           /*!< LCD PAL22: B14_0 Mask               */
#define LCD_PAL22_I1_Pos                                      31                                                        /*!< LCD PAL22: I1 Position              */
#define LCD_PAL22_I1_Msk                                      (0x01UL << LCD_PAL22_I1_Pos)                              /*!< LCD PAL22: I1 Mask                  */

// ----------------------------------------  LCD_PAL23  -------------------------------------------
#define LCD_PAL23_R04_0_Pos                                   0                                                         /*!< LCD PAL23: R04_0 Position           */
#define LCD_PAL23_R04_0_Msk                                   (0x1fUL << LCD_PAL23_R04_0_Pos)                           /*!< LCD PAL23: R04_0 Mask               */
#define LCD_PAL23_G04_0_Pos                                   5                                                         /*!< LCD PAL23: G04_0 Position           */
#define LCD_PAL23_G04_0_Msk                                   (0x1fUL << LCD_PAL23_G04_0_Pos)                           /*!< LCD PAL23: G04_0 Mask               */
#define LCD_PAL23_B04_0_Pos                                   10                                                        /*!< LCD PAL23: B04_0 Position           */
#define LCD_PAL23_B04_0_Msk                                   (0x1fUL << LCD_PAL23_B04_0_Pos)                           /*!< LCD PAL23: B04_0 Mask               */
#define LCD_PAL23_I0_Pos                                      15                                                        /*!< LCD PAL23: I0 Position              */
#define LCD_PAL23_I0_Msk                                      (0x01UL << LCD_PAL23_I0_Pos)                              /*!< LCD PAL23: I0 Mask                  */
#define LCD_PAL23_R14_0_Pos                                   16                                                        /*!< LCD PAL23: R14_0 Position           */
#define LCD_PAL23_R14_0_Msk                                   (0x1fUL << LCD_PAL23_R14_0_Pos)                           /*!< LCD PAL23: R14_0 Mask               */
#define LCD_PAL23_G14_0_Pos                                   21                                                        /*!< LCD PAL23: G14_0 Position           */
#define LCD_PAL23_G14_0_Msk                                   (0x1fUL << LCD_PAL23_G14_0_Pos)                           /*!< LCD PAL23: G14_0 Mask               */
#define LCD_PAL23_B14_0_Pos                                   26                                                        /*!< LCD PAL23: B14_0 Position           */
#define LCD_PAL23_B14_0_Msk                                   (0x1fUL << LCD_PAL23_B14_0_Pos)                           /*!< LCD PAL23: B14_0 Mask               */
#define LCD_PAL23_I1_Pos                                      31                                                        /*!< LCD PAL23: I1 Position              */
#define LCD_PAL23_I1_Msk                                      (0x01UL << LCD_PAL23_I1_Pos)                              /*!< LCD PAL23: I1 Mask                  */

// ----------------------------------------  LCD_PAL24  -------------------------------------------
#define LCD_PAL24_R04_0_Pos                                   0                                                         /*!< LCD PAL24: R04_0 Position           */
#define LCD_PAL24_R04_0_Msk                                   (0x1fUL << LCD_PAL24_R04_0_Pos)                           /*!< LCD PAL24: R04_0 Mask               */
#define LCD_PAL24_G04_0_Pos                                   5                                                         /*!< LCD PAL24: G04_0 Position           */
#define LCD_PAL24_G04_0_Msk                                   (0x1fUL << LCD_PAL24_G04_0_Pos)                           /*!< LCD PAL24: G04_0 Mask               */
#define LCD_PAL24_B04_0_Pos                                   10                                                        /*!< LCD PAL24: B04_0 Position           */
#define LCD_PAL24_B04_0_Msk                                   (0x1fUL << LCD_PAL24_B04_0_Pos)                           /*!< LCD PAL24: B04_0 Mask               */
#define LCD_PAL24_I0_Pos                                      15                                                        /*!< LCD PAL24: I0 Position              */
#define LCD_PAL24_I0_Msk                                      (0x01UL << LCD_PAL24_I0_Pos)                              /*!< LCD PAL24: I0 Mask                  */
#define LCD_PAL24_R14_0_Pos                                   16                                                        /*!< LCD PAL24: R14_0 Position           */
#define LCD_PAL24_R14_0_Msk                                   (0x1fUL << LCD_PAL24_R14_0_Pos)                           /*!< LCD PAL24: R14_0 Mask               */
#define LCD_PAL24_G14_0_Pos                                   21                                                        /*!< LCD PAL24: G14_0 Position           */
#define LCD_PAL24_G14_0_Msk                                   (0x1fUL << LCD_PAL24_G14_0_Pos)                           /*!< LCD PAL24: G14_0 Mask               */
#define LCD_PAL24_B14_0_Pos                                   26                                                        /*!< LCD PAL24: B14_0 Position           */
#define LCD_PAL24_B14_0_Msk                                   (0x1fUL << LCD_PAL24_B14_0_Pos)                           /*!< LCD PAL24: B14_0 Mask               */
#define LCD_PAL24_I1_Pos                                      31                                                        /*!< LCD PAL24: I1 Position              */
#define LCD_PAL24_I1_Msk                                      (0x01UL << LCD_PAL24_I1_Pos)                              /*!< LCD PAL24: I1 Mask                  */

// ----------------------------------------  LCD_PAL25  -------------------------------------------
#define LCD_PAL25_R04_0_Pos                                   0                                                         /*!< LCD PAL25: R04_0 Position           */
#define LCD_PAL25_R04_0_Msk                                   (0x1fUL << LCD_PAL25_R04_0_Pos)                           /*!< LCD PAL25: R04_0 Mask               */
#define LCD_PAL25_G04_0_Pos                                   5                                                         /*!< LCD PAL25: G04_0 Position           */
#define LCD_PAL25_G04_0_Msk                                   (0x1fUL << LCD_PAL25_G04_0_Pos)                           /*!< LCD PAL25: G04_0 Mask               */
#define LCD_PAL25_B04_0_Pos                                   10                                                        /*!< LCD PAL25: B04_0 Position           */
#define LCD_PAL25_B04_0_Msk                                   (0x1fUL << LCD_PAL25_B04_0_Pos)                           /*!< LCD PAL25: B04_0 Mask               */
#define LCD_PAL25_I0_Pos                                      15                                                        /*!< LCD PAL25: I0 Position              */
#define LCD_PAL25_I0_Msk                                      (0x01UL << LCD_PAL25_I0_Pos)                              /*!< LCD PAL25: I0 Mask                  */
#define LCD_PAL25_R14_0_Pos                                   16                                                        /*!< LCD PAL25: R14_0 Position           */
#define LCD_PAL25_R14_0_Msk                                   (0x1fUL << LCD_PAL25_R14_0_Pos)                           /*!< LCD PAL25: R14_0 Mask               */
#define LCD_PAL25_G14_0_Pos                                   21                                                        /*!< LCD PAL25: G14_0 Position           */
#define LCD_PAL25_G14_0_Msk                                   (0x1fUL << LCD_PAL25_G14_0_Pos)                           /*!< LCD PAL25: G14_0 Mask               */
#define LCD_PAL25_B14_0_Pos                                   26                                                        /*!< LCD PAL25: B14_0 Position           */
#define LCD_PAL25_B14_0_Msk                                   (0x1fUL << LCD_PAL25_B14_0_Pos)                           /*!< LCD PAL25: B14_0 Mask               */
#define LCD_PAL25_I1_Pos                                      31                                                        /*!< LCD PAL25: I1 Position              */
#define LCD_PAL25_I1_Msk                                      (0x01UL << LCD_PAL25_I1_Pos)                              /*!< LCD PAL25: I1 Mask                  */

// ----------------------------------------  LCD_PAL26  -------------------------------------------
#define LCD_PAL26_R04_0_Pos                                   0                                                         /*!< LCD PAL26: R04_0 Position           */
#define LCD_PAL26_R04_0_Msk                                   (0x1fUL << LCD_PAL26_R04_0_Pos)                           /*!< LCD PAL26: R04_0 Mask               */
#define LCD_PAL26_G04_0_Pos                                   5                                                         /*!< LCD PAL26: G04_0 Position           */
#define LCD_PAL26_G04_0_Msk                                   (0x1fUL << LCD_PAL26_G04_0_Pos)                           /*!< LCD PAL26: G04_0 Mask               */
#define LCD_PAL26_B04_0_Pos                                   10                                                        /*!< LCD PAL26: B04_0 Position           */
#define LCD_PAL26_B04_0_Msk                                   (0x1fUL << LCD_PAL26_B04_0_Pos)                           /*!< LCD PAL26: B04_0 Mask               */
#define LCD_PAL26_I0_Pos                                      15                                                        /*!< LCD PAL26: I0 Position              */
#define LCD_PAL26_I0_Msk                                      (0x01UL << LCD_PAL26_I0_Pos)                              /*!< LCD PAL26: I0 Mask                  */
#define LCD_PAL26_R14_0_Pos                                   16                                                        /*!< LCD PAL26: R14_0 Position           */
#define LCD_PAL26_R14_0_Msk                                   (0x1fUL << LCD_PAL26_R14_0_Pos)                           /*!< LCD PAL26: R14_0 Mask               */
#define LCD_PAL26_G14_0_Pos                                   21                                                        /*!< LCD PAL26: G14_0 Position           */
#define LCD_PAL26_G14_0_Msk                                   (0x1fUL << LCD_PAL26_G14_0_Pos)                           /*!< LCD PAL26: G14_0 Mask               */
#define LCD_PAL26_B14_0_Pos                                   26                                                        /*!< LCD PAL26: B14_0 Position           */
#define LCD_PAL26_B14_0_Msk                                   (0x1fUL << LCD_PAL26_B14_0_Pos)                           /*!< LCD PAL26: B14_0 Mask               */
#define LCD_PAL26_I1_Pos                                      31                                                        /*!< LCD PAL26: I1 Position              */
#define LCD_PAL26_I1_Msk                                      (0x01UL << LCD_PAL26_I1_Pos)                              /*!< LCD PAL26: I1 Mask                  */

// ----------------------------------------  LCD_PAL27  -------------------------------------------
#define LCD_PAL27_R04_0_Pos                                   0                                                         /*!< LCD PAL27: R04_0 Position           */
#define LCD_PAL27_R04_0_Msk                                   (0x1fUL << LCD_PAL27_R04_0_Pos)                           /*!< LCD PAL27: R04_0 Mask               */
#define LCD_PAL27_G04_0_Pos                                   5                                                         /*!< LCD PAL27: G04_0 Position           */
#define LCD_PAL27_G04_0_Msk                                   (0x1fUL << LCD_PAL27_G04_0_Pos)                           /*!< LCD PAL27: G04_0 Mask               */
#define LCD_PAL27_B04_0_Pos                                   10                                                        /*!< LCD PAL27: B04_0 Position           */
#define LCD_PAL27_B04_0_Msk                                   (0x1fUL << LCD_PAL27_B04_0_Pos)                           /*!< LCD PAL27: B04_0 Mask               */
#define LCD_PAL27_I0_Pos                                      15                                                        /*!< LCD PAL27: I0 Position              */
#define LCD_PAL27_I0_Msk                                      (0x01UL << LCD_PAL27_I0_Pos)                              /*!< LCD PAL27: I0 Mask                  */
#define LCD_PAL27_R14_0_Pos                                   16                                                        /*!< LCD PAL27: R14_0 Position           */
#define LCD_PAL27_R14_0_Msk                                   (0x1fUL << LCD_PAL27_R14_0_Pos)                           /*!< LCD PAL27: R14_0 Mask               */
#define LCD_PAL27_G14_0_Pos                                   21                                                        /*!< LCD PAL27: G14_0 Position           */
#define LCD_PAL27_G14_0_Msk                                   (0x1fUL << LCD_PAL27_G14_0_Pos)                           /*!< LCD PAL27: G14_0 Mask               */
#define LCD_PAL27_B14_0_Pos                                   26                                                        /*!< LCD PAL27: B14_0 Position           */
#define LCD_PAL27_B14_0_Msk                                   (0x1fUL << LCD_PAL27_B14_0_Pos)                           /*!< LCD PAL27: B14_0 Mask               */
#define LCD_PAL27_I1_Pos                                      31                                                        /*!< LCD PAL27: I1 Position              */
#define LCD_PAL27_I1_Msk                                      (0x01UL << LCD_PAL27_I1_Pos)                              /*!< LCD PAL27: I1 Mask                  */

// ----------------------------------------  LCD_PAL28  -------------------------------------------
#define LCD_PAL28_R04_0_Pos                                   0                                                         /*!< LCD PAL28: R04_0 Position           */
#define LCD_PAL28_R04_0_Msk                                   (0x1fUL << LCD_PAL28_R04_0_Pos)                           /*!< LCD PAL28: R04_0 Mask               */
#define LCD_PAL28_G04_0_Pos                                   5                                                         /*!< LCD PAL28: G04_0 Position           */
#define LCD_PAL28_G04_0_Msk                                   (0x1fUL << LCD_PAL28_G04_0_Pos)                           /*!< LCD PAL28: G04_0 Mask               */
#define LCD_PAL28_B04_0_Pos                                   10                                                        /*!< LCD PAL28: B04_0 Position           */
#define LCD_PAL28_B04_0_Msk                                   (0x1fUL << LCD_PAL28_B04_0_Pos)                           /*!< LCD PAL28: B04_0 Mask               */
#define LCD_PAL28_I0_Pos                                      15                                                        /*!< LCD PAL28: I0 Position              */
#define LCD_PAL28_I0_Msk                                      (0x01UL << LCD_PAL28_I0_Pos)                              /*!< LCD PAL28: I0 Mask                  */
#define LCD_PAL28_R14_0_Pos                                   16                                                        /*!< LCD PAL28: R14_0 Position           */
#define LCD_PAL28_R14_0_Msk                                   (0x1fUL << LCD_PAL28_R14_0_Pos)                           /*!< LCD PAL28: R14_0 Mask               */
#define LCD_PAL28_G14_0_Pos                                   21                                                        /*!< LCD PAL28: G14_0 Position           */
#define LCD_PAL28_G14_0_Msk                                   (0x1fUL << LCD_PAL28_G14_0_Pos)                           /*!< LCD PAL28: G14_0 Mask               */
#define LCD_PAL28_B14_0_Pos                                   26                                                        /*!< LCD PAL28: B14_0 Position           */
#define LCD_PAL28_B14_0_Msk                                   (0x1fUL << LCD_PAL28_B14_0_Pos)                           /*!< LCD PAL28: B14_0 Mask               */
#define LCD_PAL28_I1_Pos                                      31                                                        /*!< LCD PAL28: I1 Position              */
#define LCD_PAL28_I1_Msk                                      (0x01UL << LCD_PAL28_I1_Pos)                              /*!< LCD PAL28: I1 Mask                  */

// ----------------------------------------  LCD_PAL29  -------------------------------------------
#define LCD_PAL29_R04_0_Pos                                   0                                                         /*!< LCD PAL29: R04_0 Position           */
#define LCD_PAL29_R04_0_Msk                                   (0x1fUL << LCD_PAL29_R04_0_Pos)                           /*!< LCD PAL29: R04_0 Mask               */
#define LCD_PAL29_G04_0_Pos                                   5                                                         /*!< LCD PAL29: G04_0 Position           */
#define LCD_PAL29_G04_0_Msk                                   (0x1fUL << LCD_PAL29_G04_0_Pos)                           /*!< LCD PAL29: G04_0 Mask               */
#define LCD_PAL29_B04_0_Pos                                   10                                                        /*!< LCD PAL29: B04_0 Position           */
#define LCD_PAL29_B04_0_Msk                                   (0x1fUL << LCD_PAL29_B04_0_Pos)                           /*!< LCD PAL29: B04_0 Mask               */
#define LCD_PAL29_I0_Pos                                      15                                                        /*!< LCD PAL29: I0 Position              */
#define LCD_PAL29_I0_Msk                                      (0x01UL << LCD_PAL29_I0_Pos)                              /*!< LCD PAL29: I0 Mask                  */
#define LCD_PAL29_R14_0_Pos                                   16                                                        /*!< LCD PAL29: R14_0 Position           */
#define LCD_PAL29_R14_0_Msk                                   (0x1fUL << LCD_PAL29_R14_0_Pos)                           /*!< LCD PAL29: R14_0 Mask               */
#define LCD_PAL29_G14_0_Pos                                   21                                                        /*!< LCD PAL29: G14_0 Position           */
#define LCD_PAL29_G14_0_Msk                                   (0x1fUL << LCD_PAL29_G14_0_Pos)                           /*!< LCD PAL29: G14_0 Mask               */
#define LCD_PAL29_B14_0_Pos                                   26                                                        /*!< LCD PAL29: B14_0 Position           */
#define LCD_PAL29_B14_0_Msk                                   (0x1fUL << LCD_PAL29_B14_0_Pos)                           /*!< LCD PAL29: B14_0 Mask               */
#define LCD_PAL29_I1_Pos                                      31                                                        /*!< LCD PAL29: I1 Position              */
#define LCD_PAL29_I1_Msk                                      (0x01UL << LCD_PAL29_I1_Pos)                              /*!< LCD PAL29: I1 Mask                  */

// ----------------------------------------  LCD_PAL30  -------------------------------------------
#define LCD_PAL30_R04_0_Pos                                   0                                                         /*!< LCD PAL30: R04_0 Position           */
#define LCD_PAL30_R04_0_Msk                                   (0x1fUL << LCD_PAL30_R04_0_Pos)                           /*!< LCD PAL30: R04_0 Mask               */
#define LCD_PAL30_G04_0_Pos                                   5                                                         /*!< LCD PAL30: G04_0 Position           */
#define LCD_PAL30_G04_0_Msk                                   (0x1fUL << LCD_PAL30_G04_0_Pos)                           /*!< LCD PAL30: G04_0 Mask               */
#define LCD_PAL30_B04_0_Pos                                   10                                                        /*!< LCD PAL30: B04_0 Position           */
#define LCD_PAL30_B04_0_Msk                                   (0x1fUL << LCD_PAL30_B04_0_Pos)                           /*!< LCD PAL30: B04_0 Mask               */
#define LCD_PAL30_I0_Pos                                      15                                                        /*!< LCD PAL30: I0 Position              */
#define LCD_PAL30_I0_Msk                                      (0x01UL << LCD_PAL30_I0_Pos)                              /*!< LCD PAL30: I0 Mask                  */
#define LCD_PAL30_R14_0_Pos                                   16                                                        /*!< LCD PAL30: R14_0 Position           */
#define LCD_PAL30_R14_0_Msk                                   (0x1fUL << LCD_PAL30_R14_0_Pos)                           /*!< LCD PAL30: R14_0 Mask               */
#define LCD_PAL30_G14_0_Pos                                   21                                                        /*!< LCD PAL30: G14_0 Position           */
#define LCD_PAL30_G14_0_Msk                                   (0x1fUL << LCD_PAL30_G14_0_Pos)                           /*!< LCD PAL30: G14_0 Mask               */
#define LCD_PAL30_B14_0_Pos                                   26                                                        /*!< LCD PAL30: B14_0 Position           */
#define LCD_PAL30_B14_0_Msk                                   (0x1fUL << LCD_PAL30_B14_0_Pos)                           /*!< LCD PAL30: B14_0 Mask               */
#define LCD_PAL30_I1_Pos                                      31                                                        /*!< LCD PAL30: I1 Position              */
#define LCD_PAL30_I1_Msk                                      (0x01UL << LCD_PAL30_I1_Pos)                              /*!< LCD PAL30: I1 Mask                  */

// ----------------------------------------  LCD_PAL31  -------------------------------------------
#define LCD_PAL31_R04_0_Pos                                   0                                                         /*!< LCD PAL31: R04_0 Position           */
#define LCD_PAL31_R04_0_Msk                                   (0x1fUL << LCD_PAL31_R04_0_Pos)                           /*!< LCD PAL31: R04_0 Mask               */
#define LCD_PAL31_G04_0_Pos                                   5                                                         /*!< LCD PAL31: G04_0 Position           */
#define LCD_PAL31_G04_0_Msk                                   (0x1fUL << LCD_PAL31_G04_0_Pos)                           /*!< LCD PAL31: G04_0 Mask               */
#define LCD_PAL31_B04_0_Pos                                   10                                                        /*!< LCD PAL31: B04_0 Position           */
#define LCD_PAL31_B04_0_Msk                                   (0x1fUL << LCD_PAL31_B04_0_Pos)                           /*!< LCD PAL31: B04_0 Mask               */
#define LCD_PAL31_I0_Pos                                      15                                                        /*!< LCD PAL31: I0 Position              */
#define LCD_PAL31_I0_Msk                                      (0x01UL << LCD_PAL31_I0_Pos)                              /*!< LCD PAL31: I0 Mask                  */
#define LCD_PAL31_R14_0_Pos                                   16                                                        /*!< LCD PAL31: R14_0 Position           */
#define LCD_PAL31_R14_0_Msk                                   (0x1fUL << LCD_PAL31_R14_0_Pos)                           /*!< LCD PAL31: R14_0 Mask               */
#define LCD_PAL31_G14_0_Pos                                   21                                                        /*!< LCD PAL31: G14_0 Position           */
#define LCD_PAL31_G14_0_Msk                                   (0x1fUL << LCD_PAL31_G14_0_Pos)                           /*!< LCD PAL31: G14_0 Mask               */
#define LCD_PAL31_B14_0_Pos                                   26                                                        /*!< LCD PAL31: B14_0 Position           */
#define LCD_PAL31_B14_0_Msk                                   (0x1fUL << LCD_PAL31_B14_0_Pos)                           /*!< LCD PAL31: B14_0 Mask               */
#define LCD_PAL31_I1_Pos                                      31                                                        /*!< LCD PAL31: I1 Position              */
#define LCD_PAL31_I1_Msk                                      (0x01UL << LCD_PAL31_I1_Pos)                              /*!< LCD PAL31: I1 Mask                  */

// ----------------------------------------  LCD_PAL32  -------------------------------------------
#define LCD_PAL32_R04_0_Pos                                   0                                                         /*!< LCD PAL32: R04_0 Position           */
#define LCD_PAL32_R04_0_Msk                                   (0x1fUL << LCD_PAL32_R04_0_Pos)                           /*!< LCD PAL32: R04_0 Mask               */
#define LCD_PAL32_G04_0_Pos                                   5                                                         /*!< LCD PAL32: G04_0 Position           */
#define LCD_PAL32_G04_0_Msk                                   (0x1fUL << LCD_PAL32_G04_0_Pos)                           /*!< LCD PAL32: G04_0 Mask               */
#define LCD_PAL32_B04_0_Pos                                   10                                                        /*!< LCD PAL32: B04_0 Position           */
#define LCD_PAL32_B04_0_Msk                                   (0x1fUL << LCD_PAL32_B04_0_Pos)                           /*!< LCD PAL32: B04_0 Mask               */
#define LCD_PAL32_I0_Pos                                      15                                                        /*!< LCD PAL32: I0 Position              */
#define LCD_PAL32_I0_Msk                                      (0x01UL << LCD_PAL32_I0_Pos)                              /*!< LCD PAL32: I0 Mask                  */
#define LCD_PAL32_R14_0_Pos                                   16                                                        /*!< LCD PAL32: R14_0 Position           */
#define LCD_PAL32_R14_0_Msk                                   (0x1fUL << LCD_PAL32_R14_0_Pos)                           /*!< LCD PAL32: R14_0 Mask               */
#define LCD_PAL32_G14_0_Pos                                   21                                                        /*!< LCD PAL32: G14_0 Position           */
#define LCD_PAL32_G14_0_Msk                                   (0x1fUL << LCD_PAL32_G14_0_Pos)                           /*!< LCD PAL32: G14_0 Mask               */
#define LCD_PAL32_B14_0_Pos                                   26                                                        /*!< LCD PAL32: B14_0 Position           */
#define LCD_PAL32_B14_0_Msk                                   (0x1fUL << LCD_PAL32_B14_0_Pos)                           /*!< LCD PAL32: B14_0 Mask               */
#define LCD_PAL32_I1_Pos                                      31                                                        /*!< LCD PAL32: I1 Position              */
#define LCD_PAL32_I1_Msk                                      (0x01UL << LCD_PAL32_I1_Pos)                              /*!< LCD PAL32: I1 Mask                  */

// ----------------------------------------  LCD_PAL33  -------------------------------------------
#define LCD_PAL33_R04_0_Pos                                   0                                                         /*!< LCD PAL33: R04_0 Position           */
#define LCD_PAL33_R04_0_Msk                                   (0x1fUL << LCD_PAL33_R04_0_Pos)                           /*!< LCD PAL33: R04_0 Mask               */
#define LCD_PAL33_G04_0_Pos                                   5                                                         /*!< LCD PAL33: G04_0 Position           */
#define LCD_PAL33_G04_0_Msk                                   (0x1fUL << LCD_PAL33_G04_0_Pos)                           /*!< LCD PAL33: G04_0 Mask               */
#define LCD_PAL33_B04_0_Pos                                   10                                                        /*!< LCD PAL33: B04_0 Position           */
#define LCD_PAL33_B04_0_Msk                                   (0x1fUL << LCD_PAL33_B04_0_Pos)                           /*!< LCD PAL33: B04_0 Mask               */
#define LCD_PAL33_I0_Pos                                      15                                                        /*!< LCD PAL33: I0 Position              */
#define LCD_PAL33_I0_Msk                                      (0x01UL << LCD_PAL33_I0_Pos)                              /*!< LCD PAL33: I0 Mask                  */
#define LCD_PAL33_R14_0_Pos                                   16                                                        /*!< LCD PAL33: R14_0 Position           */
#define LCD_PAL33_R14_0_Msk                                   (0x1fUL << LCD_PAL33_R14_0_Pos)                           /*!< LCD PAL33: R14_0 Mask               */
#define LCD_PAL33_G14_0_Pos                                   21                                                        /*!< LCD PAL33: G14_0 Position           */
#define LCD_PAL33_G14_0_Msk                                   (0x1fUL << LCD_PAL33_G14_0_Pos)                           /*!< LCD PAL33: G14_0 Mask               */
#define LCD_PAL33_B14_0_Pos                                   26                                                        /*!< LCD PAL33: B14_0 Position           */
#define LCD_PAL33_B14_0_Msk                                   (0x1fUL << LCD_PAL33_B14_0_Pos)                           /*!< LCD PAL33: B14_0 Mask               */
#define LCD_PAL33_I1_Pos                                      31                                                        /*!< LCD PAL33: I1 Position              */
#define LCD_PAL33_I1_Msk                                      (0x01UL << LCD_PAL33_I1_Pos)                              /*!< LCD PAL33: I1 Mask                  */

// ----------------------------------------  LCD_PAL34  -------------------------------------------
#define LCD_PAL34_R04_0_Pos                                   0                                                         /*!< LCD PAL34: R04_0 Position           */
#define LCD_PAL34_R04_0_Msk                                   (0x1fUL << LCD_PAL34_R04_0_Pos)                           /*!< LCD PAL34: R04_0 Mask               */
#define LCD_PAL34_G04_0_Pos                                   5                                                         /*!< LCD PAL34: G04_0 Position           */
#define LCD_PAL34_G04_0_Msk                                   (0x1fUL << LCD_PAL34_G04_0_Pos)                           /*!< LCD PAL34: G04_0 Mask               */
#define LCD_PAL34_B04_0_Pos                                   10                                                        /*!< LCD PAL34: B04_0 Position           */
#define LCD_PAL34_B04_0_Msk                                   (0x1fUL << LCD_PAL34_B04_0_Pos)                           /*!< LCD PAL34: B04_0 Mask               */
#define LCD_PAL34_I0_Pos                                      15                                                        /*!< LCD PAL34: I0 Position              */
#define LCD_PAL34_I0_Msk                                      (0x01UL << LCD_PAL34_I0_Pos)                              /*!< LCD PAL34: I0 Mask                  */
#define LCD_PAL34_R14_0_Pos                                   16                                                        /*!< LCD PAL34: R14_0 Position           */
#define LCD_PAL34_R14_0_Msk                                   (0x1fUL << LCD_PAL34_R14_0_Pos)                           /*!< LCD PAL34: R14_0 Mask               */
#define LCD_PAL34_G14_0_Pos                                   21                                                        /*!< LCD PAL34: G14_0 Position           */
#define LCD_PAL34_G14_0_Msk                                   (0x1fUL << LCD_PAL34_G14_0_Pos)                           /*!< LCD PAL34: G14_0 Mask               */
#define LCD_PAL34_B14_0_Pos                                   26                                                        /*!< LCD PAL34: B14_0 Position           */
#define LCD_PAL34_B14_0_Msk                                   (0x1fUL << LCD_PAL34_B14_0_Pos)                           /*!< LCD PAL34: B14_0 Mask               */
#define LCD_PAL34_I1_Pos                                      31                                                        /*!< LCD PAL34: I1 Position              */
#define LCD_PAL34_I1_Msk                                      (0x01UL << LCD_PAL34_I1_Pos)                              /*!< LCD PAL34: I1 Mask                  */

// ----------------------------------------  LCD_PAL35  -------------------------------------------
#define LCD_PAL35_R04_0_Pos                                   0                                                         /*!< LCD PAL35: R04_0 Position           */
#define LCD_PAL35_R04_0_Msk                                   (0x1fUL << LCD_PAL35_R04_0_Pos)                           /*!< LCD PAL35: R04_0 Mask               */
#define LCD_PAL35_G04_0_Pos                                   5                                                         /*!< LCD PAL35: G04_0 Position           */
#define LCD_PAL35_G04_0_Msk                                   (0x1fUL << LCD_PAL35_G04_0_Pos)                           /*!< LCD PAL35: G04_0 Mask               */
#define LCD_PAL35_B04_0_Pos                                   10                                                        /*!< LCD PAL35: B04_0 Position           */
#define LCD_PAL35_B04_0_Msk                                   (0x1fUL << LCD_PAL35_B04_0_Pos)                           /*!< LCD PAL35: B04_0 Mask               */
#define LCD_PAL35_I0_Pos                                      15                                                        /*!< LCD PAL35: I0 Position              */
#define LCD_PAL35_I0_Msk                                      (0x01UL << LCD_PAL35_I0_Pos)                              /*!< LCD PAL35: I0 Mask                  */
#define LCD_PAL35_R14_0_Pos                                   16                                                        /*!< LCD PAL35: R14_0 Position           */
#define LCD_PAL35_R14_0_Msk                                   (0x1fUL << LCD_PAL35_R14_0_Pos)                           /*!< LCD PAL35: R14_0 Mask               */
#define LCD_PAL35_G14_0_Pos                                   21                                                        /*!< LCD PAL35: G14_0 Position           */
#define LCD_PAL35_G14_0_Msk                                   (0x1fUL << LCD_PAL35_G14_0_Pos)                           /*!< LCD PAL35: G14_0 Mask               */
#define LCD_PAL35_B14_0_Pos                                   26                                                        /*!< LCD PAL35: B14_0 Position           */
#define LCD_PAL35_B14_0_Msk                                   (0x1fUL << LCD_PAL35_B14_0_Pos)                           /*!< LCD PAL35: B14_0 Mask               */
#define LCD_PAL35_I1_Pos                                      31                                                        /*!< LCD PAL35: I1 Position              */
#define LCD_PAL35_I1_Msk                                      (0x01UL << LCD_PAL35_I1_Pos)                              /*!< LCD PAL35: I1 Mask                  */

// ----------------------------------------  LCD_PAL36  -------------------------------------------
#define LCD_PAL36_R04_0_Pos                                   0                                                         /*!< LCD PAL36: R04_0 Position           */
#define LCD_PAL36_R04_0_Msk                                   (0x1fUL << LCD_PAL36_R04_0_Pos)                           /*!< LCD PAL36: R04_0 Mask               */
#define LCD_PAL36_G04_0_Pos                                   5                                                         /*!< LCD PAL36: G04_0 Position           */
#define LCD_PAL36_G04_0_Msk                                   (0x1fUL << LCD_PAL36_G04_0_Pos)                           /*!< LCD PAL36: G04_0 Mask               */
#define LCD_PAL36_B04_0_Pos                                   10                                                        /*!< LCD PAL36: B04_0 Position           */
#define LCD_PAL36_B04_0_Msk                                   (0x1fUL << LCD_PAL36_B04_0_Pos)                           /*!< LCD PAL36: B04_0 Mask               */
#define LCD_PAL36_I0_Pos                                      15                                                        /*!< LCD PAL36: I0 Position              */
#define LCD_PAL36_I0_Msk                                      (0x01UL << LCD_PAL36_I0_Pos)                              /*!< LCD PAL36: I0 Mask                  */
#define LCD_PAL36_R14_0_Pos                                   16                                                        /*!< LCD PAL36: R14_0 Position           */
#define LCD_PAL36_R14_0_Msk                                   (0x1fUL << LCD_PAL36_R14_0_Pos)                           /*!< LCD PAL36: R14_0 Mask               */
#define LCD_PAL36_G14_0_Pos                                   21                                                        /*!< LCD PAL36: G14_0 Position           */
#define LCD_PAL36_G14_0_Msk                                   (0x1fUL << LCD_PAL36_G14_0_Pos)                           /*!< LCD PAL36: G14_0 Mask               */
#define LCD_PAL36_B14_0_Pos                                   26                                                        /*!< LCD PAL36: B14_0 Position           */
#define LCD_PAL36_B14_0_Msk                                   (0x1fUL << LCD_PAL36_B14_0_Pos)                           /*!< LCD PAL36: B14_0 Mask               */
#define LCD_PAL36_I1_Pos                                      31                                                        /*!< LCD PAL36: I1 Position              */
#define LCD_PAL36_I1_Msk                                      (0x01UL << LCD_PAL36_I1_Pos)                              /*!< LCD PAL36: I1 Mask                  */

// ----------------------------------------  LCD_PAL37  -------------------------------------------
#define LCD_PAL37_R04_0_Pos                                   0                                                         /*!< LCD PAL37: R04_0 Position           */
#define LCD_PAL37_R04_0_Msk                                   (0x1fUL << LCD_PAL37_R04_0_Pos)                           /*!< LCD PAL37: R04_0 Mask               */
#define LCD_PAL37_G04_0_Pos                                   5                                                         /*!< LCD PAL37: G04_0 Position           */
#define LCD_PAL37_G04_0_Msk                                   (0x1fUL << LCD_PAL37_G04_0_Pos)                           /*!< LCD PAL37: G04_0 Mask               */
#define LCD_PAL37_B04_0_Pos                                   10                                                        /*!< LCD PAL37: B04_0 Position           */
#define LCD_PAL37_B04_0_Msk                                   (0x1fUL << LCD_PAL37_B04_0_Pos)                           /*!< LCD PAL37: B04_0 Mask               */
#define LCD_PAL37_I0_Pos                                      15                                                        /*!< LCD PAL37: I0 Position              */
#define LCD_PAL37_I0_Msk                                      (0x01UL << LCD_PAL37_I0_Pos)                              /*!< LCD PAL37: I0 Mask                  */
#define LCD_PAL37_R14_0_Pos                                   16                                                        /*!< LCD PAL37: R14_0 Position           */
#define LCD_PAL37_R14_0_Msk                                   (0x1fUL << LCD_PAL37_R14_0_Pos)                           /*!< LCD PAL37: R14_0 Mask               */
#define LCD_PAL37_G14_0_Pos                                   21                                                        /*!< LCD PAL37: G14_0 Position           */
#define LCD_PAL37_G14_0_Msk                                   (0x1fUL << LCD_PAL37_G14_0_Pos)                           /*!< LCD PAL37: G14_0 Mask               */
#define LCD_PAL37_B14_0_Pos                                   26                                                        /*!< LCD PAL37: B14_0 Position           */
#define LCD_PAL37_B14_0_Msk                                   (0x1fUL << LCD_PAL37_B14_0_Pos)                           /*!< LCD PAL37: B14_0 Mask               */
#define LCD_PAL37_I1_Pos                                      31                                                        /*!< LCD PAL37: I1 Position              */
#define LCD_PAL37_I1_Msk                                      (0x01UL << LCD_PAL37_I1_Pos)                              /*!< LCD PAL37: I1 Mask                  */

// ----------------------------------------  LCD_PAL38  -------------------------------------------
#define LCD_PAL38_R04_0_Pos                                   0                                                         /*!< LCD PAL38: R04_0 Position           */
#define LCD_PAL38_R04_0_Msk                                   (0x1fUL << LCD_PAL38_R04_0_Pos)                           /*!< LCD PAL38: R04_0 Mask               */
#define LCD_PAL38_G04_0_Pos                                   5                                                         /*!< LCD PAL38: G04_0 Position           */
#define LCD_PAL38_G04_0_Msk                                   (0x1fUL << LCD_PAL38_G04_0_Pos)                           /*!< LCD PAL38: G04_0 Mask               */
#define LCD_PAL38_B04_0_Pos                                   10                                                        /*!< LCD PAL38: B04_0 Position           */
#define LCD_PAL38_B04_0_Msk                                   (0x1fUL << LCD_PAL38_B04_0_Pos)                           /*!< LCD PAL38: B04_0 Mask               */
#define LCD_PAL38_I0_Pos                                      15                                                        /*!< LCD PAL38: I0 Position              */
#define LCD_PAL38_I0_Msk                                      (0x01UL << LCD_PAL38_I0_Pos)                              /*!< LCD PAL38: I0 Mask                  */
#define LCD_PAL38_R14_0_Pos                                   16                                                        /*!< LCD PAL38: R14_0 Position           */
#define LCD_PAL38_R14_0_Msk                                   (0x1fUL << LCD_PAL38_R14_0_Pos)                           /*!< LCD PAL38: R14_0 Mask               */
#define LCD_PAL38_G14_0_Pos                                   21                                                        /*!< LCD PAL38: G14_0 Position           */
#define LCD_PAL38_G14_0_Msk                                   (0x1fUL << LCD_PAL38_G14_0_Pos)                           /*!< LCD PAL38: G14_0 Mask               */
#define LCD_PAL38_B14_0_Pos                                   26                                                        /*!< LCD PAL38: B14_0 Position           */
#define LCD_PAL38_B14_0_Msk                                   (0x1fUL << LCD_PAL38_B14_0_Pos)                           /*!< LCD PAL38: B14_0 Mask               */
#define LCD_PAL38_I1_Pos                                      31                                                        /*!< LCD PAL38: I1 Position              */
#define LCD_PAL38_I1_Msk                                      (0x01UL << LCD_PAL38_I1_Pos)                              /*!< LCD PAL38: I1 Mask                  */

// ----------------------------------------  LCD_PAL39  -------------------------------------------
#define LCD_PAL39_R04_0_Pos                                   0                                                         /*!< LCD PAL39: R04_0 Position           */
#define LCD_PAL39_R04_0_Msk                                   (0x1fUL << LCD_PAL39_R04_0_Pos)                           /*!< LCD PAL39: R04_0 Mask               */
#define LCD_PAL39_G04_0_Pos                                   5                                                         /*!< LCD PAL39: G04_0 Position           */
#define LCD_PAL39_G04_0_Msk                                   (0x1fUL << LCD_PAL39_G04_0_Pos)                           /*!< LCD PAL39: G04_0 Mask               */
#define LCD_PAL39_B04_0_Pos                                   10                                                        /*!< LCD PAL39: B04_0 Position           */
#define LCD_PAL39_B04_0_Msk                                   (0x1fUL << LCD_PAL39_B04_0_Pos)                           /*!< LCD PAL39: B04_0 Mask               */
#define LCD_PAL39_I0_Pos                                      15                                                        /*!< LCD PAL39: I0 Position              */
#define LCD_PAL39_I0_Msk                                      (0x01UL << LCD_PAL39_I0_Pos)                              /*!< LCD PAL39: I0 Mask                  */
#define LCD_PAL39_R14_0_Pos                                   16                                                        /*!< LCD PAL39: R14_0 Position           */
#define LCD_PAL39_R14_0_Msk                                   (0x1fUL << LCD_PAL39_R14_0_Pos)                           /*!< LCD PAL39: R14_0 Mask               */
#define LCD_PAL39_G14_0_Pos                                   21                                                        /*!< LCD PAL39: G14_0 Position           */
#define LCD_PAL39_G14_0_Msk                                   (0x1fUL << LCD_PAL39_G14_0_Pos)                           /*!< LCD PAL39: G14_0 Mask               */
#define LCD_PAL39_B14_0_Pos                                   26                                                        /*!< LCD PAL39: B14_0 Position           */
#define LCD_PAL39_B14_0_Msk                                   (0x1fUL << LCD_PAL39_B14_0_Pos)                           /*!< LCD PAL39: B14_0 Mask               */
#define LCD_PAL39_I1_Pos                                      31                                                        /*!< LCD PAL39: I1 Position              */
#define LCD_PAL39_I1_Msk                                      (0x01UL << LCD_PAL39_I1_Pos)                              /*!< LCD PAL39: I1 Mask                  */

// ----------------------------------------  LCD_PAL40  -------------------------------------------
#define LCD_PAL40_R04_0_Pos                                   0                                                         /*!< LCD PAL40: R04_0 Position           */
#define LCD_PAL40_R04_0_Msk                                   (0x1fUL << LCD_PAL40_R04_0_Pos)                           /*!< LCD PAL40: R04_0 Mask               */
#define LCD_PAL40_G04_0_Pos                                   5                                                         /*!< LCD PAL40: G04_0 Position           */
#define LCD_PAL40_G04_0_Msk                                   (0x1fUL << LCD_PAL40_G04_0_Pos)                           /*!< LCD PAL40: G04_0 Mask               */
#define LCD_PAL40_B04_0_Pos                                   10                                                        /*!< LCD PAL40: B04_0 Position           */
#define LCD_PAL40_B04_0_Msk                                   (0x1fUL << LCD_PAL40_B04_0_Pos)                           /*!< LCD PAL40: B04_0 Mask               */
#define LCD_PAL40_I0_Pos                                      15                                                        /*!< LCD PAL40: I0 Position              */
#define LCD_PAL40_I0_Msk                                      (0x01UL << LCD_PAL40_I0_Pos)                              /*!< LCD PAL40: I0 Mask                  */
#define LCD_PAL40_R14_0_Pos                                   16                                                        /*!< LCD PAL40: R14_0 Position           */
#define LCD_PAL40_R14_0_Msk                                   (0x1fUL << LCD_PAL40_R14_0_Pos)                           /*!< LCD PAL40: R14_0 Mask               */
#define LCD_PAL40_G14_0_Pos                                   21                                                        /*!< LCD PAL40: G14_0 Position           */
#define LCD_PAL40_G14_0_Msk                                   (0x1fUL << LCD_PAL40_G14_0_Pos)                           /*!< LCD PAL40: G14_0 Mask               */
#define LCD_PAL40_B14_0_Pos                                   26                                                        /*!< LCD PAL40: B14_0 Position           */
#define LCD_PAL40_B14_0_Msk                                   (0x1fUL << LCD_PAL40_B14_0_Pos)                           /*!< LCD PAL40: B14_0 Mask               */
#define LCD_PAL40_I1_Pos                                      31                                                        /*!< LCD PAL40: I1 Position              */
#define LCD_PAL40_I1_Msk                                      (0x01UL << LCD_PAL40_I1_Pos)                              /*!< LCD PAL40: I1 Mask                  */

// ----------------------------------------  LCD_PAL41  -------------------------------------------
#define LCD_PAL41_R04_0_Pos                                   0                                                         /*!< LCD PAL41: R04_0 Position           */
#define LCD_PAL41_R04_0_Msk                                   (0x1fUL << LCD_PAL41_R04_0_Pos)                           /*!< LCD PAL41: R04_0 Mask               */
#define LCD_PAL41_G04_0_Pos                                   5                                                         /*!< LCD PAL41: G04_0 Position           */
#define LCD_PAL41_G04_0_Msk                                   (0x1fUL << LCD_PAL41_G04_0_Pos)                           /*!< LCD PAL41: G04_0 Mask               */
#define LCD_PAL41_B04_0_Pos                                   10                                                        /*!< LCD PAL41: B04_0 Position           */
#define LCD_PAL41_B04_0_Msk                                   (0x1fUL << LCD_PAL41_B04_0_Pos)                           /*!< LCD PAL41: B04_0 Mask               */
#define LCD_PAL41_I0_Pos                                      15                                                        /*!< LCD PAL41: I0 Position              */
#define LCD_PAL41_I0_Msk                                      (0x01UL << LCD_PAL41_I0_Pos)                              /*!< LCD PAL41: I0 Mask                  */
#define LCD_PAL41_R14_0_Pos                                   16                                                        /*!< LCD PAL41: R14_0 Position           */
#define LCD_PAL41_R14_0_Msk                                   (0x1fUL << LCD_PAL41_R14_0_Pos)                           /*!< LCD PAL41: R14_0 Mask               */
#define LCD_PAL41_G14_0_Pos                                   21                                                        /*!< LCD PAL41: G14_0 Position           */
#define LCD_PAL41_G14_0_Msk                                   (0x1fUL << LCD_PAL41_G14_0_Pos)                           /*!< LCD PAL41: G14_0 Mask               */
#define LCD_PAL41_B14_0_Pos                                   26                                                        /*!< LCD PAL41: B14_0 Position           */
#define LCD_PAL41_B14_0_Msk                                   (0x1fUL << LCD_PAL41_B14_0_Pos)                           /*!< LCD PAL41: B14_0 Mask               */
#define LCD_PAL41_I1_Pos                                      31                                                        /*!< LCD PAL41: I1 Position              */
#define LCD_PAL41_I1_Msk                                      (0x01UL << LCD_PAL41_I1_Pos)                              /*!< LCD PAL41: I1 Mask                  */

// ----------------------------------------  LCD_PAL42  -------------------------------------------
#define LCD_PAL42_R04_0_Pos                                   0                                                         /*!< LCD PAL42: R04_0 Position           */
#define LCD_PAL42_R04_0_Msk                                   (0x1fUL << LCD_PAL42_R04_0_Pos)                           /*!< LCD PAL42: R04_0 Mask               */
#define LCD_PAL42_G04_0_Pos                                   5                                                         /*!< LCD PAL42: G04_0 Position           */
#define LCD_PAL42_G04_0_Msk                                   (0x1fUL << LCD_PAL42_G04_0_Pos)                           /*!< LCD PAL42: G04_0 Mask               */
#define LCD_PAL42_B04_0_Pos                                   10                                                        /*!< LCD PAL42: B04_0 Position           */
#define LCD_PAL42_B04_0_Msk                                   (0x1fUL << LCD_PAL42_B04_0_Pos)                           /*!< LCD PAL42: B04_0 Mask               */
#define LCD_PAL42_I0_Pos                                      15                                                        /*!< LCD PAL42: I0 Position              */
#define LCD_PAL42_I0_Msk                                      (0x01UL << LCD_PAL42_I0_Pos)                              /*!< LCD PAL42: I0 Mask                  */
#define LCD_PAL42_R14_0_Pos                                   16                                                        /*!< LCD PAL42: R14_0 Position           */
#define LCD_PAL42_R14_0_Msk                                   (0x1fUL << LCD_PAL42_R14_0_Pos)                           /*!< LCD PAL42: R14_0 Mask               */
#define LCD_PAL42_G14_0_Pos                                   21                                                        /*!< LCD PAL42: G14_0 Position           */
#define LCD_PAL42_G14_0_Msk                                   (0x1fUL << LCD_PAL42_G14_0_Pos)                           /*!< LCD PAL42: G14_0 Mask               */
#define LCD_PAL42_B14_0_Pos                                   26                                                        /*!< LCD PAL42: B14_0 Position           */
#define LCD_PAL42_B14_0_Msk                                   (0x1fUL << LCD_PAL42_B14_0_Pos)                           /*!< LCD PAL42: B14_0 Mask               */
#define LCD_PAL42_I1_Pos                                      31                                                        /*!< LCD PAL42: I1 Position              */
#define LCD_PAL42_I1_Msk                                      (0x01UL << LCD_PAL42_I1_Pos)                              /*!< LCD PAL42: I1 Mask                  */

// ----------------------------------------  LCD_PAL43  -------------------------------------------
#define LCD_PAL43_R04_0_Pos                                   0                                                         /*!< LCD PAL43: R04_0 Position           */
#define LCD_PAL43_R04_0_Msk                                   (0x1fUL << LCD_PAL43_R04_0_Pos)                           /*!< LCD PAL43: R04_0 Mask               */
#define LCD_PAL43_G04_0_Pos                                   5                                                         /*!< LCD PAL43: G04_0 Position           */
#define LCD_PAL43_G04_0_Msk                                   (0x1fUL << LCD_PAL43_G04_0_Pos)                           /*!< LCD PAL43: G04_0 Mask               */
#define LCD_PAL43_B04_0_Pos                                   10                                                        /*!< LCD PAL43: B04_0 Position           */
#define LCD_PAL43_B04_0_Msk                                   (0x1fUL << LCD_PAL43_B04_0_Pos)                           /*!< LCD PAL43: B04_0 Mask               */
#define LCD_PAL43_I0_Pos                                      15                                                        /*!< LCD PAL43: I0 Position              */
#define LCD_PAL43_I0_Msk                                      (0x01UL << LCD_PAL43_I0_Pos)                              /*!< LCD PAL43: I0 Mask                  */
#define LCD_PAL43_R14_0_Pos                                   16                                                        /*!< LCD PAL43: R14_0 Position           */
#define LCD_PAL43_R14_0_Msk                                   (0x1fUL << LCD_PAL43_R14_0_Pos)                           /*!< LCD PAL43: R14_0 Mask               */
#define LCD_PAL43_G14_0_Pos                                   21                                                        /*!< LCD PAL43: G14_0 Position           */
#define LCD_PAL43_G14_0_Msk                                   (0x1fUL << LCD_PAL43_G14_0_Pos)                           /*!< LCD PAL43: G14_0 Mask               */
#define LCD_PAL43_B14_0_Pos                                   26                                                        /*!< LCD PAL43: B14_0 Position           */
#define LCD_PAL43_B14_0_Msk                                   (0x1fUL << LCD_PAL43_B14_0_Pos)                           /*!< LCD PAL43: B14_0 Mask               */
#define LCD_PAL43_I1_Pos                                      31                                                        /*!< LCD PAL43: I1 Position              */
#define LCD_PAL43_I1_Msk                                      (0x01UL << LCD_PAL43_I1_Pos)                              /*!< LCD PAL43: I1 Mask                  */

// ----------------------------------------  LCD_PAL44  -------------------------------------------
#define LCD_PAL44_R04_0_Pos                                   0                                                         /*!< LCD PAL44: R04_0 Position           */
#define LCD_PAL44_R04_0_Msk                                   (0x1fUL << LCD_PAL44_R04_0_Pos)                           /*!< LCD PAL44: R04_0 Mask               */
#define LCD_PAL44_G04_0_Pos                                   5                                                         /*!< LCD PAL44: G04_0 Position           */
#define LCD_PAL44_G04_0_Msk                                   (0x1fUL << LCD_PAL44_G04_0_Pos)                           /*!< LCD PAL44: G04_0 Mask               */
#define LCD_PAL44_B04_0_Pos                                   10                                                        /*!< LCD PAL44: B04_0 Position           */
#define LCD_PAL44_B04_0_Msk                                   (0x1fUL << LCD_PAL44_B04_0_Pos)                           /*!< LCD PAL44: B04_0 Mask               */
#define LCD_PAL44_I0_Pos                                      15                                                        /*!< LCD PAL44: I0 Position              */
#define LCD_PAL44_I0_Msk                                      (0x01UL << LCD_PAL44_I0_Pos)                              /*!< LCD PAL44: I0 Mask                  */
#define LCD_PAL44_R14_0_Pos                                   16                                                        /*!< LCD PAL44: R14_0 Position           */
#define LCD_PAL44_R14_0_Msk                                   (0x1fUL << LCD_PAL44_R14_0_Pos)                           /*!< LCD PAL44: R14_0 Mask               */
#define LCD_PAL44_G14_0_Pos                                   21                                                        /*!< LCD PAL44: G14_0 Position           */
#define LCD_PAL44_G14_0_Msk                                   (0x1fUL << LCD_PAL44_G14_0_Pos)                           /*!< LCD PAL44: G14_0 Mask               */
#define LCD_PAL44_B14_0_Pos                                   26                                                        /*!< LCD PAL44: B14_0 Position           */
#define LCD_PAL44_B14_0_Msk                                   (0x1fUL << LCD_PAL44_B14_0_Pos)                           /*!< LCD PAL44: B14_0 Mask               */
#define LCD_PAL44_I1_Pos                                      31                                                        /*!< LCD PAL44: I1 Position              */
#define LCD_PAL44_I1_Msk                                      (0x01UL << LCD_PAL44_I1_Pos)                              /*!< LCD PAL44: I1 Mask                  */

// ----------------------------------------  LCD_PAL45  -------------------------------------------
#define LCD_PAL45_R04_0_Pos                                   0                                                         /*!< LCD PAL45: R04_0 Position           */
#define LCD_PAL45_R04_0_Msk                                   (0x1fUL << LCD_PAL45_R04_0_Pos)                           /*!< LCD PAL45: R04_0 Mask               */
#define LCD_PAL45_G04_0_Pos                                   5                                                         /*!< LCD PAL45: G04_0 Position           */
#define LCD_PAL45_G04_0_Msk                                   (0x1fUL << LCD_PAL45_G04_0_Pos)                           /*!< LCD PAL45: G04_0 Mask               */
#define LCD_PAL45_B04_0_Pos                                   10                                                        /*!< LCD PAL45: B04_0 Position           */
#define LCD_PAL45_B04_0_Msk                                   (0x1fUL << LCD_PAL45_B04_0_Pos)                           /*!< LCD PAL45: B04_0 Mask               */
#define LCD_PAL45_I0_Pos                                      15                                                        /*!< LCD PAL45: I0 Position              */
#define LCD_PAL45_I0_Msk                                      (0x01UL << LCD_PAL45_I0_Pos)                              /*!< LCD PAL45: I0 Mask                  */
#define LCD_PAL45_R14_0_Pos                                   16                                                        /*!< LCD PAL45: R14_0 Position           */
#define LCD_PAL45_R14_0_Msk                                   (0x1fUL << LCD_PAL45_R14_0_Pos)                           /*!< LCD PAL45: R14_0 Mask               */
#define LCD_PAL45_G14_0_Pos                                   21                                                        /*!< LCD PAL45: G14_0 Position           */
#define LCD_PAL45_G14_0_Msk                                   (0x1fUL << LCD_PAL45_G14_0_Pos)                           /*!< LCD PAL45: G14_0 Mask               */
#define LCD_PAL45_B14_0_Pos                                   26                                                        /*!< LCD PAL45: B14_0 Position           */
#define LCD_PAL45_B14_0_Msk                                   (0x1fUL << LCD_PAL45_B14_0_Pos)                           /*!< LCD PAL45: B14_0 Mask               */
#define LCD_PAL45_I1_Pos                                      31                                                        /*!< LCD PAL45: I1 Position              */
#define LCD_PAL45_I1_Msk                                      (0x01UL << LCD_PAL45_I1_Pos)                              /*!< LCD PAL45: I1 Mask                  */

// ----------------------------------------  LCD_PAL46  -------------------------------------------
#define LCD_PAL46_R04_0_Pos                                   0                                                         /*!< LCD PAL46: R04_0 Position           */
#define LCD_PAL46_R04_0_Msk                                   (0x1fUL << LCD_PAL46_R04_0_Pos)                           /*!< LCD PAL46: R04_0 Mask               */
#define LCD_PAL46_G04_0_Pos                                   5                                                         /*!< LCD PAL46: G04_0 Position           */
#define LCD_PAL46_G04_0_Msk                                   (0x1fUL << LCD_PAL46_G04_0_Pos)                           /*!< LCD PAL46: G04_0 Mask               */
#define LCD_PAL46_B04_0_Pos                                   10                                                        /*!< LCD PAL46: B04_0 Position           */
#define LCD_PAL46_B04_0_Msk                                   (0x1fUL << LCD_PAL46_B04_0_Pos)                           /*!< LCD PAL46: B04_0 Mask               */
#define LCD_PAL46_I0_Pos                                      15                                                        /*!< LCD PAL46: I0 Position              */
#define LCD_PAL46_I0_Msk                                      (0x01UL << LCD_PAL46_I0_Pos)                              /*!< LCD PAL46: I0 Mask                  */
#define LCD_PAL46_R14_0_Pos                                   16                                                        /*!< LCD PAL46: R14_0 Position           */
#define LCD_PAL46_R14_0_Msk                                   (0x1fUL << LCD_PAL46_R14_0_Pos)                           /*!< LCD PAL46: R14_0 Mask               */
#define LCD_PAL46_G14_0_Pos                                   21                                                        /*!< LCD PAL46: G14_0 Position           */
#define LCD_PAL46_G14_0_Msk                                   (0x1fUL << LCD_PAL46_G14_0_Pos)                           /*!< LCD PAL46: G14_0 Mask               */
#define LCD_PAL46_B14_0_Pos                                   26                                                        /*!< LCD PAL46: B14_0 Position           */
#define LCD_PAL46_B14_0_Msk                                   (0x1fUL << LCD_PAL46_B14_0_Pos)                           /*!< LCD PAL46: B14_0 Mask               */
#define LCD_PAL46_I1_Pos                                      31                                                        /*!< LCD PAL46: I1 Position              */
#define LCD_PAL46_I1_Msk                                      (0x01UL << LCD_PAL46_I1_Pos)                              /*!< LCD PAL46: I1 Mask                  */

// ----------------------------------------  LCD_PAL47  -------------------------------------------
#define LCD_PAL47_R04_0_Pos                                   0                                                         /*!< LCD PAL47: R04_0 Position           */
#define LCD_PAL47_R04_0_Msk                                   (0x1fUL << LCD_PAL47_R04_0_Pos)                           /*!< LCD PAL47: R04_0 Mask               */
#define LCD_PAL47_G04_0_Pos                                   5                                                         /*!< LCD PAL47: G04_0 Position           */
#define LCD_PAL47_G04_0_Msk                                   (0x1fUL << LCD_PAL47_G04_0_Pos)                           /*!< LCD PAL47: G04_0 Mask               */
#define LCD_PAL47_B04_0_Pos                                   10                                                        /*!< LCD PAL47: B04_0 Position           */
#define LCD_PAL47_B04_0_Msk                                   (0x1fUL << LCD_PAL47_B04_0_Pos)                           /*!< LCD PAL47: B04_0 Mask               */
#define LCD_PAL47_I0_Pos                                      15                                                        /*!< LCD PAL47: I0 Position              */
#define LCD_PAL47_I0_Msk                                      (0x01UL << LCD_PAL47_I0_Pos)                              /*!< LCD PAL47: I0 Mask                  */
#define LCD_PAL47_R14_0_Pos                                   16                                                        /*!< LCD PAL47: R14_0 Position           */
#define LCD_PAL47_R14_0_Msk                                   (0x1fUL << LCD_PAL47_R14_0_Pos)                           /*!< LCD PAL47: R14_0 Mask               */
#define LCD_PAL47_G14_0_Pos                                   21                                                        /*!< LCD PAL47: G14_0 Position           */
#define LCD_PAL47_G14_0_Msk                                   (0x1fUL << LCD_PAL47_G14_0_Pos)                           /*!< LCD PAL47: G14_0 Mask               */
#define LCD_PAL47_B14_0_Pos                                   26                                                        /*!< LCD PAL47: B14_0 Position           */
#define LCD_PAL47_B14_0_Msk                                   (0x1fUL << LCD_PAL47_B14_0_Pos)                           /*!< LCD PAL47: B14_0 Mask               */
#define LCD_PAL47_I1_Pos                                      31                                                        /*!< LCD PAL47: I1 Position              */
#define LCD_PAL47_I1_Msk                                      (0x01UL << LCD_PAL47_I1_Pos)                              /*!< LCD PAL47: I1 Mask                  */

// ----------------------------------------  LCD_PAL48  -------------------------------------------
#define LCD_PAL48_R04_0_Pos                                   0                                                         /*!< LCD PAL48: R04_0 Position           */
#define LCD_PAL48_R04_0_Msk                                   (0x1fUL << LCD_PAL48_R04_0_Pos)                           /*!< LCD PAL48: R04_0 Mask               */
#define LCD_PAL48_G04_0_Pos                                   5                                                         /*!< LCD PAL48: G04_0 Position           */
#define LCD_PAL48_G04_0_Msk                                   (0x1fUL << LCD_PAL48_G04_0_Pos)                           /*!< LCD PAL48: G04_0 Mask               */
#define LCD_PAL48_B04_0_Pos                                   10                                                        /*!< LCD PAL48: B04_0 Position           */
#define LCD_PAL48_B04_0_Msk                                   (0x1fUL << LCD_PAL48_B04_0_Pos)                           /*!< LCD PAL48: B04_0 Mask               */
#define LCD_PAL48_I0_Pos                                      15                                                        /*!< LCD PAL48: I0 Position              */
#define LCD_PAL48_I0_Msk                                      (0x01UL << LCD_PAL48_I0_Pos)                              /*!< LCD PAL48: I0 Mask                  */
#define LCD_PAL48_R14_0_Pos                                   16                                                        /*!< LCD PAL48: R14_0 Position           */
#define LCD_PAL48_R14_0_Msk                                   (0x1fUL << LCD_PAL48_R14_0_Pos)                           /*!< LCD PAL48: R14_0 Mask               */
#define LCD_PAL48_G14_0_Pos                                   21                                                        /*!< LCD PAL48: G14_0 Position           */
#define LCD_PAL48_G14_0_Msk                                   (0x1fUL << LCD_PAL48_G14_0_Pos)                           /*!< LCD PAL48: G14_0 Mask               */
#define LCD_PAL48_B14_0_Pos                                   26                                                        /*!< LCD PAL48: B14_0 Position           */
#define LCD_PAL48_B14_0_Msk                                   (0x1fUL << LCD_PAL48_B14_0_Pos)                           /*!< LCD PAL48: B14_0 Mask               */
#define LCD_PAL48_I1_Pos                                      31                                                        /*!< LCD PAL48: I1 Position              */
#define LCD_PAL48_I1_Msk                                      (0x01UL << LCD_PAL48_I1_Pos)                              /*!< LCD PAL48: I1 Mask                  */

// ----------------------------------------  LCD_PAL49  -------------------------------------------
#define LCD_PAL49_R04_0_Pos                                   0                                                         /*!< LCD PAL49: R04_0 Position           */
#define LCD_PAL49_R04_0_Msk                                   (0x1fUL << LCD_PAL49_R04_0_Pos)                           /*!< LCD PAL49: R04_0 Mask               */
#define LCD_PAL49_G04_0_Pos                                   5                                                         /*!< LCD PAL49: G04_0 Position           */
#define LCD_PAL49_G04_0_Msk                                   (0x1fUL << LCD_PAL49_G04_0_Pos)                           /*!< LCD PAL49: G04_0 Mask               */
#define LCD_PAL49_B04_0_Pos                                   10                                                        /*!< LCD PAL49: B04_0 Position           */
#define LCD_PAL49_B04_0_Msk                                   (0x1fUL << LCD_PAL49_B04_0_Pos)                           /*!< LCD PAL49: B04_0 Mask               */
#define LCD_PAL49_I0_Pos                                      15                                                        /*!< LCD PAL49: I0 Position              */
#define LCD_PAL49_I0_Msk                                      (0x01UL << LCD_PAL49_I0_Pos)                              /*!< LCD PAL49: I0 Mask                  */
#define LCD_PAL49_R14_0_Pos                                   16                                                        /*!< LCD PAL49: R14_0 Position           */
#define LCD_PAL49_R14_0_Msk                                   (0x1fUL << LCD_PAL49_R14_0_Pos)                           /*!< LCD PAL49: R14_0 Mask               */
#define LCD_PAL49_G14_0_Pos                                   21                                                        /*!< LCD PAL49: G14_0 Position           */
#define LCD_PAL49_G14_0_Msk                                   (0x1fUL << LCD_PAL49_G14_0_Pos)                           /*!< LCD PAL49: G14_0 Mask               */
#define LCD_PAL49_B14_0_Pos                                   26                                                        /*!< LCD PAL49: B14_0 Position           */
#define LCD_PAL49_B14_0_Msk                                   (0x1fUL << LCD_PAL49_B14_0_Pos)                           /*!< LCD PAL49: B14_0 Mask               */
#define LCD_PAL49_I1_Pos                                      31                                                        /*!< LCD PAL49: I1 Position              */
#define LCD_PAL49_I1_Msk                                      (0x01UL << LCD_PAL49_I1_Pos)                              /*!< LCD PAL49: I1 Mask                  */

// ----------------------------------------  LCD_PAL50  -------------------------------------------
#define LCD_PAL50_R04_0_Pos                                   0                                                         /*!< LCD PAL50: R04_0 Position           */
#define LCD_PAL50_R04_0_Msk                                   (0x1fUL << LCD_PAL50_R04_0_Pos)                           /*!< LCD PAL50: R04_0 Mask               */
#define LCD_PAL50_G04_0_Pos                                   5                                                         /*!< LCD PAL50: G04_0 Position           */
#define LCD_PAL50_G04_0_Msk                                   (0x1fUL << LCD_PAL50_G04_0_Pos)                           /*!< LCD PAL50: G04_0 Mask               */
#define LCD_PAL50_B04_0_Pos                                   10                                                        /*!< LCD PAL50: B04_0 Position           */
#define LCD_PAL50_B04_0_Msk                                   (0x1fUL << LCD_PAL50_B04_0_Pos)                           /*!< LCD PAL50: B04_0 Mask               */
#define LCD_PAL50_I0_Pos                                      15                                                        /*!< LCD PAL50: I0 Position              */
#define LCD_PAL50_I0_Msk                                      (0x01UL << LCD_PAL50_I0_Pos)                              /*!< LCD PAL50: I0 Mask                  */
#define LCD_PAL50_R14_0_Pos                                   16                                                        /*!< LCD PAL50: R14_0 Position           */
#define LCD_PAL50_R14_0_Msk                                   (0x1fUL << LCD_PAL50_R14_0_Pos)                           /*!< LCD PAL50: R14_0 Mask               */
#define LCD_PAL50_G14_0_Pos                                   21                                                        /*!< LCD PAL50: G14_0 Position           */
#define LCD_PAL50_G14_0_Msk                                   (0x1fUL << LCD_PAL50_G14_0_Pos)                           /*!< LCD PAL50: G14_0 Mask               */
#define LCD_PAL50_B14_0_Pos                                   26                                                        /*!< LCD PAL50: B14_0 Position           */
#define LCD_PAL50_B14_0_Msk                                   (0x1fUL << LCD_PAL50_B14_0_Pos)                           /*!< LCD PAL50: B14_0 Mask               */
#define LCD_PAL50_I1_Pos                                      31                                                        /*!< LCD PAL50: I1 Position              */
#define LCD_PAL50_I1_Msk                                      (0x01UL << LCD_PAL50_I1_Pos)                              /*!< LCD PAL50: I1 Mask                  */

// ----------------------------------------  LCD_PAL51  -------------------------------------------
#define LCD_PAL51_R04_0_Pos                                   0                                                         /*!< LCD PAL51: R04_0 Position           */
#define LCD_PAL51_R04_0_Msk                                   (0x1fUL << LCD_PAL51_R04_0_Pos)                           /*!< LCD PAL51: R04_0 Mask               */
#define LCD_PAL51_G04_0_Pos                                   5                                                         /*!< LCD PAL51: G04_0 Position           */
#define LCD_PAL51_G04_0_Msk                                   (0x1fUL << LCD_PAL51_G04_0_Pos)                           /*!< LCD PAL51: G04_0 Mask               */
#define LCD_PAL51_B04_0_Pos                                   10                                                        /*!< LCD PAL51: B04_0 Position           */
#define LCD_PAL51_B04_0_Msk                                   (0x1fUL << LCD_PAL51_B04_0_Pos)                           /*!< LCD PAL51: B04_0 Mask               */
#define LCD_PAL51_I0_Pos                                      15                                                        /*!< LCD PAL51: I0 Position              */
#define LCD_PAL51_I0_Msk                                      (0x01UL << LCD_PAL51_I0_Pos)                              /*!< LCD PAL51: I0 Mask                  */
#define LCD_PAL51_R14_0_Pos                                   16                                                        /*!< LCD PAL51: R14_0 Position           */
#define LCD_PAL51_R14_0_Msk                                   (0x1fUL << LCD_PAL51_R14_0_Pos)                           /*!< LCD PAL51: R14_0 Mask               */
#define LCD_PAL51_G14_0_Pos                                   21                                                        /*!< LCD PAL51: G14_0 Position           */
#define LCD_PAL51_G14_0_Msk                                   (0x1fUL << LCD_PAL51_G14_0_Pos)                           /*!< LCD PAL51: G14_0 Mask               */
#define LCD_PAL51_B14_0_Pos                                   26                                                        /*!< LCD PAL51: B14_0 Position           */
#define LCD_PAL51_B14_0_Msk                                   (0x1fUL << LCD_PAL51_B14_0_Pos)                           /*!< LCD PAL51: B14_0 Mask               */
#define LCD_PAL51_I1_Pos                                      31                                                        /*!< LCD PAL51: I1 Position              */
#define LCD_PAL51_I1_Msk                                      (0x01UL << LCD_PAL51_I1_Pos)                              /*!< LCD PAL51: I1 Mask                  */

// ----------------------------------------  LCD_PAL52  -------------------------------------------
#define LCD_PAL52_R04_0_Pos                                   0                                                         /*!< LCD PAL52: R04_0 Position           */
#define LCD_PAL52_R04_0_Msk                                   (0x1fUL << LCD_PAL52_R04_0_Pos)                           /*!< LCD PAL52: R04_0 Mask               */
#define LCD_PAL52_G04_0_Pos                                   5                                                         /*!< LCD PAL52: G04_0 Position           */
#define LCD_PAL52_G04_0_Msk                                   (0x1fUL << LCD_PAL52_G04_0_Pos)                           /*!< LCD PAL52: G04_0 Mask               */
#define LCD_PAL52_B04_0_Pos                                   10                                                        /*!< LCD PAL52: B04_0 Position           */
#define LCD_PAL52_B04_0_Msk                                   (0x1fUL << LCD_PAL52_B04_0_Pos)                           /*!< LCD PAL52: B04_0 Mask               */
#define LCD_PAL52_I0_Pos                                      15                                                        /*!< LCD PAL52: I0 Position              */
#define LCD_PAL52_I0_Msk                                      (0x01UL << LCD_PAL52_I0_Pos)                              /*!< LCD PAL52: I0 Mask                  */
#define LCD_PAL52_R14_0_Pos                                   16                                                        /*!< LCD PAL52: R14_0 Position           */
#define LCD_PAL52_R14_0_Msk                                   (0x1fUL << LCD_PAL52_R14_0_Pos)                           /*!< LCD PAL52: R14_0 Mask               */
#define LCD_PAL52_G14_0_Pos                                   21                                                        /*!< LCD PAL52: G14_0 Position           */
#define LCD_PAL52_G14_0_Msk                                   (0x1fUL << LCD_PAL52_G14_0_Pos)                           /*!< LCD PAL52: G14_0 Mask               */
#define LCD_PAL52_B14_0_Pos                                   26                                                        /*!< LCD PAL52: B14_0 Position           */
#define LCD_PAL52_B14_0_Msk                                   (0x1fUL << LCD_PAL52_B14_0_Pos)                           /*!< LCD PAL52: B14_0 Mask               */
#define LCD_PAL52_I1_Pos                                      31                                                        /*!< LCD PAL52: I1 Position              */
#define LCD_PAL52_I1_Msk                                      (0x01UL << LCD_PAL52_I1_Pos)                              /*!< LCD PAL52: I1 Mask                  */

// ----------------------------------------  LCD_PAL53  -------------------------------------------
#define LCD_PAL53_R04_0_Pos                                   0                                                         /*!< LCD PAL53: R04_0 Position           */
#define LCD_PAL53_R04_0_Msk                                   (0x1fUL << LCD_PAL53_R04_0_Pos)                           /*!< LCD PAL53: R04_0 Mask               */
#define LCD_PAL53_G04_0_Pos                                   5                                                         /*!< LCD PAL53: G04_0 Position           */
#define LCD_PAL53_G04_0_Msk                                   (0x1fUL << LCD_PAL53_G04_0_Pos)                           /*!< LCD PAL53: G04_0 Mask               */
#define LCD_PAL53_B04_0_Pos                                   10                                                        /*!< LCD PAL53: B04_0 Position           */
#define LCD_PAL53_B04_0_Msk                                   (0x1fUL << LCD_PAL53_B04_0_Pos)                           /*!< LCD PAL53: B04_0 Mask               */
#define LCD_PAL53_I0_Pos                                      15                                                        /*!< LCD PAL53: I0 Position              */
#define LCD_PAL53_I0_Msk                                      (0x01UL << LCD_PAL53_I0_Pos)                              /*!< LCD PAL53: I0 Mask                  */
#define LCD_PAL53_R14_0_Pos                                   16                                                        /*!< LCD PAL53: R14_0 Position           */
#define LCD_PAL53_R14_0_Msk                                   (0x1fUL << LCD_PAL53_R14_0_Pos)                           /*!< LCD PAL53: R14_0 Mask               */
#define LCD_PAL53_G14_0_Pos                                   21                                                        /*!< LCD PAL53: G14_0 Position           */
#define LCD_PAL53_G14_0_Msk                                   (0x1fUL << LCD_PAL53_G14_0_Pos)                           /*!< LCD PAL53: G14_0 Mask               */
#define LCD_PAL53_B14_0_Pos                                   26                                                        /*!< LCD PAL53: B14_0 Position           */
#define LCD_PAL53_B14_0_Msk                                   (0x1fUL << LCD_PAL53_B14_0_Pos)                           /*!< LCD PAL53: B14_0 Mask               */
#define LCD_PAL53_I1_Pos                                      31                                                        /*!< LCD PAL53: I1 Position              */
#define LCD_PAL53_I1_Msk                                      (0x01UL << LCD_PAL53_I1_Pos)                              /*!< LCD PAL53: I1 Mask                  */

// ----------------------------------------  LCD_PAL54  -------------------------------------------
#define LCD_PAL54_R04_0_Pos                                   0                                                         /*!< LCD PAL54: R04_0 Position           */
#define LCD_PAL54_R04_0_Msk                                   (0x1fUL << LCD_PAL54_R04_0_Pos)                           /*!< LCD PAL54: R04_0 Mask               */
#define LCD_PAL54_G04_0_Pos                                   5                                                         /*!< LCD PAL54: G04_0 Position           */
#define LCD_PAL54_G04_0_Msk                                   (0x1fUL << LCD_PAL54_G04_0_Pos)                           /*!< LCD PAL54: G04_0 Mask               */
#define LCD_PAL54_B04_0_Pos                                   10                                                        /*!< LCD PAL54: B04_0 Position           */
#define LCD_PAL54_B04_0_Msk                                   (0x1fUL << LCD_PAL54_B04_0_Pos)                           /*!< LCD PAL54: B04_0 Mask               */
#define LCD_PAL54_I0_Pos                                      15                                                        /*!< LCD PAL54: I0 Position              */
#define LCD_PAL54_I0_Msk                                      (0x01UL << LCD_PAL54_I0_Pos)                              /*!< LCD PAL54: I0 Mask                  */
#define LCD_PAL54_R14_0_Pos                                   16                                                        /*!< LCD PAL54: R14_0 Position           */
#define LCD_PAL54_R14_0_Msk                                   (0x1fUL << LCD_PAL54_R14_0_Pos)                           /*!< LCD PAL54: R14_0 Mask               */
#define LCD_PAL54_G14_0_Pos                                   21                                                        /*!< LCD PAL54: G14_0 Position           */
#define LCD_PAL54_G14_0_Msk                                   (0x1fUL << LCD_PAL54_G14_0_Pos)                           /*!< LCD PAL54: G14_0 Mask               */
#define LCD_PAL54_B14_0_Pos                                   26                                                        /*!< LCD PAL54: B14_0 Position           */
#define LCD_PAL54_B14_0_Msk                                   (0x1fUL << LCD_PAL54_B14_0_Pos)                           /*!< LCD PAL54: B14_0 Mask               */
#define LCD_PAL54_I1_Pos                                      31                                                        /*!< LCD PAL54: I1 Position              */
#define LCD_PAL54_I1_Msk                                      (0x01UL << LCD_PAL54_I1_Pos)                              /*!< LCD PAL54: I1 Mask                  */

// ----------------------------------------  LCD_PAL55  -------------------------------------------
#define LCD_PAL55_R04_0_Pos                                   0                                                         /*!< LCD PAL55: R04_0 Position           */
#define LCD_PAL55_R04_0_Msk                                   (0x1fUL << LCD_PAL55_R04_0_Pos)                           /*!< LCD PAL55: R04_0 Mask               */
#define LCD_PAL55_G04_0_Pos                                   5                                                         /*!< LCD PAL55: G04_0 Position           */
#define LCD_PAL55_G04_0_Msk                                   (0x1fUL << LCD_PAL55_G04_0_Pos)                           /*!< LCD PAL55: G04_0 Mask               */
#define LCD_PAL55_B04_0_Pos                                   10                                                        /*!< LCD PAL55: B04_0 Position           */
#define LCD_PAL55_B04_0_Msk                                   (0x1fUL << LCD_PAL55_B04_0_Pos)                           /*!< LCD PAL55: B04_0 Mask               */
#define LCD_PAL55_I0_Pos                                      15                                                        /*!< LCD PAL55: I0 Position              */
#define LCD_PAL55_I0_Msk                                      (0x01UL << LCD_PAL55_I0_Pos)                              /*!< LCD PAL55: I0 Mask                  */
#define LCD_PAL55_R14_0_Pos                                   16                                                        /*!< LCD PAL55: R14_0 Position           */
#define LCD_PAL55_R14_0_Msk                                   (0x1fUL << LCD_PAL55_R14_0_Pos)                           /*!< LCD PAL55: R14_0 Mask               */
#define LCD_PAL55_G14_0_Pos                                   21                                                        /*!< LCD PAL55: G14_0 Position           */
#define LCD_PAL55_G14_0_Msk                                   (0x1fUL << LCD_PAL55_G14_0_Pos)                           /*!< LCD PAL55: G14_0 Mask               */
#define LCD_PAL55_B14_0_Pos                                   26                                                        /*!< LCD PAL55: B14_0 Position           */
#define LCD_PAL55_B14_0_Msk                                   (0x1fUL << LCD_PAL55_B14_0_Pos)                           /*!< LCD PAL55: B14_0 Mask               */
#define LCD_PAL55_I1_Pos                                      31                                                        /*!< LCD PAL55: I1 Position              */
#define LCD_PAL55_I1_Msk                                      (0x01UL << LCD_PAL55_I1_Pos)                              /*!< LCD PAL55: I1 Mask                  */

// ----------------------------------------  LCD_PAL56  -------------------------------------------
#define LCD_PAL56_R04_0_Pos                                   0                                                         /*!< LCD PAL56: R04_0 Position           */
#define LCD_PAL56_R04_0_Msk                                   (0x1fUL << LCD_PAL56_R04_0_Pos)                           /*!< LCD PAL56: R04_0 Mask               */
#define LCD_PAL56_G04_0_Pos                                   5                                                         /*!< LCD PAL56: G04_0 Position           */
#define LCD_PAL56_G04_0_Msk                                   (0x1fUL << LCD_PAL56_G04_0_Pos)                           /*!< LCD PAL56: G04_0 Mask               */
#define LCD_PAL56_B04_0_Pos                                   10                                                        /*!< LCD PAL56: B04_0 Position           */
#define LCD_PAL56_B04_0_Msk                                   (0x1fUL << LCD_PAL56_B04_0_Pos)                           /*!< LCD PAL56: B04_0 Mask               */
#define LCD_PAL56_I0_Pos                                      15                                                        /*!< LCD PAL56: I0 Position              */
#define LCD_PAL56_I0_Msk                                      (0x01UL << LCD_PAL56_I0_Pos)                              /*!< LCD PAL56: I0 Mask                  */
#define LCD_PAL56_R14_0_Pos                                   16                                                        /*!< LCD PAL56: R14_0 Position           */
#define LCD_PAL56_R14_0_Msk                                   (0x1fUL << LCD_PAL56_R14_0_Pos)                           /*!< LCD PAL56: R14_0 Mask               */
#define LCD_PAL56_G14_0_Pos                                   21                                                        /*!< LCD PAL56: G14_0 Position           */
#define LCD_PAL56_G14_0_Msk                                   (0x1fUL << LCD_PAL56_G14_0_Pos)                           /*!< LCD PAL56: G14_0 Mask               */
#define LCD_PAL56_B14_0_Pos                                   26                                                        /*!< LCD PAL56: B14_0 Position           */
#define LCD_PAL56_B14_0_Msk                                   (0x1fUL << LCD_PAL56_B14_0_Pos)                           /*!< LCD PAL56: B14_0 Mask               */
#define LCD_PAL56_I1_Pos                                      31                                                        /*!< LCD PAL56: I1 Position              */
#define LCD_PAL56_I1_Msk                                      (0x01UL << LCD_PAL56_I1_Pos)                              /*!< LCD PAL56: I1 Mask                  */

// ----------------------------------------  LCD_PAL57  -------------------------------------------
#define LCD_PAL57_R04_0_Pos                                   0                                                         /*!< LCD PAL57: R04_0 Position           */
#define LCD_PAL57_R04_0_Msk                                   (0x1fUL << LCD_PAL57_R04_0_Pos)                           /*!< LCD PAL57: R04_0 Mask               */
#define LCD_PAL57_G04_0_Pos                                   5                                                         /*!< LCD PAL57: G04_0 Position           */
#define LCD_PAL57_G04_0_Msk                                   (0x1fUL << LCD_PAL57_G04_0_Pos)                           /*!< LCD PAL57: G04_0 Mask               */
#define LCD_PAL57_B04_0_Pos                                   10                                                        /*!< LCD PAL57: B04_0 Position           */
#define LCD_PAL57_B04_0_Msk                                   (0x1fUL << LCD_PAL57_B04_0_Pos)                           /*!< LCD PAL57: B04_0 Mask               */
#define LCD_PAL57_I0_Pos                                      15                                                        /*!< LCD PAL57: I0 Position              */
#define LCD_PAL57_I0_Msk                                      (0x01UL << LCD_PAL57_I0_Pos)                              /*!< LCD PAL57: I0 Mask                  */
#define LCD_PAL57_R14_0_Pos                                   16                                                        /*!< LCD PAL57: R14_0 Position           */
#define LCD_PAL57_R14_0_Msk                                   (0x1fUL << LCD_PAL57_R14_0_Pos)                           /*!< LCD PAL57: R14_0 Mask               */
#define LCD_PAL57_G14_0_Pos                                   21                                                        /*!< LCD PAL57: G14_0 Position           */
#define LCD_PAL57_G14_0_Msk                                   (0x1fUL << LCD_PAL57_G14_0_Pos)                           /*!< LCD PAL57: G14_0 Mask               */
#define LCD_PAL57_B14_0_Pos                                   26                                                        /*!< LCD PAL57: B14_0 Position           */
#define LCD_PAL57_B14_0_Msk                                   (0x1fUL << LCD_PAL57_B14_0_Pos)                           /*!< LCD PAL57: B14_0 Mask               */
#define LCD_PAL57_I1_Pos                                      31                                                        /*!< LCD PAL57: I1 Position              */
#define LCD_PAL57_I1_Msk                                      (0x01UL << LCD_PAL57_I1_Pos)                              /*!< LCD PAL57: I1 Mask                  */

// ----------------------------------------  LCD_PAL58  -------------------------------------------
#define LCD_PAL58_R04_0_Pos                                   0                                                         /*!< LCD PAL58: R04_0 Position           */
#define LCD_PAL58_R04_0_Msk                                   (0x1fUL << LCD_PAL58_R04_0_Pos)                           /*!< LCD PAL58: R04_0 Mask               */
#define LCD_PAL58_G04_0_Pos                                   5                                                         /*!< LCD PAL58: G04_0 Position           */
#define LCD_PAL58_G04_0_Msk                                   (0x1fUL << LCD_PAL58_G04_0_Pos)                           /*!< LCD PAL58: G04_0 Mask               */
#define LCD_PAL58_B04_0_Pos                                   10                                                        /*!< LCD PAL58: B04_0 Position           */
#define LCD_PAL58_B04_0_Msk                                   (0x1fUL << LCD_PAL58_B04_0_Pos)                           /*!< LCD PAL58: B04_0 Mask               */
#define LCD_PAL58_I0_Pos                                      15                                                        /*!< LCD PAL58: I0 Position              */
#define LCD_PAL58_I0_Msk                                      (0x01UL << LCD_PAL58_I0_Pos)                              /*!< LCD PAL58: I0 Mask                  */
#define LCD_PAL58_R14_0_Pos                                   16                                                        /*!< LCD PAL58: R14_0 Position           */
#define LCD_PAL58_R14_0_Msk                                   (0x1fUL << LCD_PAL58_R14_0_Pos)                           /*!< LCD PAL58: R14_0 Mask               */
#define LCD_PAL58_G14_0_Pos                                   21                                                        /*!< LCD PAL58: G14_0 Position           */
#define LCD_PAL58_G14_0_Msk                                   (0x1fUL << LCD_PAL58_G14_0_Pos)                           /*!< LCD PAL58: G14_0 Mask               */
#define LCD_PAL58_B14_0_Pos                                   26                                                        /*!< LCD PAL58: B14_0 Position           */
#define LCD_PAL58_B14_0_Msk                                   (0x1fUL << LCD_PAL58_B14_0_Pos)                           /*!< LCD PAL58: B14_0 Mask               */
#define LCD_PAL58_I1_Pos                                      31                                                        /*!< LCD PAL58: I1 Position              */
#define LCD_PAL58_I1_Msk                                      (0x01UL << LCD_PAL58_I1_Pos)                              /*!< LCD PAL58: I1 Mask                  */

// ----------------------------------------  LCD_PAL59  -------------------------------------------
#define LCD_PAL59_R04_0_Pos                                   0                                                         /*!< LCD PAL59: R04_0 Position           */
#define LCD_PAL59_R04_0_Msk                                   (0x1fUL << LCD_PAL59_R04_0_Pos)                           /*!< LCD PAL59: R04_0 Mask               */
#define LCD_PAL59_G04_0_Pos                                   5                                                         /*!< LCD PAL59: G04_0 Position           */
#define LCD_PAL59_G04_0_Msk                                   (0x1fUL << LCD_PAL59_G04_0_Pos)                           /*!< LCD PAL59: G04_0 Mask               */
#define LCD_PAL59_B04_0_Pos                                   10                                                        /*!< LCD PAL59: B04_0 Position           */
#define LCD_PAL59_B04_0_Msk                                   (0x1fUL << LCD_PAL59_B04_0_Pos)                           /*!< LCD PAL59: B04_0 Mask               */
#define LCD_PAL59_I0_Pos                                      15                                                        /*!< LCD PAL59: I0 Position              */
#define LCD_PAL59_I0_Msk                                      (0x01UL << LCD_PAL59_I0_Pos)                              /*!< LCD PAL59: I0 Mask                  */
#define LCD_PAL59_R14_0_Pos                                   16                                                        /*!< LCD PAL59: R14_0 Position           */
#define LCD_PAL59_R14_0_Msk                                   (0x1fUL << LCD_PAL59_R14_0_Pos)                           /*!< LCD PAL59: R14_0 Mask               */
#define LCD_PAL59_G14_0_Pos                                   21                                                        /*!< LCD PAL59: G14_0 Position           */
#define LCD_PAL59_G14_0_Msk                                   (0x1fUL << LCD_PAL59_G14_0_Pos)                           /*!< LCD PAL59: G14_0 Mask               */
#define LCD_PAL59_B14_0_Pos                                   26                                                        /*!< LCD PAL59: B14_0 Position           */
#define LCD_PAL59_B14_0_Msk                                   (0x1fUL << LCD_PAL59_B14_0_Pos)                           /*!< LCD PAL59: B14_0 Mask               */
#define LCD_PAL59_I1_Pos                                      31                                                        /*!< LCD PAL59: I1 Position              */
#define LCD_PAL59_I1_Msk                                      (0x01UL << LCD_PAL59_I1_Pos)                              /*!< LCD PAL59: I1 Mask                  */

// ----------------------------------------  LCD_PAL60  -------------------------------------------
#define LCD_PAL60_R04_0_Pos                                   0                                                         /*!< LCD PAL60: R04_0 Position           */
#define LCD_PAL60_R04_0_Msk                                   (0x1fUL << LCD_PAL60_R04_0_Pos)                           /*!< LCD PAL60: R04_0 Mask               */
#define LCD_PAL60_G04_0_Pos                                   5                                                         /*!< LCD PAL60: G04_0 Position           */
#define LCD_PAL60_G04_0_Msk                                   (0x1fUL << LCD_PAL60_G04_0_Pos)                           /*!< LCD PAL60: G04_0 Mask               */
#define LCD_PAL60_B04_0_Pos                                   10                                                        /*!< LCD PAL60: B04_0 Position           */
#define LCD_PAL60_B04_0_Msk                                   (0x1fUL << LCD_PAL60_B04_0_Pos)                           /*!< LCD PAL60: B04_0 Mask               */
#define LCD_PAL60_I0_Pos                                      15                                                        /*!< LCD PAL60: I0 Position              */
#define LCD_PAL60_I0_Msk                                      (0x01UL << LCD_PAL60_I0_Pos)                              /*!< LCD PAL60: I0 Mask                  */
#define LCD_PAL60_R14_0_Pos                                   16                                                        /*!< LCD PAL60: R14_0 Position           */
#define LCD_PAL60_R14_0_Msk                                   (0x1fUL << LCD_PAL60_R14_0_Pos)                           /*!< LCD PAL60: R14_0 Mask               */
#define LCD_PAL60_G14_0_Pos                                   21                                                        /*!< LCD PAL60: G14_0 Position           */
#define LCD_PAL60_G14_0_Msk                                   (0x1fUL << LCD_PAL60_G14_0_Pos)                           /*!< LCD PAL60: G14_0 Mask               */
#define LCD_PAL60_B14_0_Pos                                   26                                                        /*!< LCD PAL60: B14_0 Position           */
#define LCD_PAL60_B14_0_Msk                                   (0x1fUL << LCD_PAL60_B14_0_Pos)                           /*!< LCD PAL60: B14_0 Mask               */
#define LCD_PAL60_I1_Pos                                      31                                                        /*!< LCD PAL60: I1 Position              */
#define LCD_PAL60_I1_Msk                                      (0x01UL << LCD_PAL60_I1_Pos)                              /*!< LCD PAL60: I1 Mask                  */

// ----------------------------------------  LCD_PAL61  -------------------------------------------
#define LCD_PAL61_R04_0_Pos                                   0                                                         /*!< LCD PAL61: R04_0 Position           */
#define LCD_PAL61_R04_0_Msk                                   (0x1fUL << LCD_PAL61_R04_0_Pos)                           /*!< LCD PAL61: R04_0 Mask               */
#define LCD_PAL61_G04_0_Pos                                   5                                                         /*!< LCD PAL61: G04_0 Position           */
#define LCD_PAL61_G04_0_Msk                                   (0x1fUL << LCD_PAL61_G04_0_Pos)                           /*!< LCD PAL61: G04_0 Mask               */
#define LCD_PAL61_B04_0_Pos                                   10                                                        /*!< LCD PAL61: B04_0 Position           */
#define LCD_PAL61_B04_0_Msk                                   (0x1fUL << LCD_PAL61_B04_0_Pos)                           /*!< LCD PAL61: B04_0 Mask               */
#define LCD_PAL61_I0_Pos                                      15                                                        /*!< LCD PAL61: I0 Position              */
#define LCD_PAL61_I0_Msk                                      (0x01UL << LCD_PAL61_I0_Pos)                              /*!< LCD PAL61: I0 Mask                  */
#define LCD_PAL61_R14_0_Pos                                   16                                                        /*!< LCD PAL61: R14_0 Position           */
#define LCD_PAL61_R14_0_Msk                                   (0x1fUL << LCD_PAL61_R14_0_Pos)                           /*!< LCD PAL61: R14_0 Mask               */
#define LCD_PAL61_G14_0_Pos                                   21                                                        /*!< LCD PAL61: G14_0 Position           */
#define LCD_PAL61_G14_0_Msk                                   (0x1fUL << LCD_PAL61_G14_0_Pos)                           /*!< LCD PAL61: G14_0 Mask               */
#define LCD_PAL61_B14_0_Pos                                   26                                                        /*!< LCD PAL61: B14_0 Position           */
#define LCD_PAL61_B14_0_Msk                                   (0x1fUL << LCD_PAL61_B14_0_Pos)                           /*!< LCD PAL61: B14_0 Mask               */
#define LCD_PAL61_I1_Pos                                      31                                                        /*!< LCD PAL61: I1 Position              */
#define LCD_PAL61_I1_Msk                                      (0x01UL << LCD_PAL61_I1_Pos)                              /*!< LCD PAL61: I1 Mask                  */

// ----------------------------------------  LCD_PAL62  -------------------------------------------
#define LCD_PAL62_R04_0_Pos                                   0                                                         /*!< LCD PAL62: R04_0 Position           */
#define LCD_PAL62_R04_0_Msk                                   (0x1fUL << LCD_PAL62_R04_0_Pos)                           /*!< LCD PAL62: R04_0 Mask               */
#define LCD_PAL62_G04_0_Pos                                   5                                                         /*!< LCD PAL62: G04_0 Position           */
#define LCD_PAL62_G04_0_Msk                                   (0x1fUL << LCD_PAL62_G04_0_Pos)                           /*!< LCD PAL62: G04_0 Mask               */
#define LCD_PAL62_B04_0_Pos                                   10                                                        /*!< LCD PAL62: B04_0 Position           */
#define LCD_PAL62_B04_0_Msk                                   (0x1fUL << LCD_PAL62_B04_0_Pos)                           /*!< LCD PAL62: B04_0 Mask               */
#define LCD_PAL62_I0_Pos                                      15                                                        /*!< LCD PAL62: I0 Position              */
#define LCD_PAL62_I0_Msk                                      (0x01UL << LCD_PAL62_I0_Pos)                              /*!< LCD PAL62: I0 Mask                  */
#define LCD_PAL62_R14_0_Pos                                   16                                                        /*!< LCD PAL62: R14_0 Position           */
#define LCD_PAL62_R14_0_Msk                                   (0x1fUL << LCD_PAL62_R14_0_Pos)                           /*!< LCD PAL62: R14_0 Mask               */
#define LCD_PAL62_G14_0_Pos                                   21                                                        /*!< LCD PAL62: G14_0 Position           */
#define LCD_PAL62_G14_0_Msk                                   (0x1fUL << LCD_PAL62_G14_0_Pos)                           /*!< LCD PAL62: G14_0 Mask               */
#define LCD_PAL62_B14_0_Pos                                   26                                                        /*!< LCD PAL62: B14_0 Position           */
#define LCD_PAL62_B14_0_Msk                                   (0x1fUL << LCD_PAL62_B14_0_Pos)                           /*!< LCD PAL62: B14_0 Mask               */
#define LCD_PAL62_I1_Pos                                      31                                                        /*!< LCD PAL62: I1 Position              */
#define LCD_PAL62_I1_Msk                                      (0x01UL << LCD_PAL62_I1_Pos)                              /*!< LCD PAL62: I1 Mask                  */

// ----------------------------------------  LCD_PAL63  -------------------------------------------
#define LCD_PAL63_R04_0_Pos                                   0                                                         /*!< LCD PAL63: R04_0 Position           */
#define LCD_PAL63_R04_0_Msk                                   (0x1fUL << LCD_PAL63_R04_0_Pos)                           /*!< LCD PAL63: R04_0 Mask               */
#define LCD_PAL63_G04_0_Pos                                   5                                                         /*!< LCD PAL63: G04_0 Position           */
#define LCD_PAL63_G04_0_Msk                                   (0x1fUL << LCD_PAL63_G04_0_Pos)                           /*!< LCD PAL63: G04_0 Mask               */
#define LCD_PAL63_B04_0_Pos                                   10                                                        /*!< LCD PAL63: B04_0 Position           */
#define LCD_PAL63_B04_0_Msk                                   (0x1fUL << LCD_PAL63_B04_0_Pos)                           /*!< LCD PAL63: B04_0 Mask               */
#define LCD_PAL63_I0_Pos                                      15                                                        /*!< LCD PAL63: I0 Position              */
#define LCD_PAL63_I0_Msk                                      (0x01UL << LCD_PAL63_I0_Pos)                              /*!< LCD PAL63: I0 Mask                  */
#define LCD_PAL63_R14_0_Pos                                   16                                                        /*!< LCD PAL63: R14_0 Position           */
#define LCD_PAL63_R14_0_Msk                                   (0x1fUL << LCD_PAL63_R14_0_Pos)                           /*!< LCD PAL63: R14_0 Mask               */
#define LCD_PAL63_G14_0_Pos                                   21                                                        /*!< LCD PAL63: G14_0 Position           */
#define LCD_PAL63_G14_0_Msk                                   (0x1fUL << LCD_PAL63_G14_0_Pos)                           /*!< LCD PAL63: G14_0 Mask               */
#define LCD_PAL63_B14_0_Pos                                   26                                                        /*!< LCD PAL63: B14_0 Position           */
#define LCD_PAL63_B14_0_Msk                                   (0x1fUL << LCD_PAL63_B14_0_Pos)                           /*!< LCD PAL63: B14_0 Mask               */
#define LCD_PAL63_I1_Pos                                      31                                                        /*!< LCD PAL63: I1 Position              */
#define LCD_PAL63_I1_Msk                                      (0x01UL << LCD_PAL63_I1_Pos)                              /*!< LCD PAL63: I1 Mask                  */

// ----------------------------------------  LCD_PAL64  -------------------------------------------
#define LCD_PAL64_R04_0_Pos                                   0                                                         /*!< LCD PAL64: R04_0 Position           */
#define LCD_PAL64_R04_0_Msk                                   (0x1fUL << LCD_PAL64_R04_0_Pos)                           /*!< LCD PAL64: R04_0 Mask               */
#define LCD_PAL64_G04_0_Pos                                   5                                                         /*!< LCD PAL64: G04_0 Position           */
#define LCD_PAL64_G04_0_Msk                                   (0x1fUL << LCD_PAL64_G04_0_Pos)                           /*!< LCD PAL64: G04_0 Mask               */
#define LCD_PAL64_B04_0_Pos                                   10                                                        /*!< LCD PAL64: B04_0 Position           */
#define LCD_PAL64_B04_0_Msk                                   (0x1fUL << LCD_PAL64_B04_0_Pos)                           /*!< LCD PAL64: B04_0 Mask               */
#define LCD_PAL64_I0_Pos                                      15                                                        /*!< LCD PAL64: I0 Position              */
#define LCD_PAL64_I0_Msk                                      (0x01UL << LCD_PAL64_I0_Pos)                              /*!< LCD PAL64: I0 Mask                  */
#define LCD_PAL64_R14_0_Pos                                   16                                                        /*!< LCD PAL64: R14_0 Position           */
#define LCD_PAL64_R14_0_Msk                                   (0x1fUL << LCD_PAL64_R14_0_Pos)                           /*!< LCD PAL64: R14_0 Mask               */
#define LCD_PAL64_G14_0_Pos                                   21                                                        /*!< LCD PAL64: G14_0 Position           */
#define LCD_PAL64_G14_0_Msk                                   (0x1fUL << LCD_PAL64_G14_0_Pos)                           /*!< LCD PAL64: G14_0 Mask               */
#define LCD_PAL64_B14_0_Pos                                   26                                                        /*!< LCD PAL64: B14_0 Position           */
#define LCD_PAL64_B14_0_Msk                                   (0x1fUL << LCD_PAL64_B14_0_Pos)                           /*!< LCD PAL64: B14_0 Mask               */
#define LCD_PAL64_I1_Pos                                      31                                                        /*!< LCD PAL64: I1 Position              */
#define LCD_PAL64_I1_Msk                                      (0x01UL << LCD_PAL64_I1_Pos)                              /*!< LCD PAL64: I1 Mask                  */

// ----------------------------------------  LCD_PAL65  -------------------------------------------
#define LCD_PAL65_R04_0_Pos                                   0                                                         /*!< LCD PAL65: R04_0 Position           */
#define LCD_PAL65_R04_0_Msk                                   (0x1fUL << LCD_PAL65_R04_0_Pos)                           /*!< LCD PAL65: R04_0 Mask               */
#define LCD_PAL65_G04_0_Pos                                   5                                                         /*!< LCD PAL65: G04_0 Position           */
#define LCD_PAL65_G04_0_Msk                                   (0x1fUL << LCD_PAL65_G04_0_Pos)                           /*!< LCD PAL65: G04_0 Mask               */
#define LCD_PAL65_B04_0_Pos                                   10                                                        /*!< LCD PAL65: B04_0 Position           */
#define LCD_PAL65_B04_0_Msk                                   (0x1fUL << LCD_PAL65_B04_0_Pos)                           /*!< LCD PAL65: B04_0 Mask               */
#define LCD_PAL65_I0_Pos                                      15                                                        /*!< LCD PAL65: I0 Position              */
#define LCD_PAL65_I0_Msk                                      (0x01UL << LCD_PAL65_I0_Pos)                              /*!< LCD PAL65: I0 Mask                  */
#define LCD_PAL65_R14_0_Pos                                   16                                                        /*!< LCD PAL65: R14_0 Position           */
#define LCD_PAL65_R14_0_Msk                                   (0x1fUL << LCD_PAL65_R14_0_Pos)                           /*!< LCD PAL65: R14_0 Mask               */
#define LCD_PAL65_G14_0_Pos                                   21                                                        /*!< LCD PAL65: G14_0 Position           */
#define LCD_PAL65_G14_0_Msk                                   (0x1fUL << LCD_PAL65_G14_0_Pos)                           /*!< LCD PAL65: G14_0 Mask               */
#define LCD_PAL65_B14_0_Pos                                   26                                                        /*!< LCD PAL65: B14_0 Position           */
#define LCD_PAL65_B14_0_Msk                                   (0x1fUL << LCD_PAL65_B14_0_Pos)                           /*!< LCD PAL65: B14_0 Mask               */
#define LCD_PAL65_I1_Pos                                      31                                                        /*!< LCD PAL65: I1 Position              */
#define LCD_PAL65_I1_Msk                                      (0x01UL << LCD_PAL65_I1_Pos)                              /*!< LCD PAL65: I1 Mask                  */

// ----------------------------------------  LCD_PAL66  -------------------------------------------
#define LCD_PAL66_R04_0_Pos                                   0                                                         /*!< LCD PAL66: R04_0 Position           */
#define LCD_PAL66_R04_0_Msk                                   (0x1fUL << LCD_PAL66_R04_0_Pos)                           /*!< LCD PAL66: R04_0 Mask               */
#define LCD_PAL66_G04_0_Pos                                   5                                                         /*!< LCD PAL66: G04_0 Position           */
#define LCD_PAL66_G04_0_Msk                                   (0x1fUL << LCD_PAL66_G04_0_Pos)                           /*!< LCD PAL66: G04_0 Mask               */
#define LCD_PAL66_B04_0_Pos                                   10                                                        /*!< LCD PAL66: B04_0 Position           */
#define LCD_PAL66_B04_0_Msk                                   (0x1fUL << LCD_PAL66_B04_0_Pos)                           /*!< LCD PAL66: B04_0 Mask               */
#define LCD_PAL66_I0_Pos                                      15                                                        /*!< LCD PAL66: I0 Position              */
#define LCD_PAL66_I0_Msk                                      (0x01UL << LCD_PAL66_I0_Pos)                              /*!< LCD PAL66: I0 Mask                  */
#define LCD_PAL66_R14_0_Pos                                   16                                                        /*!< LCD PAL66: R14_0 Position           */
#define LCD_PAL66_R14_0_Msk                                   (0x1fUL << LCD_PAL66_R14_0_Pos)                           /*!< LCD PAL66: R14_0 Mask               */
#define LCD_PAL66_G14_0_Pos                                   21                                                        /*!< LCD PAL66: G14_0 Position           */
#define LCD_PAL66_G14_0_Msk                                   (0x1fUL << LCD_PAL66_G14_0_Pos)                           /*!< LCD PAL66: G14_0 Mask               */
#define LCD_PAL66_B14_0_Pos                                   26                                                        /*!< LCD PAL66: B14_0 Position           */
#define LCD_PAL66_B14_0_Msk                                   (0x1fUL << LCD_PAL66_B14_0_Pos)                           /*!< LCD PAL66: B14_0 Mask               */
#define LCD_PAL66_I1_Pos                                      31                                                        /*!< LCD PAL66: I1 Position              */
#define LCD_PAL66_I1_Msk                                      (0x01UL << LCD_PAL66_I1_Pos)                              /*!< LCD PAL66: I1 Mask                  */

// ----------------------------------------  LCD_PAL67  -------------------------------------------
#define LCD_PAL67_R04_0_Pos                                   0                                                         /*!< LCD PAL67: R04_0 Position           */
#define LCD_PAL67_R04_0_Msk                                   (0x1fUL << LCD_PAL67_R04_0_Pos)                           /*!< LCD PAL67: R04_0 Mask               */
#define LCD_PAL67_G04_0_Pos                                   5                                                         /*!< LCD PAL67: G04_0 Position           */
#define LCD_PAL67_G04_0_Msk                                   (0x1fUL << LCD_PAL67_G04_0_Pos)                           /*!< LCD PAL67: G04_0 Mask               */
#define LCD_PAL67_B04_0_Pos                                   10                                                        /*!< LCD PAL67: B04_0 Position           */
#define LCD_PAL67_B04_0_Msk                                   (0x1fUL << LCD_PAL67_B04_0_Pos)                           /*!< LCD PAL67: B04_0 Mask               */
#define LCD_PAL67_I0_Pos                                      15                                                        /*!< LCD PAL67: I0 Position              */
#define LCD_PAL67_I0_Msk                                      (0x01UL << LCD_PAL67_I0_Pos)                              /*!< LCD PAL67: I0 Mask                  */
#define LCD_PAL67_R14_0_Pos                                   16                                                        /*!< LCD PAL67: R14_0 Position           */
#define LCD_PAL67_R14_0_Msk                                   (0x1fUL << LCD_PAL67_R14_0_Pos)                           /*!< LCD PAL67: R14_0 Mask               */
#define LCD_PAL67_G14_0_Pos                                   21                                                        /*!< LCD PAL67: G14_0 Position           */
#define LCD_PAL67_G14_0_Msk                                   (0x1fUL << LCD_PAL67_G14_0_Pos)                           /*!< LCD PAL67: G14_0 Mask               */
#define LCD_PAL67_B14_0_Pos                                   26                                                        /*!< LCD PAL67: B14_0 Position           */
#define LCD_PAL67_B14_0_Msk                                   (0x1fUL << LCD_PAL67_B14_0_Pos)                           /*!< LCD PAL67: B14_0 Mask               */
#define LCD_PAL67_I1_Pos                                      31                                                        /*!< LCD PAL67: I1 Position              */
#define LCD_PAL67_I1_Msk                                      (0x01UL << LCD_PAL67_I1_Pos)                              /*!< LCD PAL67: I1 Mask                  */

// ----------------------------------------  LCD_PAL68  -------------------------------------------
#define LCD_PAL68_R04_0_Pos                                   0                                                         /*!< LCD PAL68: R04_0 Position           */
#define LCD_PAL68_R04_0_Msk                                   (0x1fUL << LCD_PAL68_R04_0_Pos)                           /*!< LCD PAL68: R04_0 Mask               */
#define LCD_PAL68_G04_0_Pos                                   5                                                         /*!< LCD PAL68: G04_0 Position           */
#define LCD_PAL68_G04_0_Msk                                   (0x1fUL << LCD_PAL68_G04_0_Pos)                           /*!< LCD PAL68: G04_0 Mask               */
#define LCD_PAL68_B04_0_Pos                                   10                                                        /*!< LCD PAL68: B04_0 Position           */
#define LCD_PAL68_B04_0_Msk                                   (0x1fUL << LCD_PAL68_B04_0_Pos)                           /*!< LCD PAL68: B04_0 Mask               */
#define LCD_PAL68_I0_Pos                                      15                                                        /*!< LCD PAL68: I0 Position              */
#define LCD_PAL68_I0_Msk                                      (0x01UL << LCD_PAL68_I0_Pos)                              /*!< LCD PAL68: I0 Mask                  */
#define LCD_PAL68_R14_0_Pos                                   16                                                        /*!< LCD PAL68: R14_0 Position           */
#define LCD_PAL68_R14_0_Msk                                   (0x1fUL << LCD_PAL68_R14_0_Pos)                           /*!< LCD PAL68: R14_0 Mask               */
#define LCD_PAL68_G14_0_Pos                                   21                                                        /*!< LCD PAL68: G14_0 Position           */
#define LCD_PAL68_G14_0_Msk                                   (0x1fUL << LCD_PAL68_G14_0_Pos)                           /*!< LCD PAL68: G14_0 Mask               */
#define LCD_PAL68_B14_0_Pos                                   26                                                        /*!< LCD PAL68: B14_0 Position           */
#define LCD_PAL68_B14_0_Msk                                   (0x1fUL << LCD_PAL68_B14_0_Pos)                           /*!< LCD PAL68: B14_0 Mask               */
#define LCD_PAL68_I1_Pos                                      31                                                        /*!< LCD PAL68: I1 Position              */
#define LCD_PAL68_I1_Msk                                      (0x01UL << LCD_PAL68_I1_Pos)                              /*!< LCD PAL68: I1 Mask                  */

// ----------------------------------------  LCD_PAL69  -------------------------------------------
#define LCD_PAL69_R04_0_Pos                                   0                                                         /*!< LCD PAL69: R04_0 Position           */
#define LCD_PAL69_R04_0_Msk                                   (0x1fUL << LCD_PAL69_R04_0_Pos)                           /*!< LCD PAL69: R04_0 Mask               */
#define LCD_PAL69_G04_0_Pos                                   5                                                         /*!< LCD PAL69: G04_0 Position           */
#define LCD_PAL69_G04_0_Msk                                   (0x1fUL << LCD_PAL69_G04_0_Pos)                           /*!< LCD PAL69: G04_0 Mask               */
#define LCD_PAL69_B04_0_Pos                                   10                                                        /*!< LCD PAL69: B04_0 Position           */
#define LCD_PAL69_B04_0_Msk                                   (0x1fUL << LCD_PAL69_B04_0_Pos)                           /*!< LCD PAL69: B04_0 Mask               */
#define LCD_PAL69_I0_Pos                                      15                                                        /*!< LCD PAL69: I0 Position              */
#define LCD_PAL69_I0_Msk                                      (0x01UL << LCD_PAL69_I0_Pos)                              /*!< LCD PAL69: I0 Mask                  */
#define LCD_PAL69_R14_0_Pos                                   16                                                        /*!< LCD PAL69: R14_0 Position           */
#define LCD_PAL69_R14_0_Msk                                   (0x1fUL << LCD_PAL69_R14_0_Pos)                           /*!< LCD PAL69: R14_0 Mask               */
#define LCD_PAL69_G14_0_Pos                                   21                                                        /*!< LCD PAL69: G14_0 Position           */
#define LCD_PAL69_G14_0_Msk                                   (0x1fUL << LCD_PAL69_G14_0_Pos)                           /*!< LCD PAL69: G14_0 Mask               */
#define LCD_PAL69_B14_0_Pos                                   26                                                        /*!< LCD PAL69: B14_0 Position           */
#define LCD_PAL69_B14_0_Msk                                   (0x1fUL << LCD_PAL69_B14_0_Pos)                           /*!< LCD PAL69: B14_0 Mask               */
#define LCD_PAL69_I1_Pos                                      31                                                        /*!< LCD PAL69: I1 Position              */
#define LCD_PAL69_I1_Msk                                      (0x01UL << LCD_PAL69_I1_Pos)                              /*!< LCD PAL69: I1 Mask                  */

// ----------------------------------------  LCD_PAL70  -------------------------------------------
#define LCD_PAL70_R04_0_Pos                                   0                                                         /*!< LCD PAL70: R04_0 Position           */
#define LCD_PAL70_R04_0_Msk                                   (0x1fUL << LCD_PAL70_R04_0_Pos)                           /*!< LCD PAL70: R04_0 Mask               */
#define LCD_PAL70_G04_0_Pos                                   5                                                         /*!< LCD PAL70: G04_0 Position           */
#define LCD_PAL70_G04_0_Msk                                   (0x1fUL << LCD_PAL70_G04_0_Pos)                           /*!< LCD PAL70: G04_0 Mask               */
#define LCD_PAL70_B04_0_Pos                                   10                                                        /*!< LCD PAL70: B04_0 Position           */
#define LCD_PAL70_B04_0_Msk                                   (0x1fUL << LCD_PAL70_B04_0_Pos)                           /*!< LCD PAL70: B04_0 Mask               */
#define LCD_PAL70_I0_Pos                                      15                                                        /*!< LCD PAL70: I0 Position              */
#define LCD_PAL70_I0_Msk                                      (0x01UL << LCD_PAL70_I0_Pos)                              /*!< LCD PAL70: I0 Mask                  */
#define LCD_PAL70_R14_0_Pos                                   16                                                        /*!< LCD PAL70: R14_0 Position           */
#define LCD_PAL70_R14_0_Msk                                   (0x1fUL << LCD_PAL70_R14_0_Pos)                           /*!< LCD PAL70: R14_0 Mask               */
#define LCD_PAL70_G14_0_Pos                                   21                                                        /*!< LCD PAL70: G14_0 Position           */
#define LCD_PAL70_G14_0_Msk                                   (0x1fUL << LCD_PAL70_G14_0_Pos)                           /*!< LCD PAL70: G14_0 Mask               */
#define LCD_PAL70_B14_0_Pos                                   26                                                        /*!< LCD PAL70: B14_0 Position           */
#define LCD_PAL70_B14_0_Msk                                   (0x1fUL << LCD_PAL70_B14_0_Pos)                           /*!< LCD PAL70: B14_0 Mask               */
#define LCD_PAL70_I1_Pos                                      31                                                        /*!< LCD PAL70: I1 Position              */
#define LCD_PAL70_I1_Msk                                      (0x01UL << LCD_PAL70_I1_Pos)                              /*!< LCD PAL70: I1 Mask                  */

// ----------------------------------------  LCD_PAL71  -------------------------------------------
#define LCD_PAL71_R04_0_Pos                                   0                                                         /*!< LCD PAL71: R04_0 Position           */
#define LCD_PAL71_R04_0_Msk                                   (0x1fUL << LCD_PAL71_R04_0_Pos)                           /*!< LCD PAL71: R04_0 Mask               */
#define LCD_PAL71_G04_0_Pos                                   5                                                         /*!< LCD PAL71: G04_0 Position           */
#define LCD_PAL71_G04_0_Msk                                   (0x1fUL << LCD_PAL71_G04_0_Pos)                           /*!< LCD PAL71: G04_0 Mask               */
#define LCD_PAL71_B04_0_Pos                                   10                                                        /*!< LCD PAL71: B04_0 Position           */
#define LCD_PAL71_B04_0_Msk                                   (0x1fUL << LCD_PAL71_B04_0_Pos)                           /*!< LCD PAL71: B04_0 Mask               */
#define LCD_PAL71_I0_Pos                                      15                                                        /*!< LCD PAL71: I0 Position              */
#define LCD_PAL71_I0_Msk                                      (0x01UL << LCD_PAL71_I0_Pos)                              /*!< LCD PAL71: I0 Mask                  */
#define LCD_PAL71_R14_0_Pos                                   16                                                        /*!< LCD PAL71: R14_0 Position           */
#define LCD_PAL71_R14_0_Msk                                   (0x1fUL << LCD_PAL71_R14_0_Pos)                           /*!< LCD PAL71: R14_0 Mask               */
#define LCD_PAL71_G14_0_Pos                                   21                                                        /*!< LCD PAL71: G14_0 Position           */
#define LCD_PAL71_G14_0_Msk                                   (0x1fUL << LCD_PAL71_G14_0_Pos)                           /*!< LCD PAL71: G14_0 Mask               */
#define LCD_PAL71_B14_0_Pos                                   26                                                        /*!< LCD PAL71: B14_0 Position           */
#define LCD_PAL71_B14_0_Msk                                   (0x1fUL << LCD_PAL71_B14_0_Pos)                           /*!< LCD PAL71: B14_0 Mask               */
#define LCD_PAL71_I1_Pos                                      31                                                        /*!< LCD PAL71: I1 Position              */
#define LCD_PAL71_I1_Msk                                      (0x01UL << LCD_PAL71_I1_Pos)                              /*!< LCD PAL71: I1 Mask                  */

// ----------------------------------------  LCD_PAL72  -------------------------------------------
#define LCD_PAL72_R04_0_Pos                                   0                                                         /*!< LCD PAL72: R04_0 Position           */
#define LCD_PAL72_R04_0_Msk                                   (0x1fUL << LCD_PAL72_R04_0_Pos)                           /*!< LCD PAL72: R04_0 Mask               */
#define LCD_PAL72_G04_0_Pos                                   5                                                         /*!< LCD PAL72: G04_0 Position           */
#define LCD_PAL72_G04_0_Msk                                   (0x1fUL << LCD_PAL72_G04_0_Pos)                           /*!< LCD PAL72: G04_0 Mask               */
#define LCD_PAL72_B04_0_Pos                                   10                                                        /*!< LCD PAL72: B04_0 Position           */
#define LCD_PAL72_B04_0_Msk                                   (0x1fUL << LCD_PAL72_B04_0_Pos)                           /*!< LCD PAL72: B04_0 Mask               */
#define LCD_PAL72_I0_Pos                                      15                                                        /*!< LCD PAL72: I0 Position              */
#define LCD_PAL72_I0_Msk                                      (0x01UL << LCD_PAL72_I0_Pos)                              /*!< LCD PAL72: I0 Mask                  */
#define LCD_PAL72_R14_0_Pos                                   16                                                        /*!< LCD PAL72: R14_0 Position           */
#define LCD_PAL72_R14_0_Msk                                   (0x1fUL << LCD_PAL72_R14_0_Pos)                           /*!< LCD PAL72: R14_0 Mask               */
#define LCD_PAL72_G14_0_Pos                                   21                                                        /*!< LCD PAL72: G14_0 Position           */
#define LCD_PAL72_G14_0_Msk                                   (0x1fUL << LCD_PAL72_G14_0_Pos)                           /*!< LCD PAL72: G14_0 Mask               */
#define LCD_PAL72_B14_0_Pos                                   26                                                        /*!< LCD PAL72: B14_0 Position           */
#define LCD_PAL72_B14_0_Msk                                   (0x1fUL << LCD_PAL72_B14_0_Pos)                           /*!< LCD PAL72: B14_0 Mask               */
#define LCD_PAL72_I1_Pos                                      31                                                        /*!< LCD PAL72: I1 Position              */
#define LCD_PAL72_I1_Msk                                      (0x01UL << LCD_PAL72_I1_Pos)                              /*!< LCD PAL72: I1 Mask                  */

// ----------------------------------------  LCD_PAL73  -------------------------------------------
#define LCD_PAL73_R04_0_Pos                                   0                                                         /*!< LCD PAL73: R04_0 Position           */
#define LCD_PAL73_R04_0_Msk                                   (0x1fUL << LCD_PAL73_R04_0_Pos)                           /*!< LCD PAL73: R04_0 Mask               */
#define LCD_PAL73_G04_0_Pos                                   5                                                         /*!< LCD PAL73: G04_0 Position           */
#define LCD_PAL73_G04_0_Msk                                   (0x1fUL << LCD_PAL73_G04_0_Pos)                           /*!< LCD PAL73: G04_0 Mask               */
#define LCD_PAL73_B04_0_Pos                                   10                                                        /*!< LCD PAL73: B04_0 Position           */
#define LCD_PAL73_B04_0_Msk                                   (0x1fUL << LCD_PAL73_B04_0_Pos)                           /*!< LCD PAL73: B04_0 Mask               */
#define LCD_PAL73_I0_Pos                                      15                                                        /*!< LCD PAL73: I0 Position              */
#define LCD_PAL73_I0_Msk                                      (0x01UL << LCD_PAL73_I0_Pos)                              /*!< LCD PAL73: I0 Mask                  */
#define LCD_PAL73_R14_0_Pos                                   16                                                        /*!< LCD PAL73: R14_0 Position           */
#define LCD_PAL73_R14_0_Msk                                   (0x1fUL << LCD_PAL73_R14_0_Pos)                           /*!< LCD PAL73: R14_0 Mask               */
#define LCD_PAL73_G14_0_Pos                                   21                                                        /*!< LCD PAL73: G14_0 Position           */
#define LCD_PAL73_G14_0_Msk                                   (0x1fUL << LCD_PAL73_G14_0_Pos)                           /*!< LCD PAL73: G14_0 Mask               */
#define LCD_PAL73_B14_0_Pos                                   26                                                        /*!< LCD PAL73: B14_0 Position           */
#define LCD_PAL73_B14_0_Msk                                   (0x1fUL << LCD_PAL73_B14_0_Pos)                           /*!< LCD PAL73: B14_0 Mask               */
#define LCD_PAL73_I1_Pos                                      31                                                        /*!< LCD PAL73: I1 Position              */
#define LCD_PAL73_I1_Msk                                      (0x01UL << LCD_PAL73_I1_Pos)                              /*!< LCD PAL73: I1 Mask                  */

// ----------------------------------------  LCD_PAL74  -------------------------------------------
#define LCD_PAL74_R04_0_Pos                                   0                                                         /*!< LCD PAL74: R04_0 Position           */
#define LCD_PAL74_R04_0_Msk                                   (0x1fUL << LCD_PAL74_R04_0_Pos)                           /*!< LCD PAL74: R04_0 Mask               */
#define LCD_PAL74_G04_0_Pos                                   5                                                         /*!< LCD PAL74: G04_0 Position           */
#define LCD_PAL74_G04_0_Msk                                   (0x1fUL << LCD_PAL74_G04_0_Pos)                           /*!< LCD PAL74: G04_0 Mask               */
#define LCD_PAL74_B04_0_Pos                                   10                                                        /*!< LCD PAL74: B04_0 Position           */
#define LCD_PAL74_B04_0_Msk                                   (0x1fUL << LCD_PAL74_B04_0_Pos)                           /*!< LCD PAL74: B04_0 Mask               */
#define LCD_PAL74_I0_Pos                                      15                                                        /*!< LCD PAL74: I0 Position              */
#define LCD_PAL74_I0_Msk                                      (0x01UL << LCD_PAL74_I0_Pos)                              /*!< LCD PAL74: I0 Mask                  */
#define LCD_PAL74_R14_0_Pos                                   16                                                        /*!< LCD PAL74: R14_0 Position           */
#define LCD_PAL74_R14_0_Msk                                   (0x1fUL << LCD_PAL74_R14_0_Pos)                           /*!< LCD PAL74: R14_0 Mask               */
#define LCD_PAL74_G14_0_Pos                                   21                                                        /*!< LCD PAL74: G14_0 Position           */
#define LCD_PAL74_G14_0_Msk                                   (0x1fUL << LCD_PAL74_G14_0_Pos)                           /*!< LCD PAL74: G14_0 Mask               */
#define LCD_PAL74_B14_0_Pos                                   26                                                        /*!< LCD PAL74: B14_0 Position           */
#define LCD_PAL74_B14_0_Msk                                   (0x1fUL << LCD_PAL74_B14_0_Pos)                           /*!< LCD PAL74: B14_0 Mask               */
#define LCD_PAL74_I1_Pos                                      31                                                        /*!< LCD PAL74: I1 Position              */
#define LCD_PAL74_I1_Msk                                      (0x01UL << LCD_PAL74_I1_Pos)                              /*!< LCD PAL74: I1 Mask                  */

// ----------------------------------------  LCD_PAL75  -------------------------------------------
#define LCD_PAL75_R04_0_Pos                                   0                                                         /*!< LCD PAL75: R04_0 Position           */
#define LCD_PAL75_R04_0_Msk                                   (0x1fUL << LCD_PAL75_R04_0_Pos)                           /*!< LCD PAL75: R04_0 Mask               */
#define LCD_PAL75_G04_0_Pos                                   5                                                         /*!< LCD PAL75: G04_0 Position           */
#define LCD_PAL75_G04_0_Msk                                   (0x1fUL << LCD_PAL75_G04_0_Pos)                           /*!< LCD PAL75: G04_0 Mask               */
#define LCD_PAL75_B04_0_Pos                                   10                                                        /*!< LCD PAL75: B04_0 Position           */
#define LCD_PAL75_B04_0_Msk                                   (0x1fUL << LCD_PAL75_B04_0_Pos)                           /*!< LCD PAL75: B04_0 Mask               */
#define LCD_PAL75_I0_Pos                                      15                                                        /*!< LCD PAL75: I0 Position              */
#define LCD_PAL75_I0_Msk                                      (0x01UL << LCD_PAL75_I0_Pos)                              /*!< LCD PAL75: I0 Mask                  */
#define LCD_PAL75_R14_0_Pos                                   16                                                        /*!< LCD PAL75: R14_0 Position           */
#define LCD_PAL75_R14_0_Msk                                   (0x1fUL << LCD_PAL75_R14_0_Pos)                           /*!< LCD PAL75: R14_0 Mask               */
#define LCD_PAL75_G14_0_Pos                                   21                                                        /*!< LCD PAL75: G14_0 Position           */
#define LCD_PAL75_G14_0_Msk                                   (0x1fUL << LCD_PAL75_G14_0_Pos)                           /*!< LCD PAL75: G14_0 Mask               */
#define LCD_PAL75_B14_0_Pos                                   26                                                        /*!< LCD PAL75: B14_0 Position           */
#define LCD_PAL75_B14_0_Msk                                   (0x1fUL << LCD_PAL75_B14_0_Pos)                           /*!< LCD PAL75: B14_0 Mask               */
#define LCD_PAL75_I1_Pos                                      31                                                        /*!< LCD PAL75: I1 Position              */
#define LCD_PAL75_I1_Msk                                      (0x01UL << LCD_PAL75_I1_Pos)                              /*!< LCD PAL75: I1 Mask                  */

// ----------------------------------------  LCD_PAL76  -------------------------------------------
#define LCD_PAL76_R04_0_Pos                                   0                                                         /*!< LCD PAL76: R04_0 Position           */
#define LCD_PAL76_R04_0_Msk                                   (0x1fUL << LCD_PAL76_R04_0_Pos)                           /*!< LCD PAL76: R04_0 Mask               */
#define LCD_PAL76_G04_0_Pos                                   5                                                         /*!< LCD PAL76: G04_0 Position           */
#define LCD_PAL76_G04_0_Msk                                   (0x1fUL << LCD_PAL76_G04_0_Pos)                           /*!< LCD PAL76: G04_0 Mask               */
#define LCD_PAL76_B04_0_Pos                                   10                                                        /*!< LCD PAL76: B04_0 Position           */
#define LCD_PAL76_B04_0_Msk                                   (0x1fUL << LCD_PAL76_B04_0_Pos)                           /*!< LCD PAL76: B04_0 Mask               */
#define LCD_PAL76_I0_Pos                                      15                                                        /*!< LCD PAL76: I0 Position              */
#define LCD_PAL76_I0_Msk                                      (0x01UL << LCD_PAL76_I0_Pos)                              /*!< LCD PAL76: I0 Mask                  */
#define LCD_PAL76_R14_0_Pos                                   16                                                        /*!< LCD PAL76: R14_0 Position           */
#define LCD_PAL76_R14_0_Msk                                   (0x1fUL << LCD_PAL76_R14_0_Pos)                           /*!< LCD PAL76: R14_0 Mask               */
#define LCD_PAL76_G14_0_Pos                                   21                                                        /*!< LCD PAL76: G14_0 Position           */
#define LCD_PAL76_G14_0_Msk                                   (0x1fUL << LCD_PAL76_G14_0_Pos)                           /*!< LCD PAL76: G14_0 Mask               */
#define LCD_PAL76_B14_0_Pos                                   26                                                        /*!< LCD PAL76: B14_0 Position           */
#define LCD_PAL76_B14_0_Msk                                   (0x1fUL << LCD_PAL76_B14_0_Pos)                           /*!< LCD PAL76: B14_0 Mask               */
#define LCD_PAL76_I1_Pos                                      31                                                        /*!< LCD PAL76: I1 Position              */
#define LCD_PAL76_I1_Msk                                      (0x01UL << LCD_PAL76_I1_Pos)                              /*!< LCD PAL76: I1 Mask                  */

// ----------------------------------------  LCD_PAL77  -------------------------------------------
#define LCD_PAL77_R04_0_Pos                                   0                                                         /*!< LCD PAL77: R04_0 Position           */
#define LCD_PAL77_R04_0_Msk                                   (0x1fUL << LCD_PAL77_R04_0_Pos)                           /*!< LCD PAL77: R04_0 Mask               */
#define LCD_PAL77_G04_0_Pos                                   5                                                         /*!< LCD PAL77: G04_0 Position           */
#define LCD_PAL77_G04_0_Msk                                   (0x1fUL << LCD_PAL77_G04_0_Pos)                           /*!< LCD PAL77: G04_0 Mask               */
#define LCD_PAL77_B04_0_Pos                                   10                                                        /*!< LCD PAL77: B04_0 Position           */
#define LCD_PAL77_B04_0_Msk                                   (0x1fUL << LCD_PAL77_B04_0_Pos)                           /*!< LCD PAL77: B04_0 Mask               */
#define LCD_PAL77_I0_Pos                                      15                                                        /*!< LCD PAL77: I0 Position              */
#define LCD_PAL77_I0_Msk                                      (0x01UL << LCD_PAL77_I0_Pos)                              /*!< LCD PAL77: I0 Mask                  */
#define LCD_PAL77_R14_0_Pos                                   16                                                        /*!< LCD PAL77: R14_0 Position           */
#define LCD_PAL77_R14_0_Msk                                   (0x1fUL << LCD_PAL77_R14_0_Pos)                           /*!< LCD PAL77: R14_0 Mask               */
#define LCD_PAL77_G14_0_Pos                                   21                                                        /*!< LCD PAL77: G14_0 Position           */
#define LCD_PAL77_G14_0_Msk                                   (0x1fUL << LCD_PAL77_G14_0_Pos)                           /*!< LCD PAL77: G14_0 Mask               */
#define LCD_PAL77_B14_0_Pos                                   26                                                        /*!< LCD PAL77: B14_0 Position           */
#define LCD_PAL77_B14_0_Msk                                   (0x1fUL << LCD_PAL77_B14_0_Pos)                           /*!< LCD PAL77: B14_0 Mask               */
#define LCD_PAL77_I1_Pos                                      31                                                        /*!< LCD PAL77: I1 Position              */
#define LCD_PAL77_I1_Msk                                      (0x01UL << LCD_PAL77_I1_Pos)                              /*!< LCD PAL77: I1 Mask                  */

// ----------------------------------------  LCD_PAL78  -------------------------------------------
#define LCD_PAL78_R04_0_Pos                                   0                                                         /*!< LCD PAL78: R04_0 Position           */
#define LCD_PAL78_R04_0_Msk                                   (0x1fUL << LCD_PAL78_R04_0_Pos)                           /*!< LCD PAL78: R04_0 Mask               */
#define LCD_PAL78_G04_0_Pos                                   5                                                         /*!< LCD PAL78: G04_0 Position           */
#define LCD_PAL78_G04_0_Msk                                   (0x1fUL << LCD_PAL78_G04_0_Pos)                           /*!< LCD PAL78: G04_0 Mask               */
#define LCD_PAL78_B04_0_Pos                                   10                                                        /*!< LCD PAL78: B04_0 Position           */
#define LCD_PAL78_B04_0_Msk                                   (0x1fUL << LCD_PAL78_B04_0_Pos)                           /*!< LCD PAL78: B04_0 Mask               */
#define LCD_PAL78_I0_Pos                                      15                                                        /*!< LCD PAL78: I0 Position              */
#define LCD_PAL78_I0_Msk                                      (0x01UL << LCD_PAL78_I0_Pos)                              /*!< LCD PAL78: I0 Mask                  */
#define LCD_PAL78_R14_0_Pos                                   16                                                        /*!< LCD PAL78: R14_0 Position           */
#define LCD_PAL78_R14_0_Msk                                   (0x1fUL << LCD_PAL78_R14_0_Pos)                           /*!< LCD PAL78: R14_0 Mask               */
#define LCD_PAL78_G14_0_Pos                                   21                                                        /*!< LCD PAL78: G14_0 Position           */
#define LCD_PAL78_G14_0_Msk                                   (0x1fUL << LCD_PAL78_G14_0_Pos)                           /*!< LCD PAL78: G14_0 Mask               */
#define LCD_PAL78_B14_0_Pos                                   26                                                        /*!< LCD PAL78: B14_0 Position           */
#define LCD_PAL78_B14_0_Msk                                   (0x1fUL << LCD_PAL78_B14_0_Pos)                           /*!< LCD PAL78: B14_0 Mask               */
#define LCD_PAL78_I1_Pos                                      31                                                        /*!< LCD PAL78: I1 Position              */
#define LCD_PAL78_I1_Msk                                      (0x01UL << LCD_PAL78_I1_Pos)                              /*!< LCD PAL78: I1 Mask                  */

// ----------------------------------------  LCD_PAL79  -------------------------------------------
#define LCD_PAL79_R04_0_Pos                                   0                                                         /*!< LCD PAL79: R04_0 Position           */
#define LCD_PAL79_R04_0_Msk                                   (0x1fUL << LCD_PAL79_R04_0_Pos)                           /*!< LCD PAL79: R04_0 Mask               */
#define LCD_PAL79_G04_0_Pos                                   5                                                         /*!< LCD PAL79: G04_0 Position           */
#define LCD_PAL79_G04_0_Msk                                   (0x1fUL << LCD_PAL79_G04_0_Pos)                           /*!< LCD PAL79: G04_0 Mask               */
#define LCD_PAL79_B04_0_Pos                                   10                                                        /*!< LCD PAL79: B04_0 Position           */
#define LCD_PAL79_B04_0_Msk                                   (0x1fUL << LCD_PAL79_B04_0_Pos)                           /*!< LCD PAL79: B04_0 Mask               */
#define LCD_PAL79_I0_Pos                                      15                                                        /*!< LCD PAL79: I0 Position              */
#define LCD_PAL79_I0_Msk                                      (0x01UL << LCD_PAL79_I0_Pos)                              /*!< LCD PAL79: I0 Mask                  */
#define LCD_PAL79_R14_0_Pos                                   16                                                        /*!< LCD PAL79: R14_0 Position           */
#define LCD_PAL79_R14_0_Msk                                   (0x1fUL << LCD_PAL79_R14_0_Pos)                           /*!< LCD PAL79: R14_0 Mask               */
#define LCD_PAL79_G14_0_Pos                                   21                                                        /*!< LCD PAL79: G14_0 Position           */
#define LCD_PAL79_G14_0_Msk                                   (0x1fUL << LCD_PAL79_G14_0_Pos)                           /*!< LCD PAL79: G14_0 Mask               */
#define LCD_PAL79_B14_0_Pos                                   26                                                        /*!< LCD PAL79: B14_0 Position           */
#define LCD_PAL79_B14_0_Msk                                   (0x1fUL << LCD_PAL79_B14_0_Pos)                           /*!< LCD PAL79: B14_0 Mask               */
#define LCD_PAL79_I1_Pos                                      31                                                        /*!< LCD PAL79: I1 Position              */
#define LCD_PAL79_I1_Msk                                      (0x01UL << LCD_PAL79_I1_Pos)                              /*!< LCD PAL79: I1 Mask                  */

// ----------------------------------------  LCD_PAL80  -------------------------------------------
#define LCD_PAL80_R04_0_Pos                                   0                                                         /*!< LCD PAL80: R04_0 Position           */
#define LCD_PAL80_R04_0_Msk                                   (0x1fUL << LCD_PAL80_R04_0_Pos)                           /*!< LCD PAL80: R04_0 Mask               */
#define LCD_PAL80_G04_0_Pos                                   5                                                         /*!< LCD PAL80: G04_0 Position           */
#define LCD_PAL80_G04_0_Msk                                   (0x1fUL << LCD_PAL80_G04_0_Pos)                           /*!< LCD PAL80: G04_0 Mask               */
#define LCD_PAL80_B04_0_Pos                                   10                                                        /*!< LCD PAL80: B04_0 Position           */
#define LCD_PAL80_B04_0_Msk                                   (0x1fUL << LCD_PAL80_B04_0_Pos)                           /*!< LCD PAL80: B04_0 Mask               */
#define LCD_PAL80_I0_Pos                                      15                                                        /*!< LCD PAL80: I0 Position              */
#define LCD_PAL80_I0_Msk                                      (0x01UL << LCD_PAL80_I0_Pos)                              /*!< LCD PAL80: I0 Mask                  */
#define LCD_PAL80_R14_0_Pos                                   16                                                        /*!< LCD PAL80: R14_0 Position           */
#define LCD_PAL80_R14_0_Msk                                   (0x1fUL << LCD_PAL80_R14_0_Pos)                           /*!< LCD PAL80: R14_0 Mask               */
#define LCD_PAL80_G14_0_Pos                                   21                                                        /*!< LCD PAL80: G14_0 Position           */
#define LCD_PAL80_G14_0_Msk                                   (0x1fUL << LCD_PAL80_G14_0_Pos)                           /*!< LCD PAL80: G14_0 Mask               */
#define LCD_PAL80_B14_0_Pos                                   26                                                        /*!< LCD PAL80: B14_0 Position           */
#define LCD_PAL80_B14_0_Msk                                   (0x1fUL << LCD_PAL80_B14_0_Pos)                           /*!< LCD PAL80: B14_0 Mask               */
#define LCD_PAL80_I1_Pos                                      31                                                        /*!< LCD PAL80: I1 Position              */
#define LCD_PAL80_I1_Msk                                      (0x01UL << LCD_PAL80_I1_Pos)                              /*!< LCD PAL80: I1 Mask                  */

// ----------------------------------------  LCD_PAL81  -------------------------------------------
#define LCD_PAL81_R04_0_Pos                                   0                                                         /*!< LCD PAL81: R04_0 Position           */
#define LCD_PAL81_R04_0_Msk                                   (0x1fUL << LCD_PAL81_R04_0_Pos)                           /*!< LCD PAL81: R04_0 Mask               */
#define LCD_PAL81_G04_0_Pos                                   5                                                         /*!< LCD PAL81: G04_0 Position           */
#define LCD_PAL81_G04_0_Msk                                   (0x1fUL << LCD_PAL81_G04_0_Pos)                           /*!< LCD PAL81: G04_0 Mask               */
#define LCD_PAL81_B04_0_Pos                                   10                                                        /*!< LCD PAL81: B04_0 Position           */
#define LCD_PAL81_B04_0_Msk                                   (0x1fUL << LCD_PAL81_B04_0_Pos)                           /*!< LCD PAL81: B04_0 Mask               */
#define LCD_PAL81_I0_Pos                                      15                                                        /*!< LCD PAL81: I0 Position              */
#define LCD_PAL81_I0_Msk                                      (0x01UL << LCD_PAL81_I0_Pos)                              /*!< LCD PAL81: I0 Mask                  */
#define LCD_PAL81_R14_0_Pos                                   16                                                        /*!< LCD PAL81: R14_0 Position           */
#define LCD_PAL81_R14_0_Msk                                   (0x1fUL << LCD_PAL81_R14_0_Pos)                           /*!< LCD PAL81: R14_0 Mask               */
#define LCD_PAL81_G14_0_Pos                                   21                                                        /*!< LCD PAL81: G14_0 Position           */
#define LCD_PAL81_G14_0_Msk                                   (0x1fUL << LCD_PAL81_G14_0_Pos)                           /*!< LCD PAL81: G14_0 Mask               */
#define LCD_PAL81_B14_0_Pos                                   26                                                        /*!< LCD PAL81: B14_0 Position           */
#define LCD_PAL81_B14_0_Msk                                   (0x1fUL << LCD_PAL81_B14_0_Pos)                           /*!< LCD PAL81: B14_0 Mask               */
#define LCD_PAL81_I1_Pos                                      31                                                        /*!< LCD PAL81: I1 Position              */
#define LCD_PAL81_I1_Msk                                      (0x01UL << LCD_PAL81_I1_Pos)                              /*!< LCD PAL81: I1 Mask                  */

// ----------------------------------------  LCD_PAL82  -------------------------------------------
#define LCD_PAL82_R04_0_Pos                                   0                                                         /*!< LCD PAL82: R04_0 Position           */
#define LCD_PAL82_R04_0_Msk                                   (0x1fUL << LCD_PAL82_R04_0_Pos)                           /*!< LCD PAL82: R04_0 Mask               */
#define LCD_PAL82_G04_0_Pos                                   5                                                         /*!< LCD PAL82: G04_0 Position           */
#define LCD_PAL82_G04_0_Msk                                   (0x1fUL << LCD_PAL82_G04_0_Pos)                           /*!< LCD PAL82: G04_0 Mask               */
#define LCD_PAL82_B04_0_Pos                                   10                                                        /*!< LCD PAL82: B04_0 Position           */
#define LCD_PAL82_B04_0_Msk                                   (0x1fUL << LCD_PAL82_B04_0_Pos)                           /*!< LCD PAL82: B04_0 Mask               */
#define LCD_PAL82_I0_Pos                                      15                                                        /*!< LCD PAL82: I0 Position              */
#define LCD_PAL82_I0_Msk                                      (0x01UL << LCD_PAL82_I0_Pos)                              /*!< LCD PAL82: I0 Mask                  */
#define LCD_PAL82_R14_0_Pos                                   16                                                        /*!< LCD PAL82: R14_0 Position           */
#define LCD_PAL82_R14_0_Msk                                   (0x1fUL << LCD_PAL82_R14_0_Pos)                           /*!< LCD PAL82: R14_0 Mask               */
#define LCD_PAL82_G14_0_Pos                                   21                                                        /*!< LCD PAL82: G14_0 Position           */
#define LCD_PAL82_G14_0_Msk                                   (0x1fUL << LCD_PAL82_G14_0_Pos)                           /*!< LCD PAL82: G14_0 Mask               */
#define LCD_PAL82_B14_0_Pos                                   26                                                        /*!< LCD PAL82: B14_0 Position           */
#define LCD_PAL82_B14_0_Msk                                   (0x1fUL << LCD_PAL82_B14_0_Pos)                           /*!< LCD PAL82: B14_0 Mask               */
#define LCD_PAL82_I1_Pos                                      31                                                        /*!< LCD PAL82: I1 Position              */
#define LCD_PAL82_I1_Msk                                      (0x01UL << LCD_PAL82_I1_Pos)                              /*!< LCD PAL82: I1 Mask                  */

// ----------------------------------------  LCD_PAL83  -------------------------------------------
#define LCD_PAL83_R04_0_Pos                                   0                                                         /*!< LCD PAL83: R04_0 Position           */
#define LCD_PAL83_R04_0_Msk                                   (0x1fUL << LCD_PAL83_R04_0_Pos)                           /*!< LCD PAL83: R04_0 Mask               */
#define LCD_PAL83_G04_0_Pos                                   5                                                         /*!< LCD PAL83: G04_0 Position           */
#define LCD_PAL83_G04_0_Msk                                   (0x1fUL << LCD_PAL83_G04_0_Pos)                           /*!< LCD PAL83: G04_0 Mask               */
#define LCD_PAL83_B04_0_Pos                                   10                                                        /*!< LCD PAL83: B04_0 Position           */
#define LCD_PAL83_B04_0_Msk                                   (0x1fUL << LCD_PAL83_B04_0_Pos)                           /*!< LCD PAL83: B04_0 Mask               */
#define LCD_PAL83_I0_Pos                                      15                                                        /*!< LCD PAL83: I0 Position              */
#define LCD_PAL83_I0_Msk                                      (0x01UL << LCD_PAL83_I0_Pos)                              /*!< LCD PAL83: I0 Mask                  */
#define LCD_PAL83_R14_0_Pos                                   16                                                        /*!< LCD PAL83: R14_0 Position           */
#define LCD_PAL83_R14_0_Msk                                   (0x1fUL << LCD_PAL83_R14_0_Pos)                           /*!< LCD PAL83: R14_0 Mask               */
#define LCD_PAL83_G14_0_Pos                                   21                                                        /*!< LCD PAL83: G14_0 Position           */
#define LCD_PAL83_G14_0_Msk                                   (0x1fUL << LCD_PAL83_G14_0_Pos)                           /*!< LCD PAL83: G14_0 Mask               */
#define LCD_PAL83_B14_0_Pos                                   26                                                        /*!< LCD PAL83: B14_0 Position           */
#define LCD_PAL83_B14_0_Msk                                   (0x1fUL << LCD_PAL83_B14_0_Pos)                           /*!< LCD PAL83: B14_0 Mask               */
#define LCD_PAL83_I1_Pos                                      31                                                        /*!< LCD PAL83: I1 Position              */
#define LCD_PAL83_I1_Msk                                      (0x01UL << LCD_PAL83_I1_Pos)                              /*!< LCD PAL83: I1 Mask                  */

// ----------------------------------------  LCD_PAL84  -------------------------------------------
#define LCD_PAL84_R04_0_Pos                                   0                                                         /*!< LCD PAL84: R04_0 Position           */
#define LCD_PAL84_R04_0_Msk                                   (0x1fUL << LCD_PAL84_R04_0_Pos)                           /*!< LCD PAL84: R04_0 Mask               */
#define LCD_PAL84_G04_0_Pos                                   5                                                         /*!< LCD PAL84: G04_0 Position           */
#define LCD_PAL84_G04_0_Msk                                   (0x1fUL << LCD_PAL84_G04_0_Pos)                           /*!< LCD PAL84: G04_0 Mask               */
#define LCD_PAL84_B04_0_Pos                                   10                                                        /*!< LCD PAL84: B04_0 Position           */
#define LCD_PAL84_B04_0_Msk                                   (0x1fUL << LCD_PAL84_B04_0_Pos)                           /*!< LCD PAL84: B04_0 Mask               */
#define LCD_PAL84_I0_Pos                                      15                                                        /*!< LCD PAL84: I0 Position              */
#define LCD_PAL84_I0_Msk                                      (0x01UL << LCD_PAL84_I0_Pos)                              /*!< LCD PAL84: I0 Mask                  */
#define LCD_PAL84_R14_0_Pos                                   16                                                        /*!< LCD PAL84: R14_0 Position           */
#define LCD_PAL84_R14_0_Msk                                   (0x1fUL << LCD_PAL84_R14_0_Pos)                           /*!< LCD PAL84: R14_0 Mask               */
#define LCD_PAL84_G14_0_Pos                                   21                                                        /*!< LCD PAL84: G14_0 Position           */
#define LCD_PAL84_G14_0_Msk                                   (0x1fUL << LCD_PAL84_G14_0_Pos)                           /*!< LCD PAL84: G14_0 Mask               */
#define LCD_PAL84_B14_0_Pos                                   26                                                        /*!< LCD PAL84: B14_0 Position           */
#define LCD_PAL84_B14_0_Msk                                   (0x1fUL << LCD_PAL84_B14_0_Pos)                           /*!< LCD PAL84: B14_0 Mask               */
#define LCD_PAL84_I1_Pos                                      31                                                        /*!< LCD PAL84: I1 Position              */
#define LCD_PAL84_I1_Msk                                      (0x01UL << LCD_PAL84_I1_Pos)                              /*!< LCD PAL84: I1 Mask                  */

// ----------------------------------------  LCD_PAL85  -------------------------------------------
#define LCD_PAL85_R04_0_Pos                                   0                                                         /*!< LCD PAL85: R04_0 Position           */
#define LCD_PAL85_R04_0_Msk                                   (0x1fUL << LCD_PAL85_R04_0_Pos)                           /*!< LCD PAL85: R04_0 Mask               */
#define LCD_PAL85_G04_0_Pos                                   5                                                         /*!< LCD PAL85: G04_0 Position           */
#define LCD_PAL85_G04_0_Msk                                   (0x1fUL << LCD_PAL85_G04_0_Pos)                           /*!< LCD PAL85: G04_0 Mask               */
#define LCD_PAL85_B04_0_Pos                                   10                                                        /*!< LCD PAL85: B04_0 Position           */
#define LCD_PAL85_B04_0_Msk                                   (0x1fUL << LCD_PAL85_B04_0_Pos)                           /*!< LCD PAL85: B04_0 Mask               */
#define LCD_PAL85_I0_Pos                                      15                                                        /*!< LCD PAL85: I0 Position              */
#define LCD_PAL85_I0_Msk                                      (0x01UL << LCD_PAL85_I0_Pos)                              /*!< LCD PAL85: I0 Mask                  */
#define LCD_PAL85_R14_0_Pos                                   16                                                        /*!< LCD PAL85: R14_0 Position           */
#define LCD_PAL85_R14_0_Msk                                   (0x1fUL << LCD_PAL85_R14_0_Pos)                           /*!< LCD PAL85: R14_0 Mask               */
#define LCD_PAL85_G14_0_Pos                                   21                                                        /*!< LCD PAL85: G14_0 Position           */
#define LCD_PAL85_G14_0_Msk                                   (0x1fUL << LCD_PAL85_G14_0_Pos)                           /*!< LCD PAL85: G14_0 Mask               */
#define LCD_PAL85_B14_0_Pos                                   26                                                        /*!< LCD PAL85: B14_0 Position           */
#define LCD_PAL85_B14_0_Msk                                   (0x1fUL << LCD_PAL85_B14_0_Pos)                           /*!< LCD PAL85: B14_0 Mask               */
#define LCD_PAL85_I1_Pos                                      31                                                        /*!< LCD PAL85: I1 Position              */
#define LCD_PAL85_I1_Msk                                      (0x01UL << LCD_PAL85_I1_Pos)                              /*!< LCD PAL85: I1 Mask                  */

// ----------------------------------------  LCD_PAL86  -------------------------------------------
#define LCD_PAL86_R04_0_Pos                                   0                                                         /*!< LCD PAL86: R04_0 Position           */
#define LCD_PAL86_R04_0_Msk                                   (0x1fUL << LCD_PAL86_R04_0_Pos)                           /*!< LCD PAL86: R04_0 Mask               */
#define LCD_PAL86_G04_0_Pos                                   5                                                         /*!< LCD PAL86: G04_0 Position           */
#define LCD_PAL86_G04_0_Msk                                   (0x1fUL << LCD_PAL86_G04_0_Pos)                           /*!< LCD PAL86: G04_0 Mask               */
#define LCD_PAL86_B04_0_Pos                                   10                                                        /*!< LCD PAL86: B04_0 Position           */
#define LCD_PAL86_B04_0_Msk                                   (0x1fUL << LCD_PAL86_B04_0_Pos)                           /*!< LCD PAL86: B04_0 Mask               */
#define LCD_PAL86_I0_Pos                                      15                                                        /*!< LCD PAL86: I0 Position              */
#define LCD_PAL86_I0_Msk                                      (0x01UL << LCD_PAL86_I0_Pos)                              /*!< LCD PAL86: I0 Mask                  */
#define LCD_PAL86_R14_0_Pos                                   16                                                        /*!< LCD PAL86: R14_0 Position           */
#define LCD_PAL86_R14_0_Msk                                   (0x1fUL << LCD_PAL86_R14_0_Pos)                           /*!< LCD PAL86: R14_0 Mask               */
#define LCD_PAL86_G14_0_Pos                                   21                                                        /*!< LCD PAL86: G14_0 Position           */
#define LCD_PAL86_G14_0_Msk                                   (0x1fUL << LCD_PAL86_G14_0_Pos)                           /*!< LCD PAL86: G14_0 Mask               */
#define LCD_PAL86_B14_0_Pos                                   26                                                        /*!< LCD PAL86: B14_0 Position           */
#define LCD_PAL86_B14_0_Msk                                   (0x1fUL << LCD_PAL86_B14_0_Pos)                           /*!< LCD PAL86: B14_0 Mask               */
#define LCD_PAL86_I1_Pos                                      31                                                        /*!< LCD PAL86: I1 Position              */
#define LCD_PAL86_I1_Msk                                      (0x01UL << LCD_PAL86_I1_Pos)                              /*!< LCD PAL86: I1 Mask                  */

// ----------------------------------------  LCD_PAL87  -------------------------------------------
#define LCD_PAL87_R04_0_Pos                                   0                                                         /*!< LCD PAL87: R04_0 Position           */
#define LCD_PAL87_R04_0_Msk                                   (0x1fUL << LCD_PAL87_R04_0_Pos)                           /*!< LCD PAL87: R04_0 Mask               */
#define LCD_PAL87_G04_0_Pos                                   5                                                         /*!< LCD PAL87: G04_0 Position           */
#define LCD_PAL87_G04_0_Msk                                   (0x1fUL << LCD_PAL87_G04_0_Pos)                           /*!< LCD PAL87: G04_0 Mask               */
#define LCD_PAL87_B04_0_Pos                                   10                                                        /*!< LCD PAL87: B04_0 Position           */
#define LCD_PAL87_B04_0_Msk                                   (0x1fUL << LCD_PAL87_B04_0_Pos)                           /*!< LCD PAL87: B04_0 Mask               */
#define LCD_PAL87_I0_Pos                                      15                                                        /*!< LCD PAL87: I0 Position              */
#define LCD_PAL87_I0_Msk                                      (0x01UL << LCD_PAL87_I0_Pos)                              /*!< LCD PAL87: I0 Mask                  */
#define LCD_PAL87_R14_0_Pos                                   16                                                        /*!< LCD PAL87: R14_0 Position           */
#define LCD_PAL87_R14_0_Msk                                   (0x1fUL << LCD_PAL87_R14_0_Pos)                           /*!< LCD PAL87: R14_0 Mask               */
#define LCD_PAL87_G14_0_Pos                                   21                                                        /*!< LCD PAL87: G14_0 Position           */
#define LCD_PAL87_G14_0_Msk                                   (0x1fUL << LCD_PAL87_G14_0_Pos)                           /*!< LCD PAL87: G14_0 Mask               */
#define LCD_PAL87_B14_0_Pos                                   26                                                        /*!< LCD PAL87: B14_0 Position           */
#define LCD_PAL87_B14_0_Msk                                   (0x1fUL << LCD_PAL87_B14_0_Pos)                           /*!< LCD PAL87: B14_0 Mask               */
#define LCD_PAL87_I1_Pos                                      31                                                        /*!< LCD PAL87: I1 Position              */
#define LCD_PAL87_I1_Msk                                      (0x01UL << LCD_PAL87_I1_Pos)                              /*!< LCD PAL87: I1 Mask                  */

// ----------------------------------------  LCD_PAL88  -------------------------------------------
#define LCD_PAL88_R04_0_Pos                                   0                                                         /*!< LCD PAL88: R04_0 Position           */
#define LCD_PAL88_R04_0_Msk                                   (0x1fUL << LCD_PAL88_R04_0_Pos)                           /*!< LCD PAL88: R04_0 Mask               */
#define LCD_PAL88_G04_0_Pos                                   5                                                         /*!< LCD PAL88: G04_0 Position           */
#define LCD_PAL88_G04_0_Msk                                   (0x1fUL << LCD_PAL88_G04_0_Pos)                           /*!< LCD PAL88: G04_0 Mask               */
#define LCD_PAL88_B04_0_Pos                                   10                                                        /*!< LCD PAL88: B04_0 Position           */
#define LCD_PAL88_B04_0_Msk                                   (0x1fUL << LCD_PAL88_B04_0_Pos)                           /*!< LCD PAL88: B04_0 Mask               */
#define LCD_PAL88_I0_Pos                                      15                                                        /*!< LCD PAL88: I0 Position              */
#define LCD_PAL88_I0_Msk                                      (0x01UL << LCD_PAL88_I0_Pos)                              /*!< LCD PAL88: I0 Mask                  */
#define LCD_PAL88_R14_0_Pos                                   16                                                        /*!< LCD PAL88: R14_0 Position           */
#define LCD_PAL88_R14_0_Msk                                   (0x1fUL << LCD_PAL88_R14_0_Pos)                           /*!< LCD PAL88: R14_0 Mask               */
#define LCD_PAL88_G14_0_Pos                                   21                                                        /*!< LCD PAL88: G14_0 Position           */
#define LCD_PAL88_G14_0_Msk                                   (0x1fUL << LCD_PAL88_G14_0_Pos)                           /*!< LCD PAL88: G14_0 Mask               */
#define LCD_PAL88_B14_0_Pos                                   26                                                        /*!< LCD PAL88: B14_0 Position           */
#define LCD_PAL88_B14_0_Msk                                   (0x1fUL << LCD_PAL88_B14_0_Pos)                           /*!< LCD PAL88: B14_0 Mask               */
#define LCD_PAL88_I1_Pos                                      31                                                        /*!< LCD PAL88: I1 Position              */
#define LCD_PAL88_I1_Msk                                      (0x01UL << LCD_PAL88_I1_Pos)                              /*!< LCD PAL88: I1 Mask                  */

// ----------------------------------------  LCD_PAL89  -------------------------------------------
#define LCD_PAL89_R04_0_Pos                                   0                                                         /*!< LCD PAL89: R04_0 Position           */
#define LCD_PAL89_R04_0_Msk                                   (0x1fUL << LCD_PAL89_R04_0_Pos)                           /*!< LCD PAL89: R04_0 Mask               */
#define LCD_PAL89_G04_0_Pos                                   5                                                         /*!< LCD PAL89: G04_0 Position           */
#define LCD_PAL89_G04_0_Msk                                   (0x1fUL << LCD_PAL89_G04_0_Pos)                           /*!< LCD PAL89: G04_0 Mask               */
#define LCD_PAL89_B04_0_Pos                                   10                                                        /*!< LCD PAL89: B04_0 Position           */
#define LCD_PAL89_B04_0_Msk                                   (0x1fUL << LCD_PAL89_B04_0_Pos)                           /*!< LCD PAL89: B04_0 Mask               */
#define LCD_PAL89_I0_Pos                                      15                                                        /*!< LCD PAL89: I0 Position              */
#define LCD_PAL89_I0_Msk                                      (0x01UL << LCD_PAL89_I0_Pos)                              /*!< LCD PAL89: I0 Mask                  */
#define LCD_PAL89_R14_0_Pos                                   16                                                        /*!< LCD PAL89: R14_0 Position           */
#define LCD_PAL89_R14_0_Msk                                   (0x1fUL << LCD_PAL89_R14_0_Pos)                           /*!< LCD PAL89: R14_0 Mask               */
#define LCD_PAL89_G14_0_Pos                                   21                                                        /*!< LCD PAL89: G14_0 Position           */
#define LCD_PAL89_G14_0_Msk                                   (0x1fUL << LCD_PAL89_G14_0_Pos)                           /*!< LCD PAL89: G14_0 Mask               */
#define LCD_PAL89_B14_0_Pos                                   26                                                        /*!< LCD PAL89: B14_0 Position           */
#define LCD_PAL89_B14_0_Msk                                   (0x1fUL << LCD_PAL89_B14_0_Pos)                           /*!< LCD PAL89: B14_0 Mask               */
#define LCD_PAL89_I1_Pos                                      31                                                        /*!< LCD PAL89: I1 Position              */
#define LCD_PAL89_I1_Msk                                      (0x01UL << LCD_PAL89_I1_Pos)                              /*!< LCD PAL89: I1 Mask                  */

// ----------------------------------------  LCD_PAL90  -------------------------------------------
#define LCD_PAL90_R04_0_Pos                                   0                                                         /*!< LCD PAL90: R04_0 Position           */
#define LCD_PAL90_R04_0_Msk                                   (0x1fUL << LCD_PAL90_R04_0_Pos)                           /*!< LCD PAL90: R04_0 Mask               */
#define LCD_PAL90_G04_0_Pos                                   5                                                         /*!< LCD PAL90: G04_0 Position           */
#define LCD_PAL90_G04_0_Msk                                   (0x1fUL << LCD_PAL90_G04_0_Pos)                           /*!< LCD PAL90: G04_0 Mask               */
#define LCD_PAL90_B04_0_Pos                                   10                                                        /*!< LCD PAL90: B04_0 Position           */
#define LCD_PAL90_B04_0_Msk                                   (0x1fUL << LCD_PAL90_B04_0_Pos)                           /*!< LCD PAL90: B04_0 Mask               */
#define LCD_PAL90_I0_Pos                                      15                                                        /*!< LCD PAL90: I0 Position              */
#define LCD_PAL90_I0_Msk                                      (0x01UL << LCD_PAL90_I0_Pos)                              /*!< LCD PAL90: I0 Mask                  */
#define LCD_PAL90_R14_0_Pos                                   16                                                        /*!< LCD PAL90: R14_0 Position           */
#define LCD_PAL90_R14_0_Msk                                   (0x1fUL << LCD_PAL90_R14_0_Pos)                           /*!< LCD PAL90: R14_0 Mask               */
#define LCD_PAL90_G14_0_Pos                                   21                                                        /*!< LCD PAL90: G14_0 Position           */
#define LCD_PAL90_G14_0_Msk                                   (0x1fUL << LCD_PAL90_G14_0_Pos)                           /*!< LCD PAL90: G14_0 Mask               */
#define LCD_PAL90_B14_0_Pos                                   26                                                        /*!< LCD PAL90: B14_0 Position           */
#define LCD_PAL90_B14_0_Msk                                   (0x1fUL << LCD_PAL90_B14_0_Pos)                           /*!< LCD PAL90: B14_0 Mask               */
#define LCD_PAL90_I1_Pos                                      31                                                        /*!< LCD PAL90: I1 Position              */
#define LCD_PAL90_I1_Msk                                      (0x01UL << LCD_PAL90_I1_Pos)                              /*!< LCD PAL90: I1 Mask                  */

// ----------------------------------------  LCD_PAL91  -------------------------------------------
#define LCD_PAL91_R04_0_Pos                                   0                                                         /*!< LCD PAL91: R04_0 Position           */
#define LCD_PAL91_R04_0_Msk                                   (0x1fUL << LCD_PAL91_R04_0_Pos)                           /*!< LCD PAL91: R04_0 Mask               */
#define LCD_PAL91_G04_0_Pos                                   5                                                         /*!< LCD PAL91: G04_0 Position           */
#define LCD_PAL91_G04_0_Msk                                   (0x1fUL << LCD_PAL91_G04_0_Pos)                           /*!< LCD PAL91: G04_0 Mask               */
#define LCD_PAL91_B04_0_Pos                                   10                                                        /*!< LCD PAL91: B04_0 Position           */
#define LCD_PAL91_B04_0_Msk                                   (0x1fUL << LCD_PAL91_B04_0_Pos)                           /*!< LCD PAL91: B04_0 Mask               */
#define LCD_PAL91_I0_Pos                                      15                                                        /*!< LCD PAL91: I0 Position              */
#define LCD_PAL91_I0_Msk                                      (0x01UL << LCD_PAL91_I0_Pos)                              /*!< LCD PAL91: I0 Mask                  */
#define LCD_PAL91_R14_0_Pos                                   16                                                        /*!< LCD PAL91: R14_0 Position           */
#define LCD_PAL91_R14_0_Msk                                   (0x1fUL << LCD_PAL91_R14_0_Pos)                           /*!< LCD PAL91: R14_0 Mask               */
#define LCD_PAL91_G14_0_Pos                                   21                                                        /*!< LCD PAL91: G14_0 Position           */
#define LCD_PAL91_G14_0_Msk                                   (0x1fUL << LCD_PAL91_G14_0_Pos)                           /*!< LCD PAL91: G14_0 Mask               */
#define LCD_PAL91_B14_0_Pos                                   26                                                        /*!< LCD PAL91: B14_0 Position           */
#define LCD_PAL91_B14_0_Msk                                   (0x1fUL << LCD_PAL91_B14_0_Pos)                           /*!< LCD PAL91: B14_0 Mask               */
#define LCD_PAL91_I1_Pos                                      31                                                        /*!< LCD PAL91: I1 Position              */
#define LCD_PAL91_I1_Msk                                      (0x01UL << LCD_PAL91_I1_Pos)                              /*!< LCD PAL91: I1 Mask                  */

// ----------------------------------------  LCD_PAL92  -------------------------------------------
#define LCD_PAL92_R04_0_Pos                                   0                                                         /*!< LCD PAL92: R04_0 Position           */
#define LCD_PAL92_R04_0_Msk                                   (0x1fUL << LCD_PAL92_R04_0_Pos)                           /*!< LCD PAL92: R04_0 Mask               */
#define LCD_PAL92_G04_0_Pos                                   5                                                         /*!< LCD PAL92: G04_0 Position           */
#define LCD_PAL92_G04_0_Msk                                   (0x1fUL << LCD_PAL92_G04_0_Pos)                           /*!< LCD PAL92: G04_0 Mask               */
#define LCD_PAL92_B04_0_Pos                                   10                                                        /*!< LCD PAL92: B04_0 Position           */
#define LCD_PAL92_B04_0_Msk                                   (0x1fUL << LCD_PAL92_B04_0_Pos)                           /*!< LCD PAL92: B04_0 Mask               */
#define LCD_PAL92_I0_Pos                                      15                                                        /*!< LCD PAL92: I0 Position              */
#define LCD_PAL92_I0_Msk                                      (0x01UL << LCD_PAL92_I0_Pos)                              /*!< LCD PAL92: I0 Mask                  */
#define LCD_PAL92_R14_0_Pos                                   16                                                        /*!< LCD PAL92: R14_0 Position           */
#define LCD_PAL92_R14_0_Msk                                   (0x1fUL << LCD_PAL92_R14_0_Pos)                           /*!< LCD PAL92: R14_0 Mask               */
#define LCD_PAL92_G14_0_Pos                                   21                                                        /*!< LCD PAL92: G14_0 Position           */
#define LCD_PAL92_G14_0_Msk                                   (0x1fUL << LCD_PAL92_G14_0_Pos)                           /*!< LCD PAL92: G14_0 Mask               */
#define LCD_PAL92_B14_0_Pos                                   26                                                        /*!< LCD PAL92: B14_0 Position           */
#define LCD_PAL92_B14_0_Msk                                   (0x1fUL << LCD_PAL92_B14_0_Pos)                           /*!< LCD PAL92: B14_0 Mask               */
#define LCD_PAL92_I1_Pos                                      31                                                        /*!< LCD PAL92: I1 Position              */
#define LCD_PAL92_I1_Msk                                      (0x01UL << LCD_PAL92_I1_Pos)                              /*!< LCD PAL92: I1 Mask                  */

// ----------------------------------------  LCD_PAL93  -------------------------------------------
#define LCD_PAL93_R04_0_Pos                                   0                                                         /*!< LCD PAL93: R04_0 Position           */
#define LCD_PAL93_R04_0_Msk                                   (0x1fUL << LCD_PAL93_R04_0_Pos)                           /*!< LCD PAL93: R04_0 Mask               */
#define LCD_PAL93_G04_0_Pos                                   5                                                         /*!< LCD PAL93: G04_0 Position           */
#define LCD_PAL93_G04_0_Msk                                   (0x1fUL << LCD_PAL93_G04_0_Pos)                           /*!< LCD PAL93: G04_0 Mask               */
#define LCD_PAL93_B04_0_Pos                                   10                                                        /*!< LCD PAL93: B04_0 Position           */
#define LCD_PAL93_B04_0_Msk                                   (0x1fUL << LCD_PAL93_B04_0_Pos)                           /*!< LCD PAL93: B04_0 Mask               */
#define LCD_PAL93_I0_Pos                                      15                                                        /*!< LCD PAL93: I0 Position              */
#define LCD_PAL93_I0_Msk                                      (0x01UL << LCD_PAL93_I0_Pos)                              /*!< LCD PAL93: I0 Mask                  */
#define LCD_PAL93_R14_0_Pos                                   16                                                        /*!< LCD PAL93: R14_0 Position           */
#define LCD_PAL93_R14_0_Msk                                   (0x1fUL << LCD_PAL93_R14_0_Pos)                           /*!< LCD PAL93: R14_0 Mask               */
#define LCD_PAL93_G14_0_Pos                                   21                                                        /*!< LCD PAL93: G14_0 Position           */
#define LCD_PAL93_G14_0_Msk                                   (0x1fUL << LCD_PAL93_G14_0_Pos)                           /*!< LCD PAL93: G14_0 Mask               */
#define LCD_PAL93_B14_0_Pos                                   26                                                        /*!< LCD PAL93: B14_0 Position           */
#define LCD_PAL93_B14_0_Msk                                   (0x1fUL << LCD_PAL93_B14_0_Pos)                           /*!< LCD PAL93: B14_0 Mask               */
#define LCD_PAL93_I1_Pos                                      31                                                        /*!< LCD PAL93: I1 Position              */
#define LCD_PAL93_I1_Msk                                      (0x01UL << LCD_PAL93_I1_Pos)                              /*!< LCD PAL93: I1 Mask                  */

// ----------------------------------------  LCD_PAL94  -------------------------------------------
#define LCD_PAL94_R04_0_Pos                                   0                                                         /*!< LCD PAL94: R04_0 Position           */
#define LCD_PAL94_R04_0_Msk                                   (0x1fUL << LCD_PAL94_R04_0_Pos)                           /*!< LCD PAL94: R04_0 Mask               */
#define LCD_PAL94_G04_0_Pos                                   5                                                         /*!< LCD PAL94: G04_0 Position           */
#define LCD_PAL94_G04_0_Msk                                   (0x1fUL << LCD_PAL94_G04_0_Pos)                           /*!< LCD PAL94: G04_0 Mask               */
#define LCD_PAL94_B04_0_Pos                                   10                                                        /*!< LCD PAL94: B04_0 Position           */
#define LCD_PAL94_B04_0_Msk                                   (0x1fUL << LCD_PAL94_B04_0_Pos)                           /*!< LCD PAL94: B04_0 Mask               */
#define LCD_PAL94_I0_Pos                                      15                                                        /*!< LCD PAL94: I0 Position              */
#define LCD_PAL94_I0_Msk                                      (0x01UL << LCD_PAL94_I0_Pos)                              /*!< LCD PAL94: I0 Mask                  */
#define LCD_PAL94_R14_0_Pos                                   16                                                        /*!< LCD PAL94: R14_0 Position           */
#define LCD_PAL94_R14_0_Msk                                   (0x1fUL << LCD_PAL94_R14_0_Pos)                           /*!< LCD PAL94: R14_0 Mask               */
#define LCD_PAL94_G14_0_Pos                                   21                                                        /*!< LCD PAL94: G14_0 Position           */
#define LCD_PAL94_G14_0_Msk                                   (0x1fUL << LCD_PAL94_G14_0_Pos)                           /*!< LCD PAL94: G14_0 Mask               */
#define LCD_PAL94_B14_0_Pos                                   26                                                        /*!< LCD PAL94: B14_0 Position           */
#define LCD_PAL94_B14_0_Msk                                   (0x1fUL << LCD_PAL94_B14_0_Pos)                           /*!< LCD PAL94: B14_0 Mask               */
#define LCD_PAL94_I1_Pos                                      31                                                        /*!< LCD PAL94: I1 Position              */
#define LCD_PAL94_I1_Msk                                      (0x01UL << LCD_PAL94_I1_Pos)                              /*!< LCD PAL94: I1 Mask                  */

// ----------------------------------------  LCD_PAL95  -------------------------------------------
#define LCD_PAL95_R04_0_Pos                                   0                                                         /*!< LCD PAL95: R04_0 Position           */
#define LCD_PAL95_R04_0_Msk                                   (0x1fUL << LCD_PAL95_R04_0_Pos)                           /*!< LCD PAL95: R04_0 Mask               */
#define LCD_PAL95_G04_0_Pos                                   5                                                         /*!< LCD PAL95: G04_0 Position           */
#define LCD_PAL95_G04_0_Msk                                   (0x1fUL << LCD_PAL95_G04_0_Pos)                           /*!< LCD PAL95: G04_0 Mask               */
#define LCD_PAL95_B04_0_Pos                                   10                                                        /*!< LCD PAL95: B04_0 Position           */
#define LCD_PAL95_B04_0_Msk                                   (0x1fUL << LCD_PAL95_B04_0_Pos)                           /*!< LCD PAL95: B04_0 Mask               */
#define LCD_PAL95_I0_Pos                                      15                                                        /*!< LCD PAL95: I0 Position              */
#define LCD_PAL95_I0_Msk                                      (0x01UL << LCD_PAL95_I0_Pos)                              /*!< LCD PAL95: I0 Mask                  */
#define LCD_PAL95_R14_0_Pos                                   16                                                        /*!< LCD PAL95: R14_0 Position           */
#define LCD_PAL95_R14_0_Msk                                   (0x1fUL << LCD_PAL95_R14_0_Pos)                           /*!< LCD PAL95: R14_0 Mask               */
#define LCD_PAL95_G14_0_Pos                                   21                                                        /*!< LCD PAL95: G14_0 Position           */
#define LCD_PAL95_G14_0_Msk                                   (0x1fUL << LCD_PAL95_G14_0_Pos)                           /*!< LCD PAL95: G14_0 Mask               */
#define LCD_PAL95_B14_0_Pos                                   26                                                        /*!< LCD PAL95: B14_0 Position           */
#define LCD_PAL95_B14_0_Msk                                   (0x1fUL << LCD_PAL95_B14_0_Pos)                           /*!< LCD PAL95: B14_0 Mask               */
#define LCD_PAL95_I1_Pos                                      31                                                        /*!< LCD PAL95: I1 Position              */
#define LCD_PAL95_I1_Msk                                      (0x01UL << LCD_PAL95_I1_Pos)                              /*!< LCD PAL95: I1 Mask                  */

// ----------------------------------------  LCD_PAL96  -------------------------------------------
#define LCD_PAL96_R04_0_Pos                                   0                                                         /*!< LCD PAL96: R04_0 Position           */
#define LCD_PAL96_R04_0_Msk                                   (0x1fUL << LCD_PAL96_R04_0_Pos)                           /*!< LCD PAL96: R04_0 Mask               */
#define LCD_PAL96_G04_0_Pos                                   5                                                         /*!< LCD PAL96: G04_0 Position           */
#define LCD_PAL96_G04_0_Msk                                   (0x1fUL << LCD_PAL96_G04_0_Pos)                           /*!< LCD PAL96: G04_0 Mask               */
#define LCD_PAL96_B04_0_Pos                                   10                                                        /*!< LCD PAL96: B04_0 Position           */
#define LCD_PAL96_B04_0_Msk                                   (0x1fUL << LCD_PAL96_B04_0_Pos)                           /*!< LCD PAL96: B04_0 Mask               */
#define LCD_PAL96_I0_Pos                                      15                                                        /*!< LCD PAL96: I0 Position              */
#define LCD_PAL96_I0_Msk                                      (0x01UL << LCD_PAL96_I0_Pos)                              /*!< LCD PAL96: I0 Mask                  */
#define LCD_PAL96_R14_0_Pos                                   16                                                        /*!< LCD PAL96: R14_0 Position           */
#define LCD_PAL96_R14_0_Msk                                   (0x1fUL << LCD_PAL96_R14_0_Pos)                           /*!< LCD PAL96: R14_0 Mask               */
#define LCD_PAL96_G14_0_Pos                                   21                                                        /*!< LCD PAL96: G14_0 Position           */
#define LCD_PAL96_G14_0_Msk                                   (0x1fUL << LCD_PAL96_G14_0_Pos)                           /*!< LCD PAL96: G14_0 Mask               */
#define LCD_PAL96_B14_0_Pos                                   26                                                        /*!< LCD PAL96: B14_0 Position           */
#define LCD_PAL96_B14_0_Msk                                   (0x1fUL << LCD_PAL96_B14_0_Pos)                           /*!< LCD PAL96: B14_0 Mask               */
#define LCD_PAL96_I1_Pos                                      31                                                        /*!< LCD PAL96: I1 Position              */
#define LCD_PAL96_I1_Msk                                      (0x01UL << LCD_PAL96_I1_Pos)                              /*!< LCD PAL96: I1 Mask                  */

// ----------------------------------------  LCD_PAL97  -------------------------------------------
#define LCD_PAL97_R04_0_Pos                                   0                                                         /*!< LCD PAL97: R04_0 Position           */
#define LCD_PAL97_R04_0_Msk                                   (0x1fUL << LCD_PAL97_R04_0_Pos)                           /*!< LCD PAL97: R04_0 Mask               */
#define LCD_PAL97_G04_0_Pos                                   5                                                         /*!< LCD PAL97: G04_0 Position           */
#define LCD_PAL97_G04_0_Msk                                   (0x1fUL << LCD_PAL97_G04_0_Pos)                           /*!< LCD PAL97: G04_0 Mask               */
#define LCD_PAL97_B04_0_Pos                                   10                                                        /*!< LCD PAL97: B04_0 Position           */
#define LCD_PAL97_B04_0_Msk                                   (0x1fUL << LCD_PAL97_B04_0_Pos)                           /*!< LCD PAL97: B04_0 Mask               */
#define LCD_PAL97_I0_Pos                                      15                                                        /*!< LCD PAL97: I0 Position              */
#define LCD_PAL97_I0_Msk                                      (0x01UL << LCD_PAL97_I0_Pos)                              /*!< LCD PAL97: I0 Mask                  */
#define LCD_PAL97_R14_0_Pos                                   16                                                        /*!< LCD PAL97: R14_0 Position           */
#define LCD_PAL97_R14_0_Msk                                   (0x1fUL << LCD_PAL97_R14_0_Pos)                           /*!< LCD PAL97: R14_0 Mask               */
#define LCD_PAL97_G14_0_Pos                                   21                                                        /*!< LCD PAL97: G14_0 Position           */
#define LCD_PAL97_G14_0_Msk                                   (0x1fUL << LCD_PAL97_G14_0_Pos)                           /*!< LCD PAL97: G14_0 Mask               */
#define LCD_PAL97_B14_0_Pos                                   26                                                        /*!< LCD PAL97: B14_0 Position           */
#define LCD_PAL97_B14_0_Msk                                   (0x1fUL << LCD_PAL97_B14_0_Pos)                           /*!< LCD PAL97: B14_0 Mask               */
#define LCD_PAL97_I1_Pos                                      31                                                        /*!< LCD PAL97: I1 Position              */
#define LCD_PAL97_I1_Msk                                      (0x01UL << LCD_PAL97_I1_Pos)                              /*!< LCD PAL97: I1 Mask                  */

// ----------------------------------------  LCD_PAL98  -------------------------------------------
#define LCD_PAL98_R04_0_Pos                                   0                                                         /*!< LCD PAL98: R04_0 Position           */
#define LCD_PAL98_R04_0_Msk                                   (0x1fUL << LCD_PAL98_R04_0_Pos)                           /*!< LCD PAL98: R04_0 Mask               */
#define LCD_PAL98_G04_0_Pos                                   5                                                         /*!< LCD PAL98: G04_0 Position           */
#define LCD_PAL98_G04_0_Msk                                   (0x1fUL << LCD_PAL98_G04_0_Pos)                           /*!< LCD PAL98: G04_0 Mask               */
#define LCD_PAL98_B04_0_Pos                                   10                                                        /*!< LCD PAL98: B04_0 Position           */
#define LCD_PAL98_B04_0_Msk                                   (0x1fUL << LCD_PAL98_B04_0_Pos)                           /*!< LCD PAL98: B04_0 Mask               */
#define LCD_PAL98_I0_Pos                                      15                                                        /*!< LCD PAL98: I0 Position              */
#define LCD_PAL98_I0_Msk                                      (0x01UL << LCD_PAL98_I0_Pos)                              /*!< LCD PAL98: I0 Mask                  */
#define LCD_PAL98_R14_0_Pos                                   16                                                        /*!< LCD PAL98: R14_0 Position           */
#define LCD_PAL98_R14_0_Msk                                   (0x1fUL << LCD_PAL98_R14_0_Pos)                           /*!< LCD PAL98: R14_0 Mask               */
#define LCD_PAL98_G14_0_Pos                                   21                                                        /*!< LCD PAL98: G14_0 Position           */
#define LCD_PAL98_G14_0_Msk                                   (0x1fUL << LCD_PAL98_G14_0_Pos)                           /*!< LCD PAL98: G14_0 Mask               */
#define LCD_PAL98_B14_0_Pos                                   26                                                        /*!< LCD PAL98: B14_0 Position           */
#define LCD_PAL98_B14_0_Msk                                   (0x1fUL << LCD_PAL98_B14_0_Pos)                           /*!< LCD PAL98: B14_0 Mask               */
#define LCD_PAL98_I1_Pos                                      31                                                        /*!< LCD PAL98: I1 Position              */
#define LCD_PAL98_I1_Msk                                      (0x01UL << LCD_PAL98_I1_Pos)                              /*!< LCD PAL98: I1 Mask                  */

// ----------------------------------------  LCD_PAL99  -------------------------------------------
#define LCD_PAL99_R04_0_Pos                                   0                                                         /*!< LCD PAL99: R04_0 Position           */
#define LCD_PAL99_R04_0_Msk                                   (0x1fUL << LCD_PAL99_R04_0_Pos)                           /*!< LCD PAL99: R04_0 Mask               */
#define LCD_PAL99_G04_0_Pos                                   5                                                         /*!< LCD PAL99: G04_0 Position           */
#define LCD_PAL99_G04_0_Msk                                   (0x1fUL << LCD_PAL99_G04_0_Pos)                           /*!< LCD PAL99: G04_0 Mask               */
#define LCD_PAL99_B04_0_Pos                                   10                                                        /*!< LCD PAL99: B04_0 Position           */
#define LCD_PAL99_B04_0_Msk                                   (0x1fUL << LCD_PAL99_B04_0_Pos)                           /*!< LCD PAL99: B04_0 Mask               */
#define LCD_PAL99_I0_Pos                                      15                                                        /*!< LCD PAL99: I0 Position              */
#define LCD_PAL99_I0_Msk                                      (0x01UL << LCD_PAL99_I0_Pos)                              /*!< LCD PAL99: I0 Mask                  */
#define LCD_PAL99_R14_0_Pos                                   16                                                        /*!< LCD PAL99: R14_0 Position           */
#define LCD_PAL99_R14_0_Msk                                   (0x1fUL << LCD_PAL99_R14_0_Pos)                           /*!< LCD PAL99: R14_0 Mask               */
#define LCD_PAL99_G14_0_Pos                                   21                                                        /*!< LCD PAL99: G14_0 Position           */
#define LCD_PAL99_G14_0_Msk                                   (0x1fUL << LCD_PAL99_G14_0_Pos)                           /*!< LCD PAL99: G14_0 Mask               */
#define LCD_PAL99_B14_0_Pos                                   26                                                        /*!< LCD PAL99: B14_0 Position           */
#define LCD_PAL99_B14_0_Msk                                   (0x1fUL << LCD_PAL99_B14_0_Pos)                           /*!< LCD PAL99: B14_0 Mask               */
#define LCD_PAL99_I1_Pos                                      31                                                        /*!< LCD PAL99: I1 Position              */
#define LCD_PAL99_I1_Msk                                      (0x01UL << LCD_PAL99_I1_Pos)                              /*!< LCD PAL99: I1 Mask                  */

// ---------------------------------------  LCD_PAL100  -------------------------------------------
#define LCD_PAL100_R04_0_Pos                                  0                                                         /*!< LCD PAL100: R04_0 Position          */
#define LCD_PAL100_R04_0_Msk                                  (0x1fUL << LCD_PAL100_R04_0_Pos)                          /*!< LCD PAL100: R04_0 Mask              */
#define LCD_PAL100_G04_0_Pos                                  5                                                         /*!< LCD PAL100: G04_0 Position          */
#define LCD_PAL100_G04_0_Msk                                  (0x1fUL << LCD_PAL100_G04_0_Pos)                          /*!< LCD PAL100: G04_0 Mask              */
#define LCD_PAL100_B04_0_Pos                                  10                                                        /*!< LCD PAL100: B04_0 Position          */
#define LCD_PAL100_B04_0_Msk                                  (0x1fUL << LCD_PAL100_B04_0_Pos)                          /*!< LCD PAL100: B04_0 Mask              */
#define LCD_PAL100_I0_Pos                                     15                                                        /*!< LCD PAL100: I0 Position             */
#define LCD_PAL100_I0_Msk                                     (0x01UL << LCD_PAL100_I0_Pos)                             /*!< LCD PAL100: I0 Mask                 */
#define LCD_PAL100_R14_0_Pos                                  16                                                        /*!< LCD PAL100: R14_0 Position          */
#define LCD_PAL100_R14_0_Msk                                  (0x1fUL << LCD_PAL100_R14_0_Pos)                          /*!< LCD PAL100: R14_0 Mask              */
#define LCD_PAL100_G14_0_Pos                                  21                                                        /*!< LCD PAL100: G14_0 Position          */
#define LCD_PAL100_G14_0_Msk                                  (0x1fUL << LCD_PAL100_G14_0_Pos)                          /*!< LCD PAL100: G14_0 Mask              */
#define LCD_PAL100_B14_0_Pos                                  26                                                        /*!< LCD PAL100: B14_0 Position          */
#define LCD_PAL100_B14_0_Msk                                  (0x1fUL << LCD_PAL100_B14_0_Pos)                          /*!< LCD PAL100: B14_0 Mask              */
#define LCD_PAL100_I1_Pos                                     31                                                        /*!< LCD PAL100: I1 Position             */
#define LCD_PAL100_I1_Msk                                     (0x01UL << LCD_PAL100_I1_Pos)                             /*!< LCD PAL100: I1 Mask                 */

// ---------------------------------------  LCD_PAL101  -------------------------------------------
#define LCD_PAL101_R04_0_Pos                                  0                                                         /*!< LCD PAL101: R04_0 Position          */
#define LCD_PAL101_R04_0_Msk                                  (0x1fUL << LCD_PAL101_R04_0_Pos)                          /*!< LCD PAL101: R04_0 Mask              */
#define LCD_PAL101_G04_0_Pos                                  5                                                         /*!< LCD PAL101: G04_0 Position          */
#define LCD_PAL101_G04_0_Msk                                  (0x1fUL << LCD_PAL101_G04_0_Pos)                          /*!< LCD PAL101: G04_0 Mask              */
#define LCD_PAL101_B04_0_Pos                                  10                                                        /*!< LCD PAL101: B04_0 Position          */
#define LCD_PAL101_B04_0_Msk                                  (0x1fUL << LCD_PAL101_B04_0_Pos)                          /*!< LCD PAL101: B04_0 Mask              */
#define LCD_PAL101_I0_Pos                                     15                                                        /*!< LCD PAL101: I0 Position             */
#define LCD_PAL101_I0_Msk                                     (0x01UL << LCD_PAL101_I0_Pos)                             /*!< LCD PAL101: I0 Mask                 */
#define LCD_PAL101_R14_0_Pos                                  16                                                        /*!< LCD PAL101: R14_0 Position          */
#define LCD_PAL101_R14_0_Msk                                  (0x1fUL << LCD_PAL101_R14_0_Pos)                          /*!< LCD PAL101: R14_0 Mask              */
#define LCD_PAL101_G14_0_Pos                                  21                                                        /*!< LCD PAL101: G14_0 Position          */
#define LCD_PAL101_G14_0_Msk                                  (0x1fUL << LCD_PAL101_G14_0_Pos)                          /*!< LCD PAL101: G14_0 Mask              */
#define LCD_PAL101_B14_0_Pos                                  26                                                        /*!< LCD PAL101: B14_0 Position          */
#define LCD_PAL101_B14_0_Msk                                  (0x1fUL << LCD_PAL101_B14_0_Pos)                          /*!< LCD PAL101: B14_0 Mask              */
#define LCD_PAL101_I1_Pos                                     31                                                        /*!< LCD PAL101: I1 Position             */
#define LCD_PAL101_I1_Msk                                     (0x01UL << LCD_PAL101_I1_Pos)                             /*!< LCD PAL101: I1 Mask                 */

// ---------------------------------------  LCD_PAL102  -------------------------------------------
#define LCD_PAL102_R04_0_Pos                                  0                                                         /*!< LCD PAL102: R04_0 Position          */
#define LCD_PAL102_R04_0_Msk                                  (0x1fUL << LCD_PAL102_R04_0_Pos)                          /*!< LCD PAL102: R04_0 Mask              */
#define LCD_PAL102_G04_0_Pos                                  5                                                         /*!< LCD PAL102: G04_0 Position          */
#define LCD_PAL102_G04_0_Msk                                  (0x1fUL << LCD_PAL102_G04_0_Pos)                          /*!< LCD PAL102: G04_0 Mask              */
#define LCD_PAL102_B04_0_Pos                                  10                                                        /*!< LCD PAL102: B04_0 Position          */
#define LCD_PAL102_B04_0_Msk                                  (0x1fUL << LCD_PAL102_B04_0_Pos)                          /*!< LCD PAL102: B04_0 Mask              */
#define LCD_PAL102_I0_Pos                                     15                                                        /*!< LCD PAL102: I0 Position             */
#define LCD_PAL102_I0_Msk                                     (0x01UL << LCD_PAL102_I0_Pos)                             /*!< LCD PAL102: I0 Mask                 */
#define LCD_PAL102_R14_0_Pos                                  16                                                        /*!< LCD PAL102: R14_0 Position          */
#define LCD_PAL102_R14_0_Msk                                  (0x1fUL << LCD_PAL102_R14_0_Pos)                          /*!< LCD PAL102: R14_0 Mask              */
#define LCD_PAL102_G14_0_Pos                                  21                                                        /*!< LCD PAL102: G14_0 Position          */
#define LCD_PAL102_G14_0_Msk                                  (0x1fUL << LCD_PAL102_G14_0_Pos)                          /*!< LCD PAL102: G14_0 Mask              */
#define LCD_PAL102_B14_0_Pos                                  26                                                        /*!< LCD PAL102: B14_0 Position          */
#define LCD_PAL102_B14_0_Msk                                  (0x1fUL << LCD_PAL102_B14_0_Pos)                          /*!< LCD PAL102: B14_0 Mask              */
#define LCD_PAL102_I1_Pos                                     31                                                        /*!< LCD PAL102: I1 Position             */
#define LCD_PAL102_I1_Msk                                     (0x01UL << LCD_PAL102_I1_Pos)                             /*!< LCD PAL102: I1 Mask                 */

// ---------------------------------------  LCD_PAL103  -------------------------------------------
#define LCD_PAL103_R04_0_Pos                                  0                                                         /*!< LCD PAL103: R04_0 Position          */
#define LCD_PAL103_R04_0_Msk                                  (0x1fUL << LCD_PAL103_R04_0_Pos)                          /*!< LCD PAL103: R04_0 Mask              */
#define LCD_PAL103_G04_0_Pos                                  5                                                         /*!< LCD PAL103: G04_0 Position          */
#define LCD_PAL103_G04_0_Msk                                  (0x1fUL << LCD_PAL103_G04_0_Pos)                          /*!< LCD PAL103: G04_0 Mask              */
#define LCD_PAL103_B04_0_Pos                                  10                                                        /*!< LCD PAL103: B04_0 Position          */
#define LCD_PAL103_B04_0_Msk                                  (0x1fUL << LCD_PAL103_B04_0_Pos)                          /*!< LCD PAL103: B04_0 Mask              */
#define LCD_PAL103_I0_Pos                                     15                                                        /*!< LCD PAL103: I0 Position             */
#define LCD_PAL103_I0_Msk                                     (0x01UL << LCD_PAL103_I0_Pos)                             /*!< LCD PAL103: I0 Mask                 */
#define LCD_PAL103_R14_0_Pos                                  16                                                        /*!< LCD PAL103: R14_0 Position          */
#define LCD_PAL103_R14_0_Msk                                  (0x1fUL << LCD_PAL103_R14_0_Pos)                          /*!< LCD PAL103: R14_0 Mask              */
#define LCD_PAL103_G14_0_Pos                                  21                                                        /*!< LCD PAL103: G14_0 Position          */
#define LCD_PAL103_G14_0_Msk                                  (0x1fUL << LCD_PAL103_G14_0_Pos)                          /*!< LCD PAL103: G14_0 Mask              */
#define LCD_PAL103_B14_0_Pos                                  26                                                        /*!< LCD PAL103: B14_0 Position          */
#define LCD_PAL103_B14_0_Msk                                  (0x1fUL << LCD_PAL103_B14_0_Pos)                          /*!< LCD PAL103: B14_0 Mask              */
#define LCD_PAL103_I1_Pos                                     31                                                        /*!< LCD PAL103: I1 Position             */
#define LCD_PAL103_I1_Msk                                     (0x01UL << LCD_PAL103_I1_Pos)                             /*!< LCD PAL103: I1 Mask                 */

// ---------------------------------------  LCD_PAL104  -------------------------------------------
#define LCD_PAL104_R04_0_Pos                                  0                                                         /*!< LCD PAL104: R04_0 Position          */
#define LCD_PAL104_R04_0_Msk                                  (0x1fUL << LCD_PAL104_R04_0_Pos)                          /*!< LCD PAL104: R04_0 Mask              */
#define LCD_PAL104_G04_0_Pos                                  5                                                         /*!< LCD PAL104: G04_0 Position          */
#define LCD_PAL104_G04_0_Msk                                  (0x1fUL << LCD_PAL104_G04_0_Pos)                          /*!< LCD PAL104: G04_0 Mask              */
#define LCD_PAL104_B04_0_Pos                                  10                                                        /*!< LCD PAL104: B04_0 Position          */
#define LCD_PAL104_B04_0_Msk                                  (0x1fUL << LCD_PAL104_B04_0_Pos)                          /*!< LCD PAL104: B04_0 Mask              */
#define LCD_PAL104_I0_Pos                                     15                                                        /*!< LCD PAL104: I0 Position             */
#define LCD_PAL104_I0_Msk                                     (0x01UL << LCD_PAL104_I0_Pos)                             /*!< LCD PAL104: I0 Mask                 */
#define LCD_PAL104_R14_0_Pos                                  16                                                        /*!< LCD PAL104: R14_0 Position          */
#define LCD_PAL104_R14_0_Msk                                  (0x1fUL << LCD_PAL104_R14_0_Pos)                          /*!< LCD PAL104: R14_0 Mask              */
#define LCD_PAL104_G14_0_Pos                                  21                                                        /*!< LCD PAL104: G14_0 Position          */
#define LCD_PAL104_G14_0_Msk                                  (0x1fUL << LCD_PAL104_G14_0_Pos)                          /*!< LCD PAL104: G14_0 Mask              */
#define LCD_PAL104_B14_0_Pos                                  26                                                        /*!< LCD PAL104: B14_0 Position          */
#define LCD_PAL104_B14_0_Msk                                  (0x1fUL << LCD_PAL104_B14_0_Pos)                          /*!< LCD PAL104: B14_0 Mask              */
#define LCD_PAL104_I1_Pos                                     31                                                        /*!< LCD PAL104: I1 Position             */
#define LCD_PAL104_I1_Msk                                     (0x01UL << LCD_PAL104_I1_Pos)                             /*!< LCD PAL104: I1 Mask                 */

// ---------------------------------------  LCD_PAL105  -------------------------------------------
#define LCD_PAL105_R04_0_Pos                                  0                                                         /*!< LCD PAL105: R04_0 Position          */
#define LCD_PAL105_R04_0_Msk                                  (0x1fUL << LCD_PAL105_R04_0_Pos)                          /*!< LCD PAL105: R04_0 Mask              */
#define LCD_PAL105_G04_0_Pos                                  5                                                         /*!< LCD PAL105: G04_0 Position          */
#define LCD_PAL105_G04_0_Msk                                  (0x1fUL << LCD_PAL105_G04_0_Pos)                          /*!< LCD PAL105: G04_0 Mask              */
#define LCD_PAL105_B04_0_Pos                                  10                                                        /*!< LCD PAL105: B04_0 Position          */
#define LCD_PAL105_B04_0_Msk                                  (0x1fUL << LCD_PAL105_B04_0_Pos)                          /*!< LCD PAL105: B04_0 Mask              */
#define LCD_PAL105_I0_Pos                                     15                                                        /*!< LCD PAL105: I0 Position             */
#define LCD_PAL105_I0_Msk                                     (0x01UL << LCD_PAL105_I0_Pos)                             /*!< LCD PAL105: I0 Mask                 */
#define LCD_PAL105_R14_0_Pos                                  16                                                        /*!< LCD PAL105: R14_0 Position          */
#define LCD_PAL105_R14_0_Msk                                  (0x1fUL << LCD_PAL105_R14_0_Pos)                          /*!< LCD PAL105: R14_0 Mask              */
#define LCD_PAL105_G14_0_Pos                                  21                                                        /*!< LCD PAL105: G14_0 Position          */
#define LCD_PAL105_G14_0_Msk                                  (0x1fUL << LCD_PAL105_G14_0_Pos)                          /*!< LCD PAL105: G14_0 Mask              */
#define LCD_PAL105_B14_0_Pos                                  26                                                        /*!< LCD PAL105: B14_0 Position          */
#define LCD_PAL105_B14_0_Msk                                  (0x1fUL << LCD_PAL105_B14_0_Pos)                          /*!< LCD PAL105: B14_0 Mask              */
#define LCD_PAL105_I1_Pos                                     31                                                        /*!< LCD PAL105: I1 Position             */
#define LCD_PAL105_I1_Msk                                     (0x01UL << LCD_PAL105_I1_Pos)                             /*!< LCD PAL105: I1 Mask                 */

// ---------------------------------------  LCD_PAL106  -------------------------------------------
#define LCD_PAL106_R04_0_Pos                                  0                                                         /*!< LCD PAL106: R04_0 Position          */
#define LCD_PAL106_R04_0_Msk                                  (0x1fUL << LCD_PAL106_R04_0_Pos)                          /*!< LCD PAL106: R04_0 Mask              */
#define LCD_PAL106_G04_0_Pos                                  5                                                         /*!< LCD PAL106: G04_0 Position          */
#define LCD_PAL106_G04_0_Msk                                  (0x1fUL << LCD_PAL106_G04_0_Pos)                          /*!< LCD PAL106: G04_0 Mask              */
#define LCD_PAL106_B04_0_Pos                                  10                                                        /*!< LCD PAL106: B04_0 Position          */
#define LCD_PAL106_B04_0_Msk                                  (0x1fUL << LCD_PAL106_B04_0_Pos)                          /*!< LCD PAL106: B04_0 Mask              */
#define LCD_PAL106_I0_Pos                                     15                                                        /*!< LCD PAL106: I0 Position             */
#define LCD_PAL106_I0_Msk                                     (0x01UL << LCD_PAL106_I0_Pos)                             /*!< LCD PAL106: I0 Mask                 */
#define LCD_PAL106_R14_0_Pos                                  16                                                        /*!< LCD PAL106: R14_0 Position          */
#define LCD_PAL106_R14_0_Msk                                  (0x1fUL << LCD_PAL106_R14_0_Pos)                          /*!< LCD PAL106: R14_0 Mask              */
#define LCD_PAL106_G14_0_Pos                                  21                                                        /*!< LCD PAL106: G14_0 Position          */
#define LCD_PAL106_G14_0_Msk                                  (0x1fUL << LCD_PAL106_G14_0_Pos)                          /*!< LCD PAL106: G14_0 Mask              */
#define LCD_PAL106_B14_0_Pos                                  26                                                        /*!< LCD PAL106: B14_0 Position          */
#define LCD_PAL106_B14_0_Msk                                  (0x1fUL << LCD_PAL106_B14_0_Pos)                          /*!< LCD PAL106: B14_0 Mask              */
#define LCD_PAL106_I1_Pos                                     31                                                        /*!< LCD PAL106: I1 Position             */
#define LCD_PAL106_I1_Msk                                     (0x01UL << LCD_PAL106_I1_Pos)                             /*!< LCD PAL106: I1 Mask                 */

// ---------------------------------------  LCD_PAL107  -------------------------------------------
#define LCD_PAL107_R04_0_Pos                                  0                                                         /*!< LCD PAL107: R04_0 Position          */
#define LCD_PAL107_R04_0_Msk                                  (0x1fUL << LCD_PAL107_R04_0_Pos)                          /*!< LCD PAL107: R04_0 Mask              */
#define LCD_PAL107_G04_0_Pos                                  5                                                         /*!< LCD PAL107: G04_0 Position          */
#define LCD_PAL107_G04_0_Msk                                  (0x1fUL << LCD_PAL107_G04_0_Pos)                          /*!< LCD PAL107: G04_0 Mask              */
#define LCD_PAL107_B04_0_Pos                                  10                                                        /*!< LCD PAL107: B04_0 Position          */
#define LCD_PAL107_B04_0_Msk                                  (0x1fUL << LCD_PAL107_B04_0_Pos)                          /*!< LCD PAL107: B04_0 Mask              */
#define LCD_PAL107_I0_Pos                                     15                                                        /*!< LCD PAL107: I0 Position             */
#define LCD_PAL107_I0_Msk                                     (0x01UL << LCD_PAL107_I0_Pos)                             /*!< LCD PAL107: I0 Mask                 */
#define LCD_PAL107_R14_0_Pos                                  16                                                        /*!< LCD PAL107: R14_0 Position          */
#define LCD_PAL107_R14_0_Msk                                  (0x1fUL << LCD_PAL107_R14_0_Pos)                          /*!< LCD PAL107: R14_0 Mask              */
#define LCD_PAL107_G14_0_Pos                                  21                                                        /*!< LCD PAL107: G14_0 Position          */
#define LCD_PAL107_G14_0_Msk                                  (0x1fUL << LCD_PAL107_G14_0_Pos)                          /*!< LCD PAL107: G14_0 Mask              */
#define LCD_PAL107_B14_0_Pos                                  26                                                        /*!< LCD PAL107: B14_0 Position          */
#define LCD_PAL107_B14_0_Msk                                  (0x1fUL << LCD_PAL107_B14_0_Pos)                          /*!< LCD PAL107: B14_0 Mask              */
#define LCD_PAL107_I1_Pos                                     31                                                        /*!< LCD PAL107: I1 Position             */
#define LCD_PAL107_I1_Msk                                     (0x01UL << LCD_PAL107_I1_Pos)                             /*!< LCD PAL107: I1 Mask                 */

// ---------------------------------------  LCD_PAL108  -------------------------------------------
#define LCD_PAL108_R04_0_Pos                                  0                                                         /*!< LCD PAL108: R04_0 Position          */
#define LCD_PAL108_R04_0_Msk                                  (0x1fUL << LCD_PAL108_R04_0_Pos)                          /*!< LCD PAL108: R04_0 Mask              */
#define LCD_PAL108_G04_0_Pos                                  5                                                         /*!< LCD PAL108: G04_0 Position          */
#define LCD_PAL108_G04_0_Msk                                  (0x1fUL << LCD_PAL108_G04_0_Pos)                          /*!< LCD PAL108: G04_0 Mask              */
#define LCD_PAL108_B04_0_Pos                                  10                                                        /*!< LCD PAL108: B04_0 Position          */
#define LCD_PAL108_B04_0_Msk                                  (0x1fUL << LCD_PAL108_B04_0_Pos)                          /*!< LCD PAL108: B04_0 Mask              */
#define LCD_PAL108_I0_Pos                                     15                                                        /*!< LCD PAL108: I0 Position             */
#define LCD_PAL108_I0_Msk                                     (0x01UL << LCD_PAL108_I0_Pos)                             /*!< LCD PAL108: I0 Mask                 */
#define LCD_PAL108_R14_0_Pos                                  16                                                        /*!< LCD PAL108: R14_0 Position          */
#define LCD_PAL108_R14_0_Msk                                  (0x1fUL << LCD_PAL108_R14_0_Pos)                          /*!< LCD PAL108: R14_0 Mask              */
#define LCD_PAL108_G14_0_Pos                                  21                                                        /*!< LCD PAL108: G14_0 Position          */
#define LCD_PAL108_G14_0_Msk                                  (0x1fUL << LCD_PAL108_G14_0_Pos)                          /*!< LCD PAL108: G14_0 Mask              */
#define LCD_PAL108_B14_0_Pos                                  26                                                        /*!< LCD PAL108: B14_0 Position          */
#define LCD_PAL108_B14_0_Msk                                  (0x1fUL << LCD_PAL108_B14_0_Pos)                          /*!< LCD PAL108: B14_0 Mask              */
#define LCD_PAL108_I1_Pos                                     31                                                        /*!< LCD PAL108: I1 Position             */
#define LCD_PAL108_I1_Msk                                     (0x01UL << LCD_PAL108_I1_Pos)                             /*!< LCD PAL108: I1 Mask                 */

// ---------------------------------------  LCD_PAL109  -------------------------------------------
#define LCD_PAL109_R04_0_Pos                                  0                                                         /*!< LCD PAL109: R04_0 Position          */
#define LCD_PAL109_R04_0_Msk                                  (0x1fUL << LCD_PAL109_R04_0_Pos)                          /*!< LCD PAL109: R04_0 Mask              */
#define LCD_PAL109_G04_0_Pos                                  5                                                         /*!< LCD PAL109: G04_0 Position          */
#define LCD_PAL109_G04_0_Msk                                  (0x1fUL << LCD_PAL109_G04_0_Pos)                          /*!< LCD PAL109: G04_0 Mask              */
#define LCD_PAL109_B04_0_Pos                                  10                                                        /*!< LCD PAL109: B04_0 Position          */
#define LCD_PAL109_B04_0_Msk                                  (0x1fUL << LCD_PAL109_B04_0_Pos)                          /*!< LCD PAL109: B04_0 Mask              */
#define LCD_PAL109_I0_Pos                                     15                                                        /*!< LCD PAL109: I0 Position             */
#define LCD_PAL109_I0_Msk                                     (0x01UL << LCD_PAL109_I0_Pos)                             /*!< LCD PAL109: I0 Mask                 */
#define LCD_PAL109_R14_0_Pos                                  16                                                        /*!< LCD PAL109: R14_0 Position          */
#define LCD_PAL109_R14_0_Msk                                  (0x1fUL << LCD_PAL109_R14_0_Pos)                          /*!< LCD PAL109: R14_0 Mask              */
#define LCD_PAL109_G14_0_Pos                                  21                                                        /*!< LCD PAL109: G14_0 Position          */
#define LCD_PAL109_G14_0_Msk                                  (0x1fUL << LCD_PAL109_G14_0_Pos)                          /*!< LCD PAL109: G14_0 Mask              */
#define LCD_PAL109_B14_0_Pos                                  26                                                        /*!< LCD PAL109: B14_0 Position          */
#define LCD_PAL109_B14_0_Msk                                  (0x1fUL << LCD_PAL109_B14_0_Pos)                          /*!< LCD PAL109: B14_0 Mask              */
#define LCD_PAL109_I1_Pos                                     31                                                        /*!< LCD PAL109: I1 Position             */
#define LCD_PAL109_I1_Msk                                     (0x01UL << LCD_PAL109_I1_Pos)                             /*!< LCD PAL109: I1 Mask                 */

// ---------------------------------------  LCD_PAL110  -------------------------------------------
#define LCD_PAL110_R04_0_Pos                                  0                                                         /*!< LCD PAL110: R04_0 Position          */
#define LCD_PAL110_R04_0_Msk                                  (0x1fUL << LCD_PAL110_R04_0_Pos)                          /*!< LCD PAL110: R04_0 Mask              */
#define LCD_PAL110_G04_0_Pos                                  5                                                         /*!< LCD PAL110: G04_0 Position          */
#define LCD_PAL110_G04_0_Msk                                  (0x1fUL << LCD_PAL110_G04_0_Pos)                          /*!< LCD PAL110: G04_0 Mask              */
#define LCD_PAL110_B04_0_Pos                                  10                                                        /*!< LCD PAL110: B04_0 Position          */
#define LCD_PAL110_B04_0_Msk                                  (0x1fUL << LCD_PAL110_B04_0_Pos)                          /*!< LCD PAL110: B04_0 Mask              */
#define LCD_PAL110_I0_Pos                                     15                                                        /*!< LCD PAL110: I0 Position             */
#define LCD_PAL110_I0_Msk                                     (0x01UL << LCD_PAL110_I0_Pos)                             /*!< LCD PAL110: I0 Mask                 */
#define LCD_PAL110_R14_0_Pos                                  16                                                        /*!< LCD PAL110: R14_0 Position          */
#define LCD_PAL110_R14_0_Msk                                  (0x1fUL << LCD_PAL110_R14_0_Pos)                          /*!< LCD PAL110: R14_0 Mask              */
#define LCD_PAL110_G14_0_Pos                                  21                                                        /*!< LCD PAL110: G14_0 Position          */
#define LCD_PAL110_G14_0_Msk                                  (0x1fUL << LCD_PAL110_G14_0_Pos)                          /*!< LCD PAL110: G14_0 Mask              */
#define LCD_PAL110_B14_0_Pos                                  26                                                        /*!< LCD PAL110: B14_0 Position          */
#define LCD_PAL110_B14_0_Msk                                  (0x1fUL << LCD_PAL110_B14_0_Pos)                          /*!< LCD PAL110: B14_0 Mask              */
#define LCD_PAL110_I1_Pos                                     31                                                        /*!< LCD PAL110: I1 Position             */
#define LCD_PAL110_I1_Msk                                     (0x01UL << LCD_PAL110_I1_Pos)                             /*!< LCD PAL110: I1 Mask                 */

// ---------------------------------------  LCD_PAL111  -------------------------------------------
#define LCD_PAL111_R04_0_Pos                                  0                                                         /*!< LCD PAL111: R04_0 Position          */
#define LCD_PAL111_R04_0_Msk                                  (0x1fUL << LCD_PAL111_R04_0_Pos)                          /*!< LCD PAL111: R04_0 Mask              */
#define LCD_PAL111_G04_0_Pos                                  5                                                         /*!< LCD PAL111: G04_0 Position          */
#define LCD_PAL111_G04_0_Msk                                  (0x1fUL << LCD_PAL111_G04_0_Pos)                          /*!< LCD PAL111: G04_0 Mask              */
#define LCD_PAL111_B04_0_Pos                                  10                                                        /*!< LCD PAL111: B04_0 Position          */
#define LCD_PAL111_B04_0_Msk                                  (0x1fUL << LCD_PAL111_B04_0_Pos)                          /*!< LCD PAL111: B04_0 Mask              */
#define LCD_PAL111_I0_Pos                                     15                                                        /*!< LCD PAL111: I0 Position             */
#define LCD_PAL111_I0_Msk                                     (0x01UL << LCD_PAL111_I0_Pos)                             /*!< LCD PAL111: I0 Mask                 */
#define LCD_PAL111_R14_0_Pos                                  16                                                        /*!< LCD PAL111: R14_0 Position          */
#define LCD_PAL111_R14_0_Msk                                  (0x1fUL << LCD_PAL111_R14_0_Pos)                          /*!< LCD PAL111: R14_0 Mask              */
#define LCD_PAL111_G14_0_Pos                                  21                                                        /*!< LCD PAL111: G14_0 Position          */
#define LCD_PAL111_G14_0_Msk                                  (0x1fUL << LCD_PAL111_G14_0_Pos)                          /*!< LCD PAL111: G14_0 Mask              */
#define LCD_PAL111_B14_0_Pos                                  26                                                        /*!< LCD PAL111: B14_0 Position          */
#define LCD_PAL111_B14_0_Msk                                  (0x1fUL << LCD_PAL111_B14_0_Pos)                          /*!< LCD PAL111: B14_0 Mask              */
#define LCD_PAL111_I1_Pos                                     31                                                        /*!< LCD PAL111: I1 Position             */
#define LCD_PAL111_I1_Msk                                     (0x01UL << LCD_PAL111_I1_Pos)                             /*!< LCD PAL111: I1 Mask                 */

// ---------------------------------------  LCD_PAL112  -------------------------------------------
#define LCD_PAL112_R04_0_Pos                                  0                                                         /*!< LCD PAL112: R04_0 Position          */
#define LCD_PAL112_R04_0_Msk                                  (0x1fUL << LCD_PAL112_R04_0_Pos)                          /*!< LCD PAL112: R04_0 Mask              */
#define LCD_PAL112_G04_0_Pos                                  5                                                         /*!< LCD PAL112: G04_0 Position          */
#define LCD_PAL112_G04_0_Msk                                  (0x1fUL << LCD_PAL112_G04_0_Pos)                          /*!< LCD PAL112: G04_0 Mask              */
#define LCD_PAL112_B04_0_Pos                                  10                                                        /*!< LCD PAL112: B04_0 Position          */
#define LCD_PAL112_B04_0_Msk                                  (0x1fUL << LCD_PAL112_B04_0_Pos)                          /*!< LCD PAL112: B04_0 Mask              */
#define LCD_PAL112_I0_Pos                                     15                                                        /*!< LCD PAL112: I0 Position             */
#define LCD_PAL112_I0_Msk                                     (0x01UL << LCD_PAL112_I0_Pos)                             /*!< LCD PAL112: I0 Mask                 */
#define LCD_PAL112_R14_0_Pos                                  16                                                        /*!< LCD PAL112: R14_0 Position          */
#define LCD_PAL112_R14_0_Msk                                  (0x1fUL << LCD_PAL112_R14_0_Pos)                          /*!< LCD PAL112: R14_0 Mask              */
#define LCD_PAL112_G14_0_Pos                                  21                                                        /*!< LCD PAL112: G14_0 Position          */
#define LCD_PAL112_G14_0_Msk                                  (0x1fUL << LCD_PAL112_G14_0_Pos)                          /*!< LCD PAL112: G14_0 Mask              */
#define LCD_PAL112_B14_0_Pos                                  26                                                        /*!< LCD PAL112: B14_0 Position          */
#define LCD_PAL112_B14_0_Msk                                  (0x1fUL << LCD_PAL112_B14_0_Pos)                          /*!< LCD PAL112: B14_0 Mask              */
#define LCD_PAL112_I1_Pos                                     31                                                        /*!< LCD PAL112: I1 Position             */
#define LCD_PAL112_I1_Msk                                     (0x01UL << LCD_PAL112_I1_Pos)                             /*!< LCD PAL112: I1 Mask                 */

// ---------------------------------------  LCD_PAL113  -------------------------------------------
#define LCD_PAL113_R04_0_Pos                                  0                                                         /*!< LCD PAL113: R04_0 Position          */
#define LCD_PAL113_R04_0_Msk                                  (0x1fUL << LCD_PAL113_R04_0_Pos)                          /*!< LCD PAL113: R04_0 Mask              */
#define LCD_PAL113_G04_0_Pos                                  5                                                         /*!< LCD PAL113: G04_0 Position          */
#define LCD_PAL113_G04_0_Msk                                  (0x1fUL << LCD_PAL113_G04_0_Pos)                          /*!< LCD PAL113: G04_0 Mask              */
#define LCD_PAL113_B04_0_Pos                                  10                                                        /*!< LCD PAL113: B04_0 Position          */
#define LCD_PAL113_B04_0_Msk                                  (0x1fUL << LCD_PAL113_B04_0_Pos)                          /*!< LCD PAL113: B04_0 Mask              */
#define LCD_PAL113_I0_Pos                                     15                                                        /*!< LCD PAL113: I0 Position             */
#define LCD_PAL113_I0_Msk                                     (0x01UL << LCD_PAL113_I0_Pos)                             /*!< LCD PAL113: I0 Mask                 */
#define LCD_PAL113_R14_0_Pos                                  16                                                        /*!< LCD PAL113: R14_0 Position          */
#define LCD_PAL113_R14_0_Msk                                  (0x1fUL << LCD_PAL113_R14_0_Pos)                          /*!< LCD PAL113: R14_0 Mask              */
#define LCD_PAL113_G14_0_Pos                                  21                                                        /*!< LCD PAL113: G14_0 Position          */
#define LCD_PAL113_G14_0_Msk                                  (0x1fUL << LCD_PAL113_G14_0_Pos)                          /*!< LCD PAL113: G14_0 Mask              */
#define LCD_PAL113_B14_0_Pos                                  26                                                        /*!< LCD PAL113: B14_0 Position          */
#define LCD_PAL113_B14_0_Msk                                  (0x1fUL << LCD_PAL113_B14_0_Pos)                          /*!< LCD PAL113: B14_0 Mask              */
#define LCD_PAL113_I1_Pos                                     31                                                        /*!< LCD PAL113: I1 Position             */
#define LCD_PAL113_I1_Msk                                     (0x01UL << LCD_PAL113_I1_Pos)                             /*!< LCD PAL113: I1 Mask                 */

// ---------------------------------------  LCD_PAL114  -------------------------------------------
#define LCD_PAL114_R04_0_Pos                                  0                                                         /*!< LCD PAL114: R04_0 Position          */
#define LCD_PAL114_R04_0_Msk                                  (0x1fUL << LCD_PAL114_R04_0_Pos)                          /*!< LCD PAL114: R04_0 Mask              */
#define LCD_PAL114_G04_0_Pos                                  5                                                         /*!< LCD PAL114: G04_0 Position          */
#define LCD_PAL114_G04_0_Msk                                  (0x1fUL << LCD_PAL114_G04_0_Pos)                          /*!< LCD PAL114: G04_0 Mask              */
#define LCD_PAL114_B04_0_Pos                                  10                                                        /*!< LCD PAL114: B04_0 Position          */
#define LCD_PAL114_B04_0_Msk                                  (0x1fUL << LCD_PAL114_B04_0_Pos)                          /*!< LCD PAL114: B04_0 Mask              */
#define LCD_PAL114_I0_Pos                                     15                                                        /*!< LCD PAL114: I0 Position             */
#define LCD_PAL114_I0_Msk                                     (0x01UL << LCD_PAL114_I0_Pos)                             /*!< LCD PAL114: I0 Mask                 */
#define LCD_PAL114_R14_0_Pos                                  16                                                        /*!< LCD PAL114: R14_0 Position          */
#define LCD_PAL114_R14_0_Msk                                  (0x1fUL << LCD_PAL114_R14_0_Pos)                          /*!< LCD PAL114: R14_0 Mask              */
#define LCD_PAL114_G14_0_Pos                                  21                                                        /*!< LCD PAL114: G14_0 Position          */
#define LCD_PAL114_G14_0_Msk                                  (0x1fUL << LCD_PAL114_G14_0_Pos)                          /*!< LCD PAL114: G14_0 Mask              */
#define LCD_PAL114_B14_0_Pos                                  26                                                        /*!< LCD PAL114: B14_0 Position          */
#define LCD_PAL114_B14_0_Msk                                  (0x1fUL << LCD_PAL114_B14_0_Pos)                          /*!< LCD PAL114: B14_0 Mask              */
#define LCD_PAL114_I1_Pos                                     31                                                        /*!< LCD PAL114: I1 Position             */
#define LCD_PAL114_I1_Msk                                     (0x01UL << LCD_PAL114_I1_Pos)                             /*!< LCD PAL114: I1 Mask                 */

// ---------------------------------------  LCD_PAL115  -------------------------------------------
#define LCD_PAL115_R04_0_Pos                                  0                                                         /*!< LCD PAL115: R04_0 Position          */
#define LCD_PAL115_R04_0_Msk                                  (0x1fUL << LCD_PAL115_R04_0_Pos)                          /*!< LCD PAL115: R04_0 Mask              */
#define LCD_PAL115_G04_0_Pos                                  5                                                         /*!< LCD PAL115: G04_0 Position          */
#define LCD_PAL115_G04_0_Msk                                  (0x1fUL << LCD_PAL115_G04_0_Pos)                          /*!< LCD PAL115: G04_0 Mask              */
#define LCD_PAL115_B04_0_Pos                                  10                                                        /*!< LCD PAL115: B04_0 Position          */
#define LCD_PAL115_B04_0_Msk                                  (0x1fUL << LCD_PAL115_B04_0_Pos)                          /*!< LCD PAL115: B04_0 Mask              */
#define LCD_PAL115_I0_Pos                                     15                                                        /*!< LCD PAL115: I0 Position             */
#define LCD_PAL115_I0_Msk                                     (0x01UL << LCD_PAL115_I0_Pos)                             /*!< LCD PAL115: I0 Mask                 */
#define LCD_PAL115_R14_0_Pos                                  16                                                        /*!< LCD PAL115: R14_0 Position          */
#define LCD_PAL115_R14_0_Msk                                  (0x1fUL << LCD_PAL115_R14_0_Pos)                          /*!< LCD PAL115: R14_0 Mask              */
#define LCD_PAL115_G14_0_Pos                                  21                                                        /*!< LCD PAL115: G14_0 Position          */
#define LCD_PAL115_G14_0_Msk                                  (0x1fUL << LCD_PAL115_G14_0_Pos)                          /*!< LCD PAL115: G14_0 Mask              */
#define LCD_PAL115_B14_0_Pos                                  26                                                        /*!< LCD PAL115: B14_0 Position          */
#define LCD_PAL115_B14_0_Msk                                  (0x1fUL << LCD_PAL115_B14_0_Pos)                          /*!< LCD PAL115: B14_0 Mask              */
#define LCD_PAL115_I1_Pos                                     31                                                        /*!< LCD PAL115: I1 Position             */
#define LCD_PAL115_I1_Msk                                     (0x01UL << LCD_PAL115_I1_Pos)                             /*!< LCD PAL115: I1 Mask                 */

// ---------------------------------------  LCD_PAL116  -------------------------------------------
#define LCD_PAL116_R04_0_Pos                                  0                                                         /*!< LCD PAL116: R04_0 Position          */
#define LCD_PAL116_R04_0_Msk                                  (0x1fUL << LCD_PAL116_R04_0_Pos)                          /*!< LCD PAL116: R04_0 Mask              */
#define LCD_PAL116_G04_0_Pos                                  5                                                         /*!< LCD PAL116: G04_0 Position          */
#define LCD_PAL116_G04_0_Msk                                  (0x1fUL << LCD_PAL116_G04_0_Pos)                          /*!< LCD PAL116: G04_0 Mask              */
#define LCD_PAL116_B04_0_Pos                                  10                                                        /*!< LCD PAL116: B04_0 Position          */
#define LCD_PAL116_B04_0_Msk                                  (0x1fUL << LCD_PAL116_B04_0_Pos)                          /*!< LCD PAL116: B04_0 Mask              */
#define LCD_PAL116_I0_Pos                                     15                                                        /*!< LCD PAL116: I0 Position             */
#define LCD_PAL116_I0_Msk                                     (0x01UL << LCD_PAL116_I0_Pos)                             /*!< LCD PAL116: I0 Mask                 */
#define LCD_PAL116_R14_0_Pos                                  16                                                        /*!< LCD PAL116: R14_0 Position          */
#define LCD_PAL116_R14_0_Msk                                  (0x1fUL << LCD_PAL116_R14_0_Pos)                          /*!< LCD PAL116: R14_0 Mask              */
#define LCD_PAL116_G14_0_Pos                                  21                                                        /*!< LCD PAL116: G14_0 Position          */
#define LCD_PAL116_G14_0_Msk                                  (0x1fUL << LCD_PAL116_G14_0_Pos)                          /*!< LCD PAL116: G14_0 Mask              */
#define LCD_PAL116_B14_0_Pos                                  26                                                        /*!< LCD PAL116: B14_0 Position          */
#define LCD_PAL116_B14_0_Msk                                  (0x1fUL << LCD_PAL116_B14_0_Pos)                          /*!< LCD PAL116: B14_0 Mask              */
#define LCD_PAL116_I1_Pos                                     31                                                        /*!< LCD PAL116: I1 Position             */
#define LCD_PAL116_I1_Msk                                     (0x01UL << LCD_PAL116_I1_Pos)                             /*!< LCD PAL116: I1 Mask                 */

// ---------------------------------------  LCD_PAL117  -------------------------------------------
#define LCD_PAL117_R04_0_Pos                                  0                                                         /*!< LCD PAL117: R04_0 Position          */
#define LCD_PAL117_R04_0_Msk                                  (0x1fUL << LCD_PAL117_R04_0_Pos)                          /*!< LCD PAL117: R04_0 Mask              */
#define LCD_PAL117_G04_0_Pos                                  5                                                         /*!< LCD PAL117: G04_0 Position          */
#define LCD_PAL117_G04_0_Msk                                  (0x1fUL << LCD_PAL117_G04_0_Pos)                          /*!< LCD PAL117: G04_0 Mask              */
#define LCD_PAL117_B04_0_Pos                                  10                                                        /*!< LCD PAL117: B04_0 Position          */
#define LCD_PAL117_B04_0_Msk                                  (0x1fUL << LCD_PAL117_B04_0_Pos)                          /*!< LCD PAL117: B04_0 Mask              */
#define LCD_PAL117_I0_Pos                                     15                                                        /*!< LCD PAL117: I0 Position             */
#define LCD_PAL117_I0_Msk                                     (0x01UL << LCD_PAL117_I0_Pos)                             /*!< LCD PAL117: I0 Mask                 */
#define LCD_PAL117_R14_0_Pos                                  16                                                        /*!< LCD PAL117: R14_0 Position          */
#define LCD_PAL117_R14_0_Msk                                  (0x1fUL << LCD_PAL117_R14_0_Pos)                          /*!< LCD PAL117: R14_0 Mask              */
#define LCD_PAL117_G14_0_Pos                                  21                                                        /*!< LCD PAL117: G14_0 Position          */
#define LCD_PAL117_G14_0_Msk                                  (0x1fUL << LCD_PAL117_G14_0_Pos)                          /*!< LCD PAL117: G14_0 Mask              */
#define LCD_PAL117_B14_0_Pos                                  26                                                        /*!< LCD PAL117: B14_0 Position          */
#define LCD_PAL117_B14_0_Msk                                  (0x1fUL << LCD_PAL117_B14_0_Pos)                          /*!< LCD PAL117: B14_0 Mask              */
#define LCD_PAL117_I1_Pos                                     31                                                        /*!< LCD PAL117: I1 Position             */
#define LCD_PAL117_I1_Msk                                     (0x01UL << LCD_PAL117_I1_Pos)                             /*!< LCD PAL117: I1 Mask                 */

// ---------------------------------------  LCD_PAL118  -------------------------------------------
#define LCD_PAL118_R04_0_Pos                                  0                                                         /*!< LCD PAL118: R04_0 Position          */
#define LCD_PAL118_R04_0_Msk                                  (0x1fUL << LCD_PAL118_R04_0_Pos)                          /*!< LCD PAL118: R04_0 Mask              */
#define LCD_PAL118_G04_0_Pos                                  5                                                         /*!< LCD PAL118: G04_0 Position          */
#define LCD_PAL118_G04_0_Msk                                  (0x1fUL << LCD_PAL118_G04_0_Pos)                          /*!< LCD PAL118: G04_0 Mask              */
#define LCD_PAL118_B04_0_Pos                                  10                                                        /*!< LCD PAL118: B04_0 Position          */
#define LCD_PAL118_B04_0_Msk                                  (0x1fUL << LCD_PAL118_B04_0_Pos)                          /*!< LCD PAL118: B04_0 Mask              */
#define LCD_PAL118_I0_Pos                                     15                                                        /*!< LCD PAL118: I0 Position             */
#define LCD_PAL118_I0_Msk                                     (0x01UL << LCD_PAL118_I0_Pos)                             /*!< LCD PAL118: I0 Mask                 */
#define LCD_PAL118_R14_0_Pos                                  16                                                        /*!< LCD PAL118: R14_0 Position          */
#define LCD_PAL118_R14_0_Msk                                  (0x1fUL << LCD_PAL118_R14_0_Pos)                          /*!< LCD PAL118: R14_0 Mask              */
#define LCD_PAL118_G14_0_Pos                                  21                                                        /*!< LCD PAL118: G14_0 Position          */
#define LCD_PAL118_G14_0_Msk                                  (0x1fUL << LCD_PAL118_G14_0_Pos)                          /*!< LCD PAL118: G14_0 Mask              */
#define LCD_PAL118_B14_0_Pos                                  26                                                        /*!< LCD PAL118: B14_0 Position          */
#define LCD_PAL118_B14_0_Msk                                  (0x1fUL << LCD_PAL118_B14_0_Pos)                          /*!< LCD PAL118: B14_0 Mask              */
#define LCD_PAL118_I1_Pos                                     31                                                        /*!< LCD PAL118: I1 Position             */
#define LCD_PAL118_I1_Msk                                     (0x01UL << LCD_PAL118_I1_Pos)                             /*!< LCD PAL118: I1 Mask                 */

// ---------------------------------------  LCD_PAL119  -------------------------------------------
#define LCD_PAL119_R04_0_Pos                                  0                                                         /*!< LCD PAL119: R04_0 Position          */
#define LCD_PAL119_R04_0_Msk                                  (0x1fUL << LCD_PAL119_R04_0_Pos)                          /*!< LCD PAL119: R04_0 Mask              */
#define LCD_PAL119_G04_0_Pos                                  5                                                         /*!< LCD PAL119: G04_0 Position          */
#define LCD_PAL119_G04_0_Msk                                  (0x1fUL << LCD_PAL119_G04_0_Pos)                          /*!< LCD PAL119: G04_0 Mask              */
#define LCD_PAL119_B04_0_Pos                                  10                                                        /*!< LCD PAL119: B04_0 Position          */
#define LCD_PAL119_B04_0_Msk                                  (0x1fUL << LCD_PAL119_B04_0_Pos)                          /*!< LCD PAL119: B04_0 Mask              */
#define LCD_PAL119_I0_Pos                                     15                                                        /*!< LCD PAL119: I0 Position             */
#define LCD_PAL119_I0_Msk                                     (0x01UL << LCD_PAL119_I0_Pos)                             /*!< LCD PAL119: I0 Mask                 */
#define LCD_PAL119_R14_0_Pos                                  16                                                        /*!< LCD PAL119: R14_0 Position          */
#define LCD_PAL119_R14_0_Msk                                  (0x1fUL << LCD_PAL119_R14_0_Pos)                          /*!< LCD PAL119: R14_0 Mask              */
#define LCD_PAL119_G14_0_Pos                                  21                                                        /*!< LCD PAL119: G14_0 Position          */
#define LCD_PAL119_G14_0_Msk                                  (0x1fUL << LCD_PAL119_G14_0_Pos)                          /*!< LCD PAL119: G14_0 Mask              */
#define LCD_PAL119_B14_0_Pos                                  26                                                        /*!< LCD PAL119: B14_0 Position          */
#define LCD_PAL119_B14_0_Msk                                  (0x1fUL << LCD_PAL119_B14_0_Pos)                          /*!< LCD PAL119: B14_0 Mask              */
#define LCD_PAL119_I1_Pos                                     31                                                        /*!< LCD PAL119: I1 Position             */
#define LCD_PAL119_I1_Msk                                     (0x01UL << LCD_PAL119_I1_Pos)                             /*!< LCD PAL119: I1 Mask                 */

// ---------------------------------------  LCD_PAL120  -------------------------------------------
#define LCD_PAL120_R04_0_Pos                                  0                                                         /*!< LCD PAL120: R04_0 Position          */
#define LCD_PAL120_R04_0_Msk                                  (0x1fUL << LCD_PAL120_R04_0_Pos)                          /*!< LCD PAL120: R04_0 Mask              */
#define LCD_PAL120_G04_0_Pos                                  5                                                         /*!< LCD PAL120: G04_0 Position          */
#define LCD_PAL120_G04_0_Msk                                  (0x1fUL << LCD_PAL120_G04_0_Pos)                          /*!< LCD PAL120: G04_0 Mask              */
#define LCD_PAL120_B04_0_Pos                                  10                                                        /*!< LCD PAL120: B04_0 Position          */
#define LCD_PAL120_B04_0_Msk                                  (0x1fUL << LCD_PAL120_B04_0_Pos)                          /*!< LCD PAL120: B04_0 Mask              */
#define LCD_PAL120_I0_Pos                                     15                                                        /*!< LCD PAL120: I0 Position             */
#define LCD_PAL120_I0_Msk                                     (0x01UL << LCD_PAL120_I0_Pos)                             /*!< LCD PAL120: I0 Mask                 */
#define LCD_PAL120_R14_0_Pos                                  16                                                        /*!< LCD PAL120: R14_0 Position          */
#define LCD_PAL120_R14_0_Msk                                  (0x1fUL << LCD_PAL120_R14_0_Pos)                          /*!< LCD PAL120: R14_0 Mask              */
#define LCD_PAL120_G14_0_Pos                                  21                                                        /*!< LCD PAL120: G14_0 Position          */
#define LCD_PAL120_G14_0_Msk                                  (0x1fUL << LCD_PAL120_G14_0_Pos)                          /*!< LCD PAL120: G14_0 Mask              */
#define LCD_PAL120_B14_0_Pos                                  26                                                        /*!< LCD PAL120: B14_0 Position          */
#define LCD_PAL120_B14_0_Msk                                  (0x1fUL << LCD_PAL120_B14_0_Pos)                          /*!< LCD PAL120: B14_0 Mask              */
#define LCD_PAL120_I1_Pos                                     31                                                        /*!< LCD PAL120: I1 Position             */
#define LCD_PAL120_I1_Msk                                     (0x01UL << LCD_PAL120_I1_Pos)                             /*!< LCD PAL120: I1 Mask                 */

// ---------------------------------------  LCD_PAL121  -------------------------------------------
#define LCD_PAL121_R04_0_Pos                                  0                                                         /*!< LCD PAL121: R04_0 Position          */
#define LCD_PAL121_R04_0_Msk                                  (0x1fUL << LCD_PAL121_R04_0_Pos)                          /*!< LCD PAL121: R04_0 Mask              */
#define LCD_PAL121_G04_0_Pos                                  5                                                         /*!< LCD PAL121: G04_0 Position          */
#define LCD_PAL121_G04_0_Msk                                  (0x1fUL << LCD_PAL121_G04_0_Pos)                          /*!< LCD PAL121: G04_0 Mask              */
#define LCD_PAL121_B04_0_Pos                                  10                                                        /*!< LCD PAL121: B04_0 Position          */
#define LCD_PAL121_B04_0_Msk                                  (0x1fUL << LCD_PAL121_B04_0_Pos)                          /*!< LCD PAL121: B04_0 Mask              */
#define LCD_PAL121_I0_Pos                                     15                                                        /*!< LCD PAL121: I0 Position             */
#define LCD_PAL121_I0_Msk                                     (0x01UL << LCD_PAL121_I0_Pos)                             /*!< LCD PAL121: I0 Mask                 */
#define LCD_PAL121_R14_0_Pos                                  16                                                        /*!< LCD PAL121: R14_0 Position          */
#define LCD_PAL121_R14_0_Msk                                  (0x1fUL << LCD_PAL121_R14_0_Pos)                          /*!< LCD PAL121: R14_0 Mask              */
#define LCD_PAL121_G14_0_Pos                                  21                                                        /*!< LCD PAL121: G14_0 Position          */
#define LCD_PAL121_G14_0_Msk                                  (0x1fUL << LCD_PAL121_G14_0_Pos)                          /*!< LCD PAL121: G14_0 Mask              */
#define LCD_PAL121_B14_0_Pos                                  26                                                        /*!< LCD PAL121: B14_0 Position          */
#define LCD_PAL121_B14_0_Msk                                  (0x1fUL << LCD_PAL121_B14_0_Pos)                          /*!< LCD PAL121: B14_0 Mask              */
#define LCD_PAL121_I1_Pos                                     31                                                        /*!< LCD PAL121: I1 Position             */
#define LCD_PAL121_I1_Msk                                     (0x01UL << LCD_PAL121_I1_Pos)                             /*!< LCD PAL121: I1 Mask                 */

// ---------------------------------------  LCD_PAL122  -------------------------------------------
#define LCD_PAL122_R04_0_Pos                                  0                                                         /*!< LCD PAL122: R04_0 Position          */
#define LCD_PAL122_R04_0_Msk                                  (0x1fUL << LCD_PAL122_R04_0_Pos)                          /*!< LCD PAL122: R04_0 Mask              */
#define LCD_PAL122_G04_0_Pos                                  5                                                         /*!< LCD PAL122: G04_0 Position          */
#define LCD_PAL122_G04_0_Msk                                  (0x1fUL << LCD_PAL122_G04_0_Pos)                          /*!< LCD PAL122: G04_0 Mask              */
#define LCD_PAL122_B04_0_Pos                                  10                                                        /*!< LCD PAL122: B04_0 Position          */
#define LCD_PAL122_B04_0_Msk                                  (0x1fUL << LCD_PAL122_B04_0_Pos)                          /*!< LCD PAL122: B04_0 Mask              */
#define LCD_PAL122_I0_Pos                                     15                                                        /*!< LCD PAL122: I0 Position             */
#define LCD_PAL122_I0_Msk                                     (0x01UL << LCD_PAL122_I0_Pos)                             /*!< LCD PAL122: I0 Mask                 */
#define LCD_PAL122_R14_0_Pos                                  16                                                        /*!< LCD PAL122: R14_0 Position          */
#define LCD_PAL122_R14_0_Msk                                  (0x1fUL << LCD_PAL122_R14_0_Pos)                          /*!< LCD PAL122: R14_0 Mask              */
#define LCD_PAL122_G14_0_Pos                                  21                                                        /*!< LCD PAL122: G14_0 Position          */
#define LCD_PAL122_G14_0_Msk                                  (0x1fUL << LCD_PAL122_G14_0_Pos)                          /*!< LCD PAL122: G14_0 Mask              */
#define LCD_PAL122_B14_0_Pos                                  26                                                        /*!< LCD PAL122: B14_0 Position          */
#define LCD_PAL122_B14_0_Msk                                  (0x1fUL << LCD_PAL122_B14_0_Pos)                          /*!< LCD PAL122: B14_0 Mask              */
#define LCD_PAL122_I1_Pos                                     31                                                        /*!< LCD PAL122: I1 Position             */
#define LCD_PAL122_I1_Msk                                     (0x01UL << LCD_PAL122_I1_Pos)                             /*!< LCD PAL122: I1 Mask                 */

// ---------------------------------------  LCD_PAL123  -------------------------------------------
#define LCD_PAL123_R04_0_Pos                                  0                                                         /*!< LCD PAL123: R04_0 Position          */
#define LCD_PAL123_R04_0_Msk                                  (0x1fUL << LCD_PAL123_R04_0_Pos)                          /*!< LCD PAL123: R04_0 Mask              */
#define LCD_PAL123_G04_0_Pos                                  5                                                         /*!< LCD PAL123: G04_0 Position          */
#define LCD_PAL123_G04_0_Msk                                  (0x1fUL << LCD_PAL123_G04_0_Pos)                          /*!< LCD PAL123: G04_0 Mask              */
#define LCD_PAL123_B04_0_Pos                                  10                                                        /*!< LCD PAL123: B04_0 Position          */
#define LCD_PAL123_B04_0_Msk                                  (0x1fUL << LCD_PAL123_B04_0_Pos)                          /*!< LCD PAL123: B04_0 Mask              */
#define LCD_PAL123_I0_Pos                                     15                                                        /*!< LCD PAL123: I0 Position             */
#define LCD_PAL123_I0_Msk                                     (0x01UL << LCD_PAL123_I0_Pos)                             /*!< LCD PAL123: I0 Mask                 */
#define LCD_PAL123_R14_0_Pos                                  16                                                        /*!< LCD PAL123: R14_0 Position          */
#define LCD_PAL123_R14_0_Msk                                  (0x1fUL << LCD_PAL123_R14_0_Pos)                          /*!< LCD PAL123: R14_0 Mask              */
#define LCD_PAL123_G14_0_Pos                                  21                                                        /*!< LCD PAL123: G14_0 Position          */
#define LCD_PAL123_G14_0_Msk                                  (0x1fUL << LCD_PAL123_G14_0_Pos)                          /*!< LCD PAL123: G14_0 Mask              */
#define LCD_PAL123_B14_0_Pos                                  26                                                        /*!< LCD PAL123: B14_0 Position          */
#define LCD_PAL123_B14_0_Msk                                  (0x1fUL << LCD_PAL123_B14_0_Pos)                          /*!< LCD PAL123: B14_0 Mask              */
#define LCD_PAL123_I1_Pos                                     31                                                        /*!< LCD PAL123: I1 Position             */
#define LCD_PAL123_I1_Msk                                     (0x01UL << LCD_PAL123_I1_Pos)                             /*!< LCD PAL123: I1 Mask                 */

// ---------------------------------------  LCD_PAL124  -------------------------------------------
#define LCD_PAL124_R04_0_Pos                                  0                                                         /*!< LCD PAL124: R04_0 Position          */
#define LCD_PAL124_R04_0_Msk                                  (0x1fUL << LCD_PAL124_R04_0_Pos)                          /*!< LCD PAL124: R04_0 Mask              */
#define LCD_PAL124_G04_0_Pos                                  5                                                         /*!< LCD PAL124: G04_0 Position          */
#define LCD_PAL124_G04_0_Msk                                  (0x1fUL << LCD_PAL124_G04_0_Pos)                          /*!< LCD PAL124: G04_0 Mask              */
#define LCD_PAL124_B04_0_Pos                                  10                                                        /*!< LCD PAL124: B04_0 Position          */
#define LCD_PAL124_B04_0_Msk                                  (0x1fUL << LCD_PAL124_B04_0_Pos)                          /*!< LCD PAL124: B04_0 Mask              */
#define LCD_PAL124_I0_Pos                                     15                                                        /*!< LCD PAL124: I0 Position             */
#define LCD_PAL124_I0_Msk                                     (0x01UL << LCD_PAL124_I0_Pos)                             /*!< LCD PAL124: I0 Mask                 */
#define LCD_PAL124_R14_0_Pos                                  16                                                        /*!< LCD PAL124: R14_0 Position          */
#define LCD_PAL124_R14_0_Msk                                  (0x1fUL << LCD_PAL124_R14_0_Pos)                          /*!< LCD PAL124: R14_0 Mask              */
#define LCD_PAL124_G14_0_Pos                                  21                                                        /*!< LCD PAL124: G14_0 Position          */
#define LCD_PAL124_G14_0_Msk                                  (0x1fUL << LCD_PAL124_G14_0_Pos)                          /*!< LCD PAL124: G14_0 Mask              */
#define LCD_PAL124_B14_0_Pos                                  26                                                        /*!< LCD PAL124: B14_0 Position          */
#define LCD_PAL124_B14_0_Msk                                  (0x1fUL << LCD_PAL124_B14_0_Pos)                          /*!< LCD PAL124: B14_0 Mask              */
#define LCD_PAL124_I1_Pos                                     31                                                        /*!< LCD PAL124: I1 Position             */
#define LCD_PAL124_I1_Msk                                     (0x01UL << LCD_PAL124_I1_Pos)                             /*!< LCD PAL124: I1 Mask                 */

// ---------------------------------------  LCD_PAL125  -------------------------------------------
#define LCD_PAL125_R04_0_Pos                                  0                                                         /*!< LCD PAL125: R04_0 Position          */
#define LCD_PAL125_R04_0_Msk                                  (0x1fUL << LCD_PAL125_R04_0_Pos)                          /*!< LCD PAL125: R04_0 Mask              */
#define LCD_PAL125_G04_0_Pos                                  5                                                         /*!< LCD PAL125: G04_0 Position          */
#define LCD_PAL125_G04_0_Msk                                  (0x1fUL << LCD_PAL125_G04_0_Pos)                          /*!< LCD PAL125: G04_0 Mask              */
#define LCD_PAL125_B04_0_Pos                                  10                                                        /*!< LCD PAL125: B04_0 Position          */
#define LCD_PAL125_B04_0_Msk                                  (0x1fUL << LCD_PAL125_B04_0_Pos)                          /*!< LCD PAL125: B04_0 Mask              */
#define LCD_PAL125_I0_Pos                                     15                                                        /*!< LCD PAL125: I0 Position             */
#define LCD_PAL125_I0_Msk                                     (0x01UL << LCD_PAL125_I0_Pos)                             /*!< LCD PAL125: I0 Mask                 */
#define LCD_PAL125_R14_0_Pos                                  16                                                        /*!< LCD PAL125: R14_0 Position          */
#define LCD_PAL125_R14_0_Msk                                  (0x1fUL << LCD_PAL125_R14_0_Pos)                          /*!< LCD PAL125: R14_0 Mask              */
#define LCD_PAL125_G14_0_Pos                                  21                                                        /*!< LCD PAL125: G14_0 Position          */
#define LCD_PAL125_G14_0_Msk                                  (0x1fUL << LCD_PAL125_G14_0_Pos)                          /*!< LCD PAL125: G14_0 Mask              */
#define LCD_PAL125_B14_0_Pos                                  26                                                        /*!< LCD PAL125: B14_0 Position          */
#define LCD_PAL125_B14_0_Msk                                  (0x1fUL << LCD_PAL125_B14_0_Pos)                          /*!< LCD PAL125: B14_0 Mask              */
#define LCD_PAL125_I1_Pos                                     31                                                        /*!< LCD PAL125: I1 Position             */
#define LCD_PAL125_I1_Msk                                     (0x01UL << LCD_PAL125_I1_Pos)                             /*!< LCD PAL125: I1 Mask                 */

// ---------------------------------------  LCD_PAL126  -------------------------------------------
#define LCD_PAL126_R04_0_Pos                                  0                                                         /*!< LCD PAL126: R04_0 Position          */
#define LCD_PAL126_R04_0_Msk                                  (0x1fUL << LCD_PAL126_R04_0_Pos)                          /*!< LCD PAL126: R04_0 Mask              */
#define LCD_PAL126_G04_0_Pos                                  5                                                         /*!< LCD PAL126: G04_0 Position          */
#define LCD_PAL126_G04_0_Msk                                  (0x1fUL << LCD_PAL126_G04_0_Pos)                          /*!< LCD PAL126: G04_0 Mask              */
#define LCD_PAL126_B04_0_Pos                                  10                                                        /*!< LCD PAL126: B04_0 Position          */
#define LCD_PAL126_B04_0_Msk                                  (0x1fUL << LCD_PAL126_B04_0_Pos)                          /*!< LCD PAL126: B04_0 Mask              */
#define LCD_PAL126_I0_Pos                                     15                                                        /*!< LCD PAL126: I0 Position             */
#define LCD_PAL126_I0_Msk                                     (0x01UL << LCD_PAL126_I0_Pos)                             /*!< LCD PAL126: I0 Mask                 */
#define LCD_PAL126_R14_0_Pos                                  16                                                        /*!< LCD PAL126: R14_0 Position          */
#define LCD_PAL126_R14_0_Msk                                  (0x1fUL << LCD_PAL126_R14_0_Pos)                          /*!< LCD PAL126: R14_0 Mask              */
#define LCD_PAL126_G14_0_Pos                                  21                                                        /*!< LCD PAL126: G14_0 Position          */
#define LCD_PAL126_G14_0_Msk                                  (0x1fUL << LCD_PAL126_G14_0_Pos)                          /*!< LCD PAL126: G14_0 Mask              */
#define LCD_PAL126_B14_0_Pos                                  26                                                        /*!< LCD PAL126: B14_0 Position          */
#define LCD_PAL126_B14_0_Msk                                  (0x1fUL << LCD_PAL126_B14_0_Pos)                          /*!< LCD PAL126: B14_0 Mask              */
#define LCD_PAL126_I1_Pos                                     31                                                        /*!< LCD PAL126: I1 Position             */
#define LCD_PAL126_I1_Msk                                     (0x01UL << LCD_PAL126_I1_Pos)                             /*!< LCD PAL126: I1 Mask                 */

// ---------------------------------------  LCD_PAL127  -------------------------------------------
#define LCD_PAL127_R04_0_Pos                                  0                                                         /*!< LCD PAL127: R04_0 Position          */
#define LCD_PAL127_R04_0_Msk                                  (0x1fUL << LCD_PAL127_R04_0_Pos)                          /*!< LCD PAL127: R04_0 Mask              */
#define LCD_PAL127_G04_0_Pos                                  5                                                         /*!< LCD PAL127: G04_0 Position          */
#define LCD_PAL127_G04_0_Msk                                  (0x1fUL << LCD_PAL127_G04_0_Pos)                          /*!< LCD PAL127: G04_0 Mask              */
#define LCD_PAL127_B04_0_Pos                                  10                                                        /*!< LCD PAL127: B04_0 Position          */
#define LCD_PAL127_B04_0_Msk                                  (0x1fUL << LCD_PAL127_B04_0_Pos)                          /*!< LCD PAL127: B04_0 Mask              */
#define LCD_PAL127_I0_Pos                                     15                                                        /*!< LCD PAL127: I0 Position             */
#define LCD_PAL127_I0_Msk                                     (0x01UL << LCD_PAL127_I0_Pos)                             /*!< LCD PAL127: I0 Mask                 */
#define LCD_PAL127_R14_0_Pos                                  16                                                        /*!< LCD PAL127: R14_0 Position          */
#define LCD_PAL127_R14_0_Msk                                  (0x1fUL << LCD_PAL127_R14_0_Pos)                          /*!< LCD PAL127: R14_0 Mask              */
#define LCD_PAL127_G14_0_Pos                                  21                                                        /*!< LCD PAL127: G14_0 Position          */
#define LCD_PAL127_G14_0_Msk                                  (0x1fUL << LCD_PAL127_G14_0_Pos)                          /*!< LCD PAL127: G14_0 Mask              */
#define LCD_PAL127_B14_0_Pos                                  26                                                        /*!< LCD PAL127: B14_0 Position          */
#define LCD_PAL127_B14_0_Msk                                  (0x1fUL << LCD_PAL127_B14_0_Pos)                          /*!< LCD PAL127: B14_0 Mask              */
#define LCD_PAL127_I1_Pos                                     31                                                        /*!< LCD PAL127: I1 Position             */
#define LCD_PAL127_I1_Msk                                     (0x01UL << LCD_PAL127_I1_Pos)                             /*!< LCD PAL127: I1 Mask                 */

// ---------------------------------------  LCD_PAL128  -------------------------------------------
#define LCD_PAL128_R04_0_Pos                                  0                                                         /*!< LCD PAL128: R04_0 Position          */
#define LCD_PAL128_R04_0_Msk                                  (0x1fUL << LCD_PAL128_R04_0_Pos)                          /*!< LCD PAL128: R04_0 Mask              */
#define LCD_PAL128_G04_0_Pos                                  5                                                         /*!< LCD PAL128: G04_0 Position          */
#define LCD_PAL128_G04_0_Msk                                  (0x1fUL << LCD_PAL128_G04_0_Pos)                          /*!< LCD PAL128: G04_0 Mask              */
#define LCD_PAL128_B04_0_Pos                                  10                                                        /*!< LCD PAL128: B04_0 Position          */
#define LCD_PAL128_B04_0_Msk                                  (0x1fUL << LCD_PAL128_B04_0_Pos)                          /*!< LCD PAL128: B04_0 Mask              */
#define LCD_PAL128_I0_Pos                                     15                                                        /*!< LCD PAL128: I0 Position             */
#define LCD_PAL128_I0_Msk                                     (0x01UL << LCD_PAL128_I0_Pos)                             /*!< LCD PAL128: I0 Mask                 */
#define LCD_PAL128_R14_0_Pos                                  16                                                        /*!< LCD PAL128: R14_0 Position          */
#define LCD_PAL128_R14_0_Msk                                  (0x1fUL << LCD_PAL128_R14_0_Pos)                          /*!< LCD PAL128: R14_0 Mask              */
#define LCD_PAL128_G14_0_Pos                                  21                                                        /*!< LCD PAL128: G14_0 Position          */
#define LCD_PAL128_G14_0_Msk                                  (0x1fUL << LCD_PAL128_G14_0_Pos)                          /*!< LCD PAL128: G14_0 Mask              */
#define LCD_PAL128_B14_0_Pos                                  26                                                        /*!< LCD PAL128: B14_0 Position          */
#define LCD_PAL128_B14_0_Msk                                  (0x1fUL << LCD_PAL128_B14_0_Pos)                          /*!< LCD PAL128: B14_0 Mask              */
#define LCD_PAL128_I1_Pos                                     31                                                        /*!< LCD PAL128: I1 Position             */
#define LCD_PAL128_I1_Msk                                     (0x01UL << LCD_PAL128_I1_Pos)                             /*!< LCD PAL128: I1 Mask                 */

// ---------------------------------------  LCD_PAL129  -------------------------------------------
#define LCD_PAL129_R04_0_Pos                                  0                                                         /*!< LCD PAL129: R04_0 Position          */
#define LCD_PAL129_R04_0_Msk                                  (0x1fUL << LCD_PAL129_R04_0_Pos)                          /*!< LCD PAL129: R04_0 Mask              */
#define LCD_PAL129_G04_0_Pos                                  5                                                         /*!< LCD PAL129: G04_0 Position          */
#define LCD_PAL129_G04_0_Msk                                  (0x1fUL << LCD_PAL129_G04_0_Pos)                          /*!< LCD PAL129: G04_0 Mask              */
#define LCD_PAL129_B04_0_Pos                                  10                                                        /*!< LCD PAL129: B04_0 Position          */
#define LCD_PAL129_B04_0_Msk                                  (0x1fUL << LCD_PAL129_B04_0_Pos)                          /*!< LCD PAL129: B04_0 Mask              */
#define LCD_PAL129_I0_Pos                                     15                                                        /*!< LCD PAL129: I0 Position             */
#define LCD_PAL129_I0_Msk                                     (0x01UL << LCD_PAL129_I0_Pos)                             /*!< LCD PAL129: I0 Mask                 */
#define LCD_PAL129_R14_0_Pos                                  16                                                        /*!< LCD PAL129: R14_0 Position          */
#define LCD_PAL129_R14_0_Msk                                  (0x1fUL << LCD_PAL129_R14_0_Pos)                          /*!< LCD PAL129: R14_0 Mask              */
#define LCD_PAL129_G14_0_Pos                                  21                                                        /*!< LCD PAL129: G14_0 Position          */
#define LCD_PAL129_G14_0_Msk                                  (0x1fUL << LCD_PAL129_G14_0_Pos)                          /*!< LCD PAL129: G14_0 Mask              */
#define LCD_PAL129_B14_0_Pos                                  26                                                        /*!< LCD PAL129: B14_0 Position          */
#define LCD_PAL129_B14_0_Msk                                  (0x1fUL << LCD_PAL129_B14_0_Pos)                          /*!< LCD PAL129: B14_0 Mask              */
#define LCD_PAL129_I1_Pos                                     31                                                        /*!< LCD PAL129: I1 Position             */
#define LCD_PAL129_I1_Msk                                     (0x01UL << LCD_PAL129_I1_Pos)                             /*!< LCD PAL129: I1 Mask                 */

// ---------------------------------------  LCD_PAL130  -------------------------------------------
#define LCD_PAL130_R04_0_Pos                                  0                                                         /*!< LCD PAL130: R04_0 Position          */
#define LCD_PAL130_R04_0_Msk                                  (0x1fUL << LCD_PAL130_R04_0_Pos)                          /*!< LCD PAL130: R04_0 Mask              */
#define LCD_PAL130_G04_0_Pos                                  5                                                         /*!< LCD PAL130: G04_0 Position          */
#define LCD_PAL130_G04_0_Msk                                  (0x1fUL << LCD_PAL130_G04_0_Pos)                          /*!< LCD PAL130: G04_0 Mask              */
#define LCD_PAL130_B04_0_Pos                                  10                                                        /*!< LCD PAL130: B04_0 Position          */
#define LCD_PAL130_B04_0_Msk                                  (0x1fUL << LCD_PAL130_B04_0_Pos)                          /*!< LCD PAL130: B04_0 Mask              */
#define LCD_PAL130_I0_Pos                                     15                                                        /*!< LCD PAL130: I0 Position             */
#define LCD_PAL130_I0_Msk                                     (0x01UL << LCD_PAL130_I0_Pos)                             /*!< LCD PAL130: I0 Mask                 */
#define LCD_PAL130_R14_0_Pos                                  16                                                        /*!< LCD PAL130: R14_0 Position          */
#define LCD_PAL130_R14_0_Msk                                  (0x1fUL << LCD_PAL130_R14_0_Pos)                          /*!< LCD PAL130: R14_0 Mask              */
#define LCD_PAL130_G14_0_Pos                                  21                                                        /*!< LCD PAL130: G14_0 Position          */
#define LCD_PAL130_G14_0_Msk                                  (0x1fUL << LCD_PAL130_G14_0_Pos)                          /*!< LCD PAL130: G14_0 Mask              */
#define LCD_PAL130_B14_0_Pos                                  26                                                        /*!< LCD PAL130: B14_0 Position          */
#define LCD_PAL130_B14_0_Msk                                  (0x1fUL << LCD_PAL130_B14_0_Pos)                          /*!< LCD PAL130: B14_0 Mask              */
#define LCD_PAL130_I1_Pos                                     31                                                        /*!< LCD PAL130: I1 Position             */
#define LCD_PAL130_I1_Msk                                     (0x01UL << LCD_PAL130_I1_Pos)                             /*!< LCD PAL130: I1 Mask                 */

// ---------------------------------------  LCD_PAL131  -------------------------------------------
#define LCD_PAL131_R04_0_Pos                                  0                                                         /*!< LCD PAL131: R04_0 Position          */
#define LCD_PAL131_R04_0_Msk                                  (0x1fUL << LCD_PAL131_R04_0_Pos)                          /*!< LCD PAL131: R04_0 Mask              */
#define LCD_PAL131_G04_0_Pos                                  5                                                         /*!< LCD PAL131: G04_0 Position          */
#define LCD_PAL131_G04_0_Msk                                  (0x1fUL << LCD_PAL131_G04_0_Pos)                          /*!< LCD PAL131: G04_0 Mask              */
#define LCD_PAL131_B04_0_Pos                                  10                                                        /*!< LCD PAL131: B04_0 Position          */
#define LCD_PAL131_B04_0_Msk                                  (0x1fUL << LCD_PAL131_B04_0_Pos)                          /*!< LCD PAL131: B04_0 Mask              */
#define LCD_PAL131_I0_Pos                                     15                                                        /*!< LCD PAL131: I0 Position             */
#define LCD_PAL131_I0_Msk                                     (0x01UL << LCD_PAL131_I0_Pos)                             /*!< LCD PAL131: I0 Mask                 */
#define LCD_PAL131_R14_0_Pos                                  16                                                        /*!< LCD PAL131: R14_0 Position          */
#define LCD_PAL131_R14_0_Msk                                  (0x1fUL << LCD_PAL131_R14_0_Pos)                          /*!< LCD PAL131: R14_0 Mask              */
#define LCD_PAL131_G14_0_Pos                                  21                                                        /*!< LCD PAL131: G14_0 Position          */
#define LCD_PAL131_G14_0_Msk                                  (0x1fUL << LCD_PAL131_G14_0_Pos)                          /*!< LCD PAL131: G14_0 Mask              */
#define LCD_PAL131_B14_0_Pos                                  26                                                        /*!< LCD PAL131: B14_0 Position          */
#define LCD_PAL131_B14_0_Msk                                  (0x1fUL << LCD_PAL131_B14_0_Pos)                          /*!< LCD PAL131: B14_0 Mask              */
#define LCD_PAL131_I1_Pos                                     31                                                        /*!< LCD PAL131: I1 Position             */
#define LCD_PAL131_I1_Msk                                     (0x01UL << LCD_PAL131_I1_Pos)                             /*!< LCD PAL131: I1 Mask                 */

// ---------------------------------------  LCD_PAL132  -------------------------------------------
#define LCD_PAL132_R04_0_Pos                                  0                                                         /*!< LCD PAL132: R04_0 Position          */
#define LCD_PAL132_R04_0_Msk                                  (0x1fUL << LCD_PAL132_R04_0_Pos)                          /*!< LCD PAL132: R04_0 Mask              */
#define LCD_PAL132_G04_0_Pos                                  5                                                         /*!< LCD PAL132: G04_0 Position          */
#define LCD_PAL132_G04_0_Msk                                  (0x1fUL << LCD_PAL132_G04_0_Pos)                          /*!< LCD PAL132: G04_0 Mask              */
#define LCD_PAL132_B04_0_Pos                                  10                                                        /*!< LCD PAL132: B04_0 Position          */
#define LCD_PAL132_B04_0_Msk                                  (0x1fUL << LCD_PAL132_B04_0_Pos)                          /*!< LCD PAL132: B04_0 Mask              */
#define LCD_PAL132_I0_Pos                                     15                                                        /*!< LCD PAL132: I0 Position             */
#define LCD_PAL132_I0_Msk                                     (0x01UL << LCD_PAL132_I0_Pos)                             /*!< LCD PAL132: I0 Mask                 */
#define LCD_PAL132_R14_0_Pos                                  16                                                        /*!< LCD PAL132: R14_0 Position          */
#define LCD_PAL132_R14_0_Msk                                  (0x1fUL << LCD_PAL132_R14_0_Pos)                          /*!< LCD PAL132: R14_0 Mask              */
#define LCD_PAL132_G14_0_Pos                                  21                                                        /*!< LCD PAL132: G14_0 Position          */
#define LCD_PAL132_G14_0_Msk                                  (0x1fUL << LCD_PAL132_G14_0_Pos)                          /*!< LCD PAL132: G14_0 Mask              */
#define LCD_PAL132_B14_0_Pos                                  26                                                        /*!< LCD PAL132: B14_0 Position          */
#define LCD_PAL132_B14_0_Msk                                  (0x1fUL << LCD_PAL132_B14_0_Pos)                          /*!< LCD PAL132: B14_0 Mask              */
#define LCD_PAL132_I1_Pos                                     31                                                        /*!< LCD PAL132: I1 Position             */
#define LCD_PAL132_I1_Msk                                     (0x01UL << LCD_PAL132_I1_Pos)                             /*!< LCD PAL132: I1 Mask                 */

// ---------------------------------------  LCD_PAL133  -------------------------------------------
#define LCD_PAL133_R04_0_Pos                                  0                                                         /*!< LCD PAL133: R04_0 Position          */
#define LCD_PAL133_R04_0_Msk                                  (0x1fUL << LCD_PAL133_R04_0_Pos)                          /*!< LCD PAL133: R04_0 Mask              */
#define LCD_PAL133_G04_0_Pos                                  5                                                         /*!< LCD PAL133: G04_0 Position          */
#define LCD_PAL133_G04_0_Msk                                  (0x1fUL << LCD_PAL133_G04_0_Pos)                          /*!< LCD PAL133: G04_0 Mask              */
#define LCD_PAL133_B04_0_Pos                                  10                                                        /*!< LCD PAL133: B04_0 Position          */
#define LCD_PAL133_B04_0_Msk                                  (0x1fUL << LCD_PAL133_B04_0_Pos)                          /*!< LCD PAL133: B04_0 Mask              */
#define LCD_PAL133_I0_Pos                                     15                                                        /*!< LCD PAL133: I0 Position             */
#define LCD_PAL133_I0_Msk                                     (0x01UL << LCD_PAL133_I0_Pos)                             /*!< LCD PAL133: I0 Mask                 */
#define LCD_PAL133_R14_0_Pos                                  16                                                        /*!< LCD PAL133: R14_0 Position          */
#define LCD_PAL133_R14_0_Msk                                  (0x1fUL << LCD_PAL133_R14_0_Pos)                          /*!< LCD PAL133: R14_0 Mask              */
#define LCD_PAL133_G14_0_Pos                                  21                                                        /*!< LCD PAL133: G14_0 Position          */
#define LCD_PAL133_G14_0_Msk                                  (0x1fUL << LCD_PAL133_G14_0_Pos)                          /*!< LCD PAL133: G14_0 Mask              */
#define LCD_PAL133_B14_0_Pos                                  26                                                        /*!< LCD PAL133: B14_0 Position          */
#define LCD_PAL133_B14_0_Msk                                  (0x1fUL << LCD_PAL133_B14_0_Pos)                          /*!< LCD PAL133: B14_0 Mask              */
#define LCD_PAL133_I1_Pos                                     31                                                        /*!< LCD PAL133: I1 Position             */
#define LCD_PAL133_I1_Msk                                     (0x01UL << LCD_PAL133_I1_Pos)                             /*!< LCD PAL133: I1 Mask                 */

// ---------------------------------------  LCD_PAL134  -------------------------------------------
#define LCD_PAL134_R04_0_Pos                                  0                                                         /*!< LCD PAL134: R04_0 Position          */
#define LCD_PAL134_R04_0_Msk                                  (0x1fUL << LCD_PAL134_R04_0_Pos)                          /*!< LCD PAL134: R04_0 Mask              */
#define LCD_PAL134_G04_0_Pos                                  5                                                         /*!< LCD PAL134: G04_0 Position          */
#define LCD_PAL134_G04_0_Msk                                  (0x1fUL << LCD_PAL134_G04_0_Pos)                          /*!< LCD PAL134: G04_0 Mask              */
#define LCD_PAL134_B04_0_Pos                                  10                                                        /*!< LCD PAL134: B04_0 Position          */
#define LCD_PAL134_B04_0_Msk                                  (0x1fUL << LCD_PAL134_B04_0_Pos)                          /*!< LCD PAL134: B04_0 Mask              */
#define LCD_PAL134_I0_Pos                                     15                                                        /*!< LCD PAL134: I0 Position             */
#define LCD_PAL134_I0_Msk                                     (0x01UL << LCD_PAL134_I0_Pos)                             /*!< LCD PAL134: I0 Mask                 */
#define LCD_PAL134_R14_0_Pos                                  16                                                        /*!< LCD PAL134: R14_0 Position          */
#define LCD_PAL134_R14_0_Msk                                  (0x1fUL << LCD_PAL134_R14_0_Pos)                          /*!< LCD PAL134: R14_0 Mask              */
#define LCD_PAL134_G14_0_Pos                                  21                                                        /*!< LCD PAL134: G14_0 Position          */
#define LCD_PAL134_G14_0_Msk                                  (0x1fUL << LCD_PAL134_G14_0_Pos)                          /*!< LCD PAL134: G14_0 Mask              */
#define LCD_PAL134_B14_0_Pos                                  26                                                        /*!< LCD PAL134: B14_0 Position          */
#define LCD_PAL134_B14_0_Msk                                  (0x1fUL << LCD_PAL134_B14_0_Pos)                          /*!< LCD PAL134: B14_0 Mask              */
#define LCD_PAL134_I1_Pos                                     31                                                        /*!< LCD PAL134: I1 Position             */
#define LCD_PAL134_I1_Msk                                     (0x01UL << LCD_PAL134_I1_Pos)                             /*!< LCD PAL134: I1 Mask                 */

// ---------------------------------------  LCD_PAL135  -------------------------------------------
#define LCD_PAL135_R04_0_Pos                                  0                                                         /*!< LCD PAL135: R04_0 Position          */
#define LCD_PAL135_R04_0_Msk                                  (0x1fUL << LCD_PAL135_R04_0_Pos)                          /*!< LCD PAL135: R04_0 Mask              */
#define LCD_PAL135_G04_0_Pos                                  5                                                         /*!< LCD PAL135: G04_0 Position          */
#define LCD_PAL135_G04_0_Msk                                  (0x1fUL << LCD_PAL135_G04_0_Pos)                          /*!< LCD PAL135: G04_0 Mask              */
#define LCD_PAL135_B04_0_Pos                                  10                                                        /*!< LCD PAL135: B04_0 Position          */
#define LCD_PAL135_B04_0_Msk                                  (0x1fUL << LCD_PAL135_B04_0_Pos)                          /*!< LCD PAL135: B04_0 Mask              */
#define LCD_PAL135_I0_Pos                                     15                                                        /*!< LCD PAL135: I0 Position             */
#define LCD_PAL135_I0_Msk                                     (0x01UL << LCD_PAL135_I0_Pos)                             /*!< LCD PAL135: I0 Mask                 */
#define LCD_PAL135_R14_0_Pos                                  16                                                        /*!< LCD PAL135: R14_0 Position          */
#define LCD_PAL135_R14_0_Msk                                  (0x1fUL << LCD_PAL135_R14_0_Pos)                          /*!< LCD PAL135: R14_0 Mask              */
#define LCD_PAL135_G14_0_Pos                                  21                                                        /*!< LCD PAL135: G14_0 Position          */
#define LCD_PAL135_G14_0_Msk                                  (0x1fUL << LCD_PAL135_G14_0_Pos)                          /*!< LCD PAL135: G14_0 Mask              */
#define LCD_PAL135_B14_0_Pos                                  26                                                        /*!< LCD PAL135: B14_0 Position          */
#define LCD_PAL135_B14_0_Msk                                  (0x1fUL << LCD_PAL135_B14_0_Pos)                          /*!< LCD PAL135: B14_0 Mask              */
#define LCD_PAL135_I1_Pos                                     31                                                        /*!< LCD PAL135: I1 Position             */
#define LCD_PAL135_I1_Msk                                     (0x01UL << LCD_PAL135_I1_Pos)                             /*!< LCD PAL135: I1 Mask                 */

// ---------------------------------------  LCD_PAL136  -------------------------------------------
#define LCD_PAL136_R04_0_Pos                                  0                                                         /*!< LCD PAL136: R04_0 Position          */
#define LCD_PAL136_R04_0_Msk                                  (0x1fUL << LCD_PAL136_R04_0_Pos)                          /*!< LCD PAL136: R04_0 Mask              */
#define LCD_PAL136_G04_0_Pos                                  5                                                         /*!< LCD PAL136: G04_0 Position          */
#define LCD_PAL136_G04_0_Msk                                  (0x1fUL << LCD_PAL136_G04_0_Pos)                          /*!< LCD PAL136: G04_0 Mask              */
#define LCD_PAL136_B04_0_Pos                                  10                                                        /*!< LCD PAL136: B04_0 Position          */
#define LCD_PAL136_B04_0_Msk                                  (0x1fUL << LCD_PAL136_B04_0_Pos)                          /*!< LCD PAL136: B04_0 Mask              */
#define LCD_PAL136_I0_Pos                                     15                                                        /*!< LCD PAL136: I0 Position             */
#define LCD_PAL136_I0_Msk                                     (0x01UL << LCD_PAL136_I0_Pos)                             /*!< LCD PAL136: I0 Mask                 */
#define LCD_PAL136_R14_0_Pos                                  16                                                        /*!< LCD PAL136: R14_0 Position          */
#define LCD_PAL136_R14_0_Msk                                  (0x1fUL << LCD_PAL136_R14_0_Pos)                          /*!< LCD PAL136: R14_0 Mask              */
#define LCD_PAL136_G14_0_Pos                                  21                                                        /*!< LCD PAL136: G14_0 Position          */
#define LCD_PAL136_G14_0_Msk                                  (0x1fUL << LCD_PAL136_G14_0_Pos)                          /*!< LCD PAL136: G14_0 Mask              */
#define LCD_PAL136_B14_0_Pos                                  26                                                        /*!< LCD PAL136: B14_0 Position          */
#define LCD_PAL136_B14_0_Msk                                  (0x1fUL << LCD_PAL136_B14_0_Pos)                          /*!< LCD PAL136: B14_0 Mask              */
#define LCD_PAL136_I1_Pos                                     31                                                        /*!< LCD PAL136: I1 Position             */
#define LCD_PAL136_I1_Msk                                     (0x01UL << LCD_PAL136_I1_Pos)                             /*!< LCD PAL136: I1 Mask                 */

// ---------------------------------------  LCD_PAL137  -------------------------------------------
#define LCD_PAL137_R04_0_Pos                                  0                                                         /*!< LCD PAL137: R04_0 Position          */
#define LCD_PAL137_R04_0_Msk                                  (0x1fUL << LCD_PAL137_R04_0_Pos)                          /*!< LCD PAL137: R04_0 Mask              */
#define LCD_PAL137_G04_0_Pos                                  5                                                         /*!< LCD PAL137: G04_0 Position          */
#define LCD_PAL137_G04_0_Msk                                  (0x1fUL << LCD_PAL137_G04_0_Pos)                          /*!< LCD PAL137: G04_0 Mask              */
#define LCD_PAL137_B04_0_Pos                                  10                                                        /*!< LCD PAL137: B04_0 Position          */
#define LCD_PAL137_B04_0_Msk                                  (0x1fUL << LCD_PAL137_B04_0_Pos)                          /*!< LCD PAL137: B04_0 Mask              */
#define LCD_PAL137_I0_Pos                                     15                                                        /*!< LCD PAL137: I0 Position             */
#define LCD_PAL137_I0_Msk                                     (0x01UL << LCD_PAL137_I0_Pos)                             /*!< LCD PAL137: I0 Mask                 */
#define LCD_PAL137_R14_0_Pos                                  16                                                        /*!< LCD PAL137: R14_0 Position          */
#define LCD_PAL137_R14_0_Msk                                  (0x1fUL << LCD_PAL137_R14_0_Pos)                          /*!< LCD PAL137: R14_0 Mask              */
#define LCD_PAL137_G14_0_Pos                                  21                                                        /*!< LCD PAL137: G14_0 Position          */
#define LCD_PAL137_G14_0_Msk                                  (0x1fUL << LCD_PAL137_G14_0_Pos)                          /*!< LCD PAL137: G14_0 Mask              */
#define LCD_PAL137_B14_0_Pos                                  26                                                        /*!< LCD PAL137: B14_0 Position          */
#define LCD_PAL137_B14_0_Msk                                  (0x1fUL << LCD_PAL137_B14_0_Pos)                          /*!< LCD PAL137: B14_0 Mask              */
#define LCD_PAL137_I1_Pos                                     31                                                        /*!< LCD PAL137: I1 Position             */
#define LCD_PAL137_I1_Msk                                     (0x01UL << LCD_PAL137_I1_Pos)                             /*!< LCD PAL137: I1 Mask                 */

// ---------------------------------------  LCD_PAL138  -------------------------------------------
#define LCD_PAL138_R04_0_Pos                                  0                                                         /*!< LCD PAL138: R04_0 Position          */
#define LCD_PAL138_R04_0_Msk                                  (0x1fUL << LCD_PAL138_R04_0_Pos)                          /*!< LCD PAL138: R04_0 Mask              */
#define LCD_PAL138_G04_0_Pos                                  5                                                         /*!< LCD PAL138: G04_0 Position          */
#define LCD_PAL138_G04_0_Msk                                  (0x1fUL << LCD_PAL138_G04_0_Pos)                          /*!< LCD PAL138: G04_0 Mask              */
#define LCD_PAL138_B04_0_Pos                                  10                                                        /*!< LCD PAL138: B04_0 Position          */
#define LCD_PAL138_B04_0_Msk                                  (0x1fUL << LCD_PAL138_B04_0_Pos)                          /*!< LCD PAL138: B04_0 Mask              */
#define LCD_PAL138_I0_Pos                                     15                                                        /*!< LCD PAL138: I0 Position             */
#define LCD_PAL138_I0_Msk                                     (0x01UL << LCD_PAL138_I0_Pos)                             /*!< LCD PAL138: I0 Mask                 */
#define LCD_PAL138_R14_0_Pos                                  16                                                        /*!< LCD PAL138: R14_0 Position          */
#define LCD_PAL138_R14_0_Msk                                  (0x1fUL << LCD_PAL138_R14_0_Pos)                          /*!< LCD PAL138: R14_0 Mask              */
#define LCD_PAL138_G14_0_Pos                                  21                                                        /*!< LCD PAL138: G14_0 Position          */
#define LCD_PAL138_G14_0_Msk                                  (0x1fUL << LCD_PAL138_G14_0_Pos)                          /*!< LCD PAL138: G14_0 Mask              */
#define LCD_PAL138_B14_0_Pos                                  26                                                        /*!< LCD PAL138: B14_0 Position          */
#define LCD_PAL138_B14_0_Msk                                  (0x1fUL << LCD_PAL138_B14_0_Pos)                          /*!< LCD PAL138: B14_0 Mask              */
#define LCD_PAL138_I1_Pos                                     31                                                        /*!< LCD PAL138: I1 Position             */
#define LCD_PAL138_I1_Msk                                     (0x01UL << LCD_PAL138_I1_Pos)                             /*!< LCD PAL138: I1 Mask                 */

// ---------------------------------------  LCD_PAL139  -------------------------------------------
#define LCD_PAL139_R04_0_Pos                                  0                                                         /*!< LCD PAL139: R04_0 Position          */
#define LCD_PAL139_R04_0_Msk                                  (0x1fUL << LCD_PAL139_R04_0_Pos)                          /*!< LCD PAL139: R04_0 Mask              */
#define LCD_PAL139_G04_0_Pos                                  5                                                         /*!< LCD PAL139: G04_0 Position          */
#define LCD_PAL139_G04_0_Msk                                  (0x1fUL << LCD_PAL139_G04_0_Pos)                          /*!< LCD PAL139: G04_0 Mask              */
#define LCD_PAL139_B04_0_Pos                                  10                                                        /*!< LCD PAL139: B04_0 Position          */
#define LCD_PAL139_B04_0_Msk                                  (0x1fUL << LCD_PAL139_B04_0_Pos)                          /*!< LCD PAL139: B04_0 Mask              */
#define LCD_PAL139_I0_Pos                                     15                                                        /*!< LCD PAL139: I0 Position             */
#define LCD_PAL139_I0_Msk                                     (0x01UL << LCD_PAL139_I0_Pos)                             /*!< LCD PAL139: I0 Mask                 */
#define LCD_PAL139_R14_0_Pos                                  16                                                        /*!< LCD PAL139: R14_0 Position          */
#define LCD_PAL139_R14_0_Msk                                  (0x1fUL << LCD_PAL139_R14_0_Pos)                          /*!< LCD PAL139: R14_0 Mask              */
#define LCD_PAL139_G14_0_Pos                                  21                                                        /*!< LCD PAL139: G14_0 Position          */
#define LCD_PAL139_G14_0_Msk                                  (0x1fUL << LCD_PAL139_G14_0_Pos)                          /*!< LCD PAL139: G14_0 Mask              */
#define LCD_PAL139_B14_0_Pos                                  26                                                        /*!< LCD PAL139: B14_0 Position          */
#define LCD_PAL139_B14_0_Msk                                  (0x1fUL << LCD_PAL139_B14_0_Pos)                          /*!< LCD PAL139: B14_0 Mask              */
#define LCD_PAL139_I1_Pos                                     31                                                        /*!< LCD PAL139: I1 Position             */
#define LCD_PAL139_I1_Msk                                     (0x01UL << LCD_PAL139_I1_Pos)                             /*!< LCD PAL139: I1 Mask                 */

// ---------------------------------------  LCD_PAL140  -------------------------------------------
#define LCD_PAL140_R04_0_Pos                                  0                                                         /*!< LCD PAL140: R04_0 Position          */
#define LCD_PAL140_R04_0_Msk                                  (0x1fUL << LCD_PAL140_R04_0_Pos)                          /*!< LCD PAL140: R04_0 Mask              */
#define LCD_PAL140_G04_0_Pos                                  5                                                         /*!< LCD PAL140: G04_0 Position          */
#define LCD_PAL140_G04_0_Msk                                  (0x1fUL << LCD_PAL140_G04_0_Pos)                          /*!< LCD PAL140: G04_0 Mask              */
#define LCD_PAL140_B04_0_Pos                                  10                                                        /*!< LCD PAL140: B04_0 Position          */
#define LCD_PAL140_B04_0_Msk                                  (0x1fUL << LCD_PAL140_B04_0_Pos)                          /*!< LCD PAL140: B04_0 Mask              */
#define LCD_PAL140_I0_Pos                                     15                                                        /*!< LCD PAL140: I0 Position             */
#define LCD_PAL140_I0_Msk                                     (0x01UL << LCD_PAL140_I0_Pos)                             /*!< LCD PAL140: I0 Mask                 */
#define LCD_PAL140_R14_0_Pos                                  16                                                        /*!< LCD PAL140: R14_0 Position          */
#define LCD_PAL140_R14_0_Msk                                  (0x1fUL << LCD_PAL140_R14_0_Pos)                          /*!< LCD PAL140: R14_0 Mask              */
#define LCD_PAL140_G14_0_Pos                                  21                                                        /*!< LCD PAL140: G14_0 Position          */
#define LCD_PAL140_G14_0_Msk                                  (0x1fUL << LCD_PAL140_G14_0_Pos)                          /*!< LCD PAL140: G14_0 Mask              */
#define LCD_PAL140_B14_0_Pos                                  26                                                        /*!< LCD PAL140: B14_0 Position          */
#define LCD_PAL140_B14_0_Msk                                  (0x1fUL << LCD_PAL140_B14_0_Pos)                          /*!< LCD PAL140: B14_0 Mask              */
#define LCD_PAL140_I1_Pos                                     31                                                        /*!< LCD PAL140: I1 Position             */
#define LCD_PAL140_I1_Msk                                     (0x01UL << LCD_PAL140_I1_Pos)                             /*!< LCD PAL140: I1 Mask                 */

// ---------------------------------------  LCD_PAL141  -------------------------------------------
#define LCD_PAL141_R04_0_Pos                                  0                                                         /*!< LCD PAL141: R04_0 Position          */
#define LCD_PAL141_R04_0_Msk                                  (0x1fUL << LCD_PAL141_R04_0_Pos)                          /*!< LCD PAL141: R04_0 Mask              */
#define LCD_PAL141_G04_0_Pos                                  5                                                         /*!< LCD PAL141: G04_0 Position          */
#define LCD_PAL141_G04_0_Msk                                  (0x1fUL << LCD_PAL141_G04_0_Pos)                          /*!< LCD PAL141: G04_0 Mask              */
#define LCD_PAL141_B04_0_Pos                                  10                                                        /*!< LCD PAL141: B04_0 Position          */
#define LCD_PAL141_B04_0_Msk                                  (0x1fUL << LCD_PAL141_B04_0_Pos)                          /*!< LCD PAL141: B04_0 Mask              */
#define LCD_PAL141_I0_Pos                                     15                                                        /*!< LCD PAL141: I0 Position             */
#define LCD_PAL141_I0_Msk                                     (0x01UL << LCD_PAL141_I0_Pos)                             /*!< LCD PAL141: I0 Mask                 */
#define LCD_PAL141_R14_0_Pos                                  16                                                        /*!< LCD PAL141: R14_0 Position          */
#define LCD_PAL141_R14_0_Msk                                  (0x1fUL << LCD_PAL141_R14_0_Pos)                          /*!< LCD PAL141: R14_0 Mask              */
#define LCD_PAL141_G14_0_Pos                                  21                                                        /*!< LCD PAL141: G14_0 Position          */
#define LCD_PAL141_G14_0_Msk                                  (0x1fUL << LCD_PAL141_G14_0_Pos)                          /*!< LCD PAL141: G14_0 Mask              */
#define LCD_PAL141_B14_0_Pos                                  26                                                        /*!< LCD PAL141: B14_0 Position          */
#define LCD_PAL141_B14_0_Msk                                  (0x1fUL << LCD_PAL141_B14_0_Pos)                          /*!< LCD PAL141: B14_0 Mask              */
#define LCD_PAL141_I1_Pos                                     31                                                        /*!< LCD PAL141: I1 Position             */
#define LCD_PAL141_I1_Msk                                     (0x01UL << LCD_PAL141_I1_Pos)                             /*!< LCD PAL141: I1 Mask                 */

// ---------------------------------------  LCD_PAL142  -------------------------------------------
#define LCD_PAL142_R04_0_Pos                                  0                                                         /*!< LCD PAL142: R04_0 Position          */
#define LCD_PAL142_R04_0_Msk                                  (0x1fUL << LCD_PAL142_R04_0_Pos)                          /*!< LCD PAL142: R04_0 Mask              */
#define LCD_PAL142_G04_0_Pos                                  5                                                         /*!< LCD PAL142: G04_0 Position          */
#define LCD_PAL142_G04_0_Msk                                  (0x1fUL << LCD_PAL142_G04_0_Pos)                          /*!< LCD PAL142: G04_0 Mask              */
#define LCD_PAL142_B04_0_Pos                                  10                                                        /*!< LCD PAL142: B04_0 Position          */
#define LCD_PAL142_B04_0_Msk                                  (0x1fUL << LCD_PAL142_B04_0_Pos)                          /*!< LCD PAL142: B04_0 Mask              */
#define LCD_PAL142_I0_Pos                                     15                                                        /*!< LCD PAL142: I0 Position             */
#define LCD_PAL142_I0_Msk                                     (0x01UL << LCD_PAL142_I0_Pos)                             /*!< LCD PAL142: I0 Mask                 */
#define LCD_PAL142_R14_0_Pos                                  16                                                        /*!< LCD PAL142: R14_0 Position          */
#define LCD_PAL142_R14_0_Msk                                  (0x1fUL << LCD_PAL142_R14_0_Pos)                          /*!< LCD PAL142: R14_0 Mask              */
#define LCD_PAL142_G14_0_Pos                                  21                                                        /*!< LCD PAL142: G14_0 Position          */
#define LCD_PAL142_G14_0_Msk                                  (0x1fUL << LCD_PAL142_G14_0_Pos)                          /*!< LCD PAL142: G14_0 Mask              */
#define LCD_PAL142_B14_0_Pos                                  26                                                        /*!< LCD PAL142: B14_0 Position          */
#define LCD_PAL142_B14_0_Msk                                  (0x1fUL << LCD_PAL142_B14_0_Pos)                          /*!< LCD PAL142: B14_0 Mask              */
#define LCD_PAL142_I1_Pos                                     31                                                        /*!< LCD PAL142: I1 Position             */
#define LCD_PAL142_I1_Msk                                     (0x01UL << LCD_PAL142_I1_Pos)                             /*!< LCD PAL142: I1 Mask                 */

// ---------------------------------------  LCD_PAL143  -------------------------------------------
#define LCD_PAL143_R04_0_Pos                                  0                                                         /*!< LCD PAL143: R04_0 Position          */
#define LCD_PAL143_R04_0_Msk                                  (0x1fUL << LCD_PAL143_R04_0_Pos)                          /*!< LCD PAL143: R04_0 Mask              */
#define LCD_PAL143_G04_0_Pos                                  5                                                         /*!< LCD PAL143: G04_0 Position          */
#define LCD_PAL143_G04_0_Msk                                  (0x1fUL << LCD_PAL143_G04_0_Pos)                          /*!< LCD PAL143: G04_0 Mask              */
#define LCD_PAL143_B04_0_Pos                                  10                                                        /*!< LCD PAL143: B04_0 Position          */
#define LCD_PAL143_B04_0_Msk                                  (0x1fUL << LCD_PAL143_B04_0_Pos)                          /*!< LCD PAL143: B04_0 Mask              */
#define LCD_PAL143_I0_Pos                                     15                                                        /*!< LCD PAL143: I0 Position             */
#define LCD_PAL143_I0_Msk                                     (0x01UL << LCD_PAL143_I0_Pos)                             /*!< LCD PAL143: I0 Mask                 */
#define LCD_PAL143_R14_0_Pos                                  16                                                        /*!< LCD PAL143: R14_0 Position          */
#define LCD_PAL143_R14_0_Msk                                  (0x1fUL << LCD_PAL143_R14_0_Pos)                          /*!< LCD PAL143: R14_0 Mask              */
#define LCD_PAL143_G14_0_Pos                                  21                                                        /*!< LCD PAL143: G14_0 Position          */
#define LCD_PAL143_G14_0_Msk                                  (0x1fUL << LCD_PAL143_G14_0_Pos)                          /*!< LCD PAL143: G14_0 Mask              */
#define LCD_PAL143_B14_0_Pos                                  26                                                        /*!< LCD PAL143: B14_0 Position          */
#define LCD_PAL143_B14_0_Msk                                  (0x1fUL << LCD_PAL143_B14_0_Pos)                          /*!< LCD PAL143: B14_0 Mask              */
#define LCD_PAL143_I1_Pos                                     31                                                        /*!< LCD PAL143: I1 Position             */
#define LCD_PAL143_I1_Msk                                     (0x01UL << LCD_PAL143_I1_Pos)                             /*!< LCD PAL143: I1 Mask                 */

// ---------------------------------------  LCD_PAL144  -------------------------------------------
#define LCD_PAL144_R04_0_Pos                                  0                                                         /*!< LCD PAL144: R04_0 Position          */
#define LCD_PAL144_R04_0_Msk                                  (0x1fUL << LCD_PAL144_R04_0_Pos)                          /*!< LCD PAL144: R04_0 Mask              */
#define LCD_PAL144_G04_0_Pos                                  5                                                         /*!< LCD PAL144: G04_0 Position          */
#define LCD_PAL144_G04_0_Msk                                  (0x1fUL << LCD_PAL144_G04_0_Pos)                          /*!< LCD PAL144: G04_0 Mask              */
#define LCD_PAL144_B04_0_Pos                                  10                                                        /*!< LCD PAL144: B04_0 Position          */
#define LCD_PAL144_B04_0_Msk                                  (0x1fUL << LCD_PAL144_B04_0_Pos)                          /*!< LCD PAL144: B04_0 Mask              */
#define LCD_PAL144_I0_Pos                                     15                                                        /*!< LCD PAL144: I0 Position             */
#define LCD_PAL144_I0_Msk                                     (0x01UL << LCD_PAL144_I0_Pos)                             /*!< LCD PAL144: I0 Mask                 */
#define LCD_PAL144_R14_0_Pos                                  16                                                        /*!< LCD PAL144: R14_0 Position          */
#define LCD_PAL144_R14_0_Msk                                  (0x1fUL << LCD_PAL144_R14_0_Pos)                          /*!< LCD PAL144: R14_0 Mask              */
#define LCD_PAL144_G14_0_Pos                                  21                                                        /*!< LCD PAL144: G14_0 Position          */
#define LCD_PAL144_G14_0_Msk                                  (0x1fUL << LCD_PAL144_G14_0_Pos)                          /*!< LCD PAL144: G14_0 Mask              */
#define LCD_PAL144_B14_0_Pos                                  26                                                        /*!< LCD PAL144: B14_0 Position          */
#define LCD_PAL144_B14_0_Msk                                  (0x1fUL << LCD_PAL144_B14_0_Pos)                          /*!< LCD PAL144: B14_0 Mask              */
#define LCD_PAL144_I1_Pos                                     31                                                        /*!< LCD PAL144: I1 Position             */
#define LCD_PAL144_I1_Msk                                     (0x01UL << LCD_PAL144_I1_Pos)                             /*!< LCD PAL144: I1 Mask                 */

// ---------------------------------------  LCD_PAL145  -------------------------------------------
#define LCD_PAL145_R04_0_Pos                                  0                                                         /*!< LCD PAL145: R04_0 Position          */
#define LCD_PAL145_R04_0_Msk                                  (0x1fUL << LCD_PAL145_R04_0_Pos)                          /*!< LCD PAL145: R04_0 Mask              */
#define LCD_PAL145_G04_0_Pos                                  5                                                         /*!< LCD PAL145: G04_0 Position          */
#define LCD_PAL145_G04_0_Msk                                  (0x1fUL << LCD_PAL145_G04_0_Pos)                          /*!< LCD PAL145: G04_0 Mask              */
#define LCD_PAL145_B04_0_Pos                                  10                                                        /*!< LCD PAL145: B04_0 Position          */
#define LCD_PAL145_B04_0_Msk                                  (0x1fUL << LCD_PAL145_B04_0_Pos)                          /*!< LCD PAL145: B04_0 Mask              */
#define LCD_PAL145_I0_Pos                                     15                                                        /*!< LCD PAL145: I0 Position             */
#define LCD_PAL145_I0_Msk                                     (0x01UL << LCD_PAL145_I0_Pos)                             /*!< LCD PAL145: I0 Mask                 */
#define LCD_PAL145_R14_0_Pos                                  16                                                        /*!< LCD PAL145: R14_0 Position          */
#define LCD_PAL145_R14_0_Msk                                  (0x1fUL << LCD_PAL145_R14_0_Pos)                          /*!< LCD PAL145: R14_0 Mask              */
#define LCD_PAL145_G14_0_Pos                                  21                                                        /*!< LCD PAL145: G14_0 Position          */
#define LCD_PAL145_G14_0_Msk                                  (0x1fUL << LCD_PAL145_G14_0_Pos)                          /*!< LCD PAL145: G14_0 Mask              */
#define LCD_PAL145_B14_0_Pos                                  26                                                        /*!< LCD PAL145: B14_0 Position          */
#define LCD_PAL145_B14_0_Msk                                  (0x1fUL << LCD_PAL145_B14_0_Pos)                          /*!< LCD PAL145: B14_0 Mask              */
#define LCD_PAL145_I1_Pos                                     31                                                        /*!< LCD PAL145: I1 Position             */
#define LCD_PAL145_I1_Msk                                     (0x01UL << LCD_PAL145_I1_Pos)                             /*!< LCD PAL145: I1 Mask                 */

// ---------------------------------------  LCD_PAL146  -------------------------------------------
#define LCD_PAL146_R04_0_Pos                                  0                                                         /*!< LCD PAL146: R04_0 Position          */
#define LCD_PAL146_R04_0_Msk                                  (0x1fUL << LCD_PAL146_R04_0_Pos)                          /*!< LCD PAL146: R04_0 Mask              */
#define LCD_PAL146_G04_0_Pos                                  5                                                         /*!< LCD PAL146: G04_0 Position          */
#define LCD_PAL146_G04_0_Msk                                  (0x1fUL << LCD_PAL146_G04_0_Pos)                          /*!< LCD PAL146: G04_0 Mask              */
#define LCD_PAL146_B04_0_Pos                                  10                                                        /*!< LCD PAL146: B04_0 Position          */
#define LCD_PAL146_B04_0_Msk                                  (0x1fUL << LCD_PAL146_B04_0_Pos)                          /*!< LCD PAL146: B04_0 Mask              */
#define LCD_PAL146_I0_Pos                                     15                                                        /*!< LCD PAL146: I0 Position             */
#define LCD_PAL146_I0_Msk                                     (0x01UL << LCD_PAL146_I0_Pos)                             /*!< LCD PAL146: I0 Mask                 */
#define LCD_PAL146_R14_0_Pos                                  16                                                        /*!< LCD PAL146: R14_0 Position          */
#define LCD_PAL146_R14_0_Msk                                  (0x1fUL << LCD_PAL146_R14_0_Pos)                          /*!< LCD PAL146: R14_0 Mask              */
#define LCD_PAL146_G14_0_Pos                                  21                                                        /*!< LCD PAL146: G14_0 Position          */
#define LCD_PAL146_G14_0_Msk                                  (0x1fUL << LCD_PAL146_G14_0_Pos)                          /*!< LCD PAL146: G14_0 Mask              */
#define LCD_PAL146_B14_0_Pos                                  26                                                        /*!< LCD PAL146: B14_0 Position          */
#define LCD_PAL146_B14_0_Msk                                  (0x1fUL << LCD_PAL146_B14_0_Pos)                          /*!< LCD PAL146: B14_0 Mask              */
#define LCD_PAL146_I1_Pos                                     31                                                        /*!< LCD PAL146: I1 Position             */
#define LCD_PAL146_I1_Msk                                     (0x01UL << LCD_PAL146_I1_Pos)                             /*!< LCD PAL146: I1 Mask                 */

// ---------------------------------------  LCD_PAL147  -------------------------------------------
#define LCD_PAL147_R04_0_Pos                                  0                                                         /*!< LCD PAL147: R04_0 Position          */
#define LCD_PAL147_R04_0_Msk                                  (0x1fUL << LCD_PAL147_R04_0_Pos)                          /*!< LCD PAL147: R04_0 Mask              */
#define LCD_PAL147_G04_0_Pos                                  5                                                         /*!< LCD PAL147: G04_0 Position          */
#define LCD_PAL147_G04_0_Msk                                  (0x1fUL << LCD_PAL147_G04_0_Pos)                          /*!< LCD PAL147: G04_0 Mask              */
#define LCD_PAL147_B04_0_Pos                                  10                                                        /*!< LCD PAL147: B04_0 Position          */
#define LCD_PAL147_B04_0_Msk                                  (0x1fUL << LCD_PAL147_B04_0_Pos)                          /*!< LCD PAL147: B04_0 Mask              */
#define LCD_PAL147_I0_Pos                                     15                                                        /*!< LCD PAL147: I0 Position             */
#define LCD_PAL147_I0_Msk                                     (0x01UL << LCD_PAL147_I0_Pos)                             /*!< LCD PAL147: I0 Mask                 */
#define LCD_PAL147_R14_0_Pos                                  16                                                        /*!< LCD PAL147: R14_0 Position          */
#define LCD_PAL147_R14_0_Msk                                  (0x1fUL << LCD_PAL147_R14_0_Pos)                          /*!< LCD PAL147: R14_0 Mask              */
#define LCD_PAL147_G14_0_Pos                                  21                                                        /*!< LCD PAL147: G14_0 Position          */
#define LCD_PAL147_G14_0_Msk                                  (0x1fUL << LCD_PAL147_G14_0_Pos)                          /*!< LCD PAL147: G14_0 Mask              */
#define LCD_PAL147_B14_0_Pos                                  26                                                        /*!< LCD PAL147: B14_0 Position          */
#define LCD_PAL147_B14_0_Msk                                  (0x1fUL << LCD_PAL147_B14_0_Pos)                          /*!< LCD PAL147: B14_0 Mask              */
#define LCD_PAL147_I1_Pos                                     31                                                        /*!< LCD PAL147: I1 Position             */
#define LCD_PAL147_I1_Msk                                     (0x01UL << LCD_PAL147_I1_Pos)                             /*!< LCD PAL147: I1 Mask                 */

// ---------------------------------------  LCD_PAL148  -------------------------------------------
#define LCD_PAL148_R04_0_Pos                                  0                                                         /*!< LCD PAL148: R04_0 Position          */
#define LCD_PAL148_R04_0_Msk                                  (0x1fUL << LCD_PAL148_R04_0_Pos)                          /*!< LCD PAL148: R04_0 Mask              */
#define LCD_PAL148_G04_0_Pos                                  5                                                         /*!< LCD PAL148: G04_0 Position          */
#define LCD_PAL148_G04_0_Msk                                  (0x1fUL << LCD_PAL148_G04_0_Pos)                          /*!< LCD PAL148: G04_0 Mask              */
#define LCD_PAL148_B04_0_Pos                                  10                                                        /*!< LCD PAL148: B04_0 Position          */
#define LCD_PAL148_B04_0_Msk                                  (0x1fUL << LCD_PAL148_B04_0_Pos)                          /*!< LCD PAL148: B04_0 Mask              */
#define LCD_PAL148_I0_Pos                                     15                                                        /*!< LCD PAL148: I0 Position             */
#define LCD_PAL148_I0_Msk                                     (0x01UL << LCD_PAL148_I0_Pos)                             /*!< LCD PAL148: I0 Mask                 */
#define LCD_PAL148_R14_0_Pos                                  16                                                        /*!< LCD PAL148: R14_0 Position          */
#define LCD_PAL148_R14_0_Msk                                  (0x1fUL << LCD_PAL148_R14_0_Pos)                          /*!< LCD PAL148: R14_0 Mask              */
#define LCD_PAL148_G14_0_Pos                                  21                                                        /*!< LCD PAL148: G14_0 Position          */
#define LCD_PAL148_G14_0_Msk                                  (0x1fUL << LCD_PAL148_G14_0_Pos)                          /*!< LCD PAL148: G14_0 Mask              */
#define LCD_PAL148_B14_0_Pos                                  26                                                        /*!< LCD PAL148: B14_0 Position          */
#define LCD_PAL148_B14_0_Msk                                  (0x1fUL << LCD_PAL148_B14_0_Pos)                          /*!< LCD PAL148: B14_0 Mask              */
#define LCD_PAL148_I1_Pos                                     31                                                        /*!< LCD PAL148: I1 Position             */
#define LCD_PAL148_I1_Msk                                     (0x01UL << LCD_PAL148_I1_Pos)                             /*!< LCD PAL148: I1 Mask                 */

// ---------------------------------------  LCD_PAL149  -------------------------------------------
#define LCD_PAL149_R04_0_Pos                                  0                                                         /*!< LCD PAL149: R04_0 Position          */
#define LCD_PAL149_R04_0_Msk                                  (0x1fUL << LCD_PAL149_R04_0_Pos)                          /*!< LCD PAL149: R04_0 Mask              */
#define LCD_PAL149_G04_0_Pos                                  5                                                         /*!< LCD PAL149: G04_0 Position          */
#define LCD_PAL149_G04_0_Msk                                  (0x1fUL << LCD_PAL149_G04_0_Pos)                          /*!< LCD PAL149: G04_0 Mask              */
#define LCD_PAL149_B04_0_Pos                                  10                                                        /*!< LCD PAL149: B04_0 Position          */
#define LCD_PAL149_B04_0_Msk                                  (0x1fUL << LCD_PAL149_B04_0_Pos)                          /*!< LCD PAL149: B04_0 Mask              */
#define LCD_PAL149_I0_Pos                                     15                                                        /*!< LCD PAL149: I0 Position             */
#define LCD_PAL149_I0_Msk                                     (0x01UL << LCD_PAL149_I0_Pos)                             /*!< LCD PAL149: I0 Mask                 */
#define LCD_PAL149_R14_0_Pos                                  16                                                        /*!< LCD PAL149: R14_0 Position          */
#define LCD_PAL149_R14_0_Msk                                  (0x1fUL << LCD_PAL149_R14_0_Pos)                          /*!< LCD PAL149: R14_0 Mask              */
#define LCD_PAL149_G14_0_Pos                                  21                                                        /*!< LCD PAL149: G14_0 Position          */
#define LCD_PAL149_G14_0_Msk                                  (0x1fUL << LCD_PAL149_G14_0_Pos)                          /*!< LCD PAL149: G14_0 Mask              */
#define LCD_PAL149_B14_0_Pos                                  26                                                        /*!< LCD PAL149: B14_0 Position          */
#define LCD_PAL149_B14_0_Msk                                  (0x1fUL << LCD_PAL149_B14_0_Pos)                          /*!< LCD PAL149: B14_0 Mask              */
#define LCD_PAL149_I1_Pos                                     31                                                        /*!< LCD PAL149: I1 Position             */
#define LCD_PAL149_I1_Msk                                     (0x01UL << LCD_PAL149_I1_Pos)                             /*!< LCD PAL149: I1 Mask                 */

// ---------------------------------------  LCD_PAL150  -------------------------------------------
#define LCD_PAL150_R04_0_Pos                                  0                                                         /*!< LCD PAL150: R04_0 Position          */
#define LCD_PAL150_R04_0_Msk                                  (0x1fUL << LCD_PAL150_R04_0_Pos)                          /*!< LCD PAL150: R04_0 Mask              */
#define LCD_PAL150_G04_0_Pos                                  5                                                         /*!< LCD PAL150: G04_0 Position          */
#define LCD_PAL150_G04_0_Msk                                  (0x1fUL << LCD_PAL150_G04_0_Pos)                          /*!< LCD PAL150: G04_0 Mask              */
#define LCD_PAL150_B04_0_Pos                                  10                                                        /*!< LCD PAL150: B04_0 Position          */
#define LCD_PAL150_B04_0_Msk                                  (0x1fUL << LCD_PAL150_B04_0_Pos)                          /*!< LCD PAL150: B04_0 Mask              */
#define LCD_PAL150_I0_Pos                                     15                                                        /*!< LCD PAL150: I0 Position             */
#define LCD_PAL150_I0_Msk                                     (0x01UL << LCD_PAL150_I0_Pos)                             /*!< LCD PAL150: I0 Mask                 */
#define LCD_PAL150_R14_0_Pos                                  16                                                        /*!< LCD PAL150: R14_0 Position          */
#define LCD_PAL150_R14_0_Msk                                  (0x1fUL << LCD_PAL150_R14_0_Pos)                          /*!< LCD PAL150: R14_0 Mask              */
#define LCD_PAL150_G14_0_Pos                                  21                                                        /*!< LCD PAL150: G14_0 Position          */
#define LCD_PAL150_G14_0_Msk                                  (0x1fUL << LCD_PAL150_G14_0_Pos)                          /*!< LCD PAL150: G14_0 Mask              */
#define LCD_PAL150_B14_0_Pos                                  26                                                        /*!< LCD PAL150: B14_0 Position          */
#define LCD_PAL150_B14_0_Msk                                  (0x1fUL << LCD_PAL150_B14_0_Pos)                          /*!< LCD PAL150: B14_0 Mask              */
#define LCD_PAL150_I1_Pos                                     31                                                        /*!< LCD PAL150: I1 Position             */
#define LCD_PAL150_I1_Msk                                     (0x01UL << LCD_PAL150_I1_Pos)                             /*!< LCD PAL150: I1 Mask                 */

// ---------------------------------------  LCD_PAL151  -------------------------------------------
#define LCD_PAL151_R04_0_Pos                                  0                                                         /*!< LCD PAL151: R04_0 Position          */
#define LCD_PAL151_R04_0_Msk                                  (0x1fUL << LCD_PAL151_R04_0_Pos)                          /*!< LCD PAL151: R04_0 Mask              */
#define LCD_PAL151_G04_0_Pos                                  5                                                         /*!< LCD PAL151: G04_0 Position          */
#define LCD_PAL151_G04_0_Msk                                  (0x1fUL << LCD_PAL151_G04_0_Pos)                          /*!< LCD PAL151: G04_0 Mask              */
#define LCD_PAL151_B04_0_Pos                                  10                                                        /*!< LCD PAL151: B04_0 Position          */
#define LCD_PAL151_B04_0_Msk                                  (0x1fUL << LCD_PAL151_B04_0_Pos)                          /*!< LCD PAL151: B04_0 Mask              */
#define LCD_PAL151_I0_Pos                                     15                                                        /*!< LCD PAL151: I0 Position             */
#define LCD_PAL151_I0_Msk                                     (0x01UL << LCD_PAL151_I0_Pos)                             /*!< LCD PAL151: I0 Mask                 */
#define LCD_PAL151_R14_0_Pos                                  16                                                        /*!< LCD PAL151: R14_0 Position          */
#define LCD_PAL151_R14_0_Msk                                  (0x1fUL << LCD_PAL151_R14_0_Pos)                          /*!< LCD PAL151: R14_0 Mask              */
#define LCD_PAL151_G14_0_Pos                                  21                                                        /*!< LCD PAL151: G14_0 Position          */
#define LCD_PAL151_G14_0_Msk                                  (0x1fUL << LCD_PAL151_G14_0_Pos)                          /*!< LCD PAL151: G14_0 Mask              */
#define LCD_PAL151_B14_0_Pos                                  26                                                        /*!< LCD PAL151: B14_0 Position          */
#define LCD_PAL151_B14_0_Msk                                  (0x1fUL << LCD_PAL151_B14_0_Pos)                          /*!< LCD PAL151: B14_0 Mask              */
#define LCD_PAL151_I1_Pos                                     31                                                        /*!< LCD PAL151: I1 Position             */
#define LCD_PAL151_I1_Msk                                     (0x01UL << LCD_PAL151_I1_Pos)                             /*!< LCD PAL151: I1 Mask                 */

// ---------------------------------------  LCD_PAL152  -------------------------------------------
#define LCD_PAL152_R04_0_Pos                                  0                                                         /*!< LCD PAL152: R04_0 Position          */
#define LCD_PAL152_R04_0_Msk                                  (0x1fUL << LCD_PAL152_R04_0_Pos)                          /*!< LCD PAL152: R04_0 Mask              */
#define LCD_PAL152_G04_0_Pos                                  5                                                         /*!< LCD PAL152: G04_0 Position          */
#define LCD_PAL152_G04_0_Msk                                  (0x1fUL << LCD_PAL152_G04_0_Pos)                          /*!< LCD PAL152: G04_0 Mask              */
#define LCD_PAL152_B04_0_Pos                                  10                                                        /*!< LCD PAL152: B04_0 Position          */
#define LCD_PAL152_B04_0_Msk                                  (0x1fUL << LCD_PAL152_B04_0_Pos)                          /*!< LCD PAL152: B04_0 Mask              */
#define LCD_PAL152_I0_Pos                                     15                                                        /*!< LCD PAL152: I0 Position             */
#define LCD_PAL152_I0_Msk                                     (0x01UL << LCD_PAL152_I0_Pos)                             /*!< LCD PAL152: I0 Mask                 */
#define LCD_PAL152_R14_0_Pos                                  16                                                        /*!< LCD PAL152: R14_0 Position          */
#define LCD_PAL152_R14_0_Msk                                  (0x1fUL << LCD_PAL152_R14_0_Pos)                          /*!< LCD PAL152: R14_0 Mask              */
#define LCD_PAL152_G14_0_Pos                                  21                                                        /*!< LCD PAL152: G14_0 Position          */
#define LCD_PAL152_G14_0_Msk                                  (0x1fUL << LCD_PAL152_G14_0_Pos)                          /*!< LCD PAL152: G14_0 Mask              */
#define LCD_PAL152_B14_0_Pos                                  26                                                        /*!< LCD PAL152: B14_0 Position          */
#define LCD_PAL152_B14_0_Msk                                  (0x1fUL << LCD_PAL152_B14_0_Pos)                          /*!< LCD PAL152: B14_0 Mask              */
#define LCD_PAL152_I1_Pos                                     31                                                        /*!< LCD PAL152: I1 Position             */
#define LCD_PAL152_I1_Msk                                     (0x01UL << LCD_PAL152_I1_Pos)                             /*!< LCD PAL152: I1 Mask                 */

// ---------------------------------------  LCD_PAL153  -------------------------------------------
#define LCD_PAL153_R04_0_Pos                                  0                                                         /*!< LCD PAL153: R04_0 Position          */
#define LCD_PAL153_R04_0_Msk                                  (0x1fUL << LCD_PAL153_R04_0_Pos)                          /*!< LCD PAL153: R04_0 Mask              */
#define LCD_PAL153_G04_0_Pos                                  5                                                         /*!< LCD PAL153: G04_0 Position          */
#define LCD_PAL153_G04_0_Msk                                  (0x1fUL << LCD_PAL153_G04_0_Pos)                          /*!< LCD PAL153: G04_0 Mask              */
#define LCD_PAL153_B04_0_Pos                                  10                                                        /*!< LCD PAL153: B04_0 Position          */
#define LCD_PAL153_B04_0_Msk                                  (0x1fUL << LCD_PAL153_B04_0_Pos)                          /*!< LCD PAL153: B04_0 Mask              */
#define LCD_PAL153_I0_Pos                                     15                                                        /*!< LCD PAL153: I0 Position             */
#define LCD_PAL153_I0_Msk                                     (0x01UL << LCD_PAL153_I0_Pos)                             /*!< LCD PAL153: I0 Mask                 */
#define LCD_PAL153_R14_0_Pos                                  16                                                        /*!< LCD PAL153: R14_0 Position          */
#define LCD_PAL153_R14_0_Msk                                  (0x1fUL << LCD_PAL153_R14_0_Pos)                          /*!< LCD PAL153: R14_0 Mask              */
#define LCD_PAL153_G14_0_Pos                                  21                                                        /*!< LCD PAL153: G14_0 Position          */
#define LCD_PAL153_G14_0_Msk                                  (0x1fUL << LCD_PAL153_G14_0_Pos)                          /*!< LCD PAL153: G14_0 Mask              */
#define LCD_PAL153_B14_0_Pos                                  26                                                        /*!< LCD PAL153: B14_0 Position          */
#define LCD_PAL153_B14_0_Msk                                  (0x1fUL << LCD_PAL153_B14_0_Pos)                          /*!< LCD PAL153: B14_0 Mask              */
#define LCD_PAL153_I1_Pos                                     31                                                        /*!< LCD PAL153: I1 Position             */
#define LCD_PAL153_I1_Msk                                     (0x01UL << LCD_PAL153_I1_Pos)                             /*!< LCD PAL153: I1 Mask                 */

// ---------------------------------------  LCD_PAL154  -------------------------------------------
#define LCD_PAL154_R04_0_Pos                                  0                                                         /*!< LCD PAL154: R04_0 Position          */
#define LCD_PAL154_R04_0_Msk                                  (0x1fUL << LCD_PAL154_R04_0_Pos)                          /*!< LCD PAL154: R04_0 Mask              */
#define LCD_PAL154_G04_0_Pos                                  5                                                         /*!< LCD PAL154: G04_0 Position          */
#define LCD_PAL154_G04_0_Msk                                  (0x1fUL << LCD_PAL154_G04_0_Pos)                          /*!< LCD PAL154: G04_0 Mask              */
#define LCD_PAL154_B04_0_Pos                                  10                                                        /*!< LCD PAL154: B04_0 Position          */
#define LCD_PAL154_B04_0_Msk                                  (0x1fUL << LCD_PAL154_B04_0_Pos)                          /*!< LCD PAL154: B04_0 Mask              */
#define LCD_PAL154_I0_Pos                                     15                                                        /*!< LCD PAL154: I0 Position             */
#define LCD_PAL154_I0_Msk                                     (0x01UL << LCD_PAL154_I0_Pos)                             /*!< LCD PAL154: I0 Mask                 */
#define LCD_PAL154_R14_0_Pos                                  16                                                        /*!< LCD PAL154: R14_0 Position          */
#define LCD_PAL154_R14_0_Msk                                  (0x1fUL << LCD_PAL154_R14_0_Pos)                          /*!< LCD PAL154: R14_0 Mask              */
#define LCD_PAL154_G14_0_Pos                                  21                                                        /*!< LCD PAL154: G14_0 Position          */
#define LCD_PAL154_G14_0_Msk                                  (0x1fUL << LCD_PAL154_G14_0_Pos)                          /*!< LCD PAL154: G14_0 Mask              */
#define LCD_PAL154_B14_0_Pos                                  26                                                        /*!< LCD PAL154: B14_0 Position          */
#define LCD_PAL154_B14_0_Msk                                  (0x1fUL << LCD_PAL154_B14_0_Pos)                          /*!< LCD PAL154: B14_0 Mask              */
#define LCD_PAL154_I1_Pos                                     31                                                        /*!< LCD PAL154: I1 Position             */
#define LCD_PAL154_I1_Msk                                     (0x01UL << LCD_PAL154_I1_Pos)                             /*!< LCD PAL154: I1 Mask                 */

// ---------------------------------------  LCD_PAL155  -------------------------------------------
#define LCD_PAL155_R04_0_Pos                                  0                                                         /*!< LCD PAL155: R04_0 Position          */
#define LCD_PAL155_R04_0_Msk                                  (0x1fUL << LCD_PAL155_R04_0_Pos)                          /*!< LCD PAL155: R04_0 Mask              */
#define LCD_PAL155_G04_0_Pos                                  5                                                         /*!< LCD PAL155: G04_0 Position          */
#define LCD_PAL155_G04_0_Msk                                  (0x1fUL << LCD_PAL155_G04_0_Pos)                          /*!< LCD PAL155: G04_0 Mask              */
#define LCD_PAL155_B04_0_Pos                                  10                                                        /*!< LCD PAL155: B04_0 Position          */
#define LCD_PAL155_B04_0_Msk                                  (0x1fUL << LCD_PAL155_B04_0_Pos)                          /*!< LCD PAL155: B04_0 Mask              */
#define LCD_PAL155_I0_Pos                                     15                                                        /*!< LCD PAL155: I0 Position             */
#define LCD_PAL155_I0_Msk                                     (0x01UL << LCD_PAL155_I0_Pos)                             /*!< LCD PAL155: I0 Mask                 */
#define LCD_PAL155_R14_0_Pos                                  16                                                        /*!< LCD PAL155: R14_0 Position          */
#define LCD_PAL155_R14_0_Msk                                  (0x1fUL << LCD_PAL155_R14_0_Pos)                          /*!< LCD PAL155: R14_0 Mask              */
#define LCD_PAL155_G14_0_Pos                                  21                                                        /*!< LCD PAL155: G14_0 Position          */
#define LCD_PAL155_G14_0_Msk                                  (0x1fUL << LCD_PAL155_G14_0_Pos)                          /*!< LCD PAL155: G14_0 Mask              */
#define LCD_PAL155_B14_0_Pos                                  26                                                        /*!< LCD PAL155: B14_0 Position          */
#define LCD_PAL155_B14_0_Msk                                  (0x1fUL << LCD_PAL155_B14_0_Pos)                          /*!< LCD PAL155: B14_0 Mask              */
#define LCD_PAL155_I1_Pos                                     31                                                        /*!< LCD PAL155: I1 Position             */
#define LCD_PAL155_I1_Msk                                     (0x01UL << LCD_PAL155_I1_Pos)                             /*!< LCD PAL155: I1 Mask                 */

// ---------------------------------------  LCD_PAL156  -------------------------------------------
#define LCD_PAL156_R04_0_Pos                                  0                                                         /*!< LCD PAL156: R04_0 Position          */
#define LCD_PAL156_R04_0_Msk                                  (0x1fUL << LCD_PAL156_R04_0_Pos)                          /*!< LCD PAL156: R04_0 Mask              */
#define LCD_PAL156_G04_0_Pos                                  5                                                         /*!< LCD PAL156: G04_0 Position          */
#define LCD_PAL156_G04_0_Msk                                  (0x1fUL << LCD_PAL156_G04_0_Pos)                          /*!< LCD PAL156: G04_0 Mask              */
#define LCD_PAL156_B04_0_Pos                                  10                                                        /*!< LCD PAL156: B04_0 Position          */
#define LCD_PAL156_B04_0_Msk                                  (0x1fUL << LCD_PAL156_B04_0_Pos)                          /*!< LCD PAL156: B04_0 Mask              */
#define LCD_PAL156_I0_Pos                                     15                                                        /*!< LCD PAL156: I0 Position             */
#define LCD_PAL156_I0_Msk                                     (0x01UL << LCD_PAL156_I0_Pos)                             /*!< LCD PAL156: I0 Mask                 */
#define LCD_PAL156_R14_0_Pos                                  16                                                        /*!< LCD PAL156: R14_0 Position          */
#define LCD_PAL156_R14_0_Msk                                  (0x1fUL << LCD_PAL156_R14_0_Pos)                          /*!< LCD PAL156: R14_0 Mask              */
#define LCD_PAL156_G14_0_Pos                                  21                                                        /*!< LCD PAL156: G14_0 Position          */
#define LCD_PAL156_G14_0_Msk                                  (0x1fUL << LCD_PAL156_G14_0_Pos)                          /*!< LCD PAL156: G14_0 Mask              */
#define LCD_PAL156_B14_0_Pos                                  26                                                        /*!< LCD PAL156: B14_0 Position          */
#define LCD_PAL156_B14_0_Msk                                  (0x1fUL << LCD_PAL156_B14_0_Pos)                          /*!< LCD PAL156: B14_0 Mask              */
#define LCD_PAL156_I1_Pos                                     31                                                        /*!< LCD PAL156: I1 Position             */
#define LCD_PAL156_I1_Msk                                     (0x01UL << LCD_PAL156_I1_Pos)                             /*!< LCD PAL156: I1 Mask                 */

// ---------------------------------------  LCD_PAL157  -------------------------------------------
#define LCD_PAL157_R04_0_Pos                                  0                                                         /*!< LCD PAL157: R04_0 Position          */
#define LCD_PAL157_R04_0_Msk                                  (0x1fUL << LCD_PAL157_R04_0_Pos)                          /*!< LCD PAL157: R04_0 Mask              */
#define LCD_PAL157_G04_0_Pos                                  5                                                         /*!< LCD PAL157: G04_0 Position          */
#define LCD_PAL157_G04_0_Msk                                  (0x1fUL << LCD_PAL157_G04_0_Pos)                          /*!< LCD PAL157: G04_0 Mask              */
#define LCD_PAL157_B04_0_Pos                                  10                                                        /*!< LCD PAL157: B04_0 Position          */
#define LCD_PAL157_B04_0_Msk                                  (0x1fUL << LCD_PAL157_B04_0_Pos)                          /*!< LCD PAL157: B04_0 Mask              */
#define LCD_PAL157_I0_Pos                                     15                                                        /*!< LCD PAL157: I0 Position             */
#define LCD_PAL157_I0_Msk                                     (0x01UL << LCD_PAL157_I0_Pos)                             /*!< LCD PAL157: I0 Mask                 */
#define LCD_PAL157_R14_0_Pos                                  16                                                        /*!< LCD PAL157: R14_0 Position          */
#define LCD_PAL157_R14_0_Msk                                  (0x1fUL << LCD_PAL157_R14_0_Pos)                          /*!< LCD PAL157: R14_0 Mask              */
#define LCD_PAL157_G14_0_Pos                                  21                                                        /*!< LCD PAL157: G14_0 Position          */
#define LCD_PAL157_G14_0_Msk                                  (0x1fUL << LCD_PAL157_G14_0_Pos)                          /*!< LCD PAL157: G14_0 Mask              */
#define LCD_PAL157_B14_0_Pos                                  26                                                        /*!< LCD PAL157: B14_0 Position          */
#define LCD_PAL157_B14_0_Msk                                  (0x1fUL << LCD_PAL157_B14_0_Pos)                          /*!< LCD PAL157: B14_0 Mask              */
#define LCD_PAL157_I1_Pos                                     31                                                        /*!< LCD PAL157: I1 Position             */
#define LCD_PAL157_I1_Msk                                     (0x01UL << LCD_PAL157_I1_Pos)                             /*!< LCD PAL157: I1 Mask                 */

// ---------------------------------------  LCD_PAL158  -------------------------------------------
#define LCD_PAL158_R04_0_Pos                                  0                                                         /*!< LCD PAL158: R04_0 Position          */
#define LCD_PAL158_R04_0_Msk                                  (0x1fUL << LCD_PAL158_R04_0_Pos)                          /*!< LCD PAL158: R04_0 Mask              */
#define LCD_PAL158_G04_0_Pos                                  5                                                         /*!< LCD PAL158: G04_0 Position          */
#define LCD_PAL158_G04_0_Msk                                  (0x1fUL << LCD_PAL158_G04_0_Pos)                          /*!< LCD PAL158: G04_0 Mask              */
#define LCD_PAL158_B04_0_Pos                                  10                                                        /*!< LCD PAL158: B04_0 Position          */
#define LCD_PAL158_B04_0_Msk                                  (0x1fUL << LCD_PAL158_B04_0_Pos)                          /*!< LCD PAL158: B04_0 Mask              */
#define LCD_PAL158_I0_Pos                                     15                                                        /*!< LCD PAL158: I0 Position             */
#define LCD_PAL158_I0_Msk                                     (0x01UL << LCD_PAL158_I0_Pos)                             /*!< LCD PAL158: I0 Mask                 */
#define LCD_PAL158_R14_0_Pos                                  16                                                        /*!< LCD PAL158: R14_0 Position          */
#define LCD_PAL158_R14_0_Msk                                  (0x1fUL << LCD_PAL158_R14_0_Pos)                          /*!< LCD PAL158: R14_0 Mask              */
#define LCD_PAL158_G14_0_Pos                                  21                                                        /*!< LCD PAL158: G14_0 Position          */
#define LCD_PAL158_G14_0_Msk                                  (0x1fUL << LCD_PAL158_G14_0_Pos)                          /*!< LCD PAL158: G14_0 Mask              */
#define LCD_PAL158_B14_0_Pos                                  26                                                        /*!< LCD PAL158: B14_0 Position          */
#define LCD_PAL158_B14_0_Msk                                  (0x1fUL << LCD_PAL158_B14_0_Pos)                          /*!< LCD PAL158: B14_0 Mask              */
#define LCD_PAL158_I1_Pos                                     31                                                        /*!< LCD PAL158: I1 Position             */
#define LCD_PAL158_I1_Msk                                     (0x01UL << LCD_PAL158_I1_Pos)                             /*!< LCD PAL158: I1 Mask                 */

// ---------------------------------------  LCD_PAL159  -------------------------------------------
#define LCD_PAL159_R04_0_Pos                                  0                                                         /*!< LCD PAL159: R04_0 Position          */
#define LCD_PAL159_R04_0_Msk                                  (0x1fUL << LCD_PAL159_R04_0_Pos)                          /*!< LCD PAL159: R04_0 Mask              */
#define LCD_PAL159_G04_0_Pos                                  5                                                         /*!< LCD PAL159: G04_0 Position          */
#define LCD_PAL159_G04_0_Msk                                  (0x1fUL << LCD_PAL159_G04_0_Pos)                          /*!< LCD PAL159: G04_0 Mask              */
#define LCD_PAL159_B04_0_Pos                                  10                                                        /*!< LCD PAL159: B04_0 Position          */
#define LCD_PAL159_B04_0_Msk                                  (0x1fUL << LCD_PAL159_B04_0_Pos)                          /*!< LCD PAL159: B04_0 Mask              */
#define LCD_PAL159_I0_Pos                                     15                                                        /*!< LCD PAL159: I0 Position             */
#define LCD_PAL159_I0_Msk                                     (0x01UL << LCD_PAL159_I0_Pos)                             /*!< LCD PAL159: I0 Mask                 */
#define LCD_PAL159_R14_0_Pos                                  16                                                        /*!< LCD PAL159: R14_0 Position          */
#define LCD_PAL159_R14_0_Msk                                  (0x1fUL << LCD_PAL159_R14_0_Pos)                          /*!< LCD PAL159: R14_0 Mask              */
#define LCD_PAL159_G14_0_Pos                                  21                                                        /*!< LCD PAL159: G14_0 Position          */
#define LCD_PAL159_G14_0_Msk                                  (0x1fUL << LCD_PAL159_G14_0_Pos)                          /*!< LCD PAL159: G14_0 Mask              */
#define LCD_PAL159_B14_0_Pos                                  26                                                        /*!< LCD PAL159: B14_0 Position          */
#define LCD_PAL159_B14_0_Msk                                  (0x1fUL << LCD_PAL159_B14_0_Pos)                          /*!< LCD PAL159: B14_0 Mask              */
#define LCD_PAL159_I1_Pos                                     31                                                        /*!< LCD PAL159: I1 Position             */
#define LCD_PAL159_I1_Msk                                     (0x01UL << LCD_PAL159_I1_Pos)                             /*!< LCD PAL159: I1 Mask                 */

// ---------------------------------------  LCD_PAL160  -------------------------------------------
#define LCD_PAL160_R04_0_Pos                                  0                                                         /*!< LCD PAL160: R04_0 Position          */
#define LCD_PAL160_R04_0_Msk                                  (0x1fUL << LCD_PAL160_R04_0_Pos)                          /*!< LCD PAL160: R04_0 Mask              */
#define LCD_PAL160_G04_0_Pos                                  5                                                         /*!< LCD PAL160: G04_0 Position          */
#define LCD_PAL160_G04_0_Msk                                  (0x1fUL << LCD_PAL160_G04_0_Pos)                          /*!< LCD PAL160: G04_0 Mask              */
#define LCD_PAL160_B04_0_Pos                                  10                                                        /*!< LCD PAL160: B04_0 Position          */
#define LCD_PAL160_B04_0_Msk                                  (0x1fUL << LCD_PAL160_B04_0_Pos)                          /*!< LCD PAL160: B04_0 Mask              */
#define LCD_PAL160_I0_Pos                                     15                                                        /*!< LCD PAL160: I0 Position             */
#define LCD_PAL160_I0_Msk                                     (0x01UL << LCD_PAL160_I0_Pos)                             /*!< LCD PAL160: I0 Mask                 */
#define LCD_PAL160_R14_0_Pos                                  16                                                        /*!< LCD PAL160: R14_0 Position          */
#define LCD_PAL160_R14_0_Msk                                  (0x1fUL << LCD_PAL160_R14_0_Pos)                          /*!< LCD PAL160: R14_0 Mask              */
#define LCD_PAL160_G14_0_Pos                                  21                                                        /*!< LCD PAL160: G14_0 Position          */
#define LCD_PAL160_G14_0_Msk                                  (0x1fUL << LCD_PAL160_G14_0_Pos)                          /*!< LCD PAL160: G14_0 Mask              */
#define LCD_PAL160_B14_0_Pos                                  26                                                        /*!< LCD PAL160: B14_0 Position          */
#define LCD_PAL160_B14_0_Msk                                  (0x1fUL << LCD_PAL160_B14_0_Pos)                          /*!< LCD PAL160: B14_0 Mask              */
#define LCD_PAL160_I1_Pos                                     31                                                        /*!< LCD PAL160: I1 Position             */
#define LCD_PAL160_I1_Msk                                     (0x01UL << LCD_PAL160_I1_Pos)                             /*!< LCD PAL160: I1 Mask                 */

// ---------------------------------------  LCD_PAL161  -------------------------------------------
#define LCD_PAL161_R04_0_Pos                                  0                                                         /*!< LCD PAL161: R04_0 Position          */
#define LCD_PAL161_R04_0_Msk                                  (0x1fUL << LCD_PAL161_R04_0_Pos)                          /*!< LCD PAL161: R04_0 Mask              */
#define LCD_PAL161_G04_0_Pos                                  5                                                         /*!< LCD PAL161: G04_0 Position          */
#define LCD_PAL161_G04_0_Msk                                  (0x1fUL << LCD_PAL161_G04_0_Pos)                          /*!< LCD PAL161: G04_0 Mask              */
#define LCD_PAL161_B04_0_Pos                                  10                                                        /*!< LCD PAL161: B04_0 Position          */
#define LCD_PAL161_B04_0_Msk                                  (0x1fUL << LCD_PAL161_B04_0_Pos)                          /*!< LCD PAL161: B04_0 Mask              */
#define LCD_PAL161_I0_Pos                                     15                                                        /*!< LCD PAL161: I0 Position             */
#define LCD_PAL161_I0_Msk                                     (0x01UL << LCD_PAL161_I0_Pos)                             /*!< LCD PAL161: I0 Mask                 */
#define LCD_PAL161_R14_0_Pos                                  16                                                        /*!< LCD PAL161: R14_0 Position          */
#define LCD_PAL161_R14_0_Msk                                  (0x1fUL << LCD_PAL161_R14_0_Pos)                          /*!< LCD PAL161: R14_0 Mask              */
#define LCD_PAL161_G14_0_Pos                                  21                                                        /*!< LCD PAL161: G14_0 Position          */
#define LCD_PAL161_G14_0_Msk                                  (0x1fUL << LCD_PAL161_G14_0_Pos)                          /*!< LCD PAL161: G14_0 Mask              */
#define LCD_PAL161_B14_0_Pos                                  26                                                        /*!< LCD PAL161: B14_0 Position          */
#define LCD_PAL161_B14_0_Msk                                  (0x1fUL << LCD_PAL161_B14_0_Pos)                          /*!< LCD PAL161: B14_0 Mask              */
#define LCD_PAL161_I1_Pos                                     31                                                        /*!< LCD PAL161: I1 Position             */
#define LCD_PAL161_I1_Msk                                     (0x01UL << LCD_PAL161_I1_Pos)                             /*!< LCD PAL161: I1 Mask                 */

// ---------------------------------------  LCD_PAL162  -------------------------------------------
#define LCD_PAL162_R04_0_Pos                                  0                                                         /*!< LCD PAL162: R04_0 Position          */
#define LCD_PAL162_R04_0_Msk                                  (0x1fUL << LCD_PAL162_R04_0_Pos)                          /*!< LCD PAL162: R04_0 Mask              */
#define LCD_PAL162_G04_0_Pos                                  5                                                         /*!< LCD PAL162: G04_0 Position          */
#define LCD_PAL162_G04_0_Msk                                  (0x1fUL << LCD_PAL162_G04_0_Pos)                          /*!< LCD PAL162: G04_0 Mask              */
#define LCD_PAL162_B04_0_Pos                                  10                                                        /*!< LCD PAL162: B04_0 Position          */
#define LCD_PAL162_B04_0_Msk                                  (0x1fUL << LCD_PAL162_B04_0_Pos)                          /*!< LCD PAL162: B04_0 Mask              */
#define LCD_PAL162_I0_Pos                                     15                                                        /*!< LCD PAL162: I0 Position             */
#define LCD_PAL162_I0_Msk                                     (0x01UL << LCD_PAL162_I0_Pos)                             /*!< LCD PAL162: I0 Mask                 */
#define LCD_PAL162_R14_0_Pos                                  16                                                        /*!< LCD PAL162: R14_0 Position          */
#define LCD_PAL162_R14_0_Msk                                  (0x1fUL << LCD_PAL162_R14_0_Pos)                          /*!< LCD PAL162: R14_0 Mask              */
#define LCD_PAL162_G14_0_Pos                                  21                                                        /*!< LCD PAL162: G14_0 Position          */
#define LCD_PAL162_G14_0_Msk                                  (0x1fUL << LCD_PAL162_G14_0_Pos)                          /*!< LCD PAL162: G14_0 Mask              */
#define LCD_PAL162_B14_0_Pos                                  26                                                        /*!< LCD PAL162: B14_0 Position          */
#define LCD_PAL162_B14_0_Msk                                  (0x1fUL << LCD_PAL162_B14_0_Pos)                          /*!< LCD PAL162: B14_0 Mask              */
#define LCD_PAL162_I1_Pos                                     31                                                        /*!< LCD PAL162: I1 Position             */
#define LCD_PAL162_I1_Msk                                     (0x01UL << LCD_PAL162_I1_Pos)                             /*!< LCD PAL162: I1 Mask                 */

// ---------------------------------------  LCD_PAL163  -------------------------------------------
#define LCD_PAL163_R04_0_Pos                                  0                                                         /*!< LCD PAL163: R04_0 Position          */
#define LCD_PAL163_R04_0_Msk                                  (0x1fUL << LCD_PAL163_R04_0_Pos)                          /*!< LCD PAL163: R04_0 Mask              */
#define LCD_PAL163_G04_0_Pos                                  5                                                         /*!< LCD PAL163: G04_0 Position          */
#define LCD_PAL163_G04_0_Msk                                  (0x1fUL << LCD_PAL163_G04_0_Pos)                          /*!< LCD PAL163: G04_0 Mask              */
#define LCD_PAL163_B04_0_Pos                                  10                                                        /*!< LCD PAL163: B04_0 Position          */
#define LCD_PAL163_B04_0_Msk                                  (0x1fUL << LCD_PAL163_B04_0_Pos)                          /*!< LCD PAL163: B04_0 Mask              */
#define LCD_PAL163_I0_Pos                                     15                                                        /*!< LCD PAL163: I0 Position             */
#define LCD_PAL163_I0_Msk                                     (0x01UL << LCD_PAL163_I0_Pos)                             /*!< LCD PAL163: I0 Mask                 */
#define LCD_PAL163_R14_0_Pos                                  16                                                        /*!< LCD PAL163: R14_0 Position          */
#define LCD_PAL163_R14_0_Msk                                  (0x1fUL << LCD_PAL163_R14_0_Pos)                          /*!< LCD PAL163: R14_0 Mask              */
#define LCD_PAL163_G14_0_Pos                                  21                                                        /*!< LCD PAL163: G14_0 Position          */
#define LCD_PAL163_G14_0_Msk                                  (0x1fUL << LCD_PAL163_G14_0_Pos)                          /*!< LCD PAL163: G14_0 Mask              */
#define LCD_PAL163_B14_0_Pos                                  26                                                        /*!< LCD PAL163: B14_0 Position          */
#define LCD_PAL163_B14_0_Msk                                  (0x1fUL << LCD_PAL163_B14_0_Pos)                          /*!< LCD PAL163: B14_0 Mask              */
#define LCD_PAL163_I1_Pos                                     31                                                        /*!< LCD PAL163: I1 Position             */
#define LCD_PAL163_I1_Msk                                     (0x01UL << LCD_PAL163_I1_Pos)                             /*!< LCD PAL163: I1 Mask                 */

// ---------------------------------------  LCD_PAL164  -------------------------------------------
#define LCD_PAL164_R04_0_Pos                                  0                                                         /*!< LCD PAL164: R04_0 Position          */
#define LCD_PAL164_R04_0_Msk                                  (0x1fUL << LCD_PAL164_R04_0_Pos)                          /*!< LCD PAL164: R04_0 Mask              */
#define LCD_PAL164_G04_0_Pos                                  5                                                         /*!< LCD PAL164: G04_0 Position          */
#define LCD_PAL164_G04_0_Msk                                  (0x1fUL << LCD_PAL164_G04_0_Pos)                          /*!< LCD PAL164: G04_0 Mask              */
#define LCD_PAL164_B04_0_Pos                                  10                                                        /*!< LCD PAL164: B04_0 Position          */
#define LCD_PAL164_B04_0_Msk                                  (0x1fUL << LCD_PAL164_B04_0_Pos)                          /*!< LCD PAL164: B04_0 Mask              */
#define LCD_PAL164_I0_Pos                                     15                                                        /*!< LCD PAL164: I0 Position             */
#define LCD_PAL164_I0_Msk                                     (0x01UL << LCD_PAL164_I0_Pos)                             /*!< LCD PAL164: I0 Mask                 */
#define LCD_PAL164_R14_0_Pos                                  16                                                        /*!< LCD PAL164: R14_0 Position          */
#define LCD_PAL164_R14_0_Msk                                  (0x1fUL << LCD_PAL164_R14_0_Pos)                          /*!< LCD PAL164: R14_0 Mask              */
#define LCD_PAL164_G14_0_Pos                                  21                                                        /*!< LCD PAL164: G14_0 Position          */
#define LCD_PAL164_G14_0_Msk                                  (0x1fUL << LCD_PAL164_G14_0_Pos)                          /*!< LCD PAL164: G14_0 Mask              */
#define LCD_PAL164_B14_0_Pos                                  26                                                        /*!< LCD PAL164: B14_0 Position          */
#define LCD_PAL164_B14_0_Msk                                  (0x1fUL << LCD_PAL164_B14_0_Pos)                          /*!< LCD PAL164: B14_0 Mask              */
#define LCD_PAL164_I1_Pos                                     31                                                        /*!< LCD PAL164: I1 Position             */
#define LCD_PAL164_I1_Msk                                     (0x01UL << LCD_PAL164_I1_Pos)                             /*!< LCD PAL164: I1 Mask                 */

// ---------------------------------------  LCD_PAL165  -------------------------------------------
#define LCD_PAL165_R04_0_Pos                                  0                                                         /*!< LCD PAL165: R04_0 Position          */
#define LCD_PAL165_R04_0_Msk                                  (0x1fUL << LCD_PAL165_R04_0_Pos)                          /*!< LCD PAL165: R04_0 Mask              */
#define LCD_PAL165_G04_0_Pos                                  5                                                         /*!< LCD PAL165: G04_0 Position          */
#define LCD_PAL165_G04_0_Msk                                  (0x1fUL << LCD_PAL165_G04_0_Pos)                          /*!< LCD PAL165: G04_0 Mask              */
#define LCD_PAL165_B04_0_Pos                                  10                                                        /*!< LCD PAL165: B04_0 Position          */
#define LCD_PAL165_B04_0_Msk                                  (0x1fUL << LCD_PAL165_B04_0_Pos)                          /*!< LCD PAL165: B04_0 Mask              */
#define LCD_PAL165_I0_Pos                                     15                                                        /*!< LCD PAL165: I0 Position             */
#define LCD_PAL165_I0_Msk                                     (0x01UL << LCD_PAL165_I0_Pos)                             /*!< LCD PAL165: I0 Mask                 */
#define LCD_PAL165_R14_0_Pos                                  16                                                        /*!< LCD PAL165: R14_0 Position          */
#define LCD_PAL165_R14_0_Msk                                  (0x1fUL << LCD_PAL165_R14_0_Pos)                          /*!< LCD PAL165: R14_0 Mask              */
#define LCD_PAL165_G14_0_Pos                                  21                                                        /*!< LCD PAL165: G14_0 Position          */
#define LCD_PAL165_G14_0_Msk                                  (0x1fUL << LCD_PAL165_G14_0_Pos)                          /*!< LCD PAL165: G14_0 Mask              */
#define LCD_PAL165_B14_0_Pos                                  26                                                        /*!< LCD PAL165: B14_0 Position          */
#define LCD_PAL165_B14_0_Msk                                  (0x1fUL << LCD_PAL165_B14_0_Pos)                          /*!< LCD PAL165: B14_0 Mask              */
#define LCD_PAL165_I1_Pos                                     31                                                        /*!< LCD PAL165: I1 Position             */
#define LCD_PAL165_I1_Msk                                     (0x01UL << LCD_PAL165_I1_Pos)                             /*!< LCD PAL165: I1 Mask                 */

// ---------------------------------------  LCD_PAL166  -------------------------------------------
#define LCD_PAL166_R04_0_Pos                                  0                                                         /*!< LCD PAL166: R04_0 Position          */
#define LCD_PAL166_R04_0_Msk                                  (0x1fUL << LCD_PAL166_R04_0_Pos)                          /*!< LCD PAL166: R04_0 Mask              */
#define LCD_PAL166_G04_0_Pos                                  5                                                         /*!< LCD PAL166: G04_0 Position          */
#define LCD_PAL166_G04_0_Msk                                  (0x1fUL << LCD_PAL166_G04_0_Pos)                          /*!< LCD PAL166: G04_0 Mask              */
#define LCD_PAL166_B04_0_Pos                                  10                                                        /*!< LCD PAL166: B04_0 Position          */
#define LCD_PAL166_B04_0_Msk                                  (0x1fUL << LCD_PAL166_B04_0_Pos)                          /*!< LCD PAL166: B04_0 Mask              */
#define LCD_PAL166_I0_Pos                                     15                                                        /*!< LCD PAL166: I0 Position             */
#define LCD_PAL166_I0_Msk                                     (0x01UL << LCD_PAL166_I0_Pos)                             /*!< LCD PAL166: I0 Mask                 */
#define LCD_PAL166_R14_0_Pos                                  16                                                        /*!< LCD PAL166: R14_0 Position          */
#define LCD_PAL166_R14_0_Msk                                  (0x1fUL << LCD_PAL166_R14_0_Pos)                          /*!< LCD PAL166: R14_0 Mask              */
#define LCD_PAL166_G14_0_Pos                                  21                                                        /*!< LCD PAL166: G14_0 Position          */
#define LCD_PAL166_G14_0_Msk                                  (0x1fUL << LCD_PAL166_G14_0_Pos)                          /*!< LCD PAL166: G14_0 Mask              */
#define LCD_PAL166_B14_0_Pos                                  26                                                        /*!< LCD PAL166: B14_0 Position          */
#define LCD_PAL166_B14_0_Msk                                  (0x1fUL << LCD_PAL166_B14_0_Pos)                          /*!< LCD PAL166: B14_0 Mask              */
#define LCD_PAL166_I1_Pos                                     31                                                        /*!< LCD PAL166: I1 Position             */
#define LCD_PAL166_I1_Msk                                     (0x01UL << LCD_PAL166_I1_Pos)                             /*!< LCD PAL166: I1 Mask                 */

// ---------------------------------------  LCD_PAL167  -------------------------------------------
#define LCD_PAL167_R04_0_Pos                                  0                                                         /*!< LCD PAL167: R04_0 Position          */
#define LCD_PAL167_R04_0_Msk                                  (0x1fUL << LCD_PAL167_R04_0_Pos)                          /*!< LCD PAL167: R04_0 Mask              */
#define LCD_PAL167_G04_0_Pos                                  5                                                         /*!< LCD PAL167: G04_0 Position          */
#define LCD_PAL167_G04_0_Msk                                  (0x1fUL << LCD_PAL167_G04_0_Pos)                          /*!< LCD PAL167: G04_0 Mask              */
#define LCD_PAL167_B04_0_Pos                                  10                                                        /*!< LCD PAL167: B04_0 Position          */
#define LCD_PAL167_B04_0_Msk                                  (0x1fUL << LCD_PAL167_B04_0_Pos)                          /*!< LCD PAL167: B04_0 Mask              */
#define LCD_PAL167_I0_Pos                                     15                                                        /*!< LCD PAL167: I0 Position             */
#define LCD_PAL167_I0_Msk                                     (0x01UL << LCD_PAL167_I0_Pos)                             /*!< LCD PAL167: I0 Mask                 */
#define LCD_PAL167_R14_0_Pos                                  16                                                        /*!< LCD PAL167: R14_0 Position          */
#define LCD_PAL167_R14_0_Msk                                  (0x1fUL << LCD_PAL167_R14_0_Pos)                          /*!< LCD PAL167: R14_0 Mask              */
#define LCD_PAL167_G14_0_Pos                                  21                                                        /*!< LCD PAL167: G14_0 Position          */
#define LCD_PAL167_G14_0_Msk                                  (0x1fUL << LCD_PAL167_G14_0_Pos)                          /*!< LCD PAL167: G14_0 Mask              */
#define LCD_PAL167_B14_0_Pos                                  26                                                        /*!< LCD PAL167: B14_0 Position          */
#define LCD_PAL167_B14_0_Msk                                  (0x1fUL << LCD_PAL167_B14_0_Pos)                          /*!< LCD PAL167: B14_0 Mask              */
#define LCD_PAL167_I1_Pos                                     31                                                        /*!< LCD PAL167: I1 Position             */
#define LCD_PAL167_I1_Msk                                     (0x01UL << LCD_PAL167_I1_Pos)                             /*!< LCD PAL167: I1 Mask                 */

// ---------------------------------------  LCD_PAL168  -------------------------------------------
#define LCD_PAL168_R04_0_Pos                                  0                                                         /*!< LCD PAL168: R04_0 Position          */
#define LCD_PAL168_R04_0_Msk                                  (0x1fUL << LCD_PAL168_R04_0_Pos)                          /*!< LCD PAL168: R04_0 Mask              */
#define LCD_PAL168_G04_0_Pos                                  5                                                         /*!< LCD PAL168: G04_0 Position          */
#define LCD_PAL168_G04_0_Msk                                  (0x1fUL << LCD_PAL168_G04_0_Pos)                          /*!< LCD PAL168: G04_0 Mask              */
#define LCD_PAL168_B04_0_Pos                                  10                                                        /*!< LCD PAL168: B04_0 Position          */
#define LCD_PAL168_B04_0_Msk                                  (0x1fUL << LCD_PAL168_B04_0_Pos)                          /*!< LCD PAL168: B04_0 Mask              */
#define LCD_PAL168_I0_Pos                                     15                                                        /*!< LCD PAL168: I0 Position             */
#define LCD_PAL168_I0_Msk                                     (0x01UL << LCD_PAL168_I0_Pos)                             /*!< LCD PAL168: I0 Mask                 */
#define LCD_PAL168_R14_0_Pos                                  16                                                        /*!< LCD PAL168: R14_0 Position          */
#define LCD_PAL168_R14_0_Msk                                  (0x1fUL << LCD_PAL168_R14_0_Pos)                          /*!< LCD PAL168: R14_0 Mask              */
#define LCD_PAL168_G14_0_Pos                                  21                                                        /*!< LCD PAL168: G14_0 Position          */
#define LCD_PAL168_G14_0_Msk                                  (0x1fUL << LCD_PAL168_G14_0_Pos)                          /*!< LCD PAL168: G14_0 Mask              */
#define LCD_PAL168_B14_0_Pos                                  26                                                        /*!< LCD PAL168: B14_0 Position          */
#define LCD_PAL168_B14_0_Msk                                  (0x1fUL << LCD_PAL168_B14_0_Pos)                          /*!< LCD PAL168: B14_0 Mask              */
#define LCD_PAL168_I1_Pos                                     31                                                        /*!< LCD PAL168: I1 Position             */
#define LCD_PAL168_I1_Msk                                     (0x01UL << LCD_PAL168_I1_Pos)                             /*!< LCD PAL168: I1 Mask                 */

// ---------------------------------------  LCD_PAL169  -------------------------------------------
#define LCD_PAL169_R04_0_Pos                                  0                                                         /*!< LCD PAL169: R04_0 Position          */
#define LCD_PAL169_R04_0_Msk                                  (0x1fUL << LCD_PAL169_R04_0_Pos)                          /*!< LCD PAL169: R04_0 Mask              */
#define LCD_PAL169_G04_0_Pos                                  5                                                         /*!< LCD PAL169: G04_0 Position          */
#define LCD_PAL169_G04_0_Msk                                  (0x1fUL << LCD_PAL169_G04_0_Pos)                          /*!< LCD PAL169: G04_0 Mask              */
#define LCD_PAL169_B04_0_Pos                                  10                                                        /*!< LCD PAL169: B04_0 Position          */
#define LCD_PAL169_B04_0_Msk                                  (0x1fUL << LCD_PAL169_B04_0_Pos)                          /*!< LCD PAL169: B04_0 Mask              */
#define LCD_PAL169_I0_Pos                                     15                                                        /*!< LCD PAL169: I0 Position             */
#define LCD_PAL169_I0_Msk                                     (0x01UL << LCD_PAL169_I0_Pos)                             /*!< LCD PAL169: I0 Mask                 */
#define LCD_PAL169_R14_0_Pos                                  16                                                        /*!< LCD PAL169: R14_0 Position          */
#define LCD_PAL169_R14_0_Msk                                  (0x1fUL << LCD_PAL169_R14_0_Pos)                          /*!< LCD PAL169: R14_0 Mask              */
#define LCD_PAL169_G14_0_Pos                                  21                                                        /*!< LCD PAL169: G14_0 Position          */
#define LCD_PAL169_G14_0_Msk                                  (0x1fUL << LCD_PAL169_G14_0_Pos)                          /*!< LCD PAL169: G14_0 Mask              */
#define LCD_PAL169_B14_0_Pos                                  26                                                        /*!< LCD PAL169: B14_0 Position          */
#define LCD_PAL169_B14_0_Msk                                  (0x1fUL << LCD_PAL169_B14_0_Pos)                          /*!< LCD PAL169: B14_0 Mask              */
#define LCD_PAL169_I1_Pos                                     31                                                        /*!< LCD PAL169: I1 Position             */
#define LCD_PAL169_I1_Msk                                     (0x01UL << LCD_PAL169_I1_Pos)                             /*!< LCD PAL169: I1 Mask                 */

// ---------------------------------------  LCD_PAL170  -------------------------------------------
#define LCD_PAL170_R04_0_Pos                                  0                                                         /*!< LCD PAL170: R04_0 Position          */
#define LCD_PAL170_R04_0_Msk                                  (0x1fUL << LCD_PAL170_R04_0_Pos)                          /*!< LCD PAL170: R04_0 Mask              */
#define LCD_PAL170_G04_0_Pos                                  5                                                         /*!< LCD PAL170: G04_0 Position          */
#define LCD_PAL170_G04_0_Msk                                  (0x1fUL << LCD_PAL170_G04_0_Pos)                          /*!< LCD PAL170: G04_0 Mask              */
#define LCD_PAL170_B04_0_Pos                                  10                                                        /*!< LCD PAL170: B04_0 Position          */
#define LCD_PAL170_B04_0_Msk                                  (0x1fUL << LCD_PAL170_B04_0_Pos)                          /*!< LCD PAL170: B04_0 Mask              */
#define LCD_PAL170_I0_Pos                                     15                                                        /*!< LCD PAL170: I0 Position             */
#define LCD_PAL170_I0_Msk                                     (0x01UL << LCD_PAL170_I0_Pos)                             /*!< LCD PAL170: I0 Mask                 */
#define LCD_PAL170_R14_0_Pos                                  16                                                        /*!< LCD PAL170: R14_0 Position          */
#define LCD_PAL170_R14_0_Msk                                  (0x1fUL << LCD_PAL170_R14_0_Pos)                          /*!< LCD PAL170: R14_0 Mask              */
#define LCD_PAL170_G14_0_Pos                                  21                                                        /*!< LCD PAL170: G14_0 Position          */
#define LCD_PAL170_G14_0_Msk                                  (0x1fUL << LCD_PAL170_G14_0_Pos)                          /*!< LCD PAL170: G14_0 Mask              */
#define LCD_PAL170_B14_0_Pos                                  26                                                        /*!< LCD PAL170: B14_0 Position          */
#define LCD_PAL170_B14_0_Msk                                  (0x1fUL << LCD_PAL170_B14_0_Pos)                          /*!< LCD PAL170: B14_0 Mask              */
#define LCD_PAL170_I1_Pos                                     31                                                        /*!< LCD PAL170: I1 Position             */
#define LCD_PAL170_I1_Msk                                     (0x01UL << LCD_PAL170_I1_Pos)                             /*!< LCD PAL170: I1 Mask                 */

// ---------------------------------------  LCD_PAL171  -------------------------------------------
#define LCD_PAL171_R04_0_Pos                                  0                                                         /*!< LCD PAL171: R04_0 Position          */
#define LCD_PAL171_R04_0_Msk                                  (0x1fUL << LCD_PAL171_R04_0_Pos)                          /*!< LCD PAL171: R04_0 Mask              */
#define LCD_PAL171_G04_0_Pos                                  5                                                         /*!< LCD PAL171: G04_0 Position          */
#define LCD_PAL171_G04_0_Msk                                  (0x1fUL << LCD_PAL171_G04_0_Pos)                          /*!< LCD PAL171: G04_0 Mask              */
#define LCD_PAL171_B04_0_Pos                                  10                                                        /*!< LCD PAL171: B04_0 Position          */
#define LCD_PAL171_B04_0_Msk                                  (0x1fUL << LCD_PAL171_B04_0_Pos)                          /*!< LCD PAL171: B04_0 Mask              */
#define LCD_PAL171_I0_Pos                                     15                                                        /*!< LCD PAL171: I0 Position             */
#define LCD_PAL171_I0_Msk                                     (0x01UL << LCD_PAL171_I0_Pos)                             /*!< LCD PAL171: I0 Mask                 */
#define LCD_PAL171_R14_0_Pos                                  16                                                        /*!< LCD PAL171: R14_0 Position          */
#define LCD_PAL171_R14_0_Msk                                  (0x1fUL << LCD_PAL171_R14_0_Pos)                          /*!< LCD PAL171: R14_0 Mask              */
#define LCD_PAL171_G14_0_Pos                                  21                                                        /*!< LCD PAL171: G14_0 Position          */
#define LCD_PAL171_G14_0_Msk                                  (0x1fUL << LCD_PAL171_G14_0_Pos)                          /*!< LCD PAL171: G14_0 Mask              */
#define LCD_PAL171_B14_0_Pos                                  26                                                        /*!< LCD PAL171: B14_0 Position          */
#define LCD_PAL171_B14_0_Msk                                  (0x1fUL << LCD_PAL171_B14_0_Pos)                          /*!< LCD PAL171: B14_0 Mask              */
#define LCD_PAL171_I1_Pos                                     31                                                        /*!< LCD PAL171: I1 Position             */
#define LCD_PAL171_I1_Msk                                     (0x01UL << LCD_PAL171_I1_Pos)                             /*!< LCD PAL171: I1 Mask                 */

// ---------------------------------------  LCD_PAL172  -------------------------------------------
#define LCD_PAL172_R04_0_Pos                                  0                                                         /*!< LCD PAL172: R04_0 Position          */
#define LCD_PAL172_R04_0_Msk                                  (0x1fUL << LCD_PAL172_R04_0_Pos)                          /*!< LCD PAL172: R04_0 Mask              */
#define LCD_PAL172_G04_0_Pos                                  5                                                         /*!< LCD PAL172: G04_0 Position          */
#define LCD_PAL172_G04_0_Msk                                  (0x1fUL << LCD_PAL172_G04_0_Pos)                          /*!< LCD PAL172: G04_0 Mask              */
#define LCD_PAL172_B04_0_Pos                                  10                                                        /*!< LCD PAL172: B04_0 Position          */
#define LCD_PAL172_B04_0_Msk                                  (0x1fUL << LCD_PAL172_B04_0_Pos)                          /*!< LCD PAL172: B04_0 Mask              */
#define LCD_PAL172_I0_Pos                                     15                                                        /*!< LCD PAL172: I0 Position             */
#define LCD_PAL172_I0_Msk                                     (0x01UL << LCD_PAL172_I0_Pos)                             /*!< LCD PAL172: I0 Mask                 */
#define LCD_PAL172_R14_0_Pos                                  16                                                        /*!< LCD PAL172: R14_0 Position          */
#define LCD_PAL172_R14_0_Msk                                  (0x1fUL << LCD_PAL172_R14_0_Pos)                          /*!< LCD PAL172: R14_0 Mask              */
#define LCD_PAL172_G14_0_Pos                                  21                                                        /*!< LCD PAL172: G14_0 Position          */
#define LCD_PAL172_G14_0_Msk                                  (0x1fUL << LCD_PAL172_G14_0_Pos)                          /*!< LCD PAL172: G14_0 Mask              */
#define LCD_PAL172_B14_0_Pos                                  26                                                        /*!< LCD PAL172: B14_0 Position          */
#define LCD_PAL172_B14_0_Msk                                  (0x1fUL << LCD_PAL172_B14_0_Pos)                          /*!< LCD PAL172: B14_0 Mask              */
#define LCD_PAL172_I1_Pos                                     31                                                        /*!< LCD PAL172: I1 Position             */
#define LCD_PAL172_I1_Msk                                     (0x01UL << LCD_PAL172_I1_Pos)                             /*!< LCD PAL172: I1 Mask                 */

// ---------------------------------------  LCD_PAL173  -------------------------------------------
#define LCD_PAL173_R04_0_Pos                                  0                                                         /*!< LCD PAL173: R04_0 Position          */
#define LCD_PAL173_R04_0_Msk                                  (0x1fUL << LCD_PAL173_R04_0_Pos)                          /*!< LCD PAL173: R04_0 Mask              */
#define LCD_PAL173_G04_0_Pos                                  5                                                         /*!< LCD PAL173: G04_0 Position          */
#define LCD_PAL173_G04_0_Msk                                  (0x1fUL << LCD_PAL173_G04_0_Pos)                          /*!< LCD PAL173: G04_0 Mask              */
#define LCD_PAL173_B04_0_Pos                                  10                                                        /*!< LCD PAL173: B04_0 Position          */
#define LCD_PAL173_B04_0_Msk                                  (0x1fUL << LCD_PAL173_B04_0_Pos)                          /*!< LCD PAL173: B04_0 Mask              */
#define LCD_PAL173_I0_Pos                                     15                                                        /*!< LCD PAL173: I0 Position             */
#define LCD_PAL173_I0_Msk                                     (0x01UL << LCD_PAL173_I0_Pos)                             /*!< LCD PAL173: I0 Mask                 */
#define LCD_PAL173_R14_0_Pos                                  16                                                        /*!< LCD PAL173: R14_0 Position          */
#define LCD_PAL173_R14_0_Msk                                  (0x1fUL << LCD_PAL173_R14_0_Pos)                          /*!< LCD PAL173: R14_0 Mask              */
#define LCD_PAL173_G14_0_Pos                                  21                                                        /*!< LCD PAL173: G14_0 Position          */
#define LCD_PAL173_G14_0_Msk                                  (0x1fUL << LCD_PAL173_G14_0_Pos)                          /*!< LCD PAL173: G14_0 Mask              */
#define LCD_PAL173_B14_0_Pos                                  26                                                        /*!< LCD PAL173: B14_0 Position          */
#define LCD_PAL173_B14_0_Msk                                  (0x1fUL << LCD_PAL173_B14_0_Pos)                          /*!< LCD PAL173: B14_0 Mask              */
#define LCD_PAL173_I1_Pos                                     31                                                        /*!< LCD PAL173: I1 Position             */
#define LCD_PAL173_I1_Msk                                     (0x01UL << LCD_PAL173_I1_Pos)                             /*!< LCD PAL173: I1 Mask                 */

// ---------------------------------------  LCD_PAL174  -------------------------------------------
#define LCD_PAL174_R04_0_Pos                                  0                                                         /*!< LCD PAL174: R04_0 Position          */
#define LCD_PAL174_R04_0_Msk                                  (0x1fUL << LCD_PAL174_R04_0_Pos)                          /*!< LCD PAL174: R04_0 Mask              */
#define LCD_PAL174_G04_0_Pos                                  5                                                         /*!< LCD PAL174: G04_0 Position          */
#define LCD_PAL174_G04_0_Msk                                  (0x1fUL << LCD_PAL174_G04_0_Pos)                          /*!< LCD PAL174: G04_0 Mask              */
#define LCD_PAL174_B04_0_Pos                                  10                                                        /*!< LCD PAL174: B04_0 Position          */
#define LCD_PAL174_B04_0_Msk                                  (0x1fUL << LCD_PAL174_B04_0_Pos)                          /*!< LCD PAL174: B04_0 Mask              */
#define LCD_PAL174_I0_Pos                                     15                                                        /*!< LCD PAL174: I0 Position             */
#define LCD_PAL174_I0_Msk                                     (0x01UL << LCD_PAL174_I0_Pos)                             /*!< LCD PAL174: I0 Mask                 */
#define LCD_PAL174_R14_0_Pos                                  16                                                        /*!< LCD PAL174: R14_0 Position          */
#define LCD_PAL174_R14_0_Msk                                  (0x1fUL << LCD_PAL174_R14_0_Pos)                          /*!< LCD PAL174: R14_0 Mask              */
#define LCD_PAL174_G14_0_Pos                                  21                                                        /*!< LCD PAL174: G14_0 Position          */
#define LCD_PAL174_G14_0_Msk                                  (0x1fUL << LCD_PAL174_G14_0_Pos)                          /*!< LCD PAL174: G14_0 Mask              */
#define LCD_PAL174_B14_0_Pos                                  26                                                        /*!< LCD PAL174: B14_0 Position          */
#define LCD_PAL174_B14_0_Msk                                  (0x1fUL << LCD_PAL174_B14_0_Pos)                          /*!< LCD PAL174: B14_0 Mask              */
#define LCD_PAL174_I1_Pos                                     31                                                        /*!< LCD PAL174: I1 Position             */
#define LCD_PAL174_I1_Msk                                     (0x01UL << LCD_PAL174_I1_Pos)                             /*!< LCD PAL174: I1 Mask                 */

// ---------------------------------------  LCD_PAL175  -------------------------------------------
#define LCD_PAL175_R04_0_Pos                                  0                                                         /*!< LCD PAL175: R04_0 Position          */
#define LCD_PAL175_R04_0_Msk                                  (0x1fUL << LCD_PAL175_R04_0_Pos)                          /*!< LCD PAL175: R04_0 Mask              */
#define LCD_PAL175_G04_0_Pos                                  5                                                         /*!< LCD PAL175: G04_0 Position          */
#define LCD_PAL175_G04_0_Msk                                  (0x1fUL << LCD_PAL175_G04_0_Pos)                          /*!< LCD PAL175: G04_0 Mask              */
#define LCD_PAL175_B04_0_Pos                                  10                                                        /*!< LCD PAL175: B04_0 Position          */
#define LCD_PAL175_B04_0_Msk                                  (0x1fUL << LCD_PAL175_B04_0_Pos)                          /*!< LCD PAL175: B04_0 Mask              */
#define LCD_PAL175_I0_Pos                                     15                                                        /*!< LCD PAL175: I0 Position             */
#define LCD_PAL175_I0_Msk                                     (0x01UL << LCD_PAL175_I0_Pos)                             /*!< LCD PAL175: I0 Mask                 */
#define LCD_PAL175_R14_0_Pos                                  16                                                        /*!< LCD PAL175: R14_0 Position          */
#define LCD_PAL175_R14_0_Msk                                  (0x1fUL << LCD_PAL175_R14_0_Pos)                          /*!< LCD PAL175: R14_0 Mask              */
#define LCD_PAL175_G14_0_Pos                                  21                                                        /*!< LCD PAL175: G14_0 Position          */
#define LCD_PAL175_G14_0_Msk                                  (0x1fUL << LCD_PAL175_G14_0_Pos)                          /*!< LCD PAL175: G14_0 Mask              */
#define LCD_PAL175_B14_0_Pos                                  26                                                        /*!< LCD PAL175: B14_0 Position          */
#define LCD_PAL175_B14_0_Msk                                  (0x1fUL << LCD_PAL175_B14_0_Pos)                          /*!< LCD PAL175: B14_0 Mask              */
#define LCD_PAL175_I1_Pos                                     31                                                        /*!< LCD PAL175: I1 Position             */
#define LCD_PAL175_I1_Msk                                     (0x01UL << LCD_PAL175_I1_Pos)                             /*!< LCD PAL175: I1 Mask                 */

// ---------------------------------------  LCD_PAL176  -------------------------------------------
#define LCD_PAL176_R04_0_Pos                                  0                                                         /*!< LCD PAL176: R04_0 Position          */
#define LCD_PAL176_R04_0_Msk                                  (0x1fUL << LCD_PAL176_R04_0_Pos)                          /*!< LCD PAL176: R04_0 Mask              */
#define LCD_PAL176_G04_0_Pos                                  5                                                         /*!< LCD PAL176: G04_0 Position          */
#define LCD_PAL176_G04_0_Msk                                  (0x1fUL << LCD_PAL176_G04_0_Pos)                          /*!< LCD PAL176: G04_0 Mask              */
#define LCD_PAL176_B04_0_Pos                                  10                                                        /*!< LCD PAL176: B04_0 Position          */
#define LCD_PAL176_B04_0_Msk                                  (0x1fUL << LCD_PAL176_B04_0_Pos)                          /*!< LCD PAL176: B04_0 Mask              */
#define LCD_PAL176_I0_Pos                                     15                                                        /*!< LCD PAL176: I0 Position             */
#define LCD_PAL176_I0_Msk                                     (0x01UL << LCD_PAL176_I0_Pos)                             /*!< LCD PAL176: I0 Mask                 */
#define LCD_PAL176_R14_0_Pos                                  16                                                        /*!< LCD PAL176: R14_0 Position          */
#define LCD_PAL176_R14_0_Msk                                  (0x1fUL << LCD_PAL176_R14_0_Pos)                          /*!< LCD PAL176: R14_0 Mask              */
#define LCD_PAL176_G14_0_Pos                                  21                                                        /*!< LCD PAL176: G14_0 Position          */
#define LCD_PAL176_G14_0_Msk                                  (0x1fUL << LCD_PAL176_G14_0_Pos)                          /*!< LCD PAL176: G14_0 Mask              */
#define LCD_PAL176_B14_0_Pos                                  26                                                        /*!< LCD PAL176: B14_0 Position          */
#define LCD_PAL176_B14_0_Msk                                  (0x1fUL << LCD_PAL176_B14_0_Pos)                          /*!< LCD PAL176: B14_0 Mask              */
#define LCD_PAL176_I1_Pos                                     31                                                        /*!< LCD PAL176: I1 Position             */
#define LCD_PAL176_I1_Msk                                     (0x01UL << LCD_PAL176_I1_Pos)                             /*!< LCD PAL176: I1 Mask                 */

// ---------------------------------------  LCD_PAL177  -------------------------------------------
#define LCD_PAL177_R04_0_Pos                                  0                                                         /*!< LCD PAL177: R04_0 Position          */
#define LCD_PAL177_R04_0_Msk                                  (0x1fUL << LCD_PAL177_R04_0_Pos)                          /*!< LCD PAL177: R04_0 Mask              */
#define LCD_PAL177_G04_0_Pos                                  5                                                         /*!< LCD PAL177: G04_0 Position          */
#define LCD_PAL177_G04_0_Msk                                  (0x1fUL << LCD_PAL177_G04_0_Pos)                          /*!< LCD PAL177: G04_0 Mask              */
#define LCD_PAL177_B04_0_Pos                                  10                                                        /*!< LCD PAL177: B04_0 Position          */
#define LCD_PAL177_B04_0_Msk                                  (0x1fUL << LCD_PAL177_B04_0_Pos)                          /*!< LCD PAL177: B04_0 Mask              */
#define LCD_PAL177_I0_Pos                                     15                                                        /*!< LCD PAL177: I0 Position             */
#define LCD_PAL177_I0_Msk                                     (0x01UL << LCD_PAL177_I0_Pos)                             /*!< LCD PAL177: I0 Mask                 */
#define LCD_PAL177_R14_0_Pos                                  16                                                        /*!< LCD PAL177: R14_0 Position          */
#define LCD_PAL177_R14_0_Msk                                  (0x1fUL << LCD_PAL177_R14_0_Pos)                          /*!< LCD PAL177: R14_0 Mask              */
#define LCD_PAL177_G14_0_Pos                                  21                                                        /*!< LCD PAL177: G14_0 Position          */
#define LCD_PAL177_G14_0_Msk                                  (0x1fUL << LCD_PAL177_G14_0_Pos)                          /*!< LCD PAL177: G14_0 Mask              */
#define LCD_PAL177_B14_0_Pos                                  26                                                        /*!< LCD PAL177: B14_0 Position          */
#define LCD_PAL177_B14_0_Msk                                  (0x1fUL << LCD_PAL177_B14_0_Pos)                          /*!< LCD PAL177: B14_0 Mask              */
#define LCD_PAL177_I1_Pos                                     31                                                        /*!< LCD PAL177: I1 Position             */
#define LCD_PAL177_I1_Msk                                     (0x01UL << LCD_PAL177_I1_Pos)                             /*!< LCD PAL177: I1 Mask                 */

// ---------------------------------------  LCD_PAL178  -------------------------------------------
#define LCD_PAL178_R04_0_Pos                                  0                                                         /*!< LCD PAL178: R04_0 Position          */
#define LCD_PAL178_R04_0_Msk                                  (0x1fUL << LCD_PAL178_R04_0_Pos)                          /*!< LCD PAL178: R04_0 Mask              */
#define LCD_PAL178_G04_0_Pos                                  5                                                         /*!< LCD PAL178: G04_0 Position          */
#define LCD_PAL178_G04_0_Msk                                  (0x1fUL << LCD_PAL178_G04_0_Pos)                          /*!< LCD PAL178: G04_0 Mask              */
#define LCD_PAL178_B04_0_Pos                                  10                                                        /*!< LCD PAL178: B04_0 Position          */
#define LCD_PAL178_B04_0_Msk                                  (0x1fUL << LCD_PAL178_B04_0_Pos)                          /*!< LCD PAL178: B04_0 Mask              */
#define LCD_PAL178_I0_Pos                                     15                                                        /*!< LCD PAL178: I0 Position             */
#define LCD_PAL178_I0_Msk                                     (0x01UL << LCD_PAL178_I0_Pos)                             /*!< LCD PAL178: I0 Mask                 */
#define LCD_PAL178_R14_0_Pos                                  16                                                        /*!< LCD PAL178: R14_0 Position          */
#define LCD_PAL178_R14_0_Msk                                  (0x1fUL << LCD_PAL178_R14_0_Pos)                          /*!< LCD PAL178: R14_0 Mask              */
#define LCD_PAL178_G14_0_Pos                                  21                                                        /*!< LCD PAL178: G14_0 Position          */
#define LCD_PAL178_G14_0_Msk                                  (0x1fUL << LCD_PAL178_G14_0_Pos)                          /*!< LCD PAL178: G14_0 Mask              */
#define LCD_PAL178_B14_0_Pos                                  26                                                        /*!< LCD PAL178: B14_0 Position          */
#define LCD_PAL178_B14_0_Msk                                  (0x1fUL << LCD_PAL178_B14_0_Pos)                          /*!< LCD PAL178: B14_0 Mask              */
#define LCD_PAL178_I1_Pos                                     31                                                        /*!< LCD PAL178: I1 Position             */
#define LCD_PAL178_I1_Msk                                     (0x01UL << LCD_PAL178_I1_Pos)                             /*!< LCD PAL178: I1 Mask                 */

// ---------------------------------------  LCD_PAL179  -------------------------------------------
#define LCD_PAL179_R04_0_Pos                                  0                                                         /*!< LCD PAL179: R04_0 Position          */
#define LCD_PAL179_R04_0_Msk                                  (0x1fUL << LCD_PAL179_R04_0_Pos)                          /*!< LCD PAL179: R04_0 Mask              */
#define LCD_PAL179_G04_0_Pos                                  5                                                         /*!< LCD PAL179: G04_0 Position          */
#define LCD_PAL179_G04_0_Msk                                  (0x1fUL << LCD_PAL179_G04_0_Pos)                          /*!< LCD PAL179: G04_0 Mask              */
#define LCD_PAL179_B04_0_Pos                                  10                                                        /*!< LCD PAL179: B04_0 Position          */
#define LCD_PAL179_B04_0_Msk                                  (0x1fUL << LCD_PAL179_B04_0_Pos)                          /*!< LCD PAL179: B04_0 Mask              */
#define LCD_PAL179_I0_Pos                                     15                                                        /*!< LCD PAL179: I0 Position             */
#define LCD_PAL179_I0_Msk                                     (0x01UL << LCD_PAL179_I0_Pos)                             /*!< LCD PAL179: I0 Mask                 */
#define LCD_PAL179_R14_0_Pos                                  16                                                        /*!< LCD PAL179: R14_0 Position          */
#define LCD_PAL179_R14_0_Msk                                  (0x1fUL << LCD_PAL179_R14_0_Pos)                          /*!< LCD PAL179: R14_0 Mask              */
#define LCD_PAL179_G14_0_Pos                                  21                                                        /*!< LCD PAL179: G14_0 Position          */
#define LCD_PAL179_G14_0_Msk                                  (0x1fUL << LCD_PAL179_G14_0_Pos)                          /*!< LCD PAL179: G14_0 Mask              */
#define LCD_PAL179_B14_0_Pos                                  26                                                        /*!< LCD PAL179: B14_0 Position          */
#define LCD_PAL179_B14_0_Msk                                  (0x1fUL << LCD_PAL179_B14_0_Pos)                          /*!< LCD PAL179: B14_0 Mask              */
#define LCD_PAL179_I1_Pos                                     31                                                        /*!< LCD PAL179: I1 Position             */
#define LCD_PAL179_I1_Msk                                     (0x01UL << LCD_PAL179_I1_Pos)                             /*!< LCD PAL179: I1 Mask                 */

// ---------------------------------------  LCD_PAL180  -------------------------------------------
#define LCD_PAL180_R04_0_Pos                                  0                                                         /*!< LCD PAL180: R04_0 Position          */
#define LCD_PAL180_R04_0_Msk                                  (0x1fUL << LCD_PAL180_R04_0_Pos)                          /*!< LCD PAL180: R04_0 Mask              */
#define LCD_PAL180_G04_0_Pos                                  5                                                         /*!< LCD PAL180: G04_0 Position          */
#define LCD_PAL180_G04_0_Msk                                  (0x1fUL << LCD_PAL180_G04_0_Pos)                          /*!< LCD PAL180: G04_0 Mask              */
#define LCD_PAL180_B04_0_Pos                                  10                                                        /*!< LCD PAL180: B04_0 Position          */
#define LCD_PAL180_B04_0_Msk                                  (0x1fUL << LCD_PAL180_B04_0_Pos)                          /*!< LCD PAL180: B04_0 Mask              */
#define LCD_PAL180_I0_Pos                                     15                                                        /*!< LCD PAL180: I0 Position             */
#define LCD_PAL180_I0_Msk                                     (0x01UL << LCD_PAL180_I0_Pos)                             /*!< LCD PAL180: I0 Mask                 */
#define LCD_PAL180_R14_0_Pos                                  16                                                        /*!< LCD PAL180: R14_0 Position          */
#define LCD_PAL180_R14_0_Msk                                  (0x1fUL << LCD_PAL180_R14_0_Pos)                          /*!< LCD PAL180: R14_0 Mask              */
#define LCD_PAL180_G14_0_Pos                                  21                                                        /*!< LCD PAL180: G14_0 Position          */
#define LCD_PAL180_G14_0_Msk                                  (0x1fUL << LCD_PAL180_G14_0_Pos)                          /*!< LCD PAL180: G14_0 Mask              */
#define LCD_PAL180_B14_0_Pos                                  26                                                        /*!< LCD PAL180: B14_0 Position          */
#define LCD_PAL180_B14_0_Msk                                  (0x1fUL << LCD_PAL180_B14_0_Pos)                          /*!< LCD PAL180: B14_0 Mask              */
#define LCD_PAL180_I1_Pos                                     31                                                        /*!< LCD PAL180: I1 Position             */
#define LCD_PAL180_I1_Msk                                     (0x01UL << LCD_PAL180_I1_Pos)                             /*!< LCD PAL180: I1 Mask                 */

// ---------------------------------------  LCD_PAL181  -------------------------------------------
#define LCD_PAL181_R04_0_Pos                                  0                                                         /*!< LCD PAL181: R04_0 Position          */
#define LCD_PAL181_R04_0_Msk                                  (0x1fUL << LCD_PAL181_R04_0_Pos)                          /*!< LCD PAL181: R04_0 Mask              */
#define LCD_PAL181_G04_0_Pos                                  5                                                         /*!< LCD PAL181: G04_0 Position          */
#define LCD_PAL181_G04_0_Msk                                  (0x1fUL << LCD_PAL181_G04_0_Pos)                          /*!< LCD PAL181: G04_0 Mask              */
#define LCD_PAL181_B04_0_Pos                                  10                                                        /*!< LCD PAL181: B04_0 Position          */
#define LCD_PAL181_B04_0_Msk                                  (0x1fUL << LCD_PAL181_B04_0_Pos)                          /*!< LCD PAL181: B04_0 Mask              */
#define LCD_PAL181_I0_Pos                                     15                                                        /*!< LCD PAL181: I0 Position             */
#define LCD_PAL181_I0_Msk                                     (0x01UL << LCD_PAL181_I0_Pos)                             /*!< LCD PAL181: I0 Mask                 */
#define LCD_PAL181_R14_0_Pos                                  16                                                        /*!< LCD PAL181: R14_0 Position          */
#define LCD_PAL181_R14_0_Msk                                  (0x1fUL << LCD_PAL181_R14_0_Pos)                          /*!< LCD PAL181: R14_0 Mask              */
#define LCD_PAL181_G14_0_Pos                                  21                                                        /*!< LCD PAL181: G14_0 Position          */
#define LCD_PAL181_G14_0_Msk                                  (0x1fUL << LCD_PAL181_G14_0_Pos)                          /*!< LCD PAL181: G14_0 Mask              */
#define LCD_PAL181_B14_0_Pos                                  26                                                        /*!< LCD PAL181: B14_0 Position          */
#define LCD_PAL181_B14_0_Msk                                  (0x1fUL << LCD_PAL181_B14_0_Pos)                          /*!< LCD PAL181: B14_0 Mask              */
#define LCD_PAL181_I1_Pos                                     31                                                        /*!< LCD PAL181: I1 Position             */
#define LCD_PAL181_I1_Msk                                     (0x01UL << LCD_PAL181_I1_Pos)                             /*!< LCD PAL181: I1 Mask                 */

// ---------------------------------------  LCD_PAL182  -------------------------------------------
#define LCD_PAL182_R04_0_Pos                                  0                                                         /*!< LCD PAL182: R04_0 Position          */
#define LCD_PAL182_R04_0_Msk                                  (0x1fUL << LCD_PAL182_R04_0_Pos)                          /*!< LCD PAL182: R04_0 Mask              */
#define LCD_PAL182_G04_0_Pos                                  5                                                         /*!< LCD PAL182: G04_0 Position          */
#define LCD_PAL182_G04_0_Msk                                  (0x1fUL << LCD_PAL182_G04_0_Pos)                          /*!< LCD PAL182: G04_0 Mask              */
#define LCD_PAL182_B04_0_Pos                                  10                                                        /*!< LCD PAL182: B04_0 Position          */
#define LCD_PAL182_B04_0_Msk                                  (0x1fUL << LCD_PAL182_B04_0_Pos)                          /*!< LCD PAL182: B04_0 Mask              */
#define LCD_PAL182_I0_Pos                                     15                                                        /*!< LCD PAL182: I0 Position             */
#define LCD_PAL182_I0_Msk                                     (0x01UL << LCD_PAL182_I0_Pos)                             /*!< LCD PAL182: I0 Mask                 */
#define LCD_PAL182_R14_0_Pos                                  16                                                        /*!< LCD PAL182: R14_0 Position          */
#define LCD_PAL182_R14_0_Msk                                  (0x1fUL << LCD_PAL182_R14_0_Pos)                          /*!< LCD PAL182: R14_0 Mask              */
#define LCD_PAL182_G14_0_Pos                                  21                                                        /*!< LCD PAL182: G14_0 Position          */
#define LCD_PAL182_G14_0_Msk                                  (0x1fUL << LCD_PAL182_G14_0_Pos)                          /*!< LCD PAL182: G14_0 Mask              */
#define LCD_PAL182_B14_0_Pos                                  26                                                        /*!< LCD PAL182: B14_0 Position          */
#define LCD_PAL182_B14_0_Msk                                  (0x1fUL << LCD_PAL182_B14_0_Pos)                          /*!< LCD PAL182: B14_0 Mask              */
#define LCD_PAL182_I1_Pos                                     31                                                        /*!< LCD PAL182: I1 Position             */
#define LCD_PAL182_I1_Msk                                     (0x01UL << LCD_PAL182_I1_Pos)                             /*!< LCD PAL182: I1 Mask                 */

// ---------------------------------------  LCD_PAL183  -------------------------------------------
#define LCD_PAL183_R04_0_Pos                                  0                                                         /*!< LCD PAL183: R04_0 Position          */
#define LCD_PAL183_R04_0_Msk                                  (0x1fUL << LCD_PAL183_R04_0_Pos)                          /*!< LCD PAL183: R04_0 Mask              */
#define LCD_PAL183_G04_0_Pos                                  5                                                         /*!< LCD PAL183: G04_0 Position          */
#define LCD_PAL183_G04_0_Msk                                  (0x1fUL << LCD_PAL183_G04_0_Pos)                          /*!< LCD PAL183: G04_0 Mask              */
#define LCD_PAL183_B04_0_Pos                                  10                                                        /*!< LCD PAL183: B04_0 Position          */
#define LCD_PAL183_B04_0_Msk                                  (0x1fUL << LCD_PAL183_B04_0_Pos)                          /*!< LCD PAL183: B04_0 Mask              */
#define LCD_PAL183_I0_Pos                                     15                                                        /*!< LCD PAL183: I0 Position             */
#define LCD_PAL183_I0_Msk                                     (0x01UL << LCD_PAL183_I0_Pos)                             /*!< LCD PAL183: I0 Mask                 */
#define LCD_PAL183_R14_0_Pos                                  16                                                        /*!< LCD PAL183: R14_0 Position          */
#define LCD_PAL183_R14_0_Msk                                  (0x1fUL << LCD_PAL183_R14_0_Pos)                          /*!< LCD PAL183: R14_0 Mask              */
#define LCD_PAL183_G14_0_Pos                                  21                                                        /*!< LCD PAL183: G14_0 Position          */
#define LCD_PAL183_G14_0_Msk                                  (0x1fUL << LCD_PAL183_G14_0_Pos)                          /*!< LCD PAL183: G14_0 Mask              */
#define LCD_PAL183_B14_0_Pos                                  26                                                        /*!< LCD PAL183: B14_0 Position          */
#define LCD_PAL183_B14_0_Msk                                  (0x1fUL << LCD_PAL183_B14_0_Pos)                          /*!< LCD PAL183: B14_0 Mask              */
#define LCD_PAL183_I1_Pos                                     31                                                        /*!< LCD PAL183: I1 Position             */
#define LCD_PAL183_I1_Msk                                     (0x01UL << LCD_PAL183_I1_Pos)                             /*!< LCD PAL183: I1 Mask                 */

// ---------------------------------------  LCD_PAL184  -------------------------------------------
#define LCD_PAL184_R04_0_Pos                                  0                                                         /*!< LCD PAL184: R04_0 Position          */
#define LCD_PAL184_R04_0_Msk                                  (0x1fUL << LCD_PAL184_R04_0_Pos)                          /*!< LCD PAL184: R04_0 Mask              */
#define LCD_PAL184_G04_0_Pos                                  5                                                         /*!< LCD PAL184: G04_0 Position          */
#define LCD_PAL184_G04_0_Msk                                  (0x1fUL << LCD_PAL184_G04_0_Pos)                          /*!< LCD PAL184: G04_0 Mask              */
#define LCD_PAL184_B04_0_Pos                                  10                                                        /*!< LCD PAL184: B04_0 Position          */
#define LCD_PAL184_B04_0_Msk                                  (0x1fUL << LCD_PAL184_B04_0_Pos)                          /*!< LCD PAL184: B04_0 Mask              */
#define LCD_PAL184_I0_Pos                                     15                                                        /*!< LCD PAL184: I0 Position             */
#define LCD_PAL184_I0_Msk                                     (0x01UL << LCD_PAL184_I0_Pos)                             /*!< LCD PAL184: I0 Mask                 */
#define LCD_PAL184_R14_0_Pos                                  16                                                        /*!< LCD PAL184: R14_0 Position          */
#define LCD_PAL184_R14_0_Msk                                  (0x1fUL << LCD_PAL184_R14_0_Pos)                          /*!< LCD PAL184: R14_0 Mask              */
#define LCD_PAL184_G14_0_Pos                                  21                                                        /*!< LCD PAL184: G14_0 Position          */
#define LCD_PAL184_G14_0_Msk                                  (0x1fUL << LCD_PAL184_G14_0_Pos)                          /*!< LCD PAL184: G14_0 Mask              */
#define LCD_PAL184_B14_0_Pos                                  26                                                        /*!< LCD PAL184: B14_0 Position          */
#define LCD_PAL184_B14_0_Msk                                  (0x1fUL << LCD_PAL184_B14_0_Pos)                          /*!< LCD PAL184: B14_0 Mask              */
#define LCD_PAL184_I1_Pos                                     31                                                        /*!< LCD PAL184: I1 Position             */
#define LCD_PAL184_I1_Msk                                     (0x01UL << LCD_PAL184_I1_Pos)                             /*!< LCD PAL184: I1 Mask                 */

// ---------------------------------------  LCD_PAL185  -------------------------------------------
#define LCD_PAL185_R04_0_Pos                                  0                                                         /*!< LCD PAL185: R04_0 Position          */
#define LCD_PAL185_R04_0_Msk                                  (0x1fUL << LCD_PAL185_R04_0_Pos)                          /*!< LCD PAL185: R04_0 Mask              */
#define LCD_PAL185_G04_0_Pos                                  5                                                         /*!< LCD PAL185: G04_0 Position          */
#define LCD_PAL185_G04_0_Msk                                  (0x1fUL << LCD_PAL185_G04_0_Pos)                          /*!< LCD PAL185: G04_0 Mask              */
#define LCD_PAL185_B04_0_Pos                                  10                                                        /*!< LCD PAL185: B04_0 Position          */
#define LCD_PAL185_B04_0_Msk                                  (0x1fUL << LCD_PAL185_B04_0_Pos)                          /*!< LCD PAL185: B04_0 Mask              */
#define LCD_PAL185_I0_Pos                                     15                                                        /*!< LCD PAL185: I0 Position             */
#define LCD_PAL185_I0_Msk                                     (0x01UL << LCD_PAL185_I0_Pos)                             /*!< LCD PAL185: I0 Mask                 */
#define LCD_PAL185_R14_0_Pos                                  16                                                        /*!< LCD PAL185: R14_0 Position          */
#define LCD_PAL185_R14_0_Msk                                  (0x1fUL << LCD_PAL185_R14_0_Pos)                          /*!< LCD PAL185: R14_0 Mask              */
#define LCD_PAL185_G14_0_Pos                                  21                                                        /*!< LCD PAL185: G14_0 Position          */
#define LCD_PAL185_G14_0_Msk                                  (0x1fUL << LCD_PAL185_G14_0_Pos)                          /*!< LCD PAL185: G14_0 Mask              */
#define LCD_PAL185_B14_0_Pos                                  26                                                        /*!< LCD PAL185: B14_0 Position          */
#define LCD_PAL185_B14_0_Msk                                  (0x1fUL << LCD_PAL185_B14_0_Pos)                          /*!< LCD PAL185: B14_0 Mask              */
#define LCD_PAL185_I1_Pos                                     31                                                        /*!< LCD PAL185: I1 Position             */
#define LCD_PAL185_I1_Msk                                     (0x01UL << LCD_PAL185_I1_Pos)                             /*!< LCD PAL185: I1 Mask                 */

// ---------------------------------------  LCD_PAL186  -------------------------------------------
#define LCD_PAL186_R04_0_Pos                                  0                                                         /*!< LCD PAL186: R04_0 Position          */
#define LCD_PAL186_R04_0_Msk                                  (0x1fUL << LCD_PAL186_R04_0_Pos)                          /*!< LCD PAL186: R04_0 Mask              */
#define LCD_PAL186_G04_0_Pos                                  5                                                         /*!< LCD PAL186: G04_0 Position          */
#define LCD_PAL186_G04_0_Msk                                  (0x1fUL << LCD_PAL186_G04_0_Pos)                          /*!< LCD PAL186: G04_0 Mask              */
#define LCD_PAL186_B04_0_Pos                                  10                                                        /*!< LCD PAL186: B04_0 Position          */
#define LCD_PAL186_B04_0_Msk                                  (0x1fUL << LCD_PAL186_B04_0_Pos)                          /*!< LCD PAL186: B04_0 Mask              */
#define LCD_PAL186_I0_Pos                                     15                                                        /*!< LCD PAL186: I0 Position             */
#define LCD_PAL186_I0_Msk                                     (0x01UL << LCD_PAL186_I0_Pos)                             /*!< LCD PAL186: I0 Mask                 */
#define LCD_PAL186_R14_0_Pos                                  16                                                        /*!< LCD PAL186: R14_0 Position          */
#define LCD_PAL186_R14_0_Msk                                  (0x1fUL << LCD_PAL186_R14_0_Pos)                          /*!< LCD PAL186: R14_0 Mask              */
#define LCD_PAL186_G14_0_Pos                                  21                                                        /*!< LCD PAL186: G14_0 Position          */
#define LCD_PAL186_G14_0_Msk                                  (0x1fUL << LCD_PAL186_G14_0_Pos)                          /*!< LCD PAL186: G14_0 Mask              */
#define LCD_PAL186_B14_0_Pos                                  26                                                        /*!< LCD PAL186: B14_0 Position          */
#define LCD_PAL186_B14_0_Msk                                  (0x1fUL << LCD_PAL186_B14_0_Pos)                          /*!< LCD PAL186: B14_0 Mask              */
#define LCD_PAL186_I1_Pos                                     31                                                        /*!< LCD PAL186: I1 Position             */
#define LCD_PAL186_I1_Msk                                     (0x01UL << LCD_PAL186_I1_Pos)                             /*!< LCD PAL186: I1 Mask                 */

// ---------------------------------------  LCD_PAL187  -------------------------------------------
#define LCD_PAL187_R04_0_Pos                                  0                                                         /*!< LCD PAL187: R04_0 Position          */
#define LCD_PAL187_R04_0_Msk                                  (0x1fUL << LCD_PAL187_R04_0_Pos)                          /*!< LCD PAL187: R04_0 Mask              */
#define LCD_PAL187_G04_0_Pos                                  5                                                         /*!< LCD PAL187: G04_0 Position          */
#define LCD_PAL187_G04_0_Msk                                  (0x1fUL << LCD_PAL187_G04_0_Pos)                          /*!< LCD PAL187: G04_0 Mask              */
#define LCD_PAL187_B04_0_Pos                                  10                                                        /*!< LCD PAL187: B04_0 Position          */
#define LCD_PAL187_B04_0_Msk                                  (0x1fUL << LCD_PAL187_B04_0_Pos)                          /*!< LCD PAL187: B04_0 Mask              */
#define LCD_PAL187_I0_Pos                                     15                                                        /*!< LCD PAL187: I0 Position             */
#define LCD_PAL187_I0_Msk                                     (0x01UL << LCD_PAL187_I0_Pos)                             /*!< LCD PAL187: I0 Mask                 */
#define LCD_PAL187_R14_0_Pos                                  16                                                        /*!< LCD PAL187: R14_0 Position          */
#define LCD_PAL187_R14_0_Msk                                  (0x1fUL << LCD_PAL187_R14_0_Pos)                          /*!< LCD PAL187: R14_0 Mask              */
#define LCD_PAL187_G14_0_Pos                                  21                                                        /*!< LCD PAL187: G14_0 Position          */
#define LCD_PAL187_G14_0_Msk                                  (0x1fUL << LCD_PAL187_G14_0_Pos)                          /*!< LCD PAL187: G14_0 Mask              */
#define LCD_PAL187_B14_0_Pos                                  26                                                        /*!< LCD PAL187: B14_0 Position          */
#define LCD_PAL187_B14_0_Msk                                  (0x1fUL << LCD_PAL187_B14_0_Pos)                          /*!< LCD PAL187: B14_0 Mask              */
#define LCD_PAL187_I1_Pos                                     31                                                        /*!< LCD PAL187: I1 Position             */
#define LCD_PAL187_I1_Msk                                     (0x01UL << LCD_PAL187_I1_Pos)                             /*!< LCD PAL187: I1 Mask                 */

// ---------------------------------------  LCD_PAL188  -------------------------------------------
#define LCD_PAL188_R04_0_Pos                                  0                                                         /*!< LCD PAL188: R04_0 Position          */
#define LCD_PAL188_R04_0_Msk                                  (0x1fUL << LCD_PAL188_R04_0_Pos)                          /*!< LCD PAL188: R04_0 Mask              */
#define LCD_PAL188_G04_0_Pos                                  5                                                         /*!< LCD PAL188: G04_0 Position          */
#define LCD_PAL188_G04_0_Msk                                  (0x1fUL << LCD_PAL188_G04_0_Pos)                          /*!< LCD PAL188: G04_0 Mask              */
#define LCD_PAL188_B04_0_Pos                                  10                                                        /*!< LCD PAL188: B04_0 Position          */
#define LCD_PAL188_B04_0_Msk                                  (0x1fUL << LCD_PAL188_B04_0_Pos)                          /*!< LCD PAL188: B04_0 Mask              */
#define LCD_PAL188_I0_Pos                                     15                                                        /*!< LCD PAL188: I0 Position             */
#define LCD_PAL188_I0_Msk                                     (0x01UL << LCD_PAL188_I0_Pos)                             /*!< LCD PAL188: I0 Mask                 */
#define LCD_PAL188_R14_0_Pos                                  16                                                        /*!< LCD PAL188: R14_0 Position          */
#define LCD_PAL188_R14_0_Msk                                  (0x1fUL << LCD_PAL188_R14_0_Pos)                          /*!< LCD PAL188: R14_0 Mask              */
#define LCD_PAL188_G14_0_Pos                                  21                                                        /*!< LCD PAL188: G14_0 Position          */
#define LCD_PAL188_G14_0_Msk                                  (0x1fUL << LCD_PAL188_G14_0_Pos)                          /*!< LCD PAL188: G14_0 Mask              */
#define LCD_PAL188_B14_0_Pos                                  26                                                        /*!< LCD PAL188: B14_0 Position          */
#define LCD_PAL188_B14_0_Msk                                  (0x1fUL << LCD_PAL188_B14_0_Pos)                          /*!< LCD PAL188: B14_0 Mask              */
#define LCD_PAL188_I1_Pos                                     31                                                        /*!< LCD PAL188: I1 Position             */
#define LCD_PAL188_I1_Msk                                     (0x01UL << LCD_PAL188_I1_Pos)                             /*!< LCD PAL188: I1 Mask                 */

// ---------------------------------------  LCD_PAL189  -------------------------------------------
#define LCD_PAL189_R04_0_Pos                                  0                                                         /*!< LCD PAL189: R04_0 Position          */
#define LCD_PAL189_R04_0_Msk                                  (0x1fUL << LCD_PAL189_R04_0_Pos)                          /*!< LCD PAL189: R04_0 Mask              */
#define LCD_PAL189_G04_0_Pos                                  5                                                         /*!< LCD PAL189: G04_0 Position          */
#define LCD_PAL189_G04_0_Msk                                  (0x1fUL << LCD_PAL189_G04_0_Pos)                          /*!< LCD PAL189: G04_0 Mask              */
#define LCD_PAL189_B04_0_Pos                                  10                                                        /*!< LCD PAL189: B04_0 Position          */
#define LCD_PAL189_B04_0_Msk                                  (0x1fUL << LCD_PAL189_B04_0_Pos)                          /*!< LCD PAL189: B04_0 Mask              */
#define LCD_PAL189_I0_Pos                                     15                                                        /*!< LCD PAL189: I0 Position             */
#define LCD_PAL189_I0_Msk                                     (0x01UL << LCD_PAL189_I0_Pos)                             /*!< LCD PAL189: I0 Mask                 */
#define LCD_PAL189_R14_0_Pos                                  16                                                        /*!< LCD PAL189: R14_0 Position          */
#define LCD_PAL189_R14_0_Msk                                  (0x1fUL << LCD_PAL189_R14_0_Pos)                          /*!< LCD PAL189: R14_0 Mask              */
#define LCD_PAL189_G14_0_Pos                                  21                                                        /*!< LCD PAL189: G14_0 Position          */
#define LCD_PAL189_G14_0_Msk                                  (0x1fUL << LCD_PAL189_G14_0_Pos)                          /*!< LCD PAL189: G14_0 Mask              */
#define LCD_PAL189_B14_0_Pos                                  26                                                        /*!< LCD PAL189: B14_0 Position          */
#define LCD_PAL189_B14_0_Msk                                  (0x1fUL << LCD_PAL189_B14_0_Pos)                          /*!< LCD PAL189: B14_0 Mask              */
#define LCD_PAL189_I1_Pos                                     31                                                        /*!< LCD PAL189: I1 Position             */
#define LCD_PAL189_I1_Msk                                     (0x01UL << LCD_PAL189_I1_Pos)                             /*!< LCD PAL189: I1 Mask                 */

// ---------------------------------------  LCD_PAL190  -------------------------------------------
#define LCD_PAL190_R04_0_Pos                                  0                                                         /*!< LCD PAL190: R04_0 Position          */
#define LCD_PAL190_R04_0_Msk                                  (0x1fUL << LCD_PAL190_R04_0_Pos)                          /*!< LCD PAL190: R04_0 Mask              */
#define LCD_PAL190_G04_0_Pos                                  5                                                         /*!< LCD PAL190: G04_0 Position          */
#define LCD_PAL190_G04_0_Msk                                  (0x1fUL << LCD_PAL190_G04_0_Pos)                          /*!< LCD PAL190: G04_0 Mask              */
#define LCD_PAL190_B04_0_Pos                                  10                                                        /*!< LCD PAL190: B04_0 Position          */
#define LCD_PAL190_B04_0_Msk                                  (0x1fUL << LCD_PAL190_B04_0_Pos)                          /*!< LCD PAL190: B04_0 Mask              */
#define LCD_PAL190_I0_Pos                                     15                                                        /*!< LCD PAL190: I0 Position             */
#define LCD_PAL190_I0_Msk                                     (0x01UL << LCD_PAL190_I0_Pos)                             /*!< LCD PAL190: I0 Mask                 */
#define LCD_PAL190_R14_0_Pos                                  16                                                        /*!< LCD PAL190: R14_0 Position          */
#define LCD_PAL190_R14_0_Msk                                  (0x1fUL << LCD_PAL190_R14_0_Pos)                          /*!< LCD PAL190: R14_0 Mask              */
#define LCD_PAL190_G14_0_Pos                                  21                                                        /*!< LCD PAL190: G14_0 Position          */
#define LCD_PAL190_G14_0_Msk                                  (0x1fUL << LCD_PAL190_G14_0_Pos)                          /*!< LCD PAL190: G14_0 Mask              */
#define LCD_PAL190_B14_0_Pos                                  26                                                        /*!< LCD PAL190: B14_0 Position          */
#define LCD_PAL190_B14_0_Msk                                  (0x1fUL << LCD_PAL190_B14_0_Pos)                          /*!< LCD PAL190: B14_0 Mask              */
#define LCD_PAL190_I1_Pos                                     31                                                        /*!< LCD PAL190: I1 Position             */
#define LCD_PAL190_I1_Msk                                     (0x01UL << LCD_PAL190_I1_Pos)                             /*!< LCD PAL190: I1 Mask                 */

// ---------------------------------------  LCD_PAL191  -------------------------------------------
#define LCD_PAL191_R04_0_Pos                                  0                                                         /*!< LCD PAL191: R04_0 Position          */
#define LCD_PAL191_R04_0_Msk                                  (0x1fUL << LCD_PAL191_R04_0_Pos)                          /*!< LCD PAL191: R04_0 Mask              */
#define LCD_PAL191_G04_0_Pos                                  5                                                         /*!< LCD PAL191: G04_0 Position          */
#define LCD_PAL191_G04_0_Msk                                  (0x1fUL << LCD_PAL191_G04_0_Pos)                          /*!< LCD PAL191: G04_0 Mask              */
#define LCD_PAL191_B04_0_Pos                                  10                                                        /*!< LCD PAL191: B04_0 Position          */
#define LCD_PAL191_B04_0_Msk                                  (0x1fUL << LCD_PAL191_B04_0_Pos)                          /*!< LCD PAL191: B04_0 Mask              */
#define LCD_PAL191_I0_Pos                                     15                                                        /*!< LCD PAL191: I0 Position             */
#define LCD_PAL191_I0_Msk                                     (0x01UL << LCD_PAL191_I0_Pos)                             /*!< LCD PAL191: I0 Mask                 */
#define LCD_PAL191_R14_0_Pos                                  16                                                        /*!< LCD PAL191: R14_0 Position          */
#define LCD_PAL191_R14_0_Msk                                  (0x1fUL << LCD_PAL191_R14_0_Pos)                          /*!< LCD PAL191: R14_0 Mask              */
#define LCD_PAL191_G14_0_Pos                                  21                                                        /*!< LCD PAL191: G14_0 Position          */
#define LCD_PAL191_G14_0_Msk                                  (0x1fUL << LCD_PAL191_G14_0_Pos)                          /*!< LCD PAL191: G14_0 Mask              */
#define LCD_PAL191_B14_0_Pos                                  26                                                        /*!< LCD PAL191: B14_0 Position          */
#define LCD_PAL191_B14_0_Msk                                  (0x1fUL << LCD_PAL191_B14_0_Pos)                          /*!< LCD PAL191: B14_0 Mask              */
#define LCD_PAL191_I1_Pos                                     31                                                        /*!< LCD PAL191: I1 Position             */
#define LCD_PAL191_I1_Msk                                     (0x01UL << LCD_PAL191_I1_Pos)                             /*!< LCD PAL191: I1 Mask                 */

// ---------------------------------------  LCD_PAL192  -------------------------------------------
#define LCD_PAL192_R04_0_Pos                                  0                                                         /*!< LCD PAL192: R04_0 Position          */
#define LCD_PAL192_R04_0_Msk                                  (0x1fUL << LCD_PAL192_R04_0_Pos)                          /*!< LCD PAL192: R04_0 Mask              */
#define LCD_PAL192_G04_0_Pos                                  5                                                         /*!< LCD PAL192: G04_0 Position          */
#define LCD_PAL192_G04_0_Msk                                  (0x1fUL << LCD_PAL192_G04_0_Pos)                          /*!< LCD PAL192: G04_0 Mask              */
#define LCD_PAL192_B04_0_Pos                                  10                                                        /*!< LCD PAL192: B04_0 Position          */
#define LCD_PAL192_B04_0_Msk                                  (0x1fUL << LCD_PAL192_B04_0_Pos)                          /*!< LCD PAL192: B04_0 Mask              */
#define LCD_PAL192_I0_Pos                                     15                                                        /*!< LCD PAL192: I0 Position             */
#define LCD_PAL192_I0_Msk                                     (0x01UL << LCD_PAL192_I0_Pos)                             /*!< LCD PAL192: I0 Mask                 */
#define LCD_PAL192_R14_0_Pos                                  16                                                        /*!< LCD PAL192: R14_0 Position          */
#define LCD_PAL192_R14_0_Msk                                  (0x1fUL << LCD_PAL192_R14_0_Pos)                          /*!< LCD PAL192: R14_0 Mask              */
#define LCD_PAL192_G14_0_Pos                                  21                                                        /*!< LCD PAL192: G14_0 Position          */
#define LCD_PAL192_G14_0_Msk                                  (0x1fUL << LCD_PAL192_G14_0_Pos)                          /*!< LCD PAL192: G14_0 Mask              */
#define LCD_PAL192_B14_0_Pos                                  26                                                        /*!< LCD PAL192: B14_0 Position          */
#define LCD_PAL192_B14_0_Msk                                  (0x1fUL << LCD_PAL192_B14_0_Pos)                          /*!< LCD PAL192: B14_0 Mask              */
#define LCD_PAL192_I1_Pos                                     31                                                        /*!< LCD PAL192: I1 Position             */
#define LCD_PAL192_I1_Msk                                     (0x01UL << LCD_PAL192_I1_Pos)                             /*!< LCD PAL192: I1 Mask                 */

// ---------------------------------------  LCD_PAL193  -------------------------------------------
#define LCD_PAL193_R04_0_Pos                                  0                                                         /*!< LCD PAL193: R04_0 Position          */
#define LCD_PAL193_R04_0_Msk                                  (0x1fUL << LCD_PAL193_R04_0_Pos)                          /*!< LCD PAL193: R04_0 Mask              */
#define LCD_PAL193_G04_0_Pos                                  5                                                         /*!< LCD PAL193: G04_0 Position          */
#define LCD_PAL193_G04_0_Msk                                  (0x1fUL << LCD_PAL193_G04_0_Pos)                          /*!< LCD PAL193: G04_0 Mask              */
#define LCD_PAL193_B04_0_Pos                                  10                                                        /*!< LCD PAL193: B04_0 Position          */
#define LCD_PAL193_B04_0_Msk                                  (0x1fUL << LCD_PAL193_B04_0_Pos)                          /*!< LCD PAL193: B04_0 Mask              */
#define LCD_PAL193_I0_Pos                                     15                                                        /*!< LCD PAL193: I0 Position             */
#define LCD_PAL193_I0_Msk                                     (0x01UL << LCD_PAL193_I0_Pos)                             /*!< LCD PAL193: I0 Mask                 */
#define LCD_PAL193_R14_0_Pos                                  16                                                        /*!< LCD PAL193: R14_0 Position          */
#define LCD_PAL193_R14_0_Msk                                  (0x1fUL << LCD_PAL193_R14_0_Pos)                          /*!< LCD PAL193: R14_0 Mask              */
#define LCD_PAL193_G14_0_Pos                                  21                                                        /*!< LCD PAL193: G14_0 Position          */
#define LCD_PAL193_G14_0_Msk                                  (0x1fUL << LCD_PAL193_G14_0_Pos)                          /*!< LCD PAL193: G14_0 Mask              */
#define LCD_PAL193_B14_0_Pos                                  26                                                        /*!< LCD PAL193: B14_0 Position          */
#define LCD_PAL193_B14_0_Msk                                  (0x1fUL << LCD_PAL193_B14_0_Pos)                          /*!< LCD PAL193: B14_0 Mask              */
#define LCD_PAL193_I1_Pos                                     31                                                        /*!< LCD PAL193: I1 Position             */
#define LCD_PAL193_I1_Msk                                     (0x01UL << LCD_PAL193_I1_Pos)                             /*!< LCD PAL193: I1 Mask                 */

// ---------------------------------------  LCD_PAL194  -------------------------------------------
#define LCD_PAL194_R04_0_Pos                                  0                                                         /*!< LCD PAL194: R04_0 Position          */
#define LCD_PAL194_R04_0_Msk                                  (0x1fUL << LCD_PAL194_R04_0_Pos)                          /*!< LCD PAL194: R04_0 Mask              */
#define LCD_PAL194_G04_0_Pos                                  5                                                         /*!< LCD PAL194: G04_0 Position          */
#define LCD_PAL194_G04_0_Msk                                  (0x1fUL << LCD_PAL194_G04_0_Pos)                          /*!< LCD PAL194: G04_0 Mask              */
#define LCD_PAL194_B04_0_Pos                                  10                                                        /*!< LCD PAL194: B04_0 Position          */
#define LCD_PAL194_B04_0_Msk                                  (0x1fUL << LCD_PAL194_B04_0_Pos)                          /*!< LCD PAL194: B04_0 Mask              */
#define LCD_PAL194_I0_Pos                                     15                                                        /*!< LCD PAL194: I0 Position             */
#define LCD_PAL194_I0_Msk                                     (0x01UL << LCD_PAL194_I0_Pos)                             /*!< LCD PAL194: I0 Mask                 */
#define LCD_PAL194_R14_0_Pos                                  16                                                        /*!< LCD PAL194: R14_0 Position          */
#define LCD_PAL194_R14_0_Msk                                  (0x1fUL << LCD_PAL194_R14_0_Pos)                          /*!< LCD PAL194: R14_0 Mask              */
#define LCD_PAL194_G14_0_Pos                                  21                                                        /*!< LCD PAL194: G14_0 Position          */
#define LCD_PAL194_G14_0_Msk                                  (0x1fUL << LCD_PAL194_G14_0_Pos)                          /*!< LCD PAL194: G14_0 Mask              */
#define LCD_PAL194_B14_0_Pos                                  26                                                        /*!< LCD PAL194: B14_0 Position          */
#define LCD_PAL194_B14_0_Msk                                  (0x1fUL << LCD_PAL194_B14_0_Pos)                          /*!< LCD PAL194: B14_0 Mask              */
#define LCD_PAL194_I1_Pos                                     31                                                        /*!< LCD PAL194: I1 Position             */
#define LCD_PAL194_I1_Msk                                     (0x01UL << LCD_PAL194_I1_Pos)                             /*!< LCD PAL194: I1 Mask                 */

// ---------------------------------------  LCD_PAL195  -------------------------------------------
#define LCD_PAL195_R04_0_Pos                                  0                                                         /*!< LCD PAL195: R04_0 Position          */
#define LCD_PAL195_R04_0_Msk                                  (0x1fUL << LCD_PAL195_R04_0_Pos)                          /*!< LCD PAL195: R04_0 Mask              */
#define LCD_PAL195_G04_0_Pos                                  5                                                         /*!< LCD PAL195: G04_0 Position          */
#define LCD_PAL195_G04_0_Msk                                  (0x1fUL << LCD_PAL195_G04_0_Pos)                          /*!< LCD PAL195: G04_0 Mask              */
#define LCD_PAL195_B04_0_Pos                                  10                                                        /*!< LCD PAL195: B04_0 Position          */
#define LCD_PAL195_B04_0_Msk                                  (0x1fUL << LCD_PAL195_B04_0_Pos)                          /*!< LCD PAL195: B04_0 Mask              */
#define LCD_PAL195_I0_Pos                                     15                                                        /*!< LCD PAL195: I0 Position             */
#define LCD_PAL195_I0_Msk                                     (0x01UL << LCD_PAL195_I0_Pos)                             /*!< LCD PAL195: I0 Mask                 */
#define LCD_PAL195_R14_0_Pos                                  16                                                        /*!< LCD PAL195: R14_0 Position          */
#define LCD_PAL195_R14_0_Msk                                  (0x1fUL << LCD_PAL195_R14_0_Pos)                          /*!< LCD PAL195: R14_0 Mask              */
#define LCD_PAL195_G14_0_Pos                                  21                                                        /*!< LCD PAL195: G14_0 Position          */
#define LCD_PAL195_G14_0_Msk                                  (0x1fUL << LCD_PAL195_G14_0_Pos)                          /*!< LCD PAL195: G14_0 Mask              */
#define LCD_PAL195_B14_0_Pos                                  26                                                        /*!< LCD PAL195: B14_0 Position          */
#define LCD_PAL195_B14_0_Msk                                  (0x1fUL << LCD_PAL195_B14_0_Pos)                          /*!< LCD PAL195: B14_0 Mask              */
#define LCD_PAL195_I1_Pos                                     31                                                        /*!< LCD PAL195: I1 Position             */
#define LCD_PAL195_I1_Msk                                     (0x01UL << LCD_PAL195_I1_Pos)                             /*!< LCD PAL195: I1 Mask                 */

// ---------------------------------------  LCD_PAL196  -------------------------------------------
#define LCD_PAL196_R04_0_Pos                                  0                                                         /*!< LCD PAL196: R04_0 Position          */
#define LCD_PAL196_R04_0_Msk                                  (0x1fUL << LCD_PAL196_R04_0_Pos)                          /*!< LCD PAL196: R04_0 Mask              */
#define LCD_PAL196_G04_0_Pos                                  5                                                         /*!< LCD PAL196: G04_0 Position          */
#define LCD_PAL196_G04_0_Msk                                  (0x1fUL << LCD_PAL196_G04_0_Pos)                          /*!< LCD PAL196: G04_0 Mask              */
#define LCD_PAL196_B04_0_Pos                                  10                                                        /*!< LCD PAL196: B04_0 Position          */
#define LCD_PAL196_B04_0_Msk                                  (0x1fUL << LCD_PAL196_B04_0_Pos)                          /*!< LCD PAL196: B04_0 Mask              */
#define LCD_PAL196_I0_Pos                                     15                                                        /*!< LCD PAL196: I0 Position             */
#define LCD_PAL196_I0_Msk                                     (0x01UL << LCD_PAL196_I0_Pos)                             /*!< LCD PAL196: I0 Mask                 */
#define LCD_PAL196_R14_0_Pos                                  16                                                        /*!< LCD PAL196: R14_0 Position          */
#define LCD_PAL196_R14_0_Msk                                  (0x1fUL << LCD_PAL196_R14_0_Pos)                          /*!< LCD PAL196: R14_0 Mask              */
#define LCD_PAL196_G14_0_Pos                                  21                                                        /*!< LCD PAL196: G14_0 Position          */
#define LCD_PAL196_G14_0_Msk                                  (0x1fUL << LCD_PAL196_G14_0_Pos)                          /*!< LCD PAL196: G14_0 Mask              */
#define LCD_PAL196_B14_0_Pos                                  26                                                        /*!< LCD PAL196: B14_0 Position          */
#define LCD_PAL196_B14_0_Msk                                  (0x1fUL << LCD_PAL196_B14_0_Pos)                          /*!< LCD PAL196: B14_0 Mask              */
#define LCD_PAL196_I1_Pos                                     31                                                        /*!< LCD PAL196: I1 Position             */
#define LCD_PAL196_I1_Msk                                     (0x01UL << LCD_PAL196_I1_Pos)                             /*!< LCD PAL196: I1 Mask                 */

// ---------------------------------------  LCD_PAL197  -------------------------------------------
#define LCD_PAL197_R04_0_Pos                                  0                                                         /*!< LCD PAL197: R04_0 Position          */
#define LCD_PAL197_R04_0_Msk                                  (0x1fUL << LCD_PAL197_R04_0_Pos)                          /*!< LCD PAL197: R04_0 Mask              */
#define LCD_PAL197_G04_0_Pos                                  5                                                         /*!< LCD PAL197: G04_0 Position          */
#define LCD_PAL197_G04_0_Msk                                  (0x1fUL << LCD_PAL197_G04_0_Pos)                          /*!< LCD PAL197: G04_0 Mask              */
#define LCD_PAL197_B04_0_Pos                                  10                                                        /*!< LCD PAL197: B04_0 Position          */
#define LCD_PAL197_B04_0_Msk                                  (0x1fUL << LCD_PAL197_B04_0_Pos)                          /*!< LCD PAL197: B04_0 Mask              */
#define LCD_PAL197_I0_Pos                                     15                                                        /*!< LCD PAL197: I0 Position             */
#define LCD_PAL197_I0_Msk                                     (0x01UL << LCD_PAL197_I0_Pos)                             /*!< LCD PAL197: I0 Mask                 */
#define LCD_PAL197_R14_0_Pos                                  16                                                        /*!< LCD PAL197: R14_0 Position          */
#define LCD_PAL197_R14_0_Msk                                  (0x1fUL << LCD_PAL197_R14_0_Pos)                          /*!< LCD PAL197: R14_0 Mask              */
#define LCD_PAL197_G14_0_Pos                                  21                                                        /*!< LCD PAL197: G14_0 Position          */
#define LCD_PAL197_G14_0_Msk                                  (0x1fUL << LCD_PAL197_G14_0_Pos)                          /*!< LCD PAL197: G14_0 Mask              */
#define LCD_PAL197_B14_0_Pos                                  26                                                        /*!< LCD PAL197: B14_0 Position          */
#define LCD_PAL197_B14_0_Msk                                  (0x1fUL << LCD_PAL197_B14_0_Pos)                          /*!< LCD PAL197: B14_0 Mask              */
#define LCD_PAL197_I1_Pos                                     31                                                        /*!< LCD PAL197: I1 Position             */
#define LCD_PAL197_I1_Msk                                     (0x01UL << LCD_PAL197_I1_Pos)                             /*!< LCD PAL197: I1 Mask                 */

// ---------------------------------------  LCD_PAL198  -------------------------------------------
#define LCD_PAL198_R04_0_Pos                                  0                                                         /*!< LCD PAL198: R04_0 Position          */
#define LCD_PAL198_R04_0_Msk                                  (0x1fUL << LCD_PAL198_R04_0_Pos)                          /*!< LCD PAL198: R04_0 Mask              */
#define LCD_PAL198_G04_0_Pos                                  5                                                         /*!< LCD PAL198: G04_0 Position          */
#define LCD_PAL198_G04_0_Msk                                  (0x1fUL << LCD_PAL198_G04_0_Pos)                          /*!< LCD PAL198: G04_0 Mask              */
#define LCD_PAL198_B04_0_Pos                                  10                                                        /*!< LCD PAL198: B04_0 Position          */
#define LCD_PAL198_B04_0_Msk                                  (0x1fUL << LCD_PAL198_B04_0_Pos)                          /*!< LCD PAL198: B04_0 Mask              */
#define LCD_PAL198_I0_Pos                                     15                                                        /*!< LCD PAL198: I0 Position             */
#define LCD_PAL198_I0_Msk                                     (0x01UL << LCD_PAL198_I0_Pos)                             /*!< LCD PAL198: I0 Mask                 */
#define LCD_PAL198_R14_0_Pos                                  16                                                        /*!< LCD PAL198: R14_0 Position          */
#define LCD_PAL198_R14_0_Msk                                  (0x1fUL << LCD_PAL198_R14_0_Pos)                          /*!< LCD PAL198: R14_0 Mask              */
#define LCD_PAL198_G14_0_Pos                                  21                                                        /*!< LCD PAL198: G14_0 Position          */
#define LCD_PAL198_G14_0_Msk                                  (0x1fUL << LCD_PAL198_G14_0_Pos)                          /*!< LCD PAL198: G14_0 Mask              */
#define LCD_PAL198_B14_0_Pos                                  26                                                        /*!< LCD PAL198: B14_0 Position          */
#define LCD_PAL198_B14_0_Msk                                  (0x1fUL << LCD_PAL198_B14_0_Pos)                          /*!< LCD PAL198: B14_0 Mask              */
#define LCD_PAL198_I1_Pos                                     31                                                        /*!< LCD PAL198: I1 Position             */
#define LCD_PAL198_I1_Msk                                     (0x01UL << LCD_PAL198_I1_Pos)                             /*!< LCD PAL198: I1 Mask                 */

// ---------------------------------------  LCD_PAL199  -------------------------------------------
#define LCD_PAL199_R04_0_Pos                                  0                                                         /*!< LCD PAL199: R04_0 Position          */
#define LCD_PAL199_R04_0_Msk                                  (0x1fUL << LCD_PAL199_R04_0_Pos)                          /*!< LCD PAL199: R04_0 Mask              */
#define LCD_PAL199_G04_0_Pos                                  5                                                         /*!< LCD PAL199: G04_0 Position          */
#define LCD_PAL199_G04_0_Msk                                  (0x1fUL << LCD_PAL199_G04_0_Pos)                          /*!< LCD PAL199: G04_0 Mask              */
#define LCD_PAL199_B04_0_Pos                                  10                                                        /*!< LCD PAL199: B04_0 Position          */
#define LCD_PAL199_B04_0_Msk                                  (0x1fUL << LCD_PAL199_B04_0_Pos)                          /*!< LCD PAL199: B04_0 Mask              */
#define LCD_PAL199_I0_Pos                                     15                                                        /*!< LCD PAL199: I0 Position             */
#define LCD_PAL199_I0_Msk                                     (0x01UL << LCD_PAL199_I0_Pos)                             /*!< LCD PAL199: I0 Mask                 */
#define LCD_PAL199_R14_0_Pos                                  16                                                        /*!< LCD PAL199: R14_0 Position          */
#define LCD_PAL199_R14_0_Msk                                  (0x1fUL << LCD_PAL199_R14_0_Pos)                          /*!< LCD PAL199: R14_0 Mask              */
#define LCD_PAL199_G14_0_Pos                                  21                                                        /*!< LCD PAL199: G14_0 Position          */
#define LCD_PAL199_G14_0_Msk                                  (0x1fUL << LCD_PAL199_G14_0_Pos)                          /*!< LCD PAL199: G14_0 Mask              */
#define LCD_PAL199_B14_0_Pos                                  26                                                        /*!< LCD PAL199: B14_0 Position          */
#define LCD_PAL199_B14_0_Msk                                  (0x1fUL << LCD_PAL199_B14_0_Pos)                          /*!< LCD PAL199: B14_0 Mask              */
#define LCD_PAL199_I1_Pos                                     31                                                        /*!< LCD PAL199: I1 Position             */
#define LCD_PAL199_I1_Msk                                     (0x01UL << LCD_PAL199_I1_Pos)                             /*!< LCD PAL199: I1 Mask                 */

// ---------------------------------------  LCD_PAL200  -------------------------------------------
#define LCD_PAL200_R04_0_Pos                                  0                                                         /*!< LCD PAL200: R04_0 Position          */
#define LCD_PAL200_R04_0_Msk                                  (0x1fUL << LCD_PAL200_R04_0_Pos)                          /*!< LCD PAL200: R04_0 Mask              */
#define LCD_PAL200_G04_0_Pos                                  5                                                         /*!< LCD PAL200: G04_0 Position          */
#define LCD_PAL200_G04_0_Msk                                  (0x1fUL << LCD_PAL200_G04_0_Pos)                          /*!< LCD PAL200: G04_0 Mask              */
#define LCD_PAL200_B04_0_Pos                                  10                                                        /*!< LCD PAL200: B04_0 Position          */
#define LCD_PAL200_B04_0_Msk                                  (0x1fUL << LCD_PAL200_B04_0_Pos)                          /*!< LCD PAL200: B04_0 Mask              */
#define LCD_PAL200_I0_Pos                                     15                                                        /*!< LCD PAL200: I0 Position             */
#define LCD_PAL200_I0_Msk                                     (0x01UL << LCD_PAL200_I0_Pos)                             /*!< LCD PAL200: I0 Mask                 */
#define LCD_PAL200_R14_0_Pos                                  16                                                        /*!< LCD PAL200: R14_0 Position          */
#define LCD_PAL200_R14_0_Msk                                  (0x1fUL << LCD_PAL200_R14_0_Pos)                          /*!< LCD PAL200: R14_0 Mask              */
#define LCD_PAL200_G14_0_Pos                                  21                                                        /*!< LCD PAL200: G14_0 Position          */
#define LCD_PAL200_G14_0_Msk                                  (0x1fUL << LCD_PAL200_G14_0_Pos)                          /*!< LCD PAL200: G14_0 Mask              */
#define LCD_PAL200_B14_0_Pos                                  26                                                        /*!< LCD PAL200: B14_0 Position          */
#define LCD_PAL200_B14_0_Msk                                  (0x1fUL << LCD_PAL200_B14_0_Pos)                          /*!< LCD PAL200: B14_0 Mask              */
#define LCD_PAL200_I1_Pos                                     31                                                        /*!< LCD PAL200: I1 Position             */
#define LCD_PAL200_I1_Msk                                     (0x01UL << LCD_PAL200_I1_Pos)                             /*!< LCD PAL200: I1 Mask                 */

// ---------------------------------------  LCD_PAL201  -------------------------------------------
#define LCD_PAL201_R04_0_Pos                                  0                                                         /*!< LCD PAL201: R04_0 Position          */
#define LCD_PAL201_R04_0_Msk                                  (0x1fUL << LCD_PAL201_R04_0_Pos)                          /*!< LCD PAL201: R04_0 Mask              */
#define LCD_PAL201_G04_0_Pos                                  5                                                         /*!< LCD PAL201: G04_0 Position          */
#define LCD_PAL201_G04_0_Msk                                  (0x1fUL << LCD_PAL201_G04_0_Pos)                          /*!< LCD PAL201: G04_0 Mask              */
#define LCD_PAL201_B04_0_Pos                                  10                                                        /*!< LCD PAL201: B04_0 Position          */
#define LCD_PAL201_B04_0_Msk                                  (0x1fUL << LCD_PAL201_B04_0_Pos)                          /*!< LCD PAL201: B04_0 Mask              */
#define LCD_PAL201_I0_Pos                                     15                                                        /*!< LCD PAL201: I0 Position             */
#define LCD_PAL201_I0_Msk                                     (0x01UL << LCD_PAL201_I0_Pos)                             /*!< LCD PAL201: I0 Mask                 */
#define LCD_PAL201_R14_0_Pos                                  16                                                        /*!< LCD PAL201: R14_0 Position          */
#define LCD_PAL201_R14_0_Msk                                  (0x1fUL << LCD_PAL201_R14_0_Pos)                          /*!< LCD PAL201: R14_0 Mask              */
#define LCD_PAL201_G14_0_Pos                                  21                                                        /*!< LCD PAL201: G14_0 Position          */
#define LCD_PAL201_G14_0_Msk                                  (0x1fUL << LCD_PAL201_G14_0_Pos)                          /*!< LCD PAL201: G14_0 Mask              */
#define LCD_PAL201_B14_0_Pos                                  26                                                        /*!< LCD PAL201: B14_0 Position          */
#define LCD_PAL201_B14_0_Msk                                  (0x1fUL << LCD_PAL201_B14_0_Pos)                          /*!< LCD PAL201: B14_0 Mask              */
#define LCD_PAL201_I1_Pos                                     31                                                        /*!< LCD PAL201: I1 Position             */
#define LCD_PAL201_I1_Msk                                     (0x01UL << LCD_PAL201_I1_Pos)                             /*!< LCD PAL201: I1 Mask                 */

// ---------------------------------------  LCD_PAL202  -------------------------------------------
#define LCD_PAL202_R04_0_Pos                                  0                                                         /*!< LCD PAL202: R04_0 Position          */
#define LCD_PAL202_R04_0_Msk                                  (0x1fUL << LCD_PAL202_R04_0_Pos)                          /*!< LCD PAL202: R04_0 Mask              */
#define LCD_PAL202_G04_0_Pos                                  5                                                         /*!< LCD PAL202: G04_0 Position          */
#define LCD_PAL202_G04_0_Msk                                  (0x1fUL << LCD_PAL202_G04_0_Pos)                          /*!< LCD PAL202: G04_0 Mask              */
#define LCD_PAL202_B04_0_Pos                                  10                                                        /*!< LCD PAL202: B04_0 Position          */
#define LCD_PAL202_B04_0_Msk                                  (0x1fUL << LCD_PAL202_B04_0_Pos)                          /*!< LCD PAL202: B04_0 Mask              */
#define LCD_PAL202_I0_Pos                                     15                                                        /*!< LCD PAL202: I0 Position             */
#define LCD_PAL202_I0_Msk                                     (0x01UL << LCD_PAL202_I0_Pos)                             /*!< LCD PAL202: I0 Mask                 */
#define LCD_PAL202_R14_0_Pos                                  16                                                        /*!< LCD PAL202: R14_0 Position          */
#define LCD_PAL202_R14_0_Msk                                  (0x1fUL << LCD_PAL202_R14_0_Pos)                          /*!< LCD PAL202: R14_0 Mask              */
#define LCD_PAL202_G14_0_Pos                                  21                                                        /*!< LCD PAL202: G14_0 Position          */
#define LCD_PAL202_G14_0_Msk                                  (0x1fUL << LCD_PAL202_G14_0_Pos)                          /*!< LCD PAL202: G14_0 Mask              */
#define LCD_PAL202_B14_0_Pos                                  26                                                        /*!< LCD PAL202: B14_0 Position          */
#define LCD_PAL202_B14_0_Msk                                  (0x1fUL << LCD_PAL202_B14_0_Pos)                          /*!< LCD PAL202: B14_0 Mask              */
#define LCD_PAL202_I1_Pos                                     31                                                        /*!< LCD PAL202: I1 Position             */
#define LCD_PAL202_I1_Msk                                     (0x01UL << LCD_PAL202_I1_Pos)                             /*!< LCD PAL202: I1 Mask                 */

// ---------------------------------------  LCD_PAL203  -------------------------------------------
#define LCD_PAL203_R04_0_Pos                                  0                                                         /*!< LCD PAL203: R04_0 Position          */
#define LCD_PAL203_R04_0_Msk                                  (0x1fUL << LCD_PAL203_R04_0_Pos)                          /*!< LCD PAL203: R04_0 Mask              */
#define LCD_PAL203_G04_0_Pos                                  5                                                         /*!< LCD PAL203: G04_0 Position          */
#define LCD_PAL203_G04_0_Msk                                  (0x1fUL << LCD_PAL203_G04_0_Pos)                          /*!< LCD PAL203: G04_0 Mask              */
#define LCD_PAL203_B04_0_Pos                                  10                                                        /*!< LCD PAL203: B04_0 Position          */
#define LCD_PAL203_B04_0_Msk                                  (0x1fUL << LCD_PAL203_B04_0_Pos)                          /*!< LCD PAL203: B04_0 Mask              */
#define LCD_PAL203_I0_Pos                                     15                                                        /*!< LCD PAL203: I0 Position             */
#define LCD_PAL203_I0_Msk                                     (0x01UL << LCD_PAL203_I0_Pos)                             /*!< LCD PAL203: I0 Mask                 */
#define LCD_PAL203_R14_0_Pos                                  16                                                        /*!< LCD PAL203: R14_0 Position          */
#define LCD_PAL203_R14_0_Msk                                  (0x1fUL << LCD_PAL203_R14_0_Pos)                          /*!< LCD PAL203: R14_0 Mask              */
#define LCD_PAL203_G14_0_Pos                                  21                                                        /*!< LCD PAL203: G14_0 Position          */
#define LCD_PAL203_G14_0_Msk                                  (0x1fUL << LCD_PAL203_G14_0_Pos)                          /*!< LCD PAL203: G14_0 Mask              */
#define LCD_PAL203_B14_0_Pos                                  26                                                        /*!< LCD PAL203: B14_0 Position          */
#define LCD_PAL203_B14_0_Msk                                  (0x1fUL << LCD_PAL203_B14_0_Pos)                          /*!< LCD PAL203: B14_0 Mask              */
#define LCD_PAL203_I1_Pos                                     31                                                        /*!< LCD PAL203: I1 Position             */
#define LCD_PAL203_I1_Msk                                     (0x01UL << LCD_PAL203_I1_Pos)                             /*!< LCD PAL203: I1 Mask                 */

// ---------------------------------------  LCD_PAL204  -------------------------------------------
#define LCD_PAL204_R04_0_Pos                                  0                                                         /*!< LCD PAL204: R04_0 Position          */
#define LCD_PAL204_R04_0_Msk                                  (0x1fUL << LCD_PAL204_R04_0_Pos)                          /*!< LCD PAL204: R04_0 Mask              */
#define LCD_PAL204_G04_0_Pos                                  5                                                         /*!< LCD PAL204: G04_0 Position          */
#define LCD_PAL204_G04_0_Msk                                  (0x1fUL << LCD_PAL204_G04_0_Pos)                          /*!< LCD PAL204: G04_0 Mask              */
#define LCD_PAL204_B04_0_Pos                                  10                                                        /*!< LCD PAL204: B04_0 Position          */
#define LCD_PAL204_B04_0_Msk                                  (0x1fUL << LCD_PAL204_B04_0_Pos)                          /*!< LCD PAL204: B04_0 Mask              */
#define LCD_PAL204_I0_Pos                                     15                                                        /*!< LCD PAL204: I0 Position             */
#define LCD_PAL204_I0_Msk                                     (0x01UL << LCD_PAL204_I0_Pos)                             /*!< LCD PAL204: I0 Mask                 */
#define LCD_PAL204_R14_0_Pos                                  16                                                        /*!< LCD PAL204: R14_0 Position          */
#define LCD_PAL204_R14_0_Msk                                  (0x1fUL << LCD_PAL204_R14_0_Pos)                          /*!< LCD PAL204: R14_0 Mask              */
#define LCD_PAL204_G14_0_Pos                                  21                                                        /*!< LCD PAL204: G14_0 Position          */
#define LCD_PAL204_G14_0_Msk                                  (0x1fUL << LCD_PAL204_G14_0_Pos)                          /*!< LCD PAL204: G14_0 Mask              */
#define LCD_PAL204_B14_0_Pos                                  26                                                        /*!< LCD PAL204: B14_0 Position          */
#define LCD_PAL204_B14_0_Msk                                  (0x1fUL << LCD_PAL204_B14_0_Pos)                          /*!< LCD PAL204: B14_0 Mask              */
#define LCD_PAL204_I1_Pos                                     31                                                        /*!< LCD PAL204: I1 Position             */
#define LCD_PAL204_I1_Msk                                     (0x01UL << LCD_PAL204_I1_Pos)                             /*!< LCD PAL204: I1 Mask                 */

// ---------------------------------------  LCD_PAL205  -------------------------------------------
#define LCD_PAL205_R04_0_Pos                                  0                                                         /*!< LCD PAL205: R04_0 Position          */
#define LCD_PAL205_R04_0_Msk                                  (0x1fUL << LCD_PAL205_R04_0_Pos)                          /*!< LCD PAL205: R04_0 Mask              */
#define LCD_PAL205_G04_0_Pos                                  5                                                         /*!< LCD PAL205: G04_0 Position          */
#define LCD_PAL205_G04_0_Msk                                  (0x1fUL << LCD_PAL205_G04_0_Pos)                          /*!< LCD PAL205: G04_0 Mask              */
#define LCD_PAL205_B04_0_Pos                                  10                                                        /*!< LCD PAL205: B04_0 Position          */
#define LCD_PAL205_B04_0_Msk                                  (0x1fUL << LCD_PAL205_B04_0_Pos)                          /*!< LCD PAL205: B04_0 Mask              */
#define LCD_PAL205_I0_Pos                                     15                                                        /*!< LCD PAL205: I0 Position             */
#define LCD_PAL205_I0_Msk                                     (0x01UL << LCD_PAL205_I0_Pos)                             /*!< LCD PAL205: I0 Mask                 */
#define LCD_PAL205_R14_0_Pos                                  16                                                        /*!< LCD PAL205: R14_0 Position          */
#define LCD_PAL205_R14_0_Msk                                  (0x1fUL << LCD_PAL205_R14_0_Pos)                          /*!< LCD PAL205: R14_0 Mask              */
#define LCD_PAL205_G14_0_Pos                                  21                                                        /*!< LCD PAL205: G14_0 Position          */
#define LCD_PAL205_G14_0_Msk                                  (0x1fUL << LCD_PAL205_G14_0_Pos)                          /*!< LCD PAL205: G14_0 Mask              */
#define LCD_PAL205_B14_0_Pos                                  26                                                        /*!< LCD PAL205: B14_0 Position          */
#define LCD_PAL205_B14_0_Msk                                  (0x1fUL << LCD_PAL205_B14_0_Pos)                          /*!< LCD PAL205: B14_0 Mask              */
#define LCD_PAL205_I1_Pos                                     31                                                        /*!< LCD PAL205: I1 Position             */
#define LCD_PAL205_I1_Msk                                     (0x01UL << LCD_PAL205_I1_Pos)                             /*!< LCD PAL205: I1 Mask                 */

// ---------------------------------------  LCD_PAL206  -------------------------------------------
#define LCD_PAL206_R04_0_Pos                                  0                                                         /*!< LCD PAL206: R04_0 Position          */
#define LCD_PAL206_R04_0_Msk                                  (0x1fUL << LCD_PAL206_R04_0_Pos)                          /*!< LCD PAL206: R04_0 Mask              */
#define LCD_PAL206_G04_0_Pos                                  5                                                         /*!< LCD PAL206: G04_0 Position          */
#define LCD_PAL206_G04_0_Msk                                  (0x1fUL << LCD_PAL206_G04_0_Pos)                          /*!< LCD PAL206: G04_0 Mask              */
#define LCD_PAL206_B04_0_Pos                                  10                                                        /*!< LCD PAL206: B04_0 Position          */
#define LCD_PAL206_B04_0_Msk                                  (0x1fUL << LCD_PAL206_B04_0_Pos)                          /*!< LCD PAL206: B04_0 Mask              */
#define LCD_PAL206_I0_Pos                                     15                                                        /*!< LCD PAL206: I0 Position             */
#define LCD_PAL206_I0_Msk                                     (0x01UL << LCD_PAL206_I0_Pos)                             /*!< LCD PAL206: I0 Mask                 */
#define LCD_PAL206_R14_0_Pos                                  16                                                        /*!< LCD PAL206: R14_0 Position          */
#define LCD_PAL206_R14_0_Msk                                  (0x1fUL << LCD_PAL206_R14_0_Pos)                          /*!< LCD PAL206: R14_0 Mask              */
#define LCD_PAL206_G14_0_Pos                                  21                                                        /*!< LCD PAL206: G14_0 Position          */
#define LCD_PAL206_G14_0_Msk                                  (0x1fUL << LCD_PAL206_G14_0_Pos)                          /*!< LCD PAL206: G14_0 Mask              */
#define LCD_PAL206_B14_0_Pos                                  26                                                        /*!< LCD PAL206: B14_0 Position          */
#define LCD_PAL206_B14_0_Msk                                  (0x1fUL << LCD_PAL206_B14_0_Pos)                          /*!< LCD PAL206: B14_0 Mask              */
#define LCD_PAL206_I1_Pos                                     31                                                        /*!< LCD PAL206: I1 Position             */
#define LCD_PAL206_I1_Msk                                     (0x01UL << LCD_PAL206_I1_Pos)                             /*!< LCD PAL206: I1 Mask                 */

// ---------------------------------------  LCD_PAL207  -------------------------------------------
#define LCD_PAL207_R04_0_Pos                                  0                                                         /*!< LCD PAL207: R04_0 Position          */
#define LCD_PAL207_R04_0_Msk                                  (0x1fUL << LCD_PAL207_R04_0_Pos)                          /*!< LCD PAL207: R04_0 Mask              */
#define LCD_PAL207_G04_0_Pos                                  5                                                         /*!< LCD PAL207: G04_0 Position          */
#define LCD_PAL207_G04_0_Msk                                  (0x1fUL << LCD_PAL207_G04_0_Pos)                          /*!< LCD PAL207: G04_0 Mask              */
#define LCD_PAL207_B04_0_Pos                                  10                                                        /*!< LCD PAL207: B04_0 Position          */
#define LCD_PAL207_B04_0_Msk                                  (0x1fUL << LCD_PAL207_B04_0_Pos)                          /*!< LCD PAL207: B04_0 Mask              */
#define LCD_PAL207_I0_Pos                                     15                                                        /*!< LCD PAL207: I0 Position             */
#define LCD_PAL207_I0_Msk                                     (0x01UL << LCD_PAL207_I0_Pos)                             /*!< LCD PAL207: I0 Mask                 */
#define LCD_PAL207_R14_0_Pos                                  16                                                        /*!< LCD PAL207: R14_0 Position          */
#define LCD_PAL207_R14_0_Msk                                  (0x1fUL << LCD_PAL207_R14_0_Pos)                          /*!< LCD PAL207: R14_0 Mask              */
#define LCD_PAL207_G14_0_Pos                                  21                                                        /*!< LCD PAL207: G14_0 Position          */
#define LCD_PAL207_G14_0_Msk                                  (0x1fUL << LCD_PAL207_G14_0_Pos)                          /*!< LCD PAL207: G14_0 Mask              */
#define LCD_PAL207_B14_0_Pos                                  26                                                        /*!< LCD PAL207: B14_0 Position          */
#define LCD_PAL207_B14_0_Msk                                  (0x1fUL << LCD_PAL207_B14_0_Pos)                          /*!< LCD PAL207: B14_0 Mask              */
#define LCD_PAL207_I1_Pos                                     31                                                        /*!< LCD PAL207: I1 Position             */
#define LCD_PAL207_I1_Msk                                     (0x01UL << LCD_PAL207_I1_Pos)                             /*!< LCD PAL207: I1 Mask                 */

// ---------------------------------------  LCD_PAL208  -------------------------------------------
#define LCD_PAL208_R04_0_Pos                                  0                                                         /*!< LCD PAL208: R04_0 Position          */
#define LCD_PAL208_R04_0_Msk                                  (0x1fUL << LCD_PAL208_R04_0_Pos)                          /*!< LCD PAL208: R04_0 Mask              */
#define LCD_PAL208_G04_0_Pos                                  5                                                         /*!< LCD PAL208: G04_0 Position          */
#define LCD_PAL208_G04_0_Msk                                  (0x1fUL << LCD_PAL208_G04_0_Pos)                          /*!< LCD PAL208: G04_0 Mask              */
#define LCD_PAL208_B04_0_Pos                                  10                                                        /*!< LCD PAL208: B04_0 Position          */
#define LCD_PAL208_B04_0_Msk                                  (0x1fUL << LCD_PAL208_B04_0_Pos)                          /*!< LCD PAL208: B04_0 Mask              */
#define LCD_PAL208_I0_Pos                                     15                                                        /*!< LCD PAL208: I0 Position             */
#define LCD_PAL208_I0_Msk                                     (0x01UL << LCD_PAL208_I0_Pos)                             /*!< LCD PAL208: I0 Mask                 */
#define LCD_PAL208_R14_0_Pos                                  16                                                        /*!< LCD PAL208: R14_0 Position          */
#define LCD_PAL208_R14_0_Msk                                  (0x1fUL << LCD_PAL208_R14_0_Pos)                          /*!< LCD PAL208: R14_0 Mask              */
#define LCD_PAL208_G14_0_Pos                                  21                                                        /*!< LCD PAL208: G14_0 Position          */
#define LCD_PAL208_G14_0_Msk                                  (0x1fUL << LCD_PAL208_G14_0_Pos)                          /*!< LCD PAL208: G14_0 Mask              */
#define LCD_PAL208_B14_0_Pos                                  26                                                        /*!< LCD PAL208: B14_0 Position          */
#define LCD_PAL208_B14_0_Msk                                  (0x1fUL << LCD_PAL208_B14_0_Pos)                          /*!< LCD PAL208: B14_0 Mask              */
#define LCD_PAL208_I1_Pos                                     31                                                        /*!< LCD PAL208: I1 Position             */
#define LCD_PAL208_I1_Msk                                     (0x01UL << LCD_PAL208_I1_Pos)                             /*!< LCD PAL208: I1 Mask                 */

// ---------------------------------------  LCD_PAL209  -------------------------------------------
#define LCD_PAL209_R04_0_Pos                                  0                                                         /*!< LCD PAL209: R04_0 Position          */
#define LCD_PAL209_R04_0_Msk                                  (0x1fUL << LCD_PAL209_R04_0_Pos)                          /*!< LCD PAL209: R04_0 Mask              */
#define LCD_PAL209_G04_0_Pos                                  5                                                         /*!< LCD PAL209: G04_0 Position          */
#define LCD_PAL209_G04_0_Msk                                  (0x1fUL << LCD_PAL209_G04_0_Pos)                          /*!< LCD PAL209: G04_0 Mask              */
#define LCD_PAL209_B04_0_Pos                                  10                                                        /*!< LCD PAL209: B04_0 Position          */
#define LCD_PAL209_B04_0_Msk                                  (0x1fUL << LCD_PAL209_B04_0_Pos)                          /*!< LCD PAL209: B04_0 Mask              */
#define LCD_PAL209_I0_Pos                                     15                                                        /*!< LCD PAL209: I0 Position             */
#define LCD_PAL209_I0_Msk                                     (0x01UL << LCD_PAL209_I0_Pos)                             /*!< LCD PAL209: I0 Mask                 */
#define LCD_PAL209_R14_0_Pos                                  16                                                        /*!< LCD PAL209: R14_0 Position          */
#define LCD_PAL209_R14_0_Msk                                  (0x1fUL << LCD_PAL209_R14_0_Pos)                          /*!< LCD PAL209: R14_0 Mask              */
#define LCD_PAL209_G14_0_Pos                                  21                                                        /*!< LCD PAL209: G14_0 Position          */
#define LCD_PAL209_G14_0_Msk                                  (0x1fUL << LCD_PAL209_G14_0_Pos)                          /*!< LCD PAL209: G14_0 Mask              */
#define LCD_PAL209_B14_0_Pos                                  26                                                        /*!< LCD PAL209: B14_0 Position          */
#define LCD_PAL209_B14_0_Msk                                  (0x1fUL << LCD_PAL209_B14_0_Pos)                          /*!< LCD PAL209: B14_0 Mask              */
#define LCD_PAL209_I1_Pos                                     31                                                        /*!< LCD PAL209: I1 Position             */
#define LCD_PAL209_I1_Msk                                     (0x01UL << LCD_PAL209_I1_Pos)                             /*!< LCD PAL209: I1 Mask                 */

// ---------------------------------------  LCD_PAL210  -------------------------------------------
#define LCD_PAL210_R04_0_Pos                                  0                                                         /*!< LCD PAL210: R04_0 Position          */
#define LCD_PAL210_R04_0_Msk                                  (0x1fUL << LCD_PAL210_R04_0_Pos)                          /*!< LCD PAL210: R04_0 Mask              */
#define LCD_PAL210_G04_0_Pos                                  5                                                         /*!< LCD PAL210: G04_0 Position          */
#define LCD_PAL210_G04_0_Msk                                  (0x1fUL << LCD_PAL210_G04_0_Pos)                          /*!< LCD PAL210: G04_0 Mask              */
#define LCD_PAL210_B04_0_Pos                                  10                                                        /*!< LCD PAL210: B04_0 Position          */
#define LCD_PAL210_B04_0_Msk                                  (0x1fUL << LCD_PAL210_B04_0_Pos)                          /*!< LCD PAL210: B04_0 Mask              */
#define LCD_PAL210_I0_Pos                                     15                                                        /*!< LCD PAL210: I0 Position             */
#define LCD_PAL210_I0_Msk                                     (0x01UL << LCD_PAL210_I0_Pos)                             /*!< LCD PAL210: I0 Mask                 */
#define LCD_PAL210_R14_0_Pos                                  16                                                        /*!< LCD PAL210: R14_0 Position          */
#define LCD_PAL210_R14_0_Msk                                  (0x1fUL << LCD_PAL210_R14_0_Pos)                          /*!< LCD PAL210: R14_0 Mask              */
#define LCD_PAL210_G14_0_Pos                                  21                                                        /*!< LCD PAL210: G14_0 Position          */
#define LCD_PAL210_G14_0_Msk                                  (0x1fUL << LCD_PAL210_G14_0_Pos)                          /*!< LCD PAL210: G14_0 Mask              */
#define LCD_PAL210_B14_0_Pos                                  26                                                        /*!< LCD PAL210: B14_0 Position          */
#define LCD_PAL210_B14_0_Msk                                  (0x1fUL << LCD_PAL210_B14_0_Pos)                          /*!< LCD PAL210: B14_0 Mask              */
#define LCD_PAL210_I1_Pos                                     31                                                        /*!< LCD PAL210: I1 Position             */
#define LCD_PAL210_I1_Msk                                     (0x01UL << LCD_PAL210_I1_Pos)                             /*!< LCD PAL210: I1 Mask                 */

// ---------------------------------------  LCD_PAL211  -------------------------------------------
#define LCD_PAL211_R04_0_Pos                                  0                                                         /*!< LCD PAL211: R04_0 Position          */
#define LCD_PAL211_R04_0_Msk                                  (0x1fUL << LCD_PAL211_R04_0_Pos)                          /*!< LCD PAL211: R04_0 Mask              */
#define LCD_PAL211_G04_0_Pos                                  5                                                         /*!< LCD PAL211: G04_0 Position          */
#define LCD_PAL211_G04_0_Msk                                  (0x1fUL << LCD_PAL211_G04_0_Pos)                          /*!< LCD PAL211: G04_0 Mask              */
#define LCD_PAL211_B04_0_Pos                                  10                                                        /*!< LCD PAL211: B04_0 Position          */
#define LCD_PAL211_B04_0_Msk                                  (0x1fUL << LCD_PAL211_B04_0_Pos)                          /*!< LCD PAL211: B04_0 Mask              */
#define LCD_PAL211_I0_Pos                                     15                                                        /*!< LCD PAL211: I0 Position             */
#define LCD_PAL211_I0_Msk                                     (0x01UL << LCD_PAL211_I0_Pos)                             /*!< LCD PAL211: I0 Mask                 */
#define LCD_PAL211_R14_0_Pos                                  16                                                        /*!< LCD PAL211: R14_0 Position          */
#define LCD_PAL211_R14_0_Msk                                  (0x1fUL << LCD_PAL211_R14_0_Pos)                          /*!< LCD PAL211: R14_0 Mask              */
#define LCD_PAL211_G14_0_Pos                                  21                                                        /*!< LCD PAL211: G14_0 Position          */
#define LCD_PAL211_G14_0_Msk                                  (0x1fUL << LCD_PAL211_G14_0_Pos)                          /*!< LCD PAL211: G14_0 Mask              */
#define LCD_PAL211_B14_0_Pos                                  26                                                        /*!< LCD PAL211: B14_0 Position          */
#define LCD_PAL211_B14_0_Msk                                  (0x1fUL << LCD_PAL211_B14_0_Pos)                          /*!< LCD PAL211: B14_0 Mask              */
#define LCD_PAL211_I1_Pos                                     31                                                        /*!< LCD PAL211: I1 Position             */
#define LCD_PAL211_I1_Msk                                     (0x01UL << LCD_PAL211_I1_Pos)                             /*!< LCD PAL211: I1 Mask                 */

// ---------------------------------------  LCD_PAL212  -------------------------------------------
#define LCD_PAL212_R04_0_Pos                                  0                                                         /*!< LCD PAL212: R04_0 Position          */
#define LCD_PAL212_R04_0_Msk                                  (0x1fUL << LCD_PAL212_R04_0_Pos)                          /*!< LCD PAL212: R04_0 Mask              */
#define LCD_PAL212_G04_0_Pos                                  5                                                         /*!< LCD PAL212: G04_0 Position          */
#define LCD_PAL212_G04_0_Msk                                  (0x1fUL << LCD_PAL212_G04_0_Pos)                          /*!< LCD PAL212: G04_0 Mask              */
#define LCD_PAL212_B04_0_Pos                                  10                                                        /*!< LCD PAL212: B04_0 Position          */
#define LCD_PAL212_B04_0_Msk                                  (0x1fUL << LCD_PAL212_B04_0_Pos)                          /*!< LCD PAL212: B04_0 Mask              */
#define LCD_PAL212_I0_Pos                                     15                                                        /*!< LCD PAL212: I0 Position             */
#define LCD_PAL212_I0_Msk                                     (0x01UL << LCD_PAL212_I0_Pos)                             /*!< LCD PAL212: I0 Mask                 */
#define LCD_PAL212_R14_0_Pos                                  16                                                        /*!< LCD PAL212: R14_0 Position          */
#define LCD_PAL212_R14_0_Msk                                  (0x1fUL << LCD_PAL212_R14_0_Pos)                          /*!< LCD PAL212: R14_0 Mask              */
#define LCD_PAL212_G14_0_Pos                                  21                                                        /*!< LCD PAL212: G14_0 Position          */
#define LCD_PAL212_G14_0_Msk                                  (0x1fUL << LCD_PAL212_G14_0_Pos)                          /*!< LCD PAL212: G14_0 Mask              */
#define LCD_PAL212_B14_0_Pos                                  26                                                        /*!< LCD PAL212: B14_0 Position          */
#define LCD_PAL212_B14_0_Msk                                  (0x1fUL << LCD_PAL212_B14_0_Pos)                          /*!< LCD PAL212: B14_0 Mask              */
#define LCD_PAL212_I1_Pos                                     31                                                        /*!< LCD PAL212: I1 Position             */
#define LCD_PAL212_I1_Msk                                     (0x01UL << LCD_PAL212_I1_Pos)                             /*!< LCD PAL212: I1 Mask                 */

// ---------------------------------------  LCD_PAL213  -------------------------------------------
#define LCD_PAL213_R04_0_Pos                                  0                                                         /*!< LCD PAL213: R04_0 Position          */
#define LCD_PAL213_R04_0_Msk                                  (0x1fUL << LCD_PAL213_R04_0_Pos)                          /*!< LCD PAL213: R04_0 Mask              */
#define LCD_PAL213_G04_0_Pos                                  5                                                         /*!< LCD PAL213: G04_0 Position          */
#define LCD_PAL213_G04_0_Msk                                  (0x1fUL << LCD_PAL213_G04_0_Pos)                          /*!< LCD PAL213: G04_0 Mask              */
#define LCD_PAL213_B04_0_Pos                                  10                                                        /*!< LCD PAL213: B04_0 Position          */
#define LCD_PAL213_B04_0_Msk                                  (0x1fUL << LCD_PAL213_B04_0_Pos)                          /*!< LCD PAL213: B04_0 Mask              */
#define LCD_PAL213_I0_Pos                                     15                                                        /*!< LCD PAL213: I0 Position             */
#define LCD_PAL213_I0_Msk                                     (0x01UL << LCD_PAL213_I0_Pos)                             /*!< LCD PAL213: I0 Mask                 */
#define LCD_PAL213_R14_0_Pos                                  16                                                        /*!< LCD PAL213: R14_0 Position          */
#define LCD_PAL213_R14_0_Msk                                  (0x1fUL << LCD_PAL213_R14_0_Pos)                          /*!< LCD PAL213: R14_0 Mask              */
#define LCD_PAL213_G14_0_Pos                                  21                                                        /*!< LCD PAL213: G14_0 Position          */
#define LCD_PAL213_G14_0_Msk                                  (0x1fUL << LCD_PAL213_G14_0_Pos)                          /*!< LCD PAL213: G14_0 Mask              */
#define LCD_PAL213_B14_0_Pos                                  26                                                        /*!< LCD PAL213: B14_0 Position          */
#define LCD_PAL213_B14_0_Msk                                  (0x1fUL << LCD_PAL213_B14_0_Pos)                          /*!< LCD PAL213: B14_0 Mask              */
#define LCD_PAL213_I1_Pos                                     31                                                        /*!< LCD PAL213: I1 Position             */
#define LCD_PAL213_I1_Msk                                     (0x01UL << LCD_PAL213_I1_Pos)                             /*!< LCD PAL213: I1 Mask                 */

// ---------------------------------------  LCD_PAL214  -------------------------------------------
#define LCD_PAL214_R04_0_Pos                                  0                                                         /*!< LCD PAL214: R04_0 Position          */
#define LCD_PAL214_R04_0_Msk                                  (0x1fUL << LCD_PAL214_R04_0_Pos)                          /*!< LCD PAL214: R04_0 Mask              */
#define LCD_PAL214_G04_0_Pos                                  5                                                         /*!< LCD PAL214: G04_0 Position          */
#define LCD_PAL214_G04_0_Msk                                  (0x1fUL << LCD_PAL214_G04_0_Pos)                          /*!< LCD PAL214: G04_0 Mask              */
#define LCD_PAL214_B04_0_Pos                                  10                                                        /*!< LCD PAL214: B04_0 Position          */
#define LCD_PAL214_B04_0_Msk                                  (0x1fUL << LCD_PAL214_B04_0_Pos)                          /*!< LCD PAL214: B04_0 Mask              */
#define LCD_PAL214_I0_Pos                                     15                                                        /*!< LCD PAL214: I0 Position             */
#define LCD_PAL214_I0_Msk                                     (0x01UL << LCD_PAL214_I0_Pos)                             /*!< LCD PAL214: I0 Mask                 */
#define LCD_PAL214_R14_0_Pos                                  16                                                        /*!< LCD PAL214: R14_0 Position          */
#define LCD_PAL214_R14_0_Msk                                  (0x1fUL << LCD_PAL214_R14_0_Pos)                          /*!< LCD PAL214: R14_0 Mask              */
#define LCD_PAL214_G14_0_Pos                                  21                                                        /*!< LCD PAL214: G14_0 Position          */
#define LCD_PAL214_G14_0_Msk                                  (0x1fUL << LCD_PAL214_G14_0_Pos)                          /*!< LCD PAL214: G14_0 Mask              */
#define LCD_PAL214_B14_0_Pos                                  26                                                        /*!< LCD PAL214: B14_0 Position          */
#define LCD_PAL214_B14_0_Msk                                  (0x1fUL << LCD_PAL214_B14_0_Pos)                          /*!< LCD PAL214: B14_0 Mask              */
#define LCD_PAL214_I1_Pos                                     31                                                        /*!< LCD PAL214: I1 Position             */
#define LCD_PAL214_I1_Msk                                     (0x01UL << LCD_PAL214_I1_Pos)                             /*!< LCD PAL214: I1 Mask                 */

// ---------------------------------------  LCD_PAL215  -------------------------------------------
#define LCD_PAL215_R04_0_Pos                                  0                                                         /*!< LCD PAL215: R04_0 Position          */
#define LCD_PAL215_R04_0_Msk                                  (0x1fUL << LCD_PAL215_R04_0_Pos)                          /*!< LCD PAL215: R04_0 Mask              */
#define LCD_PAL215_G04_0_Pos                                  5                                                         /*!< LCD PAL215: G04_0 Position          */
#define LCD_PAL215_G04_0_Msk                                  (0x1fUL << LCD_PAL215_G04_0_Pos)                          /*!< LCD PAL215: G04_0 Mask              */
#define LCD_PAL215_B04_0_Pos                                  10                                                        /*!< LCD PAL215: B04_0 Position          */
#define LCD_PAL215_B04_0_Msk                                  (0x1fUL << LCD_PAL215_B04_0_Pos)                          /*!< LCD PAL215: B04_0 Mask              */
#define LCD_PAL215_I0_Pos                                     15                                                        /*!< LCD PAL215: I0 Position             */
#define LCD_PAL215_I0_Msk                                     (0x01UL << LCD_PAL215_I0_Pos)                             /*!< LCD PAL215: I0 Mask                 */
#define LCD_PAL215_R14_0_Pos                                  16                                                        /*!< LCD PAL215: R14_0 Position          */
#define LCD_PAL215_R14_0_Msk                                  (0x1fUL << LCD_PAL215_R14_0_Pos)                          /*!< LCD PAL215: R14_0 Mask              */
#define LCD_PAL215_G14_0_Pos                                  21                                                        /*!< LCD PAL215: G14_0 Position          */
#define LCD_PAL215_G14_0_Msk                                  (0x1fUL << LCD_PAL215_G14_0_Pos)                          /*!< LCD PAL215: G14_0 Mask              */
#define LCD_PAL215_B14_0_Pos                                  26                                                        /*!< LCD PAL215: B14_0 Position          */
#define LCD_PAL215_B14_0_Msk                                  (0x1fUL << LCD_PAL215_B14_0_Pos)                          /*!< LCD PAL215: B14_0 Mask              */
#define LCD_PAL215_I1_Pos                                     31                                                        /*!< LCD PAL215: I1 Position             */
#define LCD_PAL215_I1_Msk                                     (0x01UL << LCD_PAL215_I1_Pos)                             /*!< LCD PAL215: I1 Mask                 */

// ---------------------------------------  LCD_PAL216  -------------------------------------------
#define LCD_PAL216_R04_0_Pos                                  0                                                         /*!< LCD PAL216: R04_0 Position          */
#define LCD_PAL216_R04_0_Msk                                  (0x1fUL << LCD_PAL216_R04_0_Pos)                          /*!< LCD PAL216: R04_0 Mask              */
#define LCD_PAL216_G04_0_Pos                                  5                                                         /*!< LCD PAL216: G04_0 Position          */
#define LCD_PAL216_G04_0_Msk                                  (0x1fUL << LCD_PAL216_G04_0_Pos)                          /*!< LCD PAL216: G04_0 Mask              */
#define LCD_PAL216_B04_0_Pos                                  10                                                        /*!< LCD PAL216: B04_0 Position          */
#define LCD_PAL216_B04_0_Msk                                  (0x1fUL << LCD_PAL216_B04_0_Pos)                          /*!< LCD PAL216: B04_0 Mask              */
#define LCD_PAL216_I0_Pos                                     15                                                        /*!< LCD PAL216: I0 Position             */
#define LCD_PAL216_I0_Msk                                     (0x01UL << LCD_PAL216_I0_Pos)                             /*!< LCD PAL216: I0 Mask                 */
#define LCD_PAL216_R14_0_Pos                                  16                                                        /*!< LCD PAL216: R14_0 Position          */
#define LCD_PAL216_R14_0_Msk                                  (0x1fUL << LCD_PAL216_R14_0_Pos)                          /*!< LCD PAL216: R14_0 Mask              */
#define LCD_PAL216_G14_0_Pos                                  21                                                        /*!< LCD PAL216: G14_0 Position          */
#define LCD_PAL216_G14_0_Msk                                  (0x1fUL << LCD_PAL216_G14_0_Pos)                          /*!< LCD PAL216: G14_0 Mask              */
#define LCD_PAL216_B14_0_Pos                                  26                                                        /*!< LCD PAL216: B14_0 Position          */
#define LCD_PAL216_B14_0_Msk                                  (0x1fUL << LCD_PAL216_B14_0_Pos)                          /*!< LCD PAL216: B14_0 Mask              */
#define LCD_PAL216_I1_Pos                                     31                                                        /*!< LCD PAL216: I1 Position             */
#define LCD_PAL216_I1_Msk                                     (0x01UL << LCD_PAL216_I1_Pos)                             /*!< LCD PAL216: I1 Mask                 */

// ---------------------------------------  LCD_PAL217  -------------------------------------------
#define LCD_PAL217_R04_0_Pos                                  0                                                         /*!< LCD PAL217: R04_0 Position          */
#define LCD_PAL217_R04_0_Msk                                  (0x1fUL << LCD_PAL217_R04_0_Pos)                          /*!< LCD PAL217: R04_0 Mask              */
#define LCD_PAL217_G04_0_Pos                                  5                                                         /*!< LCD PAL217: G04_0 Position          */
#define LCD_PAL217_G04_0_Msk                                  (0x1fUL << LCD_PAL217_G04_0_Pos)                          /*!< LCD PAL217: G04_0 Mask              */
#define LCD_PAL217_B04_0_Pos                                  10                                                        /*!< LCD PAL217: B04_0 Position          */
#define LCD_PAL217_B04_0_Msk                                  (0x1fUL << LCD_PAL217_B04_0_Pos)                          /*!< LCD PAL217: B04_0 Mask              */
#define LCD_PAL217_I0_Pos                                     15                                                        /*!< LCD PAL217: I0 Position             */
#define LCD_PAL217_I0_Msk                                     (0x01UL << LCD_PAL217_I0_Pos)                             /*!< LCD PAL217: I0 Mask                 */
#define LCD_PAL217_R14_0_Pos                                  16                                                        /*!< LCD PAL217: R14_0 Position          */
#define LCD_PAL217_R14_0_Msk                                  (0x1fUL << LCD_PAL217_R14_0_Pos)                          /*!< LCD PAL217: R14_0 Mask              */
#define LCD_PAL217_G14_0_Pos                                  21                                                        /*!< LCD PAL217: G14_0 Position          */
#define LCD_PAL217_G14_0_Msk                                  (0x1fUL << LCD_PAL217_G14_0_Pos)                          /*!< LCD PAL217: G14_0 Mask              */
#define LCD_PAL217_B14_0_Pos                                  26                                                        /*!< LCD PAL217: B14_0 Position          */
#define LCD_PAL217_B14_0_Msk                                  (0x1fUL << LCD_PAL217_B14_0_Pos)                          /*!< LCD PAL217: B14_0 Mask              */
#define LCD_PAL217_I1_Pos                                     31                                                        /*!< LCD PAL217: I1 Position             */
#define LCD_PAL217_I1_Msk                                     (0x01UL << LCD_PAL217_I1_Pos)                             /*!< LCD PAL217: I1 Mask                 */

// ---------------------------------------  LCD_PAL218  -------------------------------------------
#define LCD_PAL218_R04_0_Pos                                  0                                                         /*!< LCD PAL218: R04_0 Position          */
#define LCD_PAL218_R04_0_Msk                                  (0x1fUL << LCD_PAL218_R04_0_Pos)                          /*!< LCD PAL218: R04_0 Mask              */
#define LCD_PAL218_G04_0_Pos                                  5                                                         /*!< LCD PAL218: G04_0 Position          */
#define LCD_PAL218_G04_0_Msk                                  (0x1fUL << LCD_PAL218_G04_0_Pos)                          /*!< LCD PAL218: G04_0 Mask              */
#define LCD_PAL218_B04_0_Pos                                  10                                                        /*!< LCD PAL218: B04_0 Position          */
#define LCD_PAL218_B04_0_Msk                                  (0x1fUL << LCD_PAL218_B04_0_Pos)                          /*!< LCD PAL218: B04_0 Mask              */
#define LCD_PAL218_I0_Pos                                     15                                                        /*!< LCD PAL218: I0 Position             */
#define LCD_PAL218_I0_Msk                                     (0x01UL << LCD_PAL218_I0_Pos)                             /*!< LCD PAL218: I0 Mask                 */
#define LCD_PAL218_R14_0_Pos                                  16                                                        /*!< LCD PAL218: R14_0 Position          */
#define LCD_PAL218_R14_0_Msk                                  (0x1fUL << LCD_PAL218_R14_0_Pos)                          /*!< LCD PAL218: R14_0 Mask              */
#define LCD_PAL218_G14_0_Pos                                  21                                                        /*!< LCD PAL218: G14_0 Position          */
#define LCD_PAL218_G14_0_Msk                                  (0x1fUL << LCD_PAL218_G14_0_Pos)                          /*!< LCD PAL218: G14_0 Mask              */
#define LCD_PAL218_B14_0_Pos                                  26                                                        /*!< LCD PAL218: B14_0 Position          */
#define LCD_PAL218_B14_0_Msk                                  (0x1fUL << LCD_PAL218_B14_0_Pos)                          /*!< LCD PAL218: B14_0 Mask              */
#define LCD_PAL218_I1_Pos                                     31                                                        /*!< LCD PAL218: I1 Position             */
#define LCD_PAL218_I1_Msk                                     (0x01UL << LCD_PAL218_I1_Pos)                             /*!< LCD PAL218: I1 Mask                 */

// ---------------------------------------  LCD_PAL219  -------------------------------------------
#define LCD_PAL219_R04_0_Pos                                  0                                                         /*!< LCD PAL219: R04_0 Position          */
#define LCD_PAL219_R04_0_Msk                                  (0x1fUL << LCD_PAL219_R04_0_Pos)                          /*!< LCD PAL219: R04_0 Mask              */
#define LCD_PAL219_G04_0_Pos                                  5                                                         /*!< LCD PAL219: G04_0 Position          */
#define LCD_PAL219_G04_0_Msk                                  (0x1fUL << LCD_PAL219_G04_0_Pos)                          /*!< LCD PAL219: G04_0 Mask              */
#define LCD_PAL219_B04_0_Pos                                  10                                                        /*!< LCD PAL219: B04_0 Position          */
#define LCD_PAL219_B04_0_Msk                                  (0x1fUL << LCD_PAL219_B04_0_Pos)                          /*!< LCD PAL219: B04_0 Mask              */
#define LCD_PAL219_I0_Pos                                     15                                                        /*!< LCD PAL219: I0 Position             */
#define LCD_PAL219_I0_Msk                                     (0x01UL << LCD_PAL219_I0_Pos)                             /*!< LCD PAL219: I0 Mask                 */
#define LCD_PAL219_R14_0_Pos                                  16                                                        /*!< LCD PAL219: R14_0 Position          */
#define LCD_PAL219_R14_0_Msk                                  (0x1fUL << LCD_PAL219_R14_0_Pos)                          /*!< LCD PAL219: R14_0 Mask              */
#define LCD_PAL219_G14_0_Pos                                  21                                                        /*!< LCD PAL219: G14_0 Position          */
#define LCD_PAL219_G14_0_Msk                                  (0x1fUL << LCD_PAL219_G14_0_Pos)                          /*!< LCD PAL219: G14_0 Mask              */
#define LCD_PAL219_B14_0_Pos                                  26                                                        /*!< LCD PAL219: B14_0 Position          */
#define LCD_PAL219_B14_0_Msk                                  (0x1fUL << LCD_PAL219_B14_0_Pos)                          /*!< LCD PAL219: B14_0 Mask              */
#define LCD_PAL219_I1_Pos                                     31                                                        /*!< LCD PAL219: I1 Position             */
#define LCD_PAL219_I1_Msk                                     (0x01UL << LCD_PAL219_I1_Pos)                             /*!< LCD PAL219: I1 Mask                 */

// ---------------------------------------  LCD_PAL220  -------------------------------------------
#define LCD_PAL220_R04_0_Pos                                  0                                                         /*!< LCD PAL220: R04_0 Position          */
#define LCD_PAL220_R04_0_Msk                                  (0x1fUL << LCD_PAL220_R04_0_Pos)                          /*!< LCD PAL220: R04_0 Mask              */
#define LCD_PAL220_G04_0_Pos                                  5                                                         /*!< LCD PAL220: G04_0 Position          */
#define LCD_PAL220_G04_0_Msk                                  (0x1fUL << LCD_PAL220_G04_0_Pos)                          /*!< LCD PAL220: G04_0 Mask              */
#define LCD_PAL220_B04_0_Pos                                  10                                                        /*!< LCD PAL220: B04_0 Position          */
#define LCD_PAL220_B04_0_Msk                                  (0x1fUL << LCD_PAL220_B04_0_Pos)                          /*!< LCD PAL220: B04_0 Mask              */
#define LCD_PAL220_I0_Pos                                     15                                                        /*!< LCD PAL220: I0 Position             */
#define LCD_PAL220_I0_Msk                                     (0x01UL << LCD_PAL220_I0_Pos)                             /*!< LCD PAL220: I0 Mask                 */
#define LCD_PAL220_R14_0_Pos                                  16                                                        /*!< LCD PAL220: R14_0 Position          */
#define LCD_PAL220_R14_0_Msk                                  (0x1fUL << LCD_PAL220_R14_0_Pos)                          /*!< LCD PAL220: R14_0 Mask              */
#define LCD_PAL220_G14_0_Pos                                  21                                                        /*!< LCD PAL220: G14_0 Position          */
#define LCD_PAL220_G14_0_Msk                                  (0x1fUL << LCD_PAL220_G14_0_Pos)                          /*!< LCD PAL220: G14_0 Mask              */
#define LCD_PAL220_B14_0_Pos                                  26                                                        /*!< LCD PAL220: B14_0 Position          */
#define LCD_PAL220_B14_0_Msk                                  (0x1fUL << LCD_PAL220_B14_0_Pos)                          /*!< LCD PAL220: B14_0 Mask              */
#define LCD_PAL220_I1_Pos                                     31                                                        /*!< LCD PAL220: I1 Position             */
#define LCD_PAL220_I1_Msk                                     (0x01UL << LCD_PAL220_I1_Pos)                             /*!< LCD PAL220: I1 Mask                 */

// ---------------------------------------  LCD_PAL221  -------------------------------------------
#define LCD_PAL221_R04_0_Pos                                  0                                                         /*!< LCD PAL221: R04_0 Position          */
#define LCD_PAL221_R04_0_Msk                                  (0x1fUL << LCD_PAL221_R04_0_Pos)                          /*!< LCD PAL221: R04_0 Mask              */
#define LCD_PAL221_G04_0_Pos                                  5                                                         /*!< LCD PAL221: G04_0 Position          */
#define LCD_PAL221_G04_0_Msk                                  (0x1fUL << LCD_PAL221_G04_0_Pos)                          /*!< LCD PAL221: G04_0 Mask              */
#define LCD_PAL221_B04_0_Pos                                  10                                                        /*!< LCD PAL221: B04_0 Position          */
#define LCD_PAL221_B04_0_Msk                                  (0x1fUL << LCD_PAL221_B04_0_Pos)                          /*!< LCD PAL221: B04_0 Mask              */
#define LCD_PAL221_I0_Pos                                     15                                                        /*!< LCD PAL221: I0 Position             */
#define LCD_PAL221_I0_Msk                                     (0x01UL << LCD_PAL221_I0_Pos)                             /*!< LCD PAL221: I0 Mask                 */
#define LCD_PAL221_R14_0_Pos                                  16                                                        /*!< LCD PAL221: R14_0 Position          */
#define LCD_PAL221_R14_0_Msk                                  (0x1fUL << LCD_PAL221_R14_0_Pos)                          /*!< LCD PAL221: R14_0 Mask              */
#define LCD_PAL221_G14_0_Pos                                  21                                                        /*!< LCD PAL221: G14_0 Position          */
#define LCD_PAL221_G14_0_Msk                                  (0x1fUL << LCD_PAL221_G14_0_Pos)                          /*!< LCD PAL221: G14_0 Mask              */
#define LCD_PAL221_B14_0_Pos                                  26                                                        /*!< LCD PAL221: B14_0 Position          */
#define LCD_PAL221_B14_0_Msk                                  (0x1fUL << LCD_PAL221_B14_0_Pos)                          /*!< LCD PAL221: B14_0 Mask              */
#define LCD_PAL221_I1_Pos                                     31                                                        /*!< LCD PAL221: I1 Position             */
#define LCD_PAL221_I1_Msk                                     (0x01UL << LCD_PAL221_I1_Pos)                             /*!< LCD PAL221: I1 Mask                 */

// ---------------------------------------  LCD_PAL222  -------------------------------------------
#define LCD_PAL222_R04_0_Pos                                  0                                                         /*!< LCD PAL222: R04_0 Position          */
#define LCD_PAL222_R04_0_Msk                                  (0x1fUL << LCD_PAL222_R04_0_Pos)                          /*!< LCD PAL222: R04_0 Mask              */
#define LCD_PAL222_G04_0_Pos                                  5                                                         /*!< LCD PAL222: G04_0 Position          */
#define LCD_PAL222_G04_0_Msk                                  (0x1fUL << LCD_PAL222_G04_0_Pos)                          /*!< LCD PAL222: G04_0 Mask              */
#define LCD_PAL222_B04_0_Pos                                  10                                                        /*!< LCD PAL222: B04_0 Position          */
#define LCD_PAL222_B04_0_Msk                                  (0x1fUL << LCD_PAL222_B04_0_Pos)                          /*!< LCD PAL222: B04_0 Mask              */
#define LCD_PAL222_I0_Pos                                     15                                                        /*!< LCD PAL222: I0 Position             */
#define LCD_PAL222_I0_Msk                                     (0x01UL << LCD_PAL222_I0_Pos)                             /*!< LCD PAL222: I0 Mask                 */
#define LCD_PAL222_R14_0_Pos                                  16                                                        /*!< LCD PAL222: R14_0 Position          */
#define LCD_PAL222_R14_0_Msk                                  (0x1fUL << LCD_PAL222_R14_0_Pos)                          /*!< LCD PAL222: R14_0 Mask              */
#define LCD_PAL222_G14_0_Pos                                  21                                                        /*!< LCD PAL222: G14_0 Position          */
#define LCD_PAL222_G14_0_Msk                                  (0x1fUL << LCD_PAL222_G14_0_Pos)                          /*!< LCD PAL222: G14_0 Mask              */
#define LCD_PAL222_B14_0_Pos                                  26                                                        /*!< LCD PAL222: B14_0 Position          */
#define LCD_PAL222_B14_0_Msk                                  (0x1fUL << LCD_PAL222_B14_0_Pos)                          /*!< LCD PAL222: B14_0 Mask              */
#define LCD_PAL222_I1_Pos                                     31                                                        /*!< LCD PAL222: I1 Position             */
#define LCD_PAL222_I1_Msk                                     (0x01UL << LCD_PAL222_I1_Pos)                             /*!< LCD PAL222: I1 Mask                 */

// ---------------------------------------  LCD_PAL223  -------------------------------------------
#define LCD_PAL223_R04_0_Pos                                  0                                                         /*!< LCD PAL223: R04_0 Position          */
#define LCD_PAL223_R04_0_Msk                                  (0x1fUL << LCD_PAL223_R04_0_Pos)                          /*!< LCD PAL223: R04_0 Mask              */
#define LCD_PAL223_G04_0_Pos                                  5                                                         /*!< LCD PAL223: G04_0 Position          */
#define LCD_PAL223_G04_0_Msk                                  (0x1fUL << LCD_PAL223_G04_0_Pos)                          /*!< LCD PAL223: G04_0 Mask              */
#define LCD_PAL223_B04_0_Pos                                  10                                                        /*!< LCD PAL223: B04_0 Position          */
#define LCD_PAL223_B04_0_Msk                                  (0x1fUL << LCD_PAL223_B04_0_Pos)                          /*!< LCD PAL223: B04_0 Mask              */
#define LCD_PAL223_I0_Pos                                     15                                                        /*!< LCD PAL223: I0 Position             */
#define LCD_PAL223_I0_Msk                                     (0x01UL << LCD_PAL223_I0_Pos)                             /*!< LCD PAL223: I0 Mask                 */
#define LCD_PAL223_R14_0_Pos                                  16                                                        /*!< LCD PAL223: R14_0 Position          */
#define LCD_PAL223_R14_0_Msk                                  (0x1fUL << LCD_PAL223_R14_0_Pos)                          /*!< LCD PAL223: R14_0 Mask              */
#define LCD_PAL223_G14_0_Pos                                  21                                                        /*!< LCD PAL223: G14_0 Position          */
#define LCD_PAL223_G14_0_Msk                                  (0x1fUL << LCD_PAL223_G14_0_Pos)                          /*!< LCD PAL223: G14_0 Mask              */
#define LCD_PAL223_B14_0_Pos                                  26                                                        /*!< LCD PAL223: B14_0 Position          */
#define LCD_PAL223_B14_0_Msk                                  (0x1fUL << LCD_PAL223_B14_0_Pos)                          /*!< LCD PAL223: B14_0 Mask              */
#define LCD_PAL223_I1_Pos                                     31                                                        /*!< LCD PAL223: I1 Position             */
#define LCD_PAL223_I1_Msk                                     (0x01UL << LCD_PAL223_I1_Pos)                             /*!< LCD PAL223: I1 Mask                 */

// ---------------------------------------  LCD_PAL224  -------------------------------------------
#define LCD_PAL224_R04_0_Pos                                  0                                                         /*!< LCD PAL224: R04_0 Position          */
#define LCD_PAL224_R04_0_Msk                                  (0x1fUL << LCD_PAL224_R04_0_Pos)                          /*!< LCD PAL224: R04_0 Mask              */
#define LCD_PAL224_G04_0_Pos                                  5                                                         /*!< LCD PAL224: G04_0 Position          */
#define LCD_PAL224_G04_0_Msk                                  (0x1fUL << LCD_PAL224_G04_0_Pos)                          /*!< LCD PAL224: G04_0 Mask              */
#define LCD_PAL224_B04_0_Pos                                  10                                                        /*!< LCD PAL224: B04_0 Position          */
#define LCD_PAL224_B04_0_Msk                                  (0x1fUL << LCD_PAL224_B04_0_Pos)                          /*!< LCD PAL224: B04_0 Mask              */
#define LCD_PAL224_I0_Pos                                     15                                                        /*!< LCD PAL224: I0 Position             */
#define LCD_PAL224_I0_Msk                                     (0x01UL << LCD_PAL224_I0_Pos)                             /*!< LCD PAL224: I0 Mask                 */
#define LCD_PAL224_R14_0_Pos                                  16                                                        /*!< LCD PAL224: R14_0 Position          */
#define LCD_PAL224_R14_0_Msk                                  (0x1fUL << LCD_PAL224_R14_0_Pos)                          /*!< LCD PAL224: R14_0 Mask              */
#define LCD_PAL224_G14_0_Pos                                  21                                                        /*!< LCD PAL224: G14_0 Position          */
#define LCD_PAL224_G14_0_Msk                                  (0x1fUL << LCD_PAL224_G14_0_Pos)                          /*!< LCD PAL224: G14_0 Mask              */
#define LCD_PAL224_B14_0_Pos                                  26                                                        /*!< LCD PAL224: B14_0 Position          */
#define LCD_PAL224_B14_0_Msk                                  (0x1fUL << LCD_PAL224_B14_0_Pos)                          /*!< LCD PAL224: B14_0 Mask              */
#define LCD_PAL224_I1_Pos                                     31                                                        /*!< LCD PAL224: I1 Position             */
#define LCD_PAL224_I1_Msk                                     (0x01UL << LCD_PAL224_I1_Pos)                             /*!< LCD PAL224: I1 Mask                 */

// ---------------------------------------  LCD_PAL225  -------------------------------------------
#define LCD_PAL225_R04_0_Pos                                  0                                                         /*!< LCD PAL225: R04_0 Position          */
#define LCD_PAL225_R04_0_Msk                                  (0x1fUL << LCD_PAL225_R04_0_Pos)                          /*!< LCD PAL225: R04_0 Mask              */
#define LCD_PAL225_G04_0_Pos                                  5                                                         /*!< LCD PAL225: G04_0 Position          */
#define LCD_PAL225_G04_0_Msk                                  (0x1fUL << LCD_PAL225_G04_0_Pos)                          /*!< LCD PAL225: G04_0 Mask              */
#define LCD_PAL225_B04_0_Pos                                  10                                                        /*!< LCD PAL225: B04_0 Position          */
#define LCD_PAL225_B04_0_Msk                                  (0x1fUL << LCD_PAL225_B04_0_Pos)                          /*!< LCD PAL225: B04_0 Mask              */
#define LCD_PAL225_I0_Pos                                     15                                                        /*!< LCD PAL225: I0 Position             */
#define LCD_PAL225_I0_Msk                                     (0x01UL << LCD_PAL225_I0_Pos)                             /*!< LCD PAL225: I0 Mask                 */
#define LCD_PAL225_R14_0_Pos                                  16                                                        /*!< LCD PAL225: R14_0 Position          */
#define LCD_PAL225_R14_0_Msk                                  (0x1fUL << LCD_PAL225_R14_0_Pos)                          /*!< LCD PAL225: R14_0 Mask              */
#define LCD_PAL225_G14_0_Pos                                  21                                                        /*!< LCD PAL225: G14_0 Position          */
#define LCD_PAL225_G14_0_Msk                                  (0x1fUL << LCD_PAL225_G14_0_Pos)                          /*!< LCD PAL225: G14_0 Mask              */
#define LCD_PAL225_B14_0_Pos                                  26                                                        /*!< LCD PAL225: B14_0 Position          */
#define LCD_PAL225_B14_0_Msk                                  (0x1fUL << LCD_PAL225_B14_0_Pos)                          /*!< LCD PAL225: B14_0 Mask              */
#define LCD_PAL225_I1_Pos                                     31                                                        /*!< LCD PAL225: I1 Position             */
#define LCD_PAL225_I1_Msk                                     (0x01UL << LCD_PAL225_I1_Pos)                             /*!< LCD PAL225: I1 Mask                 */

// ---------------------------------------  LCD_PAL226  -------------------------------------------
#define LCD_PAL226_R04_0_Pos                                  0                                                         /*!< LCD PAL226: R04_0 Position          */
#define LCD_PAL226_R04_0_Msk                                  (0x1fUL << LCD_PAL226_R04_0_Pos)                          /*!< LCD PAL226: R04_0 Mask              */
#define LCD_PAL226_G04_0_Pos                                  5                                                         /*!< LCD PAL226: G04_0 Position          */
#define LCD_PAL226_G04_0_Msk                                  (0x1fUL << LCD_PAL226_G04_0_Pos)                          /*!< LCD PAL226: G04_0 Mask              */
#define LCD_PAL226_B04_0_Pos                                  10                                                        /*!< LCD PAL226: B04_0 Position          */
#define LCD_PAL226_B04_0_Msk                                  (0x1fUL << LCD_PAL226_B04_0_Pos)                          /*!< LCD PAL226: B04_0 Mask              */
#define LCD_PAL226_I0_Pos                                     15                                                        /*!< LCD PAL226: I0 Position             */
#define LCD_PAL226_I0_Msk                                     (0x01UL << LCD_PAL226_I0_Pos)                             /*!< LCD PAL226: I0 Mask                 */
#define LCD_PAL226_R14_0_Pos                                  16                                                        /*!< LCD PAL226: R14_0 Position          */
#define LCD_PAL226_R14_0_Msk                                  (0x1fUL << LCD_PAL226_R14_0_Pos)                          /*!< LCD PAL226: R14_0 Mask              */
#define LCD_PAL226_G14_0_Pos                                  21                                                        /*!< LCD PAL226: G14_0 Position          */
#define LCD_PAL226_G14_0_Msk                                  (0x1fUL << LCD_PAL226_G14_0_Pos)                          /*!< LCD PAL226: G14_0 Mask              */
#define LCD_PAL226_B14_0_Pos                                  26                                                        /*!< LCD PAL226: B14_0 Position          */
#define LCD_PAL226_B14_0_Msk                                  (0x1fUL << LCD_PAL226_B14_0_Pos)                          /*!< LCD PAL226: B14_0 Mask              */
#define LCD_PAL226_I1_Pos                                     31                                                        /*!< LCD PAL226: I1 Position             */
#define LCD_PAL226_I1_Msk                                     (0x01UL << LCD_PAL226_I1_Pos)                             /*!< LCD PAL226: I1 Mask                 */

// ---------------------------------------  LCD_PAL227  -------------------------------------------
#define LCD_PAL227_R04_0_Pos                                  0                                                         /*!< LCD PAL227: R04_0 Position          */
#define LCD_PAL227_R04_0_Msk                                  (0x1fUL << LCD_PAL227_R04_0_Pos)                          /*!< LCD PAL227: R04_0 Mask              */
#define LCD_PAL227_G04_0_Pos                                  5                                                         /*!< LCD PAL227: G04_0 Position          */
#define LCD_PAL227_G04_0_Msk                                  (0x1fUL << LCD_PAL227_G04_0_Pos)                          /*!< LCD PAL227: G04_0 Mask              */
#define LCD_PAL227_B04_0_Pos                                  10                                                        /*!< LCD PAL227: B04_0 Position          */
#define LCD_PAL227_B04_0_Msk                                  (0x1fUL << LCD_PAL227_B04_0_Pos)                          /*!< LCD PAL227: B04_0 Mask              */
#define LCD_PAL227_I0_Pos                                     15                                                        /*!< LCD PAL227: I0 Position             */
#define LCD_PAL227_I0_Msk                                     (0x01UL << LCD_PAL227_I0_Pos)                             /*!< LCD PAL227: I0 Mask                 */
#define LCD_PAL227_R14_0_Pos                                  16                                                        /*!< LCD PAL227: R14_0 Position          */
#define LCD_PAL227_R14_0_Msk                                  (0x1fUL << LCD_PAL227_R14_0_Pos)                          /*!< LCD PAL227: R14_0 Mask              */
#define LCD_PAL227_G14_0_Pos                                  21                                                        /*!< LCD PAL227: G14_0 Position          */
#define LCD_PAL227_G14_0_Msk                                  (0x1fUL << LCD_PAL227_G14_0_Pos)                          /*!< LCD PAL227: G14_0 Mask              */
#define LCD_PAL227_B14_0_Pos                                  26                                                        /*!< LCD PAL227: B14_0 Position          */
#define LCD_PAL227_B14_0_Msk                                  (0x1fUL << LCD_PAL227_B14_0_Pos)                          /*!< LCD PAL227: B14_0 Mask              */
#define LCD_PAL227_I1_Pos                                     31                                                        /*!< LCD PAL227: I1 Position             */
#define LCD_PAL227_I1_Msk                                     (0x01UL << LCD_PAL227_I1_Pos)                             /*!< LCD PAL227: I1 Mask                 */

// ---------------------------------------  LCD_PAL228  -------------------------------------------
#define LCD_PAL228_R04_0_Pos                                  0                                                         /*!< LCD PAL228: R04_0 Position          */
#define LCD_PAL228_R04_0_Msk                                  (0x1fUL << LCD_PAL228_R04_0_Pos)                          /*!< LCD PAL228: R04_0 Mask              */
#define LCD_PAL228_G04_0_Pos                                  5                                                         /*!< LCD PAL228: G04_0 Position          */
#define LCD_PAL228_G04_0_Msk                                  (0x1fUL << LCD_PAL228_G04_0_Pos)                          /*!< LCD PAL228: G04_0 Mask              */
#define LCD_PAL228_B04_0_Pos                                  10                                                        /*!< LCD PAL228: B04_0 Position          */
#define LCD_PAL228_B04_0_Msk                                  (0x1fUL << LCD_PAL228_B04_0_Pos)                          /*!< LCD PAL228: B04_0 Mask              */
#define LCD_PAL228_I0_Pos                                     15                                                        /*!< LCD PAL228: I0 Position             */
#define LCD_PAL228_I0_Msk                                     (0x01UL << LCD_PAL228_I0_Pos)                             /*!< LCD PAL228: I0 Mask                 */
#define LCD_PAL228_R14_0_Pos                                  16                                                        /*!< LCD PAL228: R14_0 Position          */
#define LCD_PAL228_R14_0_Msk                                  (0x1fUL << LCD_PAL228_R14_0_Pos)                          /*!< LCD PAL228: R14_0 Mask              */
#define LCD_PAL228_G14_0_Pos                                  21                                                        /*!< LCD PAL228: G14_0 Position          */
#define LCD_PAL228_G14_0_Msk                                  (0x1fUL << LCD_PAL228_G14_0_Pos)                          /*!< LCD PAL228: G14_0 Mask              */
#define LCD_PAL228_B14_0_Pos                                  26                                                        /*!< LCD PAL228: B14_0 Position          */
#define LCD_PAL228_B14_0_Msk                                  (0x1fUL << LCD_PAL228_B14_0_Pos)                          /*!< LCD PAL228: B14_0 Mask              */
#define LCD_PAL228_I1_Pos                                     31                                                        /*!< LCD PAL228: I1 Position             */
#define LCD_PAL228_I1_Msk                                     (0x01UL << LCD_PAL228_I1_Pos)                             /*!< LCD PAL228: I1 Mask                 */

// ---------------------------------------  LCD_PAL229  -------------------------------------------
#define LCD_PAL229_R04_0_Pos                                  0                                                         /*!< LCD PAL229: R04_0 Position          */
#define LCD_PAL229_R04_0_Msk                                  (0x1fUL << LCD_PAL229_R04_0_Pos)                          /*!< LCD PAL229: R04_0 Mask              */
#define LCD_PAL229_G04_0_Pos                                  5                                                         /*!< LCD PAL229: G04_0 Position          */
#define LCD_PAL229_G04_0_Msk                                  (0x1fUL << LCD_PAL229_G04_0_Pos)                          /*!< LCD PAL229: G04_0 Mask              */
#define LCD_PAL229_B04_0_Pos                                  10                                                        /*!< LCD PAL229: B04_0 Position          */
#define LCD_PAL229_B04_0_Msk                                  (0x1fUL << LCD_PAL229_B04_0_Pos)                          /*!< LCD PAL229: B04_0 Mask              */
#define LCD_PAL229_I0_Pos                                     15                                                        /*!< LCD PAL229: I0 Position             */
#define LCD_PAL229_I0_Msk                                     (0x01UL << LCD_PAL229_I0_Pos)                             /*!< LCD PAL229: I0 Mask                 */
#define LCD_PAL229_R14_0_Pos                                  16                                                        /*!< LCD PAL229: R14_0 Position          */
#define LCD_PAL229_R14_0_Msk                                  (0x1fUL << LCD_PAL229_R14_0_Pos)                          /*!< LCD PAL229: R14_0 Mask              */
#define LCD_PAL229_G14_0_Pos                                  21                                                        /*!< LCD PAL229: G14_0 Position          */
#define LCD_PAL229_G14_0_Msk                                  (0x1fUL << LCD_PAL229_G14_0_Pos)                          /*!< LCD PAL229: G14_0 Mask              */
#define LCD_PAL229_B14_0_Pos                                  26                                                        /*!< LCD PAL229: B14_0 Position          */
#define LCD_PAL229_B14_0_Msk                                  (0x1fUL << LCD_PAL229_B14_0_Pos)                          /*!< LCD PAL229: B14_0 Mask              */
#define LCD_PAL229_I1_Pos                                     31                                                        /*!< LCD PAL229: I1 Position             */
#define LCD_PAL229_I1_Msk                                     (0x01UL << LCD_PAL229_I1_Pos)                             /*!< LCD PAL229: I1 Mask                 */

// ---------------------------------------  LCD_PAL230  -------------------------------------------
#define LCD_PAL230_R04_0_Pos                                  0                                                         /*!< LCD PAL230: R04_0 Position          */
#define LCD_PAL230_R04_0_Msk                                  (0x1fUL << LCD_PAL230_R04_0_Pos)                          /*!< LCD PAL230: R04_0 Mask              */
#define LCD_PAL230_G04_0_Pos                                  5                                                         /*!< LCD PAL230: G04_0 Position          */
#define LCD_PAL230_G04_0_Msk                                  (0x1fUL << LCD_PAL230_G04_0_Pos)                          /*!< LCD PAL230: G04_0 Mask              */
#define LCD_PAL230_B04_0_Pos                                  10                                                        /*!< LCD PAL230: B04_0 Position          */
#define LCD_PAL230_B04_0_Msk                                  (0x1fUL << LCD_PAL230_B04_0_Pos)                          /*!< LCD PAL230: B04_0 Mask              */
#define LCD_PAL230_I0_Pos                                     15                                                        /*!< LCD PAL230: I0 Position             */
#define LCD_PAL230_I0_Msk                                     (0x01UL << LCD_PAL230_I0_Pos)                             /*!< LCD PAL230: I0 Mask                 */
#define LCD_PAL230_R14_0_Pos                                  16                                                        /*!< LCD PAL230: R14_0 Position          */
#define LCD_PAL230_R14_0_Msk                                  (0x1fUL << LCD_PAL230_R14_0_Pos)                          /*!< LCD PAL230: R14_0 Mask              */
#define LCD_PAL230_G14_0_Pos                                  21                                                        /*!< LCD PAL230: G14_0 Position          */
#define LCD_PAL230_G14_0_Msk                                  (0x1fUL << LCD_PAL230_G14_0_Pos)                          /*!< LCD PAL230: G14_0 Mask              */
#define LCD_PAL230_B14_0_Pos                                  26                                                        /*!< LCD PAL230: B14_0 Position          */
#define LCD_PAL230_B14_0_Msk                                  (0x1fUL << LCD_PAL230_B14_0_Pos)                          /*!< LCD PAL230: B14_0 Mask              */
#define LCD_PAL230_I1_Pos                                     31                                                        /*!< LCD PAL230: I1 Position             */
#define LCD_PAL230_I1_Msk                                     (0x01UL << LCD_PAL230_I1_Pos)                             /*!< LCD PAL230: I1 Mask                 */

// ---------------------------------------  LCD_PAL231  -------------------------------------------
#define LCD_PAL231_R04_0_Pos                                  0                                                         /*!< LCD PAL231: R04_0 Position          */
#define LCD_PAL231_R04_0_Msk                                  (0x1fUL << LCD_PAL231_R04_0_Pos)                          /*!< LCD PAL231: R04_0 Mask              */
#define LCD_PAL231_G04_0_Pos                                  5                                                         /*!< LCD PAL231: G04_0 Position          */
#define LCD_PAL231_G04_0_Msk                                  (0x1fUL << LCD_PAL231_G04_0_Pos)                          /*!< LCD PAL231: G04_0 Mask              */
#define LCD_PAL231_B04_0_Pos                                  10                                                        /*!< LCD PAL231: B04_0 Position          */
#define LCD_PAL231_B04_0_Msk                                  (0x1fUL << LCD_PAL231_B04_0_Pos)                          /*!< LCD PAL231: B04_0 Mask              */
#define LCD_PAL231_I0_Pos                                     15                                                        /*!< LCD PAL231: I0 Position             */
#define LCD_PAL231_I0_Msk                                     (0x01UL << LCD_PAL231_I0_Pos)                             /*!< LCD PAL231: I0 Mask                 */
#define LCD_PAL231_R14_0_Pos                                  16                                                        /*!< LCD PAL231: R14_0 Position          */
#define LCD_PAL231_R14_0_Msk                                  (0x1fUL << LCD_PAL231_R14_0_Pos)                          /*!< LCD PAL231: R14_0 Mask              */
#define LCD_PAL231_G14_0_Pos                                  21                                                        /*!< LCD PAL231: G14_0 Position          */
#define LCD_PAL231_G14_0_Msk                                  (0x1fUL << LCD_PAL231_G14_0_Pos)                          /*!< LCD PAL231: G14_0 Mask              */
#define LCD_PAL231_B14_0_Pos                                  26                                                        /*!< LCD PAL231: B14_0 Position          */
#define LCD_PAL231_B14_0_Msk                                  (0x1fUL << LCD_PAL231_B14_0_Pos)                          /*!< LCD PAL231: B14_0 Mask              */
#define LCD_PAL231_I1_Pos                                     31                                                        /*!< LCD PAL231: I1 Position             */
#define LCD_PAL231_I1_Msk                                     (0x01UL << LCD_PAL231_I1_Pos)                             /*!< LCD PAL231: I1 Mask                 */

// ---------------------------------------  LCD_PAL232  -------------------------------------------
#define LCD_PAL232_R04_0_Pos                                  0                                                         /*!< LCD PAL232: R04_0 Position          */
#define LCD_PAL232_R04_0_Msk                                  (0x1fUL << LCD_PAL232_R04_0_Pos)                          /*!< LCD PAL232: R04_0 Mask              */
#define LCD_PAL232_G04_0_Pos                                  5                                                         /*!< LCD PAL232: G04_0 Position          */
#define LCD_PAL232_G04_0_Msk                                  (0x1fUL << LCD_PAL232_G04_0_Pos)                          /*!< LCD PAL232: G04_0 Mask              */
#define LCD_PAL232_B04_0_Pos                                  10                                                        /*!< LCD PAL232: B04_0 Position          */
#define LCD_PAL232_B04_0_Msk                                  (0x1fUL << LCD_PAL232_B04_0_Pos)                          /*!< LCD PAL232: B04_0 Mask              */
#define LCD_PAL232_I0_Pos                                     15                                                        /*!< LCD PAL232: I0 Position             */
#define LCD_PAL232_I0_Msk                                     (0x01UL << LCD_PAL232_I0_Pos)                             /*!< LCD PAL232: I0 Mask                 */
#define LCD_PAL232_R14_0_Pos                                  16                                                        /*!< LCD PAL232: R14_0 Position          */
#define LCD_PAL232_R14_0_Msk                                  (0x1fUL << LCD_PAL232_R14_0_Pos)                          /*!< LCD PAL232: R14_0 Mask              */
#define LCD_PAL232_G14_0_Pos                                  21                                                        /*!< LCD PAL232: G14_0 Position          */
#define LCD_PAL232_G14_0_Msk                                  (0x1fUL << LCD_PAL232_G14_0_Pos)                          /*!< LCD PAL232: G14_0 Mask              */
#define LCD_PAL232_B14_0_Pos                                  26                                                        /*!< LCD PAL232: B14_0 Position          */
#define LCD_PAL232_B14_0_Msk                                  (0x1fUL << LCD_PAL232_B14_0_Pos)                          /*!< LCD PAL232: B14_0 Mask              */
#define LCD_PAL232_I1_Pos                                     31                                                        /*!< LCD PAL232: I1 Position             */
#define LCD_PAL232_I1_Msk                                     (0x01UL << LCD_PAL232_I1_Pos)                             /*!< LCD PAL232: I1 Mask                 */

// ---------------------------------------  LCD_PAL233  -------------------------------------------
#define LCD_PAL233_R04_0_Pos                                  0                                                         /*!< LCD PAL233: R04_0 Position          */
#define LCD_PAL233_R04_0_Msk                                  (0x1fUL << LCD_PAL233_R04_0_Pos)                          /*!< LCD PAL233: R04_0 Mask              */
#define LCD_PAL233_G04_0_Pos                                  5                                                         /*!< LCD PAL233: G04_0 Position          */
#define LCD_PAL233_G04_0_Msk                                  (0x1fUL << LCD_PAL233_G04_0_Pos)                          /*!< LCD PAL233: G04_0 Mask              */
#define LCD_PAL233_B04_0_Pos                                  10                                                        /*!< LCD PAL233: B04_0 Position          */
#define LCD_PAL233_B04_0_Msk                                  (0x1fUL << LCD_PAL233_B04_0_Pos)                          /*!< LCD PAL233: B04_0 Mask              */
#define LCD_PAL233_I0_Pos                                     15                                                        /*!< LCD PAL233: I0 Position             */
#define LCD_PAL233_I0_Msk                                     (0x01UL << LCD_PAL233_I0_Pos)                             /*!< LCD PAL233: I0 Mask                 */
#define LCD_PAL233_R14_0_Pos                                  16                                                        /*!< LCD PAL233: R14_0 Position          */
#define LCD_PAL233_R14_0_Msk                                  (0x1fUL << LCD_PAL233_R14_0_Pos)                          /*!< LCD PAL233: R14_0 Mask              */
#define LCD_PAL233_G14_0_Pos                                  21                                                        /*!< LCD PAL233: G14_0 Position          */
#define LCD_PAL233_G14_0_Msk                                  (0x1fUL << LCD_PAL233_G14_0_Pos)                          /*!< LCD PAL233: G14_0 Mask              */
#define LCD_PAL233_B14_0_Pos                                  26                                                        /*!< LCD PAL233: B14_0 Position          */
#define LCD_PAL233_B14_0_Msk                                  (0x1fUL << LCD_PAL233_B14_0_Pos)                          /*!< LCD PAL233: B14_0 Mask              */
#define LCD_PAL233_I1_Pos                                     31                                                        /*!< LCD PAL233: I1 Position             */
#define LCD_PAL233_I1_Msk                                     (0x01UL << LCD_PAL233_I1_Pos)                             /*!< LCD PAL233: I1 Mask                 */

// ---------------------------------------  LCD_PAL234  -------------------------------------------
#define LCD_PAL234_R04_0_Pos                                  0                                                         /*!< LCD PAL234: R04_0 Position          */
#define LCD_PAL234_R04_0_Msk                                  (0x1fUL << LCD_PAL234_R04_0_Pos)                          /*!< LCD PAL234: R04_0 Mask              */
#define LCD_PAL234_G04_0_Pos                                  5                                                         /*!< LCD PAL234: G04_0 Position          */
#define LCD_PAL234_G04_0_Msk                                  (0x1fUL << LCD_PAL234_G04_0_Pos)                          /*!< LCD PAL234: G04_0 Mask              */
#define LCD_PAL234_B04_0_Pos                                  10                                                        /*!< LCD PAL234: B04_0 Position          */
#define LCD_PAL234_B04_0_Msk                                  (0x1fUL << LCD_PAL234_B04_0_Pos)                          /*!< LCD PAL234: B04_0 Mask              */
#define LCD_PAL234_I0_Pos                                     15                                                        /*!< LCD PAL234: I0 Position             */
#define LCD_PAL234_I0_Msk                                     (0x01UL << LCD_PAL234_I0_Pos)                             /*!< LCD PAL234: I0 Mask                 */
#define LCD_PAL234_R14_0_Pos                                  16                                                        /*!< LCD PAL234: R14_0 Position          */
#define LCD_PAL234_R14_0_Msk                                  (0x1fUL << LCD_PAL234_R14_0_Pos)                          /*!< LCD PAL234: R14_0 Mask              */
#define LCD_PAL234_G14_0_Pos                                  21                                                        /*!< LCD PAL234: G14_0 Position          */
#define LCD_PAL234_G14_0_Msk                                  (0x1fUL << LCD_PAL234_G14_0_Pos)                          /*!< LCD PAL234: G14_0 Mask              */
#define LCD_PAL234_B14_0_Pos                                  26                                                        /*!< LCD PAL234: B14_0 Position          */
#define LCD_PAL234_B14_0_Msk                                  (0x1fUL << LCD_PAL234_B14_0_Pos)                          /*!< LCD PAL234: B14_0 Mask              */
#define LCD_PAL234_I1_Pos                                     31                                                        /*!< LCD PAL234: I1 Position             */
#define LCD_PAL234_I1_Msk                                     (0x01UL << LCD_PAL234_I1_Pos)                             /*!< LCD PAL234: I1 Mask                 */

// ---------------------------------------  LCD_PAL235  -------------------------------------------
#define LCD_PAL235_R04_0_Pos                                  0                                                         /*!< LCD PAL235: R04_0 Position          */
#define LCD_PAL235_R04_0_Msk                                  (0x1fUL << LCD_PAL235_R04_0_Pos)                          /*!< LCD PAL235: R04_0 Mask              */
#define LCD_PAL235_G04_0_Pos                                  5                                                         /*!< LCD PAL235: G04_0 Position          */
#define LCD_PAL235_G04_0_Msk                                  (0x1fUL << LCD_PAL235_G04_0_Pos)                          /*!< LCD PAL235: G04_0 Mask              */
#define LCD_PAL235_B04_0_Pos                                  10                                                        /*!< LCD PAL235: B04_0 Position          */
#define LCD_PAL235_B04_0_Msk                                  (0x1fUL << LCD_PAL235_B04_0_Pos)                          /*!< LCD PAL235: B04_0 Mask              */
#define LCD_PAL235_I0_Pos                                     15                                                        /*!< LCD PAL235: I0 Position             */
#define LCD_PAL235_I0_Msk                                     (0x01UL << LCD_PAL235_I0_Pos)                             /*!< LCD PAL235: I0 Mask                 */
#define LCD_PAL235_R14_0_Pos                                  16                                                        /*!< LCD PAL235: R14_0 Position          */
#define LCD_PAL235_R14_0_Msk                                  (0x1fUL << LCD_PAL235_R14_0_Pos)                          /*!< LCD PAL235: R14_0 Mask              */
#define LCD_PAL235_G14_0_Pos                                  21                                                        /*!< LCD PAL235: G14_0 Position          */
#define LCD_PAL235_G14_0_Msk                                  (0x1fUL << LCD_PAL235_G14_0_Pos)                          /*!< LCD PAL235: G14_0 Mask              */
#define LCD_PAL235_B14_0_Pos                                  26                                                        /*!< LCD PAL235: B14_0 Position          */
#define LCD_PAL235_B14_0_Msk                                  (0x1fUL << LCD_PAL235_B14_0_Pos)                          /*!< LCD PAL235: B14_0 Mask              */
#define LCD_PAL235_I1_Pos                                     31                                                        /*!< LCD PAL235: I1 Position             */
#define LCD_PAL235_I1_Msk                                     (0x01UL << LCD_PAL235_I1_Pos)                             /*!< LCD PAL235: I1 Mask                 */

// ---------------------------------------  LCD_PAL236  -------------------------------------------
#define LCD_PAL236_R04_0_Pos                                  0                                                         /*!< LCD PAL236: R04_0 Position          */
#define LCD_PAL236_R04_0_Msk                                  (0x1fUL << LCD_PAL236_R04_0_Pos)                          /*!< LCD PAL236: R04_0 Mask              */
#define LCD_PAL236_G04_0_Pos                                  5                                                         /*!< LCD PAL236: G04_0 Position          */
#define LCD_PAL236_G04_0_Msk                                  (0x1fUL << LCD_PAL236_G04_0_Pos)                          /*!< LCD PAL236: G04_0 Mask              */
#define LCD_PAL236_B04_0_Pos                                  10                                                        /*!< LCD PAL236: B04_0 Position          */
#define LCD_PAL236_B04_0_Msk                                  (0x1fUL << LCD_PAL236_B04_0_Pos)                          /*!< LCD PAL236: B04_0 Mask              */
#define LCD_PAL236_I0_Pos                                     15                                                        /*!< LCD PAL236: I0 Position             */
#define LCD_PAL236_I0_Msk                                     (0x01UL << LCD_PAL236_I0_Pos)                             /*!< LCD PAL236: I0 Mask                 */
#define LCD_PAL236_R14_0_Pos                                  16                                                        /*!< LCD PAL236: R14_0 Position          */
#define LCD_PAL236_R14_0_Msk                                  (0x1fUL << LCD_PAL236_R14_0_Pos)                          /*!< LCD PAL236: R14_0 Mask              */
#define LCD_PAL236_G14_0_Pos                                  21                                                        /*!< LCD PAL236: G14_0 Position          */
#define LCD_PAL236_G14_0_Msk                                  (0x1fUL << LCD_PAL236_G14_0_Pos)                          /*!< LCD PAL236: G14_0 Mask              */
#define LCD_PAL236_B14_0_Pos                                  26                                                        /*!< LCD PAL236: B14_0 Position          */
#define LCD_PAL236_B14_0_Msk                                  (0x1fUL << LCD_PAL236_B14_0_Pos)                          /*!< LCD PAL236: B14_0 Mask              */
#define LCD_PAL236_I1_Pos                                     31                                                        /*!< LCD PAL236: I1 Position             */
#define LCD_PAL236_I1_Msk                                     (0x01UL << LCD_PAL236_I1_Pos)                             /*!< LCD PAL236: I1 Mask                 */

// ---------------------------------------  LCD_PAL237  -------------------------------------------
#define LCD_PAL237_R04_0_Pos                                  0                                                         /*!< LCD PAL237: R04_0 Position          */
#define LCD_PAL237_R04_0_Msk                                  (0x1fUL << LCD_PAL237_R04_0_Pos)                          /*!< LCD PAL237: R04_0 Mask              */
#define LCD_PAL237_G04_0_Pos                                  5                                                         /*!< LCD PAL237: G04_0 Position          */
#define LCD_PAL237_G04_0_Msk                                  (0x1fUL << LCD_PAL237_G04_0_Pos)                          /*!< LCD PAL237: G04_0 Mask              */
#define LCD_PAL237_B04_0_Pos                                  10                                                        /*!< LCD PAL237: B04_0 Position          */
#define LCD_PAL237_B04_0_Msk                                  (0x1fUL << LCD_PAL237_B04_0_Pos)                          /*!< LCD PAL237: B04_0 Mask              */
#define LCD_PAL237_I0_Pos                                     15                                                        /*!< LCD PAL237: I0 Position             */
#define LCD_PAL237_I0_Msk                                     (0x01UL << LCD_PAL237_I0_Pos)                             /*!< LCD PAL237: I0 Mask                 */
#define LCD_PAL237_R14_0_Pos                                  16                                                        /*!< LCD PAL237: R14_0 Position          */
#define LCD_PAL237_R14_0_Msk                                  (0x1fUL << LCD_PAL237_R14_0_Pos)                          /*!< LCD PAL237: R14_0 Mask              */
#define LCD_PAL237_G14_0_Pos                                  21                                                        /*!< LCD PAL237: G14_0 Position          */
#define LCD_PAL237_G14_0_Msk                                  (0x1fUL << LCD_PAL237_G14_0_Pos)                          /*!< LCD PAL237: G14_0 Mask              */
#define LCD_PAL237_B14_0_Pos                                  26                                                        /*!< LCD PAL237: B14_0 Position          */
#define LCD_PAL237_B14_0_Msk                                  (0x1fUL << LCD_PAL237_B14_0_Pos)                          /*!< LCD PAL237: B14_0 Mask              */
#define LCD_PAL237_I1_Pos                                     31                                                        /*!< LCD PAL237: I1 Position             */
#define LCD_PAL237_I1_Msk                                     (0x01UL << LCD_PAL237_I1_Pos)                             /*!< LCD PAL237: I1 Mask                 */

// ---------------------------------------  LCD_PAL238  -------------------------------------------
#define LCD_PAL238_R04_0_Pos                                  0                                                         /*!< LCD PAL238: R04_0 Position          */
#define LCD_PAL238_R04_0_Msk                                  (0x1fUL << LCD_PAL238_R04_0_Pos)                          /*!< LCD PAL238: R04_0 Mask              */
#define LCD_PAL238_G04_0_Pos                                  5                                                         /*!< LCD PAL238: G04_0 Position          */
#define LCD_PAL238_G04_0_Msk                                  (0x1fUL << LCD_PAL238_G04_0_Pos)                          /*!< LCD PAL238: G04_0 Mask              */
#define LCD_PAL238_B04_0_Pos                                  10                                                        /*!< LCD PAL238: B04_0 Position          */
#define LCD_PAL238_B04_0_Msk                                  (0x1fUL << LCD_PAL238_B04_0_Pos)                          /*!< LCD PAL238: B04_0 Mask              */
#define LCD_PAL238_I0_Pos                                     15                                                        /*!< LCD PAL238: I0 Position             */
#define LCD_PAL238_I0_Msk                                     (0x01UL << LCD_PAL238_I0_Pos)                             /*!< LCD PAL238: I0 Mask                 */
#define LCD_PAL238_R14_0_Pos                                  16                                                        /*!< LCD PAL238: R14_0 Position          */
#define LCD_PAL238_R14_0_Msk                                  (0x1fUL << LCD_PAL238_R14_0_Pos)                          /*!< LCD PAL238: R14_0 Mask              */
#define LCD_PAL238_G14_0_Pos                                  21                                                        /*!< LCD PAL238: G14_0 Position          */
#define LCD_PAL238_G14_0_Msk                                  (0x1fUL << LCD_PAL238_G14_0_Pos)                          /*!< LCD PAL238: G14_0 Mask              */
#define LCD_PAL238_B14_0_Pos                                  26                                                        /*!< LCD PAL238: B14_0 Position          */
#define LCD_PAL238_B14_0_Msk                                  (0x1fUL << LCD_PAL238_B14_0_Pos)                          /*!< LCD PAL238: B14_0 Mask              */
#define LCD_PAL238_I1_Pos                                     31                                                        /*!< LCD PAL238: I1 Position             */
#define LCD_PAL238_I1_Msk                                     (0x01UL << LCD_PAL238_I1_Pos)                             /*!< LCD PAL238: I1 Mask                 */

// ---------------------------------------  LCD_PAL239  -------------------------------------------
#define LCD_PAL239_R04_0_Pos                                  0                                                         /*!< LCD PAL239: R04_0 Position          */
#define LCD_PAL239_R04_0_Msk                                  (0x1fUL << LCD_PAL239_R04_0_Pos)                          /*!< LCD PAL239: R04_0 Mask              */
#define LCD_PAL239_G04_0_Pos                                  5                                                         /*!< LCD PAL239: G04_0 Position          */
#define LCD_PAL239_G04_0_Msk                                  (0x1fUL << LCD_PAL239_G04_0_Pos)                          /*!< LCD PAL239: G04_0 Mask              */
#define LCD_PAL239_B04_0_Pos                                  10                                                        /*!< LCD PAL239: B04_0 Position          */
#define LCD_PAL239_B04_0_Msk                                  (0x1fUL << LCD_PAL239_B04_0_Pos)                          /*!< LCD PAL239: B04_0 Mask              */
#define LCD_PAL239_I0_Pos                                     15                                                        /*!< LCD PAL239: I0 Position             */
#define LCD_PAL239_I0_Msk                                     (0x01UL << LCD_PAL239_I0_Pos)                             /*!< LCD PAL239: I0 Mask                 */
#define LCD_PAL239_R14_0_Pos                                  16                                                        /*!< LCD PAL239: R14_0 Position          */
#define LCD_PAL239_R14_0_Msk                                  (0x1fUL << LCD_PAL239_R14_0_Pos)                          /*!< LCD PAL239: R14_0 Mask              */
#define LCD_PAL239_G14_0_Pos                                  21                                                        /*!< LCD PAL239: G14_0 Position          */
#define LCD_PAL239_G14_0_Msk                                  (0x1fUL << LCD_PAL239_G14_0_Pos)                          /*!< LCD PAL239: G14_0 Mask              */
#define LCD_PAL239_B14_0_Pos                                  26                                                        /*!< LCD PAL239: B14_0 Position          */
#define LCD_PAL239_B14_0_Msk                                  (0x1fUL << LCD_PAL239_B14_0_Pos)                          /*!< LCD PAL239: B14_0 Mask              */
#define LCD_PAL239_I1_Pos                                     31                                                        /*!< LCD PAL239: I1 Position             */
#define LCD_PAL239_I1_Msk                                     (0x01UL << LCD_PAL239_I1_Pos)                             /*!< LCD PAL239: I1 Mask                 */

// ---------------------------------------  LCD_PAL240  -------------------------------------------
#define LCD_PAL240_R04_0_Pos                                  0                                                         /*!< LCD PAL240: R04_0 Position          */
#define LCD_PAL240_R04_0_Msk                                  (0x1fUL << LCD_PAL240_R04_0_Pos)                          /*!< LCD PAL240: R04_0 Mask              */
#define LCD_PAL240_G04_0_Pos                                  5                                                         /*!< LCD PAL240: G04_0 Position          */
#define LCD_PAL240_G04_0_Msk                                  (0x1fUL << LCD_PAL240_G04_0_Pos)                          /*!< LCD PAL240: G04_0 Mask              */
#define LCD_PAL240_B04_0_Pos                                  10                                                        /*!< LCD PAL240: B04_0 Position          */
#define LCD_PAL240_B04_0_Msk                                  (0x1fUL << LCD_PAL240_B04_0_Pos)                          /*!< LCD PAL240: B04_0 Mask              */
#define LCD_PAL240_I0_Pos                                     15                                                        /*!< LCD PAL240: I0 Position             */
#define LCD_PAL240_I0_Msk                                     (0x01UL << LCD_PAL240_I0_Pos)                             /*!< LCD PAL240: I0 Mask                 */
#define LCD_PAL240_R14_0_Pos                                  16                                                        /*!< LCD PAL240: R14_0 Position          */
#define LCD_PAL240_R14_0_Msk                                  (0x1fUL << LCD_PAL240_R14_0_Pos)                          /*!< LCD PAL240: R14_0 Mask              */
#define LCD_PAL240_G14_0_Pos                                  21                                                        /*!< LCD PAL240: G14_0 Position          */
#define LCD_PAL240_G14_0_Msk                                  (0x1fUL << LCD_PAL240_G14_0_Pos)                          /*!< LCD PAL240: G14_0 Mask              */
#define LCD_PAL240_B14_0_Pos                                  26                                                        /*!< LCD PAL240: B14_0 Position          */
#define LCD_PAL240_B14_0_Msk                                  (0x1fUL << LCD_PAL240_B14_0_Pos)                          /*!< LCD PAL240: B14_0 Mask              */
#define LCD_PAL240_I1_Pos                                     31                                                        /*!< LCD PAL240: I1 Position             */
#define LCD_PAL240_I1_Msk                                     (0x01UL << LCD_PAL240_I1_Pos)                             /*!< LCD PAL240: I1 Mask                 */

// ---------------------------------------  LCD_PAL241  -------------------------------------------
#define LCD_PAL241_R04_0_Pos                                  0                                                         /*!< LCD PAL241: R04_0 Position          */
#define LCD_PAL241_R04_0_Msk                                  (0x1fUL << LCD_PAL241_R04_0_Pos)                          /*!< LCD PAL241: R04_0 Mask              */
#define LCD_PAL241_G04_0_Pos                                  5                                                         /*!< LCD PAL241: G04_0 Position          */
#define LCD_PAL241_G04_0_Msk                                  (0x1fUL << LCD_PAL241_G04_0_Pos)                          /*!< LCD PAL241: G04_0 Mask              */
#define LCD_PAL241_B04_0_Pos                                  10                                                        /*!< LCD PAL241: B04_0 Position          */
#define LCD_PAL241_B04_0_Msk                                  (0x1fUL << LCD_PAL241_B04_0_Pos)                          /*!< LCD PAL241: B04_0 Mask              */
#define LCD_PAL241_I0_Pos                                     15                                                        /*!< LCD PAL241: I0 Position             */
#define LCD_PAL241_I0_Msk                                     (0x01UL << LCD_PAL241_I0_Pos)                             /*!< LCD PAL241: I0 Mask                 */
#define LCD_PAL241_R14_0_Pos                                  16                                                        /*!< LCD PAL241: R14_0 Position          */
#define LCD_PAL241_R14_0_Msk                                  (0x1fUL << LCD_PAL241_R14_0_Pos)                          /*!< LCD PAL241: R14_0 Mask              */
#define LCD_PAL241_G14_0_Pos                                  21                                                        /*!< LCD PAL241: G14_0 Position          */
#define LCD_PAL241_G14_0_Msk                                  (0x1fUL << LCD_PAL241_G14_0_Pos)                          /*!< LCD PAL241: G14_0 Mask              */
#define LCD_PAL241_B14_0_Pos                                  26                                                        /*!< LCD PAL241: B14_0 Position          */
#define LCD_PAL241_B14_0_Msk                                  (0x1fUL << LCD_PAL241_B14_0_Pos)                          /*!< LCD PAL241: B14_0 Mask              */
#define LCD_PAL241_I1_Pos                                     31                                                        /*!< LCD PAL241: I1 Position             */
#define LCD_PAL241_I1_Msk                                     (0x01UL << LCD_PAL241_I1_Pos)                             /*!< LCD PAL241: I1 Mask                 */

// ---------------------------------------  LCD_PAL242  -------------------------------------------
#define LCD_PAL242_R04_0_Pos                                  0                                                         /*!< LCD PAL242: R04_0 Position          */
#define LCD_PAL242_R04_0_Msk                                  (0x1fUL << LCD_PAL242_R04_0_Pos)                          /*!< LCD PAL242: R04_0 Mask              */
#define LCD_PAL242_G04_0_Pos                                  5                                                         /*!< LCD PAL242: G04_0 Position          */
#define LCD_PAL242_G04_0_Msk                                  (0x1fUL << LCD_PAL242_G04_0_Pos)                          /*!< LCD PAL242: G04_0 Mask              */
#define LCD_PAL242_B04_0_Pos                                  10                                                        /*!< LCD PAL242: B04_0 Position          */
#define LCD_PAL242_B04_0_Msk                                  (0x1fUL << LCD_PAL242_B04_0_Pos)                          /*!< LCD PAL242: B04_0 Mask              */
#define LCD_PAL242_I0_Pos                                     15                                                        /*!< LCD PAL242: I0 Position             */
#define LCD_PAL242_I0_Msk                                     (0x01UL << LCD_PAL242_I0_Pos)                             /*!< LCD PAL242: I0 Mask                 */
#define LCD_PAL242_R14_0_Pos                                  16                                                        /*!< LCD PAL242: R14_0 Position          */
#define LCD_PAL242_R14_0_Msk                                  (0x1fUL << LCD_PAL242_R14_0_Pos)                          /*!< LCD PAL242: R14_0 Mask              */
#define LCD_PAL242_G14_0_Pos                                  21                                                        /*!< LCD PAL242: G14_0 Position          */
#define LCD_PAL242_G14_0_Msk                                  (0x1fUL << LCD_PAL242_G14_0_Pos)                          /*!< LCD PAL242: G14_0 Mask              */
#define LCD_PAL242_B14_0_Pos                                  26                                                        /*!< LCD PAL242: B14_0 Position          */
#define LCD_PAL242_B14_0_Msk                                  (0x1fUL << LCD_PAL242_B14_0_Pos)                          /*!< LCD PAL242: B14_0 Mask              */
#define LCD_PAL242_I1_Pos                                     31                                                        /*!< LCD PAL242: I1 Position             */
#define LCD_PAL242_I1_Msk                                     (0x01UL << LCD_PAL242_I1_Pos)                             /*!< LCD PAL242: I1 Mask                 */

// ---------------------------------------  LCD_PAL243  -------------------------------------------
#define LCD_PAL243_R04_0_Pos                                  0                                                         /*!< LCD PAL243: R04_0 Position          */
#define LCD_PAL243_R04_0_Msk                                  (0x1fUL << LCD_PAL243_R04_0_Pos)                          /*!< LCD PAL243: R04_0 Mask              */
#define LCD_PAL243_G04_0_Pos                                  5                                                         /*!< LCD PAL243: G04_0 Position          */
#define LCD_PAL243_G04_0_Msk                                  (0x1fUL << LCD_PAL243_G04_0_Pos)                          /*!< LCD PAL243: G04_0 Mask              */
#define LCD_PAL243_B04_0_Pos                                  10                                                        /*!< LCD PAL243: B04_0 Position          */
#define LCD_PAL243_B04_0_Msk                                  (0x1fUL << LCD_PAL243_B04_0_Pos)                          /*!< LCD PAL243: B04_0 Mask              */
#define LCD_PAL243_I0_Pos                                     15                                                        /*!< LCD PAL243: I0 Position             */
#define LCD_PAL243_I0_Msk                                     (0x01UL << LCD_PAL243_I0_Pos)                             /*!< LCD PAL243: I0 Mask                 */
#define LCD_PAL243_R14_0_Pos                                  16                                                        /*!< LCD PAL243: R14_0 Position          */
#define LCD_PAL243_R14_0_Msk                                  (0x1fUL << LCD_PAL243_R14_0_Pos)                          /*!< LCD PAL243: R14_0 Mask              */
#define LCD_PAL243_G14_0_Pos                                  21                                                        /*!< LCD PAL243: G14_0 Position          */
#define LCD_PAL243_G14_0_Msk                                  (0x1fUL << LCD_PAL243_G14_0_Pos)                          /*!< LCD PAL243: G14_0 Mask              */
#define LCD_PAL243_B14_0_Pos                                  26                                                        /*!< LCD PAL243: B14_0 Position          */
#define LCD_PAL243_B14_0_Msk                                  (0x1fUL << LCD_PAL243_B14_0_Pos)                          /*!< LCD PAL243: B14_0 Mask              */
#define LCD_PAL243_I1_Pos                                     31                                                        /*!< LCD PAL243: I1 Position             */
#define LCD_PAL243_I1_Msk                                     (0x01UL << LCD_PAL243_I1_Pos)                             /*!< LCD PAL243: I1 Mask                 */

// ---------------------------------------  LCD_PAL244  -------------------------------------------
#define LCD_PAL244_R04_0_Pos                                  0                                                         /*!< LCD PAL244: R04_0 Position          */
#define LCD_PAL244_R04_0_Msk                                  (0x1fUL << LCD_PAL244_R04_0_Pos)                          /*!< LCD PAL244: R04_0 Mask              */
#define LCD_PAL244_G04_0_Pos                                  5                                                         /*!< LCD PAL244: G04_0 Position          */
#define LCD_PAL244_G04_0_Msk                                  (0x1fUL << LCD_PAL244_G04_0_Pos)                          /*!< LCD PAL244: G04_0 Mask              */
#define LCD_PAL244_B04_0_Pos                                  10                                                        /*!< LCD PAL244: B04_0 Position          */
#define LCD_PAL244_B04_0_Msk                                  (0x1fUL << LCD_PAL244_B04_0_Pos)                          /*!< LCD PAL244: B04_0 Mask              */
#define LCD_PAL244_I0_Pos                                     15                                                        /*!< LCD PAL244: I0 Position             */
#define LCD_PAL244_I0_Msk                                     (0x01UL << LCD_PAL244_I0_Pos)                             /*!< LCD PAL244: I0 Mask                 */
#define LCD_PAL244_R14_0_Pos                                  16                                                        /*!< LCD PAL244: R14_0 Position          */
#define LCD_PAL244_R14_0_Msk                                  (0x1fUL << LCD_PAL244_R14_0_Pos)                          /*!< LCD PAL244: R14_0 Mask              */
#define LCD_PAL244_G14_0_Pos                                  21                                                        /*!< LCD PAL244: G14_0 Position          */
#define LCD_PAL244_G14_0_Msk                                  (0x1fUL << LCD_PAL244_G14_0_Pos)                          /*!< LCD PAL244: G14_0 Mask              */
#define LCD_PAL244_B14_0_Pos                                  26                                                        /*!< LCD PAL244: B14_0 Position          */
#define LCD_PAL244_B14_0_Msk                                  (0x1fUL << LCD_PAL244_B14_0_Pos)                          /*!< LCD PAL244: B14_0 Mask              */
#define LCD_PAL244_I1_Pos                                     31                                                        /*!< LCD PAL244: I1 Position             */
#define LCD_PAL244_I1_Msk                                     (0x01UL << LCD_PAL244_I1_Pos)                             /*!< LCD PAL244: I1 Mask                 */

// ---------------------------------------  LCD_PAL245  -------------------------------------------
#define LCD_PAL245_R04_0_Pos                                  0                                                         /*!< LCD PAL245: R04_0 Position          */
#define LCD_PAL245_R04_0_Msk                                  (0x1fUL << LCD_PAL245_R04_0_Pos)                          /*!< LCD PAL245: R04_0 Mask              */
#define LCD_PAL245_G04_0_Pos                                  5                                                         /*!< LCD PAL245: G04_0 Position          */
#define LCD_PAL245_G04_0_Msk                                  (0x1fUL << LCD_PAL245_G04_0_Pos)                          /*!< LCD PAL245: G04_0 Mask              */
#define LCD_PAL245_B04_0_Pos                                  10                                                        /*!< LCD PAL245: B04_0 Position          */
#define LCD_PAL245_B04_0_Msk                                  (0x1fUL << LCD_PAL245_B04_0_Pos)                          /*!< LCD PAL245: B04_0 Mask              */
#define LCD_PAL245_I0_Pos                                     15                                                        /*!< LCD PAL245: I0 Position             */
#define LCD_PAL245_I0_Msk                                     (0x01UL << LCD_PAL245_I0_Pos)                             /*!< LCD PAL245: I0 Mask                 */
#define LCD_PAL245_R14_0_Pos                                  16                                                        /*!< LCD PAL245: R14_0 Position          */
#define LCD_PAL245_R14_0_Msk                                  (0x1fUL << LCD_PAL245_R14_0_Pos)                          /*!< LCD PAL245: R14_0 Mask              */
#define LCD_PAL245_G14_0_Pos                                  21                                                        /*!< LCD PAL245: G14_0 Position          */
#define LCD_PAL245_G14_0_Msk                                  (0x1fUL << LCD_PAL245_G14_0_Pos)                          /*!< LCD PAL245: G14_0 Mask              */
#define LCD_PAL245_B14_0_Pos                                  26                                                        /*!< LCD PAL245: B14_0 Position          */
#define LCD_PAL245_B14_0_Msk                                  (0x1fUL << LCD_PAL245_B14_0_Pos)                          /*!< LCD PAL245: B14_0 Mask              */
#define LCD_PAL245_I1_Pos                                     31                                                        /*!< LCD PAL245: I1 Position             */
#define LCD_PAL245_I1_Msk                                     (0x01UL << LCD_PAL245_I1_Pos)                             /*!< LCD PAL245: I1 Mask                 */

// ---------------------------------------  LCD_PAL246  -------------------------------------------
#define LCD_PAL246_R04_0_Pos                                  0                                                         /*!< LCD PAL246: R04_0 Position          */
#define LCD_PAL246_R04_0_Msk                                  (0x1fUL << LCD_PAL246_R04_0_Pos)                          /*!< LCD PAL246: R04_0 Mask              */
#define LCD_PAL246_G04_0_Pos                                  5                                                         /*!< LCD PAL246: G04_0 Position          */
#define LCD_PAL246_G04_0_Msk                                  (0x1fUL << LCD_PAL246_G04_0_Pos)                          /*!< LCD PAL246: G04_0 Mask              */
#define LCD_PAL246_B04_0_Pos                                  10                                                        /*!< LCD PAL246: B04_0 Position          */
#define LCD_PAL246_B04_0_Msk                                  (0x1fUL << LCD_PAL246_B04_0_Pos)                          /*!< LCD PAL246: B04_0 Mask              */
#define LCD_PAL246_I0_Pos                                     15                                                        /*!< LCD PAL246: I0 Position             */
#define LCD_PAL246_I0_Msk                                     (0x01UL << LCD_PAL246_I0_Pos)                             /*!< LCD PAL246: I0 Mask                 */
#define LCD_PAL246_R14_0_Pos                                  16                                                        /*!< LCD PAL246: R14_0 Position          */
#define LCD_PAL246_R14_0_Msk                                  (0x1fUL << LCD_PAL246_R14_0_Pos)                          /*!< LCD PAL246: R14_0 Mask              */
#define LCD_PAL246_G14_0_Pos                                  21                                                        /*!< LCD PAL246: G14_0 Position          */
#define LCD_PAL246_G14_0_Msk                                  (0x1fUL << LCD_PAL246_G14_0_Pos)                          /*!< LCD PAL246: G14_0 Mask              */
#define LCD_PAL246_B14_0_Pos                                  26                                                        /*!< LCD PAL246: B14_0 Position          */
#define LCD_PAL246_B14_0_Msk                                  (0x1fUL << LCD_PAL246_B14_0_Pos)                          /*!< LCD PAL246: B14_0 Mask              */
#define LCD_PAL246_I1_Pos                                     31                                                        /*!< LCD PAL246: I1 Position             */
#define LCD_PAL246_I1_Msk                                     (0x01UL << LCD_PAL246_I1_Pos)                             /*!< LCD PAL246: I1 Mask                 */

// ---------------------------------------  LCD_PAL247  -------------------------------------------
#define LCD_PAL247_R04_0_Pos                                  0                                                         /*!< LCD PAL247: R04_0 Position          */
#define LCD_PAL247_R04_0_Msk                                  (0x1fUL << LCD_PAL247_R04_0_Pos)                          /*!< LCD PAL247: R04_0 Mask              */
#define LCD_PAL247_G04_0_Pos                                  5                                                         /*!< LCD PAL247: G04_0 Position          */
#define LCD_PAL247_G04_0_Msk                                  (0x1fUL << LCD_PAL247_G04_0_Pos)                          /*!< LCD PAL247: G04_0 Mask              */
#define LCD_PAL247_B04_0_Pos                                  10                                                        /*!< LCD PAL247: B04_0 Position          */
#define LCD_PAL247_B04_0_Msk                                  (0x1fUL << LCD_PAL247_B04_0_Pos)                          /*!< LCD PAL247: B04_0 Mask              */
#define LCD_PAL247_I0_Pos                                     15                                                        /*!< LCD PAL247: I0 Position             */
#define LCD_PAL247_I0_Msk                                     (0x01UL << LCD_PAL247_I0_Pos)                             /*!< LCD PAL247: I0 Mask                 */
#define LCD_PAL247_R14_0_Pos                                  16                                                        /*!< LCD PAL247: R14_0 Position          */
#define LCD_PAL247_R14_0_Msk                                  (0x1fUL << LCD_PAL247_R14_0_Pos)                          /*!< LCD PAL247: R14_0 Mask              */
#define LCD_PAL247_G14_0_Pos                                  21                                                        /*!< LCD PAL247: G14_0 Position          */
#define LCD_PAL247_G14_0_Msk                                  (0x1fUL << LCD_PAL247_G14_0_Pos)                          /*!< LCD PAL247: G14_0 Mask              */
#define LCD_PAL247_B14_0_Pos                                  26                                                        /*!< LCD PAL247: B14_0 Position          */
#define LCD_PAL247_B14_0_Msk                                  (0x1fUL << LCD_PAL247_B14_0_Pos)                          /*!< LCD PAL247: B14_0 Mask              */
#define LCD_PAL247_I1_Pos                                     31                                                        /*!< LCD PAL247: I1 Position             */
#define LCD_PAL247_I1_Msk                                     (0x01UL << LCD_PAL247_I1_Pos)                             /*!< LCD PAL247: I1 Mask                 */

// ---------------------------------------  LCD_PAL248  -------------------------------------------
#define LCD_PAL248_R04_0_Pos                                  0                                                         /*!< LCD PAL248: R04_0 Position          */
#define LCD_PAL248_R04_0_Msk                                  (0x1fUL << LCD_PAL248_R04_0_Pos)                          /*!< LCD PAL248: R04_0 Mask              */
#define LCD_PAL248_G04_0_Pos                                  5                                                         /*!< LCD PAL248: G04_0 Position          */
#define LCD_PAL248_G04_0_Msk                                  (0x1fUL << LCD_PAL248_G04_0_Pos)                          /*!< LCD PAL248: G04_0 Mask              */
#define LCD_PAL248_B04_0_Pos                                  10                                                        /*!< LCD PAL248: B04_0 Position          */
#define LCD_PAL248_B04_0_Msk                                  (0x1fUL << LCD_PAL248_B04_0_Pos)                          /*!< LCD PAL248: B04_0 Mask              */
#define LCD_PAL248_I0_Pos                                     15                                                        /*!< LCD PAL248: I0 Position             */
#define LCD_PAL248_I0_Msk                                     (0x01UL << LCD_PAL248_I0_Pos)                             /*!< LCD PAL248: I0 Mask                 */
#define LCD_PAL248_R14_0_Pos                                  16                                                        /*!< LCD PAL248: R14_0 Position          */
#define LCD_PAL248_R14_0_Msk                                  (0x1fUL << LCD_PAL248_R14_0_Pos)                          /*!< LCD PAL248: R14_0 Mask              */
#define LCD_PAL248_G14_0_Pos                                  21                                                        /*!< LCD PAL248: G14_0 Position          */
#define LCD_PAL248_G14_0_Msk                                  (0x1fUL << LCD_PAL248_G14_0_Pos)                          /*!< LCD PAL248: G14_0 Mask              */
#define LCD_PAL248_B14_0_Pos                                  26                                                        /*!< LCD PAL248: B14_0 Position          */
#define LCD_PAL248_B14_0_Msk                                  (0x1fUL << LCD_PAL248_B14_0_Pos)                          /*!< LCD PAL248: B14_0 Mask              */
#define LCD_PAL248_I1_Pos                                     31                                                        /*!< LCD PAL248: I1 Position             */
#define LCD_PAL248_I1_Msk                                     (0x01UL << LCD_PAL248_I1_Pos)                             /*!< LCD PAL248: I1 Mask                 */

// ---------------------------------------  LCD_PAL249  -------------------------------------------
#define LCD_PAL249_R04_0_Pos                                  0                                                         /*!< LCD PAL249: R04_0 Position          */
#define LCD_PAL249_R04_0_Msk                                  (0x1fUL << LCD_PAL249_R04_0_Pos)                          /*!< LCD PAL249: R04_0 Mask              */
#define LCD_PAL249_G04_0_Pos                                  5                                                         /*!< LCD PAL249: G04_0 Position          */
#define LCD_PAL249_G04_0_Msk                                  (0x1fUL << LCD_PAL249_G04_0_Pos)                          /*!< LCD PAL249: G04_0 Mask              */
#define LCD_PAL249_B04_0_Pos                                  10                                                        /*!< LCD PAL249: B04_0 Position          */
#define LCD_PAL249_B04_0_Msk                                  (0x1fUL << LCD_PAL249_B04_0_Pos)                          /*!< LCD PAL249: B04_0 Mask              */
#define LCD_PAL249_I0_Pos                                     15                                                        /*!< LCD PAL249: I0 Position             */
#define LCD_PAL249_I0_Msk                                     (0x01UL << LCD_PAL249_I0_Pos)                             /*!< LCD PAL249: I0 Mask                 */
#define LCD_PAL249_R14_0_Pos                                  16                                                        /*!< LCD PAL249: R14_0 Position          */
#define LCD_PAL249_R14_0_Msk                                  (0x1fUL << LCD_PAL249_R14_0_Pos)                          /*!< LCD PAL249: R14_0 Mask              */
#define LCD_PAL249_G14_0_Pos                                  21                                                        /*!< LCD PAL249: G14_0 Position          */
#define LCD_PAL249_G14_0_Msk                                  (0x1fUL << LCD_PAL249_G14_0_Pos)                          /*!< LCD PAL249: G14_0 Mask              */
#define LCD_PAL249_B14_0_Pos                                  26                                                        /*!< LCD PAL249: B14_0 Position          */
#define LCD_PAL249_B14_0_Msk                                  (0x1fUL << LCD_PAL249_B14_0_Pos)                          /*!< LCD PAL249: B14_0 Mask              */
#define LCD_PAL249_I1_Pos                                     31                                                        /*!< LCD PAL249: I1 Position             */
#define LCD_PAL249_I1_Msk                                     (0x01UL << LCD_PAL249_I1_Pos)                             /*!< LCD PAL249: I1 Mask                 */

// ---------------------------------------  LCD_PAL250  -------------------------------------------
#define LCD_PAL250_R04_0_Pos                                  0                                                         /*!< LCD PAL250: R04_0 Position          */
#define LCD_PAL250_R04_0_Msk                                  (0x1fUL << LCD_PAL250_R04_0_Pos)                          /*!< LCD PAL250: R04_0 Mask              */
#define LCD_PAL250_G04_0_Pos                                  5                                                         /*!< LCD PAL250: G04_0 Position          */
#define LCD_PAL250_G04_0_Msk                                  (0x1fUL << LCD_PAL250_G04_0_Pos)                          /*!< LCD PAL250: G04_0 Mask              */
#define LCD_PAL250_B04_0_Pos                                  10                                                        /*!< LCD PAL250: B04_0 Position          */
#define LCD_PAL250_B04_0_Msk                                  (0x1fUL << LCD_PAL250_B04_0_Pos)                          /*!< LCD PAL250: B04_0 Mask              */
#define LCD_PAL250_I0_Pos                                     15                                                        /*!< LCD PAL250: I0 Position             */
#define LCD_PAL250_I0_Msk                                     (0x01UL << LCD_PAL250_I0_Pos)                             /*!< LCD PAL250: I0 Mask                 */
#define LCD_PAL250_R14_0_Pos                                  16                                                        /*!< LCD PAL250: R14_0 Position          */
#define LCD_PAL250_R14_0_Msk                                  (0x1fUL << LCD_PAL250_R14_0_Pos)                          /*!< LCD PAL250: R14_0 Mask              */
#define LCD_PAL250_G14_0_Pos                                  21                                                        /*!< LCD PAL250: G14_0 Position          */
#define LCD_PAL250_G14_0_Msk                                  (0x1fUL << LCD_PAL250_G14_0_Pos)                          /*!< LCD PAL250: G14_0 Mask              */
#define LCD_PAL250_B14_0_Pos                                  26                                                        /*!< LCD PAL250: B14_0 Position          */
#define LCD_PAL250_B14_0_Msk                                  (0x1fUL << LCD_PAL250_B14_0_Pos)                          /*!< LCD PAL250: B14_0 Mask              */
#define LCD_PAL250_I1_Pos                                     31                                                        /*!< LCD PAL250: I1 Position             */
#define LCD_PAL250_I1_Msk                                     (0x01UL << LCD_PAL250_I1_Pos)                             /*!< LCD PAL250: I1 Mask                 */

// ---------------------------------------  LCD_PAL251  -------------------------------------------
#define LCD_PAL251_R04_0_Pos                                  0                                                         /*!< LCD PAL251: R04_0 Position          */
#define LCD_PAL251_R04_0_Msk                                  (0x1fUL << LCD_PAL251_R04_0_Pos)                          /*!< LCD PAL251: R04_0 Mask              */
#define LCD_PAL251_G04_0_Pos                                  5                                                         /*!< LCD PAL251: G04_0 Position          */
#define LCD_PAL251_G04_0_Msk                                  (0x1fUL << LCD_PAL251_G04_0_Pos)                          /*!< LCD PAL251: G04_0 Mask              */
#define LCD_PAL251_B04_0_Pos                                  10                                                        /*!< LCD PAL251: B04_0 Position          */
#define LCD_PAL251_B04_0_Msk                                  (0x1fUL << LCD_PAL251_B04_0_Pos)                          /*!< LCD PAL251: B04_0 Mask              */
#define LCD_PAL251_I0_Pos                                     15                                                        /*!< LCD PAL251: I0 Position             */
#define LCD_PAL251_I0_Msk                                     (0x01UL << LCD_PAL251_I0_Pos)                             /*!< LCD PAL251: I0 Mask                 */
#define LCD_PAL251_R14_0_Pos                                  16                                                        /*!< LCD PAL251: R14_0 Position          */
#define LCD_PAL251_R14_0_Msk                                  (0x1fUL << LCD_PAL251_R14_0_Pos)                          /*!< LCD PAL251: R14_0 Mask              */
#define LCD_PAL251_G14_0_Pos                                  21                                                        /*!< LCD PAL251: G14_0 Position          */
#define LCD_PAL251_G14_0_Msk                                  (0x1fUL << LCD_PAL251_G14_0_Pos)                          /*!< LCD PAL251: G14_0 Mask              */
#define LCD_PAL251_B14_0_Pos                                  26                                                        /*!< LCD PAL251: B14_0 Position          */
#define LCD_PAL251_B14_0_Msk                                  (0x1fUL << LCD_PAL251_B14_0_Pos)                          /*!< LCD PAL251: B14_0 Mask              */
#define LCD_PAL251_I1_Pos                                     31                                                        /*!< LCD PAL251: I1 Position             */
#define LCD_PAL251_I1_Msk                                     (0x01UL << LCD_PAL251_I1_Pos)                             /*!< LCD PAL251: I1 Mask                 */

// ---------------------------------------  LCD_PAL252  -------------------------------------------
#define LCD_PAL252_R04_0_Pos                                  0                                                         /*!< LCD PAL252: R04_0 Position          */
#define LCD_PAL252_R04_0_Msk                                  (0x1fUL << LCD_PAL252_R04_0_Pos)                          /*!< LCD PAL252: R04_0 Mask              */
#define LCD_PAL252_G04_0_Pos                                  5                                                         /*!< LCD PAL252: G04_0 Position          */
#define LCD_PAL252_G04_0_Msk                                  (0x1fUL << LCD_PAL252_G04_0_Pos)                          /*!< LCD PAL252: G04_0 Mask              */
#define LCD_PAL252_B04_0_Pos                                  10                                                        /*!< LCD PAL252: B04_0 Position          */
#define LCD_PAL252_B04_0_Msk                                  (0x1fUL << LCD_PAL252_B04_0_Pos)                          /*!< LCD PAL252: B04_0 Mask              */
#define LCD_PAL252_I0_Pos                                     15                                                        /*!< LCD PAL252: I0 Position             */
#define LCD_PAL252_I0_Msk                                     (0x01UL << LCD_PAL252_I0_Pos)                             /*!< LCD PAL252: I0 Mask                 */
#define LCD_PAL252_R14_0_Pos                                  16                                                        /*!< LCD PAL252: R14_0 Position          */
#define LCD_PAL252_R14_0_Msk                                  (0x1fUL << LCD_PAL252_R14_0_Pos)                          /*!< LCD PAL252: R14_0 Mask              */
#define LCD_PAL252_G14_0_Pos                                  21                                                        /*!< LCD PAL252: G14_0 Position          */
#define LCD_PAL252_G14_0_Msk                                  (0x1fUL << LCD_PAL252_G14_0_Pos)                          /*!< LCD PAL252: G14_0 Mask              */
#define LCD_PAL252_B14_0_Pos                                  26                                                        /*!< LCD PAL252: B14_0 Position          */
#define LCD_PAL252_B14_0_Msk                                  (0x1fUL << LCD_PAL252_B14_0_Pos)                          /*!< LCD PAL252: B14_0 Mask              */
#define LCD_PAL252_I1_Pos                                     31                                                        /*!< LCD PAL252: I1 Position             */
#define LCD_PAL252_I1_Msk                                     (0x01UL << LCD_PAL252_I1_Pos)                             /*!< LCD PAL252: I1 Mask                 */

// ---------------------------------------  LCD_PAL253  -------------------------------------------
#define LCD_PAL253_R04_0_Pos                                  0                                                         /*!< LCD PAL253: R04_0 Position          */
#define LCD_PAL253_R04_0_Msk                                  (0x1fUL << LCD_PAL253_R04_0_Pos)                          /*!< LCD PAL253: R04_0 Mask              */
#define LCD_PAL253_G04_0_Pos                                  5                                                         /*!< LCD PAL253: G04_0 Position          */
#define LCD_PAL253_G04_0_Msk                                  (0x1fUL << LCD_PAL253_G04_0_Pos)                          /*!< LCD PAL253: G04_0 Mask              */
#define LCD_PAL253_B04_0_Pos                                  10                                                        /*!< LCD PAL253: B04_0 Position          */
#define LCD_PAL253_B04_0_Msk                                  (0x1fUL << LCD_PAL253_B04_0_Pos)                          /*!< LCD PAL253: B04_0 Mask              */
#define LCD_PAL253_I0_Pos                                     15                                                        /*!< LCD PAL253: I0 Position             */
#define LCD_PAL253_I0_Msk                                     (0x01UL << LCD_PAL253_I0_Pos)                             /*!< LCD PAL253: I0 Mask                 */
#define LCD_PAL253_R14_0_Pos                                  16                                                        /*!< LCD PAL253: R14_0 Position          */
#define LCD_PAL253_R14_0_Msk                                  (0x1fUL << LCD_PAL253_R14_0_Pos)                          /*!< LCD PAL253: R14_0 Mask              */
#define LCD_PAL253_G14_0_Pos                                  21                                                        /*!< LCD PAL253: G14_0 Position          */
#define LCD_PAL253_G14_0_Msk                                  (0x1fUL << LCD_PAL253_G14_0_Pos)                          /*!< LCD PAL253: G14_0 Mask              */
#define LCD_PAL253_B14_0_Pos                                  26                                                        /*!< LCD PAL253: B14_0 Position          */
#define LCD_PAL253_B14_0_Msk                                  (0x1fUL << LCD_PAL253_B14_0_Pos)                          /*!< LCD PAL253: B14_0 Mask              */
#define LCD_PAL253_I1_Pos                                     31                                                        /*!< LCD PAL253: I1 Position             */
#define LCD_PAL253_I1_Msk                                     (0x01UL << LCD_PAL253_I1_Pos)                             /*!< LCD PAL253: I1 Mask                 */

// ---------------------------------------  LCD_PAL254  -------------------------------------------
#define LCD_PAL254_R04_0_Pos                                  0                                                         /*!< LCD PAL254: R04_0 Position          */
#define LCD_PAL254_R04_0_Msk                                  (0x1fUL << LCD_PAL254_R04_0_Pos)                          /*!< LCD PAL254: R04_0 Mask              */
#define LCD_PAL254_G04_0_Pos                                  5                                                         /*!< LCD PAL254: G04_0 Position          */
#define LCD_PAL254_G04_0_Msk                                  (0x1fUL << LCD_PAL254_G04_0_Pos)                          /*!< LCD PAL254: G04_0 Mask              */
#define LCD_PAL254_B04_0_Pos                                  10                                                        /*!< LCD PAL254: B04_0 Position          */
#define LCD_PAL254_B04_0_Msk                                  (0x1fUL << LCD_PAL254_B04_0_Pos)                          /*!< LCD PAL254: B04_0 Mask              */
#define LCD_PAL254_I0_Pos                                     15                                                        /*!< LCD PAL254: I0 Position             */
#define LCD_PAL254_I0_Msk                                     (0x01UL << LCD_PAL254_I0_Pos)                             /*!< LCD PAL254: I0 Mask                 */
#define LCD_PAL254_R14_0_Pos                                  16                                                        /*!< LCD PAL254: R14_0 Position          */
#define LCD_PAL254_R14_0_Msk                                  (0x1fUL << LCD_PAL254_R14_0_Pos)                          /*!< LCD PAL254: R14_0 Mask              */
#define LCD_PAL254_G14_0_Pos                                  21                                                        /*!< LCD PAL254: G14_0 Position          */
#define LCD_PAL254_G14_0_Msk                                  (0x1fUL << LCD_PAL254_G14_0_Pos)                          /*!< LCD PAL254: G14_0 Mask              */
#define LCD_PAL254_B14_0_Pos                                  26                                                        /*!< LCD PAL254: B14_0 Position          */
#define LCD_PAL254_B14_0_Msk                                  (0x1fUL << LCD_PAL254_B14_0_Pos)                          /*!< LCD PAL254: B14_0 Mask              */
#define LCD_PAL254_I1_Pos                                     31                                                        /*!< LCD PAL254: I1 Position             */
#define LCD_PAL254_I1_Msk                                     (0x01UL << LCD_PAL254_I1_Pos)                             /*!< LCD PAL254: I1 Mask                 */

// ---------------------------------------  LCD_PAL255  -------------------------------------------
#define LCD_PAL255_R04_0_Pos                                  0                                                         /*!< LCD PAL255: R04_0 Position          */
#define LCD_PAL255_R04_0_Msk                                  (0x1fUL << LCD_PAL255_R04_0_Pos)                          /*!< LCD PAL255: R04_0 Mask              */
#define LCD_PAL255_G04_0_Pos                                  5                                                         /*!< LCD PAL255: G04_0 Position          */
#define LCD_PAL255_G04_0_Msk                                  (0x1fUL << LCD_PAL255_G04_0_Pos)                          /*!< LCD PAL255: G04_0 Mask              */
#define LCD_PAL255_B04_0_Pos                                  10                                                        /*!< LCD PAL255: B04_0 Position          */
#define LCD_PAL255_B04_0_Msk                                  (0x1fUL << LCD_PAL255_B04_0_Pos)                          /*!< LCD PAL255: B04_0 Mask              */
#define LCD_PAL255_I0_Pos                                     15                                                        /*!< LCD PAL255: I0 Position             */
#define LCD_PAL255_I0_Msk                                     (0x01UL << LCD_PAL255_I0_Pos)                             /*!< LCD PAL255: I0 Mask                 */
#define LCD_PAL255_R14_0_Pos                                  16                                                        /*!< LCD PAL255: R14_0 Position          */
#define LCD_PAL255_R14_0_Msk                                  (0x1fUL << LCD_PAL255_R14_0_Pos)                          /*!< LCD PAL255: R14_0 Mask              */
#define LCD_PAL255_G14_0_Pos                                  21                                                        /*!< LCD PAL255: G14_0 Position          */
#define LCD_PAL255_G14_0_Msk                                  (0x1fUL << LCD_PAL255_G14_0_Pos)                          /*!< LCD PAL255: G14_0 Mask              */
#define LCD_PAL255_B14_0_Pos                                  26                                                        /*!< LCD PAL255: B14_0 Position          */
#define LCD_PAL255_B14_0_Msk                                  (0x1fUL << LCD_PAL255_B14_0_Pos)                          /*!< LCD PAL255: B14_0 Mask              */
#define LCD_PAL255_I1_Pos                                     31                                                        /*!< LCD PAL255: I1 Position             */
#define LCD_PAL255_I1_Msk                                     (0x01UL << LCD_PAL255_I1_Pos)                             /*!< LCD PAL255: I1 Mask                 */

// --------------------------------------  LCD_CRSR_IMG0  -----------------------------------------
#define LCD_CRSR_IMG0_CRSR_IMG_Pos                            0                                                         /*!< LCD CRSR_IMG0: CRSR_IMG Position    */
#define LCD_CRSR_IMG0_CRSR_IMG_Msk                            (0xffffffffUL << LCD_CRSR_IMG0_CRSR_IMG_Pos)              /*!< LCD CRSR_IMG0: CRSR_IMG Mask        */

// --------------------------------------  LCD_CRSR_IMG1  -----------------------------------------
#define LCD_CRSR_IMG1_CRSR_IMG_Pos                            0                                                         /*!< LCD CRSR_IMG1: CRSR_IMG Position    */
#define LCD_CRSR_IMG1_CRSR_IMG_Msk                            (0xffffffffUL << LCD_CRSR_IMG1_CRSR_IMG_Pos)              /*!< LCD CRSR_IMG1: CRSR_IMG Mask        */

// --------------------------------------  LCD_CRSR_IMG2  -----------------------------------------
#define LCD_CRSR_IMG2_CRSR_IMG_Pos                            0                                                         /*!< LCD CRSR_IMG2: CRSR_IMG Position    */
#define LCD_CRSR_IMG2_CRSR_IMG_Msk                            (0xffffffffUL << LCD_CRSR_IMG2_CRSR_IMG_Pos)              /*!< LCD CRSR_IMG2: CRSR_IMG Mask        */

// --------------------------------------  LCD_CRSR_IMG3  -----------------------------------------
#define LCD_CRSR_IMG3_CRSR_IMG_Pos                            0                                                         /*!< LCD CRSR_IMG3: CRSR_IMG Position    */
#define LCD_CRSR_IMG3_CRSR_IMG_Msk                            (0xffffffffUL << LCD_CRSR_IMG3_CRSR_IMG_Pos)              /*!< LCD CRSR_IMG3: CRSR_IMG Mask        */

// --------------------------------------  LCD_CRSR_IMG4  -----------------------------------------
#define LCD_CRSR_IMG4_CRSR_IMG_Pos                            0                                                         /*!< LCD CRSR_IMG4: CRSR_IMG Position    */
#define LCD_CRSR_IMG4_CRSR_IMG_Msk                            (0xffffffffUL << LCD_CRSR_IMG4_CRSR_IMG_Pos)              /*!< LCD CRSR_IMG4: CRSR_IMG Mask        */

// --------------------------------------  LCD_CRSR_IMG5  -----------------------------------------
#define LCD_CRSR_IMG5_CRSR_IMG_Pos                            0                                                         /*!< LCD CRSR_IMG5: CRSR_IMG Position    */
#define LCD_CRSR_IMG5_CRSR_IMG_Msk                            (0xffffffffUL << LCD_CRSR_IMG5_CRSR_IMG_Pos)              /*!< LCD CRSR_IMG5: CRSR_IMG Mask        */

// --------------------------------------  LCD_CRSR_IMG6  -----------------------------------------
#define LCD_CRSR_IMG6_CRSR_IMG_Pos                            0                                                         /*!< LCD CRSR_IMG6: CRSR_IMG Position    */
#define LCD_CRSR_IMG6_CRSR_IMG_Msk                            (0xffffffffUL << LCD_CRSR_IMG6_CRSR_IMG_Pos)              /*!< LCD CRSR_IMG6: CRSR_IMG Mask        */

// --------------------------------------  LCD_CRSR_IMG7  -----------------------------------------
#define LCD_CRSR_IMG7_CRSR_IMG_Pos                            0                                                         /*!< LCD CRSR_IMG7: CRSR_IMG Position    */
#define LCD_CRSR_IMG7_CRSR_IMG_Msk                            (0xffffffffUL << LCD_CRSR_IMG7_CRSR_IMG_Pos)              /*!< LCD CRSR_IMG7: CRSR_IMG Mask        */

// --------------------------------------  LCD_CRSR_IMG8  -----------------------------------------
#define LCD_CRSR_IMG8_CRSR_IMG_Pos                            0                                                         /*!< LCD CRSR_IMG8: CRSR_IMG Position    */
#define LCD_CRSR_IMG8_CRSR_IMG_Msk                            (0xffffffffUL << LCD_CRSR_IMG8_CRSR_IMG_Pos)              /*!< LCD CRSR_IMG8: CRSR_IMG Mask        */

// --------------------------------------  LCD_CRSR_IMG9  -----------------------------------------
#define LCD_CRSR_IMG9_CRSR_IMG_Pos                            0                                                         /*!< LCD CRSR_IMG9: CRSR_IMG Position    */
#define LCD_CRSR_IMG9_CRSR_IMG_Msk                            (0xffffffffUL << LCD_CRSR_IMG9_CRSR_IMG_Pos)              /*!< LCD CRSR_IMG9: CRSR_IMG Mask        */

// -------------------------------------  LCD_CRSR_IMG10  -----------------------------------------
#define LCD_CRSR_IMG10_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG10: CRSR_IMG Position   */
#define LCD_CRSR_IMG10_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG10_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG10: CRSR_IMG Mask       */

// -------------------------------------  LCD_CRSR_IMG11  -----------------------------------------
#define LCD_CRSR_IMG11_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG11: CRSR_IMG Position   */
#define LCD_CRSR_IMG11_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG11_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG11: CRSR_IMG Mask       */

// -------------------------------------  LCD_CRSR_IMG12  -----------------------------------------
#define LCD_CRSR_IMG12_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG12: CRSR_IMG Position   */
#define LCD_CRSR_IMG12_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG12_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG12: CRSR_IMG Mask       */

// -------------------------------------  LCD_CRSR_IMG13  -----------------------------------------
#define LCD_CRSR_IMG13_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG13: CRSR_IMG Position   */
#define LCD_CRSR_IMG13_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG13_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG13: CRSR_IMG Mask       */

// -------------------------------------  LCD_CRSR_IMG14  -----------------------------------------
#define LCD_CRSR_IMG14_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG14: CRSR_IMG Position   */
#define LCD_CRSR_IMG14_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG14_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG14: CRSR_IMG Mask       */

// -------------------------------------  LCD_CRSR_IMG15  -----------------------------------------
#define LCD_CRSR_IMG15_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG15: CRSR_IMG Position   */
#define LCD_CRSR_IMG15_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG15_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG15: CRSR_IMG Mask       */

// -------------------------------------  LCD_CRSR_IMG16  -----------------------------------------
#define LCD_CRSR_IMG16_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG16: CRSR_IMG Position   */
#define LCD_CRSR_IMG16_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG16_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG16: CRSR_IMG Mask       */

// -------------------------------------  LCD_CRSR_IMG17  -----------------------------------------
#define LCD_CRSR_IMG17_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG17: CRSR_IMG Position   */
#define LCD_CRSR_IMG17_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG17_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG17: CRSR_IMG Mask       */

// -------------------------------------  LCD_CRSR_IMG18  -----------------------------------------
#define LCD_CRSR_IMG18_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG18: CRSR_IMG Position   */
#define LCD_CRSR_IMG18_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG18_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG18: CRSR_IMG Mask       */

// -------------------------------------  LCD_CRSR_IMG19  -----------------------------------------
#define LCD_CRSR_IMG19_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG19: CRSR_IMG Position   */
#define LCD_CRSR_IMG19_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG19_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG19: CRSR_IMG Mask       */

// -------------------------------------  LCD_CRSR_IMG20  -----------------------------------------
#define LCD_CRSR_IMG20_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG20: CRSR_IMG Position   */
#define LCD_CRSR_IMG20_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG20_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG20: CRSR_IMG Mask       */

// -------------------------------------  LCD_CRSR_IMG21  -----------------------------------------
#define LCD_CRSR_IMG21_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG21: CRSR_IMG Position   */
#define LCD_CRSR_IMG21_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG21_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG21: CRSR_IMG Mask       */

// -------------------------------------  LCD_CRSR_IMG22  -----------------------------------------
#define LCD_CRSR_IMG22_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG22: CRSR_IMG Position   */
#define LCD_CRSR_IMG22_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG22_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG22: CRSR_IMG Mask       */

// -------------------------------------  LCD_CRSR_IMG23  -----------------------------------------
#define LCD_CRSR_IMG23_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG23: CRSR_IMG Position   */
#define LCD_CRSR_IMG23_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG23_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG23: CRSR_IMG Mask       */

// -------------------------------------  LCD_CRSR_IMG24  -----------------------------------------
#define LCD_CRSR_IMG24_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG24: CRSR_IMG Position   */
#define LCD_CRSR_IMG24_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG24_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG24: CRSR_IMG Mask       */

// -------------------------------------  LCD_CRSR_IMG25  -----------------------------------------
#define LCD_CRSR_IMG25_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG25: CRSR_IMG Position   */
#define LCD_CRSR_IMG25_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG25_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG25: CRSR_IMG Mask       */

// -------------------------------------  LCD_CRSR_IMG26  -----------------------------------------
#define LCD_CRSR_IMG26_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG26: CRSR_IMG Position   */
#define LCD_CRSR_IMG26_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG26_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG26: CRSR_IMG Mask       */

// -------------------------------------  LCD_CRSR_IMG27  -----------------------------------------
#define LCD_CRSR_IMG27_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG27: CRSR_IMG Position   */
#define LCD_CRSR_IMG27_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG27_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG27: CRSR_IMG Mask       */

// -------------------------------------  LCD_CRSR_IMG28  -----------------------------------------
#define LCD_CRSR_IMG28_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG28: CRSR_IMG Position   */
#define LCD_CRSR_IMG28_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG28_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG28: CRSR_IMG Mask       */

// -------------------------------------  LCD_CRSR_IMG29  -----------------------------------------
#define LCD_CRSR_IMG29_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG29: CRSR_IMG Position   */
#define LCD_CRSR_IMG29_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG29_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG29: CRSR_IMG Mask       */

// -------------------------------------  LCD_CRSR_IMG30  -----------------------------------------
#define LCD_CRSR_IMG30_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG30: CRSR_IMG Position   */
#define LCD_CRSR_IMG30_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG30_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG30: CRSR_IMG Mask       */

// -------------------------------------  LCD_CRSR_IMG31  -----------------------------------------
#define LCD_CRSR_IMG31_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG31: CRSR_IMG Position   */
#define LCD_CRSR_IMG31_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG31_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG31: CRSR_IMG Mask       */

// -------------------------------------  LCD_CRSR_IMG32  -----------------------------------------
#define LCD_CRSR_IMG32_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG32: CRSR_IMG Position   */
#define LCD_CRSR_IMG32_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG32_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG32: CRSR_IMG Mask       */

// -------------------------------------  LCD_CRSR_IMG33  -----------------------------------------
#define LCD_CRSR_IMG33_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG33: CRSR_IMG Position   */
#define LCD_CRSR_IMG33_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG33_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG33: CRSR_IMG Mask       */

// -------------------------------------  LCD_CRSR_IMG34  -----------------------------------------
#define LCD_CRSR_IMG34_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG34: CRSR_IMG Position   */
#define LCD_CRSR_IMG34_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG34_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG34: CRSR_IMG Mask       */

// -------------------------------------  LCD_CRSR_IMG35  -----------------------------------------
#define LCD_CRSR_IMG35_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG35: CRSR_IMG Position   */
#define LCD_CRSR_IMG35_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG35_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG35: CRSR_IMG Mask       */

// -------------------------------------  LCD_CRSR_IMG36  -----------------------------------------
#define LCD_CRSR_IMG36_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG36: CRSR_IMG Position   */
#define LCD_CRSR_IMG36_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG36_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG36: CRSR_IMG Mask       */

// -------------------------------------  LCD_CRSR_IMG37  -----------------------------------------
#define LCD_CRSR_IMG37_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG37: CRSR_IMG Position   */
#define LCD_CRSR_IMG37_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG37_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG37: CRSR_IMG Mask       */

// -------------------------------------  LCD_CRSR_IMG38  -----------------------------------------
#define LCD_CRSR_IMG38_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG38: CRSR_IMG Position   */
#define LCD_CRSR_IMG38_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG38_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG38: CRSR_IMG Mask       */

// -------------------------------------  LCD_CRSR_IMG39  -----------------------------------------
#define LCD_CRSR_IMG39_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG39: CRSR_IMG Position   */
#define LCD_CRSR_IMG39_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG39_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG39: CRSR_IMG Mask       */

// -------------------------------------  LCD_CRSR_IMG40  -----------------------------------------
#define LCD_CRSR_IMG40_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG40: CRSR_IMG Position   */
#define LCD_CRSR_IMG40_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG40_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG40: CRSR_IMG Mask       */

// -------------------------------------  LCD_CRSR_IMG41  -----------------------------------------
#define LCD_CRSR_IMG41_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG41: CRSR_IMG Position   */
#define LCD_CRSR_IMG41_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG41_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG41: CRSR_IMG Mask       */

// -------------------------------------  LCD_CRSR_IMG42  -----------------------------------------
#define LCD_CRSR_IMG42_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG42: CRSR_IMG Position   */
#define LCD_CRSR_IMG42_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG42_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG42: CRSR_IMG Mask       */

// -------------------------------------  LCD_CRSR_IMG43  -----------------------------------------
#define LCD_CRSR_IMG43_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG43: CRSR_IMG Position   */
#define LCD_CRSR_IMG43_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG43_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG43: CRSR_IMG Mask       */

// -------------------------------------  LCD_CRSR_IMG44  -----------------------------------------
#define LCD_CRSR_IMG44_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG44: CRSR_IMG Position   */
#define LCD_CRSR_IMG44_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG44_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG44: CRSR_IMG Mask       */

// -------------------------------------  LCD_CRSR_IMG45  -----------------------------------------
#define LCD_CRSR_IMG45_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG45: CRSR_IMG Position   */
#define LCD_CRSR_IMG45_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG45_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG45: CRSR_IMG Mask       */

// -------------------------------------  LCD_CRSR_IMG46  -----------------------------------------
#define LCD_CRSR_IMG46_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG46: CRSR_IMG Position   */
#define LCD_CRSR_IMG46_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG46_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG46: CRSR_IMG Mask       */

// -------------------------------------  LCD_CRSR_IMG47  -----------------------------------------
#define LCD_CRSR_IMG47_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG47: CRSR_IMG Position   */
#define LCD_CRSR_IMG47_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG47_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG47: CRSR_IMG Mask       */

// -------------------------------------  LCD_CRSR_IMG48  -----------------------------------------
#define LCD_CRSR_IMG48_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG48: CRSR_IMG Position   */
#define LCD_CRSR_IMG48_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG48_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG48: CRSR_IMG Mask       */

// -------------------------------------  LCD_CRSR_IMG49  -----------------------------------------
#define LCD_CRSR_IMG49_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG49: CRSR_IMG Position   */
#define LCD_CRSR_IMG49_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG49_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG49: CRSR_IMG Mask       */

// -------------------------------------  LCD_CRSR_IMG50  -----------------------------------------
#define LCD_CRSR_IMG50_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG50: CRSR_IMG Position   */
#define LCD_CRSR_IMG50_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG50_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG50: CRSR_IMG Mask       */

// -------------------------------------  LCD_CRSR_IMG51  -----------------------------------------
#define LCD_CRSR_IMG51_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG51: CRSR_IMG Position   */
#define LCD_CRSR_IMG51_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG51_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG51: CRSR_IMG Mask       */

// -------------------------------------  LCD_CRSR_IMG52  -----------------------------------------
#define LCD_CRSR_IMG52_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG52: CRSR_IMG Position   */
#define LCD_CRSR_IMG52_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG52_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG52: CRSR_IMG Mask       */

// -------------------------------------  LCD_CRSR_IMG53  -----------------------------------------
#define LCD_CRSR_IMG53_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG53: CRSR_IMG Position   */
#define LCD_CRSR_IMG53_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG53_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG53: CRSR_IMG Mask       */

// -------------------------------------  LCD_CRSR_IMG54  -----------------------------------------
#define LCD_CRSR_IMG54_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG54: CRSR_IMG Position   */
#define LCD_CRSR_IMG54_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG54_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG54: CRSR_IMG Mask       */

// -------------------------------------  LCD_CRSR_IMG55  -----------------------------------------
#define LCD_CRSR_IMG55_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG55: CRSR_IMG Position   */
#define LCD_CRSR_IMG55_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG55_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG55: CRSR_IMG Mask       */

// -------------------------------------  LCD_CRSR_IMG56  -----------------------------------------
#define LCD_CRSR_IMG56_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG56: CRSR_IMG Position   */
#define LCD_CRSR_IMG56_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG56_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG56: CRSR_IMG Mask       */

// -------------------------------------  LCD_CRSR_IMG57  -----------------------------------------
#define LCD_CRSR_IMG57_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG57: CRSR_IMG Position   */
#define LCD_CRSR_IMG57_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG57_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG57: CRSR_IMG Mask       */

// -------------------------------------  LCD_CRSR_IMG58  -----------------------------------------
#define LCD_CRSR_IMG58_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG58: CRSR_IMG Position   */
#define LCD_CRSR_IMG58_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG58_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG58: CRSR_IMG Mask       */

// -------------------------------------  LCD_CRSR_IMG59  -----------------------------------------
#define LCD_CRSR_IMG59_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG59: CRSR_IMG Position   */
#define LCD_CRSR_IMG59_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG59_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG59: CRSR_IMG Mask       */

// -------------------------------------  LCD_CRSR_IMG60  -----------------------------------------
#define LCD_CRSR_IMG60_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG60: CRSR_IMG Position   */
#define LCD_CRSR_IMG60_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG60_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG60: CRSR_IMG Mask       */

// -------------------------------------  LCD_CRSR_IMG61  -----------------------------------------
#define LCD_CRSR_IMG61_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG61: CRSR_IMG Position   */
#define LCD_CRSR_IMG61_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG61_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG61: CRSR_IMG Mask       */

// -------------------------------------  LCD_CRSR_IMG62  -----------------------------------------
#define LCD_CRSR_IMG62_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG62: CRSR_IMG Position   */
#define LCD_CRSR_IMG62_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG62_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG62: CRSR_IMG Mask       */

// -------------------------------------  LCD_CRSR_IMG63  -----------------------------------------
#define LCD_CRSR_IMG63_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG63: CRSR_IMG Position   */
#define LCD_CRSR_IMG63_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG63_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG63: CRSR_IMG Mask       */

// -------------------------------------  LCD_CRSR_IMG64  -----------------------------------------
#define LCD_CRSR_IMG64_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG64: CRSR_IMG Position   */
#define LCD_CRSR_IMG64_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG64_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG64: CRSR_IMG Mask       */

// -------------------------------------  LCD_CRSR_IMG65  -----------------------------------------
#define LCD_CRSR_IMG65_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG65: CRSR_IMG Position   */
#define LCD_CRSR_IMG65_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG65_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG65: CRSR_IMG Mask       */

// -------------------------------------  LCD_CRSR_IMG66  -----------------------------------------
#define LCD_CRSR_IMG66_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG66: CRSR_IMG Position   */
#define LCD_CRSR_IMG66_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG66_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG66: CRSR_IMG Mask       */

// -------------------------------------  LCD_CRSR_IMG67  -----------------------------------------
#define LCD_CRSR_IMG67_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG67: CRSR_IMG Position   */
#define LCD_CRSR_IMG67_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG67_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG67: CRSR_IMG Mask       */

// -------------------------------------  LCD_CRSR_IMG68  -----------------------------------------
#define LCD_CRSR_IMG68_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG68: CRSR_IMG Position   */
#define LCD_CRSR_IMG68_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG68_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG68: CRSR_IMG Mask       */

// -------------------------------------  LCD_CRSR_IMG69  -----------------------------------------
#define LCD_CRSR_IMG69_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG69: CRSR_IMG Position   */
#define LCD_CRSR_IMG69_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG69_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG69: CRSR_IMG Mask       */

// -------------------------------------  LCD_CRSR_IMG70  -----------------------------------------
#define LCD_CRSR_IMG70_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG70: CRSR_IMG Position   */
#define LCD_CRSR_IMG70_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG70_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG70: CRSR_IMG Mask       */

// -------------------------------------  LCD_CRSR_IMG71  -----------------------------------------
#define LCD_CRSR_IMG71_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG71: CRSR_IMG Position   */
#define LCD_CRSR_IMG71_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG71_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG71: CRSR_IMG Mask       */

// -------------------------------------  LCD_CRSR_IMG72  -----------------------------------------
#define LCD_CRSR_IMG72_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG72: CRSR_IMG Position   */
#define LCD_CRSR_IMG72_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG72_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG72: CRSR_IMG Mask       */

// -------------------------------------  LCD_CRSR_IMG73  -----------------------------------------
#define LCD_CRSR_IMG73_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG73: CRSR_IMG Position   */
#define LCD_CRSR_IMG73_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG73_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG73: CRSR_IMG Mask       */

// -------------------------------------  LCD_CRSR_IMG74  -----------------------------------------
#define LCD_CRSR_IMG74_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG74: CRSR_IMG Position   */
#define LCD_CRSR_IMG74_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG74_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG74: CRSR_IMG Mask       */

// -------------------------------------  LCD_CRSR_IMG75  -----------------------------------------
#define LCD_CRSR_IMG75_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG75: CRSR_IMG Position   */
#define LCD_CRSR_IMG75_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG75_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG75: CRSR_IMG Mask       */

// -------------------------------------  LCD_CRSR_IMG76  -----------------------------------------
#define LCD_CRSR_IMG76_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG76: CRSR_IMG Position   */
#define LCD_CRSR_IMG76_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG76_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG76: CRSR_IMG Mask       */

// -------------------------------------  LCD_CRSR_IMG77  -----------------------------------------
#define LCD_CRSR_IMG77_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG77: CRSR_IMG Position   */
#define LCD_CRSR_IMG77_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG77_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG77: CRSR_IMG Mask       */

// -------------------------------------  LCD_CRSR_IMG78  -----------------------------------------
#define LCD_CRSR_IMG78_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG78: CRSR_IMG Position   */
#define LCD_CRSR_IMG78_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG78_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG78: CRSR_IMG Mask       */

// -------------------------------------  LCD_CRSR_IMG79  -----------------------------------------
#define LCD_CRSR_IMG79_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG79: CRSR_IMG Position   */
#define LCD_CRSR_IMG79_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG79_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG79: CRSR_IMG Mask       */

// -------------------------------------  LCD_CRSR_IMG80  -----------------------------------------
#define LCD_CRSR_IMG80_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG80: CRSR_IMG Position   */
#define LCD_CRSR_IMG80_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG80_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG80: CRSR_IMG Mask       */

// -------------------------------------  LCD_CRSR_IMG81  -----------------------------------------
#define LCD_CRSR_IMG81_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG81: CRSR_IMG Position   */
#define LCD_CRSR_IMG81_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG81_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG81: CRSR_IMG Mask       */

// -------------------------------------  LCD_CRSR_IMG82  -----------------------------------------
#define LCD_CRSR_IMG82_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG82: CRSR_IMG Position   */
#define LCD_CRSR_IMG82_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG82_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG82: CRSR_IMG Mask       */

// -------------------------------------  LCD_CRSR_IMG83  -----------------------------------------
#define LCD_CRSR_IMG83_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG83: CRSR_IMG Position   */
#define LCD_CRSR_IMG83_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG83_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG83: CRSR_IMG Mask       */

// -------------------------------------  LCD_CRSR_IMG84  -----------------------------------------
#define LCD_CRSR_IMG84_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG84: CRSR_IMG Position   */
#define LCD_CRSR_IMG84_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG84_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG84: CRSR_IMG Mask       */

// -------------------------------------  LCD_CRSR_IMG85  -----------------------------------------
#define LCD_CRSR_IMG85_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG85: CRSR_IMG Position   */
#define LCD_CRSR_IMG85_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG85_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG85: CRSR_IMG Mask       */

// -------------------------------------  LCD_CRSR_IMG86  -----------------------------------------
#define LCD_CRSR_IMG86_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG86: CRSR_IMG Position   */
#define LCD_CRSR_IMG86_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG86_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG86: CRSR_IMG Mask       */

// -------------------------------------  LCD_CRSR_IMG87  -----------------------------------------
#define LCD_CRSR_IMG87_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG87: CRSR_IMG Position   */
#define LCD_CRSR_IMG87_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG87_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG87: CRSR_IMG Mask       */

// -------------------------------------  LCD_CRSR_IMG88  -----------------------------------------
#define LCD_CRSR_IMG88_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG88: CRSR_IMG Position   */
#define LCD_CRSR_IMG88_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG88_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG88: CRSR_IMG Mask       */

// -------------------------------------  LCD_CRSR_IMG89  -----------------------------------------
#define LCD_CRSR_IMG89_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG89: CRSR_IMG Position   */
#define LCD_CRSR_IMG89_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG89_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG89: CRSR_IMG Mask       */

// -------------------------------------  LCD_CRSR_IMG90  -----------------------------------------
#define LCD_CRSR_IMG90_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG90: CRSR_IMG Position   */
#define LCD_CRSR_IMG90_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG90_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG90: CRSR_IMG Mask       */

// -------------------------------------  LCD_CRSR_IMG91  -----------------------------------------
#define LCD_CRSR_IMG91_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG91: CRSR_IMG Position   */
#define LCD_CRSR_IMG91_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG91_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG91: CRSR_IMG Mask       */

// -------------------------------------  LCD_CRSR_IMG92  -----------------------------------------
#define LCD_CRSR_IMG92_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG92: CRSR_IMG Position   */
#define LCD_CRSR_IMG92_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG92_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG92: CRSR_IMG Mask       */

// -------------------------------------  LCD_CRSR_IMG93  -----------------------------------------
#define LCD_CRSR_IMG93_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG93: CRSR_IMG Position   */
#define LCD_CRSR_IMG93_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG93_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG93: CRSR_IMG Mask       */

// -------------------------------------  LCD_CRSR_IMG94  -----------------------------------------
#define LCD_CRSR_IMG94_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG94: CRSR_IMG Position   */
#define LCD_CRSR_IMG94_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG94_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG94: CRSR_IMG Mask       */

// -------------------------------------  LCD_CRSR_IMG95  -----------------------------------------
#define LCD_CRSR_IMG95_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG95: CRSR_IMG Position   */
#define LCD_CRSR_IMG95_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG95_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG95: CRSR_IMG Mask       */

// -------------------------------------  LCD_CRSR_IMG96  -----------------------------------------
#define LCD_CRSR_IMG96_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG96: CRSR_IMG Position   */
#define LCD_CRSR_IMG96_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG96_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG96: CRSR_IMG Mask       */

// -------------------------------------  LCD_CRSR_IMG97  -----------------------------------------
#define LCD_CRSR_IMG97_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG97: CRSR_IMG Position   */
#define LCD_CRSR_IMG97_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG97_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG97: CRSR_IMG Mask       */

// -------------------------------------  LCD_CRSR_IMG98  -----------------------------------------
#define LCD_CRSR_IMG98_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG98: CRSR_IMG Position   */
#define LCD_CRSR_IMG98_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG98_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG98: CRSR_IMG Mask       */

// -------------------------------------  LCD_CRSR_IMG99  -----------------------------------------
#define LCD_CRSR_IMG99_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG99: CRSR_IMG Position   */
#define LCD_CRSR_IMG99_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG99_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG99: CRSR_IMG Mask       */

// -------------------------------------  LCD_CRSR_IMG100  ----------------------------------------
#define LCD_CRSR_IMG100_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG100: CRSR_IMG Position  */
#define LCD_CRSR_IMG100_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG100_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG100: CRSR_IMG Mask      */

// -------------------------------------  LCD_CRSR_IMG101  ----------------------------------------
#define LCD_CRSR_IMG101_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG101: CRSR_IMG Position  */
#define LCD_CRSR_IMG101_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG101_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG101: CRSR_IMG Mask      */

// -------------------------------------  LCD_CRSR_IMG102  ----------------------------------------
#define LCD_CRSR_IMG102_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG102: CRSR_IMG Position  */
#define LCD_CRSR_IMG102_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG102_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG102: CRSR_IMG Mask      */

// -------------------------------------  LCD_CRSR_IMG103  ----------------------------------------
#define LCD_CRSR_IMG103_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG103: CRSR_IMG Position  */
#define LCD_CRSR_IMG103_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG103_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG103: CRSR_IMG Mask      */

// -------------------------------------  LCD_CRSR_IMG104  ----------------------------------------
#define LCD_CRSR_IMG104_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG104: CRSR_IMG Position  */
#define LCD_CRSR_IMG104_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG104_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG104: CRSR_IMG Mask      */

// -------------------------------------  LCD_CRSR_IMG105  ----------------------------------------
#define LCD_CRSR_IMG105_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG105: CRSR_IMG Position  */
#define LCD_CRSR_IMG105_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG105_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG105: CRSR_IMG Mask      */

// -------------------------------------  LCD_CRSR_IMG106  ----------------------------------------
#define LCD_CRSR_IMG106_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG106: CRSR_IMG Position  */
#define LCD_CRSR_IMG106_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG106_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG106: CRSR_IMG Mask      */

// -------------------------------------  LCD_CRSR_IMG107  ----------------------------------------
#define LCD_CRSR_IMG107_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG107: CRSR_IMG Position  */
#define LCD_CRSR_IMG107_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG107_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG107: CRSR_IMG Mask      */

// -------------------------------------  LCD_CRSR_IMG108  ----------------------------------------
#define LCD_CRSR_IMG108_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG108: CRSR_IMG Position  */
#define LCD_CRSR_IMG108_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG108_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG108: CRSR_IMG Mask      */

// -------------------------------------  LCD_CRSR_IMG109  ----------------------------------------
#define LCD_CRSR_IMG109_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG109: CRSR_IMG Position  */
#define LCD_CRSR_IMG109_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG109_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG109: CRSR_IMG Mask      */

// -------------------------------------  LCD_CRSR_IMG110  ----------------------------------------
#define LCD_CRSR_IMG110_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG110: CRSR_IMG Position  */
#define LCD_CRSR_IMG110_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG110_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG110: CRSR_IMG Mask      */

// -------------------------------------  LCD_CRSR_IMG111  ----------------------------------------
#define LCD_CRSR_IMG111_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG111: CRSR_IMG Position  */
#define LCD_CRSR_IMG111_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG111_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG111: CRSR_IMG Mask      */

// -------------------------------------  LCD_CRSR_IMG112  ----------------------------------------
#define LCD_CRSR_IMG112_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG112: CRSR_IMG Position  */
#define LCD_CRSR_IMG112_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG112_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG112: CRSR_IMG Mask      */

// -------------------------------------  LCD_CRSR_IMG113  ----------------------------------------
#define LCD_CRSR_IMG113_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG113: CRSR_IMG Position  */
#define LCD_CRSR_IMG113_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG113_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG113: CRSR_IMG Mask      */

// -------------------------------------  LCD_CRSR_IMG114  ----------------------------------------
#define LCD_CRSR_IMG114_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG114: CRSR_IMG Position  */
#define LCD_CRSR_IMG114_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG114_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG114: CRSR_IMG Mask      */

// -------------------------------------  LCD_CRSR_IMG115  ----------------------------------------
#define LCD_CRSR_IMG115_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG115: CRSR_IMG Position  */
#define LCD_CRSR_IMG115_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG115_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG115: CRSR_IMG Mask      */

// -------------------------------------  LCD_CRSR_IMG116  ----------------------------------------
#define LCD_CRSR_IMG116_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG116: CRSR_IMG Position  */
#define LCD_CRSR_IMG116_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG116_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG116: CRSR_IMG Mask      */

// -------------------------------------  LCD_CRSR_IMG117  ----------------------------------------
#define LCD_CRSR_IMG117_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG117: CRSR_IMG Position  */
#define LCD_CRSR_IMG117_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG117_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG117: CRSR_IMG Mask      */

// -------------------------------------  LCD_CRSR_IMG118  ----------------------------------------
#define LCD_CRSR_IMG118_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG118: CRSR_IMG Position  */
#define LCD_CRSR_IMG118_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG118_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG118: CRSR_IMG Mask      */

// -------------------------------------  LCD_CRSR_IMG119  ----------------------------------------
#define LCD_CRSR_IMG119_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG119: CRSR_IMG Position  */
#define LCD_CRSR_IMG119_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG119_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG119: CRSR_IMG Mask      */

// -------------------------------------  LCD_CRSR_IMG120  ----------------------------------------
#define LCD_CRSR_IMG120_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG120: CRSR_IMG Position  */
#define LCD_CRSR_IMG120_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG120_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG120: CRSR_IMG Mask      */

// -------------------------------------  LCD_CRSR_IMG121  ----------------------------------------
#define LCD_CRSR_IMG121_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG121: CRSR_IMG Position  */
#define LCD_CRSR_IMG121_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG121_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG121: CRSR_IMG Mask      */

// -------------------------------------  LCD_CRSR_IMG122  ----------------------------------------
#define LCD_CRSR_IMG122_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG122: CRSR_IMG Position  */
#define LCD_CRSR_IMG122_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG122_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG122: CRSR_IMG Mask      */

// -------------------------------------  LCD_CRSR_IMG123  ----------------------------------------
#define LCD_CRSR_IMG123_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG123: CRSR_IMG Position  */
#define LCD_CRSR_IMG123_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG123_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG123: CRSR_IMG Mask      */

// -------------------------------------  LCD_CRSR_IMG124  ----------------------------------------
#define LCD_CRSR_IMG124_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG124: CRSR_IMG Position  */
#define LCD_CRSR_IMG124_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG124_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG124: CRSR_IMG Mask      */

// -------------------------------------  LCD_CRSR_IMG125  ----------------------------------------
#define LCD_CRSR_IMG125_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG125: CRSR_IMG Position  */
#define LCD_CRSR_IMG125_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG125_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG125: CRSR_IMG Mask      */

// -------------------------------------  LCD_CRSR_IMG126  ----------------------------------------
#define LCD_CRSR_IMG126_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG126: CRSR_IMG Position  */
#define LCD_CRSR_IMG126_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG126_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG126: CRSR_IMG Mask      */

// -------------------------------------  LCD_CRSR_IMG127  ----------------------------------------
#define LCD_CRSR_IMG127_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG127: CRSR_IMG Position  */
#define LCD_CRSR_IMG127_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG127_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG127: CRSR_IMG Mask      */

// -------------------------------------  LCD_CRSR_IMG128  ----------------------------------------
#define LCD_CRSR_IMG128_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG128: CRSR_IMG Position  */
#define LCD_CRSR_IMG128_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG128_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG128: CRSR_IMG Mask      */

// -------------------------------------  LCD_CRSR_IMG129  ----------------------------------------
#define LCD_CRSR_IMG129_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG129: CRSR_IMG Position  */
#define LCD_CRSR_IMG129_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG129_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG129: CRSR_IMG Mask      */

// -------------------------------------  LCD_CRSR_IMG130  ----------------------------------------
#define LCD_CRSR_IMG130_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG130: CRSR_IMG Position  */
#define LCD_CRSR_IMG130_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG130_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG130: CRSR_IMG Mask      */

// -------------------------------------  LCD_CRSR_IMG131  ----------------------------------------
#define LCD_CRSR_IMG131_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG131: CRSR_IMG Position  */
#define LCD_CRSR_IMG131_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG131_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG131: CRSR_IMG Mask      */

// -------------------------------------  LCD_CRSR_IMG132  ----------------------------------------
#define LCD_CRSR_IMG132_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG132: CRSR_IMG Position  */
#define LCD_CRSR_IMG132_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG132_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG132: CRSR_IMG Mask      */

// -------------------------------------  LCD_CRSR_IMG133  ----------------------------------------
#define LCD_CRSR_IMG133_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG133: CRSR_IMG Position  */
#define LCD_CRSR_IMG133_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG133_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG133: CRSR_IMG Mask      */

// -------------------------------------  LCD_CRSR_IMG134  ----------------------------------------
#define LCD_CRSR_IMG134_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG134: CRSR_IMG Position  */
#define LCD_CRSR_IMG134_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG134_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG134: CRSR_IMG Mask      */

// -------------------------------------  LCD_CRSR_IMG135  ----------------------------------------
#define LCD_CRSR_IMG135_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG135: CRSR_IMG Position  */
#define LCD_CRSR_IMG135_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG135_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG135: CRSR_IMG Mask      */

// -------------------------------------  LCD_CRSR_IMG136  ----------------------------------------
#define LCD_CRSR_IMG136_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG136: CRSR_IMG Position  */
#define LCD_CRSR_IMG136_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG136_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG136: CRSR_IMG Mask      */

// -------------------------------------  LCD_CRSR_IMG137  ----------------------------------------
#define LCD_CRSR_IMG137_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG137: CRSR_IMG Position  */
#define LCD_CRSR_IMG137_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG137_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG137: CRSR_IMG Mask      */

// -------------------------------------  LCD_CRSR_IMG138  ----------------------------------------
#define LCD_CRSR_IMG138_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG138: CRSR_IMG Position  */
#define LCD_CRSR_IMG138_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG138_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG138: CRSR_IMG Mask      */

// -------------------------------------  LCD_CRSR_IMG139  ----------------------------------------
#define LCD_CRSR_IMG139_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG139: CRSR_IMG Position  */
#define LCD_CRSR_IMG139_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG139_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG139: CRSR_IMG Mask      */

// -------------------------------------  LCD_CRSR_IMG140  ----------------------------------------
#define LCD_CRSR_IMG140_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG140: CRSR_IMG Position  */
#define LCD_CRSR_IMG140_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG140_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG140: CRSR_IMG Mask      */

// -------------------------------------  LCD_CRSR_IMG141  ----------------------------------------
#define LCD_CRSR_IMG141_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG141: CRSR_IMG Position  */
#define LCD_CRSR_IMG141_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG141_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG141: CRSR_IMG Mask      */

// -------------------------------------  LCD_CRSR_IMG142  ----------------------------------------
#define LCD_CRSR_IMG142_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG142: CRSR_IMG Position  */
#define LCD_CRSR_IMG142_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG142_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG142: CRSR_IMG Mask      */

// -------------------------------------  LCD_CRSR_IMG143  ----------------------------------------
#define LCD_CRSR_IMG143_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG143: CRSR_IMG Position  */
#define LCD_CRSR_IMG143_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG143_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG143: CRSR_IMG Mask      */

// -------------------------------------  LCD_CRSR_IMG144  ----------------------------------------
#define LCD_CRSR_IMG144_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG144: CRSR_IMG Position  */
#define LCD_CRSR_IMG144_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG144_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG144: CRSR_IMG Mask      */

// -------------------------------------  LCD_CRSR_IMG145  ----------------------------------------
#define LCD_CRSR_IMG145_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG145: CRSR_IMG Position  */
#define LCD_CRSR_IMG145_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG145_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG145: CRSR_IMG Mask      */

// -------------------------------------  LCD_CRSR_IMG146  ----------------------------------------
#define LCD_CRSR_IMG146_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG146: CRSR_IMG Position  */
#define LCD_CRSR_IMG146_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG146_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG146: CRSR_IMG Mask      */

// -------------------------------------  LCD_CRSR_IMG147  ----------------------------------------
#define LCD_CRSR_IMG147_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG147: CRSR_IMG Position  */
#define LCD_CRSR_IMG147_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG147_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG147: CRSR_IMG Mask      */

// -------------------------------------  LCD_CRSR_IMG148  ----------------------------------------
#define LCD_CRSR_IMG148_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG148: CRSR_IMG Position  */
#define LCD_CRSR_IMG148_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG148_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG148: CRSR_IMG Mask      */

// -------------------------------------  LCD_CRSR_IMG149  ----------------------------------------
#define LCD_CRSR_IMG149_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG149: CRSR_IMG Position  */
#define LCD_CRSR_IMG149_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG149_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG149: CRSR_IMG Mask      */

// -------------------------------------  LCD_CRSR_IMG150  ----------------------------------------
#define LCD_CRSR_IMG150_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG150: CRSR_IMG Position  */
#define LCD_CRSR_IMG150_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG150_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG150: CRSR_IMG Mask      */

// -------------------------------------  LCD_CRSR_IMG151  ----------------------------------------
#define LCD_CRSR_IMG151_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG151: CRSR_IMG Position  */
#define LCD_CRSR_IMG151_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG151_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG151: CRSR_IMG Mask      */

// -------------------------------------  LCD_CRSR_IMG152  ----------------------------------------
#define LCD_CRSR_IMG152_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG152: CRSR_IMG Position  */
#define LCD_CRSR_IMG152_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG152_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG152: CRSR_IMG Mask      */

// -------------------------------------  LCD_CRSR_IMG153  ----------------------------------------
#define LCD_CRSR_IMG153_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG153: CRSR_IMG Position  */
#define LCD_CRSR_IMG153_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG153_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG153: CRSR_IMG Mask      */

// -------------------------------------  LCD_CRSR_IMG154  ----------------------------------------
#define LCD_CRSR_IMG154_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG154: CRSR_IMG Position  */
#define LCD_CRSR_IMG154_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG154_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG154: CRSR_IMG Mask      */

// -------------------------------------  LCD_CRSR_IMG155  ----------------------------------------
#define LCD_CRSR_IMG155_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG155: CRSR_IMG Position  */
#define LCD_CRSR_IMG155_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG155_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG155: CRSR_IMG Mask      */

// -------------------------------------  LCD_CRSR_IMG156  ----------------------------------------
#define LCD_CRSR_IMG156_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG156: CRSR_IMG Position  */
#define LCD_CRSR_IMG156_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG156_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG156: CRSR_IMG Mask      */

// -------------------------------------  LCD_CRSR_IMG157  ----------------------------------------
#define LCD_CRSR_IMG157_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG157: CRSR_IMG Position  */
#define LCD_CRSR_IMG157_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG157_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG157: CRSR_IMG Mask      */

// -------------------------------------  LCD_CRSR_IMG158  ----------------------------------------
#define LCD_CRSR_IMG158_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG158: CRSR_IMG Position  */
#define LCD_CRSR_IMG158_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG158_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG158: CRSR_IMG Mask      */

// -------------------------------------  LCD_CRSR_IMG159  ----------------------------------------
#define LCD_CRSR_IMG159_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG159: CRSR_IMG Position  */
#define LCD_CRSR_IMG159_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG159_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG159: CRSR_IMG Mask      */

// -------------------------------------  LCD_CRSR_IMG160  ----------------------------------------
#define LCD_CRSR_IMG160_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG160: CRSR_IMG Position  */
#define LCD_CRSR_IMG160_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG160_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG160: CRSR_IMG Mask      */

// -------------------------------------  LCD_CRSR_IMG161  ----------------------------------------
#define LCD_CRSR_IMG161_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG161: CRSR_IMG Position  */
#define LCD_CRSR_IMG161_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG161_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG161: CRSR_IMG Mask      */

// -------------------------------------  LCD_CRSR_IMG162  ----------------------------------------
#define LCD_CRSR_IMG162_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG162: CRSR_IMG Position  */
#define LCD_CRSR_IMG162_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG162_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG162: CRSR_IMG Mask      */

// -------------------------------------  LCD_CRSR_IMG163  ----------------------------------------
#define LCD_CRSR_IMG163_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG163: CRSR_IMG Position  */
#define LCD_CRSR_IMG163_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG163_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG163: CRSR_IMG Mask      */

// -------------------------------------  LCD_CRSR_IMG164  ----------------------------------------
#define LCD_CRSR_IMG164_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG164: CRSR_IMG Position  */
#define LCD_CRSR_IMG164_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG164_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG164: CRSR_IMG Mask      */

// -------------------------------------  LCD_CRSR_IMG165  ----------------------------------------
#define LCD_CRSR_IMG165_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG165: CRSR_IMG Position  */
#define LCD_CRSR_IMG165_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG165_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG165: CRSR_IMG Mask      */

// -------------------------------------  LCD_CRSR_IMG166  ----------------------------------------
#define LCD_CRSR_IMG166_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG166: CRSR_IMG Position  */
#define LCD_CRSR_IMG166_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG166_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG166: CRSR_IMG Mask      */

// -------------------------------------  LCD_CRSR_IMG167  ----------------------------------------
#define LCD_CRSR_IMG167_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG167: CRSR_IMG Position  */
#define LCD_CRSR_IMG167_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG167_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG167: CRSR_IMG Mask      */

// -------------------------------------  LCD_CRSR_IMG168  ----------------------------------------
#define LCD_CRSR_IMG168_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG168: CRSR_IMG Position  */
#define LCD_CRSR_IMG168_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG168_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG168: CRSR_IMG Mask      */

// -------------------------------------  LCD_CRSR_IMG169  ----------------------------------------
#define LCD_CRSR_IMG169_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG169: CRSR_IMG Position  */
#define LCD_CRSR_IMG169_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG169_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG169: CRSR_IMG Mask      */

// -------------------------------------  LCD_CRSR_IMG170  ----------------------------------------
#define LCD_CRSR_IMG170_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG170: CRSR_IMG Position  */
#define LCD_CRSR_IMG170_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG170_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG170: CRSR_IMG Mask      */

// -------------------------------------  LCD_CRSR_IMG171  ----------------------------------------
#define LCD_CRSR_IMG171_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG171: CRSR_IMG Position  */
#define LCD_CRSR_IMG171_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG171_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG171: CRSR_IMG Mask      */

// -------------------------------------  LCD_CRSR_IMG172  ----------------------------------------
#define LCD_CRSR_IMG172_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG172: CRSR_IMG Position  */
#define LCD_CRSR_IMG172_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG172_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG172: CRSR_IMG Mask      */

// -------------------------------------  LCD_CRSR_IMG173  ----------------------------------------
#define LCD_CRSR_IMG173_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG173: CRSR_IMG Position  */
#define LCD_CRSR_IMG173_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG173_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG173: CRSR_IMG Mask      */

// -------------------------------------  LCD_CRSR_IMG174  ----------------------------------------
#define LCD_CRSR_IMG174_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG174: CRSR_IMG Position  */
#define LCD_CRSR_IMG174_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG174_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG174: CRSR_IMG Mask      */

// -------------------------------------  LCD_CRSR_IMG175  ----------------------------------------
#define LCD_CRSR_IMG175_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG175: CRSR_IMG Position  */
#define LCD_CRSR_IMG175_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG175_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG175: CRSR_IMG Mask      */

// -------------------------------------  LCD_CRSR_IMG176  ----------------------------------------
#define LCD_CRSR_IMG176_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG176: CRSR_IMG Position  */
#define LCD_CRSR_IMG176_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG176_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG176: CRSR_IMG Mask      */

// -------------------------------------  LCD_CRSR_IMG177  ----------------------------------------
#define LCD_CRSR_IMG177_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG177: CRSR_IMG Position  */
#define LCD_CRSR_IMG177_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG177_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG177: CRSR_IMG Mask      */

// -------------------------------------  LCD_CRSR_IMG178  ----------------------------------------
#define LCD_CRSR_IMG178_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG178: CRSR_IMG Position  */
#define LCD_CRSR_IMG178_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG178_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG178: CRSR_IMG Mask      */

// -------------------------------------  LCD_CRSR_IMG179  ----------------------------------------
#define LCD_CRSR_IMG179_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG179: CRSR_IMG Position  */
#define LCD_CRSR_IMG179_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG179_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG179: CRSR_IMG Mask      */

// -------------------------------------  LCD_CRSR_IMG180  ----------------------------------------
#define LCD_CRSR_IMG180_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG180: CRSR_IMG Position  */
#define LCD_CRSR_IMG180_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG180_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG180: CRSR_IMG Mask      */

// -------------------------------------  LCD_CRSR_IMG181  ----------------------------------------
#define LCD_CRSR_IMG181_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG181: CRSR_IMG Position  */
#define LCD_CRSR_IMG181_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG181_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG181: CRSR_IMG Mask      */

// -------------------------------------  LCD_CRSR_IMG182  ----------------------------------------
#define LCD_CRSR_IMG182_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG182: CRSR_IMG Position  */
#define LCD_CRSR_IMG182_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG182_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG182: CRSR_IMG Mask      */

// -------------------------------------  LCD_CRSR_IMG183  ----------------------------------------
#define LCD_CRSR_IMG183_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG183: CRSR_IMG Position  */
#define LCD_CRSR_IMG183_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG183_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG183: CRSR_IMG Mask      */

// -------------------------------------  LCD_CRSR_IMG184  ----------------------------------------
#define LCD_CRSR_IMG184_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG184: CRSR_IMG Position  */
#define LCD_CRSR_IMG184_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG184_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG184: CRSR_IMG Mask      */

// -------------------------------------  LCD_CRSR_IMG185  ----------------------------------------
#define LCD_CRSR_IMG185_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG185: CRSR_IMG Position  */
#define LCD_CRSR_IMG185_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG185_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG185: CRSR_IMG Mask      */

// -------------------------------------  LCD_CRSR_IMG186  ----------------------------------------
#define LCD_CRSR_IMG186_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG186: CRSR_IMG Position  */
#define LCD_CRSR_IMG186_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG186_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG186: CRSR_IMG Mask      */

// -------------------------------------  LCD_CRSR_IMG187  ----------------------------------------
#define LCD_CRSR_IMG187_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG187: CRSR_IMG Position  */
#define LCD_CRSR_IMG187_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG187_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG187: CRSR_IMG Mask      */

// -------------------------------------  LCD_CRSR_IMG188  ----------------------------------------
#define LCD_CRSR_IMG188_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG188: CRSR_IMG Position  */
#define LCD_CRSR_IMG188_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG188_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG188: CRSR_IMG Mask      */

// -------------------------------------  LCD_CRSR_IMG189  ----------------------------------------
#define LCD_CRSR_IMG189_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG189: CRSR_IMG Position  */
#define LCD_CRSR_IMG189_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG189_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG189: CRSR_IMG Mask      */

// -------------------------------------  LCD_CRSR_IMG190  ----------------------------------------
#define LCD_CRSR_IMG190_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG190: CRSR_IMG Position  */
#define LCD_CRSR_IMG190_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG190_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG190: CRSR_IMG Mask      */

// -------------------------------------  LCD_CRSR_IMG191  ----------------------------------------
#define LCD_CRSR_IMG191_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG191: CRSR_IMG Position  */
#define LCD_CRSR_IMG191_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG191_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG191: CRSR_IMG Mask      */

// -------------------------------------  LCD_CRSR_IMG192  ----------------------------------------
#define LCD_CRSR_IMG192_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG192: CRSR_IMG Position  */
#define LCD_CRSR_IMG192_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG192_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG192: CRSR_IMG Mask      */

// -------------------------------------  LCD_CRSR_IMG193  ----------------------------------------
#define LCD_CRSR_IMG193_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG193: CRSR_IMG Position  */
#define LCD_CRSR_IMG193_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG193_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG193: CRSR_IMG Mask      */

// -------------------------------------  LCD_CRSR_IMG194  ----------------------------------------
#define LCD_CRSR_IMG194_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG194: CRSR_IMG Position  */
#define LCD_CRSR_IMG194_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG194_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG194: CRSR_IMG Mask      */

// -------------------------------------  LCD_CRSR_IMG195  ----------------------------------------
#define LCD_CRSR_IMG195_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG195: CRSR_IMG Position  */
#define LCD_CRSR_IMG195_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG195_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG195: CRSR_IMG Mask      */

// -------------------------------------  LCD_CRSR_IMG196  ----------------------------------------
#define LCD_CRSR_IMG196_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG196: CRSR_IMG Position  */
#define LCD_CRSR_IMG196_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG196_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG196: CRSR_IMG Mask      */

// -------------------------------------  LCD_CRSR_IMG197  ----------------------------------------
#define LCD_CRSR_IMG197_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG197: CRSR_IMG Position  */
#define LCD_CRSR_IMG197_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG197_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG197: CRSR_IMG Mask      */

// -------------------------------------  LCD_CRSR_IMG198  ----------------------------------------
#define LCD_CRSR_IMG198_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG198: CRSR_IMG Position  */
#define LCD_CRSR_IMG198_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG198_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG198: CRSR_IMG Mask      */

// -------------------------------------  LCD_CRSR_IMG199  ----------------------------------------
#define LCD_CRSR_IMG199_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG199: CRSR_IMG Position  */
#define LCD_CRSR_IMG199_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG199_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG199: CRSR_IMG Mask      */

// -------------------------------------  LCD_CRSR_IMG200  ----------------------------------------
#define LCD_CRSR_IMG200_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG200: CRSR_IMG Position  */
#define LCD_CRSR_IMG200_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG200_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG200: CRSR_IMG Mask      */

// -------------------------------------  LCD_CRSR_IMG201  ----------------------------------------
#define LCD_CRSR_IMG201_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG201: CRSR_IMG Position  */
#define LCD_CRSR_IMG201_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG201_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG201: CRSR_IMG Mask      */

// -------------------------------------  LCD_CRSR_IMG202  ----------------------------------------
#define LCD_CRSR_IMG202_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG202: CRSR_IMG Position  */
#define LCD_CRSR_IMG202_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG202_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG202: CRSR_IMG Mask      */

// -------------------------------------  LCD_CRSR_IMG203  ----------------------------------------
#define LCD_CRSR_IMG203_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG203: CRSR_IMG Position  */
#define LCD_CRSR_IMG203_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG203_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG203: CRSR_IMG Mask      */

// -------------------------------------  LCD_CRSR_IMG204  ----------------------------------------
#define LCD_CRSR_IMG204_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG204: CRSR_IMG Position  */
#define LCD_CRSR_IMG204_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG204_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG204: CRSR_IMG Mask      */

// -------------------------------------  LCD_CRSR_IMG205  ----------------------------------------
#define LCD_CRSR_IMG205_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG205: CRSR_IMG Position  */
#define LCD_CRSR_IMG205_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG205_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG205: CRSR_IMG Mask      */

// -------------------------------------  LCD_CRSR_IMG206  ----------------------------------------
#define LCD_CRSR_IMG206_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG206: CRSR_IMG Position  */
#define LCD_CRSR_IMG206_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG206_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG206: CRSR_IMG Mask      */

// -------------------------------------  LCD_CRSR_IMG207  ----------------------------------------
#define LCD_CRSR_IMG207_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG207: CRSR_IMG Position  */
#define LCD_CRSR_IMG207_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG207_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG207: CRSR_IMG Mask      */

// -------------------------------------  LCD_CRSR_IMG208  ----------------------------------------
#define LCD_CRSR_IMG208_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG208: CRSR_IMG Position  */
#define LCD_CRSR_IMG208_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG208_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG208: CRSR_IMG Mask      */

// -------------------------------------  LCD_CRSR_IMG209  ----------------------------------------
#define LCD_CRSR_IMG209_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG209: CRSR_IMG Position  */
#define LCD_CRSR_IMG209_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG209_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG209: CRSR_IMG Mask      */

// -------------------------------------  LCD_CRSR_IMG210  ----------------------------------------
#define LCD_CRSR_IMG210_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG210: CRSR_IMG Position  */
#define LCD_CRSR_IMG210_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG210_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG210: CRSR_IMG Mask      */

// -------------------------------------  LCD_CRSR_IMG211  ----------------------------------------
#define LCD_CRSR_IMG211_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG211: CRSR_IMG Position  */
#define LCD_CRSR_IMG211_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG211_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG211: CRSR_IMG Mask      */

// -------------------------------------  LCD_CRSR_IMG212  ----------------------------------------
#define LCD_CRSR_IMG212_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG212: CRSR_IMG Position  */
#define LCD_CRSR_IMG212_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG212_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG212: CRSR_IMG Mask      */

// -------------------------------------  LCD_CRSR_IMG213  ----------------------------------------
#define LCD_CRSR_IMG213_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG213: CRSR_IMG Position  */
#define LCD_CRSR_IMG213_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG213_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG213: CRSR_IMG Mask      */

// -------------------------------------  LCD_CRSR_IMG214  ----------------------------------------
#define LCD_CRSR_IMG214_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG214: CRSR_IMG Position  */
#define LCD_CRSR_IMG214_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG214_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG214: CRSR_IMG Mask      */

// -------------------------------------  LCD_CRSR_IMG215  ----------------------------------------
#define LCD_CRSR_IMG215_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG215: CRSR_IMG Position  */
#define LCD_CRSR_IMG215_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG215_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG215: CRSR_IMG Mask      */

// -------------------------------------  LCD_CRSR_IMG216  ----------------------------------------
#define LCD_CRSR_IMG216_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG216: CRSR_IMG Position  */
#define LCD_CRSR_IMG216_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG216_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG216: CRSR_IMG Mask      */

// -------------------------------------  LCD_CRSR_IMG217  ----------------------------------------
#define LCD_CRSR_IMG217_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG217: CRSR_IMG Position  */
#define LCD_CRSR_IMG217_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG217_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG217: CRSR_IMG Mask      */

// -------------------------------------  LCD_CRSR_IMG218  ----------------------------------------
#define LCD_CRSR_IMG218_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG218: CRSR_IMG Position  */
#define LCD_CRSR_IMG218_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG218_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG218: CRSR_IMG Mask      */

// -------------------------------------  LCD_CRSR_IMG219  ----------------------------------------
#define LCD_CRSR_IMG219_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG219: CRSR_IMG Position  */
#define LCD_CRSR_IMG219_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG219_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG219: CRSR_IMG Mask      */

// -------------------------------------  LCD_CRSR_IMG220  ----------------------------------------
#define LCD_CRSR_IMG220_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG220: CRSR_IMG Position  */
#define LCD_CRSR_IMG220_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG220_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG220: CRSR_IMG Mask      */

// -------------------------------------  LCD_CRSR_IMG221  ----------------------------------------
#define LCD_CRSR_IMG221_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG221: CRSR_IMG Position  */
#define LCD_CRSR_IMG221_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG221_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG221: CRSR_IMG Mask      */

// -------------------------------------  LCD_CRSR_IMG222  ----------------------------------------
#define LCD_CRSR_IMG222_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG222: CRSR_IMG Position  */
#define LCD_CRSR_IMG222_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG222_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG222: CRSR_IMG Mask      */

// -------------------------------------  LCD_CRSR_IMG223  ----------------------------------------
#define LCD_CRSR_IMG223_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG223: CRSR_IMG Position  */
#define LCD_CRSR_IMG223_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG223_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG223: CRSR_IMG Mask      */

// -------------------------------------  LCD_CRSR_IMG224  ----------------------------------------
#define LCD_CRSR_IMG224_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG224: CRSR_IMG Position  */
#define LCD_CRSR_IMG224_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG224_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG224: CRSR_IMG Mask      */

// -------------------------------------  LCD_CRSR_IMG225  ----------------------------------------
#define LCD_CRSR_IMG225_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG225: CRSR_IMG Position  */
#define LCD_CRSR_IMG225_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG225_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG225: CRSR_IMG Mask      */

// -------------------------------------  LCD_CRSR_IMG226  ----------------------------------------
#define LCD_CRSR_IMG226_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG226: CRSR_IMG Position  */
#define LCD_CRSR_IMG226_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG226_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG226: CRSR_IMG Mask      */

// -------------------------------------  LCD_CRSR_IMG227  ----------------------------------------
#define LCD_CRSR_IMG227_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG227: CRSR_IMG Position  */
#define LCD_CRSR_IMG227_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG227_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG227: CRSR_IMG Mask      */

// -------------------------------------  LCD_CRSR_IMG228  ----------------------------------------
#define LCD_CRSR_IMG228_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG228: CRSR_IMG Position  */
#define LCD_CRSR_IMG228_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG228_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG228: CRSR_IMG Mask      */

// -------------------------------------  LCD_CRSR_IMG229  ----------------------------------------
#define LCD_CRSR_IMG229_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG229: CRSR_IMG Position  */
#define LCD_CRSR_IMG229_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG229_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG229: CRSR_IMG Mask      */

// -------------------------------------  LCD_CRSR_IMG230  ----------------------------------------
#define LCD_CRSR_IMG230_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG230: CRSR_IMG Position  */
#define LCD_CRSR_IMG230_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG230_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG230: CRSR_IMG Mask      */

// -------------------------------------  LCD_CRSR_IMG231  ----------------------------------------
#define LCD_CRSR_IMG231_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG231: CRSR_IMG Position  */
#define LCD_CRSR_IMG231_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG231_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG231: CRSR_IMG Mask      */

// -------------------------------------  LCD_CRSR_IMG232  ----------------------------------------
#define LCD_CRSR_IMG232_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG232: CRSR_IMG Position  */
#define LCD_CRSR_IMG232_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG232_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG232: CRSR_IMG Mask      */

// -------------------------------------  LCD_CRSR_IMG233  ----------------------------------------
#define LCD_CRSR_IMG233_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG233: CRSR_IMG Position  */
#define LCD_CRSR_IMG233_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG233_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG233: CRSR_IMG Mask      */

// -------------------------------------  LCD_CRSR_IMG234  ----------------------------------------
#define LCD_CRSR_IMG234_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG234: CRSR_IMG Position  */
#define LCD_CRSR_IMG234_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG234_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG234: CRSR_IMG Mask      */

// -------------------------------------  LCD_CRSR_IMG235  ----------------------------------------
#define LCD_CRSR_IMG235_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG235: CRSR_IMG Position  */
#define LCD_CRSR_IMG235_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG235_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG235: CRSR_IMG Mask      */

// -------------------------------------  LCD_CRSR_IMG236  ----------------------------------------
#define LCD_CRSR_IMG236_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG236: CRSR_IMG Position  */
#define LCD_CRSR_IMG236_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG236_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG236: CRSR_IMG Mask      */

// -------------------------------------  LCD_CRSR_IMG237  ----------------------------------------
#define LCD_CRSR_IMG237_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG237: CRSR_IMG Position  */
#define LCD_CRSR_IMG237_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG237_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG237: CRSR_IMG Mask      */

// -------------------------------------  LCD_CRSR_IMG238  ----------------------------------------
#define LCD_CRSR_IMG238_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG238: CRSR_IMG Position  */
#define LCD_CRSR_IMG238_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG238_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG238: CRSR_IMG Mask      */

// -------------------------------------  LCD_CRSR_IMG239  ----------------------------------------
#define LCD_CRSR_IMG239_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG239: CRSR_IMG Position  */
#define LCD_CRSR_IMG239_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG239_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG239: CRSR_IMG Mask      */

// -------------------------------------  LCD_CRSR_IMG240  ----------------------------------------
#define LCD_CRSR_IMG240_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG240: CRSR_IMG Position  */
#define LCD_CRSR_IMG240_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG240_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG240: CRSR_IMG Mask      */

// -------------------------------------  LCD_CRSR_IMG241  ----------------------------------------
#define LCD_CRSR_IMG241_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG241: CRSR_IMG Position  */
#define LCD_CRSR_IMG241_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG241_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG241: CRSR_IMG Mask      */

// -------------------------------------  LCD_CRSR_IMG242  ----------------------------------------
#define LCD_CRSR_IMG242_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG242: CRSR_IMG Position  */
#define LCD_CRSR_IMG242_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG242_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG242: CRSR_IMG Mask      */

// -------------------------------------  LCD_CRSR_IMG243  ----------------------------------------
#define LCD_CRSR_IMG243_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG243: CRSR_IMG Position  */
#define LCD_CRSR_IMG243_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG243_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG243: CRSR_IMG Mask      */

// -------------------------------------  LCD_CRSR_IMG244  ----------------------------------------
#define LCD_CRSR_IMG244_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG244: CRSR_IMG Position  */
#define LCD_CRSR_IMG244_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG244_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG244: CRSR_IMG Mask      */

// -------------------------------------  LCD_CRSR_IMG245  ----------------------------------------
#define LCD_CRSR_IMG245_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG245: CRSR_IMG Position  */
#define LCD_CRSR_IMG245_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG245_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG245: CRSR_IMG Mask      */

// -------------------------------------  LCD_CRSR_IMG246  ----------------------------------------
#define LCD_CRSR_IMG246_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG246: CRSR_IMG Position  */
#define LCD_CRSR_IMG246_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG246_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG246: CRSR_IMG Mask      */

// -------------------------------------  LCD_CRSR_IMG247  ----------------------------------------
#define LCD_CRSR_IMG247_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG247: CRSR_IMG Position  */
#define LCD_CRSR_IMG247_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG247_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG247: CRSR_IMG Mask      */

// -------------------------------------  LCD_CRSR_IMG248  ----------------------------------------
#define LCD_CRSR_IMG248_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG248: CRSR_IMG Position  */
#define LCD_CRSR_IMG248_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG248_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG248: CRSR_IMG Mask      */

// -------------------------------------  LCD_CRSR_IMG249  ----------------------------------------
#define LCD_CRSR_IMG249_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG249: CRSR_IMG Position  */
#define LCD_CRSR_IMG249_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG249_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG249: CRSR_IMG Mask      */

// -------------------------------------  LCD_CRSR_IMG250  ----------------------------------------
#define LCD_CRSR_IMG250_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG250: CRSR_IMG Position  */
#define LCD_CRSR_IMG250_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG250_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG250: CRSR_IMG Mask      */

// -------------------------------------  LCD_CRSR_IMG251  ----------------------------------------
#define LCD_CRSR_IMG251_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG251: CRSR_IMG Position  */
#define LCD_CRSR_IMG251_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG251_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG251: CRSR_IMG Mask      */

// -------------------------------------  LCD_CRSR_IMG252  ----------------------------------------
#define LCD_CRSR_IMG252_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG252: CRSR_IMG Position  */
#define LCD_CRSR_IMG252_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG252_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG252: CRSR_IMG Mask      */

// -------------------------------------  LCD_CRSR_IMG253  ----------------------------------------
#define LCD_CRSR_IMG253_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG253: CRSR_IMG Position  */
#define LCD_CRSR_IMG253_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG253_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG253: CRSR_IMG Mask      */

// -------------------------------------  LCD_CRSR_IMG254  ----------------------------------------
#define LCD_CRSR_IMG254_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG254: CRSR_IMG Position  */
#define LCD_CRSR_IMG254_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG254_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG254: CRSR_IMG Mask      */

// -------------------------------------  LCD_CRSR_IMG255  ----------------------------------------
#define LCD_CRSR_IMG255_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG255: CRSR_IMG Position  */
#define LCD_CRSR_IMG255_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG255_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG255: CRSR_IMG Mask      */

// --------------------------------------  LCD_CRSR_CTRL  -----------------------------------------
#define LCD_CRSR_CTRL_CrsrOn_Pos                              0                                                         /*!< LCD CRSR_CTRL: CrsrOn Position      */
#define LCD_CRSR_CTRL_CrsrOn_Msk                              (0x01UL << LCD_CRSR_CTRL_CrsrOn_Pos)                      /*!< LCD CRSR_CTRL: CrsrOn Mask          */
#define LCD_CRSR_CTRL_CRSRNUM1_0_Pos                          4                                                         /*!< LCD CRSR_CTRL: CRSRNUM1_0 Position  */
#define LCD_CRSR_CTRL_CRSRNUM1_0_Msk                          (0x03UL << LCD_CRSR_CTRL_CRSRNUM1_0_Pos)                  /*!< LCD CRSR_CTRL: CRSRNUM1_0 Mask      */

// --------------------------------------  LCD_CRSR_CFG  ------------------------------------------
#define LCD_CRSR_CFG_CrsrSize_Pos                             0                                                         /*!< LCD CRSR_CFG: CrsrSize Position     */
#define LCD_CRSR_CFG_CrsrSize_Msk                             (0x01UL << LCD_CRSR_CFG_CrsrSize_Pos)                     /*!< LCD CRSR_CFG: CrsrSize Mask         */
#define LCD_CRSR_CFG_FRAMESYNC_Pos                            1                                                         /*!< LCD CRSR_CFG: FRAMESYNC Position    */
#define LCD_CRSR_CFG_FRAMESYNC_Msk                            (0x01UL << LCD_CRSR_CFG_FRAMESYNC_Pos)                    /*!< LCD CRSR_CFG: FRAMESYNC Mask        */

// --------------------------------------  LCD_CRSR_PAL0  -----------------------------------------
#define LCD_CRSR_PAL0_RED_Pos                                 0                                                         /*!< LCD CRSR_PAL0: RED Position         */
#define LCD_CRSR_PAL0_RED_Msk                                 (0x000000ffUL << LCD_CRSR_PAL0_RED_Pos)                   /*!< LCD CRSR_PAL0: RED Mask             */
#define LCD_CRSR_PAL0_GREEN_Pos                               8                                                         /*!< LCD CRSR_PAL0: GREEN Position       */
#define LCD_CRSR_PAL0_GREEN_Msk                               (0x000000ffUL << LCD_CRSR_PAL0_GREEN_Pos)                 /*!< LCD CRSR_PAL0: GREEN Mask           */
#define LCD_CRSR_PAL0_BLUE_Pos                                16                                                        /*!< LCD CRSR_PAL0: BLUE Position        */
#define LCD_CRSR_PAL0_BLUE_Msk                                (0x000000ffUL << LCD_CRSR_PAL0_BLUE_Pos)                  /*!< LCD CRSR_PAL0: BLUE Mask            */

// --------------------------------------  LCD_CRSR_PAL1  -----------------------------------------
#define LCD_CRSR_PAL1_RED_Pos                                 0                                                         /*!< LCD CRSR_PAL1: RED Position         */
#define LCD_CRSR_PAL1_RED_Msk                                 (0x000000ffUL << LCD_CRSR_PAL1_RED_Pos)                   /*!< LCD CRSR_PAL1: RED Mask             */
#define LCD_CRSR_PAL1_GREEN_Pos                               8                                                         /*!< LCD CRSR_PAL1: GREEN Position       */
#define LCD_CRSR_PAL1_GREEN_Msk                               (0x000000ffUL << LCD_CRSR_PAL1_GREEN_Pos)                 /*!< LCD CRSR_PAL1: GREEN Mask           */
#define LCD_CRSR_PAL1_BLUE_Pos                                16                                                        /*!< LCD CRSR_PAL1: BLUE Position        */
#define LCD_CRSR_PAL1_BLUE_Msk                                (0x000000ffUL << LCD_CRSR_PAL1_BLUE_Pos)                  /*!< LCD CRSR_PAL1: BLUE Mask            */

// ---------------------------------------  LCD_CRSR_XY  ------------------------------------------
#define LCD_CRSR_XY_CRSRX_Pos                                 0                                                         /*!< LCD CRSR_XY: CRSRX Position         */
#define LCD_CRSR_XY_CRSRX_Msk                                 (0x000003ffUL << LCD_CRSR_XY_CRSRX_Pos)                   /*!< LCD CRSR_XY: CRSRX Mask             */
#define LCD_CRSR_XY_CRSRY_Pos                                 16                                                        /*!< LCD CRSR_XY: CRSRY Position         */
#define LCD_CRSR_XY_CRSRY_Msk                                 (0x000003ffUL << LCD_CRSR_XY_CRSRY_Pos)                   /*!< LCD CRSR_XY: CRSRY Mask             */

// --------------------------------------  LCD_CRSR_CLIP  -----------------------------------------
#define LCD_CRSR_CLIP_CRSRCLIPX_Pos                           0                                                         /*!< LCD CRSR_CLIP: CRSRCLIPX Position   */
#define LCD_CRSR_CLIP_CRSRCLIPX_Msk                           (0x3fUL << LCD_CRSR_CLIP_CRSRCLIPX_Pos)                   /*!< LCD CRSR_CLIP: CRSRCLIPX Mask       */
#define LCD_CRSR_CLIP_CRSRCLIPY_Pos                           8                                                         /*!< LCD CRSR_CLIP: CRSRCLIPY Position   */
#define LCD_CRSR_CLIP_CRSRCLIPY_Msk                           (0x3fUL << LCD_CRSR_CLIP_CRSRCLIPY_Pos)                   /*!< LCD CRSR_CLIP: CRSRCLIPY Mask       */

// -------------------------------------  LCD_CRSR_INTMSK  ----------------------------------------
#define LCD_CRSR_INTMSK_CRSRIM_Pos                            0                                                         /*!< LCD CRSR_INTMSK: CRSRIM Position    */
#define LCD_CRSR_INTMSK_CRSRIM_Msk                            (0x01UL << LCD_CRSR_INTMSK_CRSRIM_Pos)                    /*!< LCD CRSR_INTMSK: CRSRIM Mask        */

// -------------------------------------  LCD_CRSR_INTCLR  ----------------------------------------
#define LCD_CRSR_INTCLR_CRSRIC_Pos                            0                                                         /*!< LCD CRSR_INTCLR: CRSRIC Position    */
#define LCD_CRSR_INTCLR_CRSRIC_Msk                            (0x01UL << LCD_CRSR_INTCLR_CRSRIC_Pos)                    /*!< LCD CRSR_INTCLR: CRSRIC Mask        */

// -------------------------------------  LCD_CRSR_INTRAW  ----------------------------------------
#define LCD_CRSR_INTRAW_CRSRRIS_Pos                           0                                                         /*!< LCD CRSR_INTRAW: CRSRRIS Position   */
#define LCD_CRSR_INTRAW_CRSRRIS_Msk                           (0x01UL << LCD_CRSR_INTRAW_CRSRRIS_Pos)                   /*!< LCD CRSR_INTRAW: CRSRRIS Mask       */

// ------------------------------------  LCD_CRSR_INTSTAT  ----------------------------------------
#define LCD_CRSR_INTSTAT_CRSRMIS_Pos                          0                                                         /*!< LCD CRSR_INTSTAT: CRSRMIS Position  */
#define LCD_CRSR_INTSTAT_CRSRMIS_Msk                          (0x01UL << LCD_CRSR_INTSTAT_CRSRMIS_Pos)                  /*!< LCD CRSR_INTSTAT: CRSRMIS Mask      */


// ------------------------------------------------------------------------------------------------
// -----                               ETHERNET Position & Mask                               -----
// ------------------------------------------------------------------------------------------------


// -----------------------------------  ETHERNET_MAC_CONFIG  --------------------------------------
#define ETHERNET_MAC_CONFIG_RE_Pos                            2                                                         /*!< ETHERNET MAC_CONFIG: RE Position    */
#define ETHERNET_MAC_CONFIG_RE_Msk                            (0x01UL << ETHERNET_MAC_CONFIG_RE_Pos)                    /*!< ETHERNET MAC_CONFIG: RE Mask        */
#define ETHERNET_MAC_CONFIG_TE_Pos                            3                                                         /*!< ETHERNET MAC_CONFIG: TE Position    */
#define ETHERNET_MAC_CONFIG_TE_Msk                            (0x01UL << ETHERNET_MAC_CONFIG_TE_Pos)                    /*!< ETHERNET MAC_CONFIG: TE Mask        */
#define ETHERNET_MAC_CONFIG_DF_Pos                            4                                                         /*!< ETHERNET MAC_CONFIG: DF Position    */
#define ETHERNET_MAC_CONFIG_DF_Msk                            (0x01UL << ETHERNET_MAC_CONFIG_DF_Pos)                    /*!< ETHERNET MAC_CONFIG: DF Mask        */
#define ETHERNET_MAC_CONFIG_BL_Pos                            5                                                         /*!< ETHERNET MAC_CONFIG: BL Position    */
#define ETHERNET_MAC_CONFIG_BL_Msk                            (0x03UL << ETHERNET_MAC_CONFIG_BL_Pos)                    /*!< ETHERNET MAC_CONFIG: BL Mask        */
#define ETHERNET_MAC_CONFIG_ACS_Pos                           7                                                         /*!< ETHERNET MAC_CONFIG: ACS Position   */
#define ETHERNET_MAC_CONFIG_ACS_Msk                           (0x01UL << ETHERNET_MAC_CONFIG_ACS_Pos)                   /*!< ETHERNET MAC_CONFIG: ACS Mask       */
#define ETHERNET_MAC_CONFIG_DR_Pos                            9                                                         /*!< ETHERNET MAC_CONFIG: DR Position    */
#define ETHERNET_MAC_CONFIG_DR_Msk                            (0x01UL << ETHERNET_MAC_CONFIG_DR_Pos)                    /*!< ETHERNET MAC_CONFIG: DR Mask        */
#define ETHERNET_MAC_CONFIG_IPC_Pos                           10                                                        /*!< ETHERNET MAC_CONFIG: IPC Position   */
#define ETHERNET_MAC_CONFIG_IPC_Msk                           (0x01UL << ETHERNET_MAC_CONFIG_IPC_Pos)                   /*!< ETHERNET MAC_CONFIG: IPC Mask       */
#define ETHERNET_MAC_CONFIG_DM_Pos                            11                                                        /*!< ETHERNET MAC_CONFIG: DM Position    */
#define ETHERNET_MAC_CONFIG_DM_Msk                            (0x01UL << ETHERNET_MAC_CONFIG_DM_Pos)                    /*!< ETHERNET MAC_CONFIG: DM Mask        */
#define ETHERNET_MAC_CONFIG_LM_Pos                            12                                                        /*!< ETHERNET MAC_CONFIG: LM Position    */
#define ETHERNET_MAC_CONFIG_LM_Msk                            (0x01UL << ETHERNET_MAC_CONFIG_LM_Pos)                    /*!< ETHERNET MAC_CONFIG: LM Mask        */
#define ETHERNET_MAC_CONFIG_DO_Pos                            13                                                        /*!< ETHERNET MAC_CONFIG: DO Position    */
#define ETHERNET_MAC_CONFIG_DO_Msk                            (0x01UL << ETHERNET_MAC_CONFIG_DO_Pos)                    /*!< ETHERNET MAC_CONFIG: DO Mask        */
#define ETHERNET_MAC_CONFIG_FES_Pos                           14                                                        /*!< ETHERNET MAC_CONFIG: FES Position   */
#define ETHERNET_MAC_CONFIG_FES_Msk                           (0x01UL << ETHERNET_MAC_CONFIG_FES_Pos)                   /*!< ETHERNET MAC_CONFIG: FES Mask       */
#define ETHERNET_MAC_CONFIG_PS_Pos                            15                                                        /*!< ETHERNET MAC_CONFIG: PS Position    */
#define ETHERNET_MAC_CONFIG_PS_Msk                            (0x01UL << ETHERNET_MAC_CONFIG_PS_Pos)                    /*!< ETHERNET MAC_CONFIG: PS Mask        */
#define ETHERNET_MAC_CONFIG_DCRS_Pos                          16                                                        /*!< ETHERNET MAC_CONFIG: DCRS Position  */
#define ETHERNET_MAC_CONFIG_DCRS_Msk                          (0x01UL << ETHERNET_MAC_CONFIG_DCRS_Pos)                  /*!< ETHERNET MAC_CONFIG: DCRS Mask      */
#define ETHERNET_MAC_CONFIG_IFG_Pos                           17                                                        /*!< ETHERNET MAC_CONFIG: IFG Position   */
#define ETHERNET_MAC_CONFIG_IFG_Msk                           (0x07UL << ETHERNET_MAC_CONFIG_IFG_Pos)                   /*!< ETHERNET MAC_CONFIG: IFG Mask       */
#define ETHERNET_MAC_CONFIG_JE_Pos                            20                                                        /*!< ETHERNET MAC_CONFIG: JE Position    */
#define ETHERNET_MAC_CONFIG_JE_Msk                            (0x01UL << ETHERNET_MAC_CONFIG_JE_Pos)                    /*!< ETHERNET MAC_CONFIG: JE Mask        */
#define ETHERNET_MAC_CONFIG_JD_Pos                            22                                                        /*!< ETHERNET MAC_CONFIG: JD Position    */
#define ETHERNET_MAC_CONFIG_JD_Msk                            (0x01UL << ETHERNET_MAC_CONFIG_JD_Pos)                    /*!< ETHERNET MAC_CONFIG: JD Mask        */
#define ETHERNET_MAC_CONFIG_WD_Pos                            23                                                        /*!< ETHERNET MAC_CONFIG: WD Position    */
#define ETHERNET_MAC_CONFIG_WD_Msk                            (0x01UL << ETHERNET_MAC_CONFIG_WD_Pos)                    /*!< ETHERNET MAC_CONFIG: WD Mask        */

// --------------------------------  ETHERNET_MAC_FRAME_FILTER  -----------------------------------
#define ETHERNET_MAC_FRAME_FILTER_PR_Pos                      0                                                         /*!< ETHERNET MAC_FRAME_FILTER: PR Position */
#define ETHERNET_MAC_FRAME_FILTER_PR_Msk                      (0x01UL << ETHERNET_MAC_FRAME_FILTER_PR_Pos)              /*!< ETHERNET MAC_FRAME_FILTER: PR Mask  */
#define ETHERNET_MAC_FRAME_FILTER_DAIF_Pos                    3                                                         /*!< ETHERNET MAC_FRAME_FILTER: DAIF Position */
#define ETHERNET_MAC_FRAME_FILTER_DAIF_Msk                    (0x01UL << ETHERNET_MAC_FRAME_FILTER_DAIF_Pos)            /*!< ETHERNET MAC_FRAME_FILTER: DAIF Mask */
#define ETHERNET_MAC_FRAME_FILTER_PM_Pos                      4                                                         /*!< ETHERNET MAC_FRAME_FILTER: PM Position */
#define ETHERNET_MAC_FRAME_FILTER_PM_Msk                      (0x01UL << ETHERNET_MAC_FRAME_FILTER_PM_Pos)              /*!< ETHERNET MAC_FRAME_FILTER: PM Mask  */
#define ETHERNET_MAC_FRAME_FILTER_DBF_Pos                     5                                                         /*!< ETHERNET MAC_FRAME_FILTER: DBF Position */
#define ETHERNET_MAC_FRAME_FILTER_DBF_Msk                     (0x01UL << ETHERNET_MAC_FRAME_FILTER_DBF_Pos)             /*!< ETHERNET MAC_FRAME_FILTER: DBF Mask */
#define ETHERNET_MAC_FRAME_FILTER_PCF_Pos                     6                                                         /*!< ETHERNET MAC_FRAME_FILTER: PCF Position */
#define ETHERNET_MAC_FRAME_FILTER_PCF_Msk                     (0x03UL << ETHERNET_MAC_FRAME_FILTER_PCF_Pos)             /*!< ETHERNET MAC_FRAME_FILTER: PCF Mask */
#define ETHERNET_MAC_FRAME_FILTER_SAIF_Pos                    8                                                         /*!< ETHERNET MAC_FRAME_FILTER: SAIF Position */
#define ETHERNET_MAC_FRAME_FILTER_SAIF_Msk                    (0x01UL << ETHERNET_MAC_FRAME_FILTER_SAIF_Pos)            /*!< ETHERNET MAC_FRAME_FILTER: SAIF Mask */
#define ETHERNET_MAC_FRAME_FILTER_SAF_Pos                     9                                                         /*!< ETHERNET MAC_FRAME_FILTER: SAF Position */
#define ETHERNET_MAC_FRAME_FILTER_SAF_Msk                     (0x01UL << ETHERNET_MAC_FRAME_FILTER_SAF_Pos)             /*!< ETHERNET MAC_FRAME_FILTER: SAF Mask */
#define ETHERNET_MAC_FRAME_FILTER_RA_Pos                      31                                                        /*!< ETHERNET MAC_FRAME_FILTER: RA Position */
#define ETHERNET_MAC_FRAME_FILTER_RA_Msk                      (0x01UL << ETHERNET_MAC_FRAME_FILTER_RA_Pos)              /*!< ETHERNET MAC_FRAME_FILTER: RA Mask  */

// -------------------------------  ETHERNET_MAC_HASHTABLE_HIGH  ----------------------------------
#define ETHERNET_MAC_HASHTABLE_HIGH_HTH_Pos                   0                                                         /*!< ETHERNET MAC_HASHTABLE_HIGH: HTH Position */
#define ETHERNET_MAC_HASHTABLE_HIGH_HTH_Msk                   (0xffffffffUL << ETHERNET_MAC_HASHTABLE_HIGH_HTH_Pos)     /*!< ETHERNET MAC_HASHTABLE_HIGH: HTH Mask */

// -------------------------------  ETHERNET_MAC_HASHTABLE_LOW  -----------------------------------
#define ETHERNET_MAC_HASHTABLE_LOW_HTL_Pos                    0                                                         /*!< ETHERNET MAC_HASHTABLE_LOW: HTL Position */
#define ETHERNET_MAC_HASHTABLE_LOW_HTL_Msk                    (0xffffffffUL << ETHERNET_MAC_HASHTABLE_LOW_HTL_Pos)      /*!< ETHERNET MAC_HASHTABLE_LOW: HTL Mask */

// ----------------------------------  ETHERNET_MAC_MII_ADDR  -------------------------------------
#define ETHERNET_MAC_MII_ADDR_GB_Pos                          0                                                         /*!< ETHERNET MAC_MII_ADDR: GB Position  */
#define ETHERNET_MAC_MII_ADDR_GB_Msk                          (0x01UL << ETHERNET_MAC_MII_ADDR_GB_Pos)                  /*!< ETHERNET MAC_MII_ADDR: GB Mask      */
#define ETHERNET_MAC_MII_ADDR_W_Pos                           1                                                         /*!< ETHERNET MAC_MII_ADDR: W Position   */
#define ETHERNET_MAC_MII_ADDR_W_Msk                           (0x01UL << ETHERNET_MAC_MII_ADDR_W_Pos)                   /*!< ETHERNET MAC_MII_ADDR: W Mask       */
#define ETHERNET_MAC_MII_ADDR_CR_Pos                          2                                                         /*!< ETHERNET MAC_MII_ADDR: CR Position  */
#define ETHERNET_MAC_MII_ADDR_CR_Msk                          (0x0fUL << ETHERNET_MAC_MII_ADDR_CR_Pos)                  /*!< ETHERNET MAC_MII_ADDR: CR Mask      */
#define ETHERNET_MAC_MII_ADDR_GR_Pos                          6                                                         /*!< ETHERNET MAC_MII_ADDR: GR Position  */
#define ETHERNET_MAC_MII_ADDR_GR_Msk                          (0x1fUL << ETHERNET_MAC_MII_ADDR_GR_Pos)                  /*!< ETHERNET MAC_MII_ADDR: GR Mask      */
#define ETHERNET_MAC_MII_ADDR_PA_Pos                          11                                                        /*!< ETHERNET MAC_MII_ADDR: PA Position  */
#define ETHERNET_MAC_MII_ADDR_PA_Msk                          (0x1fUL << ETHERNET_MAC_MII_ADDR_PA_Pos)                  /*!< ETHERNET MAC_MII_ADDR: PA Mask      */

// ----------------------------------  ETHERNET_MAC_MII_DATA  -------------------------------------
#define ETHERNET_MAC_MII_DATA_GD_Pos                          0                                                         /*!< ETHERNET MAC_MII_DATA: GD Position  */
#define ETHERNET_MAC_MII_DATA_GD_Msk                          (0x0000ffffUL << ETHERNET_MAC_MII_DATA_GD_Pos)            /*!< ETHERNET MAC_MII_DATA: GD Mask      */

// ---------------------------------  ETHERNET_MAC_FLOW_CTRL  -------------------------------------
#define ETHERNET_MAC_FLOW_CTRL_FCB_Pos                        0                                                         /*!< ETHERNET MAC_FLOW_CTRL: FCB Position */
#define ETHERNET_MAC_FLOW_CTRL_FCB_Msk                        (0x01UL << ETHERNET_MAC_FLOW_CTRL_FCB_Pos)                /*!< ETHERNET MAC_FLOW_CTRL: FCB Mask    */
#define ETHERNET_MAC_FLOW_CTRL_TFE_Pos                        1                                                         /*!< ETHERNET MAC_FLOW_CTRL: TFE Position */
#define ETHERNET_MAC_FLOW_CTRL_TFE_Msk                        (0x01UL << ETHERNET_MAC_FLOW_CTRL_TFE_Pos)                /*!< ETHERNET MAC_FLOW_CTRL: TFE Mask    */
#define ETHERNET_MAC_FLOW_CTRL_RFE_Pos                        2                                                         /*!< ETHERNET MAC_FLOW_CTRL: RFE Position */
#define ETHERNET_MAC_FLOW_CTRL_RFE_Msk                        (0x01UL << ETHERNET_MAC_FLOW_CTRL_RFE_Pos)                /*!< ETHERNET MAC_FLOW_CTRL: RFE Mask    */
#define ETHERNET_MAC_FLOW_CTRL_UP_Pos                         3                                                         /*!< ETHERNET MAC_FLOW_CTRL: UP Position */
#define ETHERNET_MAC_FLOW_CTRL_UP_Msk                         (0x01UL << ETHERNET_MAC_FLOW_CTRL_UP_Pos)                 /*!< ETHERNET MAC_FLOW_CTRL: UP Mask     */
#define ETHERNET_MAC_FLOW_CTRL_PLT_Pos                        4                                                         /*!< ETHERNET MAC_FLOW_CTRL: PLT Position */
#define ETHERNET_MAC_FLOW_CTRL_PLT_Msk                        (0x03UL << ETHERNET_MAC_FLOW_CTRL_PLT_Pos)                /*!< ETHERNET MAC_FLOW_CTRL: PLT Mask    */
#define ETHERNET_MAC_FLOW_CTRL_DZPQ_Pos                       7                                                         /*!< ETHERNET MAC_FLOW_CTRL: DZPQ Position */
#define ETHERNET_MAC_FLOW_CTRL_DZPQ_Msk                       (0x01UL << ETHERNET_MAC_FLOW_CTRL_DZPQ_Pos)               /*!< ETHERNET MAC_FLOW_CTRL: DZPQ Mask   */
#define ETHERNET_MAC_FLOW_CTRL_PT_Pos                         16                                                        /*!< ETHERNET MAC_FLOW_CTRL: PT Position */
#define ETHERNET_MAC_FLOW_CTRL_PT_Msk                         (0x0000ffffUL << ETHERNET_MAC_FLOW_CTRL_PT_Pos)           /*!< ETHERNET MAC_FLOW_CTRL: PT Mask     */

// ----------------------------------  ETHERNET_MAC_VLAN_TAG  -------------------------------------
#define ETHERNET_MAC_VLAN_TAG_VL_Pos                          0                                                         /*!< ETHERNET MAC_VLAN_TAG: VL Position  */
#define ETHERNET_MAC_VLAN_TAG_VL_Msk                          (0x0000ffffUL << ETHERNET_MAC_VLAN_TAG_VL_Pos)            /*!< ETHERNET MAC_VLAN_TAG: VL Mask      */
#define ETHERNET_MAC_VLAN_TAG_ETV_Pos                         16                                                        /*!< ETHERNET MAC_VLAN_TAG: ETV Position */
#define ETHERNET_MAC_VLAN_TAG_ETV_Msk                         (0x01UL << ETHERNET_MAC_VLAN_TAG_ETV_Pos)                 /*!< ETHERNET MAC_VLAN_TAG: ETV Mask     */

// -----------------------------------  ETHERNET_MAC_DEBUG  ---------------------------------------
#define ETHERNET_MAC_DEBUG_RXIDLESTAT_Pos                     0                                                         /*!< ETHERNET MAC_DEBUG: RXIDLESTAT Position */
#define ETHERNET_MAC_DEBUG_RXIDLESTAT_Msk                     (0x01UL << ETHERNET_MAC_DEBUG_RXIDLESTAT_Pos)             /*!< ETHERNET MAC_DEBUG: RXIDLESTAT Mask */
#define ETHERNET_MAC_DEBUG_FIFOSTAT0_Pos                      1                                                         /*!< ETHERNET MAC_DEBUG: FIFOSTAT0 Position */
#define ETHERNET_MAC_DEBUG_FIFOSTAT0_Msk                      (0x03UL << ETHERNET_MAC_DEBUG_FIFOSTAT0_Pos)              /*!< ETHERNET MAC_DEBUG: FIFOSTAT0 Mask  */
#define ETHERNET_MAC_DEBUG_RXFIFOSTAT1_Pos                    4                                                         /*!< ETHERNET MAC_DEBUG: RXFIFOSTAT1 Position */
#define ETHERNET_MAC_DEBUG_RXFIFOSTAT1_Msk                    (0x01UL << ETHERNET_MAC_DEBUG_RXFIFOSTAT1_Pos)            /*!< ETHERNET MAC_DEBUG: RXFIFOSTAT1 Mask */
#define ETHERNET_MAC_DEBUG_RXFIFOSTAT_Pos                     5                                                         /*!< ETHERNET MAC_DEBUG: RXFIFOSTAT Position */
#define ETHERNET_MAC_DEBUG_RXFIFOSTAT_Msk                     (0x03UL << ETHERNET_MAC_DEBUG_RXFIFOSTAT_Pos)             /*!< ETHERNET MAC_DEBUG: RXFIFOSTAT Mask */
#define ETHERNET_MAC_DEBUG_RXFIFOLVL_Pos                      8                                                         /*!< ETHERNET MAC_DEBUG: RXFIFOLVL Position */
#define ETHERNET_MAC_DEBUG_RXFIFOLVL_Msk                      (0x03UL << ETHERNET_MAC_DEBUG_RXFIFOLVL_Pos)              /*!< ETHERNET MAC_DEBUG: RXFIFOLVL Mask  */
#define ETHERNET_MAC_DEBUG_TXIDLESTAT_Pos                     16                                                        /*!< ETHERNET MAC_DEBUG: TXIDLESTAT Position */
#define ETHERNET_MAC_DEBUG_TXIDLESTAT_Msk                     (0x01UL << ETHERNET_MAC_DEBUG_TXIDLESTAT_Pos)             /*!< ETHERNET MAC_DEBUG: TXIDLESTAT Mask */
#define ETHERNET_MAC_DEBUG_TXSTAT_Pos                         17                                                        /*!< ETHERNET MAC_DEBUG: TXSTAT Position */
#define ETHERNET_MAC_DEBUG_TXSTAT_Msk                         (0x03UL << ETHERNET_MAC_DEBUG_TXSTAT_Pos)                 /*!< ETHERNET MAC_DEBUG: TXSTAT Mask     */
#define ETHERNET_MAC_DEBUG_PAUSE_Pos                          19                                                        /*!< ETHERNET MAC_DEBUG: PAUSE Position  */
#define ETHERNET_MAC_DEBUG_PAUSE_Msk                          (0x01UL << ETHERNET_MAC_DEBUG_PAUSE_Pos)                  /*!< ETHERNET MAC_DEBUG: PAUSE Mask      */
#define ETHERNET_MAC_DEBUG_TXFIFOSTAT_Pos                     20                                                        /*!< ETHERNET MAC_DEBUG: TXFIFOSTAT Position */
#define ETHERNET_MAC_DEBUG_TXFIFOSTAT_Msk                     (0x03UL << ETHERNET_MAC_DEBUG_TXFIFOSTAT_Pos)             /*!< ETHERNET MAC_DEBUG: TXFIFOSTAT Mask */
#define ETHERNET_MAC_DEBUG_TXFIFOSTAT1_Pos                    22                                                        /*!< ETHERNET MAC_DEBUG: TXFIFOSTAT1 Position */
#define ETHERNET_MAC_DEBUG_TXFIFOSTAT1_Msk                    (0x01UL << ETHERNET_MAC_DEBUG_TXFIFOSTAT1_Pos)            /*!< ETHERNET MAC_DEBUG: TXFIFOSTAT1 Mask */
#define ETHERNET_MAC_DEBUG_TXFIFOLVL_Pos                      24                                                        /*!< ETHERNET MAC_DEBUG: TXFIFOLVL Position */
#define ETHERNET_MAC_DEBUG_TXFIFOLVL_Msk                      (0x01UL << ETHERNET_MAC_DEBUG_TXFIFOLVL_Pos)              /*!< ETHERNET MAC_DEBUG: TXFIFOLVL Mask  */
#define ETHERNET_MAC_DEBUG_TXFIFOFULL_Pos                     25                                                        /*!< ETHERNET MAC_DEBUG: TXFIFOFULL Position */
#define ETHERNET_MAC_DEBUG_TXFIFOFULL_Msk                     (0x01UL << ETHERNET_MAC_DEBUG_TXFIFOFULL_Pos)             /*!< ETHERNET MAC_DEBUG: TXFIFOFULL Mask */

// --------------------------------  ETHERNET_MAC_RWAKE_FRFLT  ------------------------------------
#define ETHERNET_MAC_RWAKE_FRFLT_ADDR_Pos                     0                                                         /*!< ETHERNET MAC_RWAKE_FRFLT: ADDR Position */
#define ETHERNET_MAC_RWAKE_FRFLT_ADDR_Msk                     (0xffffffffUL << ETHERNET_MAC_RWAKE_FRFLT_ADDR_Pos)       /*!< ETHERNET MAC_RWAKE_FRFLT: ADDR Mask */

// -------------------------------  ETHERNET_MAC_PMT_CTRL_STAT  -----------------------------------
#define ETHERNET_MAC_PMT_CTRL_STAT_PD_Pos                     0                                                         /*!< ETHERNET MAC_PMT_CTRL_STAT: PD Position */
#define ETHERNET_MAC_PMT_CTRL_STAT_PD_Msk                     (0x01UL << ETHERNET_MAC_PMT_CTRL_STAT_PD_Pos)             /*!< ETHERNET MAC_PMT_CTRL_STAT: PD Mask */
#define ETHERNET_MAC_PMT_CTRL_STAT_MPE_Pos                    1                                                         /*!< ETHERNET MAC_PMT_CTRL_STAT: MPE Position */
#define ETHERNET_MAC_PMT_CTRL_STAT_MPE_Msk                    (0x01UL << ETHERNET_MAC_PMT_CTRL_STAT_MPE_Pos)            /*!< ETHERNET MAC_PMT_CTRL_STAT: MPE Mask */
#define ETHERNET_MAC_PMT_CTRL_STAT_WFE_Pos                    2                                                         /*!< ETHERNET MAC_PMT_CTRL_STAT: WFE Position */
#define ETHERNET_MAC_PMT_CTRL_STAT_WFE_Msk                    (0x01UL << ETHERNET_MAC_PMT_CTRL_STAT_WFE_Pos)            /*!< ETHERNET MAC_PMT_CTRL_STAT: WFE Mask */
#define ETHERNET_MAC_PMT_CTRL_STAT_MPR_Pos                    5                                                         /*!< ETHERNET MAC_PMT_CTRL_STAT: MPR Position */
#define ETHERNET_MAC_PMT_CTRL_STAT_MPR_Msk                    (0x01UL << ETHERNET_MAC_PMT_CTRL_STAT_MPR_Pos)            /*!< ETHERNET MAC_PMT_CTRL_STAT: MPR Mask */
#define ETHERNET_MAC_PMT_CTRL_STAT_WFR_Pos                    6                                                         /*!< ETHERNET MAC_PMT_CTRL_STAT: WFR Position */
#define ETHERNET_MAC_PMT_CTRL_STAT_WFR_Msk                    (0x01UL << ETHERNET_MAC_PMT_CTRL_STAT_WFR_Pos)            /*!< ETHERNET MAC_PMT_CTRL_STAT: WFR Mask */
#define ETHERNET_MAC_PMT_CTRL_STAT_GU_Pos                     9                                                         /*!< ETHERNET MAC_PMT_CTRL_STAT: GU Position */
#define ETHERNET_MAC_PMT_CTRL_STAT_GU_Msk                     (0x01UL << ETHERNET_MAC_PMT_CTRL_STAT_GU_Pos)             /*!< ETHERNET MAC_PMT_CTRL_STAT: GU Mask */
#define ETHERNET_MAC_PMT_CTRL_STAT_WFFRPR_Pos                 31                                                        /*!< ETHERNET MAC_PMT_CTRL_STAT: WFFRPR Position */
#define ETHERNET_MAC_PMT_CTRL_STAT_WFFRPR_Msk                 (0x01UL << ETHERNET_MAC_PMT_CTRL_STAT_WFFRPR_Pos)         /*!< ETHERNET MAC_PMT_CTRL_STAT: WFFRPR Mask */

// ---------------------------------  ETHERNET_MAC_INTR_MASK  -------------------------------------
#define ETHERNET_MAC_INTR_MASK_PMTMSK_Pos                     3                                                         /*!< ETHERNET MAC_INTR_MASK: PMTMSK Position */
#define ETHERNET_MAC_INTR_MASK_PMTMSK_Msk                     (0x01UL << ETHERNET_MAC_INTR_MASK_PMTMSK_Pos)             /*!< ETHERNET MAC_INTR_MASK: PMTMSK Mask */

// ---------------------------------  ETHERNET_MAC_ADDR0_HIGH  ------------------------------------
#define ETHERNET_MAC_ADDR0_HIGH_A47_32_Pos                    0                                                         /*!< ETHERNET MAC_ADDR0_HIGH: A47_32 Position */
#define ETHERNET_MAC_ADDR0_HIGH_A47_32_Msk                    (0x0000ffffUL << ETHERNET_MAC_ADDR0_HIGH_A47_32_Pos)      /*!< ETHERNET MAC_ADDR0_HIGH: A47_32 Mask */
#define ETHERNET_MAC_ADDR0_HIGH_MO_Pos                        31                                                        /*!< ETHERNET MAC_ADDR0_HIGH: MO Position */
#define ETHERNET_MAC_ADDR0_HIGH_MO_Msk                        (0x01UL << ETHERNET_MAC_ADDR0_HIGH_MO_Pos)                /*!< ETHERNET MAC_ADDR0_HIGH: MO Mask    */

// ---------------------------------  ETHERNET_MAC_ADDR0_LOW  -------------------------------------
#define ETHERNET_MAC_ADDR0_LOW_A31_0_Pos                      0                                                         /*!< ETHERNET MAC_ADDR0_LOW: A31_0 Position */
#define ETHERNET_MAC_ADDR0_LOW_A31_0_Msk                      (0xffffffffUL << ETHERNET_MAC_ADDR0_LOW_A31_0_Pos)        /*!< ETHERNET MAC_ADDR0_LOW: A31_0 Mask  */

// --------------------------------  ETHERNET_MAC_TIMESTP_CTRL  -----------------------------------
#define ETHERNET_MAC_TIMESTP_CTRL_TSENA_Pos                   0                                                         /*!< ETHERNET MAC_TIMESTP_CTRL: TSENA Position */
#define ETHERNET_MAC_TIMESTP_CTRL_TSENA_Msk                   (0x01UL << ETHERNET_MAC_TIMESTP_CTRL_TSENA_Pos)           /*!< ETHERNET MAC_TIMESTP_CTRL: TSENA Mask */
#define ETHERNET_MAC_TIMESTP_CTRL_TSCFUPDT_Pos                1                                                         /*!< ETHERNET MAC_TIMESTP_CTRL: TSCFUPDT Position */
#define ETHERNET_MAC_TIMESTP_CTRL_TSCFUPDT_Msk                (0x01UL << ETHERNET_MAC_TIMESTP_CTRL_TSCFUPDT_Pos)        /*!< ETHERNET MAC_TIMESTP_CTRL: TSCFUPDT Mask */
#define ETHERNET_MAC_TIMESTP_CTRL_TSINIT_Pos                  2                                                         /*!< ETHERNET MAC_TIMESTP_CTRL: TSINIT Position */
#define ETHERNET_MAC_TIMESTP_CTRL_TSINIT_Msk                  (0x01UL << ETHERNET_MAC_TIMESTP_CTRL_TSINIT_Pos)          /*!< ETHERNET MAC_TIMESTP_CTRL: TSINIT Mask */
#define ETHERNET_MAC_TIMESTP_CTRL_TSUPDT_Pos                  3                                                         /*!< ETHERNET MAC_TIMESTP_CTRL: TSUPDT Position */
#define ETHERNET_MAC_TIMESTP_CTRL_TSUPDT_Msk                  (0x01UL << ETHERNET_MAC_TIMESTP_CTRL_TSUPDT_Pos)          /*!< ETHERNET MAC_TIMESTP_CTRL: TSUPDT Mask */
#define ETHERNET_MAC_TIMESTP_CTRL_TSTRIG_Pos                  4                                                         /*!< ETHERNET MAC_TIMESTP_CTRL: TSTRIG Position */
#define ETHERNET_MAC_TIMESTP_CTRL_TSTRIG_Msk                  (0x01UL << ETHERNET_MAC_TIMESTP_CTRL_TSTRIG_Pos)          /*!< ETHERNET MAC_TIMESTP_CTRL: TSTRIG Mask */
#define ETHERNET_MAC_TIMESTP_CTRL_TSADDREG_Pos                5                                                         /*!< ETHERNET MAC_TIMESTP_CTRL: TSADDREG Position */
#define ETHERNET_MAC_TIMESTP_CTRL_TSADDREG_Msk                (0x01UL << ETHERNET_MAC_TIMESTP_CTRL_TSADDREG_Pos)        /*!< ETHERNET MAC_TIMESTP_CTRL: TSADDREG Mask */
#define ETHERNET_MAC_TIMESTP_CTRL_TSENALL_Pos                 8                                                         /*!< ETHERNET MAC_TIMESTP_CTRL: TSENALL Position */
#define ETHERNET_MAC_TIMESTP_CTRL_TSENALL_Msk                 (0x01UL << ETHERNET_MAC_TIMESTP_CTRL_TSENALL_Pos)         /*!< ETHERNET MAC_TIMESTP_CTRL: TSENALL Mask */
#define ETHERNET_MAC_TIMESTP_CTRL_TSCTRLSSR_Pos               9                                                         /*!< ETHERNET MAC_TIMESTP_CTRL: TSCTRLSSR Position */
#define ETHERNET_MAC_TIMESTP_CTRL_TSCTRLSSR_Msk               (0x01UL << ETHERNET_MAC_TIMESTP_CTRL_TSCTRLSSR_Pos)       /*!< ETHERNET MAC_TIMESTP_CTRL: TSCTRLSSR Mask */
#define ETHERNET_MAC_TIMESTP_CTRL_TSVER2ENA_Pos               10                                                        /*!< ETHERNET MAC_TIMESTP_CTRL: TSVER2ENA Position */
#define ETHERNET_MAC_TIMESTP_CTRL_TSVER2ENA_Msk               (0x01UL << ETHERNET_MAC_TIMESTP_CTRL_TSVER2ENA_Pos)       /*!< ETHERNET MAC_TIMESTP_CTRL: TSVER2ENA Mask */
#define ETHERNET_MAC_TIMESTP_CTRL_TSIPENA_Pos                 11                                                        /*!< ETHERNET MAC_TIMESTP_CTRL: TSIPENA Position */
#define ETHERNET_MAC_TIMESTP_CTRL_TSIPENA_Msk                 (0x01UL << ETHERNET_MAC_TIMESTP_CTRL_TSIPENA_Pos)         /*!< ETHERNET MAC_TIMESTP_CTRL: TSIPENA Mask */
#define ETHERNET_MAC_TIMESTP_CTRL_TSIPV6ENA_Pos               12                                                        /*!< ETHERNET MAC_TIMESTP_CTRL: TSIPV6ENA Position */
#define ETHERNET_MAC_TIMESTP_CTRL_TSIPV6ENA_Msk               (0x01UL << ETHERNET_MAC_TIMESTP_CTRL_TSIPV6ENA_Pos)       /*!< ETHERNET MAC_TIMESTP_CTRL: TSIPV6ENA Mask */
#define ETHERNET_MAC_TIMESTP_CTRL_TSIPV4ENA_Pos               13                                                        /*!< ETHERNET MAC_TIMESTP_CTRL: TSIPV4ENA Position */
#define ETHERNET_MAC_TIMESTP_CTRL_TSIPV4ENA_Msk               (0x01UL << ETHERNET_MAC_TIMESTP_CTRL_TSIPV4ENA_Pos)       /*!< ETHERNET MAC_TIMESTP_CTRL: TSIPV4ENA Mask */
#define ETHERNET_MAC_TIMESTP_CTRL_TSEVNTENA_Pos               14                                                        /*!< ETHERNET MAC_TIMESTP_CTRL: TSEVNTENA Position */
#define ETHERNET_MAC_TIMESTP_CTRL_TSEVNTENA_Msk               (0x01UL << ETHERNET_MAC_TIMESTP_CTRL_TSEVNTENA_Pos)       /*!< ETHERNET MAC_TIMESTP_CTRL: TSEVNTENA Mask */
#define ETHERNET_MAC_TIMESTP_CTRL_TSMSTRENA_Pos               15                                                        /*!< ETHERNET MAC_TIMESTP_CTRL: TSMSTRENA Position */
#define ETHERNET_MAC_TIMESTP_CTRL_TSMSTRENA_Msk               (0x01UL << ETHERNET_MAC_TIMESTP_CTRL_TSMSTRENA_Pos)       /*!< ETHERNET MAC_TIMESTP_CTRL: TSMSTRENA Mask */
#define ETHERNET_MAC_TIMESTP_CTRL_TSCLKTYPE_Pos               16                                                        /*!< ETHERNET MAC_TIMESTP_CTRL: TSCLKTYPE Position */
#define ETHERNET_MAC_TIMESTP_CTRL_TSCLKTYPE_Msk               (0x03UL << ETHERNET_MAC_TIMESTP_CTRL_TSCLKTYPE_Pos)       /*!< ETHERNET MAC_TIMESTP_CTRL: TSCLKTYPE Mask */
#define ETHERNET_MAC_TIMESTP_CTRL_TSENMACADDR_Pos             18                                                        /*!< ETHERNET MAC_TIMESTP_CTRL: TSENMACADDR Position */
#define ETHERNET_MAC_TIMESTP_CTRL_TSENMACADDR_Msk             (0x01UL << ETHERNET_MAC_TIMESTP_CTRL_TSENMACADDR_Pos)     /*!< ETHERNET MAC_TIMESTP_CTRL: TSENMACADDR Mask */

// ---------------------------------  ETHERNET_SUBSECOND_INCR  ------------------------------------
#define ETHERNET_SUBSECOND_INCR_SSINC_Pos                     0                                                         /*!< ETHERNET SUBSECOND_INCR: SSINC Position */
#define ETHERNET_SUBSECOND_INCR_SSINC_Msk                     (0x000000ffUL << ETHERNET_SUBSECOND_INCR_SSINC_Pos)       /*!< ETHERNET SUBSECOND_INCR: SSINC Mask */

// ------------------------------------  ETHERNET_SECONDS  ----------------------------------------
#define ETHERNET_SECONDS_TSS_Pos                              0                                                         /*!< ETHERNET SECONDS: TSS Position      */
#define ETHERNET_SECONDS_TSS_Msk                              (0xffffffffUL << ETHERNET_SECONDS_TSS_Pos)                /*!< ETHERNET SECONDS: TSS Mask          */

// ----------------------------------  ETHERNET_NANOSECONDS  --------------------------------------
#define ETHERNET_NANOSECONDS_TSSS_Pos                         0                                                         /*!< ETHERNET NANOSECONDS: TSSS Position */
#define ETHERNET_NANOSECONDS_TSSS_Msk                         (0x7fffffffUL << ETHERNET_NANOSECONDS_TSSS_Pos)           /*!< ETHERNET NANOSECONDS: TSSS Mask     */
#define ETHERNET_NANOSECONDS_PSNT_Pos                         31                                                        /*!< ETHERNET NANOSECONDS: PSNT Position */
#define ETHERNET_NANOSECONDS_PSNT_Msk                         (0x01UL << ETHERNET_NANOSECONDS_PSNT_Pos)                 /*!< ETHERNET NANOSECONDS: PSNT Mask     */

// ---------------------------------  ETHERNET_SECONDSUPDATE  -------------------------------------
#define ETHERNET_SECONDSUPDATE_TSS_Pos                        0                                                         /*!< ETHERNET SECONDSUPDATE: TSS Position */
#define ETHERNET_SECONDSUPDATE_TSS_Msk                        (0xffffffffUL << ETHERNET_SECONDSUPDATE_TSS_Pos)          /*!< ETHERNET SECONDSUPDATE: TSS Mask    */

// -------------------------------  ETHERNET_NANOSECONDSUPDATE  -----------------------------------
#define ETHERNET_NANOSECONDSUPDATE_TSSS_Pos                   0                                                         /*!< ETHERNET NANOSECONDSUPDATE: TSSS Position */
#define ETHERNET_NANOSECONDSUPDATE_TSSS_Msk                   (0x7fffffffUL << ETHERNET_NANOSECONDSUPDATE_TSSS_Pos)     /*!< ETHERNET NANOSECONDSUPDATE: TSSS Mask */
#define ETHERNET_NANOSECONDSUPDATE_ADDSUB_Pos                 31                                                        /*!< ETHERNET NANOSECONDSUPDATE: ADDSUB Position */
#define ETHERNET_NANOSECONDSUPDATE_ADDSUB_Msk                 (0x01UL << ETHERNET_NANOSECONDSUPDATE_ADDSUB_Pos)         /*!< ETHERNET NANOSECONDSUPDATE: ADDSUB Mask */

// -------------------------------------  ETHERNET_ADDEND  ----------------------------------------
#define ETHERNET_ADDEND_TSAR_Pos                              0                                                         /*!< ETHERNET ADDEND: TSAR Position      */
#define ETHERNET_ADDEND_TSAR_Msk                              (0xffffffffUL << ETHERNET_ADDEND_TSAR_Pos)                /*!< ETHERNET ADDEND: TSAR Mask          */

// ---------------------------------  ETHERNET_TARGETSECONDS  -------------------------------------
#define ETHERNET_TARGETSECONDS_TSTR_Pos                       0                                                         /*!< ETHERNET TARGETSECONDS: TSTR Position */
#define ETHERNET_TARGETSECONDS_TSTR_Msk                       (0xffffffffUL << ETHERNET_TARGETSECONDS_TSTR_Pos)         /*!< ETHERNET TARGETSECONDS: TSTR Mask   */

// -------------------------------  ETHERNET_TARGETNANOSECONDS  -----------------------------------
#define ETHERNET_TARGETNANOSECONDS_TSTR_Pos                   0                                                         /*!< ETHERNET TARGETNANOSECONDS: TSTR Position */
#define ETHERNET_TARGETNANOSECONDS_TSTR_Msk                   (0x7fffffffUL << ETHERNET_TARGETNANOSECONDS_TSTR_Pos)     /*!< ETHERNET TARGETNANOSECONDS: TSTR Mask */

// ------------------------------------  ETHERNET_HIGHWORD  ---------------------------------------
#define ETHERNET_HIGHWORD_TSHWR_Pos                           0                                                         /*!< ETHERNET HIGHWORD: TSHWR Position   */
#define ETHERNET_HIGHWORD_TSHWR_Msk                           (0x0000ffffUL << ETHERNET_HIGHWORD_TSHWR_Pos)             /*!< ETHERNET HIGHWORD: TSHWR Mask       */

// ---------------------------------  ETHERNET_TIMESTAMPSTAT  -------------------------------------
#define ETHERNET_TIMESTAMPSTAT_TSSOVF_Pos                     0                                                         /*!< ETHERNET TIMESTAMPSTAT: TSSOVF Position */
#define ETHERNET_TIMESTAMPSTAT_TSSOVF_Msk                     (0x01UL << ETHERNET_TIMESTAMPSTAT_TSSOVF_Pos)             /*!< ETHERNET TIMESTAMPSTAT: TSSOVF Mask */
#define ETHERNET_TIMESTAMPSTAT_TSTARGT_Pos                    1                                                         /*!< ETHERNET TIMESTAMPSTAT: TSTARGT Position */
#define ETHERNET_TIMESTAMPSTAT_TSTARGT_Msk                    (0x01UL << ETHERNET_TIMESTAMPSTAT_TSTARGT_Pos)            /*!< ETHERNET TIMESTAMPSTAT: TSTARGT Mask */
#define ETHERNET_TIMESTAMPSTAT_AUXSS_Pos                      2                                                         /*!< ETHERNET TIMESTAMPSTAT: AUXSS Position */
#define ETHERNET_TIMESTAMPSTAT_AUXSS_Msk                      (0x01UL << ETHERNET_TIMESTAMPSTAT_AUXSS_Pos)              /*!< ETHERNET TIMESTAMPSTAT: AUXSS Mask  */
#define ETHERNET_TIMESTAMPSTAT_ATSSTM_Pos                     24                                                        /*!< ETHERNET TIMESTAMPSTAT: ATSSTM Position */
#define ETHERNET_TIMESTAMPSTAT_ATSSTM_Msk                     (0x01UL << ETHERNET_TIMESTAMPSTAT_ATSSTM_Pos)             /*!< ETHERNET TIMESTAMPSTAT: ATSSTM Mask */
#define ETHERNET_TIMESTAMPSTAT_ATSNS_Pos                      25                                                        /*!< ETHERNET TIMESTAMPSTAT: ATSNS Position */
#define ETHERNET_TIMESTAMPSTAT_ATSNS_Msk                      (0x07UL << ETHERNET_TIMESTAMPSTAT_ATSNS_Pos)              /*!< ETHERNET TIMESTAMPSTAT: ATSNS Mask  */

// ------------------------------------  ETHERNET_PPSCTRL  ----------------------------------------
#define ETHERNET_PPSCTRL_PPSCTRL_Pos                          0                                                         /*!< ETHERNET PPSCTRL: PPSCTRL Position  */
#define ETHERNET_PPSCTRL_PPSCTRL_Msk                          (0x0fUL << ETHERNET_PPSCTRL_PPSCTRL_Pos)                  /*!< ETHERNET PPSCTRL: PPSCTRL Mask      */

// ---------------------------------  ETHERNET_AUXNANOSECONDS  ------------------------------------
#define ETHERNET_AUXNANOSECONDS_AUXNS_Pos                     0                                                         /*!< ETHERNET AUXNANOSECONDS: AUXNS Position */
#define ETHERNET_AUXNANOSECONDS_AUXNS_Msk                     (0xffffffffUL << ETHERNET_AUXNANOSECONDS_AUXNS_Pos)       /*!< ETHERNET AUXNANOSECONDS: AUXNS Mask */

// -----------------------------------  ETHERNET_AUXSECONDS  --------------------------------------
#define ETHERNET_AUXSECONDS_AUXS_Pos                          0                                                         /*!< ETHERNET AUXSECONDS: AUXS Position  */
#define ETHERNET_AUXSECONDS_AUXS_Msk                          (0xffffffffUL << ETHERNET_AUXSECONDS_AUXS_Pos)            /*!< ETHERNET AUXSECONDS: AUXS Mask      */

// ----------------------------------  ETHERNET_DMA_BUS_MODE  -------------------------------------
#define ETHERNET_DMA_BUS_MODE_SWR_Pos                         0                                                         /*!< ETHERNET DMA_BUS_MODE: SWR Position */
#define ETHERNET_DMA_BUS_MODE_SWR_Msk                         (0x01UL << ETHERNET_DMA_BUS_MODE_SWR_Pos)                 /*!< ETHERNET DMA_BUS_MODE: SWR Mask     */
#define ETHERNET_DMA_BUS_MODE_DA_Pos                          1                                                         /*!< ETHERNET DMA_BUS_MODE: DA Position  */
#define ETHERNET_DMA_BUS_MODE_DA_Msk                          (0x01UL << ETHERNET_DMA_BUS_MODE_DA_Pos)                  /*!< ETHERNET DMA_BUS_MODE: DA Mask      */
#define ETHERNET_DMA_BUS_MODE_DSL_Pos                         2                                                         /*!< ETHERNET DMA_BUS_MODE: DSL Position */
#define ETHERNET_DMA_BUS_MODE_DSL_Msk                         (0x1fUL << ETHERNET_DMA_BUS_MODE_DSL_Pos)                 /*!< ETHERNET DMA_BUS_MODE: DSL Mask     */
#define ETHERNET_DMA_BUS_MODE_ATDS_Pos                        7                                                         /*!< ETHERNET DMA_BUS_MODE: ATDS Position */
#define ETHERNET_DMA_BUS_MODE_ATDS_Msk                        (0x01UL << ETHERNET_DMA_BUS_MODE_ATDS_Pos)                /*!< ETHERNET DMA_BUS_MODE: ATDS Mask    */
#define ETHERNET_DMA_BUS_MODE_PBL_Pos                         8                                                         /*!< ETHERNET DMA_BUS_MODE: PBL Position */
#define ETHERNET_DMA_BUS_MODE_PBL_Msk                         (0x3fUL << ETHERNET_DMA_BUS_MODE_PBL_Pos)                 /*!< ETHERNET DMA_BUS_MODE: PBL Mask     */
#define ETHERNET_DMA_BUS_MODE_PR_Pos                          14                                                        /*!< ETHERNET DMA_BUS_MODE: PR Position  */
#define ETHERNET_DMA_BUS_MODE_PR_Msk                          (0x03UL << ETHERNET_DMA_BUS_MODE_PR_Pos)                  /*!< ETHERNET DMA_BUS_MODE: PR Mask      */
#define ETHERNET_DMA_BUS_MODE_FB_Pos                          16                                                        /*!< ETHERNET DMA_BUS_MODE: FB Position  */
#define ETHERNET_DMA_BUS_MODE_FB_Msk                          (0x01UL << ETHERNET_DMA_BUS_MODE_FB_Pos)                  /*!< ETHERNET DMA_BUS_MODE: FB Mask      */
#define ETHERNET_DMA_BUS_MODE_RPBL_Pos                        17                                                        /*!< ETHERNET DMA_BUS_MODE: RPBL Position */
#define ETHERNET_DMA_BUS_MODE_RPBL_Msk                        (0x3fUL << ETHERNET_DMA_BUS_MODE_RPBL_Pos)                /*!< ETHERNET DMA_BUS_MODE: RPBL Mask    */
#define ETHERNET_DMA_BUS_MODE_USP_Pos                         23                                                        /*!< ETHERNET DMA_BUS_MODE: USP Position */
#define ETHERNET_DMA_BUS_MODE_USP_Msk                         (0x01UL << ETHERNET_DMA_BUS_MODE_USP_Pos)                 /*!< ETHERNET DMA_BUS_MODE: USP Mask     */
#define ETHERNET_DMA_BUS_MODE_PBL8X_Pos                       24                                                        /*!< ETHERNET DMA_BUS_MODE: PBL8X Position */
#define ETHERNET_DMA_BUS_MODE_PBL8X_Msk                       (0x01UL << ETHERNET_DMA_BUS_MODE_PBL8X_Pos)               /*!< ETHERNET DMA_BUS_MODE: PBL8X Mask   */
#define ETHERNET_DMA_BUS_MODE_AAL_Pos                         25                                                        /*!< ETHERNET DMA_BUS_MODE: AAL Position */
#define ETHERNET_DMA_BUS_MODE_AAL_Msk                         (0x01UL << ETHERNET_DMA_BUS_MODE_AAL_Pos)                 /*!< ETHERNET DMA_BUS_MODE: AAL Mask     */
#define ETHERNET_DMA_BUS_MODE_MB_Pos                          26                                                        /*!< ETHERNET DMA_BUS_MODE: MB Position  */
#define ETHERNET_DMA_BUS_MODE_MB_Msk                          (0x01UL << ETHERNET_DMA_BUS_MODE_MB_Pos)                  /*!< ETHERNET DMA_BUS_MODE: MB Mask      */
#define ETHERNET_DMA_BUS_MODE_TXPR_Pos                        27                                                        /*!< ETHERNET DMA_BUS_MODE: TXPR Position */
#define ETHERNET_DMA_BUS_MODE_TXPR_Msk                        (0x01UL << ETHERNET_DMA_BUS_MODE_TXPR_Pos)                /*!< ETHERNET DMA_BUS_MODE: TXPR Mask    */

// -----------------------------  ETHERNET_DMA_TRANS_POLL_DEMAND  ---------------------------------
#define ETHERNET_DMA_TRANS_POLL_DEMAND_TPD_Pos                0                                                         /*!< ETHERNET DMA_TRANS_POLL_DEMAND: TPD Position */
#define ETHERNET_DMA_TRANS_POLL_DEMAND_TPD_Msk                (0xffffffffUL << ETHERNET_DMA_TRANS_POLL_DEMAND_TPD_Pos)  /*!< ETHERNET DMA_TRANS_POLL_DEMAND: TPD Mask */

// ------------------------------  ETHERNET_DMA_REC_POLL_DEMAND  ----------------------------------
#define ETHERNET_DMA_REC_POLL_DEMAND_RPD_Pos                  0                                                         /*!< ETHERNET DMA_REC_POLL_DEMAND: RPD Position */
#define ETHERNET_DMA_REC_POLL_DEMAND_RPD_Msk                  (0xffffffffUL << ETHERNET_DMA_REC_POLL_DEMAND_RPD_Pos)    /*!< ETHERNET DMA_REC_POLL_DEMAND: RPD Mask */

// --------------------------------  ETHERNET_DMA_REC_DES_ADDR  -----------------------------------
#define ETHERNET_DMA_REC_DES_ADDR_SRL_Pos                     0                                                         /*!< ETHERNET DMA_REC_DES_ADDR: SRL Position */
#define ETHERNET_DMA_REC_DES_ADDR_SRL_Msk                     (0xffffffffUL << ETHERNET_DMA_REC_DES_ADDR_SRL_Pos)       /*!< ETHERNET DMA_REC_DES_ADDR: SRL Mask */

// -------------------------------  ETHERNET_DMA_TRANS_DES_ADDR  ----------------------------------
#define ETHERNET_DMA_TRANS_DES_ADDR_SRL_Pos                   0                                                         /*!< ETHERNET DMA_TRANS_DES_ADDR: SRL Position */
#define ETHERNET_DMA_TRANS_DES_ADDR_SRL_Msk                   (0xffffffffUL << ETHERNET_DMA_TRANS_DES_ADDR_SRL_Pos)     /*!< ETHERNET DMA_TRANS_DES_ADDR: SRL Mask */

// ------------------------------------  ETHERNET_DMA_STAT  ---------------------------------------
#define ETHERNET_DMA_STAT_TI_Pos                              0                                                         /*!< ETHERNET DMA_STAT: TI Position      */
#define ETHERNET_DMA_STAT_TI_Msk                              (0x01UL << ETHERNET_DMA_STAT_TI_Pos)                      /*!< ETHERNET DMA_STAT: TI Mask          */
#define ETHERNET_DMA_STAT_TPS_Pos                             1                                                         /*!< ETHERNET DMA_STAT: TPS Position     */
#define ETHERNET_DMA_STAT_TPS_Msk                             (0x01UL << ETHERNET_DMA_STAT_TPS_Pos)                     /*!< ETHERNET DMA_STAT: TPS Mask         */
#define ETHERNET_DMA_STAT_TU_Pos                              2                                                         /*!< ETHERNET DMA_STAT: TU Position      */
#define ETHERNET_DMA_STAT_TU_Msk                              (0x01UL << ETHERNET_DMA_STAT_TU_Pos)                      /*!< ETHERNET DMA_STAT: TU Mask          */
#define ETHERNET_DMA_STAT_TJT_Pos                             3                                                         /*!< ETHERNET DMA_STAT: TJT Position     */
#define ETHERNET_DMA_STAT_TJT_Msk                             (0x01UL << ETHERNET_DMA_STAT_TJT_Pos)                     /*!< ETHERNET DMA_STAT: TJT Mask         */
#define ETHERNET_DMA_STAT_OVF_Pos                             4                                                         /*!< ETHERNET DMA_STAT: OVF Position     */
#define ETHERNET_DMA_STAT_OVF_Msk                             (0x01UL << ETHERNET_DMA_STAT_OVF_Pos)                     /*!< ETHERNET DMA_STAT: OVF Mask         */
#define ETHERNET_DMA_STAT_UNF_Pos                             5                                                         /*!< ETHERNET DMA_STAT: UNF Position     */
#define ETHERNET_DMA_STAT_UNF_Msk                             (0x01UL << ETHERNET_DMA_STAT_UNF_Pos)                     /*!< ETHERNET DMA_STAT: UNF Mask         */
#define ETHERNET_DMA_STAT_RI_Pos                              6                                                         /*!< ETHERNET DMA_STAT: RI Position      */
#define ETHERNET_DMA_STAT_RI_Msk                              (0x01UL << ETHERNET_DMA_STAT_RI_Pos)                      /*!< ETHERNET DMA_STAT: RI Mask          */
#define ETHERNET_DMA_STAT_RU_Pos                              7                                                         /*!< ETHERNET DMA_STAT: RU Position      */
#define ETHERNET_DMA_STAT_RU_Msk                              (0x01UL << ETHERNET_DMA_STAT_RU_Pos)                      /*!< ETHERNET DMA_STAT: RU Mask          */
#define ETHERNET_DMA_STAT_RPS_Pos                             8                                                         /*!< ETHERNET DMA_STAT: RPS Position     */
#define ETHERNET_DMA_STAT_RPS_Msk                             (0x01UL << ETHERNET_DMA_STAT_RPS_Pos)                     /*!< ETHERNET DMA_STAT: RPS Mask         */
#define ETHERNET_DMA_STAT_RWT_Pos                             9                                                         /*!< ETHERNET DMA_STAT: RWT Position     */
#define ETHERNET_DMA_STAT_RWT_Msk                             (0x01UL << ETHERNET_DMA_STAT_RWT_Pos)                     /*!< ETHERNET DMA_STAT: RWT Mask         */
#define ETHERNET_DMA_STAT_ETI_Pos                             10                                                        /*!< ETHERNET DMA_STAT: ETI Position     */
#define ETHERNET_DMA_STAT_ETI_Msk                             (0x01UL << ETHERNET_DMA_STAT_ETI_Pos)                     /*!< ETHERNET DMA_STAT: ETI Mask         */
#define ETHERNET_DMA_STAT_FBI_Pos                             13                                                        /*!< ETHERNET DMA_STAT: FBI Position     */
#define ETHERNET_DMA_STAT_FBI_Msk                             (0x01UL << ETHERNET_DMA_STAT_FBI_Pos)                     /*!< ETHERNET DMA_STAT: FBI Mask         */
#define ETHERNET_DMA_STAT_ERI_Pos                             14                                                        /*!< ETHERNET DMA_STAT: ERI Position     */
#define ETHERNET_DMA_STAT_ERI_Msk                             (0x01UL << ETHERNET_DMA_STAT_ERI_Pos)                     /*!< ETHERNET DMA_STAT: ERI Mask         */
#define ETHERNET_DMA_STAT_AIE_Pos                             15                                                        /*!< ETHERNET DMA_STAT: AIE Position     */
#define ETHERNET_DMA_STAT_AIE_Msk                             (0x01UL << ETHERNET_DMA_STAT_AIE_Pos)                     /*!< ETHERNET DMA_STAT: AIE Mask         */
#define ETHERNET_DMA_STAT_NIS_Pos                             16                                                        /*!< ETHERNET DMA_STAT: NIS Position     */
#define ETHERNET_DMA_STAT_NIS_Msk                             (0x01UL << ETHERNET_DMA_STAT_NIS_Pos)                     /*!< ETHERNET DMA_STAT: NIS Mask         */

// ----------------------------------  ETHERNET_DMA_OP_MODE  --------------------------------------
#define ETHERNET_DMA_OP_MODE_SR_Pos                           1                                                         /*!< ETHERNET DMA_OP_MODE: SR Position   */
#define ETHERNET_DMA_OP_MODE_SR_Msk                           (0x01UL << ETHERNET_DMA_OP_MODE_SR_Pos)                   /*!< ETHERNET DMA_OP_MODE: SR Mask       */
#define ETHERNET_DMA_OP_MODE_OSF_Pos                          2                                                         /*!< ETHERNET DMA_OP_MODE: OSF Position  */
#define ETHERNET_DMA_OP_MODE_OSF_Msk                          (0x01UL << ETHERNET_DMA_OP_MODE_OSF_Pos)                  /*!< ETHERNET DMA_OP_MODE: OSF Mask      */
#define ETHERNET_DMA_OP_MODE_RTC_Pos                          3                                                         /*!< ETHERNET DMA_OP_MODE: RTC Position  */
#define ETHERNET_DMA_OP_MODE_RTC_Msk                          (0x03UL << ETHERNET_DMA_OP_MODE_RTC_Pos)                  /*!< ETHERNET DMA_OP_MODE: RTC Mask      */
#define ETHERNET_DMA_OP_MODE_FUF_Pos                          6                                                         /*!< ETHERNET DMA_OP_MODE: FUF Position  */
#define ETHERNET_DMA_OP_MODE_FUF_Msk                          (0x01UL << ETHERNET_DMA_OP_MODE_FUF_Pos)                  /*!< ETHERNET DMA_OP_MODE: FUF Mask      */
#define ETHERNET_DMA_OP_MODE_FEF_Pos                          7                                                         /*!< ETHERNET DMA_OP_MODE: FEF Position  */
#define ETHERNET_DMA_OP_MODE_FEF_Msk                          (0x01UL << ETHERNET_DMA_OP_MODE_FEF_Pos)                  /*!< ETHERNET DMA_OP_MODE: FEF Mask      */
#define ETHERNET_DMA_OP_MODE_ST_Pos                           13                                                        /*!< ETHERNET DMA_OP_MODE: ST Position   */
#define ETHERNET_DMA_OP_MODE_ST_Msk                           (0x01UL << ETHERNET_DMA_OP_MODE_ST_Pos)                   /*!< ETHERNET DMA_OP_MODE: ST Mask       */
#define ETHERNET_DMA_OP_MODE_TTC_Pos                          14                                                        /*!< ETHERNET DMA_OP_MODE: TTC Position  */
#define ETHERNET_DMA_OP_MODE_TTC_Msk                          (0x07UL << ETHERNET_DMA_OP_MODE_TTC_Pos)                  /*!< ETHERNET DMA_OP_MODE: TTC Mask      */
#define ETHERNET_DMA_OP_MODE_FTF_Pos                          20                                                        /*!< ETHERNET DMA_OP_MODE: FTF Position  */
#define ETHERNET_DMA_OP_MODE_FTF_Msk                          (0x01UL << ETHERNET_DMA_OP_MODE_FTF_Pos)                  /*!< ETHERNET DMA_OP_MODE: FTF Mask      */
#define ETHERNET_DMA_OP_MODE_TSF_Pos                          21                                                        /*!< ETHERNET DMA_OP_MODE: TSF Position  */
#define ETHERNET_DMA_OP_MODE_TSF_Msk                          (0x01UL << ETHERNET_DMA_OP_MODE_TSF_Pos)                  /*!< ETHERNET DMA_OP_MODE: TSF Mask      */
#define ETHERNET_DMA_OP_MODE_DFF_Pos                          24                                                        /*!< ETHERNET DMA_OP_MODE: DFF Position  */
#define ETHERNET_DMA_OP_MODE_DFF_Msk                          (0x01UL << ETHERNET_DMA_OP_MODE_DFF_Pos)                  /*!< ETHERNET DMA_OP_MODE: DFF Mask      */
#define ETHERNET_DMA_OP_MODE_RSF_Pos                          25                                                        /*!< ETHERNET DMA_OP_MODE: RSF Position  */
#define ETHERNET_DMA_OP_MODE_RSF_Msk                          (0x01UL << ETHERNET_DMA_OP_MODE_RSF_Pos)                  /*!< ETHERNET DMA_OP_MODE: RSF Mask      */
#define ETHERNET_DMA_OP_MODE_DT_Pos                           26                                                        /*!< ETHERNET DMA_OP_MODE: DT Position   */
#define ETHERNET_DMA_OP_MODE_DT_Msk                           (0x01UL << ETHERNET_DMA_OP_MODE_DT_Pos)                   /*!< ETHERNET DMA_OP_MODE: DT Mask       */

// -----------------------------------  ETHERNET_DMA_INT_EN  --------------------------------------
#define ETHERNET_DMA_INT_EN_TIE_Pos                           0                                                         /*!< ETHERNET DMA_INT_EN: TIE Position   */
#define ETHERNET_DMA_INT_EN_TIE_Msk                           (0x01UL << ETHERNET_DMA_INT_EN_TIE_Pos)                   /*!< ETHERNET DMA_INT_EN: TIE Mask       */
#define ETHERNET_DMA_INT_EN_TSE_Pos                           1                                                         /*!< ETHERNET DMA_INT_EN: TSE Position   */
#define ETHERNET_DMA_INT_EN_TSE_Msk                           (0x01UL << ETHERNET_DMA_INT_EN_TSE_Pos)                   /*!< ETHERNET DMA_INT_EN: TSE Mask       */
#define ETHERNET_DMA_INT_EN_TUE_Pos                           2                                                         /*!< ETHERNET DMA_INT_EN: TUE Position   */
#define ETHERNET_DMA_INT_EN_TUE_Msk                           (0x01UL << ETHERNET_DMA_INT_EN_TUE_Pos)                   /*!< ETHERNET DMA_INT_EN: TUE Mask       */
#define ETHERNET_DMA_INT_EN_TJE_Pos                           3                                                         /*!< ETHERNET DMA_INT_EN: TJE Position   */
#define ETHERNET_DMA_INT_EN_TJE_Msk                           (0x01UL << ETHERNET_DMA_INT_EN_TJE_Pos)                   /*!< ETHERNET DMA_INT_EN: TJE Mask       */
#define ETHERNET_DMA_INT_EN_OVE_Pos                           4                                                         /*!< ETHERNET DMA_INT_EN: OVE Position   */
#define ETHERNET_DMA_INT_EN_OVE_Msk                           (0x01UL << ETHERNET_DMA_INT_EN_OVE_Pos)                   /*!< ETHERNET DMA_INT_EN: OVE Mask       */
#define ETHERNET_DMA_INT_EN_UNE_Pos                           5                                                         /*!< ETHERNET DMA_INT_EN: UNE Position   */
#define ETHERNET_DMA_INT_EN_UNE_Msk                           (0x01UL << ETHERNET_DMA_INT_EN_UNE_Pos)                   /*!< ETHERNET DMA_INT_EN: UNE Mask       */
#define ETHERNET_DMA_INT_EN_RIE_Pos                           6                                                         /*!< ETHERNET DMA_INT_EN: RIE Position   */
#define ETHERNET_DMA_INT_EN_RIE_Msk                           (0x01UL << ETHERNET_DMA_INT_EN_RIE_Pos)                   /*!< ETHERNET DMA_INT_EN: RIE Mask       */
#define ETHERNET_DMA_INT_EN_RUE_Pos                           7                                                         /*!< ETHERNET DMA_INT_EN: RUE Position   */
#define ETHERNET_DMA_INT_EN_RUE_Msk                           (0x01UL << ETHERNET_DMA_INT_EN_RUE_Pos)                   /*!< ETHERNET DMA_INT_EN: RUE Mask       */
#define ETHERNET_DMA_INT_EN_RSE_Pos                           8                                                         /*!< ETHERNET DMA_INT_EN: RSE Position   */
#define ETHERNET_DMA_INT_EN_RSE_Msk                           (0x01UL << ETHERNET_DMA_INT_EN_RSE_Pos)                   /*!< ETHERNET DMA_INT_EN: RSE Mask       */
#define ETHERNET_DMA_INT_EN_RWE_Pos                           9                                                         /*!< ETHERNET DMA_INT_EN: RWE Position   */
#define ETHERNET_DMA_INT_EN_RWE_Msk                           (0x01UL << ETHERNET_DMA_INT_EN_RWE_Pos)                   /*!< ETHERNET DMA_INT_EN: RWE Mask       */
#define ETHERNET_DMA_INT_EN_ETE_Pos                           10                                                        /*!< ETHERNET DMA_INT_EN: ETE Position   */
#define ETHERNET_DMA_INT_EN_ETE_Msk                           (0x01UL << ETHERNET_DMA_INT_EN_ETE_Pos)                   /*!< ETHERNET DMA_INT_EN: ETE Mask       */
#define ETHERNET_DMA_INT_EN_FBE_Pos                           13                                                        /*!< ETHERNET DMA_INT_EN: FBE Position   */
#define ETHERNET_DMA_INT_EN_FBE_Msk                           (0x01UL << ETHERNET_DMA_INT_EN_FBE_Pos)                   /*!< ETHERNET DMA_INT_EN: FBE Mask       */
#define ETHERNET_DMA_INT_EN_ERE_Pos                           14                                                        /*!< ETHERNET DMA_INT_EN: ERE Position   */
#define ETHERNET_DMA_INT_EN_ERE_Msk                           (0x01UL << ETHERNET_DMA_INT_EN_ERE_Pos)                   /*!< ETHERNET DMA_INT_EN: ERE Mask       */
#define ETHERNET_DMA_INT_EN_AIE_Pos                           15                                                        /*!< ETHERNET DMA_INT_EN: AIE Position   */
#define ETHERNET_DMA_INT_EN_AIE_Msk                           (0x01UL << ETHERNET_DMA_INT_EN_AIE_Pos)                   /*!< ETHERNET DMA_INT_EN: AIE Mask       */
#define ETHERNET_DMA_INT_EN_NIE_Pos                           16                                                        /*!< ETHERNET DMA_INT_EN: NIE Position   */
#define ETHERNET_DMA_INT_EN_NIE_Msk                           (0x01UL << ETHERNET_DMA_INT_EN_NIE_Pos)                   /*!< ETHERNET DMA_INT_EN: NIE Mask       */

// ---------------------------------  ETHERNET_DMA_MFRM_BUFOF  ------------------------------------
#define ETHERNET_DMA_MFRM_BUFOF_FMC_Pos                       0                                                         /*!< ETHERNET DMA_MFRM_BUFOF: FMC Position */
#define ETHERNET_DMA_MFRM_BUFOF_FMC_Msk                       (0x0000ffffUL << ETHERNET_DMA_MFRM_BUFOF_FMC_Pos)         /*!< ETHERNET DMA_MFRM_BUFOF: FMC Mask   */
#define ETHERNET_DMA_MFRM_BUFOF_OC_Pos                        16                                                        /*!< ETHERNET DMA_MFRM_BUFOF: OC Position */
#define ETHERNET_DMA_MFRM_BUFOF_OC_Msk                        (0x01UL << ETHERNET_DMA_MFRM_BUFOF_OC_Pos)                /*!< ETHERNET DMA_MFRM_BUFOF: OC Mask    */
#define ETHERNET_DMA_MFRM_BUFOF_FMA_Pos                       17                                                        /*!< ETHERNET DMA_MFRM_BUFOF: FMA Position */
#define ETHERNET_DMA_MFRM_BUFOF_FMA_Msk                       (0x000007ffUL << ETHERNET_DMA_MFRM_BUFOF_FMA_Pos)         /*!< ETHERNET DMA_MFRM_BUFOF: FMA Mask   */
#define ETHERNET_DMA_MFRM_BUFOF_OF_Pos                        28                                                        /*!< ETHERNET DMA_MFRM_BUFOF: OF Position */
#define ETHERNET_DMA_MFRM_BUFOF_OF_Msk                        (0x01UL << ETHERNET_DMA_MFRM_BUFOF_OF_Pos)                /*!< ETHERNET DMA_MFRM_BUFOF: OF Mask    */

// --------------------------------  ETHERNET_DMA_REC_INT_WDT  ------------------------------------
#define ETHERNET_DMA_REC_INT_WDT_RIWT_Pos                     0                                                         /*!< ETHERNET DMA_REC_INT_WDT: RIWT Position */
#define ETHERNET_DMA_REC_INT_WDT_RIWT_Msk                     (0x000000ffUL << ETHERNET_DMA_REC_INT_WDT_RIWT_Pos)       /*!< ETHERNET DMA_REC_INT_WDT: RIWT Mask */

// -----------------------------  ETHERNET_DMA_CURHOST_TRANS_DES  ---------------------------------
#define ETHERNET_DMA_CURHOST_TRANS_DES_HTD_Pos                0                                                         /*!< ETHERNET DMA_CURHOST_TRANS_DES: HTD Position */
#define ETHERNET_DMA_CURHOST_TRANS_DES_HTD_Msk                (0xffffffffUL << ETHERNET_DMA_CURHOST_TRANS_DES_HTD_Pos)  /*!< ETHERNET DMA_CURHOST_TRANS_DES: HTD Mask */

// ------------------------------  ETHERNET_DMA_CURHOST_REC_DES  ----------------------------------
#define ETHERNET_DMA_CURHOST_REC_DES_HRD_Pos                  0                                                         /*!< ETHERNET DMA_CURHOST_REC_DES: HRD Position */
#define ETHERNET_DMA_CURHOST_REC_DES_HRD_Msk                  (0xffffffffUL << ETHERNET_DMA_CURHOST_REC_DES_HRD_Pos)    /*!< ETHERNET DMA_CURHOST_REC_DES: HRD Mask */

// -----------------------------  ETHERNET_DMA_CURHOST_TRANS_BUF  ---------------------------------
#define ETHERNET_DMA_CURHOST_TRANS_BUF_HTB_Pos                0                                                         /*!< ETHERNET DMA_CURHOST_TRANS_BUF: HTB Position */
#define ETHERNET_DMA_CURHOST_TRANS_BUF_HTB_Msk                (0xffffffffUL << ETHERNET_DMA_CURHOST_TRANS_BUF_HTB_Pos)  /*!< ETHERNET DMA_CURHOST_TRANS_BUF: HTB Mask */

// ------------------------------  ETHERNET_DMA_CURHOST_REC_BUF  ----------------------------------
#define ETHERNET_DMA_CURHOST_REC_BUF_HRB_Pos                  0                                                         /*!< ETHERNET DMA_CURHOST_REC_BUF: HRB Position */
#define ETHERNET_DMA_CURHOST_REC_BUF_HRB_Msk                  (0xffffffffUL << ETHERNET_DMA_CURHOST_REC_BUF_HRB_Pos)    /*!< ETHERNET DMA_CURHOST_REC_BUF: HRB Mask */


// ------------------------------------------------------------------------------------------------
// -----                                ATIMER Position & Mask                                -----
// ------------------------------------------------------------------------------------------------


// -----------------------------------  ATIMER_DOWNCOUNTER  ---------------------------------------
#define ATIMER_DOWNCOUNTER_CVAL_Pos                           0                                                         /*!< ATIMER DOWNCOUNTER: CVAL Position   */
#define ATIMER_DOWNCOUNTER_CVAL_Msk                           (0x0000ffffUL << ATIMER_DOWNCOUNTER_CVAL_Pos)             /*!< ATIMER DOWNCOUNTER: CVAL Mask       */

// --------------------------------------  ATIMER_PRESET  -----------------------------------------
#define ATIMER_PRESET_PRESETVAL_Pos                           0                                                         /*!< ATIMER PRESET: PRESETVAL Position   */
#define ATIMER_PRESET_PRESETVAL_Msk                           (0x0000ffffUL << ATIMER_PRESET_PRESETVAL_Pos)             /*!< ATIMER PRESET: PRESETVAL Mask       */

// --------------------------------------  ATIMER_CLR_EN  -----------------------------------------
#define ATIMER_CLR_EN_CLR_EN_Pos                              0                                                         /*!< ATIMER CLR_EN: CLR_EN Position      */
#define ATIMER_CLR_EN_CLR_EN_Msk                              (0x01UL << ATIMER_CLR_EN_CLR_EN_Pos)                      /*!< ATIMER CLR_EN: CLR_EN Mask          */

// --------------------------------------  ATIMER_SET_EN  -----------------------------------------
#define ATIMER_SET_EN_SET_EN_Pos                              0                                                         /*!< ATIMER SET_EN: SET_EN Position      */
#define ATIMER_SET_EN_SET_EN_Msk                              (0x01UL << ATIMER_SET_EN_SET_EN_Pos)                      /*!< ATIMER SET_EN: SET_EN Mask          */

// --------------------------------------  ATIMER_STATUS  -----------------------------------------
#define ATIMER_STATUS_STAT_Pos                                0                                                         /*!< ATIMER STATUS: STAT Position        */
#define ATIMER_STATUS_STAT_Msk                                (0x01UL << ATIMER_STATUS_STAT_Pos)                        /*!< ATIMER STATUS: STAT Mask            */

// --------------------------------------  ATIMER_ENABLE  -----------------------------------------
#define ATIMER_ENABLE_EN_Pos                                  0                                                         /*!< ATIMER ENABLE: EN Position          */
#define ATIMER_ENABLE_EN_Msk                                  (0x01UL << ATIMER_ENABLE_EN_Pos)                          /*!< ATIMER ENABLE: EN Mask              */

// -------------------------------------  ATIMER_CLR_STAT  ----------------------------------------
#define ATIMER_CLR_STAT_CSTAT_Pos                             0                                                         /*!< ATIMER CLR_STAT: CSTAT Position     */
#define ATIMER_CLR_STAT_CSTAT_Msk                             (0x01UL << ATIMER_CLR_STAT_CSTAT_Pos)                     /*!< ATIMER CLR_STAT: CSTAT Mask         */

// -------------------------------------  ATIMER_SET_STAT  ----------------------------------------
#define ATIMER_SET_STAT_SSTAT_Pos                             0                                                         /*!< ATIMER SET_STAT: SSTAT Position     */
#define ATIMER_SET_STAT_SSTAT_Msk                             (0x01UL << ATIMER_SET_STAT_SSTAT_Pos)                     /*!< ATIMER SET_STAT: SSTAT Mask         */


// ------------------------------------------------------------------------------------------------
// -----                                REGFILE Position & Mask                               -----
// ------------------------------------------------------------------------------------------------


// ------------------------------------  REGFILE_REGFILE0  ----------------------------------------
#define REGFILE_REGFILE0_REGVAL_Pos                           0                                                         /*!< REGFILE REGFILE0: REGVAL Position   */
#define REGFILE_REGFILE0_REGVAL_Msk                           (0xffffffffUL << REGFILE_REGFILE0_REGVAL_Pos)             /*!< REGFILE REGFILE0: REGVAL Mask       */

// ------------------------------------  REGFILE_REGFILE1  ----------------------------------------
#define REGFILE_REGFILE1_REGVAL_Pos                           0                                                         /*!< REGFILE REGFILE1: REGVAL Position   */
#define REGFILE_REGFILE1_REGVAL_Msk                           (0xffffffffUL << REGFILE_REGFILE1_REGVAL_Pos)             /*!< REGFILE REGFILE1: REGVAL Mask       */

// ------------------------------------  REGFILE_REGFILE2  ----------------------------------------
#define REGFILE_REGFILE2_REGVAL_Pos                           0                                                         /*!< REGFILE REGFILE2: REGVAL Position   */
#define REGFILE_REGFILE2_REGVAL_Msk                           (0xffffffffUL << REGFILE_REGFILE2_REGVAL_Pos)             /*!< REGFILE REGFILE2: REGVAL Mask       */

// ------------------------------------  REGFILE_REGFILE3  ----------------------------------------
#define REGFILE_REGFILE3_REGVAL_Pos                           0                                                         /*!< REGFILE REGFILE3: REGVAL Position   */
#define REGFILE_REGFILE3_REGVAL_Msk                           (0xffffffffUL << REGFILE_REGFILE3_REGVAL_Pos)             /*!< REGFILE REGFILE3: REGVAL Mask       */

// ------------------------------------  REGFILE_REGFILE4  ----------------------------------------
#define REGFILE_REGFILE4_REGVAL_Pos                           0                                                         /*!< REGFILE REGFILE4: REGVAL Position   */
#define REGFILE_REGFILE4_REGVAL_Msk                           (0xffffffffUL << REGFILE_REGFILE4_REGVAL_Pos)             /*!< REGFILE REGFILE4: REGVAL Mask       */

// ------------------------------------  REGFILE_REGFILE5  ----------------------------------------
#define REGFILE_REGFILE5_REGVAL_Pos                           0                                                         /*!< REGFILE REGFILE5: REGVAL Position   */
#define REGFILE_REGFILE5_REGVAL_Msk                           (0xffffffffUL << REGFILE_REGFILE5_REGVAL_Pos)             /*!< REGFILE REGFILE5: REGVAL Mask       */

// ------------------------------------  REGFILE_REGFILE6  ----------------------------------------
#define REGFILE_REGFILE6_REGVAL_Pos                           0                                                         /*!< REGFILE REGFILE6: REGVAL Position   */
#define REGFILE_REGFILE6_REGVAL_Msk                           (0xffffffffUL << REGFILE_REGFILE6_REGVAL_Pos)             /*!< REGFILE REGFILE6: REGVAL Mask       */

// ------------------------------------  REGFILE_REGFILE7  ----------------------------------------
#define REGFILE_REGFILE7_REGVAL_Pos                           0                                                         /*!< REGFILE REGFILE7: REGVAL Position   */
#define REGFILE_REGFILE7_REGVAL_Msk                           (0xffffffffUL << REGFILE_REGFILE7_REGVAL_Pos)             /*!< REGFILE REGFILE7: REGVAL Mask       */

// ------------------------------------  REGFILE_REGFILE8  ----------------------------------------
#define REGFILE_REGFILE8_REGVAL_Pos                           0                                                         /*!< REGFILE REGFILE8: REGVAL Position   */
#define REGFILE_REGFILE8_REGVAL_Msk                           (0xffffffffUL << REGFILE_REGFILE8_REGVAL_Pos)             /*!< REGFILE REGFILE8: REGVAL Mask       */

// ------------------------------------  REGFILE_REGFILE9  ----------------------------------------
#define REGFILE_REGFILE9_REGVAL_Pos                           0                                                         /*!< REGFILE REGFILE9: REGVAL Position   */
#define REGFILE_REGFILE9_REGVAL_Msk                           (0xffffffffUL << REGFILE_REGFILE9_REGVAL_Pos)             /*!< REGFILE REGFILE9: REGVAL Mask       */

// ------------------------------------  REGFILE_REGFILE10  ---------------------------------------
#define REGFILE_REGFILE10_REGVAL_Pos                          0                                                         /*!< REGFILE REGFILE10: REGVAL Position  */
#define REGFILE_REGFILE10_REGVAL_Msk                          (0xffffffffUL << REGFILE_REGFILE10_REGVAL_Pos)            /*!< REGFILE REGFILE10: REGVAL Mask      */

// ------------------------------------  REGFILE_REGFILE11  ---------------------------------------
#define REGFILE_REGFILE11_REGVAL_Pos                          0                                                         /*!< REGFILE REGFILE11: REGVAL Position  */
#define REGFILE_REGFILE11_REGVAL_Msk                          (0xffffffffUL << REGFILE_REGFILE11_REGVAL_Pos)            /*!< REGFILE REGFILE11: REGVAL Mask      */

// ------------------------------------  REGFILE_REGFILE12  ---------------------------------------
#define REGFILE_REGFILE12_REGVAL_Pos                          0                                                         /*!< REGFILE REGFILE12: REGVAL Position  */
#define REGFILE_REGFILE12_REGVAL_Msk                          (0xffffffffUL << REGFILE_REGFILE12_REGVAL_Pos)            /*!< REGFILE REGFILE12: REGVAL Mask      */

// ------------------------------------  REGFILE_REGFILE13  ---------------------------------------
#define REGFILE_REGFILE13_REGVAL_Pos                          0                                                         /*!< REGFILE REGFILE13: REGVAL Position  */
#define REGFILE_REGFILE13_REGVAL_Msk                          (0xffffffffUL << REGFILE_REGFILE13_REGVAL_Pos)            /*!< REGFILE REGFILE13: REGVAL Mask      */

// ------------------------------------  REGFILE_REGFILE14  ---------------------------------------
#define REGFILE_REGFILE14_REGVAL_Pos                          0                                                         /*!< REGFILE REGFILE14: REGVAL Position  */
#define REGFILE_REGFILE14_REGVAL_Msk                          (0xffffffffUL << REGFILE_REGFILE14_REGVAL_Pos)            /*!< REGFILE REGFILE14: REGVAL Mask      */

// ------------------------------------  REGFILE_REGFILE15  ---------------------------------------
#define REGFILE_REGFILE15_REGVAL_Pos                          0                                                         /*!< REGFILE REGFILE15: REGVAL Position  */
#define REGFILE_REGFILE15_REGVAL_Msk                          (0xffffffffUL << REGFILE_REGFILE15_REGVAL_Pos)            /*!< REGFILE REGFILE15: REGVAL Mask      */

// ------------------------------------  REGFILE_REGFILE16  ---------------------------------------
#define REGFILE_REGFILE16_REGVAL_Pos                          0                                                         /*!< REGFILE REGFILE16: REGVAL Position  */
#define REGFILE_REGFILE16_REGVAL_Msk                          (0xffffffffUL << REGFILE_REGFILE16_REGVAL_Pos)            /*!< REGFILE REGFILE16: REGVAL Mask      */

// ------------------------------------  REGFILE_REGFILE17  ---------------------------------------
#define REGFILE_REGFILE17_REGVAL_Pos                          0                                                         /*!< REGFILE REGFILE17: REGVAL Position  */
#define REGFILE_REGFILE17_REGVAL_Msk                          (0xffffffffUL << REGFILE_REGFILE17_REGVAL_Pos)            /*!< REGFILE REGFILE17: REGVAL Mask      */

// ------------------------------------  REGFILE_REGFILE18  ---------------------------------------
#define REGFILE_REGFILE18_REGVAL_Pos                          0                                                         /*!< REGFILE REGFILE18: REGVAL Position  */
#define REGFILE_REGFILE18_REGVAL_Msk                          (0xffffffffUL << REGFILE_REGFILE18_REGVAL_Pos)            /*!< REGFILE REGFILE18: REGVAL Mask      */

// ------------------------------------  REGFILE_REGFILE19  ---------------------------------------
#define REGFILE_REGFILE19_REGVAL_Pos                          0                                                         /*!< REGFILE REGFILE19: REGVAL Position  */
#define REGFILE_REGFILE19_REGVAL_Msk                          (0xffffffffUL << REGFILE_REGFILE19_REGVAL_Pos)            /*!< REGFILE REGFILE19: REGVAL Mask      */

// ------------------------------------  REGFILE_REGFILE20  ---------------------------------------
#define REGFILE_REGFILE20_REGVAL_Pos                          0                                                         /*!< REGFILE REGFILE20: REGVAL Position  */
#define REGFILE_REGFILE20_REGVAL_Msk                          (0xffffffffUL << REGFILE_REGFILE20_REGVAL_Pos)            /*!< REGFILE REGFILE20: REGVAL Mask      */

// ------------------------------------  REGFILE_REGFILE21  ---------------------------------------
#define REGFILE_REGFILE21_REGVAL_Pos                          0                                                         /*!< REGFILE REGFILE21: REGVAL Position  */
#define REGFILE_REGFILE21_REGVAL_Msk                          (0xffffffffUL << REGFILE_REGFILE21_REGVAL_Pos)            /*!< REGFILE REGFILE21: REGVAL Mask      */

// ------------------------------------  REGFILE_REGFILE22  ---------------------------------------
#define REGFILE_REGFILE22_REGVAL_Pos                          0                                                         /*!< REGFILE REGFILE22: REGVAL Position  */
#define REGFILE_REGFILE22_REGVAL_Msk                          (0xffffffffUL << REGFILE_REGFILE22_REGVAL_Pos)            /*!< REGFILE REGFILE22: REGVAL Mask      */

// ------------------------------------  REGFILE_REGFILE23  ---------------------------------------
#define REGFILE_REGFILE23_REGVAL_Pos                          0                                                         /*!< REGFILE REGFILE23: REGVAL Position  */
#define REGFILE_REGFILE23_REGVAL_Msk                          (0xffffffffUL << REGFILE_REGFILE23_REGVAL_Pos)            /*!< REGFILE REGFILE23: REGVAL Mask      */

// ------------------------------------  REGFILE_REGFILE24  ---------------------------------------
#define REGFILE_REGFILE24_REGVAL_Pos                          0                                                         /*!< REGFILE REGFILE24: REGVAL Position  */
#define REGFILE_REGFILE24_REGVAL_Msk                          (0xffffffffUL << REGFILE_REGFILE24_REGVAL_Pos)            /*!< REGFILE REGFILE24: REGVAL Mask      */

// ------------------------------------  REGFILE_REGFILE25  ---------------------------------------
#define REGFILE_REGFILE25_REGVAL_Pos                          0                                                         /*!< REGFILE REGFILE25: REGVAL Position  */
#define REGFILE_REGFILE25_REGVAL_Msk                          (0xffffffffUL << REGFILE_REGFILE25_REGVAL_Pos)            /*!< REGFILE REGFILE25: REGVAL Mask      */

// ------------------------------------  REGFILE_REGFILE26  ---------------------------------------
#define REGFILE_REGFILE26_REGVAL_Pos                          0                                                         /*!< REGFILE REGFILE26: REGVAL Position  */
#define REGFILE_REGFILE26_REGVAL_Msk                          (0xffffffffUL << REGFILE_REGFILE26_REGVAL_Pos)            /*!< REGFILE REGFILE26: REGVAL Mask      */

// ------------------------------------  REGFILE_REGFILE27  ---------------------------------------
#define REGFILE_REGFILE27_REGVAL_Pos                          0                                                         /*!< REGFILE REGFILE27: REGVAL Position  */
#define REGFILE_REGFILE27_REGVAL_Msk                          (0xffffffffUL << REGFILE_REGFILE27_REGVAL_Pos)            /*!< REGFILE REGFILE27: REGVAL Mask      */

// ------------------------------------  REGFILE_REGFILE28  ---------------------------------------
#define REGFILE_REGFILE28_REGVAL_Pos                          0                                                         /*!< REGFILE REGFILE28: REGVAL Position  */
#define REGFILE_REGFILE28_REGVAL_Msk                          (0xffffffffUL << REGFILE_REGFILE28_REGVAL_Pos)            /*!< REGFILE REGFILE28: REGVAL Mask      */

// ------------------------------------  REGFILE_REGFILE29  ---------------------------------------
#define REGFILE_REGFILE29_REGVAL_Pos                          0                                                         /*!< REGFILE REGFILE29: REGVAL Position  */
#define REGFILE_REGFILE29_REGVAL_Msk                          (0xffffffffUL << REGFILE_REGFILE29_REGVAL_Pos)            /*!< REGFILE REGFILE29: REGVAL Mask      */

// ------------------------------------  REGFILE_REGFILE30  ---------------------------------------
#define REGFILE_REGFILE30_REGVAL_Pos                          0                                                         /*!< REGFILE REGFILE30: REGVAL Position  */
#define REGFILE_REGFILE30_REGVAL_Msk                          (0xffffffffUL << REGFILE_REGFILE30_REGVAL_Pos)            /*!< REGFILE REGFILE30: REGVAL Mask      */

// ------------------------------------  REGFILE_REGFILE31  ---------------------------------------
#define REGFILE_REGFILE31_REGVAL_Pos                          0                                                         /*!< REGFILE REGFILE31: REGVAL Position  */
#define REGFILE_REGFILE31_REGVAL_Msk                          (0xffffffffUL << REGFILE_REGFILE31_REGVAL_Pos)            /*!< REGFILE REGFILE31: REGVAL Mask      */

// ------------------------------------  REGFILE_REGFILE32  ---------------------------------------
#define REGFILE_REGFILE32_REGVAL_Pos                          0                                                         /*!< REGFILE REGFILE32: REGVAL Position  */
#define REGFILE_REGFILE32_REGVAL_Msk                          (0xffffffffUL << REGFILE_REGFILE32_REGVAL_Pos)            /*!< REGFILE REGFILE32: REGVAL Mask      */

// ------------------------------------  REGFILE_REGFILE33  ---------------------------------------
#define REGFILE_REGFILE33_REGVAL_Pos                          0                                                         /*!< REGFILE REGFILE33: REGVAL Position  */
#define REGFILE_REGFILE33_REGVAL_Msk                          (0xffffffffUL << REGFILE_REGFILE33_REGVAL_Pos)            /*!< REGFILE REGFILE33: REGVAL Mask      */

// ------------------------------------  REGFILE_REGFILE34  ---------------------------------------
#define REGFILE_REGFILE34_REGVAL_Pos                          0                                                         /*!< REGFILE REGFILE34: REGVAL Position  */
#define REGFILE_REGFILE34_REGVAL_Msk                          (0xffffffffUL << REGFILE_REGFILE34_REGVAL_Pos)            /*!< REGFILE REGFILE34: REGVAL Mask      */

// ------------------------------------  REGFILE_REGFILE35  ---------------------------------------
#define REGFILE_REGFILE35_REGVAL_Pos                          0                                                         /*!< REGFILE REGFILE35: REGVAL Position  */
#define REGFILE_REGFILE35_REGVAL_Msk                          (0xffffffffUL << REGFILE_REGFILE35_REGVAL_Pos)            /*!< REGFILE REGFILE35: REGVAL Mask      */

// ------------------------------------  REGFILE_REGFILE36  ---------------------------------------
#define REGFILE_REGFILE36_REGVAL_Pos                          0                                                         /*!< REGFILE REGFILE36: REGVAL Position  */
#define REGFILE_REGFILE36_REGVAL_Msk                          (0xffffffffUL << REGFILE_REGFILE36_REGVAL_Pos)            /*!< REGFILE REGFILE36: REGVAL Mask      */

// ------------------------------------  REGFILE_REGFILE37  ---------------------------------------
#define REGFILE_REGFILE37_REGVAL_Pos                          0                                                         /*!< REGFILE REGFILE37: REGVAL Position  */
#define REGFILE_REGFILE37_REGVAL_Msk                          (0xffffffffUL << REGFILE_REGFILE37_REGVAL_Pos)            /*!< REGFILE REGFILE37: REGVAL Mask      */

// ------------------------------------  REGFILE_REGFILE38  ---------------------------------------
#define REGFILE_REGFILE38_REGVAL_Pos                          0                                                         /*!< REGFILE REGFILE38: REGVAL Position  */
#define REGFILE_REGFILE38_REGVAL_Msk                          (0xffffffffUL << REGFILE_REGFILE38_REGVAL_Pos)            /*!< REGFILE REGFILE38: REGVAL Mask      */

// ------------------------------------  REGFILE_REGFILE39  ---------------------------------------
#define REGFILE_REGFILE39_REGVAL_Pos                          0                                                         /*!< REGFILE REGFILE39: REGVAL Position  */
#define REGFILE_REGFILE39_REGVAL_Msk                          (0xffffffffUL << REGFILE_REGFILE39_REGVAL_Pos)            /*!< REGFILE REGFILE39: REGVAL Mask      */

// ------------------------------------  REGFILE_REGFILE40  ---------------------------------------
#define REGFILE_REGFILE40_REGVAL_Pos                          0                                                         /*!< REGFILE REGFILE40: REGVAL Position  */
#define REGFILE_REGFILE40_REGVAL_Msk                          (0xffffffffUL << REGFILE_REGFILE40_REGVAL_Pos)            /*!< REGFILE REGFILE40: REGVAL Mask      */

// ------------------------------------  REGFILE_REGFILE41  ---------------------------------------
#define REGFILE_REGFILE41_REGVAL_Pos                          0                                                         /*!< REGFILE REGFILE41: REGVAL Position  */
#define REGFILE_REGFILE41_REGVAL_Msk                          (0xffffffffUL << REGFILE_REGFILE41_REGVAL_Pos)            /*!< REGFILE REGFILE41: REGVAL Mask      */

// ------------------------------------  REGFILE_REGFILE42  ---------------------------------------
#define REGFILE_REGFILE42_REGVAL_Pos                          0                                                         /*!< REGFILE REGFILE42: REGVAL Position  */
#define REGFILE_REGFILE42_REGVAL_Msk                          (0xffffffffUL << REGFILE_REGFILE42_REGVAL_Pos)            /*!< REGFILE REGFILE42: REGVAL Mask      */

// ------------------------------------  REGFILE_REGFILE43  ---------------------------------------
#define REGFILE_REGFILE43_REGVAL_Pos                          0                                                         /*!< REGFILE REGFILE43: REGVAL Position  */
#define REGFILE_REGFILE43_REGVAL_Msk                          (0xffffffffUL << REGFILE_REGFILE43_REGVAL_Pos)            /*!< REGFILE REGFILE43: REGVAL Mask      */

// ------------------------------------  REGFILE_REGFILE44  ---------------------------------------
#define REGFILE_REGFILE44_REGVAL_Pos                          0                                                         /*!< REGFILE REGFILE44: REGVAL Position  */
#define REGFILE_REGFILE44_REGVAL_Msk                          (0xffffffffUL << REGFILE_REGFILE44_REGVAL_Pos)            /*!< REGFILE REGFILE44: REGVAL Mask      */

// ------------------------------------  REGFILE_REGFILE45  ---------------------------------------
#define REGFILE_REGFILE45_REGVAL_Pos                          0                                                         /*!< REGFILE REGFILE45: REGVAL Position  */
#define REGFILE_REGFILE45_REGVAL_Msk                          (0xffffffffUL << REGFILE_REGFILE45_REGVAL_Pos)            /*!< REGFILE REGFILE45: REGVAL Mask      */

// ------------------------------------  REGFILE_REGFILE46  ---------------------------------------
#define REGFILE_REGFILE46_REGVAL_Pos                          0                                                         /*!< REGFILE REGFILE46: REGVAL Position  */
#define REGFILE_REGFILE46_REGVAL_Msk                          (0xffffffffUL << REGFILE_REGFILE46_REGVAL_Pos)            /*!< REGFILE REGFILE46: REGVAL Mask      */

// ------------------------------------  REGFILE_REGFILE47  ---------------------------------------
#define REGFILE_REGFILE47_REGVAL_Pos                          0                                                         /*!< REGFILE REGFILE47: REGVAL Position  */
#define REGFILE_REGFILE47_REGVAL_Msk                          (0xffffffffUL << REGFILE_REGFILE47_REGVAL_Pos)            /*!< REGFILE REGFILE47: REGVAL Mask      */

// ------------------------------------  REGFILE_REGFILE48  ---------------------------------------
#define REGFILE_REGFILE48_REGVAL_Pos                          0                                                         /*!< REGFILE REGFILE48: REGVAL Position  */
#define REGFILE_REGFILE48_REGVAL_Msk                          (0xffffffffUL << REGFILE_REGFILE48_REGVAL_Pos)            /*!< REGFILE REGFILE48: REGVAL Mask      */

// ------------------------------------  REGFILE_REGFILE49  ---------------------------------------
#define REGFILE_REGFILE49_REGVAL_Pos                          0                                                         /*!< REGFILE REGFILE49: REGVAL Position  */
#define REGFILE_REGFILE49_REGVAL_Msk                          (0xffffffffUL << REGFILE_REGFILE49_REGVAL_Pos)            /*!< REGFILE REGFILE49: REGVAL Mask      */

// ------------------------------------  REGFILE_REGFILE50  ---------------------------------------
#define REGFILE_REGFILE50_REGVAL_Pos                          0                                                         /*!< REGFILE REGFILE50: REGVAL Position  */
#define REGFILE_REGFILE50_REGVAL_Msk                          (0xffffffffUL << REGFILE_REGFILE50_REGVAL_Pos)            /*!< REGFILE REGFILE50: REGVAL Mask      */

// ------------------------------------  REGFILE_REGFILE51  ---------------------------------------
#define REGFILE_REGFILE51_REGVAL_Pos                          0                                                         /*!< REGFILE REGFILE51: REGVAL Position  */
#define REGFILE_REGFILE51_REGVAL_Msk                          (0xffffffffUL << REGFILE_REGFILE51_REGVAL_Pos)            /*!< REGFILE REGFILE51: REGVAL Mask      */

// ------------------------------------  REGFILE_REGFILE52  ---------------------------------------
#define REGFILE_REGFILE52_REGVAL_Pos                          0                                                         /*!< REGFILE REGFILE52: REGVAL Position  */
#define REGFILE_REGFILE52_REGVAL_Msk                          (0xffffffffUL << REGFILE_REGFILE52_REGVAL_Pos)            /*!< REGFILE REGFILE52: REGVAL Mask      */

// ------------------------------------  REGFILE_REGFILE53  ---------------------------------------
#define REGFILE_REGFILE53_REGVAL_Pos                          0                                                         /*!< REGFILE REGFILE53: REGVAL Position  */
#define REGFILE_REGFILE53_REGVAL_Msk                          (0xffffffffUL << REGFILE_REGFILE53_REGVAL_Pos)            /*!< REGFILE REGFILE53: REGVAL Mask      */

// ------------------------------------  REGFILE_REGFILE54  ---------------------------------------
#define REGFILE_REGFILE54_REGVAL_Pos                          0                                                         /*!< REGFILE REGFILE54: REGVAL Position  */
#define REGFILE_REGFILE54_REGVAL_Msk                          (0xffffffffUL << REGFILE_REGFILE54_REGVAL_Pos)            /*!< REGFILE REGFILE54: REGVAL Mask      */

// ------------------------------------  REGFILE_REGFILE55  ---------------------------------------
#define REGFILE_REGFILE55_REGVAL_Pos                          0                                                         /*!< REGFILE REGFILE55: REGVAL Position  */
#define REGFILE_REGFILE55_REGVAL_Msk                          (0xffffffffUL << REGFILE_REGFILE55_REGVAL_Pos)            /*!< REGFILE REGFILE55: REGVAL Mask      */

// ------------------------------------  REGFILE_REGFILE56  ---------------------------------------
#define REGFILE_REGFILE56_REGVAL_Pos                          0                                                         /*!< REGFILE REGFILE56: REGVAL Position  */
#define REGFILE_REGFILE56_REGVAL_Msk                          (0xffffffffUL << REGFILE_REGFILE56_REGVAL_Pos)            /*!< REGFILE REGFILE56: REGVAL Mask      */

// ------------------------------------  REGFILE_REGFILE57  ---------------------------------------
#define REGFILE_REGFILE57_REGVAL_Pos                          0                                                         /*!< REGFILE REGFILE57: REGVAL Position  */
#define REGFILE_REGFILE57_REGVAL_Msk                          (0xffffffffUL << REGFILE_REGFILE57_REGVAL_Pos)            /*!< REGFILE REGFILE57: REGVAL Mask      */

// ------------------------------------  REGFILE_REGFILE58  ---------------------------------------
#define REGFILE_REGFILE58_REGVAL_Pos                          0                                                         /*!< REGFILE REGFILE58: REGVAL Position  */
#define REGFILE_REGFILE58_REGVAL_Msk                          (0xffffffffUL << REGFILE_REGFILE58_REGVAL_Pos)            /*!< REGFILE REGFILE58: REGVAL Mask      */

// ------------------------------------  REGFILE_REGFILE59  ---------------------------------------
#define REGFILE_REGFILE59_REGVAL_Pos                          0                                                         /*!< REGFILE REGFILE59: REGVAL Position  */
#define REGFILE_REGFILE59_REGVAL_Msk                          (0xffffffffUL << REGFILE_REGFILE59_REGVAL_Pos)            /*!< REGFILE REGFILE59: REGVAL Mask      */

// ------------------------------------  REGFILE_REGFILE60  ---------------------------------------
#define REGFILE_REGFILE60_REGVAL_Pos                          0                                                         /*!< REGFILE REGFILE60: REGVAL Position  */
#define REGFILE_REGFILE60_REGVAL_Msk                          (0xffffffffUL << REGFILE_REGFILE60_REGVAL_Pos)            /*!< REGFILE REGFILE60: REGVAL Mask      */

// ------------------------------------  REGFILE_REGFILE61  ---------------------------------------
#define REGFILE_REGFILE61_REGVAL_Pos                          0                                                         /*!< REGFILE REGFILE61: REGVAL Position  */
#define REGFILE_REGFILE61_REGVAL_Msk                          (0xffffffffUL << REGFILE_REGFILE61_REGVAL_Pos)            /*!< REGFILE REGFILE61: REGVAL Mask      */

// ------------------------------------  REGFILE_REGFILE62  ---------------------------------------
#define REGFILE_REGFILE62_REGVAL_Pos                          0                                                         /*!< REGFILE REGFILE62: REGVAL Position  */
#define REGFILE_REGFILE62_REGVAL_Msk                          (0xffffffffUL << REGFILE_REGFILE62_REGVAL_Pos)            /*!< REGFILE REGFILE62: REGVAL Mask      */

// ------------------------------------  REGFILE_REGFILE63  ---------------------------------------
#define REGFILE_REGFILE63_REGVAL_Pos                          0                                                         /*!< REGFILE REGFILE63: REGVAL Position  */
#define REGFILE_REGFILE63_REGVAL_Msk                          (0xffffffffUL << REGFILE_REGFILE63_REGVAL_Pos)            /*!< REGFILE REGFILE63: REGVAL Mask      */


// ------------------------------------------------------------------------------------------------
// -----                                  PMC Position & Mask                                 -----
// ------------------------------------------------------------------------------------------------


// ----------------------------------  PMC_PD0_SLEEP0_HW_ENA  -------------------------------------
#define PMC_PD0_SLEEP0_HW_ENA_ENA_EVENT0_Pos                  0                                                         /*!< PMC PD0_SLEEP0_HW_ENA: ENA_EVENT0 Position */
#define PMC_PD0_SLEEP0_HW_ENA_ENA_EVENT0_Msk                  (0x01UL << PMC_PD0_SLEEP0_HW_ENA_ENA_EVENT0_Pos)          /*!< PMC PD0_SLEEP0_HW_ENA: ENA_EVENT0 Mask */

// -----------------------------------  PMC_PD0_SLEEP0_MODE  --------------------------------------
#define PMC_PD0_SLEEP0_MODE_PWR_STATE_Pos                     0                                                         /*!< PMC PD0_SLEEP0_MODE: PWR_STATE Position */
#define PMC_PD0_SLEEP0_MODE_PWR_STATE_Msk                     (0xffffffffUL << PMC_PD0_SLEEP0_MODE_PWR_STATE_Pos)       /*!< PMC PD0_SLEEP0_MODE: PWR_STATE Mask */


// ------------------------------------------------------------------------------------------------
// -----                                 CREG Position & Mask                                 -----
// ------------------------------------------------------------------------------------------------


// ---------------------------------------  CREG_IRCTRM  ------------------------------------------
#define CREG_IRCTRM_TRM_Pos                                   0                                                         /*!< CREG IRCTRM: TRM Position           */
#define CREG_IRCTRM_TRM_Msk                                   (0x00000fffUL << CREG_IRCTRM_TRM_Pos)                     /*!< CREG IRCTRM: TRM Mask               */

// ---------------------------------------  CREG_CREG0  -------------------------------------------
#define CREG_CREG0_EN1KHZ_Pos                                 0                                                         /*!< CREG CREG0: EN1KHZ Position         */
#define CREG_CREG0_EN1KHZ_Msk                                 (0x01UL << CREG_CREG0_EN1KHZ_Pos)                         /*!< CREG CREG0: EN1KHZ Mask             */
#define CREG_CREG0_EN32KHZ_Pos                                1                                                         /*!< CREG CREG0: EN32KHZ Position        */
#define CREG_CREG0_EN32KHZ_Msk                                (0x01UL << CREG_CREG0_EN32KHZ_Pos)                        /*!< CREG CREG0: EN32KHZ Mask            */
#define CREG_CREG0_RESET32KHZ_Pos                             2                                                         /*!< CREG CREG0: RESET32KHZ Position     */
#define CREG_CREG0_RESET32KHZ_Msk                             (0x01UL << CREG_CREG0_RESET32KHZ_Pos)                     /*!< CREG CREG0: RESET32KHZ Mask         */
#define CREG_CREG0_32KHZPD_Pos                                3                                                         /*!< CREG CREG0: 32KHZPD Position        */
#define CREG_CREG0_32KHZPD_Msk                                (0x01UL << CREG_CREG0_32KHZPD_Pos)                        /*!< CREG CREG0: 32KHZPD Mask            */
#define CREG_CREG0_USB0PHY_Pos                                5                                                         /*!< CREG CREG0: USB0PHY Position        */
#define CREG_CREG0_USB0PHY_Msk                                (0x01UL << CREG_CREG0_USB0PHY_Pos)                        /*!< CREG CREG0: USB0PHY Mask            */
#define CREG_CREG0_ALARMCTRL_Pos                              6                                                         /*!< CREG CREG0: ALARMCTRL Position      */
#define CREG_CREG0_ALARMCTRL_Msk                              (0x03UL << CREG_CREG0_ALARMCTRL_Pos)                      /*!< CREG CREG0: ALARMCTRL Mask          */
#define CREG_CREG0_BODLVL1_Pos                                8                                                         /*!< CREG CREG0: BODLVL1 Position        */
#define CREG_CREG0_BODLVL1_Msk                                (0x03UL << CREG_CREG0_BODLVL1_Pos)                        /*!< CREG CREG0: BODLVL1 Mask            */
#define CREG_CREG0_BODLVL2_Pos                                10                                                        /*!< CREG CREG0: BODLVL2 Position        */
#define CREG_CREG0_BODLVL2_Msk                                (0x03UL << CREG_CREG0_BODLVL2_Pos)                        /*!< CREG CREG0: BODLVL2 Mask            */
#define CREG_CREG0_WAKEUP0CTRL_Pos                            14                                                        /*!< CREG CREG0: WAKEUP0CTRL Position    */
#define CREG_CREG0_WAKEUP0CTRL_Msk                            (0x03UL << CREG_CREG0_WAKEUP0CTRL_Pos)                    /*!< CREG CREG0: WAKEUP0CTRL Mask        */
#define CREG_CREG0_WAKEUP1CTRL_Pos                            16                                                        /*!< CREG CREG0: WAKEUP1CTRL Position    */
#define CREG_CREG0_WAKEUP1CTRL_Msk                            (0x03UL << CREG_CREG0_WAKEUP1CTRL_Pos)                    /*!< CREG CREG0: WAKEUP1CTRL Mask        */

// --------------------------------------  CREG_M4MEMMAP  -----------------------------------------
#define CREG_M4MEMMAP_M4MAP_Pos                               12                                                        /*!< CREG M4MEMMAP: M4MAP Position       */
#define CREG_M4MEMMAP_M4MAP_Msk                               (0x000fffffUL << CREG_M4MEMMAP_M4MAP_Pos)                 /*!< CREG M4MEMMAP: M4MAP Mask           */

// ---------------------------------------  CREG_CREG5  -------------------------------------------
#define CREG_CREG5_M4TAPSEL_Pos                               6                                                         /*!< CREG CREG5: M4TAPSEL Position       */
#define CREG_CREG5_M4TAPSEL_Msk                               (0x01UL << CREG_CREG5_M4TAPSEL_Pos)                       /*!< CREG CREG5: M4TAPSEL Mask           */

// ---------------------------------------  CREG_DMAMUX  ------------------------------------------
#define CREG_DMAMUX_DMAMUXCH0_Pos                             0                                                         /*!< CREG DMAMUX: DMAMUXCH0 Position     */
#define CREG_DMAMUX_DMAMUXCH0_Msk                             (0x03UL << CREG_DMAMUX_DMAMUXCH0_Pos)                     /*!< CREG DMAMUX: DMAMUXCH0 Mask         */
#define CREG_DMAMUX_DMAMUXCH1_Pos                             2                                                         /*!< CREG DMAMUX: DMAMUXCH1 Position     */
#define CREG_DMAMUX_DMAMUXCH1_Msk                             (0x03UL << CREG_DMAMUX_DMAMUXCH1_Pos)                     /*!< CREG DMAMUX: DMAMUXCH1 Mask         */
#define CREG_DMAMUX_DMAMUXCH2_Pos                             4                                                         /*!< CREG DMAMUX: DMAMUXCH2 Position     */
#define CREG_DMAMUX_DMAMUXCH2_Msk                             (0x03UL << CREG_DMAMUX_DMAMUXCH2_Pos)                     /*!< CREG DMAMUX: DMAMUXCH2 Mask         */
#define CREG_DMAMUX_DMAMUXCH3_Pos                             6                                                         /*!< CREG DMAMUX: DMAMUXCH3 Position     */
#define CREG_DMAMUX_DMAMUXCH3_Msk                             (0x03UL << CREG_DMAMUX_DMAMUXCH3_Pos)                     /*!< CREG DMAMUX: DMAMUXCH3 Mask         */
#define CREG_DMAMUX_DMAMUXCH4_Pos                             8                                                         /*!< CREG DMAMUX: DMAMUXCH4 Position     */
#define CREG_DMAMUX_DMAMUXCH4_Msk                             (0x03UL << CREG_DMAMUX_DMAMUXCH4_Pos)                     /*!< CREG DMAMUX: DMAMUXCH4 Mask         */
#define CREG_DMAMUX_DMAMUXCH5_Pos                             10                                                        /*!< CREG DMAMUX: DMAMUXCH5 Position     */
#define CREG_DMAMUX_DMAMUXCH5_Msk                             (0x03UL << CREG_DMAMUX_DMAMUXCH5_Pos)                     /*!< CREG DMAMUX: DMAMUXCH5 Mask         */
#define CREG_DMAMUX_DMAMUXCH6_Pos                             12                                                        /*!< CREG DMAMUX: DMAMUXCH6 Position     */
#define CREG_DMAMUX_DMAMUXCH6_Msk                             (0x03UL << CREG_DMAMUX_DMAMUXCH6_Pos)                     /*!< CREG DMAMUX: DMAMUXCH6 Mask         */
#define CREG_DMAMUX_DMAMUXCH7_Pos                             14                                                        /*!< CREG DMAMUX: DMAMUXCH7 Position     */
#define CREG_DMAMUX_DMAMUXCH7_Msk                             (0x03UL << CREG_DMAMUX_DMAMUXCH7_Pos)                     /*!< CREG DMAMUX: DMAMUXCH7 Mask         */
#define CREG_DMAMUX_DMAMUXCH8_Pos                             16                                                        /*!< CREG DMAMUX: DMAMUXCH8 Position     */
#define CREG_DMAMUX_DMAMUXCH8_Msk                             (0x03UL << CREG_DMAMUX_DMAMUXCH8_Pos)                     /*!< CREG DMAMUX: DMAMUXCH8 Mask         */
#define CREG_DMAMUX_DMAMUXCH9_Pos                             18                                                        /*!< CREG DMAMUX: DMAMUXCH9 Position     */
#define CREG_DMAMUX_DMAMUXCH9_Msk                             (0x03UL << CREG_DMAMUX_DMAMUXCH9_Pos)                     /*!< CREG DMAMUX: DMAMUXCH9 Mask         */
#define CREG_DMAMUX_DMAMUXCH10_Pos                            20                                                        /*!< CREG DMAMUX: DMAMUXCH10 Position    */
#define CREG_DMAMUX_DMAMUXCH10_Msk                            (0x03UL << CREG_DMAMUX_DMAMUXCH10_Pos)                    /*!< CREG DMAMUX: DMAMUXCH10 Mask        */
#define CREG_DMAMUX_DMAMUXCH11_Pos                            22                                                        /*!< CREG DMAMUX: DMAMUXCH11 Position    */
#define CREG_DMAMUX_DMAMUXCH11_Msk                            (0x03UL << CREG_DMAMUX_DMAMUXCH11_Pos)                    /*!< CREG DMAMUX: DMAMUXCH11 Mask        */
#define CREG_DMAMUX_DMAMUXCH12_Pos                            24                                                        /*!< CREG DMAMUX: DMAMUXCH12 Position    */
#define CREG_DMAMUX_DMAMUXCH12_Msk                            (0x03UL << CREG_DMAMUX_DMAMUXCH12_Pos)                    /*!< CREG DMAMUX: DMAMUXCH12 Mask        */
#define CREG_DMAMUX_DMAMUXCH13_Pos                            26                                                        /*!< CREG DMAMUX: DMAMUXCH13 Position    */
#define CREG_DMAMUX_DMAMUXCH13_Msk                            (0x03UL << CREG_DMAMUX_DMAMUXCH13_Pos)                    /*!< CREG DMAMUX: DMAMUXCH13 Mask        */
#define CREG_DMAMUX_DMAMUXCH14_Pos                            28                                                        /*!< CREG DMAMUX: DMAMUXCH14 Position    */
#define CREG_DMAMUX_DMAMUXCH14_Msk                            (0x03UL << CREG_DMAMUX_DMAMUXCH14_Pos)                    /*!< CREG DMAMUX: DMAMUXCH14 Mask        */
#define CREG_DMAMUX_DMAMUXCH15_Pos                            30                                                        /*!< CREG DMAMUX: DMAMUXCH15 Position    */
#define CREG_DMAMUX_DMAMUXCH15_Msk                            (0x03UL << CREG_DMAMUX_DMAMUXCH15_Pos)                    /*!< CREG DMAMUX: DMAMUXCH15 Mask        */

// ---------------------------------------  CREG_ETBCFG  ------------------------------------------
#define CREG_ETBCFG_ETB_Pos                                   0                                                         /*!< CREG ETBCFG: ETB Position           */
#define CREG_ETBCFG_ETB_Msk                                   (0x01UL << CREG_ETBCFG_ETB_Pos)                           /*!< CREG ETBCFG: ETB Mask               */

// ---------------------------------------  CREG_CREG6  -------------------------------------------
#define CREG_CREG6_ETHMODE_Pos                                0                                                         /*!< CREG CREG6: ETHMODE Position        */
#define CREG_CREG6_ETHMODE_Msk                                (0x07UL << CREG_CREG6_ETHMODE_Pos)                        /*!< CREG CREG6: ETHMODE Mask            */
#define CREG_CREG6_TIMCTRL_Pos                                4                                                         /*!< CREG CREG6: TIMCTRL Position        */
#define CREG_CREG6_TIMCTRL_Msk                                (0x01UL << CREG_CREG6_TIMCTRL_Pos)                        /*!< CREG CREG6: TIMCTRL Mask            */
#define CREG_CREG6_I2S0_TX_SCK_IN_SEL_Pos                     12                                                        /*!< CREG CREG6: I2S0_TX_SCK_IN_SEL Position */
#define CREG_CREG6_I2S0_TX_SCK_IN_SEL_Msk                     (0x01UL << CREG_CREG6_I2S0_TX_SCK_IN_SEL_Pos)             /*!< CREG CREG6: I2S0_TX_SCK_IN_SEL Mask */
#define CREG_CREG6_I2S0_RX_SCK_IN_SEL_Pos                     13                                                        /*!< CREG CREG6: I2S0_RX_SCK_IN_SEL Position */
#define CREG_CREG6_I2S0_RX_SCK_IN_SEL_Msk                     (0x01UL << CREG_CREG6_I2S0_RX_SCK_IN_SEL_Pos)             /*!< CREG CREG6: I2S0_RX_SCK_IN_SEL Mask */
#define CREG_CREG6_I2S1_TX_SCK_IN_SEL_Pos                     14                                                        /*!< CREG CREG6: I2S1_TX_SCK_IN_SEL Position */
#define CREG_CREG6_I2S1_TX_SCK_IN_SEL_Msk                     (0x01UL << CREG_CREG6_I2S1_TX_SCK_IN_SEL_Pos)             /*!< CREG CREG6: I2S1_TX_SCK_IN_SEL Mask */
#define CREG_CREG6_I2S1_RX_SCK_IN_SEL_Pos                     15                                                        /*!< CREG CREG6: I2S1_RX_SCK_IN_SEL Position */
#define CREG_CREG6_I2S1_RX_SCK_IN_SEL_Msk                     (0x01UL << CREG_CREG6_I2S1_RX_SCK_IN_SEL_Pos)             /*!< CREG CREG6: I2S1_RX_SCK_IN_SEL Mask */
#define CREG_CREG6_EMC_CLK_SEL_Pos                            16                                                        /*!< CREG CREG6: EMC_CLK_SEL Position    */
#define CREG_CREG6_EMC_CLK_SEL_Msk                            (0x01UL << CREG_CREG6_EMC_CLK_SEL_Pos)                    /*!< CREG CREG6: EMC_CLK_SEL Mask        */

// -------------------------------------  CREG_M4TXEVENT  -----------------------------------------
#define CREG_M4TXEVENT_TXEVCLR_Pos                            0                                                         /*!< CREG M4TXEVENT: TXEVCLR Position    */
#define CREG_M4TXEVENT_TXEVCLR_Msk                            (0x01UL << CREG_M4TXEVENT_TXEVCLR_Pos)                    /*!< CREG M4TXEVENT: TXEVCLR Mask        */

// ---------------------------------------  CREG_CHIPID  ------------------------------------------
#define CREG_CHIPID_ID_Pos                                    0                                                         /*!< CREG CHIPID: ID Position            */
#define CREG_CHIPID_ID_Msk                                    (0xffffffffUL << CREG_CHIPID_ID_Pos)                      /*!< CREG CHIPID: ID Mask                */

// -------------------------------------  CREG_M0TXEVENT  -----------------------------------------
#define CREG_M0TXEVENT_TXEVCLR_Pos                            0                                                         /*!< CREG M0TXEVENT: TXEVCLR Position    */
#define CREG_M0TXEVENT_TXEVCLR_Msk                            (0x01UL << CREG_M0TXEVENT_TXEVCLR_Pos)                    /*!< CREG M0TXEVENT: TXEVCLR Mask        */

// ------------------------------------  CREG_M0APPMEMMAP  ----------------------------------------
#define CREG_M0APPMEMMAP_M0APPMAP_Pos                         12                                                        /*!< CREG M0APPMEMMAP: M0APPMAP Position */
#define CREG_M0APPMEMMAP_M0APPMAP_Msk                         (0x000fffffUL << CREG_M0APPMEMMAP_M0APPMAP_Pos)           /*!< CREG M0APPMEMMAP: M0APPMAP Mask     */


// ------------------------------------------------------------------------------------------------
// -----                              EVENTROUTER Position & Mask                             -----
// ------------------------------------------------------------------------------------------------


// ------------------------------------  EVENTROUTER_HILO  ----------------------------------------
#define EVENTROUTER_HILO_WAKEUP0_L_Pos                        0                                                         /*!< EVENTROUTER HILO: WAKEUP0_L Position */
#define EVENTROUTER_HILO_WAKEUP0_L_Msk                        (0x01UL << EVENTROUTER_HILO_WAKEUP0_L_Pos)                /*!< EVENTROUTER HILO: WAKEUP0_L Mask    */
#define EVENTROUTER_HILO_WAKEUP1_L_Pos                        1                                                         /*!< EVENTROUTER HILO: WAKEUP1_L Position */
#define EVENTROUTER_HILO_WAKEUP1_L_Msk                        (0x01UL << EVENTROUTER_HILO_WAKEUP1_L_Pos)                /*!< EVENTROUTER HILO: WAKEUP1_L Mask    */
#define EVENTROUTER_HILO_WAKEUP2_L_Pos                        2                                                         /*!< EVENTROUTER HILO: WAKEUP2_L Position */
#define EVENTROUTER_HILO_WAKEUP2_L_Msk                        (0x01UL << EVENTROUTER_HILO_WAKEUP2_L_Pos)                /*!< EVENTROUTER HILO: WAKEUP2_L Mask    */
#define EVENTROUTER_HILO_WAKEUP3_L_Pos                        3                                                         /*!< EVENTROUTER HILO: WAKEUP3_L Position */
#define EVENTROUTER_HILO_WAKEUP3_L_Msk                        (0x01UL << EVENTROUTER_HILO_WAKEUP3_L_Pos)                /*!< EVENTROUTER HILO: WAKEUP3_L Mask    */
#define EVENTROUTER_HILO_ATIMER_L_Pos                         4                                                         /*!< EVENTROUTER HILO: ATIMER_L Position */
#define EVENTROUTER_HILO_ATIMER_L_Msk                         (0x01UL << EVENTROUTER_HILO_ATIMER_L_Pos)                 /*!< EVENTROUTER HILO: ATIMER_L Mask     */
#define EVENTROUTER_HILO_RTC_L_Pos                            5                                                         /*!< EVENTROUTER HILO: RTC_L Position    */
#define EVENTROUTER_HILO_RTC_L_Msk                            (0x01UL << EVENTROUTER_HILO_RTC_L_Pos)                    /*!< EVENTROUTER HILO: RTC_L Mask        */
#define EVENTROUTER_HILO_BOD_L_Pos                            6                                                         /*!< EVENTROUTER HILO: BOD_L Position    */
#define EVENTROUTER_HILO_BOD_L_Msk                            (0x01UL << EVENTROUTER_HILO_BOD_L_Pos)                    /*!< EVENTROUTER HILO: BOD_L Mask        */
#define EVENTROUTER_HILO_WWDT_L_Pos                           7                                                         /*!< EVENTROUTER HILO: WWDT_L Position   */
#define EVENTROUTER_HILO_WWDT_L_Msk                           (0x01UL << EVENTROUTER_HILO_WWDT_L_Pos)                   /*!< EVENTROUTER HILO: WWDT_L Mask       */
#define EVENTROUTER_HILO_ETH_L_Pos                            8                                                         /*!< EVENTROUTER HILO: ETH_L Position    */
#define EVENTROUTER_HILO_ETH_L_Msk                            (0x01UL << EVENTROUTER_HILO_ETH_L_Pos)                    /*!< EVENTROUTER HILO: ETH_L Mask        */
#define EVENTROUTER_HILO_USB0_L_Pos                           9                                                         /*!< EVENTROUTER HILO: USB0_L Position   */
#define EVENTROUTER_HILO_USB0_L_Msk                           (0x01UL << EVENTROUTER_HILO_USB0_L_Pos)                   /*!< EVENTROUTER HILO: USB0_L Mask       */
#define EVENTROUTER_HILO_USB1_L_Pos                           10                                                        /*!< EVENTROUTER HILO: USB1_L Position   */
#define EVENTROUTER_HILO_USB1_L_Msk                           (0x01UL << EVENTROUTER_HILO_USB1_L_Pos)                   /*!< EVENTROUTER HILO: USB1_L Mask       */
#define EVENTROUTER_HILO_SDMMC_L_Pos                          11                                                        /*!< EVENTROUTER HILO: SDMMC_L Position  */
#define EVENTROUTER_HILO_SDMMC_L_Msk                          (0x01UL << EVENTROUTER_HILO_SDMMC_L_Pos)                  /*!< EVENTROUTER HILO: SDMMC_L Mask      */
#define EVENTROUTER_HILO_CAN_L_Pos                            12                                                        /*!< EVENTROUTER HILO: CAN_L Position    */
#define EVENTROUTER_HILO_CAN_L_Msk                            (0x01UL << EVENTROUTER_HILO_CAN_L_Pos)                    /*!< EVENTROUTER HILO: CAN_L Mask        */
#define EVENTROUTER_HILO_TIM2_L_Pos                           13                                                        /*!< EVENTROUTER HILO: TIM2_L Position   */
#define EVENTROUTER_HILO_TIM2_L_Msk                           (0x01UL << EVENTROUTER_HILO_TIM2_L_Pos)                   /*!< EVENTROUTER HILO: TIM2_L Mask       */
#define EVENTROUTER_HILO_TIM6_L_Pos                           14                                                        /*!< EVENTROUTER HILO: TIM6_L Position   */
#define EVENTROUTER_HILO_TIM6_L_Msk                           (0x01UL << EVENTROUTER_HILO_TIM6_L_Pos)                   /*!< EVENTROUTER HILO: TIM6_L Mask       */
#define EVENTROUTER_HILO_QEI_L_Pos                            15                                                        /*!< EVENTROUTER HILO: QEI_L Position    */
#define EVENTROUTER_HILO_QEI_L_Msk                            (0x01UL << EVENTROUTER_HILO_QEI_L_Pos)                    /*!< EVENTROUTER HILO: QEI_L Mask        */
#define EVENTROUTER_HILO_TIM14_L_Pos                          16                                                        /*!< EVENTROUTER HILO: TIM14_L Position  */
#define EVENTROUTER_HILO_TIM14_L_Msk                          (0x01UL << EVENTROUTER_HILO_TIM14_L_Pos)                  /*!< EVENTROUTER HILO: TIM14_L Mask      */
#define EVENTROUTER_HILO_RESET_L_Pos                          19                                                        /*!< EVENTROUTER HILO: RESET_L Position  */
#define EVENTROUTER_HILO_RESET_L_Msk                          (0x01UL << EVENTROUTER_HILO_RESET_L_Pos)                  /*!< EVENTROUTER HILO: RESET_L Mask      */

// ------------------------------------  EVENTROUTER_EDGE  ----------------------------------------
#define EVENTROUTER_EDGE_WAKEUP0_E_Pos                        0                                                         /*!< EVENTROUTER EDGE: WAKEUP0_E Position */
#define EVENTROUTER_EDGE_WAKEUP0_E_Msk                        (0x01UL << EVENTROUTER_EDGE_WAKEUP0_E_Pos)                /*!< EVENTROUTER EDGE: WAKEUP0_E Mask    */
#define EVENTROUTER_EDGE_WAKEUP1_E_Pos                        1                                                         /*!< EVENTROUTER EDGE: WAKEUP1_E Position */
#define EVENTROUTER_EDGE_WAKEUP1_E_Msk                        (0x01UL << EVENTROUTER_EDGE_WAKEUP1_E_Pos)                /*!< EVENTROUTER EDGE: WAKEUP1_E Mask    */
#define EVENTROUTER_EDGE_WAKEUP2_E_Pos                        2                                                         /*!< EVENTROUTER EDGE: WAKEUP2_E Position */
#define EVENTROUTER_EDGE_WAKEUP2_E_Msk                        (0x01UL << EVENTROUTER_EDGE_WAKEUP2_E_Pos)                /*!< EVENTROUTER EDGE: WAKEUP2_E Mask    */
#define EVENTROUTER_EDGE_WAKEUP3_E_Pos                        3                                                         /*!< EVENTROUTER EDGE: WAKEUP3_E Position */
#define EVENTROUTER_EDGE_WAKEUP3_E_Msk                        (0x01UL << EVENTROUTER_EDGE_WAKEUP3_E_Pos)                /*!< EVENTROUTER EDGE: WAKEUP3_E Mask    */
#define EVENTROUTER_EDGE_ATIMER_E_Pos                         4                                                         /*!< EVENTROUTER EDGE: ATIMER_E Position */
#define EVENTROUTER_EDGE_ATIMER_E_Msk                         (0x01UL << EVENTROUTER_EDGE_ATIMER_E_Pos)                 /*!< EVENTROUTER EDGE: ATIMER_E Mask     */
#define EVENTROUTER_EDGE_RTC_E_Pos                            5                                                         /*!< EVENTROUTER EDGE: RTC_E Position    */
#define EVENTROUTER_EDGE_RTC_E_Msk                            (0x01UL << EVENTROUTER_EDGE_RTC_E_Pos)                    /*!< EVENTROUTER EDGE: RTC_E Mask        */
#define EVENTROUTER_EDGE_BOD_E_Pos                            6                                                         /*!< EVENTROUTER EDGE: BOD_E Position    */
#define EVENTROUTER_EDGE_BOD_E_Msk                            (0x01UL << EVENTROUTER_EDGE_BOD_E_Pos)                    /*!< EVENTROUTER EDGE: BOD_E Mask        */
#define EVENTROUTER_EDGE_WWDT_E_Pos                           7                                                         /*!< EVENTROUTER EDGE: WWDT_E Position   */
#define EVENTROUTER_EDGE_WWDT_E_Msk                           (0x01UL << EVENTROUTER_EDGE_WWDT_E_Pos)                   /*!< EVENTROUTER EDGE: WWDT_E Mask       */
#define EVENTROUTER_EDGE_ETH_E_Pos                            8                                                         /*!< EVENTROUTER EDGE: ETH_E Position    */
#define EVENTROUTER_EDGE_ETH_E_Msk                            (0x01UL << EVENTROUTER_EDGE_ETH_E_Pos)                    /*!< EVENTROUTER EDGE: ETH_E Mask        */
#define EVENTROUTER_EDGE_USB0_E_Pos                           9                                                         /*!< EVENTROUTER EDGE: USB0_E Position   */
#define EVENTROUTER_EDGE_USB0_E_Msk                           (0x01UL << EVENTROUTER_EDGE_USB0_E_Pos)                   /*!< EVENTROUTER EDGE: USB0_E Mask       */
#define EVENTROUTER_EDGE_USB1_E_Pos                           10                                                        /*!< EVENTROUTER EDGE: USB1_E Position   */
#define EVENTROUTER_EDGE_USB1_E_Msk                           (0x01UL << EVENTROUTER_EDGE_USB1_E_Pos)                   /*!< EVENTROUTER EDGE: USB1_E Mask       */
#define EVENTROUTER_EDGE_SDMMC_E_Pos                          11                                                        /*!< EVENTROUTER EDGE: SDMMC_E Position  */
#define EVENTROUTER_EDGE_SDMMC_E_Msk                          (0x01UL << EVENTROUTER_EDGE_SDMMC_E_Pos)                  /*!< EVENTROUTER EDGE: SDMMC_E Mask      */
#define EVENTROUTER_EDGE_CAN_E_Pos                            12                                                        /*!< EVENTROUTER EDGE: CAN_E Position    */
#define EVENTROUTER_EDGE_CAN_E_Msk                            (0x01UL << EVENTROUTER_EDGE_CAN_E_Pos)                    /*!< EVENTROUTER EDGE: CAN_E Mask        */
#define EVENTROUTER_EDGE_TIM2_E_Pos                           13                                                        /*!< EVENTROUTER EDGE: TIM2_E Position   */
#define EVENTROUTER_EDGE_TIM2_E_Msk                           (0x01UL << EVENTROUTER_EDGE_TIM2_E_Pos)                   /*!< EVENTROUTER EDGE: TIM2_E Mask       */
#define EVENTROUTER_EDGE_TIM6_E_Pos                           14                                                        /*!< EVENTROUTER EDGE: TIM6_E Position   */
#define EVENTROUTER_EDGE_TIM6_E_Msk                           (0x01UL << EVENTROUTER_EDGE_TIM6_E_Pos)                   /*!< EVENTROUTER EDGE: TIM6_E Mask       */
#define EVENTROUTER_EDGE_QEI_E_Pos                            15                                                        /*!< EVENTROUTER EDGE: QEI_E Position    */
#define EVENTROUTER_EDGE_QEI_E_Msk                            (0x01UL << EVENTROUTER_EDGE_QEI_E_Pos)                    /*!< EVENTROUTER EDGE: QEI_E Mask        */
#define EVENTROUTER_EDGE_TIM14_E_Pos                          16                                                        /*!< EVENTROUTER EDGE: TIM14_E Position  */
#define EVENTROUTER_EDGE_TIM14_E_Msk                          (0x01UL << EVENTROUTER_EDGE_TIM14_E_Pos)                  /*!< EVENTROUTER EDGE: TIM14_E Mask      */
#define EVENTROUTER_EDGE_RESET_E_Pos                          19                                                        /*!< EVENTROUTER EDGE: RESET_E Position  */
#define EVENTROUTER_EDGE_RESET_E_Msk                          (0x01UL << EVENTROUTER_EDGE_RESET_E_Pos)                  /*!< EVENTROUTER EDGE: RESET_E Mask      */

// -----------------------------------  EVENTROUTER_CLR_EN  ---------------------------------------
#define EVENTROUTER_CLR_EN_WAKEUP0_CLREN_Pos                  0                                                         /*!< EVENTROUTER CLR_EN: WAKEUP0_CLREN Position */
#define EVENTROUTER_CLR_EN_WAKEUP0_CLREN_Msk                  (0x01UL << EVENTROUTER_CLR_EN_WAKEUP0_CLREN_Pos)          /*!< EVENTROUTER CLR_EN: WAKEUP0_CLREN Mask */
#define EVENTROUTER_CLR_EN_WAKEUP1_CLREN_Pos                  1                                                         /*!< EVENTROUTER CLR_EN: WAKEUP1_CLREN Position */
#define EVENTROUTER_CLR_EN_WAKEUP1_CLREN_Msk                  (0x01UL << EVENTROUTER_CLR_EN_WAKEUP1_CLREN_Pos)          /*!< EVENTROUTER CLR_EN: WAKEUP1_CLREN Mask */
#define EVENTROUTER_CLR_EN_WAKEUP2_CLREN_Pos                  2                                                         /*!< EVENTROUTER CLR_EN: WAKEUP2_CLREN Position */
#define EVENTROUTER_CLR_EN_WAKEUP2_CLREN_Msk                  (0x01UL << EVENTROUTER_CLR_EN_WAKEUP2_CLREN_Pos)          /*!< EVENTROUTER CLR_EN: WAKEUP2_CLREN Mask */
#define EVENTROUTER_CLR_EN_WAKEUP3_CLREN_Pos                  3                                                         /*!< EVENTROUTER CLR_EN: WAKEUP3_CLREN Position */
#define EVENTROUTER_CLR_EN_WAKEUP3_CLREN_Msk                  (0x01UL << EVENTROUTER_CLR_EN_WAKEUP3_CLREN_Pos)          /*!< EVENTROUTER CLR_EN: WAKEUP3_CLREN Mask */
#define EVENTROUTER_CLR_EN_ATIMER_CLREN_Pos                   4                                                         /*!< EVENTROUTER CLR_EN: ATIMER_CLREN Position */
#define EVENTROUTER_CLR_EN_ATIMER_CLREN_Msk                   (0x01UL << EVENTROUTER_CLR_EN_ATIMER_CLREN_Pos)           /*!< EVENTROUTER CLR_EN: ATIMER_CLREN Mask */
#define EVENTROUTER_CLR_EN_RTC_CLREN_Pos                      5                                                         /*!< EVENTROUTER CLR_EN: RTC_CLREN Position */
#define EVENTROUTER_CLR_EN_RTC_CLREN_Msk                      (0x01UL << EVENTROUTER_CLR_EN_RTC_CLREN_Pos)              /*!< EVENTROUTER CLR_EN: RTC_CLREN Mask  */
#define EVENTROUTER_CLR_EN_BOD_CLREN_Pos                      6                                                         /*!< EVENTROUTER CLR_EN: BOD_CLREN Position */
#define EVENTROUTER_CLR_EN_BOD_CLREN_Msk                      (0x01UL << EVENTROUTER_CLR_EN_BOD_CLREN_Pos)              /*!< EVENTROUTER CLR_EN: BOD_CLREN Mask  */
#define EVENTROUTER_CLR_EN_WWDT_CLREN_Pos                     7                                                         /*!< EVENTROUTER CLR_EN: WWDT_CLREN Position */
#define EVENTROUTER_CLR_EN_WWDT_CLREN_Msk                     (0x01UL << EVENTROUTER_CLR_EN_WWDT_CLREN_Pos)             /*!< EVENTROUTER CLR_EN: WWDT_CLREN Mask */
#define EVENTROUTER_CLR_EN_ETH_CLREN_Pos                      8                                                         /*!< EVENTROUTER CLR_EN: ETH_CLREN Position */
#define EVENTROUTER_CLR_EN_ETH_CLREN_Msk                      (0x01UL << EVENTROUTER_CLR_EN_ETH_CLREN_Pos)              /*!< EVENTROUTER CLR_EN: ETH_CLREN Mask  */
#define EVENTROUTER_CLR_EN_USB0_CLREN_Pos                     9                                                         /*!< EVENTROUTER CLR_EN: USB0_CLREN Position */
#define EVENTROUTER_CLR_EN_USB0_CLREN_Msk                     (0x01UL << EVENTROUTER_CLR_EN_USB0_CLREN_Pos)             /*!< EVENTROUTER CLR_EN: USB0_CLREN Mask */
#define EVENTROUTER_CLR_EN_USB1_CLREN_Pos                     10                                                        /*!< EVENTROUTER CLR_EN: USB1_CLREN Position */
#define EVENTROUTER_CLR_EN_USB1_CLREN_Msk                     (0x01UL << EVENTROUTER_CLR_EN_USB1_CLREN_Pos)             /*!< EVENTROUTER CLR_EN: USB1_CLREN Mask */
#define EVENTROUTER_CLR_EN_SDMMC_CLREN_Pos                    11                                                        /*!< EVENTROUTER CLR_EN: SDMMC_CLREN Position */
#define EVENTROUTER_CLR_EN_SDMMC_CLREN_Msk                    (0x01UL << EVENTROUTER_CLR_EN_SDMMC_CLREN_Pos)            /*!< EVENTROUTER CLR_EN: SDMMC_CLREN Mask */
#define EVENTROUTER_CLR_EN_CAN_CLREN_Pos                      12                                                        /*!< EVENTROUTER CLR_EN: CAN_CLREN Position */
#define EVENTROUTER_CLR_EN_CAN_CLREN_Msk                      (0x01UL << EVENTROUTER_CLR_EN_CAN_CLREN_Pos)              /*!< EVENTROUTER CLR_EN: CAN_CLREN Mask  */
#define EVENTROUTER_CLR_EN_TIM2_CLREN_Pos                     13                                                        /*!< EVENTROUTER CLR_EN: TIM2_CLREN Position */
#define EVENTROUTER_CLR_EN_TIM2_CLREN_Msk                     (0x01UL << EVENTROUTER_CLR_EN_TIM2_CLREN_Pos)             /*!< EVENTROUTER CLR_EN: TIM2_CLREN Mask */
#define EVENTROUTER_CLR_EN_TIM6_CLREN_Pos                     14                                                        /*!< EVENTROUTER CLR_EN: TIM6_CLREN Position */
#define EVENTROUTER_CLR_EN_TIM6_CLREN_Msk                     (0x01UL << EVENTROUTER_CLR_EN_TIM6_CLREN_Pos)             /*!< EVENTROUTER CLR_EN: TIM6_CLREN Mask */
#define EVENTROUTER_CLR_EN_QEI_CLREN_Pos                      15                                                        /*!< EVENTROUTER CLR_EN: QEI_CLREN Position */
#define EVENTROUTER_CLR_EN_QEI_CLREN_Msk                      (0x01UL << EVENTROUTER_CLR_EN_QEI_CLREN_Pos)              /*!< EVENTROUTER CLR_EN: QEI_CLREN Mask  */
#define EVENTROUTER_CLR_EN_TIM14_CLREN_Pos                    16                                                        /*!< EVENTROUTER CLR_EN: TIM14_CLREN Position */
#define EVENTROUTER_CLR_EN_TIM14_CLREN_Msk                    (0x01UL << EVENTROUTER_CLR_EN_TIM14_CLREN_Pos)            /*!< EVENTROUTER CLR_EN: TIM14_CLREN Mask */
#define EVENTROUTER_CLR_EN_RESET_CLREN_Pos                    19                                                        /*!< EVENTROUTER CLR_EN: RESET_CLREN Position */
#define EVENTROUTER_CLR_EN_RESET_CLREN_Msk                    (0x01UL << EVENTROUTER_CLR_EN_RESET_CLREN_Pos)            /*!< EVENTROUTER CLR_EN: RESET_CLREN Mask */

// -----------------------------------  EVENTROUTER_SET_EN  ---------------------------------------
#define EVENTROUTER_SET_EN_WAKEUP0_SETEN_Pos                  0                                                         /*!< EVENTROUTER SET_EN: WAKEUP0_SETEN Position */
#define EVENTROUTER_SET_EN_WAKEUP0_SETEN_Msk                  (0x01UL << EVENTROUTER_SET_EN_WAKEUP0_SETEN_Pos)          /*!< EVENTROUTER SET_EN: WAKEUP0_SETEN Mask */
#define EVENTROUTER_SET_EN_WAKEUP1_SETEN_Pos                  1                                                         /*!< EVENTROUTER SET_EN: WAKEUP1_SETEN Position */
#define EVENTROUTER_SET_EN_WAKEUP1_SETEN_Msk                  (0x01UL << EVENTROUTER_SET_EN_WAKEUP1_SETEN_Pos)          /*!< EVENTROUTER SET_EN: WAKEUP1_SETEN Mask */
#define EVENTROUTER_SET_EN_WAKEUP2_SETEN_Pos                  2                                                         /*!< EVENTROUTER SET_EN: WAKEUP2_SETEN Position */
#define EVENTROUTER_SET_EN_WAKEUP2_SETEN_Msk                  (0x01UL << EVENTROUTER_SET_EN_WAKEUP2_SETEN_Pos)          /*!< EVENTROUTER SET_EN: WAKEUP2_SETEN Mask */
#define EVENTROUTER_SET_EN_WAKEUP3_SETEN_Pos                  3                                                         /*!< EVENTROUTER SET_EN: WAKEUP3_SETEN Position */
#define EVENTROUTER_SET_EN_WAKEUP3_SETEN_Msk                  (0x01UL << EVENTROUTER_SET_EN_WAKEUP3_SETEN_Pos)          /*!< EVENTROUTER SET_EN: WAKEUP3_SETEN Mask */
#define EVENTROUTER_SET_EN_ATIMER_SETEN_Pos                   4                                                         /*!< EVENTROUTER SET_EN: ATIMER_SETEN Position */
#define EVENTROUTER_SET_EN_ATIMER_SETEN_Msk                   (0x01UL << EVENTROUTER_SET_EN_ATIMER_SETEN_Pos)           /*!< EVENTROUTER SET_EN: ATIMER_SETEN Mask */
#define EVENTROUTER_SET_EN_RTC_SETEN_Pos                      5                                                         /*!< EVENTROUTER SET_EN: RTC_SETEN Position */
#define EVENTROUTER_SET_EN_RTC_SETEN_Msk                      (0x01UL << EVENTROUTER_SET_EN_RTC_SETEN_Pos)              /*!< EVENTROUTER SET_EN: RTC_SETEN Mask  */
#define EVENTROUTER_SET_EN_BOD_SETEN_Pos                      6                                                         /*!< EVENTROUTER SET_EN: BOD_SETEN Position */
#define EVENTROUTER_SET_EN_BOD_SETEN_Msk                      (0x01UL << EVENTROUTER_SET_EN_BOD_SETEN_Pos)              /*!< EVENTROUTER SET_EN: BOD_SETEN Mask  */
#define EVENTROUTER_SET_EN_WWDT_SETEN_Pos                     7                                                         /*!< EVENTROUTER SET_EN: WWDT_SETEN Position */
#define EVENTROUTER_SET_EN_WWDT_SETEN_Msk                     (0x01UL << EVENTROUTER_SET_EN_WWDT_SETEN_Pos)             /*!< EVENTROUTER SET_EN: WWDT_SETEN Mask */
#define EVENTROUTER_SET_EN_ETH_SETEN_Pos                      8                                                         /*!< EVENTROUTER SET_EN: ETH_SETEN Position */
#define EVENTROUTER_SET_EN_ETH_SETEN_Msk                      (0x01UL << EVENTROUTER_SET_EN_ETH_SETEN_Pos)              /*!< EVENTROUTER SET_EN: ETH_SETEN Mask  */
#define EVENTROUTER_SET_EN_USB0_SETEN_Pos                     9                                                         /*!< EVENTROUTER SET_EN: USB0_SETEN Position */
#define EVENTROUTER_SET_EN_USB0_SETEN_Msk                     (0x01UL << EVENTROUTER_SET_EN_USB0_SETEN_Pos)             /*!< EVENTROUTER SET_EN: USB0_SETEN Mask */
#define EVENTROUTER_SET_EN_USB1_SETEN_Pos                     10                                                        /*!< EVENTROUTER SET_EN: USB1_SETEN Position */
#define EVENTROUTER_SET_EN_USB1_SETEN_Msk                     (0x01UL << EVENTROUTER_SET_EN_USB1_SETEN_Pos)             /*!< EVENTROUTER SET_EN: USB1_SETEN Mask */
#define EVENTROUTER_SET_EN_SDMMC_SETEN_Pos                    11                                                        /*!< EVENTROUTER SET_EN: SDMMC_SETEN Position */
#define EVENTROUTER_SET_EN_SDMMC_SETEN_Msk                    (0x01UL << EVENTROUTER_SET_EN_SDMMC_SETEN_Pos)            /*!< EVENTROUTER SET_EN: SDMMC_SETEN Mask */
#define EVENTROUTER_SET_EN_CAN_SETEN_Pos                      12                                                        /*!< EVENTROUTER SET_EN: CAN_SETEN Position */
#define EVENTROUTER_SET_EN_CAN_SETEN_Msk                      (0x01UL << EVENTROUTER_SET_EN_CAN_SETEN_Pos)              /*!< EVENTROUTER SET_EN: CAN_SETEN Mask  */
#define EVENTROUTER_SET_EN_TIM2_SETEN_Pos                     13                                                        /*!< EVENTROUTER SET_EN: TIM2_SETEN Position */
#define EVENTROUTER_SET_EN_TIM2_SETEN_Msk                     (0x01UL << EVENTROUTER_SET_EN_TIM2_SETEN_Pos)             /*!< EVENTROUTER SET_EN: TIM2_SETEN Mask */
#define EVENTROUTER_SET_EN_TIM6_SETEN_Pos                     14                                                        /*!< EVENTROUTER SET_EN: TIM6_SETEN Position */
#define EVENTROUTER_SET_EN_TIM6_SETEN_Msk                     (0x01UL << EVENTROUTER_SET_EN_TIM6_SETEN_Pos)             /*!< EVENTROUTER SET_EN: TIM6_SETEN Mask */
#define EVENTROUTER_SET_EN_QEI_SETEN_Pos                      15                                                        /*!< EVENTROUTER SET_EN: QEI_SETEN Position */
#define EVENTROUTER_SET_EN_QEI_SETEN_Msk                      (0x01UL << EVENTROUTER_SET_EN_QEI_SETEN_Pos)              /*!< EVENTROUTER SET_EN: QEI_SETEN Mask  */
#define EVENTROUTER_SET_EN_TIM14_SETEN_Pos                    16                                                        /*!< EVENTROUTER SET_EN: TIM14_SETEN Position */
#define EVENTROUTER_SET_EN_TIM14_SETEN_Msk                    (0x01UL << EVENTROUTER_SET_EN_TIM14_SETEN_Pos)            /*!< EVENTROUTER SET_EN: TIM14_SETEN Mask */
#define EVENTROUTER_SET_EN_RESET_SETEN_Pos                    19                                                        /*!< EVENTROUTER SET_EN: RESET_SETEN Position */
#define EVENTROUTER_SET_EN_RESET_SETEN_Msk                    (0x01UL << EVENTROUTER_SET_EN_RESET_SETEN_Pos)            /*!< EVENTROUTER SET_EN: RESET_SETEN Mask */

// -----------------------------------  EVENTROUTER_STATUS  ---------------------------------------
#define EVENTROUTER_STATUS_WAKEUP0_ST_Pos                     0                                                         /*!< EVENTROUTER STATUS: WAKEUP0_ST Position */
#define EVENTROUTER_STATUS_WAKEUP0_ST_Msk                     (0x01UL << EVENTROUTER_STATUS_WAKEUP0_ST_Pos)             /*!< EVENTROUTER STATUS: WAKEUP0_ST Mask */
#define EVENTROUTER_STATUS_WAKEUP1_ST_Pos                     1                                                         /*!< EVENTROUTER STATUS: WAKEUP1_ST Position */
#define EVENTROUTER_STATUS_WAKEUP1_ST_Msk                     (0x01UL << EVENTROUTER_STATUS_WAKEUP1_ST_Pos)             /*!< EVENTROUTER STATUS: WAKEUP1_ST Mask */
#define EVENTROUTER_STATUS_WAKEUP2_ST_Pos                     2                                                         /*!< EVENTROUTER STATUS: WAKEUP2_ST Position */
#define EVENTROUTER_STATUS_WAKEUP2_ST_Msk                     (0x01UL << EVENTROUTER_STATUS_WAKEUP2_ST_Pos)             /*!< EVENTROUTER STATUS: WAKEUP2_ST Mask */
#define EVENTROUTER_STATUS_WAKEUP3_ST_Pos                     3                                                         /*!< EVENTROUTER STATUS: WAKEUP3_ST Position */
#define EVENTROUTER_STATUS_WAKEUP3_ST_Msk                     (0x01UL << EVENTROUTER_STATUS_WAKEUP3_ST_Pos)             /*!< EVENTROUTER STATUS: WAKEUP3_ST Mask */
#define EVENTROUTER_STATUS_ATIMER_ST_Pos                      4                                                         /*!< EVENTROUTER STATUS: ATIMER_ST Position */
#define EVENTROUTER_STATUS_ATIMER_ST_Msk                      (0x01UL << EVENTROUTER_STATUS_ATIMER_ST_Pos)              /*!< EVENTROUTER STATUS: ATIMER_ST Mask  */
#define EVENTROUTER_STATUS_RTC_ST_Pos                         5                                                         /*!< EVENTROUTER STATUS: RTC_ST Position */
#define EVENTROUTER_STATUS_RTC_ST_Msk                         (0x01UL << EVENTROUTER_STATUS_RTC_ST_Pos)                 /*!< EVENTROUTER STATUS: RTC_ST Mask     */
#define EVENTROUTER_STATUS_BOD_ST_Pos                         6                                                         /*!< EVENTROUTER STATUS: BOD_ST Position */
#define EVENTROUTER_STATUS_BOD_ST_Msk                         (0x01UL << EVENTROUTER_STATUS_BOD_ST_Pos)                 /*!< EVENTROUTER STATUS: BOD_ST Mask     */
#define EVENTROUTER_STATUS_WWDT_ST_Pos                        7                                                         /*!< EVENTROUTER STATUS: WWDT_ST Position */
#define EVENTROUTER_STATUS_WWDT_ST_Msk                        (0x01UL << EVENTROUTER_STATUS_WWDT_ST_Pos)                /*!< EVENTROUTER STATUS: WWDT_ST Mask    */
#define EVENTROUTER_STATUS_ETH_ST_Pos                         8                                                         /*!< EVENTROUTER STATUS: ETH_ST Position */
#define EVENTROUTER_STATUS_ETH_ST_Msk                         (0x01UL << EVENTROUTER_STATUS_ETH_ST_Pos)                 /*!< EVENTROUTER STATUS: ETH_ST Mask     */
#define EVENTROUTER_STATUS_USB0_ST_Pos                        9                                                         /*!< EVENTROUTER STATUS: USB0_ST Position */
#define EVENTROUTER_STATUS_USB0_ST_Msk                        (0x01UL << EVENTROUTER_STATUS_USB0_ST_Pos)                /*!< EVENTROUTER STATUS: USB0_ST Mask    */
#define EVENTROUTER_STATUS_USB1_ST_Pos                        10                                                        /*!< EVENTROUTER STATUS: USB1_ST Position */
#define EVENTROUTER_STATUS_USB1_ST_Msk                        (0x01UL << EVENTROUTER_STATUS_USB1_ST_Pos)                /*!< EVENTROUTER STATUS: USB1_ST Mask    */
#define EVENTROUTER_STATUS_SDMMC_ST_Pos                       11                                                        /*!< EVENTROUTER STATUS: SDMMC_ST Position */
#define EVENTROUTER_STATUS_SDMMC_ST_Msk                       (0x01UL << EVENTROUTER_STATUS_SDMMC_ST_Pos)               /*!< EVENTROUTER STATUS: SDMMC_ST Mask   */
#define EVENTROUTER_STATUS_CAN_ST_Pos                         12                                                        /*!< EVENTROUTER STATUS: CAN_ST Position */
#define EVENTROUTER_STATUS_CAN_ST_Msk                         (0x01UL << EVENTROUTER_STATUS_CAN_ST_Pos)                 /*!< EVENTROUTER STATUS: CAN_ST Mask     */
#define EVENTROUTER_STATUS_TIM2_ST_Pos                        13                                                        /*!< EVENTROUTER STATUS: TIM2_ST Position */
#define EVENTROUTER_STATUS_TIM2_ST_Msk                        (0x01UL << EVENTROUTER_STATUS_TIM2_ST_Pos)                /*!< EVENTROUTER STATUS: TIM2_ST Mask    */
#define EVENTROUTER_STATUS_TIM6_ST_Pos                        14                                                        /*!< EVENTROUTER STATUS: TIM6_ST Position */
#define EVENTROUTER_STATUS_TIM6_ST_Msk                        (0x01UL << EVENTROUTER_STATUS_TIM6_ST_Pos)                /*!< EVENTROUTER STATUS: TIM6_ST Mask    */
#define EVENTROUTER_STATUS_QEI_ST_Pos                         15                                                        /*!< EVENTROUTER STATUS: QEI_ST Position */
#define EVENTROUTER_STATUS_QEI_ST_Msk                         (0x01UL << EVENTROUTER_STATUS_QEI_ST_Pos)                 /*!< EVENTROUTER STATUS: QEI_ST Mask     */
#define EVENTROUTER_STATUS_TIM14_ST_Pos                       16                                                        /*!< EVENTROUTER STATUS: TIM14_ST Position */
#define EVENTROUTER_STATUS_TIM14_ST_Msk                       (0x01UL << EVENTROUTER_STATUS_TIM14_ST_Pos)               /*!< EVENTROUTER STATUS: TIM14_ST Mask   */
#define EVENTROUTER_STATUS_RESET_ST_Pos                       19                                                        /*!< EVENTROUTER STATUS: RESET_ST Position */
#define EVENTROUTER_STATUS_RESET_ST_Msk                       (0x01UL << EVENTROUTER_STATUS_RESET_ST_Pos)               /*!< EVENTROUTER STATUS: RESET_ST Mask   */

// -----------------------------------  EVENTROUTER_ENABLE  ---------------------------------------
#define EVENTROUTER_ENABLE_WAKEUP0_EN_Pos                     0                                                         /*!< EVENTROUTER ENABLE: WAKEUP0_EN Position */
#define EVENTROUTER_ENABLE_WAKEUP0_EN_Msk                     (0x01UL << EVENTROUTER_ENABLE_WAKEUP0_EN_Pos)             /*!< EVENTROUTER ENABLE: WAKEUP0_EN Mask */
#define EVENTROUTER_ENABLE_WAKEUP1_EN_Pos                     1                                                         /*!< EVENTROUTER ENABLE: WAKEUP1_EN Position */
#define EVENTROUTER_ENABLE_WAKEUP1_EN_Msk                     (0x01UL << EVENTROUTER_ENABLE_WAKEUP1_EN_Pos)             /*!< EVENTROUTER ENABLE: WAKEUP1_EN Mask */
#define EVENTROUTER_ENABLE_WAKEUP2_EN_Pos                     2                                                         /*!< EVENTROUTER ENABLE: WAKEUP2_EN Position */
#define EVENTROUTER_ENABLE_WAKEUP2_EN_Msk                     (0x01UL << EVENTROUTER_ENABLE_WAKEUP2_EN_Pos)             /*!< EVENTROUTER ENABLE: WAKEUP2_EN Mask */
#define EVENTROUTER_ENABLE_WAKEUP3_EN_Pos                     3                                                         /*!< EVENTROUTER ENABLE: WAKEUP3_EN Position */
#define EVENTROUTER_ENABLE_WAKEUP3_EN_Msk                     (0x01UL << EVENTROUTER_ENABLE_WAKEUP3_EN_Pos)             /*!< EVENTROUTER ENABLE: WAKEUP3_EN Mask */
#define EVENTROUTER_ENABLE_ATIMER_EN_Pos                      4                                                         /*!< EVENTROUTER ENABLE: ATIMER_EN Position */
#define EVENTROUTER_ENABLE_ATIMER_EN_Msk                      (0x01UL << EVENTROUTER_ENABLE_ATIMER_EN_Pos)              /*!< EVENTROUTER ENABLE: ATIMER_EN Mask  */
#define EVENTROUTER_ENABLE_RTC_EN_Pos                         5                                                         /*!< EVENTROUTER ENABLE: RTC_EN Position */
#define EVENTROUTER_ENABLE_RTC_EN_Msk                         (0x01UL << EVENTROUTER_ENABLE_RTC_EN_Pos)                 /*!< EVENTROUTER ENABLE: RTC_EN Mask     */
#define EVENTROUTER_ENABLE_BOD_EN_Pos                         6                                                         /*!< EVENTROUTER ENABLE: BOD_EN Position */
#define EVENTROUTER_ENABLE_BOD_EN_Msk                         (0x01UL << EVENTROUTER_ENABLE_BOD_EN_Pos)                 /*!< EVENTROUTER ENABLE: BOD_EN Mask     */
#define EVENTROUTER_ENABLE_WWDT_EN_Pos                        7                                                         /*!< EVENTROUTER ENABLE: WWDT_EN Position */
#define EVENTROUTER_ENABLE_WWDT_EN_Msk                        (0x01UL << EVENTROUTER_ENABLE_WWDT_EN_Pos)                /*!< EVENTROUTER ENABLE: WWDT_EN Mask    */
#define EVENTROUTER_ENABLE_ETH_EN_Pos                         8                                                         /*!< EVENTROUTER ENABLE: ETH_EN Position */
#define EVENTROUTER_ENABLE_ETH_EN_Msk                         (0x01UL << EVENTROUTER_ENABLE_ETH_EN_Pos)                 /*!< EVENTROUTER ENABLE: ETH_EN Mask     */
#define EVENTROUTER_ENABLE_USB0_EN_Pos                        9                                                         /*!< EVENTROUTER ENABLE: USB0_EN Position */
#define EVENTROUTER_ENABLE_USB0_EN_Msk                        (0x01UL << EVENTROUTER_ENABLE_USB0_EN_Pos)                /*!< EVENTROUTER ENABLE: USB0_EN Mask    */
#define EVENTROUTER_ENABLE_USB1_EN_Pos                        10                                                        /*!< EVENTROUTER ENABLE: USB1_EN Position */
#define EVENTROUTER_ENABLE_USB1_EN_Msk                        (0x01UL << EVENTROUTER_ENABLE_USB1_EN_Pos)                /*!< EVENTROUTER ENABLE: USB1_EN Mask    */
#define EVENTROUTER_ENABLE_SDMMC_EN_Pos                       11                                                        /*!< EVENTROUTER ENABLE: SDMMC_EN Position */
#define EVENTROUTER_ENABLE_SDMMC_EN_Msk                       (0x01UL << EVENTROUTER_ENABLE_SDMMC_EN_Pos)               /*!< EVENTROUTER ENABLE: SDMMC_EN Mask   */
#define EVENTROUTER_ENABLE_CAN_EN_Pos                         12                                                        /*!< EVENTROUTER ENABLE: CAN_EN Position */
#define EVENTROUTER_ENABLE_CAN_EN_Msk                         (0x01UL << EVENTROUTER_ENABLE_CAN_EN_Pos)                 /*!< EVENTROUTER ENABLE: CAN_EN Mask     */
#define EVENTROUTER_ENABLE_TIM2_EN_Pos                        13                                                        /*!< EVENTROUTER ENABLE: TIM2_EN Position */
#define EVENTROUTER_ENABLE_TIM2_EN_Msk                        (0x01UL << EVENTROUTER_ENABLE_TIM2_EN_Pos)                /*!< EVENTROUTER ENABLE: TIM2_EN Mask    */
#define EVENTROUTER_ENABLE_TIM6_EN_Pos                        14                                                        /*!< EVENTROUTER ENABLE: TIM6_EN Position */
#define EVENTROUTER_ENABLE_TIM6_EN_Msk                        (0x01UL << EVENTROUTER_ENABLE_TIM6_EN_Pos)                /*!< EVENTROUTER ENABLE: TIM6_EN Mask    */
#define EVENTROUTER_ENABLE_QEI_EN_Pos                         15                                                        /*!< EVENTROUTER ENABLE: QEI_EN Position */
#define EVENTROUTER_ENABLE_QEI_EN_Msk                         (0x01UL << EVENTROUTER_ENABLE_QEI_EN_Pos)                 /*!< EVENTROUTER ENABLE: QEI_EN Mask     */
#define EVENTROUTER_ENABLE_TIM14_EN_Pos                       16                                                        /*!< EVENTROUTER ENABLE: TIM14_EN Position */
#define EVENTROUTER_ENABLE_TIM14_EN_Msk                       (0x01UL << EVENTROUTER_ENABLE_TIM14_EN_Pos)               /*!< EVENTROUTER ENABLE: TIM14_EN Mask   */
#define EVENTROUTER_ENABLE_RESET_EN_Pos                       19                                                        /*!< EVENTROUTER ENABLE: RESET_EN Position */
#define EVENTROUTER_ENABLE_RESET_EN_Msk                       (0x01UL << EVENTROUTER_ENABLE_RESET_EN_Pos)               /*!< EVENTROUTER ENABLE: RESET_EN Mask   */

// ----------------------------------  EVENTROUTER_CLR_STAT  --------------------------------------
#define EVENTROUTER_CLR_STAT_WAKEUP0_CLRST_Pos                0                                                         /*!< EVENTROUTER CLR_STAT: WAKEUP0_CLRST Position */
#define EVENTROUTER_CLR_STAT_WAKEUP0_CLRST_Msk                (0x01UL << EVENTROUTER_CLR_STAT_WAKEUP0_CLRST_Pos)        /*!< EVENTROUTER CLR_STAT: WAKEUP0_CLRST Mask */
#define EVENTROUTER_CLR_STAT_WAKEUP1_CLRST_Pos                1                                                         /*!< EVENTROUTER CLR_STAT: WAKEUP1_CLRST Position */
#define EVENTROUTER_CLR_STAT_WAKEUP1_CLRST_Msk                (0x01UL << EVENTROUTER_CLR_STAT_WAKEUP1_CLRST_Pos)        /*!< EVENTROUTER CLR_STAT: WAKEUP1_CLRST Mask */
#define EVENTROUTER_CLR_STAT_WAKEUP2_CLRST_Pos                2                                                         /*!< EVENTROUTER CLR_STAT: WAKEUP2_CLRST Position */
#define EVENTROUTER_CLR_STAT_WAKEUP2_CLRST_Msk                (0x01UL << EVENTROUTER_CLR_STAT_WAKEUP2_CLRST_Pos)        /*!< EVENTROUTER CLR_STAT: WAKEUP2_CLRST Mask */
#define EVENTROUTER_CLR_STAT_WAKEUP3_CLRST_Pos                3                                                         /*!< EVENTROUTER CLR_STAT: WAKEUP3_CLRST Position */
#define EVENTROUTER_CLR_STAT_WAKEUP3_CLRST_Msk                (0x01UL << EVENTROUTER_CLR_STAT_WAKEUP3_CLRST_Pos)        /*!< EVENTROUTER CLR_STAT: WAKEUP3_CLRST Mask */
#define EVENTROUTER_CLR_STAT_ATIMER_CLRST_Pos                 4                                                         /*!< EVENTROUTER CLR_STAT: ATIMER_CLRST Position */
#define EVENTROUTER_CLR_STAT_ATIMER_CLRST_Msk                 (0x01UL << EVENTROUTER_CLR_STAT_ATIMER_CLRST_Pos)         /*!< EVENTROUTER CLR_STAT: ATIMER_CLRST Mask */
#define EVENTROUTER_CLR_STAT_RTC_CLRST_Pos                    5                                                         /*!< EVENTROUTER CLR_STAT: RTC_CLRST Position */
#define EVENTROUTER_CLR_STAT_RTC_CLRST_Msk                    (0x01UL << EVENTROUTER_CLR_STAT_RTC_CLRST_Pos)            /*!< EVENTROUTER CLR_STAT: RTC_CLRST Mask */
#define EVENTROUTER_CLR_STAT_BOD_CLRST_Pos                    6                                                         /*!< EVENTROUTER CLR_STAT: BOD_CLRST Position */
#define EVENTROUTER_CLR_STAT_BOD_CLRST_Msk                    (0x01UL << EVENTROUTER_CLR_STAT_BOD_CLRST_Pos)            /*!< EVENTROUTER CLR_STAT: BOD_CLRST Mask */
#define EVENTROUTER_CLR_STAT_WWDT_CLRST_Pos                   7                                                         /*!< EVENTROUTER CLR_STAT: WWDT_CLRST Position */
#define EVENTROUTER_CLR_STAT_WWDT_CLRST_Msk                   (0x01UL << EVENTROUTER_CLR_STAT_WWDT_CLRST_Pos)           /*!< EVENTROUTER CLR_STAT: WWDT_CLRST Mask */
#define EVENTROUTER_CLR_STAT_ETH_CLRST_Pos                    8                                                         /*!< EVENTROUTER CLR_STAT: ETH_CLRST Position */
#define EVENTROUTER_CLR_STAT_ETH_CLRST_Msk                    (0x01UL << EVENTROUTER_CLR_STAT_ETH_CLRST_Pos)            /*!< EVENTROUTER CLR_STAT: ETH_CLRST Mask */
#define EVENTROUTER_CLR_STAT_USB0_CLRST_Pos                   9                                                         /*!< EVENTROUTER CLR_STAT: USB0_CLRST Position */
#define EVENTROUTER_CLR_STAT_USB0_CLRST_Msk                   (0x01UL << EVENTROUTER_CLR_STAT_USB0_CLRST_Pos)           /*!< EVENTROUTER CLR_STAT: USB0_CLRST Mask */
#define EVENTROUTER_CLR_STAT_USB1_CLRST_Pos                   10                                                        /*!< EVENTROUTER CLR_STAT: USB1_CLRST Position */
#define EVENTROUTER_CLR_STAT_USB1_CLRST_Msk                   (0x01UL << EVENTROUTER_CLR_STAT_USB1_CLRST_Pos)           /*!< EVENTROUTER CLR_STAT: USB1_CLRST Mask */
#define EVENTROUTER_CLR_STAT_SDMMC_CLRST_Pos                  11                                                        /*!< EVENTROUTER CLR_STAT: SDMMC_CLRST Position */
#define EVENTROUTER_CLR_STAT_SDMMC_CLRST_Msk                  (0x01UL << EVENTROUTER_CLR_STAT_SDMMC_CLRST_Pos)          /*!< EVENTROUTER CLR_STAT: SDMMC_CLRST Mask */
#define EVENTROUTER_CLR_STAT_CAN_CLRST_Pos                    12                                                        /*!< EVENTROUTER CLR_STAT: CAN_CLRST Position */
#define EVENTROUTER_CLR_STAT_CAN_CLRST_Msk                    (0x01UL << EVENTROUTER_CLR_STAT_CAN_CLRST_Pos)            /*!< EVENTROUTER CLR_STAT: CAN_CLRST Mask */
#define EVENTROUTER_CLR_STAT_TIM2_CLRST_Pos                   13                                                        /*!< EVENTROUTER CLR_STAT: TIM2_CLRST Position */
#define EVENTROUTER_CLR_STAT_TIM2_CLRST_Msk                   (0x01UL << EVENTROUTER_CLR_STAT_TIM2_CLRST_Pos)           /*!< EVENTROUTER CLR_STAT: TIM2_CLRST Mask */
#define EVENTROUTER_CLR_STAT_TIM6_CLRST_Pos                   14                                                        /*!< EVENTROUTER CLR_STAT: TIM6_CLRST Position */
#define EVENTROUTER_CLR_STAT_TIM6_CLRST_Msk                   (0x01UL << EVENTROUTER_CLR_STAT_TIM6_CLRST_Pos)           /*!< EVENTROUTER CLR_STAT: TIM6_CLRST Mask */
#define EVENTROUTER_CLR_STAT_QEI_CLRST_Pos                    15                                                        /*!< EVENTROUTER CLR_STAT: QEI_CLRST Position */
#define EVENTROUTER_CLR_STAT_QEI_CLRST_Msk                    (0x01UL << EVENTROUTER_CLR_STAT_QEI_CLRST_Pos)            /*!< EVENTROUTER CLR_STAT: QEI_CLRST Mask */
#define EVENTROUTER_CLR_STAT_TIM14_CLRST_Pos                  16                                                        /*!< EVENTROUTER CLR_STAT: TIM14_CLRST Position */
#define EVENTROUTER_CLR_STAT_TIM14_CLRST_Msk                  (0x01UL << EVENTROUTER_CLR_STAT_TIM14_CLRST_Pos)          /*!< EVENTROUTER CLR_STAT: TIM14_CLRST Mask */
#define EVENTROUTER_CLR_STAT_RESET_CLRST_Pos                  19                                                        /*!< EVENTROUTER CLR_STAT: RESET_CLRST Position */
#define EVENTROUTER_CLR_STAT_RESET_CLRST_Msk                  (0x01UL << EVENTROUTER_CLR_STAT_RESET_CLRST_Pos)          /*!< EVENTROUTER CLR_STAT: RESET_CLRST Mask */

// ----------------------------------  EVENTROUTER_SET_STAT  --------------------------------------
#define EVENTROUTER_SET_STAT_WAKEUP0_SETST_Pos                0                                                         /*!< EVENTROUTER SET_STAT: WAKEUP0_SETST Position */
#define EVENTROUTER_SET_STAT_WAKEUP0_SETST_Msk                (0x01UL << EVENTROUTER_SET_STAT_WAKEUP0_SETST_Pos)        /*!< EVENTROUTER SET_STAT: WAKEUP0_SETST Mask */
#define EVENTROUTER_SET_STAT_WAKEUP1_SETST_Pos                1                                                         /*!< EVENTROUTER SET_STAT: WAKEUP1_SETST Position */
#define EVENTROUTER_SET_STAT_WAKEUP1_SETST_Msk                (0x01UL << EVENTROUTER_SET_STAT_WAKEUP1_SETST_Pos)        /*!< EVENTROUTER SET_STAT: WAKEUP1_SETST Mask */
#define EVENTROUTER_SET_STAT_WAKEUP2_SETST_Pos                2                                                         /*!< EVENTROUTER SET_STAT: WAKEUP2_SETST Position */
#define EVENTROUTER_SET_STAT_WAKEUP2_SETST_Msk                (0x01UL << EVENTROUTER_SET_STAT_WAKEUP2_SETST_Pos)        /*!< EVENTROUTER SET_STAT: WAKEUP2_SETST Mask */
#define EVENTROUTER_SET_STAT_WAKEUP3_SETST_Pos                3                                                         /*!< EVENTROUTER SET_STAT: WAKEUP3_SETST Position */
#define EVENTROUTER_SET_STAT_WAKEUP3_SETST_Msk                (0x01UL << EVENTROUTER_SET_STAT_WAKEUP3_SETST_Pos)        /*!< EVENTROUTER SET_STAT: WAKEUP3_SETST Mask */
#define EVENTROUTER_SET_STAT_ATIMER_SETST_Pos                 4                                                         /*!< EVENTROUTER SET_STAT: ATIMER_SETST Position */
#define EVENTROUTER_SET_STAT_ATIMER_SETST_Msk                 (0x01UL << EVENTROUTER_SET_STAT_ATIMER_SETST_Pos)         /*!< EVENTROUTER SET_STAT: ATIMER_SETST Mask */
#define EVENTROUTER_SET_STAT_RTC_SETST_Pos                    5                                                         /*!< EVENTROUTER SET_STAT: RTC_SETST Position */
#define EVENTROUTER_SET_STAT_RTC_SETST_Msk                    (0x01UL << EVENTROUTER_SET_STAT_RTC_SETST_Pos)            /*!< EVENTROUTER SET_STAT: RTC_SETST Mask */
#define EVENTROUTER_SET_STAT_BOD_SETST_Pos                    6                                                         /*!< EVENTROUTER SET_STAT: BOD_SETST Position */
#define EVENTROUTER_SET_STAT_BOD_SETST_Msk                    (0x01UL << EVENTROUTER_SET_STAT_BOD_SETST_Pos)            /*!< EVENTROUTER SET_STAT: BOD_SETST Mask */
#define EVENTROUTER_SET_STAT_WWDT_SETST_Pos                   7                                                         /*!< EVENTROUTER SET_STAT: WWDT_SETST Position */
#define EVENTROUTER_SET_STAT_WWDT_SETST_Msk                   (0x01UL << EVENTROUTER_SET_STAT_WWDT_SETST_Pos)           /*!< EVENTROUTER SET_STAT: WWDT_SETST Mask */
#define EVENTROUTER_SET_STAT_ETH_SETST_Pos                    8                                                         /*!< EVENTROUTER SET_STAT: ETH_SETST Position */
#define EVENTROUTER_SET_STAT_ETH_SETST_Msk                    (0x01UL << EVENTROUTER_SET_STAT_ETH_SETST_Pos)            /*!< EVENTROUTER SET_STAT: ETH_SETST Mask */
#define EVENTROUTER_SET_STAT_USB0_SETST_Pos                   9                                                         /*!< EVENTROUTER SET_STAT: USB0_SETST Position */
#define EVENTROUTER_SET_STAT_USB0_SETST_Msk                   (0x01UL << EVENTROUTER_SET_STAT_USB0_SETST_Pos)           /*!< EVENTROUTER SET_STAT: USB0_SETST Mask */
#define EVENTROUTER_SET_STAT_USB1_SETST_Pos                   10                                                        /*!< EVENTROUTER SET_STAT: USB1_SETST Position */
#define EVENTROUTER_SET_STAT_USB1_SETST_Msk                   (0x01UL << EVENTROUTER_SET_STAT_USB1_SETST_Pos)           /*!< EVENTROUTER SET_STAT: USB1_SETST Mask */
#define EVENTROUTER_SET_STAT_SDMMC_SETST_Pos                  11                                                        /*!< EVENTROUTER SET_STAT: SDMMC_SETST Position */
#define EVENTROUTER_SET_STAT_SDMMC_SETST_Msk                  (0x01UL << EVENTROUTER_SET_STAT_SDMMC_SETST_Pos)          /*!< EVENTROUTER SET_STAT: SDMMC_SETST Mask */
#define EVENTROUTER_SET_STAT_CAN_SETST_Pos                    12                                                        /*!< EVENTROUTER SET_STAT: CAN_SETST Position */
#define EVENTROUTER_SET_STAT_CAN_SETST_Msk                    (0x01UL << EVENTROUTER_SET_STAT_CAN_SETST_Pos)            /*!< EVENTROUTER SET_STAT: CAN_SETST Mask */
#define EVENTROUTER_SET_STAT_TIM2_SETST_Pos                   13                                                        /*!< EVENTROUTER SET_STAT: TIM2_SETST Position */
#define EVENTROUTER_SET_STAT_TIM2_SETST_Msk                   (0x01UL << EVENTROUTER_SET_STAT_TIM2_SETST_Pos)           /*!< EVENTROUTER SET_STAT: TIM2_SETST Mask */
#define EVENTROUTER_SET_STAT_TIM6_SETST_Pos                   14                                                        /*!< EVENTROUTER SET_STAT: TIM6_SETST Position */
#define EVENTROUTER_SET_STAT_TIM6_SETST_Msk                   (0x01UL << EVENTROUTER_SET_STAT_TIM6_SETST_Pos)           /*!< EVENTROUTER SET_STAT: TIM6_SETST Mask */
#define EVENTROUTER_SET_STAT_QEI_SETST_Pos                    15                                                        /*!< EVENTROUTER SET_STAT: QEI_SETST Position */
#define EVENTROUTER_SET_STAT_QEI_SETST_Msk                    (0x01UL << EVENTROUTER_SET_STAT_QEI_SETST_Pos)            /*!< EVENTROUTER SET_STAT: QEI_SETST Mask */
#define EVENTROUTER_SET_STAT_TIM14_SETST_Pos                  16                                                        /*!< EVENTROUTER SET_STAT: TIM14_SETST Position */
#define EVENTROUTER_SET_STAT_TIM14_SETST_Msk                  (0x01UL << EVENTROUTER_SET_STAT_TIM14_SETST_Pos)          /*!< EVENTROUTER SET_STAT: TIM14_SETST Mask */
#define EVENTROUTER_SET_STAT_RESET_SETST_Pos                  19                                                        /*!< EVENTROUTER SET_STAT: RESET_SETST Position */
#define EVENTROUTER_SET_STAT_RESET_SETST_Msk                  (0x01UL << EVENTROUTER_SET_STAT_RESET_SETST_Pos)          /*!< EVENTROUTER SET_STAT: RESET_SETST Mask */


// ------------------------------------------------------------------------------------------------
// -----                                  RTC Position & Mask                                 -----
// ------------------------------------------------------------------------------------------------


// -----------------------------------------  RTC_ILR  --------------------------------------------
#define RTC_ILR_RTCCIF_Pos                                    0                                                         /*!< RTC ILR: RTCCIF Position            */
#define RTC_ILR_RTCCIF_Msk                                    (0x01UL << RTC_ILR_RTCCIF_Pos)                            /*!< RTC ILR: RTCCIF Mask                */
#define RTC_ILR_RTCALF_Pos                                    1                                                         /*!< RTC ILR: RTCALF Position            */
#define RTC_ILR_RTCALF_Msk                                    (0x01UL << RTC_ILR_RTCALF_Pos)                            /*!< RTC ILR: RTCALF Mask                */

// -----------------------------------------  RTC_CCR  --------------------------------------------
#define RTC_CCR_CLKEN_Pos                                     0                                                         /*!< RTC CCR: CLKEN Position             */
#define RTC_CCR_CLKEN_Msk                                     (0x01UL << RTC_CCR_CLKEN_Pos)                             /*!< RTC CCR: CLKEN Mask                 */
#define RTC_CCR_CTCRST_Pos                                    1                                                         /*!< RTC CCR: CTCRST Position            */
#define RTC_CCR_CTCRST_Msk                                    (0x01UL << RTC_CCR_CTCRST_Pos)                            /*!< RTC CCR: CTCRST Mask                */
#define RTC_CCR_CCALEN_Pos                                    4                                                         /*!< RTC CCR: CCALEN Position            */
#define RTC_CCR_CCALEN_Msk                                    (0x01UL << RTC_CCR_CCALEN_Pos)                            /*!< RTC CCR: CCALEN Mask                */

// ----------------------------------------  RTC_CIIR  --------------------------------------------
#define RTC_CIIR_IMSEC_Pos                                    0                                                         /*!< RTC CIIR: IMSEC Position            */
#define RTC_CIIR_IMSEC_Msk                                    (0x01UL << RTC_CIIR_IMSEC_Pos)                            /*!< RTC CIIR: IMSEC Mask                */
#define RTC_CIIR_IMMIN_Pos                                    1                                                         /*!< RTC CIIR: IMMIN Position            */
#define RTC_CIIR_IMMIN_Msk                                    (0x01UL << RTC_CIIR_IMMIN_Pos)                            /*!< RTC CIIR: IMMIN Mask                */
#define RTC_CIIR_IMHOUR_Pos                                   2                                                         /*!< RTC CIIR: IMHOUR Position           */
#define RTC_CIIR_IMHOUR_Msk                                   (0x01UL << RTC_CIIR_IMHOUR_Pos)                           /*!< RTC CIIR: IMHOUR Mask               */
#define RTC_CIIR_IMDOM_Pos                                    3                                                         /*!< RTC CIIR: IMDOM Position            */
#define RTC_CIIR_IMDOM_Msk                                    (0x01UL << RTC_CIIR_IMDOM_Pos)                            /*!< RTC CIIR: IMDOM Mask                */
#define RTC_CIIR_IMDOW_Pos                                    4                                                         /*!< RTC CIIR: IMDOW Position            */
#define RTC_CIIR_IMDOW_Msk                                    (0x01UL << RTC_CIIR_IMDOW_Pos)                            /*!< RTC CIIR: IMDOW Mask                */
#define RTC_CIIR_IMDOY_Pos                                    5                                                         /*!< RTC CIIR: IMDOY Position            */
#define RTC_CIIR_IMDOY_Msk                                    (0x01UL << RTC_CIIR_IMDOY_Pos)                            /*!< RTC CIIR: IMDOY Mask                */
#define RTC_CIIR_IMMON_Pos                                    6                                                         /*!< RTC CIIR: IMMON Position            */
#define RTC_CIIR_IMMON_Msk                                    (0x01UL << RTC_CIIR_IMMON_Pos)                            /*!< RTC CIIR: IMMON Mask                */
#define RTC_CIIR_IMYEAR_Pos                                   7                                                         /*!< RTC CIIR: IMYEAR Position           */
#define RTC_CIIR_IMYEAR_Msk                                   (0x01UL << RTC_CIIR_IMYEAR_Pos)                           /*!< RTC CIIR: IMYEAR Mask               */

// -----------------------------------------  RTC_AMR  --------------------------------------------
#define RTC_AMR_AMRSEC_Pos                                    0                                                         /*!< RTC AMR: AMRSEC Position            */
#define RTC_AMR_AMRSEC_Msk                                    (0x01UL << RTC_AMR_AMRSEC_Pos)                            /*!< RTC AMR: AMRSEC Mask                */
#define RTC_AMR_AMRMIN_Pos                                    1                                                         /*!< RTC AMR: AMRMIN Position            */
#define RTC_AMR_AMRMIN_Msk                                    (0x01UL << RTC_AMR_AMRMIN_Pos)                            /*!< RTC AMR: AMRMIN Mask                */
#define RTC_AMR_AMRHOUR_Pos                                   2                                                         /*!< RTC AMR: AMRHOUR Position           */
#define RTC_AMR_AMRHOUR_Msk                                   (0x01UL << RTC_AMR_AMRHOUR_Pos)                           /*!< RTC AMR: AMRHOUR Mask               */
#define RTC_AMR_AMRDOM_Pos                                    3                                                         /*!< RTC AMR: AMRDOM Position            */
#define RTC_AMR_AMRDOM_Msk                                    (0x01UL << RTC_AMR_AMRDOM_Pos)                            /*!< RTC AMR: AMRDOM Mask                */
#define RTC_AMR_AMRDOW_Pos                                    4                                                         /*!< RTC AMR: AMRDOW Position            */
#define RTC_AMR_AMRDOW_Msk                                    (0x01UL << RTC_AMR_AMRDOW_Pos)                            /*!< RTC AMR: AMRDOW Mask                */
#define RTC_AMR_AMRDOY_Pos                                    5                                                         /*!< RTC AMR: AMRDOY Position            */
#define RTC_AMR_AMRDOY_Msk                                    (0x01UL << RTC_AMR_AMRDOY_Pos)                            /*!< RTC AMR: AMRDOY Mask                */
#define RTC_AMR_AMRMON_Pos                                    6                                                         /*!< RTC AMR: AMRMON Position            */
#define RTC_AMR_AMRMON_Msk                                    (0x01UL << RTC_AMR_AMRMON_Pos)                            /*!< RTC AMR: AMRMON Mask                */
#define RTC_AMR_AMRYEAR_Pos                                   7                                                         /*!< RTC AMR: AMRYEAR Position           */
#define RTC_AMR_AMRYEAR_Msk                                   (0x01UL << RTC_AMR_AMRYEAR_Pos)                           /*!< RTC AMR: AMRYEAR Mask               */

// ---------------------------------------  RTC_CTIME0  -------------------------------------------
#define RTC_CTIME0_SECONDS_Pos                                0                                                         /*!< RTC CTIME0: SECONDS Position        */
#define RTC_CTIME0_SECONDS_Msk                                (0x3fUL << RTC_CTIME0_SECONDS_Pos)                        /*!< RTC CTIME0: SECONDS Mask            */
#define RTC_CTIME0_MINUTES_Pos                                8                                                         /*!< RTC CTIME0: MINUTES Position        */
#define RTC_CTIME0_MINUTES_Msk                                (0x3fUL << RTC_CTIME0_MINUTES_Pos)                        /*!< RTC CTIME0: MINUTES Mask            */
#define RTC_CTIME0_HOURS_Pos                                  16                                                        /*!< RTC CTIME0: HOURS Position          */
#define RTC_CTIME0_HOURS_Msk                                  (0x1fUL << RTC_CTIME0_HOURS_Pos)                          /*!< RTC CTIME0: HOURS Mask              */
#define RTC_CTIME0_DOW_Pos                                    24                                                        /*!< RTC CTIME0: DOW Position            */
#define RTC_CTIME0_DOW_Msk                                    (0x07UL << RTC_CTIME0_DOW_Pos)                            /*!< RTC CTIME0: DOW Mask                */

// ---------------------------------------  RTC_CTIME1  -------------------------------------------
#define RTC_CTIME1_DOM_Pos                                    0                                                         /*!< RTC CTIME1: DOM Position            */
#define RTC_CTIME1_DOM_Msk                                    (0x1fUL << RTC_CTIME1_DOM_Pos)                            /*!< RTC CTIME1: DOM Mask                */
#define RTC_CTIME1_MONTH_Pos                                  8                                                         /*!< RTC CTIME1: MONTH Position          */
#define RTC_CTIME1_MONTH_Msk                                  (0x0fUL << RTC_CTIME1_MONTH_Pos)                          /*!< RTC CTIME1: MONTH Mask              */
#define RTC_CTIME1_YEAR_Pos                                   16                                                        /*!< RTC CTIME1: YEAR Position           */
#define RTC_CTIME1_YEAR_Msk                                   (0x00000fffUL << RTC_CTIME1_YEAR_Pos)                     /*!< RTC CTIME1: YEAR Mask               */

// ---------------------------------------  RTC_CTIME2  -------------------------------------------
#define RTC_CTIME2_DOY_Pos                                    0                                                         /*!< RTC CTIME2: DOY Position            */
#define RTC_CTIME2_DOY_Msk                                    (0x00000fffUL << RTC_CTIME2_DOY_Pos)                      /*!< RTC CTIME2: DOY Mask                */

// -----------------------------------------  RTC_SEC  --------------------------------------------
#define RTC_SEC_SECONDS_Pos                                   0                                                         /*!< RTC SEC: SECONDS Position           */
#define RTC_SEC_SECONDS_Msk                                   (0x3fUL << RTC_SEC_SECONDS_Pos)                           /*!< RTC SEC: SECONDS Mask               */

// -----------------------------------------  RTC_MIN  --------------------------------------------
#define RTC_MIN_MINUTES_Pos                                   0                                                         /*!< RTC MIN: MINUTES Position           */
#define RTC_MIN_MINUTES_Msk                                   (0x3fUL << RTC_MIN_MINUTES_Pos)                           /*!< RTC MIN: MINUTES Mask               */

// -----------------------------------------  RTC_HRS  --------------------------------------------
#define RTC_HRS_HOURS_Pos                                     0                                                         /*!< RTC HRS: HOURS Position             */
#define RTC_HRS_HOURS_Msk                                     (0x1fUL << RTC_HRS_HOURS_Pos)                             /*!< RTC HRS: HOURS Mask                 */

// -----------------------------------------  RTC_DOM  --------------------------------------------
#define RTC_DOM_DOM_Pos                                       0                                                         /*!< RTC DOM: DOM Position               */
#define RTC_DOM_DOM_Msk                                       (0x1fUL << RTC_DOM_DOM_Pos)                               /*!< RTC DOM: DOM Mask                   */

// -----------------------------------------  RTC_DOW  --------------------------------------------
#define RTC_DOW_DOW_Pos                                       0                                                         /*!< RTC DOW: DOW Position               */
#define RTC_DOW_DOW_Msk                                       (0x07UL << RTC_DOW_DOW_Pos)                               /*!< RTC DOW: DOW Mask                   */

// -----------------------------------------  RTC_DOY  --------------------------------------------
#define RTC_DOY_DOY_Pos                                       0                                                         /*!< RTC DOY: DOY Position               */
#define RTC_DOY_DOY_Msk                                       (0x000001ffUL << RTC_DOY_DOY_Pos)                         /*!< RTC DOY: DOY Mask                   */

// ----------------------------------------  RTC_MONTH  -------------------------------------------
#define RTC_MONTH_MONTH_Pos                                   0                                                         /*!< RTC MONTH: MONTH Position           */
#define RTC_MONTH_MONTH_Msk                                   (0x0fUL << RTC_MONTH_MONTH_Pos)                           /*!< RTC MONTH: MONTH Mask               */

// ----------------------------------------  RTC_YEAR  --------------------------------------------
#define RTC_YEAR_YEAR_Pos                                     0                                                         /*!< RTC YEAR: YEAR Position             */
#define RTC_YEAR_YEAR_Msk                                     (0x00000fffUL << RTC_YEAR_YEAR_Pos)                       /*!< RTC YEAR: YEAR Mask                 */

// -------------------------------------  RTC_CALIBRATION  ----------------------------------------
#define RTC_CALIBRATION_CALVAL_Pos                            0                                                         /*!< RTC CALIBRATION: CALVAL Position    */
#define RTC_CALIBRATION_CALVAL_Msk                            (0x0001ffffUL << RTC_CALIBRATION_CALVAL_Pos)              /*!< RTC CALIBRATION: CALVAL Mask        */
#define RTC_CALIBRATION_CALDIR_Pos                            17                                                        /*!< RTC CALIBRATION: CALDIR Position    */
#define RTC_CALIBRATION_CALDIR_Msk                            (0x01UL << RTC_CALIBRATION_CALDIR_Pos)                    /*!< RTC CALIBRATION: CALDIR Mask        */

// ----------------------------------------  RTC_ASEC  --------------------------------------------
#define RTC_ASEC_SECONDS_Pos                                  0                                                         /*!< RTC ASEC: SECONDS Position          */
#define RTC_ASEC_SECONDS_Msk                                  (0x3fUL << RTC_ASEC_SECONDS_Pos)                          /*!< RTC ASEC: SECONDS Mask              */

// ----------------------------------------  RTC_AMIN  --------------------------------------------
#define RTC_AMIN_MINUTES_Pos                                  0                                                         /*!< RTC AMIN: MINUTES Position          */
#define RTC_AMIN_MINUTES_Msk                                  (0x3fUL << RTC_AMIN_MINUTES_Pos)                          /*!< RTC AMIN: MINUTES Mask              */

// ----------------------------------------  RTC_AHRS  --------------------------------------------
#define RTC_AHRS_HOURS_Pos                                    0                                                         /*!< RTC AHRS: HOURS Position            */
#define RTC_AHRS_HOURS_Msk                                    (0x1fUL << RTC_AHRS_HOURS_Pos)                            /*!< RTC AHRS: HOURS Mask                */

// ----------------------------------------  RTC_ADOM  --------------------------------------------
#define RTC_ADOM_DOM_Pos                                      0                                                         /*!< RTC ADOM: DOM Position              */
#define RTC_ADOM_DOM_Msk                                      (0x1fUL << RTC_ADOM_DOM_Pos)                              /*!< RTC ADOM: DOM Mask                  */

// ----------------------------------------  RTC_ADOW  --------------------------------------------
#define RTC_ADOW_DOW_Pos                                      0                                                         /*!< RTC ADOW: DOW Position              */
#define RTC_ADOW_DOW_Msk                                      (0x07UL << RTC_ADOW_DOW_Pos)                              /*!< RTC ADOW: DOW Mask                  */

// ----------------------------------------  RTC_ADOY  --------------------------------------------
#define RTC_ADOY_DOY_Pos                                      0                                                         /*!< RTC ADOY: DOY Position              */
#define RTC_ADOY_DOY_Msk                                      (0x000001ffUL << RTC_ADOY_DOY_Pos)                        /*!< RTC ADOY: DOY Mask                  */

// ----------------------------------------  RTC_AMON  --------------------------------------------
#define RTC_AMON_MONTH_Pos                                    0                                                         /*!< RTC AMON: MONTH Position            */
#define RTC_AMON_MONTH_Msk                                    (0x0fUL << RTC_AMON_MONTH_Pos)                            /*!< RTC AMON: MONTH Mask                */

// ----------------------------------------  RTC_AYRS  --------------------------------------------
#define RTC_AYRS_YEAR_Pos                                     0                                                         /*!< RTC AYRS: YEAR Position             */
#define RTC_AYRS_YEAR_Msk                                     (0x00000fffUL << RTC_AYRS_YEAR_Pos)                       /*!< RTC AYRS: YEAR Mask                 */


// ------------------------------------------------------------------------------------------------
// -----                                  CGU Position & Mask                                 -----
// ------------------------------------------------------------------------------------------------


// --------------------------------------  CGU_FREQ_MON  ------------------------------------------
#define CGU_FREQ_MON_RCNT_Pos                                 0                                                         /*!< CGU FREQ_MON: RCNT Position         */
#define CGU_FREQ_MON_RCNT_Msk                                 (0x000001ffUL << CGU_FREQ_MON_RCNT_Pos)                   /*!< CGU FREQ_MON: RCNT Mask             */
#define CGU_FREQ_MON_FCNT_Pos                                 9                                                         /*!< CGU FREQ_MON: FCNT Position         */
#define CGU_FREQ_MON_FCNT_Msk                                 (0x00003fffUL << CGU_FREQ_MON_FCNT_Pos)                   /*!< CGU FREQ_MON: FCNT Mask             */
#define CGU_FREQ_MON_MEAS_Pos                                 23                                                        /*!< CGU FREQ_MON: MEAS Position         */
#define CGU_FREQ_MON_MEAS_Msk                                 (0x01UL << CGU_FREQ_MON_MEAS_Pos)                         /*!< CGU FREQ_MON: MEAS Mask             */
#define CGU_FREQ_MON_CLK_SEL_Pos                              24                                                        /*!< CGU FREQ_MON: CLK_SEL Position      */
#define CGU_FREQ_MON_CLK_SEL_Msk                              (0x1fUL << CGU_FREQ_MON_CLK_SEL_Pos)                      /*!< CGU FREQ_MON: CLK_SEL Mask          */

// ------------------------------------  CGU_XTAL_OSC_CTRL  ---------------------------------------
#define CGU_XTAL_OSC_CTRL_ENABLE_Pos                          0                                                         /*!< CGU XTAL_OSC_CTRL: ENABLE Position  */
#define CGU_XTAL_OSC_CTRL_ENABLE_Msk                          (0x01UL << CGU_XTAL_OSC_CTRL_ENABLE_Pos)                  /*!< CGU XTAL_OSC_CTRL: ENABLE Mask      */
#define CGU_XTAL_OSC_CTRL_BYPASS_Pos                          1                                                         /*!< CGU XTAL_OSC_CTRL: BYPASS Position  */
#define CGU_XTAL_OSC_CTRL_BYPASS_Msk                          (0x01UL << CGU_XTAL_OSC_CTRL_BYPASS_Pos)                  /*!< CGU XTAL_OSC_CTRL: BYPASS Mask      */
#define CGU_XTAL_OSC_CTRL_HF_Pos                              2                                                         /*!< CGU XTAL_OSC_CTRL: HF Position      */
#define CGU_XTAL_OSC_CTRL_HF_Msk                              (0x01UL << CGU_XTAL_OSC_CTRL_HF_Pos)                      /*!< CGU XTAL_OSC_CTRL: HF Mask          */

// ------------------------------------  CGU_PLL0USB_STAT  ----------------------------------------
#define CGU_PLL0USB_STAT_LOCK_Pos                             0                                                         /*!< CGU PLL0USB_STAT: LOCK Position     */
#define CGU_PLL0USB_STAT_LOCK_Msk                             (0x01UL << CGU_PLL0USB_STAT_LOCK_Pos)                     /*!< CGU PLL0USB_STAT: LOCK Mask         */
#define CGU_PLL0USB_STAT_FR_Pos                               1                                                         /*!< CGU PLL0USB_STAT: FR Position       */
#define CGU_PLL0USB_STAT_FR_Msk                               (0x01UL << CGU_PLL0USB_STAT_FR_Pos)                       /*!< CGU PLL0USB_STAT: FR Mask           */

// ------------------------------------  CGU_PLL0USB_CTRL  ----------------------------------------
#define CGU_PLL0USB_CTRL_PD_Pos                               0                                                         /*!< CGU PLL0USB_CTRL: PD Position       */
#define CGU_PLL0USB_CTRL_PD_Msk                               (0x01UL << CGU_PLL0USB_CTRL_PD_Pos)                       /*!< CGU PLL0USB_CTRL: PD Mask           */
#define CGU_PLL0USB_CTRL_BYPASS_Pos                           1                                                         /*!< CGU PLL0USB_CTRL: BYPASS Position   */
#define CGU_PLL0USB_CTRL_BYPASS_Msk                           (0x01UL << CGU_PLL0USB_CTRL_BYPASS_Pos)                   /*!< CGU PLL0USB_CTRL: BYPASS Mask       */
#define CGU_PLL0USB_CTRL_DIRECTI_Pos                          2                                                         /*!< CGU PLL0USB_CTRL: DIRECTI Position  */
#define CGU_PLL0USB_CTRL_DIRECTI_Msk                          (0x01UL << CGU_PLL0USB_CTRL_DIRECTI_Pos)                  /*!< CGU PLL0USB_CTRL: DIRECTI Mask      */
#define CGU_PLL0USB_CTRL_DIRECTO_Pos                          3                                                         /*!< CGU PLL0USB_CTRL: DIRECTO Position  */
#define CGU_PLL0USB_CTRL_DIRECTO_Msk                          (0x01UL << CGU_PLL0USB_CTRL_DIRECTO_Pos)                  /*!< CGU PLL0USB_CTRL: DIRECTO Mask      */
#define CGU_PLL0USB_CTRL_CLKEN_Pos                            4                                                         /*!< CGU PLL0USB_CTRL: CLKEN Position    */
#define CGU_PLL0USB_CTRL_CLKEN_Msk                            (0x01UL << CGU_PLL0USB_CTRL_CLKEN_Pos)                    /*!< CGU PLL0USB_CTRL: CLKEN Mask        */
#define CGU_PLL0USB_CTRL_FRM_Pos                              6                                                         /*!< CGU PLL0USB_CTRL: FRM Position      */
#define CGU_PLL0USB_CTRL_FRM_Msk                              (0x01UL << CGU_PLL0USB_CTRL_FRM_Pos)                      /*!< CGU PLL0USB_CTRL: FRM Mask          */
#define CGU_PLL0USB_CTRL_AUTOBLOCK_Pos                        11                                                        /*!< CGU PLL0USB_CTRL: AUTOBLOCK Position */
#define CGU_PLL0USB_CTRL_AUTOBLOCK_Msk                        (0x01UL << CGU_PLL0USB_CTRL_AUTOBLOCK_Pos)                /*!< CGU PLL0USB_CTRL: AUTOBLOCK Mask    */
#define CGU_PLL0USB_CTRL_CLK_SEL_Pos                          24                                                        /*!< CGU PLL0USB_CTRL: CLK_SEL Position  */
#define CGU_PLL0USB_CTRL_CLK_SEL_Msk                          (0x1fUL << CGU_PLL0USB_CTRL_CLK_SEL_Pos)                  /*!< CGU PLL0USB_CTRL: CLK_SEL Mask      */

// ------------------------------------  CGU_PLL0USB_MDIV  ----------------------------------------
#define CGU_PLL0USB_MDIV_MDEC_Pos                             0                                                         /*!< CGU PLL0USB_MDIV: MDEC Position     */
#define CGU_PLL0USB_MDIV_MDEC_Msk                             (0x0001ffffUL << CGU_PLL0USB_MDIV_MDEC_Pos)               /*!< CGU PLL0USB_MDIV: MDEC Mask         */
#define CGU_PLL0USB_MDIV_SELP_Pos                             17                                                        /*!< CGU PLL0USB_MDIV: SELP Position     */
#define CGU_PLL0USB_MDIV_SELP_Msk                             (0x1fUL << CGU_PLL0USB_MDIV_SELP_Pos)                     /*!< CGU PLL0USB_MDIV: SELP Mask         */
#define CGU_PLL0USB_MDIV_SELI_Pos                             22                                                        /*!< CGU PLL0USB_MDIV: SELI Position     */
#define CGU_PLL0USB_MDIV_SELI_Msk                             (0x3fUL << CGU_PLL0USB_MDIV_SELI_Pos)                     /*!< CGU PLL0USB_MDIV: SELI Mask         */
#define CGU_PLL0USB_MDIV_SELR_Pos                             28                                                        /*!< CGU PLL0USB_MDIV: SELR Position     */
#define CGU_PLL0USB_MDIV_SELR_Msk                             (0x0fUL << CGU_PLL0USB_MDIV_SELR_Pos)                     /*!< CGU PLL0USB_MDIV: SELR Mask         */

// -----------------------------------  CGU_PLL0USB_NP_DIV  ---------------------------------------
#define CGU_PLL0USB_NP_DIV_PDEC_Pos                           0                                                         /*!< CGU PLL0USB_NP_DIV: PDEC Position   */
#define CGU_PLL0USB_NP_DIV_PDEC_Msk                           (0x7fUL << CGU_PLL0USB_NP_DIV_PDEC_Pos)                   /*!< CGU PLL0USB_NP_DIV: PDEC Mask       */
#define CGU_PLL0USB_NP_DIV_NDEC_Pos                           12                                                        /*!< CGU PLL0USB_NP_DIV: NDEC Position   */
#define CGU_PLL0USB_NP_DIV_NDEC_Msk                           (0x000003ffUL << CGU_PLL0USB_NP_DIV_NDEC_Pos)             /*!< CGU PLL0USB_NP_DIV: NDEC Mask       */

// -----------------------------------  CGU_PLL0AUDIO_STAT  ---------------------------------------
#define CGU_PLL0AUDIO_STAT_LOCK_Pos                           0                                                         /*!< CGU PLL0AUDIO_STAT: LOCK Position   */
#define CGU_PLL0AUDIO_STAT_LOCK_Msk                           (0x01UL << CGU_PLL0AUDIO_STAT_LOCK_Pos)                   /*!< CGU PLL0AUDIO_STAT: LOCK Mask       */
#define CGU_PLL0AUDIO_STAT_FR_Pos                             1                                                         /*!< CGU PLL0AUDIO_STAT: FR Position     */
#define CGU_PLL0AUDIO_STAT_FR_Msk                             (0x01UL << CGU_PLL0AUDIO_STAT_FR_Pos)                     /*!< CGU PLL0AUDIO_STAT: FR Mask         */

// -----------------------------------  CGU_PLL0AUDIO_CTRL  ---------------------------------------
#define CGU_PLL0AUDIO_CTRL_PD_Pos                             0                                                         /*!< CGU PLL0AUDIO_CTRL: PD Position     */
#define CGU_PLL0AUDIO_CTRL_PD_Msk                             (0x01UL << CGU_PLL0AUDIO_CTRL_PD_Pos)                     /*!< CGU PLL0AUDIO_CTRL: PD Mask         */
#define CGU_PLL0AUDIO_CTRL_BYPASS_Pos                         1                                                         /*!< CGU PLL0AUDIO_CTRL: BYPASS Position */
#define CGU_PLL0AUDIO_CTRL_BYPASS_Msk                         (0x01UL << CGU_PLL0AUDIO_CTRL_BYPASS_Pos)                 /*!< CGU PLL0AUDIO_CTRL: BYPASS Mask     */
#define CGU_PLL0AUDIO_CTRL_DIRECTI_Pos                        2                                                         /*!< CGU PLL0AUDIO_CTRL: DIRECTI Position */
#define CGU_PLL0AUDIO_CTRL_DIRECTI_Msk                        (0x01UL << CGU_PLL0AUDIO_CTRL_DIRECTI_Pos)                /*!< CGU PLL0AUDIO_CTRL: DIRECTI Mask    */
#define CGU_PLL0AUDIO_CTRL_DIRECTO_Pos                        3                                                         /*!< CGU PLL0AUDIO_CTRL: DIRECTO Position */
#define CGU_PLL0AUDIO_CTRL_DIRECTO_Msk                        (0x01UL << CGU_PLL0AUDIO_CTRL_DIRECTO_Pos)                /*!< CGU PLL0AUDIO_CTRL: DIRECTO Mask    */
#define CGU_PLL0AUDIO_CTRL_CLKEN_Pos                          4                                                         /*!< CGU PLL0AUDIO_CTRL: CLKEN Position  */
#define CGU_PLL0AUDIO_CTRL_CLKEN_Msk                          (0x01UL << CGU_PLL0AUDIO_CTRL_CLKEN_Pos)                  /*!< CGU PLL0AUDIO_CTRL: CLKEN Mask      */
#define CGU_PLL0AUDIO_CTRL_FRM_Pos                            6                                                         /*!< CGU PLL0AUDIO_CTRL: FRM Position    */
#define CGU_PLL0AUDIO_CTRL_FRM_Msk                            (0x01UL << CGU_PLL0AUDIO_CTRL_FRM_Pos)                    /*!< CGU PLL0AUDIO_CTRL: FRM Mask        */
#define CGU_PLL0AUDIO_CTRL_AUTOBLOCK_Pos                      11                                                        /*!< CGU PLL0AUDIO_CTRL: AUTOBLOCK Position */
#define CGU_PLL0AUDIO_CTRL_AUTOBLOCK_Msk                      (0x01UL << CGU_PLL0AUDIO_CTRL_AUTOBLOCK_Pos)              /*!< CGU PLL0AUDIO_CTRL: AUTOBLOCK Mask  */
#define CGU_PLL0AUDIO_CTRL_PLLFRAQ_REQ_Pos                    12                                                        /*!< CGU PLL0AUDIO_CTRL: PLLFRAQ_REQ Position */
#define CGU_PLL0AUDIO_CTRL_PLLFRAQ_REQ_Msk                    (0x01UL << CGU_PLL0AUDIO_CTRL_PLLFRAQ_REQ_Pos)            /*!< CGU PLL0AUDIO_CTRL: PLLFRAQ_REQ Mask */
#define CGU_PLL0AUDIO_CTRL_SEL_EXT_Pos                        13                                                        /*!< CGU PLL0AUDIO_CTRL: SEL_EXT Position */
#define CGU_PLL0AUDIO_CTRL_SEL_EXT_Msk                        (0x01UL << CGU_PLL0AUDIO_CTRL_SEL_EXT_Pos)                /*!< CGU PLL0AUDIO_CTRL: SEL_EXT Mask    */
#define CGU_PLL0AUDIO_CTRL_MOD_PD_Pos                         14                                                        /*!< CGU PLL0AUDIO_CTRL: MOD_PD Position */
#define CGU_PLL0AUDIO_CTRL_MOD_PD_Msk                         (0x01UL << CGU_PLL0AUDIO_CTRL_MOD_PD_Pos)                 /*!< CGU PLL0AUDIO_CTRL: MOD_PD Mask     */
#define CGU_PLL0AUDIO_CTRL_CLK_SEL_Pos                        24                                                        /*!< CGU PLL0AUDIO_CTRL: CLK_SEL Position */
#define CGU_PLL0AUDIO_CTRL_CLK_SEL_Msk                        (0x1fUL << CGU_PLL0AUDIO_CTRL_CLK_SEL_Pos)                /*!< CGU PLL0AUDIO_CTRL: CLK_SEL Mask    */

// -----------------------------------  CGU_PLL0AUDIO_MDIV  ---------------------------------------
#define CGU_PLL0AUDIO_MDIV_MDEC_Pos                           0                                                         /*!< CGU PLL0AUDIO_MDIV: MDEC Position   */
#define CGU_PLL0AUDIO_MDIV_MDEC_Msk                           (0x0001ffffUL << CGU_PLL0AUDIO_MDIV_MDEC_Pos)             /*!< CGU PLL0AUDIO_MDIV: MDEC Mask       */

// ----------------------------------  CGU_PLL0AUDIO_NP_DIV  --------------------------------------
#define CGU_PLL0AUDIO_NP_DIV_PDEC_Pos                         0                                                         /*!< CGU PLL0AUDIO_NP_DIV: PDEC Position */
#define CGU_PLL0AUDIO_NP_DIV_PDEC_Msk                         (0x7fUL << CGU_PLL0AUDIO_NP_DIV_PDEC_Pos)                 /*!< CGU PLL0AUDIO_NP_DIV: PDEC Mask     */
#define CGU_PLL0AUDIO_NP_DIV_NDEC_Pos                         12                                                        /*!< CGU PLL0AUDIO_NP_DIV: NDEC Position */
#define CGU_PLL0AUDIO_NP_DIV_NDEC_Msk                         (0x000003ffUL << CGU_PLL0AUDIO_NP_DIV_NDEC_Pos)           /*!< CGU PLL0AUDIO_NP_DIV: NDEC Mask     */

// -----------------------------------  CGU_PLL0AUDIO_FRAC  ---------------------------------------
#define CGU_PLL0AUDIO_FRAC_PLLFRACT_CTRL_Pos                  0                                                         /*!< CGU PLL0AUDIO_FRAC: PLLFRACT_CTRL Position */
#define CGU_PLL0AUDIO_FRAC_PLLFRACT_CTRL_Msk                  (0x003fffffUL << CGU_PLL0AUDIO_FRAC_PLLFRACT_CTRL_Pos)    /*!< CGU PLL0AUDIO_FRAC: PLLFRACT_CTRL Mask */

// --------------------------------------  CGU_PLL1_STAT  -----------------------------------------
#define CGU_PLL1_STAT_LOCK_Pos                                0                                                         /*!< CGU PLL1_STAT: LOCK Position        */
#define CGU_PLL1_STAT_LOCK_Msk                                (0x01UL << CGU_PLL1_STAT_LOCK_Pos)                        /*!< CGU PLL1_STAT: LOCK Mask            */

// --------------------------------------  CGU_PLL1_CTRL  -----------------------------------------
#define CGU_PLL1_CTRL_PD_Pos                                  0                                                         /*!< CGU PLL1_CTRL: PD Position          */
#define CGU_PLL1_CTRL_PD_Msk                                  (0x01UL << CGU_PLL1_CTRL_PD_Pos)                          /*!< CGU PLL1_CTRL: PD Mask              */
#define CGU_PLL1_CTRL_BYPASS_Pos                              1                                                         /*!< CGU PLL1_CTRL: BYPASS Position      */
#define CGU_PLL1_CTRL_BYPASS_Msk                              (0x01UL << CGU_PLL1_CTRL_BYPASS_Pos)                      /*!< CGU PLL1_CTRL: BYPASS Mask          */
#define CGU_PLL1_CTRL_FBSEL_Pos                               6                                                         /*!< CGU PLL1_CTRL: FBSEL Position       */
#define CGU_PLL1_CTRL_FBSEL_Msk                               (0x01UL << CGU_PLL1_CTRL_FBSEL_Pos)                       /*!< CGU PLL1_CTRL: FBSEL Mask           */
#define CGU_PLL1_CTRL_DIRECT_Pos                              7                                                         /*!< CGU PLL1_CTRL: DIRECT Position      */
#define CGU_PLL1_CTRL_DIRECT_Msk                              (0x01UL << CGU_PLL1_CTRL_DIRECT_Pos)                      /*!< CGU PLL1_CTRL: DIRECT Mask          */
#define CGU_PLL1_CTRL_PSEL_Pos                                8                                                         /*!< CGU PLL1_CTRL: PSEL Position        */
#define CGU_PLL1_CTRL_PSEL_Msk                                (0x03UL << CGU_PLL1_CTRL_PSEL_Pos)                        /*!< CGU PLL1_CTRL: PSEL Mask            */
#define CGU_PLL1_CTRL_AUTOBLOCK_Pos                           11                                                        /*!< CGU PLL1_CTRL: AUTOBLOCK Position   */
#define CGU_PLL1_CTRL_AUTOBLOCK_Msk                           (0x01UL << CGU_PLL1_CTRL_AUTOBLOCK_Pos)                   /*!< CGU PLL1_CTRL: AUTOBLOCK Mask       */
#define CGU_PLL1_CTRL_NSEL_Pos                                12                                                        /*!< CGU PLL1_CTRL: NSEL Position        */
#define CGU_PLL1_CTRL_NSEL_Msk                                (0x03UL << CGU_PLL1_CTRL_NSEL_Pos)                        /*!< CGU PLL1_CTRL: NSEL Mask            */
#define CGU_PLL1_CTRL_MSEL_Pos                                16                                                        /*!< CGU PLL1_CTRL: MSEL Position        */
#define CGU_PLL1_CTRL_MSEL_Msk                                (0x000000ffUL << CGU_PLL1_CTRL_MSEL_Pos)                  /*!< CGU PLL1_CTRL: MSEL Mask            */
#define CGU_PLL1_CTRL_CLK_SEL_Pos                             24                                                        /*!< CGU PLL1_CTRL: CLK_SEL Position     */
#define CGU_PLL1_CTRL_CLK_SEL_Msk                             (0x1fUL << CGU_PLL1_CTRL_CLK_SEL_Pos)                     /*!< CGU PLL1_CTRL: CLK_SEL Mask         */

// -------------------------------------  CGU_IDIVA_CTRL  -----------------------------------------
#define CGU_IDIVA_CTRL_PD_Pos                                 0                                                         /*!< CGU IDIVA_CTRL: PD Position         */
#define CGU_IDIVA_CTRL_PD_Msk                                 (0x01UL << CGU_IDIVA_CTRL_PD_Pos)                         /*!< CGU IDIVA_CTRL: PD Mask             */
#define CGU_IDIVA_CTRL_IDIV_Pos                               2                                                         /*!< CGU IDIVA_CTRL: IDIV Position       */
#define CGU_IDIVA_CTRL_IDIV_Msk                               (0x03UL << CGU_IDIVA_CTRL_IDIV_Pos)                       /*!< CGU IDIVA_CTRL: IDIV Mask           */
#define CGU_IDIVA_CTRL_AUTOBLOCK_Pos                          11                                                        /*!< CGU IDIVA_CTRL: AUTOBLOCK Position  */
#define CGU_IDIVA_CTRL_AUTOBLOCK_Msk                          (0x01UL << CGU_IDIVA_CTRL_AUTOBLOCK_Pos)                  /*!< CGU IDIVA_CTRL: AUTOBLOCK Mask      */
#define CGU_IDIVA_CTRL_CLK_SEL_Pos                            24                                                        /*!< CGU IDIVA_CTRL: CLK_SEL Position    */
#define CGU_IDIVA_CTRL_CLK_SEL_Msk                            (0x1fUL << CGU_IDIVA_CTRL_CLK_SEL_Pos)                    /*!< CGU IDIVA_CTRL: CLK_SEL Mask        */

// -------------------------------------  CGU_IDIVB_CTRL  -----------------------------------------
#define CGU_IDIVB_CTRL_PD_Pos                                 0                                                         /*!< CGU IDIVB_CTRL: PD Position         */
#define CGU_IDIVB_CTRL_PD_Msk                                 (0x01UL << CGU_IDIVB_CTRL_PD_Pos)                         /*!< CGU IDIVB_CTRL: PD Mask             */
#define CGU_IDIVB_CTRL_IDIV_Pos                               2                                                         /*!< CGU IDIVB_CTRL: IDIV Position       */
#define CGU_IDIVB_CTRL_IDIV_Msk                               (0x0fUL << CGU_IDIVB_CTRL_IDIV_Pos)                       /*!< CGU IDIVB_CTRL: IDIV Mask           */
#define CGU_IDIVB_CTRL_AUTOBLOCK_Pos                          11                                                        /*!< CGU IDIVB_CTRL: AUTOBLOCK Position  */
#define CGU_IDIVB_CTRL_AUTOBLOCK_Msk                          (0x01UL << CGU_IDIVB_CTRL_AUTOBLOCK_Pos)                  /*!< CGU IDIVB_CTRL: AUTOBLOCK Mask      */
#define CGU_IDIVB_CTRL_CLK_SEL_Pos                            24                                                        /*!< CGU IDIVB_CTRL: CLK_SEL Position    */
#define CGU_IDIVB_CTRL_CLK_SEL_Msk                            (0x1fUL << CGU_IDIVB_CTRL_CLK_SEL_Pos)                    /*!< CGU IDIVB_CTRL: CLK_SEL Mask        */

// -------------------------------------  CGU_IDIVE_CTRL  -----------------------------------------
#define CGU_IDIVE_CTRL_PD_Pos                                 0                                                         /*!< CGU IDIVE_CTRL: PD Position         */
#define CGU_IDIVE_CTRL_PD_Msk                                 (0x01UL << CGU_IDIVE_CTRL_PD_Pos)                         /*!< CGU IDIVE_CTRL: PD Mask             */
#define CGU_IDIVE_CTRL_IDIV_Pos                               2                                                         /*!< CGU IDIVE_CTRL: IDIV Position       */
#define CGU_IDIVE_CTRL_IDIV_Msk                               (0x000000ffUL << CGU_IDIVE_CTRL_IDIV_Pos)                 /*!< CGU IDIVE_CTRL: IDIV Mask           */
#define CGU_IDIVE_CTRL_AUTOBLOCK_Pos                          11                                                        /*!< CGU IDIVE_CTRL: AUTOBLOCK Position  */
#define CGU_IDIVE_CTRL_AUTOBLOCK_Msk                          (0x01UL << CGU_IDIVE_CTRL_AUTOBLOCK_Pos)                  /*!< CGU IDIVE_CTRL: AUTOBLOCK Mask      */
#define CGU_IDIVE_CTRL_CLK_SEL_Pos                            24                                                        /*!< CGU IDIVE_CTRL: CLK_SEL Position    */
#define CGU_IDIVE_CTRL_CLK_SEL_Msk                            (0x1fUL << CGU_IDIVE_CTRL_CLK_SEL_Pos)                    /*!< CGU IDIVE_CTRL: CLK_SEL Mask        */

// ------------------------------------  CGU_BASE_SAFE_CLK  ---------------------------------------
#define CGU_BASE_SAFE_CLK_PD_Pos                              0                                                         /*!< CGU BASE_SAFE_CLK: PD Position      */
#define CGU_BASE_SAFE_CLK_PD_Msk                              (0x01UL << CGU_BASE_SAFE_CLK_PD_Pos)                      /*!< CGU BASE_SAFE_CLK: PD Mask          */
#define CGU_BASE_SAFE_CLK_AUTOBLOCK_Pos                       11                                                        /*!< CGU BASE_SAFE_CLK: AUTOBLOCK Position */
#define CGU_BASE_SAFE_CLK_AUTOBLOCK_Msk                       (0x01UL << CGU_BASE_SAFE_CLK_AUTOBLOCK_Pos)               /*!< CGU BASE_SAFE_CLK: AUTOBLOCK Mask   */
#define CGU_BASE_SAFE_CLK_CLK_SEL_Pos                         24                                                        /*!< CGU BASE_SAFE_CLK: CLK_SEL Position */
#define CGU_BASE_SAFE_CLK_CLK_SEL_Msk                         (0x1fUL << CGU_BASE_SAFE_CLK_CLK_SEL_Pos)                 /*!< CGU BASE_SAFE_CLK: CLK_SEL Mask     */

// ------------------------------------  CGU_BASE_USB0_CLK  ---------------------------------------
#define CGU_BASE_USB0_CLK_PD_Pos                              0                                                         /*!< CGU BASE_USB0_CLK: PD Position      */
#define CGU_BASE_USB0_CLK_PD_Msk                              (0x01UL << CGU_BASE_USB0_CLK_PD_Pos)                      /*!< CGU BASE_USB0_CLK: PD Mask          */
#define CGU_BASE_USB0_CLK_AUTOBLOCK_Pos                       11                                                        /*!< CGU BASE_USB0_CLK: AUTOBLOCK Position */
#define CGU_BASE_USB0_CLK_AUTOBLOCK_Msk                       (0x01UL << CGU_BASE_USB0_CLK_AUTOBLOCK_Pos)               /*!< CGU BASE_USB0_CLK: AUTOBLOCK Mask   */
#define CGU_BASE_USB0_CLK_CLK_SEL_Pos                         24                                                        /*!< CGU BASE_USB0_CLK: CLK_SEL Position */
#define CGU_BASE_USB0_CLK_CLK_SEL_Msk                         (0x1fUL << CGU_BASE_USB0_CLK_CLK_SEL_Pos)                 /*!< CGU BASE_USB0_CLK: CLK_SEL Mask     */

// -----------------------------------  CGU_BASE_PERIPH_CLK  --------------------------------------
#define CGU_BASE_PERIPH_CLK_PD_Pos                            0                                                         /*!< CGU BASE_PERIPH_CLK: PD Position    */
#define CGU_BASE_PERIPH_CLK_PD_Msk                            (0x01UL << CGU_BASE_PERIPH_CLK_PD_Pos)                    /*!< CGU BASE_PERIPH_CLK: PD Mask        */
#define CGU_BASE_PERIPH_CLK_AUTOBLOCK_Pos                     11                                                        /*!< CGU BASE_PERIPH_CLK: AUTOBLOCK Position */
#define CGU_BASE_PERIPH_CLK_AUTOBLOCK_Msk                     (0x01UL << CGU_BASE_PERIPH_CLK_AUTOBLOCK_Pos)             /*!< CGU BASE_PERIPH_CLK: AUTOBLOCK Mask */
#define CGU_BASE_PERIPH_CLK_CLK_SEL_Pos                       24                                                        /*!< CGU BASE_PERIPH_CLK: CLK_SEL Position */
#define CGU_BASE_PERIPH_CLK_CLK_SEL_Msk                       (0x1fUL << CGU_BASE_PERIPH_CLK_CLK_SEL_Pos)               /*!< CGU BASE_PERIPH_CLK: CLK_SEL Mask   */

// ------------------------------------  CGU_BASE_USB1_CLK  ---------------------------------------
#define CGU_BASE_USB1_CLK_PD_Pos                              0                                                         /*!< CGU BASE_USB1_CLK: PD Position      */
#define CGU_BASE_USB1_CLK_PD_Msk                              (0x01UL << CGU_BASE_USB1_CLK_PD_Pos)                      /*!< CGU BASE_USB1_CLK: PD Mask          */
#define CGU_BASE_USB1_CLK_AUTOBLOCK_Pos                       11                                                        /*!< CGU BASE_USB1_CLK: AUTOBLOCK Position */
#define CGU_BASE_USB1_CLK_AUTOBLOCK_Msk                       (0x01UL << CGU_BASE_USB1_CLK_AUTOBLOCK_Pos)               /*!< CGU BASE_USB1_CLK: AUTOBLOCK Mask   */
#define CGU_BASE_USB1_CLK_CLK_SEL_Pos                         24                                                        /*!< CGU BASE_USB1_CLK: CLK_SEL Position */
#define CGU_BASE_USB1_CLK_CLK_SEL_Msk                         (0x1fUL << CGU_BASE_USB1_CLK_CLK_SEL_Pos)                 /*!< CGU BASE_USB1_CLK: CLK_SEL Mask     */

// -------------------------------------  CGU_BASE_M4_CLK  ----------------------------------------
#define CGU_BASE_M4_CLK_PD_Pos                                0                                                         /*!< CGU BASE_M4_CLK: PD Position        */
#define CGU_BASE_M4_CLK_PD_Msk                                (0x01UL << CGU_BASE_M4_CLK_PD_Pos)                        /*!< CGU BASE_M4_CLK: PD Mask            */
#define CGU_BASE_M4_CLK_AUTOBLOCK_Pos                         11                                                        /*!< CGU BASE_M4_CLK: AUTOBLOCK Position */
#define CGU_BASE_M4_CLK_AUTOBLOCK_Msk                         (0x01UL << CGU_BASE_M4_CLK_AUTOBLOCK_Pos)                 /*!< CGU BASE_M4_CLK: AUTOBLOCK Mask     */
#define CGU_BASE_M4_CLK_CLK_SEL_Pos                           24                                                        /*!< CGU BASE_M4_CLK: CLK_SEL Position   */
#define CGU_BASE_M4_CLK_CLK_SEL_Msk                           (0x1fUL << CGU_BASE_M4_CLK_CLK_SEL_Pos)                   /*!< CGU BASE_M4_CLK: CLK_SEL Mask       */

// -----------------------------------  CGU_BASE_SPIFI_CLK  ---------------------------------------
#define CGU_BASE_SPIFI_CLK_PD_Pos                             0                                                         /*!< CGU BASE_SPIFI_CLK: PD Position     */
#define CGU_BASE_SPIFI_CLK_PD_Msk                             (0x01UL << CGU_BASE_SPIFI_CLK_PD_Pos)                     /*!< CGU BASE_SPIFI_CLK: PD Mask         */
#define CGU_BASE_SPIFI_CLK_AUTOBLOCK_Pos                      11                                                        /*!< CGU BASE_SPIFI_CLK: AUTOBLOCK Position */
#define CGU_BASE_SPIFI_CLK_AUTOBLOCK_Msk                      (0x01UL << CGU_BASE_SPIFI_CLK_AUTOBLOCK_Pos)              /*!< CGU BASE_SPIFI_CLK: AUTOBLOCK Mask  */
#define CGU_BASE_SPIFI_CLK_CLK_SEL_Pos                        24                                                        /*!< CGU BASE_SPIFI_CLK: CLK_SEL Position */
#define CGU_BASE_SPIFI_CLK_CLK_SEL_Msk                        (0x1fUL << CGU_BASE_SPIFI_CLK_CLK_SEL_Pos)                /*!< CGU BASE_SPIFI_CLK: CLK_SEL Mask    */

// ------------------------------------  CGU_BASE_SPI_CLK  ----------------------------------------
#define CGU_BASE_SPI_CLK_PD_Pos                               0                                                         /*!< CGU BASE_SPI_CLK: PD Position       */
#define CGU_BASE_SPI_CLK_PD_Msk                               (0x01UL << CGU_BASE_SPI_CLK_PD_Pos)                       /*!< CGU BASE_SPI_CLK: PD Mask           */
#define CGU_BASE_SPI_CLK_AUTOBLOCK_Pos                        11                                                        /*!< CGU BASE_SPI_CLK: AUTOBLOCK Position */
#define CGU_BASE_SPI_CLK_AUTOBLOCK_Msk                        (0x01UL << CGU_BASE_SPI_CLK_AUTOBLOCK_Pos)                /*!< CGU BASE_SPI_CLK: AUTOBLOCK Mask    */
#define CGU_BASE_SPI_CLK_CLK_SEL_Pos                          24                                                        /*!< CGU BASE_SPI_CLK: CLK_SEL Position  */
#define CGU_BASE_SPI_CLK_CLK_SEL_Msk                          (0x1fUL << CGU_BASE_SPI_CLK_CLK_SEL_Pos)                  /*!< CGU BASE_SPI_CLK: CLK_SEL Mask      */

// -----------------------------------  CGU_BASE_PHY_RX_CLK  --------------------------------------
#define CGU_BASE_PHY_RX_CLK_PD_Pos                            0                                                         /*!< CGU BASE_PHY_RX_CLK: PD Position    */
#define CGU_BASE_PHY_RX_CLK_PD_Msk                            (0x01UL << CGU_BASE_PHY_RX_CLK_PD_Pos)                    /*!< CGU BASE_PHY_RX_CLK: PD Mask        */
#define CGU_BASE_PHY_RX_CLK_AUTOBLOCK_Pos                     11                                                        /*!< CGU BASE_PHY_RX_CLK: AUTOBLOCK Position */
#define CGU_BASE_PHY_RX_CLK_AUTOBLOCK_Msk                     (0x01UL << CGU_BASE_PHY_RX_CLK_AUTOBLOCK_Pos)             /*!< CGU BASE_PHY_RX_CLK: AUTOBLOCK Mask */
#define CGU_BASE_PHY_RX_CLK_CLK_SEL_Pos                       24                                                        /*!< CGU BASE_PHY_RX_CLK: CLK_SEL Position */
#define CGU_BASE_PHY_RX_CLK_CLK_SEL_Msk                       (0x1fUL << CGU_BASE_PHY_RX_CLK_CLK_SEL_Pos)               /*!< CGU BASE_PHY_RX_CLK: CLK_SEL Mask   */

// -----------------------------------  CGU_BASE_PHY_TX_CLK  --------------------------------------
#define CGU_BASE_PHY_TX_CLK_PD_Pos                            0                                                         /*!< CGU BASE_PHY_TX_CLK: PD Position    */
#define CGU_BASE_PHY_TX_CLK_PD_Msk                            (0x01UL << CGU_BASE_PHY_TX_CLK_PD_Pos)                    /*!< CGU BASE_PHY_TX_CLK: PD Mask        */
#define CGU_BASE_PHY_TX_CLK_AUTOBLOCK_Pos                     11                                                        /*!< CGU BASE_PHY_TX_CLK: AUTOBLOCK Position */
#define CGU_BASE_PHY_TX_CLK_AUTOBLOCK_Msk                     (0x01UL << CGU_BASE_PHY_TX_CLK_AUTOBLOCK_Pos)             /*!< CGU BASE_PHY_TX_CLK: AUTOBLOCK Mask */
#define CGU_BASE_PHY_TX_CLK_CLK_SEL_Pos                       24                                                        /*!< CGU BASE_PHY_TX_CLK: CLK_SEL Position */
#define CGU_BASE_PHY_TX_CLK_CLK_SEL_Msk                       (0x1fUL << CGU_BASE_PHY_TX_CLK_CLK_SEL_Pos)               /*!< CGU BASE_PHY_TX_CLK: CLK_SEL Mask   */

// ------------------------------------  CGU_BASE_APB1_CLK  ---------------------------------------
#define CGU_BASE_APB1_CLK_PD_Pos                              0                                                         /*!< CGU BASE_APB1_CLK: PD Position      */
#define CGU_BASE_APB1_CLK_PD_Msk                              (0x01UL << CGU_BASE_APB1_CLK_PD_Pos)                      /*!< CGU BASE_APB1_CLK: PD Mask          */
#define CGU_BASE_APB1_CLK_AUTOBLOCK_Pos                       11                                                        /*!< CGU BASE_APB1_CLK: AUTOBLOCK Position */
#define CGU_BASE_APB1_CLK_AUTOBLOCK_Msk                       (0x01UL << CGU_BASE_APB1_CLK_AUTOBLOCK_Pos)               /*!< CGU BASE_APB1_CLK: AUTOBLOCK Mask   */
#define CGU_BASE_APB1_CLK_CLK_SEL_Pos                         24                                                        /*!< CGU BASE_APB1_CLK: CLK_SEL Position */
#define CGU_BASE_APB1_CLK_CLK_SEL_Msk                         (0x1fUL << CGU_BASE_APB1_CLK_CLK_SEL_Pos)                 /*!< CGU BASE_APB1_CLK: CLK_SEL Mask     */

// ------------------------------------  CGU_BASE_APB3_CLK  ---------------------------------------
#define CGU_BASE_APB3_CLK_PD_Pos                              0                                                         /*!< CGU BASE_APB3_CLK: PD Position      */
#define CGU_BASE_APB3_CLK_PD_Msk                              (0x01UL << CGU_BASE_APB3_CLK_PD_Pos)                      /*!< CGU BASE_APB3_CLK: PD Mask          */
#define CGU_BASE_APB3_CLK_AUTOBLOCK_Pos                       11                                                        /*!< CGU BASE_APB3_CLK: AUTOBLOCK Position */
#define CGU_BASE_APB3_CLK_AUTOBLOCK_Msk                       (0x01UL << CGU_BASE_APB3_CLK_AUTOBLOCK_Pos)               /*!< CGU BASE_APB3_CLK: AUTOBLOCK Mask   */
#define CGU_BASE_APB3_CLK_CLK_SEL_Pos                         24                                                        /*!< CGU BASE_APB3_CLK: CLK_SEL Position */
#define CGU_BASE_APB3_CLK_CLK_SEL_Msk                         (0x1fUL << CGU_BASE_APB3_CLK_CLK_SEL_Pos)                 /*!< CGU BASE_APB3_CLK: CLK_SEL Mask     */

// ------------------------------------  CGU_BASE_LCD_CLK  ----------------------------------------
#define CGU_BASE_LCD_CLK_PD_Pos                               0                                                         /*!< CGU BASE_LCD_CLK: PD Position       */
#define CGU_BASE_LCD_CLK_PD_Msk                               (0x01UL << CGU_BASE_LCD_CLK_PD_Pos)                       /*!< CGU BASE_LCD_CLK: PD Mask           */
#define CGU_BASE_LCD_CLK_AUTOBLOCK_Pos                        11                                                        /*!< CGU BASE_LCD_CLK: AUTOBLOCK Position */
#define CGU_BASE_LCD_CLK_AUTOBLOCK_Msk                        (0x01UL << CGU_BASE_LCD_CLK_AUTOBLOCK_Pos)                /*!< CGU BASE_LCD_CLK: AUTOBLOCK Mask    */
#define CGU_BASE_LCD_CLK_CLK_SEL_Pos                          24                                                        /*!< CGU BASE_LCD_CLK: CLK_SEL Position  */
#define CGU_BASE_LCD_CLK_CLK_SEL_Msk                          (0x1fUL << CGU_BASE_LCD_CLK_CLK_SEL_Pos)                  /*!< CGU BASE_LCD_CLK: CLK_SEL Mask      */

// ------------------------------------  CGU_BASE_SDIO_CLK  ---------------------------------------
#define CGU_BASE_SDIO_CLK_PD_Pos                              0                                                         /*!< CGU BASE_SDIO_CLK: PD Position      */
#define CGU_BASE_SDIO_CLK_PD_Msk                              (0x01UL << CGU_BASE_SDIO_CLK_PD_Pos)                      /*!< CGU BASE_SDIO_CLK: PD Mask          */
#define CGU_BASE_SDIO_CLK_AUTOBLOCK_Pos                       11                                                        /*!< CGU BASE_SDIO_CLK: AUTOBLOCK Position */
#define CGU_BASE_SDIO_CLK_AUTOBLOCK_Msk                       (0x01UL << CGU_BASE_SDIO_CLK_AUTOBLOCK_Pos)               /*!< CGU BASE_SDIO_CLK: AUTOBLOCK Mask   */
#define CGU_BASE_SDIO_CLK_CLK_SEL_Pos                         24                                                        /*!< CGU BASE_SDIO_CLK: CLK_SEL Position */
#define CGU_BASE_SDIO_CLK_CLK_SEL_Msk                         (0x1fUL << CGU_BASE_SDIO_CLK_CLK_SEL_Pos)                 /*!< CGU BASE_SDIO_CLK: CLK_SEL Mask     */

// ------------------------------------  CGU_BASE_SSP0_CLK  ---------------------------------------
#define CGU_BASE_SSP0_CLK_PD_Pos                              0                                                         /*!< CGU BASE_SSP0_CLK: PD Position      */
#define CGU_BASE_SSP0_CLK_PD_Msk                              (0x01UL << CGU_BASE_SSP0_CLK_PD_Pos)                      /*!< CGU BASE_SSP0_CLK: PD Mask          */
#define CGU_BASE_SSP0_CLK_AUTOBLOCK_Pos                       11                                                        /*!< CGU BASE_SSP0_CLK: AUTOBLOCK Position */
#define CGU_BASE_SSP0_CLK_AUTOBLOCK_Msk                       (0x01UL << CGU_BASE_SSP0_CLK_AUTOBLOCK_Pos)               /*!< CGU BASE_SSP0_CLK: AUTOBLOCK Mask   */
#define CGU_BASE_SSP0_CLK_CLK_SEL_Pos                         24                                                        /*!< CGU BASE_SSP0_CLK: CLK_SEL Position */
#define CGU_BASE_SSP0_CLK_CLK_SEL_Msk                         (0x1fUL << CGU_BASE_SSP0_CLK_CLK_SEL_Pos)                 /*!< CGU BASE_SSP0_CLK: CLK_SEL Mask     */

// ------------------------------------  CGU_BASE_SSP1_CLK  ---------------------------------------
#define CGU_BASE_SSP1_CLK_PD_Pos                              0                                                         /*!< CGU BASE_SSP1_CLK: PD Position      */
#define CGU_BASE_SSP1_CLK_PD_Msk                              (0x01UL << CGU_BASE_SSP1_CLK_PD_Pos)                      /*!< CGU BASE_SSP1_CLK: PD Mask          */
#define CGU_BASE_SSP1_CLK_AUTOBLOCK_Pos                       11                                                        /*!< CGU BASE_SSP1_CLK: AUTOBLOCK Position */
#define CGU_BASE_SSP1_CLK_AUTOBLOCK_Msk                       (0x01UL << CGU_BASE_SSP1_CLK_AUTOBLOCK_Pos)               /*!< CGU BASE_SSP1_CLK: AUTOBLOCK Mask   */
#define CGU_BASE_SSP1_CLK_CLK_SEL_Pos                         24                                                        /*!< CGU BASE_SSP1_CLK: CLK_SEL Position */
#define CGU_BASE_SSP1_CLK_CLK_SEL_Msk                         (0x1fUL << CGU_BASE_SSP1_CLK_CLK_SEL_Pos)                 /*!< CGU BASE_SSP1_CLK: CLK_SEL Mask     */

// -----------------------------------  CGU_BASE_UART0_CLK  ---------------------------------------
#define CGU_BASE_UART0_CLK_PD_Pos                             0                                                         /*!< CGU BASE_UART0_CLK: PD Position     */
#define CGU_BASE_UART0_CLK_PD_Msk                             (0x01UL << CGU_BASE_UART0_CLK_PD_Pos)                     /*!< CGU BASE_UART0_CLK: PD Mask         */
#define CGU_BASE_UART0_CLK_AUTOBLOCK_Pos                      11                                                        /*!< CGU BASE_UART0_CLK: AUTOBLOCK Position */
#define CGU_BASE_UART0_CLK_AUTOBLOCK_Msk                      (0x01UL << CGU_BASE_UART0_CLK_AUTOBLOCK_Pos)              /*!< CGU BASE_UART0_CLK: AUTOBLOCK Mask  */
#define CGU_BASE_UART0_CLK_CLK_SEL_Pos                        24                                                        /*!< CGU BASE_UART0_CLK: CLK_SEL Position */
#define CGU_BASE_UART0_CLK_CLK_SEL_Msk                        (0x1fUL << CGU_BASE_UART0_CLK_CLK_SEL_Pos)                /*!< CGU BASE_UART0_CLK: CLK_SEL Mask    */

// -----------------------------------  CGU_BASE_UART1_CLK  ---------------------------------------
#define CGU_BASE_UART1_CLK_PD_Pos                             0                                                         /*!< CGU BASE_UART1_CLK: PD Position     */
#define CGU_BASE_UART1_CLK_PD_Msk                             (0x01UL << CGU_BASE_UART1_CLK_PD_Pos)                     /*!< CGU BASE_UART1_CLK: PD Mask         */
#define CGU_BASE_UART1_CLK_AUTOBLOCK_Pos                      11                                                        /*!< CGU BASE_UART1_CLK: AUTOBLOCK Position */
#define CGU_BASE_UART1_CLK_AUTOBLOCK_Msk                      (0x01UL << CGU_BASE_UART1_CLK_AUTOBLOCK_Pos)              /*!< CGU BASE_UART1_CLK: AUTOBLOCK Mask  */
#define CGU_BASE_UART1_CLK_CLK_SEL_Pos                        24                                                        /*!< CGU BASE_UART1_CLK: CLK_SEL Position */
#define CGU_BASE_UART1_CLK_CLK_SEL_Msk                        (0x1fUL << CGU_BASE_UART1_CLK_CLK_SEL_Pos)                /*!< CGU BASE_UART1_CLK: CLK_SEL Mask    */

// -----------------------------------  CGU_BASE_UART2_CLK  ---------------------------------------
#define CGU_BASE_UART2_CLK_PD_Pos                             0                                                         /*!< CGU BASE_UART2_CLK: PD Position     */
#define CGU_BASE_UART2_CLK_PD_Msk                             (0x01UL << CGU_BASE_UART2_CLK_PD_Pos)                     /*!< CGU BASE_UART2_CLK: PD Mask         */
#define CGU_BASE_UART2_CLK_AUTOBLOCK_Pos                      11                                                        /*!< CGU BASE_UART2_CLK: AUTOBLOCK Position */
#define CGU_BASE_UART2_CLK_AUTOBLOCK_Msk                      (0x01UL << CGU_BASE_UART2_CLK_AUTOBLOCK_Pos)              /*!< CGU BASE_UART2_CLK: AUTOBLOCK Mask  */
#define CGU_BASE_UART2_CLK_CLK_SEL_Pos                        24                                                        /*!< CGU BASE_UART2_CLK: CLK_SEL Position */
#define CGU_BASE_UART2_CLK_CLK_SEL_Msk                        (0x1fUL << CGU_BASE_UART2_CLK_CLK_SEL_Pos)                /*!< CGU BASE_UART2_CLK: CLK_SEL Mask    */

// -----------------------------------  CGU_BASE_UART3_CLK  ---------------------------------------
#define CGU_BASE_UART3_CLK_PD_Pos                             0                                                         /*!< CGU BASE_UART3_CLK: PD Position     */
#define CGU_BASE_UART3_CLK_PD_Msk                             (0x01UL << CGU_BASE_UART3_CLK_PD_Pos)                     /*!< CGU BASE_UART3_CLK: PD Mask         */
#define CGU_BASE_UART3_CLK_AUTOBLOCK_Pos                      11                                                        /*!< CGU BASE_UART3_CLK: AUTOBLOCK Position */
#define CGU_BASE_UART3_CLK_AUTOBLOCK_Msk                      (0x01UL << CGU_BASE_UART3_CLK_AUTOBLOCK_Pos)              /*!< CGU BASE_UART3_CLK: AUTOBLOCK Mask  */
#define CGU_BASE_UART3_CLK_CLK_SEL_Pos                        24                                                        /*!< CGU BASE_UART3_CLK: CLK_SEL Position */
#define CGU_BASE_UART3_CLK_CLK_SEL_Msk                        (0x1fUL << CGU_BASE_UART3_CLK_CLK_SEL_Pos)                /*!< CGU BASE_UART3_CLK: CLK_SEL Mask    */

// ------------------------------------  CGU_BASE_OUT_CLK  ----------------------------------------
#define CGU_BASE_OUT_CLK_PD_Pos                               0                                                         /*!< CGU BASE_OUT_CLK: PD Position       */
#define CGU_BASE_OUT_CLK_PD_Msk                               (0x01UL << CGU_BASE_OUT_CLK_PD_Pos)                       /*!< CGU BASE_OUT_CLK: PD Mask           */
#define CGU_BASE_OUT_CLK_AUTOBLOCK_Pos                        11                                                        /*!< CGU BASE_OUT_CLK: AUTOBLOCK Position */
#define CGU_BASE_OUT_CLK_AUTOBLOCK_Msk                        (0x01UL << CGU_BASE_OUT_CLK_AUTOBLOCK_Pos)                /*!< CGU BASE_OUT_CLK: AUTOBLOCK Mask    */
#define CGU_BASE_OUT_CLK_CLK_SEL_Pos                          24                                                        /*!< CGU BASE_OUT_CLK: CLK_SEL Position  */
#define CGU_BASE_OUT_CLK_CLK_SEL_Msk                          (0x1fUL << CGU_BASE_OUT_CLK_CLK_SEL_Pos)                  /*!< CGU BASE_OUT_CLK: CLK_SEL Mask      */

// ------------------------------------  CGU_BASE_APLL_CLK  ---------------------------------------
#define CGU_BASE_APLL_CLK_PD_Pos                              0                                                         /*!< CGU BASE_APLL_CLK: PD Position      */
#define CGU_BASE_APLL_CLK_PD_Msk                              (0x01UL << CGU_BASE_APLL_CLK_PD_Pos)                      /*!< CGU BASE_APLL_CLK: PD Mask          */
#define CGU_BASE_APLL_CLK_AUTOBLOCK_Pos                       11                                                        /*!< CGU BASE_APLL_CLK: AUTOBLOCK Position */
#define CGU_BASE_APLL_CLK_AUTOBLOCK_Msk                       (0x01UL << CGU_BASE_APLL_CLK_AUTOBLOCK_Pos)               /*!< CGU BASE_APLL_CLK: AUTOBLOCK Mask   */
#define CGU_BASE_APLL_CLK_CLK_SEL_Pos                         24                                                        /*!< CGU BASE_APLL_CLK: CLK_SEL Position */
#define CGU_BASE_APLL_CLK_CLK_SEL_Msk                         (0x1fUL << CGU_BASE_APLL_CLK_CLK_SEL_Pos)                 /*!< CGU BASE_APLL_CLK: CLK_SEL Mask     */

// ----------------------------------  CGU_BASE_CGU_OUT0_CLK  -------------------------------------
#define CGU_BASE_CGU_OUT0_CLK_PD_Pos                          0                                                         /*!< CGU BASE_CGU_OUT0_CLK: PD Position  */
#define CGU_BASE_CGU_OUT0_CLK_PD_Msk                          (0x01UL << CGU_BASE_CGU_OUT0_CLK_PD_Pos)                  /*!< CGU BASE_CGU_OUT0_CLK: PD Mask      */
#define CGU_BASE_CGU_OUT0_CLK_AUTOBLOCK_Pos                   11                                                        /*!< CGU BASE_CGU_OUT0_CLK: AUTOBLOCK Position */
#define CGU_BASE_CGU_OUT0_CLK_AUTOBLOCK_Msk                   (0x01UL << CGU_BASE_CGU_OUT0_CLK_AUTOBLOCK_Pos)           /*!< CGU BASE_CGU_OUT0_CLK: AUTOBLOCK Mask */
#define CGU_BASE_CGU_OUT0_CLK_CLK_SEL_Pos                     24                                                        /*!< CGU BASE_CGU_OUT0_CLK: CLK_SEL Position */
#define CGU_BASE_CGU_OUT0_CLK_CLK_SEL_Msk                     (0x1fUL << CGU_BASE_CGU_OUT0_CLK_CLK_SEL_Pos)             /*!< CGU BASE_CGU_OUT0_CLK: CLK_SEL Mask */

// ----------------------------------  CGU_BASE_CGU_OUT1_CLK  -------------------------------------
#define CGU_BASE_CGU_OUT1_CLK_PD_Pos                          0                                                         /*!< CGU BASE_CGU_OUT1_CLK: PD Position  */
#define CGU_BASE_CGU_OUT1_CLK_PD_Msk                          (0x01UL << CGU_BASE_CGU_OUT1_CLK_PD_Pos)                  /*!< CGU BASE_CGU_OUT1_CLK: PD Mask      */
#define CGU_BASE_CGU_OUT1_CLK_AUTOBLOCK_Pos                   11                                                        /*!< CGU BASE_CGU_OUT1_CLK: AUTOBLOCK Position */
#define CGU_BASE_CGU_OUT1_CLK_AUTOBLOCK_Msk                   (0x01UL << CGU_BASE_CGU_OUT1_CLK_AUTOBLOCK_Pos)           /*!< CGU BASE_CGU_OUT1_CLK: AUTOBLOCK Mask */
#define CGU_BASE_CGU_OUT1_CLK_CLK_SEL_Pos                     24                                                        /*!< CGU BASE_CGU_OUT1_CLK: CLK_SEL Position */
#define CGU_BASE_CGU_OUT1_CLK_CLK_SEL_Msk                     (0x1fUL << CGU_BASE_CGU_OUT1_CLK_CLK_SEL_Pos)             /*!< CGU BASE_CGU_OUT1_CLK: CLK_SEL Mask */

// -------------------------------------  CGU_IDIVC_CTRL  -----------------------------------------
#define CGU_IDIVC_CTRL_PD_Pos                                 0                                                         /*!< CGU IDIVC_CTRL: PD Position         */
#define CGU_IDIVC_CTRL_PD_Msk                                 (0x01UL << CGU_IDIVC_CTRL_PD_Pos)                         /*!< CGU IDIVC_CTRL: PD Mask             */
#define CGU_IDIVC_CTRL_IDIV_Pos                               2                                                         /*!< CGU IDIVC_CTRL: IDIV Position       */
#define CGU_IDIVC_CTRL_IDIV_Msk                               (0x0fUL << CGU_IDIVC_CTRL_IDIV_Pos)                       /*!< CGU IDIVC_CTRL: IDIV Mask           */
#define CGU_IDIVC_CTRL_AUTOBLOCK_Pos                          11                                                        /*!< CGU IDIVC_CTRL: AUTOBLOCK Position  */
#define CGU_IDIVC_CTRL_AUTOBLOCK_Msk                          (0x01UL << CGU_IDIVC_CTRL_AUTOBLOCK_Pos)                  /*!< CGU IDIVC_CTRL: AUTOBLOCK Mask      */
#define CGU_IDIVC_CTRL_CLK_SEL_Pos                            24                                                        /*!< CGU IDIVC_CTRL: CLK_SEL Position    */
#define CGU_IDIVC_CTRL_CLK_SEL_Msk                            (0x1fUL << CGU_IDIVC_CTRL_CLK_SEL_Pos)                    /*!< CGU IDIVC_CTRL: CLK_SEL Mask        */

// -------------------------------------  CGU_IDIVD_CTRL  -----------------------------------------
#define CGU_IDIVD_CTRL_PD_Pos                                 0                                                         /*!< CGU IDIVD_CTRL: PD Position         */
#define CGU_IDIVD_CTRL_PD_Msk                                 (0x01UL << CGU_IDIVD_CTRL_PD_Pos)                         /*!< CGU IDIVD_CTRL: PD Mask             */
#define CGU_IDIVD_CTRL_IDIV_Pos                               2                                                         /*!< CGU IDIVD_CTRL: IDIV Position       */
#define CGU_IDIVD_CTRL_IDIV_Msk                               (0x0fUL << CGU_IDIVD_CTRL_IDIV_Pos)                       /*!< CGU IDIVD_CTRL: IDIV Mask           */
#define CGU_IDIVD_CTRL_AUTOBLOCK_Pos                          11                                                        /*!< CGU IDIVD_CTRL: AUTOBLOCK Position  */
#define CGU_IDIVD_CTRL_AUTOBLOCK_Msk                          (0x01UL << CGU_IDIVD_CTRL_AUTOBLOCK_Pos)                  /*!< CGU IDIVD_CTRL: AUTOBLOCK Mask      */
#define CGU_IDIVD_CTRL_CLK_SEL_Pos                            24                                                        /*!< CGU IDIVD_CTRL: CLK_SEL Position    */
#define CGU_IDIVD_CTRL_CLK_SEL_Msk                            (0x1fUL << CGU_IDIVD_CTRL_CLK_SEL_Pos)                    /*!< CGU IDIVD_CTRL: CLK_SEL Mask        */


// ------------------------------------------------------------------------------------------------
// -----                                 CCU1 Position & Mask                                 -----
// ------------------------------------------------------------------------------------------------


// -----------------------------------------  CCU1_PM  --------------------------------------------
#define CCU1_PM_PD_Pos                                        0                                                         /*!< CCU1 PM: PD Position                */
#define CCU1_PM_PD_Msk                                        (0x01UL << CCU1_PM_PD_Pos)                                /*!< CCU1 PM: PD Mask                    */

// -------------------------------------  CCU1_BASE_STAT  -----------------------------------------
#define CCU1_BASE_STAT_BASE_APB3_CLK_IND_Pos                  0                                                         /*!< CCU1 BASE_STAT: BASE_APB3_CLK_IND Position */
#define CCU1_BASE_STAT_BASE_APB3_CLK_IND_Msk                  (0x01UL << CCU1_BASE_STAT_BASE_APB3_CLK_IND_Pos)          /*!< CCU1 BASE_STAT: BASE_APB3_CLK_IND Mask */
#define CCU1_BASE_STAT_BASE_APB1_CLK_IND_Pos                  1                                                         /*!< CCU1 BASE_STAT: BASE_APB1_CLK_IND Position */
#define CCU1_BASE_STAT_BASE_APB1_CLK_IND_Msk                  (0x01UL << CCU1_BASE_STAT_BASE_APB1_CLK_IND_Pos)          /*!< CCU1 BASE_STAT: BASE_APB1_CLK_IND Mask */
#define CCU1_BASE_STAT_BASE_SPIFI_CLK_IND_Pos                 2                                                         /*!< CCU1 BASE_STAT: BASE_SPIFI_CLK_IND Position */
#define CCU1_BASE_STAT_BASE_SPIFI_CLK_IND_Msk                 (0x01UL << CCU1_BASE_STAT_BASE_SPIFI_CLK_IND_Pos)         /*!< CCU1 BASE_STAT: BASE_SPIFI_CLK_IND Mask */
#define CCU1_BASE_STAT_BASE_M3_CLK_IND_Pos                    3                                                         /*!< CCU1 BASE_STAT: BASE_M3_CLK_IND Position */
#define CCU1_BASE_STAT_BASE_M3_CLK_IND_Msk                    (0x01UL << CCU1_BASE_STAT_BASE_M3_CLK_IND_Pos)            /*!< CCU1 BASE_STAT: BASE_M3_CLK_IND Mask */
#define CCU1_BASE_STAT_BASE_USB0_CLK_IND_Pos                  7                                                         /*!< CCU1 BASE_STAT: BASE_USB0_CLK_IND Position */
#define CCU1_BASE_STAT_BASE_USB0_CLK_IND_Msk                  (0x01UL << CCU1_BASE_STAT_BASE_USB0_CLK_IND_Pos)          /*!< CCU1 BASE_STAT: BASE_USB0_CLK_IND Mask */
#define CCU1_BASE_STAT_BASE_USB1_CLK_IND_Pos                  8                                                         /*!< CCU1 BASE_STAT: BASE_USB1_CLK_IND Position */
#define CCU1_BASE_STAT_BASE_USB1_CLK_IND_Msk                  (0x01UL << CCU1_BASE_STAT_BASE_USB1_CLK_IND_Pos)          /*!< CCU1 BASE_STAT: BASE_USB1_CLK_IND Mask */

// ----------------------------------  CCU1_CLK_APB3_BUS_CFG  -------------------------------------
#define CCU1_CLK_APB3_BUS_CFG_RUN_Pos                         0                                                         /*!< CCU1 CLK_APB3_BUS_CFG: RUN Position */
#define CCU1_CLK_APB3_BUS_CFG_RUN_Msk                         (0x01UL << CCU1_CLK_APB3_BUS_CFG_RUN_Pos)                 /*!< CCU1 CLK_APB3_BUS_CFG: RUN Mask     */
#define CCU1_CLK_APB3_BUS_CFG_AUTO_Pos                        1                                                         /*!< CCU1 CLK_APB3_BUS_CFG: AUTO Position */
#define CCU1_CLK_APB3_BUS_CFG_AUTO_Msk                        (0x01UL << CCU1_CLK_APB3_BUS_CFG_AUTO_Pos)                /*!< CCU1 CLK_APB3_BUS_CFG: AUTO Mask    */
#define CCU1_CLK_APB3_BUS_CFG_WAKEUP_Pos                      2                                                         /*!< CCU1 CLK_APB3_BUS_CFG: WAKEUP Position */
#define CCU1_CLK_APB3_BUS_CFG_WAKEUP_Msk                      (0x01UL << CCU1_CLK_APB3_BUS_CFG_WAKEUP_Pos)              /*!< CCU1 CLK_APB3_BUS_CFG: WAKEUP Mask  */

// ---------------------------------  CCU1_CLK_APB3_BUS_STAT  -------------------------------------
#define CCU1_CLK_APB3_BUS_STAT_RUN_Pos                        0                                                         /*!< CCU1 CLK_APB3_BUS_STAT: RUN Position */
#define CCU1_CLK_APB3_BUS_STAT_RUN_Msk                        (0x01UL << CCU1_CLK_APB3_BUS_STAT_RUN_Pos)                /*!< CCU1 CLK_APB3_BUS_STAT: RUN Mask    */
#define CCU1_CLK_APB3_BUS_STAT_AUTO_Pos                       1                                                         /*!< CCU1 CLK_APB3_BUS_STAT: AUTO Position */
#define CCU1_CLK_APB3_BUS_STAT_AUTO_Msk                       (0x01UL << CCU1_CLK_APB3_BUS_STAT_AUTO_Pos)               /*!< CCU1 CLK_APB3_BUS_STAT: AUTO Mask   */
#define CCU1_CLK_APB3_BUS_STAT_WAKEUP_Pos                     2                                                         /*!< CCU1 CLK_APB3_BUS_STAT: WAKEUP Position */
#define CCU1_CLK_APB3_BUS_STAT_WAKEUP_Msk                     (0x01UL << CCU1_CLK_APB3_BUS_STAT_WAKEUP_Pos)             /*!< CCU1 CLK_APB3_BUS_STAT: WAKEUP Mask */

// ---------------------------------  CCU1_CLK_APB3_I2C1_CFG  -------------------------------------
#define CCU1_CLK_APB3_I2C1_CFG_RUN_Pos                        0                                                         /*!< CCU1 CLK_APB3_I2C1_CFG: RUN Position */
#define CCU1_CLK_APB3_I2C1_CFG_RUN_Msk                        (0x01UL << CCU1_CLK_APB3_I2C1_CFG_RUN_Pos)                /*!< CCU1 CLK_APB3_I2C1_CFG: RUN Mask    */
#define CCU1_CLK_APB3_I2C1_CFG_AUTO_Pos                       1                                                         /*!< CCU1 CLK_APB3_I2C1_CFG: AUTO Position */
#define CCU1_CLK_APB3_I2C1_CFG_AUTO_Msk                       (0x01UL << CCU1_CLK_APB3_I2C1_CFG_AUTO_Pos)               /*!< CCU1 CLK_APB3_I2C1_CFG: AUTO Mask   */
#define CCU1_CLK_APB3_I2C1_CFG_WAKEUP_Pos                     2                                                         /*!< CCU1 CLK_APB3_I2C1_CFG: WAKEUP Position */
#define CCU1_CLK_APB3_I2C1_CFG_WAKEUP_Msk                     (0x01UL << CCU1_CLK_APB3_I2C1_CFG_WAKEUP_Pos)             /*!< CCU1 CLK_APB3_I2C1_CFG: WAKEUP Mask */

// ---------------------------------  CCU1_CLK_APB3_I2C1_STAT  ------------------------------------
#define CCU1_CLK_APB3_I2C1_STAT_RUN_Pos                       0                                                         /*!< CCU1 CLK_APB3_I2C1_STAT: RUN Position */
#define CCU1_CLK_APB3_I2C1_STAT_RUN_Msk                       (0x01UL << CCU1_CLK_APB3_I2C1_STAT_RUN_Pos)               /*!< CCU1 CLK_APB3_I2C1_STAT: RUN Mask   */
#define CCU1_CLK_APB3_I2C1_STAT_AUTO_Pos                      1                                                         /*!< CCU1 CLK_APB3_I2C1_STAT: AUTO Position */
#define CCU1_CLK_APB3_I2C1_STAT_AUTO_Msk                      (0x01UL << CCU1_CLK_APB3_I2C1_STAT_AUTO_Pos)              /*!< CCU1 CLK_APB3_I2C1_STAT: AUTO Mask  */
#define CCU1_CLK_APB3_I2C1_STAT_WAKEUP_Pos                    2                                                         /*!< CCU1 CLK_APB3_I2C1_STAT: WAKEUP Position */
#define CCU1_CLK_APB3_I2C1_STAT_WAKEUP_Msk                    (0x01UL << CCU1_CLK_APB3_I2C1_STAT_WAKEUP_Pos)            /*!< CCU1 CLK_APB3_I2C1_STAT: WAKEUP Mask */

// ----------------------------------  CCU1_CLK_APB3_DAC_CFG  -------------------------------------
#define CCU1_CLK_APB3_DAC_CFG_RUN_Pos                         0                                                         /*!< CCU1 CLK_APB3_DAC_CFG: RUN Position */
#define CCU1_CLK_APB3_DAC_CFG_RUN_Msk                         (0x01UL << CCU1_CLK_APB3_DAC_CFG_RUN_Pos)                 /*!< CCU1 CLK_APB3_DAC_CFG: RUN Mask     */
#define CCU1_CLK_APB3_DAC_CFG_AUTO_Pos                        1                                                         /*!< CCU1 CLK_APB3_DAC_CFG: AUTO Position */
#define CCU1_CLK_APB3_DAC_CFG_AUTO_Msk                        (0x01UL << CCU1_CLK_APB3_DAC_CFG_AUTO_Pos)                /*!< CCU1 CLK_APB3_DAC_CFG: AUTO Mask    */
#define CCU1_CLK_APB3_DAC_CFG_WAKEUP_Pos                      2                                                         /*!< CCU1 CLK_APB3_DAC_CFG: WAKEUP Position */
#define CCU1_CLK_APB3_DAC_CFG_WAKEUP_Msk                      (0x01UL << CCU1_CLK_APB3_DAC_CFG_WAKEUP_Pos)              /*!< CCU1 CLK_APB3_DAC_CFG: WAKEUP Mask  */

// ---------------------------------  CCU1_CLK_APB3_DAC_STAT  -------------------------------------
#define CCU1_CLK_APB3_DAC_STAT_RUN_Pos                        0                                                         /*!< CCU1 CLK_APB3_DAC_STAT: RUN Position */
#define CCU1_CLK_APB3_DAC_STAT_RUN_Msk                        (0x01UL << CCU1_CLK_APB3_DAC_STAT_RUN_Pos)                /*!< CCU1 CLK_APB3_DAC_STAT: RUN Mask    */
#define CCU1_CLK_APB3_DAC_STAT_AUTO_Pos                       1                                                         /*!< CCU1 CLK_APB3_DAC_STAT: AUTO Position */
#define CCU1_CLK_APB3_DAC_STAT_AUTO_Msk                       (0x01UL << CCU1_CLK_APB3_DAC_STAT_AUTO_Pos)               /*!< CCU1 CLK_APB3_DAC_STAT: AUTO Mask   */
#define CCU1_CLK_APB3_DAC_STAT_WAKEUP_Pos                     2                                                         /*!< CCU1 CLK_APB3_DAC_STAT: WAKEUP Position */
#define CCU1_CLK_APB3_DAC_STAT_WAKEUP_Msk                     (0x01UL << CCU1_CLK_APB3_DAC_STAT_WAKEUP_Pos)             /*!< CCU1 CLK_APB3_DAC_STAT: WAKEUP Mask */

// ---------------------------------  CCU1_CLK_APB3_ADC0_CFG  -------------------------------------
#define CCU1_CLK_APB3_ADC0_CFG_RUN_Pos                        0                                                         /*!< CCU1 CLK_APB3_ADC0_CFG: RUN Position */
#define CCU1_CLK_APB3_ADC0_CFG_RUN_Msk                        (0x01UL << CCU1_CLK_APB3_ADC0_CFG_RUN_Pos)                /*!< CCU1 CLK_APB3_ADC0_CFG: RUN Mask    */
#define CCU1_CLK_APB3_ADC0_CFG_AUTO_Pos                       1                                                         /*!< CCU1 CLK_APB3_ADC0_CFG: AUTO Position */
#define CCU1_CLK_APB3_ADC0_CFG_AUTO_Msk                       (0x01UL << CCU1_CLK_APB3_ADC0_CFG_AUTO_Pos)               /*!< CCU1 CLK_APB3_ADC0_CFG: AUTO Mask   */
#define CCU1_CLK_APB3_ADC0_CFG_WAKEUP_Pos                     2                                                         /*!< CCU1 CLK_APB3_ADC0_CFG: WAKEUP Position */
#define CCU1_CLK_APB3_ADC0_CFG_WAKEUP_Msk                     (0x01UL << CCU1_CLK_APB3_ADC0_CFG_WAKEUP_Pos)             /*!< CCU1 CLK_APB3_ADC0_CFG: WAKEUP Mask */

// ---------------------------------  CCU1_CLK_APB3_ADC0_STAT  ------------------------------------
#define CCU1_CLK_APB3_ADC0_STAT_RUN_Pos                       0                                                         /*!< CCU1 CLK_APB3_ADC0_STAT: RUN Position */
#define CCU1_CLK_APB3_ADC0_STAT_RUN_Msk                       (0x01UL << CCU1_CLK_APB3_ADC0_STAT_RUN_Pos)               /*!< CCU1 CLK_APB3_ADC0_STAT: RUN Mask   */
#define CCU1_CLK_APB3_ADC0_STAT_AUTO_Pos                      1                                                         /*!< CCU1 CLK_APB3_ADC0_STAT: AUTO Position */
#define CCU1_CLK_APB3_ADC0_STAT_AUTO_Msk                      (0x01UL << CCU1_CLK_APB3_ADC0_STAT_AUTO_Pos)              /*!< CCU1 CLK_APB3_ADC0_STAT: AUTO Mask  */
#define CCU1_CLK_APB3_ADC0_STAT_WAKEUP_Pos                    2                                                         /*!< CCU1 CLK_APB3_ADC0_STAT: WAKEUP Position */
#define CCU1_CLK_APB3_ADC0_STAT_WAKEUP_Msk                    (0x01UL << CCU1_CLK_APB3_ADC0_STAT_WAKEUP_Pos)            /*!< CCU1 CLK_APB3_ADC0_STAT: WAKEUP Mask */

// ---------------------------------  CCU1_CLK_APB3_ADC1_CFG  -------------------------------------
#define CCU1_CLK_APB3_ADC1_CFG_RUN_Pos                        0                                                         /*!< CCU1 CLK_APB3_ADC1_CFG: RUN Position */
#define CCU1_CLK_APB3_ADC1_CFG_RUN_Msk                        (0x01UL << CCU1_CLK_APB3_ADC1_CFG_RUN_Pos)                /*!< CCU1 CLK_APB3_ADC1_CFG: RUN Mask    */
#define CCU1_CLK_APB3_ADC1_CFG_AUTO_Pos                       1                                                         /*!< CCU1 CLK_APB3_ADC1_CFG: AUTO Position */
#define CCU1_CLK_APB3_ADC1_CFG_AUTO_Msk                       (0x01UL << CCU1_CLK_APB3_ADC1_CFG_AUTO_Pos)               /*!< CCU1 CLK_APB3_ADC1_CFG: AUTO Mask   */
#define CCU1_CLK_APB3_ADC1_CFG_WAKEUP_Pos                     2                                                         /*!< CCU1 CLK_APB3_ADC1_CFG: WAKEUP Position */
#define CCU1_CLK_APB3_ADC1_CFG_WAKEUP_Msk                     (0x01UL << CCU1_CLK_APB3_ADC1_CFG_WAKEUP_Pos)             /*!< CCU1 CLK_APB3_ADC1_CFG: WAKEUP Mask */

// ---------------------------------  CCU1_CLK_APB3_ADC1_STAT  ------------------------------------
#define CCU1_CLK_APB3_ADC1_STAT_RUN_Pos                       0                                                         /*!< CCU1 CLK_APB3_ADC1_STAT: RUN Position */
#define CCU1_CLK_APB3_ADC1_STAT_RUN_Msk                       (0x01UL << CCU1_CLK_APB3_ADC1_STAT_RUN_Pos)               /*!< CCU1 CLK_APB3_ADC1_STAT: RUN Mask   */
#define CCU1_CLK_APB3_ADC1_STAT_AUTO_Pos                      1                                                         /*!< CCU1 CLK_APB3_ADC1_STAT: AUTO Position */
#define CCU1_CLK_APB3_ADC1_STAT_AUTO_Msk                      (0x01UL << CCU1_CLK_APB3_ADC1_STAT_AUTO_Pos)              /*!< CCU1 CLK_APB3_ADC1_STAT: AUTO Mask  */
#define CCU1_CLK_APB3_ADC1_STAT_WAKEUP_Pos                    2                                                         /*!< CCU1 CLK_APB3_ADC1_STAT: WAKEUP Position */
#define CCU1_CLK_APB3_ADC1_STAT_WAKEUP_Msk                    (0x01UL << CCU1_CLK_APB3_ADC1_STAT_WAKEUP_Pos)            /*!< CCU1 CLK_APB3_ADC1_STAT: WAKEUP Mask */

// ---------------------------------  CCU1_CLK_APB3_CAN0_CFG  -------------------------------------
#define CCU1_CLK_APB3_CAN0_CFG_RUN_Pos                        0                                                         /*!< CCU1 CLK_APB3_CAN0_CFG: RUN Position */
#define CCU1_CLK_APB3_CAN0_CFG_RUN_Msk                        (0x01UL << CCU1_CLK_APB3_CAN0_CFG_RUN_Pos)                /*!< CCU1 CLK_APB3_CAN0_CFG: RUN Mask    */
#define CCU1_CLK_APB3_CAN0_CFG_AUTO_Pos                       1                                                         /*!< CCU1 CLK_APB3_CAN0_CFG: AUTO Position */
#define CCU1_CLK_APB3_CAN0_CFG_AUTO_Msk                       (0x01UL << CCU1_CLK_APB3_CAN0_CFG_AUTO_Pos)               /*!< CCU1 CLK_APB3_CAN0_CFG: AUTO Mask   */
#define CCU1_CLK_APB3_CAN0_CFG_WAKEUP_Pos                     2                                                         /*!< CCU1 CLK_APB3_CAN0_CFG: WAKEUP Position */
#define CCU1_CLK_APB3_CAN0_CFG_WAKEUP_Msk                     (0x01UL << CCU1_CLK_APB3_CAN0_CFG_WAKEUP_Pos)             /*!< CCU1 CLK_APB3_CAN0_CFG: WAKEUP Mask */

// ---------------------------------  CCU1_CLK_APB3_CAN0_STAT  ------------------------------------
#define CCU1_CLK_APB3_CAN0_STAT_RUN_Pos                       0                                                         /*!< CCU1 CLK_APB3_CAN0_STAT: RUN Position */
#define CCU1_CLK_APB3_CAN0_STAT_RUN_Msk                       (0x01UL << CCU1_CLK_APB3_CAN0_STAT_RUN_Pos)               /*!< CCU1 CLK_APB3_CAN0_STAT: RUN Mask   */
#define CCU1_CLK_APB3_CAN0_STAT_AUTO_Pos                      1                                                         /*!< CCU1 CLK_APB3_CAN0_STAT: AUTO Position */
#define CCU1_CLK_APB3_CAN0_STAT_AUTO_Msk                      (0x01UL << CCU1_CLK_APB3_CAN0_STAT_AUTO_Pos)              /*!< CCU1 CLK_APB3_CAN0_STAT: AUTO Mask  */
#define CCU1_CLK_APB3_CAN0_STAT_WAKEUP_Pos                    2                                                         /*!< CCU1 CLK_APB3_CAN0_STAT: WAKEUP Position */
#define CCU1_CLK_APB3_CAN0_STAT_WAKEUP_Msk                    (0x01UL << CCU1_CLK_APB3_CAN0_STAT_WAKEUP_Pos)            /*!< CCU1 CLK_APB3_CAN0_STAT: WAKEUP Mask */

// ----------------------------------  CCU1_CLK_APB1_BUS_CFG  -------------------------------------
#define CCU1_CLK_APB1_BUS_CFG_RUN_Pos                         0                                                         /*!< CCU1 CLK_APB1_BUS_CFG: RUN Position */
#define CCU1_CLK_APB1_BUS_CFG_RUN_Msk                         (0x01UL << CCU1_CLK_APB1_BUS_CFG_RUN_Pos)                 /*!< CCU1 CLK_APB1_BUS_CFG: RUN Mask     */
#define CCU1_CLK_APB1_BUS_CFG_AUTO_Pos                        1                                                         /*!< CCU1 CLK_APB1_BUS_CFG: AUTO Position */
#define CCU1_CLK_APB1_BUS_CFG_AUTO_Msk                        (0x01UL << CCU1_CLK_APB1_BUS_CFG_AUTO_Pos)                /*!< CCU1 CLK_APB1_BUS_CFG: AUTO Mask    */
#define CCU1_CLK_APB1_BUS_CFG_WAKEUP_Pos                      2                                                         /*!< CCU1 CLK_APB1_BUS_CFG: WAKEUP Position */
#define CCU1_CLK_APB1_BUS_CFG_WAKEUP_Msk                      (0x01UL << CCU1_CLK_APB1_BUS_CFG_WAKEUP_Pos)              /*!< CCU1 CLK_APB1_BUS_CFG: WAKEUP Mask  */

// ---------------------------------  CCU1_CLK_APB1_BUS_STAT  -------------------------------------
#define CCU1_CLK_APB1_BUS_STAT_RUN_Pos                        0                                                         /*!< CCU1 CLK_APB1_BUS_STAT: RUN Position */
#define CCU1_CLK_APB1_BUS_STAT_RUN_Msk                        (0x01UL << CCU1_CLK_APB1_BUS_STAT_RUN_Pos)                /*!< CCU1 CLK_APB1_BUS_STAT: RUN Mask    */
#define CCU1_CLK_APB1_BUS_STAT_AUTO_Pos                       1                                                         /*!< CCU1 CLK_APB1_BUS_STAT: AUTO Position */
#define CCU1_CLK_APB1_BUS_STAT_AUTO_Msk                       (0x01UL << CCU1_CLK_APB1_BUS_STAT_AUTO_Pos)               /*!< CCU1 CLK_APB1_BUS_STAT: AUTO Mask   */
#define CCU1_CLK_APB1_BUS_STAT_WAKEUP_Pos                     2                                                         /*!< CCU1 CLK_APB1_BUS_STAT: WAKEUP Position */
#define CCU1_CLK_APB1_BUS_STAT_WAKEUP_Msk                     (0x01UL << CCU1_CLK_APB1_BUS_STAT_WAKEUP_Pos)             /*!< CCU1 CLK_APB1_BUS_STAT: WAKEUP Mask */

// ------------------------------  CCU1_CLK_APB1_MOTOCONPWM_CFG  ----------------------------------
#define CCU1_CLK_APB1_MOTOCONPWM_CFG_RUN_Pos                  0                                                         /*!< CCU1 CLK_APB1_MOTOCONPWM_CFG: RUN Position */
#define CCU1_CLK_APB1_MOTOCONPWM_CFG_RUN_Msk                  (0x01UL << CCU1_CLK_APB1_MOTOCONPWM_CFG_RUN_Pos)          /*!< CCU1 CLK_APB1_MOTOCONPWM_CFG: RUN Mask */
#define CCU1_CLK_APB1_MOTOCONPWM_CFG_AUTO_Pos                 1                                                         /*!< CCU1 CLK_APB1_MOTOCONPWM_CFG: AUTO Position */
#define CCU1_CLK_APB1_MOTOCONPWM_CFG_AUTO_Msk                 (0x01UL << CCU1_CLK_APB1_MOTOCONPWM_CFG_AUTO_Pos)         /*!< CCU1 CLK_APB1_MOTOCONPWM_CFG: AUTO Mask */
#define CCU1_CLK_APB1_MOTOCONPWM_CFG_WAKEUP_Pos               2                                                         /*!< CCU1 CLK_APB1_MOTOCONPWM_CFG: WAKEUP Position */
#define CCU1_CLK_APB1_MOTOCONPWM_CFG_WAKEUP_Msk               (0x01UL << CCU1_CLK_APB1_MOTOCONPWM_CFG_WAKEUP_Pos)       /*!< CCU1 CLK_APB1_MOTOCONPWM_CFG: WAKEUP Mask */

// ------------------------------  CCU1_CLK_APB1_MOTOCONPWM_STAT  ---------------------------------
#define CCU1_CLK_APB1_MOTOCONPWM_STAT_RUN_Pos                 0                                                         /*!< CCU1 CLK_APB1_MOTOCONPWM_STAT: RUN Position */
#define CCU1_CLK_APB1_MOTOCONPWM_STAT_RUN_Msk                 (0x01UL << CCU1_CLK_APB1_MOTOCONPWM_STAT_RUN_Pos)         /*!< CCU1 CLK_APB1_MOTOCONPWM_STAT: RUN Mask */
#define CCU1_CLK_APB1_MOTOCONPWM_STAT_AUTO_Pos                1                                                         /*!< CCU1 CLK_APB1_MOTOCONPWM_STAT: AUTO Position */
#define CCU1_CLK_APB1_MOTOCONPWM_STAT_AUTO_Msk                (0x01UL << CCU1_CLK_APB1_MOTOCONPWM_STAT_AUTO_Pos)        /*!< CCU1 CLK_APB1_MOTOCONPWM_STAT: AUTO Mask */
#define CCU1_CLK_APB1_MOTOCONPWM_STAT_WAKEUP_Pos              2                                                         /*!< CCU1 CLK_APB1_MOTOCONPWM_STAT: WAKEUP Position */
#define CCU1_CLK_APB1_MOTOCONPWM_STAT_WAKEUP_Msk              (0x01UL << CCU1_CLK_APB1_MOTOCONPWM_STAT_WAKEUP_Pos)      /*!< CCU1 CLK_APB1_MOTOCONPWM_STAT: WAKEUP Mask */

// ---------------------------------  CCU1_CLK_ABP1_I2C0_CFG  -------------------------------------
#define CCU1_CLK_ABP1_I2C0_CFG_RUN_Pos                        0                                                         /*!< CCU1 CLK_ABP1_I2C0_CFG: RUN Position */
#define CCU1_CLK_ABP1_I2C0_CFG_RUN_Msk                        (0x01UL << CCU1_CLK_ABP1_I2C0_CFG_RUN_Pos)                /*!< CCU1 CLK_ABP1_I2C0_CFG: RUN Mask    */
#define CCU1_CLK_ABP1_I2C0_CFG_AUTO_Pos                       1                                                         /*!< CCU1 CLK_ABP1_I2C0_CFG: AUTO Position */
#define CCU1_CLK_ABP1_I2C0_CFG_AUTO_Msk                       (0x01UL << CCU1_CLK_ABP1_I2C0_CFG_AUTO_Pos)               /*!< CCU1 CLK_ABP1_I2C0_CFG: AUTO Mask   */
#define CCU1_CLK_ABP1_I2C0_CFG_WAKEUP_Pos                     2                                                         /*!< CCU1 CLK_ABP1_I2C0_CFG: WAKEUP Position */
#define CCU1_CLK_ABP1_I2C0_CFG_WAKEUP_Msk                     (0x01UL << CCU1_CLK_ABP1_I2C0_CFG_WAKEUP_Pos)             /*!< CCU1 CLK_ABP1_I2C0_CFG: WAKEUP Mask */

// ---------------------------------  CCU1_CLK_APB1_I2C0_STAT  ------------------------------------
#define CCU1_CLK_APB1_I2C0_STAT_RUN_Pos                       0                                                         /*!< CCU1 CLK_APB1_I2C0_STAT: RUN Position */
#define CCU1_CLK_APB1_I2C0_STAT_RUN_Msk                       (0x01UL << CCU1_CLK_APB1_I2C0_STAT_RUN_Pos)               /*!< CCU1 CLK_APB1_I2C0_STAT: RUN Mask   */
#define CCU1_CLK_APB1_I2C0_STAT_AUTO_Pos                      1                                                         /*!< CCU1 CLK_APB1_I2C0_STAT: AUTO Position */
#define CCU1_CLK_APB1_I2C0_STAT_AUTO_Msk                      (0x01UL << CCU1_CLK_APB1_I2C0_STAT_AUTO_Pos)              /*!< CCU1 CLK_APB1_I2C0_STAT: AUTO Mask  */
#define CCU1_CLK_APB1_I2C0_STAT_WAKEUP_Pos                    2                                                         /*!< CCU1 CLK_APB1_I2C0_STAT: WAKEUP Position */
#define CCU1_CLK_APB1_I2C0_STAT_WAKEUP_Msk                    (0x01UL << CCU1_CLK_APB1_I2C0_STAT_WAKEUP_Pos)            /*!< CCU1 CLK_APB1_I2C0_STAT: WAKEUP Mask */

// ----------------------------------  CCU1_CLK_APB1_I2S_CFG  -------------------------------------
#define CCU1_CLK_APB1_I2S_CFG_RUN_Pos                         0                                                         /*!< CCU1 CLK_APB1_I2S_CFG: RUN Position */
#define CCU1_CLK_APB1_I2S_CFG_RUN_Msk                         (0x01UL << CCU1_CLK_APB1_I2S_CFG_RUN_Pos)                 /*!< CCU1 CLK_APB1_I2S_CFG: RUN Mask     */
#define CCU1_CLK_APB1_I2S_CFG_AUTO_Pos                        1                                                         /*!< CCU1 CLK_APB1_I2S_CFG: AUTO Position */
#define CCU1_CLK_APB1_I2S_CFG_AUTO_Msk                        (0x01UL << CCU1_CLK_APB1_I2S_CFG_AUTO_Pos)                /*!< CCU1 CLK_APB1_I2S_CFG: AUTO Mask    */
#define CCU1_CLK_APB1_I2S_CFG_WAKEUP_Pos                      2                                                         /*!< CCU1 CLK_APB1_I2S_CFG: WAKEUP Position */
#define CCU1_CLK_APB1_I2S_CFG_WAKEUP_Msk                      (0x01UL << CCU1_CLK_APB1_I2S_CFG_WAKEUP_Pos)              /*!< CCU1 CLK_APB1_I2S_CFG: WAKEUP Mask  */

// ---------------------------------  CCU1_CLK_APB1_I2S_STAT  -------------------------------------
#define CCU1_CLK_APB1_I2S_STAT_RUN_Pos                        0                                                         /*!< CCU1 CLK_APB1_I2S_STAT: RUN Position */
#define CCU1_CLK_APB1_I2S_STAT_RUN_Msk                        (0x01UL << CCU1_CLK_APB1_I2S_STAT_RUN_Pos)                /*!< CCU1 CLK_APB1_I2S_STAT: RUN Mask    */
#define CCU1_CLK_APB1_I2S_STAT_AUTO_Pos                       1                                                         /*!< CCU1 CLK_APB1_I2S_STAT: AUTO Position */
#define CCU1_CLK_APB1_I2S_STAT_AUTO_Msk                       (0x01UL << CCU1_CLK_APB1_I2S_STAT_AUTO_Pos)               /*!< CCU1 CLK_APB1_I2S_STAT: AUTO Mask   */
#define CCU1_CLK_APB1_I2S_STAT_WAKEUP_Pos                     2                                                         /*!< CCU1 CLK_APB1_I2S_STAT: WAKEUP Position */
#define CCU1_CLK_APB1_I2S_STAT_WAKEUP_Msk                     (0x01UL << CCU1_CLK_APB1_I2S_STAT_WAKEUP_Pos)             /*!< CCU1 CLK_APB1_I2S_STAT: WAKEUP Mask */

// ---------------------------------  CCU1_CLK_APB1_CAN1_CFG  -------------------------------------
#define CCU1_CLK_APB1_CAN1_CFG_RUN_Pos                        0                                                         /*!< CCU1 CLK_APB1_CAN1_CFG: RUN Position */
#define CCU1_CLK_APB1_CAN1_CFG_RUN_Msk                        (0x01UL << CCU1_CLK_APB1_CAN1_CFG_RUN_Pos)                /*!< CCU1 CLK_APB1_CAN1_CFG: RUN Mask    */
#define CCU1_CLK_APB1_CAN1_CFG_AUTO_Pos                       1                                                         /*!< CCU1 CLK_APB1_CAN1_CFG: AUTO Position */
#define CCU1_CLK_APB1_CAN1_CFG_AUTO_Msk                       (0x01UL << CCU1_CLK_APB1_CAN1_CFG_AUTO_Pos)               /*!< CCU1 CLK_APB1_CAN1_CFG: AUTO Mask   */
#define CCU1_CLK_APB1_CAN1_CFG_WAKEUP_Pos                     2                                                         /*!< CCU1 CLK_APB1_CAN1_CFG: WAKEUP Position */
#define CCU1_CLK_APB1_CAN1_CFG_WAKEUP_Msk                     (0x01UL << CCU1_CLK_APB1_CAN1_CFG_WAKEUP_Pos)             /*!< CCU1 CLK_APB1_CAN1_CFG: WAKEUP Mask */

// ---------------------------------  CCU1_CLK_APB1_CAN1_STAT  ------------------------------------
#define CCU1_CLK_APB1_CAN1_STAT_RUN_Pos                       0                                                         /*!< CCU1 CLK_APB1_CAN1_STAT: RUN Position */
#define CCU1_CLK_APB1_CAN1_STAT_RUN_Msk                       (0x01UL << CCU1_CLK_APB1_CAN1_STAT_RUN_Pos)               /*!< CCU1 CLK_APB1_CAN1_STAT: RUN Mask   */
#define CCU1_CLK_APB1_CAN1_STAT_AUTO_Pos                      1                                                         /*!< CCU1 CLK_APB1_CAN1_STAT: AUTO Position */
#define CCU1_CLK_APB1_CAN1_STAT_AUTO_Msk                      (0x01UL << CCU1_CLK_APB1_CAN1_STAT_AUTO_Pos)              /*!< CCU1 CLK_APB1_CAN1_STAT: AUTO Mask  */
#define CCU1_CLK_APB1_CAN1_STAT_WAKEUP_Pos                    2                                                         /*!< CCU1 CLK_APB1_CAN1_STAT: WAKEUP Position */
#define CCU1_CLK_APB1_CAN1_STAT_WAKEUP_Msk                    (0x01UL << CCU1_CLK_APB1_CAN1_STAT_WAKEUP_Pos)            /*!< CCU1 CLK_APB1_CAN1_STAT: WAKEUP Mask */

// -----------------------------------  CCU1_CLK_SPIFI_CFG  ---------------------------------------
#define CCU1_CLK_SPIFI_CFG_RUN_Pos                            0                                                         /*!< CCU1 CLK_SPIFI_CFG: RUN Position    */
#define CCU1_CLK_SPIFI_CFG_RUN_Msk                            (0x01UL << CCU1_CLK_SPIFI_CFG_RUN_Pos)                    /*!< CCU1 CLK_SPIFI_CFG: RUN Mask        */
#define CCU1_CLK_SPIFI_CFG_AUTO_Pos                           1                                                         /*!< CCU1 CLK_SPIFI_CFG: AUTO Position   */
#define CCU1_CLK_SPIFI_CFG_AUTO_Msk                           (0x01UL << CCU1_CLK_SPIFI_CFG_AUTO_Pos)                   /*!< CCU1 CLK_SPIFI_CFG: AUTO Mask       */
#define CCU1_CLK_SPIFI_CFG_WAKEUP_Pos                         2                                                         /*!< CCU1 CLK_SPIFI_CFG: WAKEUP Position */
#define CCU1_CLK_SPIFI_CFG_WAKEUP_Msk                         (0x01UL << CCU1_CLK_SPIFI_CFG_WAKEUP_Pos)                 /*!< CCU1 CLK_SPIFI_CFG: WAKEUP Mask     */

// -----------------------------------  CCU1_CLK_SPIFI_STAT  --------------------------------------
#define CCU1_CLK_SPIFI_STAT_RUN_Pos                           0                                                         /*!< CCU1 CLK_SPIFI_STAT: RUN Position   */
#define CCU1_CLK_SPIFI_STAT_RUN_Msk                           (0x01UL << CCU1_CLK_SPIFI_STAT_RUN_Pos)                   /*!< CCU1 CLK_SPIFI_STAT: RUN Mask       */
#define CCU1_CLK_SPIFI_STAT_AUTO_Pos                          1                                                         /*!< CCU1 CLK_SPIFI_STAT: AUTO Position  */
#define CCU1_CLK_SPIFI_STAT_AUTO_Msk                          (0x01UL << CCU1_CLK_SPIFI_STAT_AUTO_Pos)                  /*!< CCU1 CLK_SPIFI_STAT: AUTO Mask      */
#define CCU1_CLK_SPIFI_STAT_WAKEUP_Pos                        2                                                         /*!< CCU1 CLK_SPIFI_STAT: WAKEUP Position */
#define CCU1_CLK_SPIFI_STAT_WAKEUP_Msk                        (0x01UL << CCU1_CLK_SPIFI_STAT_WAKEUP_Pos)                /*!< CCU1 CLK_SPIFI_STAT: WAKEUP Mask    */

// -----------------------------------  CCU1_CLK_M4_BUS_CFG  --------------------------------------
#define CCU1_CLK_M4_BUS_CFG_RUN_Pos                           0                                                         /*!< CCU1 CLK_M4_BUS_CFG: RUN Position   */
#define CCU1_CLK_M4_BUS_CFG_RUN_Msk                           (0x01UL << CCU1_CLK_M4_BUS_CFG_RUN_Pos)                   /*!< CCU1 CLK_M4_BUS_CFG: RUN Mask       */
#define CCU1_CLK_M4_BUS_CFG_AUTO_Pos                          1                                                         /*!< CCU1 CLK_M4_BUS_CFG: AUTO Position  */
#define CCU1_CLK_M4_BUS_CFG_AUTO_Msk                          (0x01UL << CCU1_CLK_M4_BUS_CFG_AUTO_Pos)                  /*!< CCU1 CLK_M4_BUS_CFG: AUTO Mask      */
#define CCU1_CLK_M4_BUS_CFG_WAKEUP_Pos                        2                                                         /*!< CCU1 CLK_M4_BUS_CFG: WAKEUP Position */
#define CCU1_CLK_M4_BUS_CFG_WAKEUP_Msk                        (0x01UL << CCU1_CLK_M4_BUS_CFG_WAKEUP_Pos)                /*!< CCU1 CLK_M4_BUS_CFG: WAKEUP Mask    */

// ----------------------------------  CCU1_CLK_M4_BUS_STAT  --------------------------------------
#define CCU1_CLK_M4_BUS_STAT_RUN_Pos                          0                                                         /*!< CCU1 CLK_M4_BUS_STAT: RUN Position  */
#define CCU1_CLK_M4_BUS_STAT_RUN_Msk                          (0x01UL << CCU1_CLK_M4_BUS_STAT_RUN_Pos)                  /*!< CCU1 CLK_M4_BUS_STAT: RUN Mask      */
#define CCU1_CLK_M4_BUS_STAT_AUTO_Pos                         1                                                         /*!< CCU1 CLK_M4_BUS_STAT: AUTO Position */
#define CCU1_CLK_M4_BUS_STAT_AUTO_Msk                         (0x01UL << CCU1_CLK_M4_BUS_STAT_AUTO_Pos)                 /*!< CCU1 CLK_M4_BUS_STAT: AUTO Mask     */
#define CCU1_CLK_M4_BUS_STAT_WAKEUP_Pos                       2                                                         /*!< CCU1 CLK_M4_BUS_STAT: WAKEUP Position */
#define CCU1_CLK_M4_BUS_STAT_WAKEUP_Msk                       (0x01UL << CCU1_CLK_M4_BUS_STAT_WAKEUP_Pos)               /*!< CCU1 CLK_M4_BUS_STAT: WAKEUP Mask   */

// ----------------------------------  CCU1_CLK_M4_SPIFI_CFG  -------------------------------------
#define CCU1_CLK_M4_SPIFI_CFG_RUN_Pos                         0                                                         /*!< CCU1 CLK_M4_SPIFI_CFG: RUN Position */
#define CCU1_CLK_M4_SPIFI_CFG_RUN_Msk                         (0x01UL << CCU1_CLK_M4_SPIFI_CFG_RUN_Pos)                 /*!< CCU1 CLK_M4_SPIFI_CFG: RUN Mask     */
#define CCU1_CLK_M4_SPIFI_CFG_AUTO_Pos                        1                                                         /*!< CCU1 CLK_M4_SPIFI_CFG: AUTO Position */
#define CCU1_CLK_M4_SPIFI_CFG_AUTO_Msk                        (0x01UL << CCU1_CLK_M4_SPIFI_CFG_AUTO_Pos)                /*!< CCU1 CLK_M4_SPIFI_CFG: AUTO Mask    */
#define CCU1_CLK_M4_SPIFI_CFG_WAKEUP_Pos                      2                                                         /*!< CCU1 CLK_M4_SPIFI_CFG: WAKEUP Position */
#define CCU1_CLK_M4_SPIFI_CFG_WAKEUP_Msk                      (0x01UL << CCU1_CLK_M4_SPIFI_CFG_WAKEUP_Pos)              /*!< CCU1 CLK_M4_SPIFI_CFG: WAKEUP Mask  */

// ---------------------------------  CCU1_CLK_M4_SPIFI_STAT  -------------------------------------
#define CCU1_CLK_M4_SPIFI_STAT_RUN_Pos                        0                                                         /*!< CCU1 CLK_M4_SPIFI_STAT: RUN Position */
#define CCU1_CLK_M4_SPIFI_STAT_RUN_Msk                        (0x01UL << CCU1_CLK_M4_SPIFI_STAT_RUN_Pos)                /*!< CCU1 CLK_M4_SPIFI_STAT: RUN Mask    */
#define CCU1_CLK_M4_SPIFI_STAT_AUTO_Pos                       1                                                         /*!< CCU1 CLK_M4_SPIFI_STAT: AUTO Position */
#define CCU1_CLK_M4_SPIFI_STAT_AUTO_Msk                       (0x01UL << CCU1_CLK_M4_SPIFI_STAT_AUTO_Pos)               /*!< CCU1 CLK_M4_SPIFI_STAT: AUTO Mask   */
#define CCU1_CLK_M4_SPIFI_STAT_WAKEUP_Pos                     2                                                         /*!< CCU1 CLK_M4_SPIFI_STAT: WAKEUP Position */
#define CCU1_CLK_M4_SPIFI_STAT_WAKEUP_Msk                     (0x01UL << CCU1_CLK_M4_SPIFI_STAT_WAKEUP_Pos)             /*!< CCU1 CLK_M4_SPIFI_STAT: WAKEUP Mask */

// ----------------------------------  CCU1_CLK_M4_GPIO_CFG  --------------------------------------
#define CCU1_CLK_M4_GPIO_CFG_RUN_Pos                          0                                                         /*!< CCU1 CLK_M4_GPIO_CFG: RUN Position  */
#define CCU1_CLK_M4_GPIO_CFG_RUN_Msk                          (0x01UL << CCU1_CLK_M4_GPIO_CFG_RUN_Pos)                  /*!< CCU1 CLK_M4_GPIO_CFG: RUN Mask      */
#define CCU1_CLK_M4_GPIO_CFG_AUTO_Pos                         1                                                         /*!< CCU1 CLK_M4_GPIO_CFG: AUTO Position */
#define CCU1_CLK_M4_GPIO_CFG_AUTO_Msk                         (0x01UL << CCU1_CLK_M4_GPIO_CFG_AUTO_Pos)                 /*!< CCU1 CLK_M4_GPIO_CFG: AUTO Mask     */
#define CCU1_CLK_M4_GPIO_CFG_WAKEUP_Pos                       2                                                         /*!< CCU1 CLK_M4_GPIO_CFG: WAKEUP Position */
#define CCU1_CLK_M4_GPIO_CFG_WAKEUP_Msk                       (0x01UL << CCU1_CLK_M4_GPIO_CFG_WAKEUP_Pos)               /*!< CCU1 CLK_M4_GPIO_CFG: WAKEUP Mask   */

// ----------------------------------  CCU1_CLK_M4_GPIO_STAT  -------------------------------------
#define CCU1_CLK_M4_GPIO_STAT_RUN_Pos                         0                                                         /*!< CCU1 CLK_M4_GPIO_STAT: RUN Position */
#define CCU1_CLK_M4_GPIO_STAT_RUN_Msk                         (0x01UL << CCU1_CLK_M4_GPIO_STAT_RUN_Pos)                 /*!< CCU1 CLK_M4_GPIO_STAT: RUN Mask     */
#define CCU1_CLK_M4_GPIO_STAT_AUTO_Pos                        1                                                         /*!< CCU1 CLK_M4_GPIO_STAT: AUTO Position */
#define CCU1_CLK_M4_GPIO_STAT_AUTO_Msk                        (0x01UL << CCU1_CLK_M4_GPIO_STAT_AUTO_Pos)                /*!< CCU1 CLK_M4_GPIO_STAT: AUTO Mask    */
#define CCU1_CLK_M4_GPIO_STAT_WAKEUP_Pos                      2                                                         /*!< CCU1 CLK_M4_GPIO_STAT: WAKEUP Position */
#define CCU1_CLK_M4_GPIO_STAT_WAKEUP_Msk                      (0x01UL << CCU1_CLK_M4_GPIO_STAT_WAKEUP_Pos)              /*!< CCU1 CLK_M4_GPIO_STAT: WAKEUP Mask  */

// -----------------------------------  CCU1_CLK_M4_LCD_CFG  --------------------------------------
#define CCU1_CLK_M4_LCD_CFG_RUN_Pos                           0                                                         /*!< CCU1 CLK_M4_LCD_CFG: RUN Position   */
#define CCU1_CLK_M4_LCD_CFG_RUN_Msk                           (0x01UL << CCU1_CLK_M4_LCD_CFG_RUN_Pos)                   /*!< CCU1 CLK_M4_LCD_CFG: RUN Mask       */
#define CCU1_CLK_M4_LCD_CFG_AUTO_Pos                          1                                                         /*!< CCU1 CLK_M4_LCD_CFG: AUTO Position  */
#define CCU1_CLK_M4_LCD_CFG_AUTO_Msk                          (0x01UL << CCU1_CLK_M4_LCD_CFG_AUTO_Pos)                  /*!< CCU1 CLK_M4_LCD_CFG: AUTO Mask      */
#define CCU1_CLK_M4_LCD_CFG_WAKEUP_Pos                        2                                                         /*!< CCU1 CLK_M4_LCD_CFG: WAKEUP Position */
#define CCU1_CLK_M4_LCD_CFG_WAKEUP_Msk                        (0x01UL << CCU1_CLK_M4_LCD_CFG_WAKEUP_Pos)                /*!< CCU1 CLK_M4_LCD_CFG: WAKEUP Mask    */

// ----------------------------------  CCU1_CLK_M4_LCD_STAT  --------------------------------------
#define CCU1_CLK_M4_LCD_STAT_RUN_Pos                          0                                                         /*!< CCU1 CLK_M4_LCD_STAT: RUN Position  */
#define CCU1_CLK_M4_LCD_STAT_RUN_Msk                          (0x01UL << CCU1_CLK_M4_LCD_STAT_RUN_Pos)                  /*!< CCU1 CLK_M4_LCD_STAT: RUN Mask      */
#define CCU1_CLK_M4_LCD_STAT_AUTO_Pos                         1                                                         /*!< CCU1 CLK_M4_LCD_STAT: AUTO Position */
#define CCU1_CLK_M4_LCD_STAT_AUTO_Msk                         (0x01UL << CCU1_CLK_M4_LCD_STAT_AUTO_Pos)                 /*!< CCU1 CLK_M4_LCD_STAT: AUTO Mask     */
#define CCU1_CLK_M4_LCD_STAT_WAKEUP_Pos                       2                                                         /*!< CCU1 CLK_M4_LCD_STAT: WAKEUP Position */
#define CCU1_CLK_M4_LCD_STAT_WAKEUP_Msk                       (0x01UL << CCU1_CLK_M4_LCD_STAT_WAKEUP_Pos)               /*!< CCU1 CLK_M4_LCD_STAT: WAKEUP Mask   */

// --------------------------------  CCU1_CLK_M4_ETHERNET_CFG  ------------------------------------
#define CCU1_CLK_M4_ETHERNET_CFG_RUN_Pos                      0                                                         /*!< CCU1 CLK_M4_ETHERNET_CFG: RUN Position */
#define CCU1_CLK_M4_ETHERNET_CFG_RUN_Msk                      (0x01UL << CCU1_CLK_M4_ETHERNET_CFG_RUN_Pos)              /*!< CCU1 CLK_M4_ETHERNET_CFG: RUN Mask  */
#define CCU1_CLK_M4_ETHERNET_CFG_AUTO_Pos                     1                                                         /*!< CCU1 CLK_M4_ETHERNET_CFG: AUTO Position */
#define CCU1_CLK_M4_ETHERNET_CFG_AUTO_Msk                     (0x01UL << CCU1_CLK_M4_ETHERNET_CFG_AUTO_Pos)             /*!< CCU1 CLK_M4_ETHERNET_CFG: AUTO Mask */
#define CCU1_CLK_M4_ETHERNET_CFG_WAKEUP_Pos                   2                                                         /*!< CCU1 CLK_M4_ETHERNET_CFG: WAKEUP Position */
#define CCU1_CLK_M4_ETHERNET_CFG_WAKEUP_Msk                   (0x01UL << CCU1_CLK_M4_ETHERNET_CFG_WAKEUP_Pos)           /*!< CCU1 CLK_M4_ETHERNET_CFG: WAKEUP Mask */

// --------------------------------  CCU1_CLK_M4_ETHERNET_STAT  -----------------------------------
#define CCU1_CLK_M4_ETHERNET_STAT_RUN_Pos                     0                                                         /*!< CCU1 CLK_M4_ETHERNET_STAT: RUN Position */
#define CCU1_CLK_M4_ETHERNET_STAT_RUN_Msk                     (0x01UL << CCU1_CLK_M4_ETHERNET_STAT_RUN_Pos)             /*!< CCU1 CLK_M4_ETHERNET_STAT: RUN Mask */
#define CCU1_CLK_M4_ETHERNET_STAT_AUTO_Pos                    1                                                         /*!< CCU1 CLK_M4_ETHERNET_STAT: AUTO Position */
#define CCU1_CLK_M4_ETHERNET_STAT_AUTO_Msk                    (0x01UL << CCU1_CLK_M4_ETHERNET_STAT_AUTO_Pos)            /*!< CCU1 CLK_M4_ETHERNET_STAT: AUTO Mask */
#define CCU1_CLK_M4_ETHERNET_STAT_WAKEUP_Pos                  2                                                         /*!< CCU1 CLK_M4_ETHERNET_STAT: WAKEUP Position */
#define CCU1_CLK_M4_ETHERNET_STAT_WAKEUP_Msk                  (0x01UL << CCU1_CLK_M4_ETHERNET_STAT_WAKEUP_Pos)          /*!< CCU1 CLK_M4_ETHERNET_STAT: WAKEUP Mask */

// ----------------------------------  CCU1_CLK_M4_USB0_CFG  --------------------------------------
#define CCU1_CLK_M4_USB0_CFG_RUN_Pos                          0                                                         /*!< CCU1 CLK_M4_USB0_CFG: RUN Position  */
#define CCU1_CLK_M4_USB0_CFG_RUN_Msk                          (0x01UL << CCU1_CLK_M4_USB0_CFG_RUN_Pos)                  /*!< CCU1 CLK_M4_USB0_CFG: RUN Mask      */
#define CCU1_CLK_M4_USB0_CFG_AUTO_Pos                         1                                                         /*!< CCU1 CLK_M4_USB0_CFG: AUTO Position */
#define CCU1_CLK_M4_USB0_CFG_AUTO_Msk                         (0x01UL << CCU1_CLK_M4_USB0_CFG_AUTO_Pos)                 /*!< CCU1 CLK_M4_USB0_CFG: AUTO Mask     */
#define CCU1_CLK_M4_USB0_CFG_WAKEUP_Pos                       2                                                         /*!< CCU1 CLK_M4_USB0_CFG: WAKEUP Position */
#define CCU1_CLK_M4_USB0_CFG_WAKEUP_Msk                       (0x01UL << CCU1_CLK_M4_USB0_CFG_WAKEUP_Pos)               /*!< CCU1 CLK_M4_USB0_CFG: WAKEUP Mask   */

// ----------------------------------  CCU1_CLK_M4_USB0_STAT  -------------------------------------
#define CCU1_CLK_M4_USB0_STAT_RUN_Pos                         0                                                         /*!< CCU1 CLK_M4_USB0_STAT: RUN Position */
#define CCU1_CLK_M4_USB0_STAT_RUN_Msk                         (0x01UL << CCU1_CLK_M4_USB0_STAT_RUN_Pos)                 /*!< CCU1 CLK_M4_USB0_STAT: RUN Mask     */
#define CCU1_CLK_M4_USB0_STAT_AUTO_Pos                        1                                                         /*!< CCU1 CLK_M4_USB0_STAT: AUTO Position */
#define CCU1_CLK_M4_USB0_STAT_AUTO_Msk                        (0x01UL << CCU1_CLK_M4_USB0_STAT_AUTO_Pos)                /*!< CCU1 CLK_M4_USB0_STAT: AUTO Mask    */
#define CCU1_CLK_M4_USB0_STAT_WAKEUP_Pos                      2                                                         /*!< CCU1 CLK_M4_USB0_STAT: WAKEUP Position */
#define CCU1_CLK_M4_USB0_STAT_WAKEUP_Msk                      (0x01UL << CCU1_CLK_M4_USB0_STAT_WAKEUP_Pos)              /*!< CCU1 CLK_M4_USB0_STAT: WAKEUP Mask  */

// -----------------------------------  CCU1_CLK_M4_EMC_CFG  --------------------------------------
#define CCU1_CLK_M4_EMC_CFG_RUN_Pos                           0                                                         /*!< CCU1 CLK_M4_EMC_CFG: RUN Position   */
#define CCU1_CLK_M4_EMC_CFG_RUN_Msk                           (0x01UL << CCU1_CLK_M4_EMC_CFG_RUN_Pos)                   /*!< CCU1 CLK_M4_EMC_CFG: RUN Mask       */
#define CCU1_CLK_M4_EMC_CFG_AUTO_Pos                          1                                                         /*!< CCU1 CLK_M4_EMC_CFG: AUTO Position  */
#define CCU1_CLK_M4_EMC_CFG_AUTO_Msk                          (0x01UL << CCU1_CLK_M4_EMC_CFG_AUTO_Pos)                  /*!< CCU1 CLK_M4_EMC_CFG: AUTO Mask      */
#define CCU1_CLK_M4_EMC_CFG_WAKEUP_Pos                        2                                                         /*!< CCU1 CLK_M4_EMC_CFG: WAKEUP Position */
#define CCU1_CLK_M4_EMC_CFG_WAKEUP_Msk                        (0x01UL << CCU1_CLK_M4_EMC_CFG_WAKEUP_Pos)                /*!< CCU1 CLK_M4_EMC_CFG: WAKEUP Mask    */

// ----------------------------------  CCU1_CLK_M4_EMC_STAT  --------------------------------------
#define CCU1_CLK_M4_EMC_STAT_RUN_Pos                          0                                                         /*!< CCU1 CLK_M4_EMC_STAT: RUN Position  */
#define CCU1_CLK_M4_EMC_STAT_RUN_Msk                          (0x01UL << CCU1_CLK_M4_EMC_STAT_RUN_Pos)                  /*!< CCU1 CLK_M4_EMC_STAT: RUN Mask      */
#define CCU1_CLK_M4_EMC_STAT_AUTO_Pos                         1                                                         /*!< CCU1 CLK_M4_EMC_STAT: AUTO Position */
#define CCU1_CLK_M4_EMC_STAT_AUTO_Msk                         (0x01UL << CCU1_CLK_M4_EMC_STAT_AUTO_Pos)                 /*!< CCU1 CLK_M4_EMC_STAT: AUTO Mask     */
#define CCU1_CLK_M4_EMC_STAT_WAKEUP_Pos                       2                                                         /*!< CCU1 CLK_M4_EMC_STAT: WAKEUP Position */
#define CCU1_CLK_M4_EMC_STAT_WAKEUP_Msk                       (0x01UL << CCU1_CLK_M4_EMC_STAT_WAKEUP_Pos)               /*!< CCU1 CLK_M4_EMC_STAT: WAKEUP Mask   */

// ----------------------------------  CCU1_CLK_M4_SDIO_CFG  --------------------------------------
#define CCU1_CLK_M4_SDIO_CFG_RUN_Pos                          0                                                         /*!< CCU1 CLK_M4_SDIO_CFG: RUN Position  */
#define CCU1_CLK_M4_SDIO_CFG_RUN_Msk                          (0x01UL << CCU1_CLK_M4_SDIO_CFG_RUN_Pos)                  /*!< CCU1 CLK_M4_SDIO_CFG: RUN Mask      */
#define CCU1_CLK_M4_SDIO_CFG_AUTO_Pos                         1                                                         /*!< CCU1 CLK_M4_SDIO_CFG: AUTO Position */
#define CCU1_CLK_M4_SDIO_CFG_AUTO_Msk                         (0x01UL << CCU1_CLK_M4_SDIO_CFG_AUTO_Pos)                 /*!< CCU1 CLK_M4_SDIO_CFG: AUTO Mask     */
#define CCU1_CLK_M4_SDIO_CFG_WAKEUP_Pos                       2                                                         /*!< CCU1 CLK_M4_SDIO_CFG: WAKEUP Position */
#define CCU1_CLK_M4_SDIO_CFG_WAKEUP_Msk                       (0x01UL << CCU1_CLK_M4_SDIO_CFG_WAKEUP_Pos)               /*!< CCU1 CLK_M4_SDIO_CFG: WAKEUP Mask   */

// ----------------------------------  CCU1_CLK_M4_SDIO_STAT  -------------------------------------
#define CCU1_CLK_M4_SDIO_STAT_RUN_Pos                         0                                                         /*!< CCU1 CLK_M4_SDIO_STAT: RUN Position */
#define CCU1_CLK_M4_SDIO_STAT_RUN_Msk                         (0x01UL << CCU1_CLK_M4_SDIO_STAT_RUN_Pos)                 /*!< CCU1 CLK_M4_SDIO_STAT: RUN Mask     */
#define CCU1_CLK_M4_SDIO_STAT_AUTO_Pos                        1                                                         /*!< CCU1 CLK_M4_SDIO_STAT: AUTO Position */
#define CCU1_CLK_M4_SDIO_STAT_AUTO_Msk                        (0x01UL << CCU1_CLK_M4_SDIO_STAT_AUTO_Pos)                /*!< CCU1 CLK_M4_SDIO_STAT: AUTO Mask    */
#define CCU1_CLK_M4_SDIO_STAT_WAKEUP_Pos                      2                                                         /*!< CCU1 CLK_M4_SDIO_STAT: WAKEUP Position */
#define CCU1_CLK_M4_SDIO_STAT_WAKEUP_Msk                      (0x01UL << CCU1_CLK_M4_SDIO_STAT_WAKEUP_Pos)              /*!< CCU1 CLK_M4_SDIO_STAT: WAKEUP Mask  */

// -----------------------------------  CCU1_CLK_M4_DMA_CFG  --------------------------------------
#define CCU1_CLK_M4_DMA_CFG_RUN_Pos                           0                                                         /*!< CCU1 CLK_M4_DMA_CFG: RUN Position   */
#define CCU1_CLK_M4_DMA_CFG_RUN_Msk                           (0x01UL << CCU1_CLK_M4_DMA_CFG_RUN_Pos)                   /*!< CCU1 CLK_M4_DMA_CFG: RUN Mask       */
#define CCU1_CLK_M4_DMA_CFG_AUTO_Pos                          1                                                         /*!< CCU1 CLK_M4_DMA_CFG: AUTO Position  */
#define CCU1_CLK_M4_DMA_CFG_AUTO_Msk                          (0x01UL << CCU1_CLK_M4_DMA_CFG_AUTO_Pos)                  /*!< CCU1 CLK_M4_DMA_CFG: AUTO Mask      */
#define CCU1_CLK_M4_DMA_CFG_WAKEUP_Pos                        2                                                         /*!< CCU1 CLK_M4_DMA_CFG: WAKEUP Position */
#define CCU1_CLK_M4_DMA_CFG_WAKEUP_Msk                        (0x01UL << CCU1_CLK_M4_DMA_CFG_WAKEUP_Pos)                /*!< CCU1 CLK_M4_DMA_CFG: WAKEUP Mask    */

// ----------------------------------  CCU1_CLK_M4_DMA_STAT  --------------------------------------
#define CCU1_CLK_M4_DMA_STAT_RUN_Pos                          0                                                         /*!< CCU1 CLK_M4_DMA_STAT: RUN Position  */
#define CCU1_CLK_M4_DMA_STAT_RUN_Msk                          (0x01UL << CCU1_CLK_M4_DMA_STAT_RUN_Pos)                  /*!< CCU1 CLK_M4_DMA_STAT: RUN Mask      */
#define CCU1_CLK_M4_DMA_STAT_AUTO_Pos                         1                                                         /*!< CCU1 CLK_M4_DMA_STAT: AUTO Position */
#define CCU1_CLK_M4_DMA_STAT_AUTO_Msk                         (0x01UL << CCU1_CLK_M4_DMA_STAT_AUTO_Pos)                 /*!< CCU1 CLK_M4_DMA_STAT: AUTO Mask     */
#define CCU1_CLK_M4_DMA_STAT_WAKEUP_Pos                       2                                                         /*!< CCU1 CLK_M4_DMA_STAT: WAKEUP Position */
#define CCU1_CLK_M4_DMA_STAT_WAKEUP_Msk                       (0x01UL << CCU1_CLK_M4_DMA_STAT_WAKEUP_Pos)               /*!< CCU1 CLK_M4_DMA_STAT: WAKEUP Mask   */

// ---------------------------------  CCU1_CLK_M4_M4CORE_CFG  -------------------------------------
#define CCU1_CLK_M4_M4CORE_CFG_RUN_Pos                        0                                                         /*!< CCU1 CLK_M4_M4CORE_CFG: RUN Position */
#define CCU1_CLK_M4_M4CORE_CFG_RUN_Msk                        (0x01UL << CCU1_CLK_M4_M4CORE_CFG_RUN_Pos)                /*!< CCU1 CLK_M4_M4CORE_CFG: RUN Mask    */
#define CCU1_CLK_M4_M4CORE_CFG_AUTO_Pos                       1                                                         /*!< CCU1 CLK_M4_M4CORE_CFG: AUTO Position */
#define CCU1_CLK_M4_M4CORE_CFG_AUTO_Msk                       (0x01UL << CCU1_CLK_M4_M4CORE_CFG_AUTO_Pos)               /*!< CCU1 CLK_M4_M4CORE_CFG: AUTO Mask   */
#define CCU1_CLK_M4_M4CORE_CFG_WAKEUP_Pos                     2                                                         /*!< CCU1 CLK_M4_M4CORE_CFG: WAKEUP Position */
#define CCU1_CLK_M4_M4CORE_CFG_WAKEUP_Msk                     (0x01UL << CCU1_CLK_M4_M4CORE_CFG_WAKEUP_Pos)             /*!< CCU1 CLK_M4_M4CORE_CFG: WAKEUP Mask */

// ---------------------------------  CCU1_CLK_M4_M3CORE_STAT  ------------------------------------
#define CCU1_CLK_M4_M3CORE_STAT_RUN_Pos                       0                                                         /*!< CCU1 CLK_M4_M3CORE_STAT: RUN Position */
#define CCU1_CLK_M4_M3CORE_STAT_RUN_Msk                       (0x01UL << CCU1_CLK_M4_M3CORE_STAT_RUN_Pos)               /*!< CCU1 CLK_M4_M3CORE_STAT: RUN Mask   */
#define CCU1_CLK_M4_M3CORE_STAT_AUTO_Pos                      1                                                         /*!< CCU1 CLK_M4_M3CORE_STAT: AUTO Position */
#define CCU1_CLK_M4_M3CORE_STAT_AUTO_Msk                      (0x01UL << CCU1_CLK_M4_M3CORE_STAT_AUTO_Pos)              /*!< CCU1 CLK_M4_M3CORE_STAT: AUTO Mask  */
#define CCU1_CLK_M4_M3CORE_STAT_WAKEUP_Pos                    2                                                         /*!< CCU1 CLK_M4_M3CORE_STAT: WAKEUP Position */
#define CCU1_CLK_M4_M3CORE_STAT_WAKEUP_Msk                    (0x01UL << CCU1_CLK_M4_M3CORE_STAT_WAKEUP_Pos)            /*!< CCU1 CLK_M4_M3CORE_STAT: WAKEUP Mask */

// -----------------------------------  CCU1_CLK_M4_SCT_CFG  --------------------------------------
#define CCU1_CLK_M4_SCT_CFG_RUN_Pos                           0                                                         /*!< CCU1 CLK_M4_SCT_CFG: RUN Position   */
#define CCU1_CLK_M4_SCT_CFG_RUN_Msk                           (0x01UL << CCU1_CLK_M4_SCT_CFG_RUN_Pos)                   /*!< CCU1 CLK_M4_SCT_CFG: RUN Mask       */
#define CCU1_CLK_M4_SCT_CFG_AUTO_Pos                          1                                                         /*!< CCU1 CLK_M4_SCT_CFG: AUTO Position  */
#define CCU1_CLK_M4_SCT_CFG_AUTO_Msk                          (0x01UL << CCU1_CLK_M4_SCT_CFG_AUTO_Pos)                  /*!< CCU1 CLK_M4_SCT_CFG: AUTO Mask      */
#define CCU1_CLK_M4_SCT_CFG_WAKEUP_Pos                        2                                                         /*!< CCU1 CLK_M4_SCT_CFG: WAKEUP Position */
#define CCU1_CLK_M4_SCT_CFG_WAKEUP_Msk                        (0x01UL << CCU1_CLK_M4_SCT_CFG_WAKEUP_Pos)                /*!< CCU1 CLK_M4_SCT_CFG: WAKEUP Mask    */

// ----------------------------------  CCU1_CLK_M4_SCT_STAT  --------------------------------------
#define CCU1_CLK_M4_SCT_STAT_RUN_Pos                          0                                                         /*!< CCU1 CLK_M4_SCT_STAT: RUN Position  */
#define CCU1_CLK_M4_SCT_STAT_RUN_Msk                          (0x01UL << CCU1_CLK_M4_SCT_STAT_RUN_Pos)                  /*!< CCU1 CLK_M4_SCT_STAT: RUN Mask      */
#define CCU1_CLK_M4_SCT_STAT_AUTO_Pos                         1                                                         /*!< CCU1 CLK_M4_SCT_STAT: AUTO Position */
#define CCU1_CLK_M4_SCT_STAT_AUTO_Msk                         (0x01UL << CCU1_CLK_M4_SCT_STAT_AUTO_Pos)                 /*!< CCU1 CLK_M4_SCT_STAT: AUTO Mask     */
#define CCU1_CLK_M4_SCT_STAT_WAKEUP_Pos                       2                                                         /*!< CCU1 CLK_M4_SCT_STAT: WAKEUP Position */
#define CCU1_CLK_M4_SCT_STAT_WAKEUP_Msk                       (0x01UL << CCU1_CLK_M4_SCT_STAT_WAKEUP_Pos)               /*!< CCU1 CLK_M4_SCT_STAT: WAKEUP Mask   */

// ----------------------------------  CCU1_CLK_M4_USB1_CFG  --------------------------------------
#define CCU1_CLK_M4_USB1_CFG_RUN_Pos                          0                                                         /*!< CCU1 CLK_M4_USB1_CFG: RUN Position  */
#define CCU1_CLK_M4_USB1_CFG_RUN_Msk                          (0x01UL << CCU1_CLK_M4_USB1_CFG_RUN_Pos)                  /*!< CCU1 CLK_M4_USB1_CFG: RUN Mask      */
#define CCU1_CLK_M4_USB1_CFG_AUTO_Pos                         1                                                         /*!< CCU1 CLK_M4_USB1_CFG: AUTO Position */
#define CCU1_CLK_M4_USB1_CFG_AUTO_Msk                         (0x01UL << CCU1_CLK_M4_USB1_CFG_AUTO_Pos)                 /*!< CCU1 CLK_M4_USB1_CFG: AUTO Mask     */
#define CCU1_CLK_M4_USB1_CFG_WAKEUP_Pos                       2                                                         /*!< CCU1 CLK_M4_USB1_CFG: WAKEUP Position */
#define CCU1_CLK_M4_USB1_CFG_WAKEUP_Msk                       (0x01UL << CCU1_CLK_M4_USB1_CFG_WAKEUP_Pos)               /*!< CCU1 CLK_M4_USB1_CFG: WAKEUP Mask   */

// ----------------------------------  CCU1_CLK_M4_USB1_STAT  -------------------------------------
#define CCU1_CLK_M4_USB1_STAT_RUN_Pos                         0                                                         /*!< CCU1 CLK_M4_USB1_STAT: RUN Position */
#define CCU1_CLK_M4_USB1_STAT_RUN_Msk                         (0x01UL << CCU1_CLK_M4_USB1_STAT_RUN_Pos)                 /*!< CCU1 CLK_M4_USB1_STAT: RUN Mask     */
#define CCU1_CLK_M4_USB1_STAT_AUTO_Pos                        1                                                         /*!< CCU1 CLK_M4_USB1_STAT: AUTO Position */
#define CCU1_CLK_M4_USB1_STAT_AUTO_Msk                        (0x01UL << CCU1_CLK_M4_USB1_STAT_AUTO_Pos)                /*!< CCU1 CLK_M4_USB1_STAT: AUTO Mask    */
#define CCU1_CLK_M4_USB1_STAT_WAKEUP_Pos                      2                                                         /*!< CCU1 CLK_M4_USB1_STAT: WAKEUP Position */
#define CCU1_CLK_M4_USB1_STAT_WAKEUP_Msk                      (0x01UL << CCU1_CLK_M4_USB1_STAT_WAKEUP_Pos)              /*!< CCU1 CLK_M4_USB1_STAT: WAKEUP Mask  */

// ---------------------------------  CCU1_CLK_M4_EMCDIV_CFG  -------------------------------------
#define CCU1_CLK_M4_EMCDIV_CFG_RUN_Pos                        0                                                         /*!< CCU1 CLK_M4_EMCDIV_CFG: RUN Position */
#define CCU1_CLK_M4_EMCDIV_CFG_RUN_Msk                        (0x01UL << CCU1_CLK_M4_EMCDIV_CFG_RUN_Pos)                /*!< CCU1 CLK_M4_EMCDIV_CFG: RUN Mask    */
#define CCU1_CLK_M4_EMCDIV_CFG_AUTO_Pos                       1                                                         /*!< CCU1 CLK_M4_EMCDIV_CFG: AUTO Position */
#define CCU1_CLK_M4_EMCDIV_CFG_AUTO_Msk                       (0x01UL << CCU1_CLK_M4_EMCDIV_CFG_AUTO_Pos)               /*!< CCU1 CLK_M4_EMCDIV_CFG: AUTO Mask   */
#define CCU1_CLK_M4_EMCDIV_CFG_WAKEUP_Pos                     2                                                         /*!< CCU1 CLK_M4_EMCDIV_CFG: WAKEUP Position */
#define CCU1_CLK_M4_EMCDIV_CFG_WAKEUP_Msk                     (0x01UL << CCU1_CLK_M4_EMCDIV_CFG_WAKEUP_Pos)             /*!< CCU1 CLK_M4_EMCDIV_CFG: WAKEUP Mask */

// ---------------------------------  CCU1_CLK_M4_EMCDIV_STAT  ------------------------------------
#define CCU1_CLK_M4_EMCDIV_STAT_RUN_Pos                       0                                                         /*!< CCU1 CLK_M4_EMCDIV_STAT: RUN Position */
#define CCU1_CLK_M4_EMCDIV_STAT_RUN_Msk                       (0x01UL << CCU1_CLK_M4_EMCDIV_STAT_RUN_Pos)               /*!< CCU1 CLK_M4_EMCDIV_STAT: RUN Mask   */
#define CCU1_CLK_M4_EMCDIV_STAT_AUTO_Pos                      1                                                         /*!< CCU1 CLK_M4_EMCDIV_STAT: AUTO Position */
#define CCU1_CLK_M4_EMCDIV_STAT_AUTO_Msk                      (0x01UL << CCU1_CLK_M4_EMCDIV_STAT_AUTO_Pos)              /*!< CCU1 CLK_M4_EMCDIV_STAT: AUTO Mask  */
#define CCU1_CLK_M4_EMCDIV_STAT_WAKEUP_Pos                    2                                                         /*!< CCU1 CLK_M4_EMCDIV_STAT: WAKEUP Position */
#define CCU1_CLK_M4_EMCDIV_STAT_WAKEUP_Msk                    (0x01UL << CCU1_CLK_M4_EMCDIV_STAT_WAKEUP_Pos)            /*!< CCU1 CLK_M4_EMCDIV_STAT: WAKEUP Mask */

// ----------------------------------  CCU1_CLK_M4_M0APP_CFG  -------------------------------------
#define CCU1_CLK_M4_M0APP_CFG_RUN_Pos                         0                                                         /*!< CCU1 CLK_M4_M0APP_CFG: RUN Position */
#define CCU1_CLK_M4_M0APP_CFG_RUN_Msk                         (0x01UL << CCU1_CLK_M4_M0APP_CFG_RUN_Pos)                 /*!< CCU1 CLK_M4_M0APP_CFG: RUN Mask     */
#define CCU1_CLK_M4_M0APP_CFG_AUTO_Pos                        1                                                         /*!< CCU1 CLK_M4_M0APP_CFG: AUTO Position */
#define CCU1_CLK_M4_M0APP_CFG_AUTO_Msk                        (0x01UL << CCU1_CLK_M4_M0APP_CFG_AUTO_Pos)                /*!< CCU1 CLK_M4_M0APP_CFG: AUTO Mask    */
#define CCU1_CLK_M4_M0APP_CFG_WAKEUP_Pos                      2                                                         /*!< CCU1 CLK_M4_M0APP_CFG: WAKEUP Position */
#define CCU1_CLK_M4_M0APP_CFG_WAKEUP_Msk                      (0x01UL << CCU1_CLK_M4_M0APP_CFG_WAKEUP_Pos)              /*!< CCU1 CLK_M4_M0APP_CFG: WAKEUP Mask  */

// ---------------------------------  CCU1_CLK_M4_M0APP_STAT  -------------------------------------
#define CCU1_CLK_M4_M0APP_STAT_RUN_Pos                        0                                                         /*!< CCU1 CLK_M4_M0APP_STAT: RUN Position */
#define CCU1_CLK_M4_M0APP_STAT_RUN_Msk                        (0x01UL << CCU1_CLK_M4_M0APP_STAT_RUN_Pos)                /*!< CCU1 CLK_M4_M0APP_STAT: RUN Mask    */
#define CCU1_CLK_M4_M0APP_STAT_AUTO_Pos                       1                                                         /*!< CCU1 CLK_M4_M0APP_STAT: AUTO Position */
#define CCU1_CLK_M4_M0APP_STAT_AUTO_Msk                       (0x01UL << CCU1_CLK_M4_M0APP_STAT_AUTO_Pos)               /*!< CCU1 CLK_M4_M0APP_STAT: AUTO Mask   */
#define CCU1_CLK_M4_M0APP_STAT_WAKEUP_Pos                     2                                                         /*!< CCU1 CLK_M4_M0APP_STAT: WAKEUP Position */
#define CCU1_CLK_M4_M0APP_STAT_WAKEUP_Msk                     (0x01UL << CCU1_CLK_M4_M0APP_STAT_WAKEUP_Pos)             /*!< CCU1 CLK_M4_M0APP_STAT: WAKEUP Mask */

// ----------------------------------  CCU1_CLK_M4_WWDT_CFG  --------------------------------------
#define CCU1_CLK_M4_WWDT_CFG_RUN_Pos                          0                                                         /*!< CCU1 CLK_M4_WWDT_CFG: RUN Position  */
#define CCU1_CLK_M4_WWDT_CFG_RUN_Msk                          (0x01UL << CCU1_CLK_M4_WWDT_CFG_RUN_Pos)                  /*!< CCU1 CLK_M4_WWDT_CFG: RUN Mask      */
#define CCU1_CLK_M4_WWDT_CFG_AUTO_Pos                         1                                                         /*!< CCU1 CLK_M4_WWDT_CFG: AUTO Position */
#define CCU1_CLK_M4_WWDT_CFG_AUTO_Msk                         (0x01UL << CCU1_CLK_M4_WWDT_CFG_AUTO_Pos)                 /*!< CCU1 CLK_M4_WWDT_CFG: AUTO Mask     */
#define CCU1_CLK_M4_WWDT_CFG_WAKEUP_Pos                       2                                                         /*!< CCU1 CLK_M4_WWDT_CFG: WAKEUP Position */
#define CCU1_CLK_M4_WWDT_CFG_WAKEUP_Msk                       (0x01UL << CCU1_CLK_M4_WWDT_CFG_WAKEUP_Pos)               /*!< CCU1 CLK_M4_WWDT_CFG: WAKEUP Mask   */

// ----------------------------------  CCU1_CLK_M4_WWDT_STAT  -------------------------------------
#define CCU1_CLK_M4_WWDT_STAT_RUN_Pos                         0                                                         /*!< CCU1 CLK_M4_WWDT_STAT: RUN Position */
#define CCU1_CLK_M4_WWDT_STAT_RUN_Msk                         (0x01UL << CCU1_CLK_M4_WWDT_STAT_RUN_Pos)                 /*!< CCU1 CLK_M4_WWDT_STAT: RUN Mask     */
#define CCU1_CLK_M4_WWDT_STAT_AUTO_Pos                        1                                                         /*!< CCU1 CLK_M4_WWDT_STAT: AUTO Position */
#define CCU1_CLK_M4_WWDT_STAT_AUTO_Msk                        (0x01UL << CCU1_CLK_M4_WWDT_STAT_AUTO_Pos)                /*!< CCU1 CLK_M4_WWDT_STAT: AUTO Mask    */
#define CCU1_CLK_M4_WWDT_STAT_WAKEUP_Pos                      2                                                         /*!< CCU1 CLK_M4_WWDT_STAT: WAKEUP Position */
#define CCU1_CLK_M4_WWDT_STAT_WAKEUP_Msk                      (0x01UL << CCU1_CLK_M4_WWDT_STAT_WAKEUP_Pos)              /*!< CCU1 CLK_M4_WWDT_STAT: WAKEUP Mask  */

// ---------------------------------  CCU1_CLK_M4_USART0_CFG  -------------------------------------
#define CCU1_CLK_M4_USART0_CFG_RUN_Pos                        0                                                         /*!< CCU1 CLK_M4_USART0_CFG: RUN Position */
#define CCU1_CLK_M4_USART0_CFG_RUN_Msk                        (0x01UL << CCU1_CLK_M4_USART0_CFG_RUN_Pos)                /*!< CCU1 CLK_M4_USART0_CFG: RUN Mask    */
#define CCU1_CLK_M4_USART0_CFG_AUTO_Pos                       1                                                         /*!< CCU1 CLK_M4_USART0_CFG: AUTO Position */
#define CCU1_CLK_M4_USART0_CFG_AUTO_Msk                       (0x01UL << CCU1_CLK_M4_USART0_CFG_AUTO_Pos)               /*!< CCU1 CLK_M4_USART0_CFG: AUTO Mask   */
#define CCU1_CLK_M4_USART0_CFG_WAKEUP_Pos                     2                                                         /*!< CCU1 CLK_M4_USART0_CFG: WAKEUP Position */
#define CCU1_CLK_M4_USART0_CFG_WAKEUP_Msk                     (0x01UL << CCU1_CLK_M4_USART0_CFG_WAKEUP_Pos)             /*!< CCU1 CLK_M4_USART0_CFG: WAKEUP Mask */

// ---------------------------------  CCU1_CLK_M4_USART0_STAT  ------------------------------------
#define CCU1_CLK_M4_USART0_STAT_RUN_Pos                       0                                                         /*!< CCU1 CLK_M4_USART0_STAT: RUN Position */
#define CCU1_CLK_M4_USART0_STAT_RUN_Msk                       (0x01UL << CCU1_CLK_M4_USART0_STAT_RUN_Pos)               /*!< CCU1 CLK_M4_USART0_STAT: RUN Mask   */
#define CCU1_CLK_M4_USART0_STAT_AUTO_Pos                      1                                                         /*!< CCU1 CLK_M4_USART0_STAT: AUTO Position */
#define CCU1_CLK_M4_USART0_STAT_AUTO_Msk                      (0x01UL << CCU1_CLK_M4_USART0_STAT_AUTO_Pos)              /*!< CCU1 CLK_M4_USART0_STAT: AUTO Mask  */
#define CCU1_CLK_M4_USART0_STAT_WAKEUP_Pos                    2                                                         /*!< CCU1 CLK_M4_USART0_STAT: WAKEUP Position */
#define CCU1_CLK_M4_USART0_STAT_WAKEUP_Msk                    (0x01UL << CCU1_CLK_M4_USART0_STAT_WAKEUP_Pos)            /*!< CCU1 CLK_M4_USART0_STAT: WAKEUP Mask */

// ----------------------------------  CCU1_CLK_M4_UART1_CFG  -------------------------------------
#define CCU1_CLK_M4_UART1_CFG_RUN_Pos                         0                                                         /*!< CCU1 CLK_M4_UART1_CFG: RUN Position */
#define CCU1_CLK_M4_UART1_CFG_RUN_Msk                         (0x01UL << CCU1_CLK_M4_UART1_CFG_RUN_Pos)                 /*!< CCU1 CLK_M4_UART1_CFG: RUN Mask     */
#define CCU1_CLK_M4_UART1_CFG_AUTO_Pos                        1                                                         /*!< CCU1 CLK_M4_UART1_CFG: AUTO Position */
#define CCU1_CLK_M4_UART1_CFG_AUTO_Msk                        (0x01UL << CCU1_CLK_M4_UART1_CFG_AUTO_Pos)                /*!< CCU1 CLK_M4_UART1_CFG: AUTO Mask    */
#define CCU1_CLK_M4_UART1_CFG_WAKEUP_Pos                      2                                                         /*!< CCU1 CLK_M4_UART1_CFG: WAKEUP Position */
#define CCU1_CLK_M4_UART1_CFG_WAKEUP_Msk                      (0x01UL << CCU1_CLK_M4_UART1_CFG_WAKEUP_Pos)              /*!< CCU1 CLK_M4_UART1_CFG: WAKEUP Mask  */

// ---------------------------------  CCU1_CLK_M4_UART1_STAT  -------------------------------------
#define CCU1_CLK_M4_UART1_STAT_RUN_Pos                        0                                                         /*!< CCU1 CLK_M4_UART1_STAT: RUN Position */
#define CCU1_CLK_M4_UART1_STAT_RUN_Msk                        (0x01UL << CCU1_CLK_M4_UART1_STAT_RUN_Pos)                /*!< CCU1 CLK_M4_UART1_STAT: RUN Mask    */
#define CCU1_CLK_M4_UART1_STAT_AUTO_Pos                       1                                                         /*!< CCU1 CLK_M4_UART1_STAT: AUTO Position */
#define CCU1_CLK_M4_UART1_STAT_AUTO_Msk                       (0x01UL << CCU1_CLK_M4_UART1_STAT_AUTO_Pos)               /*!< CCU1 CLK_M4_UART1_STAT: AUTO Mask   */
#define CCU1_CLK_M4_UART1_STAT_WAKEUP_Pos                     2                                                         /*!< CCU1 CLK_M4_UART1_STAT: WAKEUP Position */
#define CCU1_CLK_M4_UART1_STAT_WAKEUP_Msk                     (0x01UL << CCU1_CLK_M4_UART1_STAT_WAKEUP_Pos)             /*!< CCU1 CLK_M4_UART1_STAT: WAKEUP Mask */

// ----------------------------------  CCU1_CLK_M4_SSP0_CFG  --------------------------------------
#define CCU1_CLK_M4_SSP0_CFG_RUN_Pos                          0                                                         /*!< CCU1 CLK_M4_SSP0_CFG: RUN Position  */
#define CCU1_CLK_M4_SSP0_CFG_RUN_Msk                          (0x01UL << CCU1_CLK_M4_SSP0_CFG_RUN_Pos)                  /*!< CCU1 CLK_M4_SSP0_CFG: RUN Mask      */
#define CCU1_CLK_M4_SSP0_CFG_AUTO_Pos                         1                                                         /*!< CCU1 CLK_M4_SSP0_CFG: AUTO Position */
#define CCU1_CLK_M4_SSP0_CFG_AUTO_Msk                         (0x01UL << CCU1_CLK_M4_SSP0_CFG_AUTO_Pos)                 /*!< CCU1 CLK_M4_SSP0_CFG: AUTO Mask     */
#define CCU1_CLK_M4_SSP0_CFG_WAKEUP_Pos                       2                                                         /*!< CCU1 CLK_M4_SSP0_CFG: WAKEUP Position */
#define CCU1_CLK_M4_SSP0_CFG_WAKEUP_Msk                       (0x01UL << CCU1_CLK_M4_SSP0_CFG_WAKEUP_Pos)               /*!< CCU1 CLK_M4_SSP0_CFG: WAKEUP Mask   */

// ----------------------------------  CCU1_CLK_M4_SSP0_STAT  -------------------------------------
#define CCU1_CLK_M4_SSP0_STAT_RUN_Pos                         0                                                         /*!< CCU1 CLK_M4_SSP0_STAT: RUN Position */
#define CCU1_CLK_M4_SSP0_STAT_RUN_Msk                         (0x01UL << CCU1_CLK_M4_SSP0_STAT_RUN_Pos)                 /*!< CCU1 CLK_M4_SSP0_STAT: RUN Mask     */
#define CCU1_CLK_M4_SSP0_STAT_AUTO_Pos                        1                                                         /*!< CCU1 CLK_M4_SSP0_STAT: AUTO Position */
#define CCU1_CLK_M4_SSP0_STAT_AUTO_Msk                        (0x01UL << CCU1_CLK_M4_SSP0_STAT_AUTO_Pos)                /*!< CCU1 CLK_M4_SSP0_STAT: AUTO Mask    */
#define CCU1_CLK_M4_SSP0_STAT_WAKEUP_Pos                      2                                                         /*!< CCU1 CLK_M4_SSP0_STAT: WAKEUP Position */
#define CCU1_CLK_M4_SSP0_STAT_WAKEUP_Msk                      (0x01UL << CCU1_CLK_M4_SSP0_STAT_WAKEUP_Pos)              /*!< CCU1 CLK_M4_SSP0_STAT: WAKEUP Mask  */

// ---------------------------------  CCU1_CLK_M4_TIMER0_CFG  -------------------------------------
#define CCU1_CLK_M4_TIMER0_CFG_RUN_Pos                        0                                                         /*!< CCU1 CLK_M4_TIMER0_CFG: RUN Position */
#define CCU1_CLK_M4_TIMER0_CFG_RUN_Msk                        (0x01UL << CCU1_CLK_M4_TIMER0_CFG_RUN_Pos)                /*!< CCU1 CLK_M4_TIMER0_CFG: RUN Mask    */
#define CCU1_CLK_M4_TIMER0_CFG_AUTO_Pos                       1                                                         /*!< CCU1 CLK_M4_TIMER0_CFG: AUTO Position */
#define CCU1_CLK_M4_TIMER0_CFG_AUTO_Msk                       (0x01UL << CCU1_CLK_M4_TIMER0_CFG_AUTO_Pos)               /*!< CCU1 CLK_M4_TIMER0_CFG: AUTO Mask   */
#define CCU1_CLK_M4_TIMER0_CFG_WAKEUP_Pos                     2                                                         /*!< CCU1 CLK_M4_TIMER0_CFG: WAKEUP Position */
#define CCU1_CLK_M4_TIMER0_CFG_WAKEUP_Msk                     (0x01UL << CCU1_CLK_M4_TIMER0_CFG_WAKEUP_Pos)             /*!< CCU1 CLK_M4_TIMER0_CFG: WAKEUP Mask */

// ---------------------------------  CCU1_CLK_M4_TIMER0_STAT  ------------------------------------
#define CCU1_CLK_M4_TIMER0_STAT_RUN_Pos                       0                                                         /*!< CCU1 CLK_M4_TIMER0_STAT: RUN Position */
#define CCU1_CLK_M4_TIMER0_STAT_RUN_Msk                       (0x01UL << CCU1_CLK_M4_TIMER0_STAT_RUN_Pos)               /*!< CCU1 CLK_M4_TIMER0_STAT: RUN Mask   */
#define CCU1_CLK_M4_TIMER0_STAT_AUTO_Pos                      1                                                         /*!< CCU1 CLK_M4_TIMER0_STAT: AUTO Position */
#define CCU1_CLK_M4_TIMER0_STAT_AUTO_Msk                      (0x01UL << CCU1_CLK_M4_TIMER0_STAT_AUTO_Pos)              /*!< CCU1 CLK_M4_TIMER0_STAT: AUTO Mask  */
#define CCU1_CLK_M4_TIMER0_STAT_WAKEUP_Pos                    2                                                         /*!< CCU1 CLK_M4_TIMER0_STAT: WAKEUP Position */
#define CCU1_CLK_M4_TIMER0_STAT_WAKEUP_Msk                    (0x01UL << CCU1_CLK_M4_TIMER0_STAT_WAKEUP_Pos)            /*!< CCU1 CLK_M4_TIMER0_STAT: WAKEUP Mask */

// ---------------------------------  CCU1_CLK_M4_TIMER1_CFG  -------------------------------------
#define CCU1_CLK_M4_TIMER1_CFG_RUN_Pos                        0                                                         /*!< CCU1 CLK_M4_TIMER1_CFG: RUN Position */
#define CCU1_CLK_M4_TIMER1_CFG_RUN_Msk                        (0x01UL << CCU1_CLK_M4_TIMER1_CFG_RUN_Pos)                /*!< CCU1 CLK_M4_TIMER1_CFG: RUN Mask    */
#define CCU1_CLK_M4_TIMER1_CFG_AUTO_Pos                       1                                                         /*!< CCU1 CLK_M4_TIMER1_CFG: AUTO Position */
#define CCU1_CLK_M4_TIMER1_CFG_AUTO_Msk                       (0x01UL << CCU1_CLK_M4_TIMER1_CFG_AUTO_Pos)               /*!< CCU1 CLK_M4_TIMER1_CFG: AUTO Mask   */
#define CCU1_CLK_M4_TIMER1_CFG_WAKEUP_Pos                     2                                                         /*!< CCU1 CLK_M4_TIMER1_CFG: WAKEUP Position */
#define CCU1_CLK_M4_TIMER1_CFG_WAKEUP_Msk                     (0x01UL << CCU1_CLK_M4_TIMER1_CFG_WAKEUP_Pos)             /*!< CCU1 CLK_M4_TIMER1_CFG: WAKEUP Mask */

// ---------------------------------  CCU1_CLK_M4_TIMER1_STAT  ------------------------------------
#define CCU1_CLK_M4_TIMER1_STAT_RUN_Pos                       0                                                         /*!< CCU1 CLK_M4_TIMER1_STAT: RUN Position */
#define CCU1_CLK_M4_TIMER1_STAT_RUN_Msk                       (0x01UL << CCU1_CLK_M4_TIMER1_STAT_RUN_Pos)               /*!< CCU1 CLK_M4_TIMER1_STAT: RUN Mask   */
#define CCU1_CLK_M4_TIMER1_STAT_AUTO_Pos                      1                                                         /*!< CCU1 CLK_M4_TIMER1_STAT: AUTO Position */
#define CCU1_CLK_M4_TIMER1_STAT_AUTO_Msk                      (0x01UL << CCU1_CLK_M4_TIMER1_STAT_AUTO_Pos)              /*!< CCU1 CLK_M4_TIMER1_STAT: AUTO Mask  */
#define CCU1_CLK_M4_TIMER1_STAT_WAKEUP_Pos                    2                                                         /*!< CCU1 CLK_M4_TIMER1_STAT: WAKEUP Position */
#define CCU1_CLK_M4_TIMER1_STAT_WAKEUP_Msk                    (0x01UL << CCU1_CLK_M4_TIMER1_STAT_WAKEUP_Pos)            /*!< CCU1 CLK_M4_TIMER1_STAT: WAKEUP Mask */

// -----------------------------------  CCU1_CLK_M4_SCU_CFG  --------------------------------------
#define CCU1_CLK_M4_SCU_CFG_RUN_Pos                           0                                                         /*!< CCU1 CLK_M4_SCU_CFG: RUN Position   */
#define CCU1_CLK_M4_SCU_CFG_RUN_Msk                           (0x01UL << CCU1_CLK_M4_SCU_CFG_RUN_Pos)                   /*!< CCU1 CLK_M4_SCU_CFG: RUN Mask       */
#define CCU1_CLK_M4_SCU_CFG_AUTO_Pos                          1                                                         /*!< CCU1 CLK_M4_SCU_CFG: AUTO Position  */
#define CCU1_CLK_M4_SCU_CFG_AUTO_Msk                          (0x01UL << CCU1_CLK_M4_SCU_CFG_AUTO_Pos)                  /*!< CCU1 CLK_M4_SCU_CFG: AUTO Mask      */
#define CCU1_CLK_M4_SCU_CFG_WAKEUP_Pos                        2                                                         /*!< CCU1 CLK_M4_SCU_CFG: WAKEUP Position */
#define CCU1_CLK_M4_SCU_CFG_WAKEUP_Msk                        (0x01UL << CCU1_CLK_M4_SCU_CFG_WAKEUP_Pos)                /*!< CCU1 CLK_M4_SCU_CFG: WAKEUP Mask    */

// ----------------------------------  CCU1_CLK_M4_SCU_STAT  --------------------------------------
#define CCU1_CLK_M4_SCU_STAT_RUN_Pos                          0                                                         /*!< CCU1 CLK_M4_SCU_STAT: RUN Position  */
#define CCU1_CLK_M4_SCU_STAT_RUN_Msk                          (0x01UL << CCU1_CLK_M4_SCU_STAT_RUN_Pos)                  /*!< CCU1 CLK_M4_SCU_STAT: RUN Mask      */
#define CCU1_CLK_M4_SCU_STAT_AUTO_Pos                         1                                                         /*!< CCU1 CLK_M4_SCU_STAT: AUTO Position */
#define CCU1_CLK_M4_SCU_STAT_AUTO_Msk                         (0x01UL << CCU1_CLK_M4_SCU_STAT_AUTO_Pos)                 /*!< CCU1 CLK_M4_SCU_STAT: AUTO Mask     */
#define CCU1_CLK_M4_SCU_STAT_WAKEUP_Pos                       2                                                         /*!< CCU1 CLK_M4_SCU_STAT: WAKEUP Position */
#define CCU1_CLK_M4_SCU_STAT_WAKEUP_Msk                       (0x01UL << CCU1_CLK_M4_SCU_STAT_WAKEUP_Pos)               /*!< CCU1 CLK_M4_SCU_STAT: WAKEUP Mask   */

// ----------------------------------  CCU1_CLK_M4_CREG_CFG  --------------------------------------
#define CCU1_CLK_M4_CREG_CFG_RUN_Pos                          0                                                         /*!< CCU1 CLK_M4_CREG_CFG: RUN Position  */
#define CCU1_CLK_M4_CREG_CFG_RUN_Msk                          (0x01UL << CCU1_CLK_M4_CREG_CFG_RUN_Pos)                  /*!< CCU1 CLK_M4_CREG_CFG: RUN Mask      */
#define CCU1_CLK_M4_CREG_CFG_AUTO_Pos                         1                                                         /*!< CCU1 CLK_M4_CREG_CFG: AUTO Position */
#define CCU1_CLK_M4_CREG_CFG_AUTO_Msk                         (0x01UL << CCU1_CLK_M4_CREG_CFG_AUTO_Pos)                 /*!< CCU1 CLK_M4_CREG_CFG: AUTO Mask     */
#define CCU1_CLK_M4_CREG_CFG_WAKEUP_Pos                       2                                                         /*!< CCU1 CLK_M4_CREG_CFG: WAKEUP Position */
#define CCU1_CLK_M4_CREG_CFG_WAKEUP_Msk                       (0x01UL << CCU1_CLK_M4_CREG_CFG_WAKEUP_Pos)               /*!< CCU1 CLK_M4_CREG_CFG: WAKEUP Mask   */

// ----------------------------------  CCU1_CLK_M4_CREG_STAT  -------------------------------------
#define CCU1_CLK_M4_CREG_STAT_RUN_Pos                         0                                                         /*!< CCU1 CLK_M4_CREG_STAT: RUN Position */
#define CCU1_CLK_M4_CREG_STAT_RUN_Msk                         (0x01UL << CCU1_CLK_M4_CREG_STAT_RUN_Pos)                 /*!< CCU1 CLK_M4_CREG_STAT: RUN Mask     */
#define CCU1_CLK_M4_CREG_STAT_AUTO_Pos                        1                                                         /*!< CCU1 CLK_M4_CREG_STAT: AUTO Position */
#define CCU1_CLK_M4_CREG_STAT_AUTO_Msk                        (0x01UL << CCU1_CLK_M4_CREG_STAT_AUTO_Pos)                /*!< CCU1 CLK_M4_CREG_STAT: AUTO Mask    */
#define CCU1_CLK_M4_CREG_STAT_WAKEUP_Pos                      2                                                         /*!< CCU1 CLK_M4_CREG_STAT: WAKEUP Position */
#define CCU1_CLK_M4_CREG_STAT_WAKEUP_Msk                      (0x01UL << CCU1_CLK_M4_CREG_STAT_WAKEUP_Pos)              /*!< CCU1 CLK_M4_CREG_STAT: WAKEUP Mask  */

// ---------------------------------  CCU1_CLK_M4_RITIMER_CFG  ------------------------------------
#define CCU1_CLK_M4_RITIMER_CFG_RUN_Pos                       0                                                         /*!< CCU1 CLK_M4_RITIMER_CFG: RUN Position */
#define CCU1_CLK_M4_RITIMER_CFG_RUN_Msk                       (0x01UL << CCU1_CLK_M4_RITIMER_CFG_RUN_Pos)               /*!< CCU1 CLK_M4_RITIMER_CFG: RUN Mask   */
#define CCU1_CLK_M4_RITIMER_CFG_AUTO_Pos                      1                                                         /*!< CCU1 CLK_M4_RITIMER_CFG: AUTO Position */
#define CCU1_CLK_M4_RITIMER_CFG_AUTO_Msk                      (0x01UL << CCU1_CLK_M4_RITIMER_CFG_AUTO_Pos)              /*!< CCU1 CLK_M4_RITIMER_CFG: AUTO Mask  */
#define CCU1_CLK_M4_RITIMER_CFG_WAKEUP_Pos                    2                                                         /*!< CCU1 CLK_M4_RITIMER_CFG: WAKEUP Position */
#define CCU1_CLK_M4_RITIMER_CFG_WAKEUP_Msk                    (0x01UL << CCU1_CLK_M4_RITIMER_CFG_WAKEUP_Pos)            /*!< CCU1 CLK_M4_RITIMER_CFG: WAKEUP Mask */

// --------------------------------  CCU1_CLK_M4_RITIMER_STAT  ------------------------------------
#define CCU1_CLK_M4_RITIMER_STAT_RUN_Pos                      0                                                         /*!< CCU1 CLK_M4_RITIMER_STAT: RUN Position */
#define CCU1_CLK_M4_RITIMER_STAT_RUN_Msk                      (0x01UL << CCU1_CLK_M4_RITIMER_STAT_RUN_Pos)              /*!< CCU1 CLK_M4_RITIMER_STAT: RUN Mask  */
#define CCU1_CLK_M4_RITIMER_STAT_AUTO_Pos                     1                                                         /*!< CCU1 CLK_M4_RITIMER_STAT: AUTO Position */
#define CCU1_CLK_M4_RITIMER_STAT_AUTO_Msk                     (0x01UL << CCU1_CLK_M4_RITIMER_STAT_AUTO_Pos)             /*!< CCU1 CLK_M4_RITIMER_STAT: AUTO Mask */
#define CCU1_CLK_M4_RITIMER_STAT_WAKEUP_Pos                   2                                                         /*!< CCU1 CLK_M4_RITIMER_STAT: WAKEUP Position */
#define CCU1_CLK_M4_RITIMER_STAT_WAKEUP_Msk                   (0x01UL << CCU1_CLK_M4_RITIMER_STAT_WAKEUP_Pos)           /*!< CCU1 CLK_M4_RITIMER_STAT: WAKEUP Mask */

// ---------------------------------  CCU1_CLK_M4_USART2_CFG  -------------------------------------
#define CCU1_CLK_M4_USART2_CFG_RUN_Pos                        0                                                         /*!< CCU1 CLK_M4_USART2_CFG: RUN Position */
#define CCU1_CLK_M4_USART2_CFG_RUN_Msk                        (0x01UL << CCU1_CLK_M4_USART2_CFG_RUN_Pos)                /*!< CCU1 CLK_M4_USART2_CFG: RUN Mask    */
#define CCU1_CLK_M4_USART2_CFG_AUTO_Pos                       1                                                         /*!< CCU1 CLK_M4_USART2_CFG: AUTO Position */
#define CCU1_CLK_M4_USART2_CFG_AUTO_Msk                       (0x01UL << CCU1_CLK_M4_USART2_CFG_AUTO_Pos)               /*!< CCU1 CLK_M4_USART2_CFG: AUTO Mask   */
#define CCU1_CLK_M4_USART2_CFG_WAKEUP_Pos                     2                                                         /*!< CCU1 CLK_M4_USART2_CFG: WAKEUP Position */
#define CCU1_CLK_M4_USART2_CFG_WAKEUP_Msk                     (0x01UL << CCU1_CLK_M4_USART2_CFG_WAKEUP_Pos)             /*!< CCU1 CLK_M4_USART2_CFG: WAKEUP Mask */

// ---------------------------------  CCU1_CLK_M4_USART2_STAT  ------------------------------------
#define CCU1_CLK_M4_USART2_STAT_RUN_Pos                       0                                                         /*!< CCU1 CLK_M4_USART2_STAT: RUN Position */
#define CCU1_CLK_M4_USART2_STAT_RUN_Msk                       (0x01UL << CCU1_CLK_M4_USART2_STAT_RUN_Pos)               /*!< CCU1 CLK_M4_USART2_STAT: RUN Mask   */
#define CCU1_CLK_M4_USART2_STAT_AUTO_Pos                      1                                                         /*!< CCU1 CLK_M4_USART2_STAT: AUTO Position */
#define CCU1_CLK_M4_USART2_STAT_AUTO_Msk                      (0x01UL << CCU1_CLK_M4_USART2_STAT_AUTO_Pos)              /*!< CCU1 CLK_M4_USART2_STAT: AUTO Mask  */
#define CCU1_CLK_M4_USART2_STAT_WAKEUP_Pos                    2                                                         /*!< CCU1 CLK_M4_USART2_STAT: WAKEUP Position */
#define CCU1_CLK_M4_USART2_STAT_WAKEUP_Msk                    (0x01UL << CCU1_CLK_M4_USART2_STAT_WAKEUP_Pos)            /*!< CCU1 CLK_M4_USART2_STAT: WAKEUP Mask */

// ---------------------------------  CCU1_CLK_M4_USART3_CFG  -------------------------------------
#define CCU1_CLK_M4_USART3_CFG_RUN_Pos                        0                                                         /*!< CCU1 CLK_M4_USART3_CFG: RUN Position */
#define CCU1_CLK_M4_USART3_CFG_RUN_Msk                        (0x01UL << CCU1_CLK_M4_USART3_CFG_RUN_Pos)                /*!< CCU1 CLK_M4_USART3_CFG: RUN Mask    */
#define CCU1_CLK_M4_USART3_CFG_AUTO_Pos                       1                                                         /*!< CCU1 CLK_M4_USART3_CFG: AUTO Position */
#define CCU1_CLK_M4_USART3_CFG_AUTO_Msk                       (0x01UL << CCU1_CLK_M4_USART3_CFG_AUTO_Pos)               /*!< CCU1 CLK_M4_USART3_CFG: AUTO Mask   */
#define CCU1_CLK_M4_USART3_CFG_WAKEUP_Pos                     2                                                         /*!< CCU1 CLK_M4_USART3_CFG: WAKEUP Position */
#define CCU1_CLK_M4_USART3_CFG_WAKEUP_Msk                     (0x01UL << CCU1_CLK_M4_USART3_CFG_WAKEUP_Pos)             /*!< CCU1 CLK_M4_USART3_CFG: WAKEUP Mask */

// ---------------------------------  CCU1_CLK_M4_USART3_STAT  ------------------------------------
#define CCU1_CLK_M4_USART3_STAT_RUN_Pos                       0                                                         /*!< CCU1 CLK_M4_USART3_STAT: RUN Position */
#define CCU1_CLK_M4_USART3_STAT_RUN_Msk                       (0x01UL << CCU1_CLK_M4_USART3_STAT_RUN_Pos)               /*!< CCU1 CLK_M4_USART3_STAT: RUN Mask   */
#define CCU1_CLK_M4_USART3_STAT_AUTO_Pos                      1                                                         /*!< CCU1 CLK_M4_USART3_STAT: AUTO Position */
#define CCU1_CLK_M4_USART3_STAT_AUTO_Msk                      (0x01UL << CCU1_CLK_M4_USART3_STAT_AUTO_Pos)              /*!< CCU1 CLK_M4_USART3_STAT: AUTO Mask  */
#define CCU1_CLK_M4_USART3_STAT_WAKEUP_Pos                    2                                                         /*!< CCU1 CLK_M4_USART3_STAT: WAKEUP Position */
#define CCU1_CLK_M4_USART3_STAT_WAKEUP_Msk                    (0x01UL << CCU1_CLK_M4_USART3_STAT_WAKEUP_Pos)            /*!< CCU1 CLK_M4_USART3_STAT: WAKEUP Mask */

// ---------------------------------  CCU1_CLK_M4_TIMER2_CFG  -------------------------------------
#define CCU1_CLK_M4_TIMER2_CFG_RUN_Pos                        0                                                         /*!< CCU1 CLK_M4_TIMER2_CFG: RUN Position */
#define CCU1_CLK_M4_TIMER2_CFG_RUN_Msk                        (0x01UL << CCU1_CLK_M4_TIMER2_CFG_RUN_Pos)                /*!< CCU1 CLK_M4_TIMER2_CFG: RUN Mask    */
#define CCU1_CLK_M4_TIMER2_CFG_AUTO_Pos                       1                                                         /*!< CCU1 CLK_M4_TIMER2_CFG: AUTO Position */
#define CCU1_CLK_M4_TIMER2_CFG_AUTO_Msk                       (0x01UL << CCU1_CLK_M4_TIMER2_CFG_AUTO_Pos)               /*!< CCU1 CLK_M4_TIMER2_CFG: AUTO Mask   */
#define CCU1_CLK_M4_TIMER2_CFG_WAKEUP_Pos                     2                                                         /*!< CCU1 CLK_M4_TIMER2_CFG: WAKEUP Position */
#define CCU1_CLK_M4_TIMER2_CFG_WAKEUP_Msk                     (0x01UL << CCU1_CLK_M4_TIMER2_CFG_WAKEUP_Pos)             /*!< CCU1 CLK_M4_TIMER2_CFG: WAKEUP Mask */

// ---------------------------------  CCU1_CLK_M4_TIMER2_STAT  ------------------------------------
#define CCU1_CLK_M4_TIMER2_STAT_RUN_Pos                       0                                                         /*!< CCU1 CLK_M4_TIMER2_STAT: RUN Position */
#define CCU1_CLK_M4_TIMER2_STAT_RUN_Msk                       (0x01UL << CCU1_CLK_M4_TIMER2_STAT_RUN_Pos)               /*!< CCU1 CLK_M4_TIMER2_STAT: RUN Mask   */
#define CCU1_CLK_M4_TIMER2_STAT_AUTO_Pos                      1                                                         /*!< CCU1 CLK_M4_TIMER2_STAT: AUTO Position */
#define CCU1_CLK_M4_TIMER2_STAT_AUTO_Msk                      (0x01UL << CCU1_CLK_M4_TIMER2_STAT_AUTO_Pos)              /*!< CCU1 CLK_M4_TIMER2_STAT: AUTO Mask  */
#define CCU1_CLK_M4_TIMER2_STAT_WAKEUP_Pos                    2                                                         /*!< CCU1 CLK_M4_TIMER2_STAT: WAKEUP Position */
#define CCU1_CLK_M4_TIMER2_STAT_WAKEUP_Msk                    (0x01UL << CCU1_CLK_M4_TIMER2_STAT_WAKEUP_Pos)            /*!< CCU1 CLK_M4_TIMER2_STAT: WAKEUP Mask */

// ---------------------------------  CCU1_CLK_M4_TIMER3_CFG  -------------------------------------
#define CCU1_CLK_M4_TIMER3_CFG_RUN_Pos                        0                                                         /*!< CCU1 CLK_M4_TIMER3_CFG: RUN Position */
#define CCU1_CLK_M4_TIMER3_CFG_RUN_Msk                        (0x01UL << CCU1_CLK_M4_TIMER3_CFG_RUN_Pos)                /*!< CCU1 CLK_M4_TIMER3_CFG: RUN Mask    */
#define CCU1_CLK_M4_TIMER3_CFG_AUTO_Pos                       1                                                         /*!< CCU1 CLK_M4_TIMER3_CFG: AUTO Position */
#define CCU1_CLK_M4_TIMER3_CFG_AUTO_Msk                       (0x01UL << CCU1_CLK_M4_TIMER3_CFG_AUTO_Pos)               /*!< CCU1 CLK_M4_TIMER3_CFG: AUTO Mask   */
#define CCU1_CLK_M4_TIMER3_CFG_WAKEUP_Pos                     2                                                         /*!< CCU1 CLK_M4_TIMER3_CFG: WAKEUP Position */
#define CCU1_CLK_M4_TIMER3_CFG_WAKEUP_Msk                     (0x01UL << CCU1_CLK_M4_TIMER3_CFG_WAKEUP_Pos)             /*!< CCU1 CLK_M4_TIMER3_CFG: WAKEUP Mask */

// ---------------------------------  CCU1_CLK_M4_TIMER3_STAT  ------------------------------------
#define CCU1_CLK_M4_TIMER3_STAT_RUN_Pos                       0                                                         /*!< CCU1 CLK_M4_TIMER3_STAT: RUN Position */
#define CCU1_CLK_M4_TIMER3_STAT_RUN_Msk                       (0x01UL << CCU1_CLK_M4_TIMER3_STAT_RUN_Pos)               /*!< CCU1 CLK_M4_TIMER3_STAT: RUN Mask   */
#define CCU1_CLK_M4_TIMER3_STAT_AUTO_Pos                      1                                                         /*!< CCU1 CLK_M4_TIMER3_STAT: AUTO Position */
#define CCU1_CLK_M4_TIMER3_STAT_AUTO_Msk                      (0x01UL << CCU1_CLK_M4_TIMER3_STAT_AUTO_Pos)              /*!< CCU1 CLK_M4_TIMER3_STAT: AUTO Mask  */
#define CCU1_CLK_M4_TIMER3_STAT_WAKEUP_Pos                    2                                                         /*!< CCU1 CLK_M4_TIMER3_STAT: WAKEUP Position */
#define CCU1_CLK_M4_TIMER3_STAT_WAKEUP_Msk                    (0x01UL << CCU1_CLK_M4_TIMER3_STAT_WAKEUP_Pos)            /*!< CCU1 CLK_M4_TIMER3_STAT: WAKEUP Mask */

// ----------------------------------  CCU1_CLK_M4_SSP1_CFG  --------------------------------------
#define CCU1_CLK_M4_SSP1_CFG_RUN_Pos                          0                                                         /*!< CCU1 CLK_M4_SSP1_CFG: RUN Position  */
#define CCU1_CLK_M4_SSP1_CFG_RUN_Msk                          (0x01UL << CCU1_CLK_M4_SSP1_CFG_RUN_Pos)                  /*!< CCU1 CLK_M4_SSP1_CFG: RUN Mask      */
#define CCU1_CLK_M4_SSP1_CFG_AUTO_Pos                         1                                                         /*!< CCU1 CLK_M4_SSP1_CFG: AUTO Position */
#define CCU1_CLK_M4_SSP1_CFG_AUTO_Msk                         (0x01UL << CCU1_CLK_M4_SSP1_CFG_AUTO_Pos)                 /*!< CCU1 CLK_M4_SSP1_CFG: AUTO Mask     */
#define CCU1_CLK_M4_SSP1_CFG_WAKEUP_Pos                       2                                                         /*!< CCU1 CLK_M4_SSP1_CFG: WAKEUP Position */
#define CCU1_CLK_M4_SSP1_CFG_WAKEUP_Msk                       (0x01UL << CCU1_CLK_M4_SSP1_CFG_WAKEUP_Pos)               /*!< CCU1 CLK_M4_SSP1_CFG: WAKEUP Mask   */

// ----------------------------------  CCU1_CLK_M4_SSP1_STAT  -------------------------------------
#define CCU1_CLK_M4_SSP1_STAT_RUN_Pos                         0                                                         /*!< CCU1 CLK_M4_SSP1_STAT: RUN Position */
#define CCU1_CLK_M4_SSP1_STAT_RUN_Msk                         (0x01UL << CCU1_CLK_M4_SSP1_STAT_RUN_Pos)                 /*!< CCU1 CLK_M4_SSP1_STAT: RUN Mask     */
#define CCU1_CLK_M4_SSP1_STAT_AUTO_Pos                        1                                                         /*!< CCU1 CLK_M4_SSP1_STAT: AUTO Position */
#define CCU1_CLK_M4_SSP1_STAT_AUTO_Msk                        (0x01UL << CCU1_CLK_M4_SSP1_STAT_AUTO_Pos)                /*!< CCU1 CLK_M4_SSP1_STAT: AUTO Mask    */
#define CCU1_CLK_M4_SSP1_STAT_WAKEUP_Pos                      2                                                         /*!< CCU1 CLK_M4_SSP1_STAT: WAKEUP Position */
#define CCU1_CLK_M4_SSP1_STAT_WAKEUP_Msk                      (0x01UL << CCU1_CLK_M4_SSP1_STAT_WAKEUP_Pos)              /*!< CCU1 CLK_M4_SSP1_STAT: WAKEUP Mask  */

// -----------------------------------  CCU1_CLK_M4_QEI_CFG  --------------------------------------
#define CCU1_CLK_M4_QEI_CFG_RUN_Pos                           0                                                         /*!< CCU1 CLK_M4_QEI_CFG: RUN Position   */
#define CCU1_CLK_M4_QEI_CFG_RUN_Msk                           (0x01UL << CCU1_CLK_M4_QEI_CFG_RUN_Pos)                   /*!< CCU1 CLK_M4_QEI_CFG: RUN Mask       */
#define CCU1_CLK_M4_QEI_CFG_AUTO_Pos                          1                                                         /*!< CCU1 CLK_M4_QEI_CFG: AUTO Position  */
#define CCU1_CLK_M4_QEI_CFG_AUTO_Msk                          (0x01UL << CCU1_CLK_M4_QEI_CFG_AUTO_Pos)                  /*!< CCU1 CLK_M4_QEI_CFG: AUTO Mask      */
#define CCU1_CLK_M4_QEI_CFG_WAKEUP_Pos                        2                                                         /*!< CCU1 CLK_M4_QEI_CFG: WAKEUP Position */
#define CCU1_CLK_M4_QEI_CFG_WAKEUP_Msk                        (0x01UL << CCU1_CLK_M4_QEI_CFG_WAKEUP_Pos)                /*!< CCU1 CLK_M4_QEI_CFG: WAKEUP Mask    */

// ----------------------------------  CCU1_CLK_M4_QEI_STAT  --------------------------------------
#define CCU1_CLK_M4_QEI_STAT_RUN_Pos                          0                                                         /*!< CCU1 CLK_M4_QEI_STAT: RUN Position  */
#define CCU1_CLK_M4_QEI_STAT_RUN_Msk                          (0x01UL << CCU1_CLK_M4_QEI_STAT_RUN_Pos)                  /*!< CCU1 CLK_M4_QEI_STAT: RUN Mask      */
#define CCU1_CLK_M4_QEI_STAT_AUTO_Pos                         1                                                         /*!< CCU1 CLK_M4_QEI_STAT: AUTO Position */
#define CCU1_CLK_M4_QEI_STAT_AUTO_Msk                         (0x01UL << CCU1_CLK_M4_QEI_STAT_AUTO_Pos)                 /*!< CCU1 CLK_M4_QEI_STAT: AUTO Mask     */
#define CCU1_CLK_M4_QEI_STAT_WAKEUP_Pos                       2                                                         /*!< CCU1 CLK_M4_QEI_STAT: WAKEUP Position */
#define CCU1_CLK_M4_QEI_STAT_WAKEUP_Msk                       (0x01UL << CCU1_CLK_M4_QEI_STAT_WAKEUP_Pos)               /*!< CCU1 CLK_M4_QEI_STAT: WAKEUP Mask   */

// ---------------------------------  CCU1_CLK_PERIPH_BUS_CFG  ------------------------------------
#define CCU1_CLK_PERIPH_BUS_CFG_RUN_Pos                       0                                                         /*!< CCU1 CLK_PERIPH_BUS_CFG: RUN Position */
#define CCU1_CLK_PERIPH_BUS_CFG_RUN_Msk                       (0x01UL << CCU1_CLK_PERIPH_BUS_CFG_RUN_Pos)               /*!< CCU1 CLK_PERIPH_BUS_CFG: RUN Mask   */
#define CCU1_CLK_PERIPH_BUS_CFG_AUTO_Pos                      1                                                         /*!< CCU1 CLK_PERIPH_BUS_CFG: AUTO Position */
#define CCU1_CLK_PERIPH_BUS_CFG_AUTO_Msk                      (0x01UL << CCU1_CLK_PERIPH_BUS_CFG_AUTO_Pos)              /*!< CCU1 CLK_PERIPH_BUS_CFG: AUTO Mask  */
#define CCU1_CLK_PERIPH_BUS_CFG_WAKEUP_Pos                    2                                                         /*!< CCU1 CLK_PERIPH_BUS_CFG: WAKEUP Position */
#define CCU1_CLK_PERIPH_BUS_CFG_WAKEUP_Msk                    (0x01UL << CCU1_CLK_PERIPH_BUS_CFG_WAKEUP_Pos)            /*!< CCU1 CLK_PERIPH_BUS_CFG: WAKEUP Mask */

// --------------------------------  CCU1_CLK_PERIPH_BUS_STAT  ------------------------------------
#define CCU1_CLK_PERIPH_BUS_STAT_RUN_Pos                      0                                                         /*!< CCU1 CLK_PERIPH_BUS_STAT: RUN Position */
#define CCU1_CLK_PERIPH_BUS_STAT_RUN_Msk                      (0x01UL << CCU1_CLK_PERIPH_BUS_STAT_RUN_Pos)              /*!< CCU1 CLK_PERIPH_BUS_STAT: RUN Mask  */
#define CCU1_CLK_PERIPH_BUS_STAT_AUTO_Pos                     1                                                         /*!< CCU1 CLK_PERIPH_BUS_STAT: AUTO Position */
#define CCU1_CLK_PERIPH_BUS_STAT_AUTO_Msk                     (0x01UL << CCU1_CLK_PERIPH_BUS_STAT_AUTO_Pos)             /*!< CCU1 CLK_PERIPH_BUS_STAT: AUTO Mask */
#define CCU1_CLK_PERIPH_BUS_STAT_WAKEUP_Pos                   2                                                         /*!< CCU1 CLK_PERIPH_BUS_STAT: WAKEUP Position */
#define CCU1_CLK_PERIPH_BUS_STAT_WAKEUP_Msk                   (0x01UL << CCU1_CLK_PERIPH_BUS_STAT_WAKEUP_Pos)           /*!< CCU1 CLK_PERIPH_BUS_STAT: WAKEUP Mask */

// --------------------------------  CCU1_CLK_PERIPH_CORE_CFG  ------------------------------------
#define CCU1_CLK_PERIPH_CORE_CFG_RUN_Pos                      0                                                         /*!< CCU1 CLK_PERIPH_CORE_CFG: RUN Position */
#define CCU1_CLK_PERIPH_CORE_CFG_RUN_Msk                      (0x01UL << CCU1_CLK_PERIPH_CORE_CFG_RUN_Pos)              /*!< CCU1 CLK_PERIPH_CORE_CFG: RUN Mask  */
#define CCU1_CLK_PERIPH_CORE_CFG_AUTO_Pos                     1                                                         /*!< CCU1 CLK_PERIPH_CORE_CFG: AUTO Position */
#define CCU1_CLK_PERIPH_CORE_CFG_AUTO_Msk                     (0x01UL << CCU1_CLK_PERIPH_CORE_CFG_AUTO_Pos)             /*!< CCU1 CLK_PERIPH_CORE_CFG: AUTO Mask */
#define CCU1_CLK_PERIPH_CORE_CFG_WAKEUP_Pos                   2                                                         /*!< CCU1 CLK_PERIPH_CORE_CFG: WAKEUP Position */
#define CCU1_CLK_PERIPH_CORE_CFG_WAKEUP_Msk                   (0x01UL << CCU1_CLK_PERIPH_CORE_CFG_WAKEUP_Pos)           /*!< CCU1 CLK_PERIPH_CORE_CFG: WAKEUP Mask */

// --------------------------------  CCU1_CLK_PERIPH_CORE_STAT  -----------------------------------
#define CCU1_CLK_PERIPH_CORE_STAT_RUN_Pos                     0                                                         /*!< CCU1 CLK_PERIPH_CORE_STAT: RUN Position */
#define CCU1_CLK_PERIPH_CORE_STAT_RUN_Msk                     (0x01UL << CCU1_CLK_PERIPH_CORE_STAT_RUN_Pos)             /*!< CCU1 CLK_PERIPH_CORE_STAT: RUN Mask */
#define CCU1_CLK_PERIPH_CORE_STAT_AUTO_Pos                    1                                                         /*!< CCU1 CLK_PERIPH_CORE_STAT: AUTO Position */
#define CCU1_CLK_PERIPH_CORE_STAT_AUTO_Msk                    (0x01UL << CCU1_CLK_PERIPH_CORE_STAT_AUTO_Pos)            /*!< CCU1 CLK_PERIPH_CORE_STAT: AUTO Mask */
#define CCU1_CLK_PERIPH_CORE_STAT_WAKEUP_Pos                  2                                                         /*!< CCU1 CLK_PERIPH_CORE_STAT: WAKEUP Position */
#define CCU1_CLK_PERIPH_CORE_STAT_WAKEUP_Msk                  (0x01UL << CCU1_CLK_PERIPH_CORE_STAT_WAKEUP_Pos)          /*!< CCU1 CLK_PERIPH_CORE_STAT: WAKEUP Mask */

// --------------------------------  CCU1_CLK_PERIPH_SGPIO_CFG  -----------------------------------
#define CCU1_CLK_PERIPH_SGPIO_CFG_RUN_Pos                     0                                                         /*!< CCU1 CLK_PERIPH_SGPIO_CFG: RUN Position */
#define CCU1_CLK_PERIPH_SGPIO_CFG_RUN_Msk                     (0x01UL << CCU1_CLK_PERIPH_SGPIO_CFG_RUN_Pos)             /*!< CCU1 CLK_PERIPH_SGPIO_CFG: RUN Mask */
#define CCU1_CLK_PERIPH_SGPIO_CFG_AUTO_Pos                    1                                                         /*!< CCU1 CLK_PERIPH_SGPIO_CFG: AUTO Position */
#define CCU1_CLK_PERIPH_SGPIO_CFG_AUTO_Msk                    (0x01UL << CCU1_CLK_PERIPH_SGPIO_CFG_AUTO_Pos)            /*!< CCU1 CLK_PERIPH_SGPIO_CFG: AUTO Mask */
#define CCU1_CLK_PERIPH_SGPIO_CFG_WAKEUP_Pos                  2                                                         /*!< CCU1 CLK_PERIPH_SGPIO_CFG: WAKEUP Position */
#define CCU1_CLK_PERIPH_SGPIO_CFG_WAKEUP_Msk                  (0x01UL << CCU1_CLK_PERIPH_SGPIO_CFG_WAKEUP_Pos)          /*!< CCU1 CLK_PERIPH_SGPIO_CFG: WAKEUP Mask */

// -------------------------------  CCU1_CLK_PERIPH_SGPIO_STAT  -----------------------------------
#define CCU1_CLK_PERIPH_SGPIO_STAT_RUN_Pos                    0                                                         /*!< CCU1 CLK_PERIPH_SGPIO_STAT: RUN Position */
#define CCU1_CLK_PERIPH_SGPIO_STAT_RUN_Msk                    (0x01UL << CCU1_CLK_PERIPH_SGPIO_STAT_RUN_Pos)            /*!< CCU1 CLK_PERIPH_SGPIO_STAT: RUN Mask */
#define CCU1_CLK_PERIPH_SGPIO_STAT_AUTO_Pos                   1                                                         /*!< CCU1 CLK_PERIPH_SGPIO_STAT: AUTO Position */
#define CCU1_CLK_PERIPH_SGPIO_STAT_AUTO_Msk                   (0x01UL << CCU1_CLK_PERIPH_SGPIO_STAT_AUTO_Pos)           /*!< CCU1 CLK_PERIPH_SGPIO_STAT: AUTO Mask */
#define CCU1_CLK_PERIPH_SGPIO_STAT_WAKEUP_Pos                 2                                                         /*!< CCU1 CLK_PERIPH_SGPIO_STAT: WAKEUP Position */
#define CCU1_CLK_PERIPH_SGPIO_STAT_WAKEUP_Msk                 (0x01UL << CCU1_CLK_PERIPH_SGPIO_STAT_WAKEUP_Pos)         /*!< CCU1 CLK_PERIPH_SGPIO_STAT: WAKEUP Mask */

// ------------------------------------  CCU1_CLK_USB0_CFG  ---------------------------------------
#define CCU1_CLK_USB0_CFG_RUN_Pos                             0                                                         /*!< CCU1 CLK_USB0_CFG: RUN Position     */
#define CCU1_CLK_USB0_CFG_RUN_Msk                             (0x01UL << CCU1_CLK_USB0_CFG_RUN_Pos)                     /*!< CCU1 CLK_USB0_CFG: RUN Mask         */
#define CCU1_CLK_USB0_CFG_AUTO_Pos                            1                                                         /*!< CCU1 CLK_USB0_CFG: AUTO Position    */
#define CCU1_CLK_USB0_CFG_AUTO_Msk                            (0x01UL << CCU1_CLK_USB0_CFG_AUTO_Pos)                    /*!< CCU1 CLK_USB0_CFG: AUTO Mask        */
#define CCU1_CLK_USB0_CFG_WAKEUP_Pos                          2                                                         /*!< CCU1 CLK_USB0_CFG: WAKEUP Position  */
#define CCU1_CLK_USB0_CFG_WAKEUP_Msk                          (0x01UL << CCU1_CLK_USB0_CFG_WAKEUP_Pos)                  /*!< CCU1 CLK_USB0_CFG: WAKEUP Mask      */

// -----------------------------------  CCU1_CLK_USB0_STAT  ---------------------------------------
#define CCU1_CLK_USB0_STAT_RUN_Pos                            0                                                         /*!< CCU1 CLK_USB0_STAT: RUN Position    */
#define CCU1_CLK_USB0_STAT_RUN_Msk                            (0x01UL << CCU1_CLK_USB0_STAT_RUN_Pos)                    /*!< CCU1 CLK_USB0_STAT: RUN Mask        */
#define CCU1_CLK_USB0_STAT_AUTO_Pos                           1                                                         /*!< CCU1 CLK_USB0_STAT: AUTO Position   */
#define CCU1_CLK_USB0_STAT_AUTO_Msk                           (0x01UL << CCU1_CLK_USB0_STAT_AUTO_Pos)                   /*!< CCU1 CLK_USB0_STAT: AUTO Mask       */
#define CCU1_CLK_USB0_STAT_WAKEUP_Pos                         2                                                         /*!< CCU1 CLK_USB0_STAT: WAKEUP Position */
#define CCU1_CLK_USB0_STAT_WAKEUP_Msk                         (0x01UL << CCU1_CLK_USB0_STAT_WAKEUP_Pos)                 /*!< CCU1 CLK_USB0_STAT: WAKEUP Mask     */

// ------------------------------------  CCU1_CLK_USB1_CFG  ---------------------------------------
#define CCU1_CLK_USB1_CFG_RUN_Pos                             0                                                         /*!< CCU1 CLK_USB1_CFG: RUN Position     */
#define CCU1_CLK_USB1_CFG_RUN_Msk                             (0x01UL << CCU1_CLK_USB1_CFG_RUN_Pos)                     /*!< CCU1 CLK_USB1_CFG: RUN Mask         */
#define CCU1_CLK_USB1_CFG_AUTO_Pos                            1                                                         /*!< CCU1 CLK_USB1_CFG: AUTO Position    */
#define CCU1_CLK_USB1_CFG_AUTO_Msk                            (0x01UL << CCU1_CLK_USB1_CFG_AUTO_Pos)                    /*!< CCU1 CLK_USB1_CFG: AUTO Mask        */
#define CCU1_CLK_USB1_CFG_WAKEUP_Pos                          2                                                         /*!< CCU1 CLK_USB1_CFG: WAKEUP Position  */
#define CCU1_CLK_USB1_CFG_WAKEUP_Msk                          (0x01UL << CCU1_CLK_USB1_CFG_WAKEUP_Pos)                  /*!< CCU1 CLK_USB1_CFG: WAKEUP Mask      */

// -----------------------------------  CCU1_CLK_USB1_STAT  ---------------------------------------
#define CCU1_CLK_USB1_STAT_RUN_Pos                            0                                                         /*!< CCU1 CLK_USB1_STAT: RUN Position    */
#define CCU1_CLK_USB1_STAT_RUN_Msk                            (0x01UL << CCU1_CLK_USB1_STAT_RUN_Pos)                    /*!< CCU1 CLK_USB1_STAT: RUN Mask        */
#define CCU1_CLK_USB1_STAT_AUTO_Pos                           1                                                         /*!< CCU1 CLK_USB1_STAT: AUTO Position   */
#define CCU1_CLK_USB1_STAT_AUTO_Msk                           (0x01UL << CCU1_CLK_USB1_STAT_AUTO_Pos)                   /*!< CCU1 CLK_USB1_STAT: AUTO Mask       */
#define CCU1_CLK_USB1_STAT_WAKEUP_Pos                         2                                                         /*!< CCU1 CLK_USB1_STAT: WAKEUP Position */
#define CCU1_CLK_USB1_STAT_WAKEUP_Msk                         (0x01UL << CCU1_CLK_USB1_STAT_WAKEUP_Pos)                 /*!< CCU1 CLK_USB1_STAT: WAKEUP Mask     */

// ------------------------------------  CCU1_CLK_SPI_CFG  ----------------------------------------
#define CCU1_CLK_SPI_CFG_RUN_Pos                              0                                                         /*!< CCU1 CLK_SPI_CFG: RUN Position      */
#define CCU1_CLK_SPI_CFG_RUN_Msk                              (0x01UL << CCU1_CLK_SPI_CFG_RUN_Pos)                      /*!< CCU1 CLK_SPI_CFG: RUN Mask          */
#define CCU1_CLK_SPI_CFG_AUTO_Pos                             1                                                         /*!< CCU1 CLK_SPI_CFG: AUTO Position     */
#define CCU1_CLK_SPI_CFG_AUTO_Msk                             (0x01UL << CCU1_CLK_SPI_CFG_AUTO_Pos)                     /*!< CCU1 CLK_SPI_CFG: AUTO Mask         */
#define CCU1_CLK_SPI_CFG_WAKEUP_Pos                           2                                                         /*!< CCU1 CLK_SPI_CFG: WAKEUP Position   */
#define CCU1_CLK_SPI_CFG_WAKEUP_Msk                           (0x01UL << CCU1_CLK_SPI_CFG_WAKEUP_Pos)                   /*!< CCU1 CLK_SPI_CFG: WAKEUP Mask       */

// ------------------------------------  CCU1_CLK_SPI_STAT  ---------------------------------------
#define CCU1_CLK_SPI_STAT_RUN_Pos                             0                                                         /*!< CCU1 CLK_SPI_STAT: RUN Position     */
#define CCU1_CLK_SPI_STAT_RUN_Msk                             (0x01UL << CCU1_CLK_SPI_STAT_RUN_Pos)                     /*!< CCU1 CLK_SPI_STAT: RUN Mask         */
#define CCU1_CLK_SPI_STAT_AUTO_Pos                            1                                                         /*!< CCU1 CLK_SPI_STAT: AUTO Position    */
#define CCU1_CLK_SPI_STAT_AUTO_Msk                            (0x01UL << CCU1_CLK_SPI_STAT_AUTO_Pos)                    /*!< CCU1 CLK_SPI_STAT: AUTO Mask        */
#define CCU1_CLK_SPI_STAT_WAKEUP_Pos                          2                                                         /*!< CCU1 CLK_SPI_STAT: WAKEUP Position  */
#define CCU1_CLK_SPI_STAT_WAKEUP_Msk                          (0x01UL << CCU1_CLK_SPI_STAT_WAKEUP_Pos)                  /*!< CCU1 CLK_SPI_STAT: WAKEUP Mask      */

// ------------------------------------  CCU1_CLK_VADC_CFG  ---------------------------------------
#define CCU1_CLK_VADC_CFG_RUN_Pos                             0                                                         /*!< CCU1 CLK_VADC_CFG: RUN Position     */
#define CCU1_CLK_VADC_CFG_RUN_Msk                             (0x01UL << CCU1_CLK_VADC_CFG_RUN_Pos)                     /*!< CCU1 CLK_VADC_CFG: RUN Mask         */
#define CCU1_CLK_VADC_CFG_AUTO_Pos                            1                                                         /*!< CCU1 CLK_VADC_CFG: AUTO Position    */
#define CCU1_CLK_VADC_CFG_AUTO_Msk                            (0x01UL << CCU1_CLK_VADC_CFG_AUTO_Pos)                    /*!< CCU1 CLK_VADC_CFG: AUTO Mask        */
#define CCU1_CLK_VADC_CFG_WAKEUP_Pos                          2                                                         /*!< CCU1 CLK_VADC_CFG: WAKEUP Position  */
#define CCU1_CLK_VADC_CFG_WAKEUP_Msk                          (0x01UL << CCU1_CLK_VADC_CFG_WAKEUP_Pos)                  /*!< CCU1 CLK_VADC_CFG: WAKEUP Mask      */

// -----------------------------------  CCU1_CLK_VADC_STAT  ---------------------------------------
#define CCU1_CLK_VADC_STAT_RUN_Pos                            0                                                         /*!< CCU1 CLK_VADC_STAT: RUN Position    */
#define CCU1_CLK_VADC_STAT_RUN_Msk                            (0x01UL << CCU1_CLK_VADC_STAT_RUN_Pos)                    /*!< CCU1 CLK_VADC_STAT: RUN Mask        */
#define CCU1_CLK_VADC_STAT_AUTO_Pos                           1                                                         /*!< CCU1 CLK_VADC_STAT: AUTO Position   */
#define CCU1_CLK_VADC_STAT_AUTO_Msk                           (0x01UL << CCU1_CLK_VADC_STAT_AUTO_Pos)                   /*!< CCU1 CLK_VADC_STAT: AUTO Mask       */
#define CCU1_CLK_VADC_STAT_WAKEUP_Pos                         2                                                         /*!< CCU1 CLK_VADC_STAT: WAKEUP Position */
#define CCU1_CLK_VADC_STAT_WAKEUP_Msk                         (0x01UL << CCU1_CLK_VADC_STAT_WAKEUP_Pos)                 /*!< CCU1 CLK_VADC_STAT: WAKEUP Mask     */


// ------------------------------------------------------------------------------------------------
// -----                                 CCU2 Position & Mask                                 -----
// ------------------------------------------------------------------------------------------------


// -----------------------------------------  CCU2_PM  --------------------------------------------
#define CCU2_PM_PD_Pos                                        0                                                         /*!< CCU2 PM: PD Position                */
#define CCU2_PM_PD_Msk                                        (0x01UL << CCU2_PM_PD_Pos)                                /*!< CCU2 PM: PD Mask                    */

// -------------------------------------  CCU2_BASE_STAT  -----------------------------------------
#define CCU2_BASE_STAT_BASE_UART3_CLK_Pos                     1                                                         /*!< CCU2 BASE_STAT: BASE_UART3_CLK Position */
#define CCU2_BASE_STAT_BASE_UART3_CLK_Msk                     (0x01UL << CCU2_BASE_STAT_BASE_UART3_CLK_Pos)             /*!< CCU2 BASE_STAT: BASE_UART3_CLK Mask */
#define CCU2_BASE_STAT_BASE_UART2_CLK_Pos                     2                                                         /*!< CCU2 BASE_STAT: BASE_UART2_CLK Position */
#define CCU2_BASE_STAT_BASE_UART2_CLK_Msk                     (0x01UL << CCU2_BASE_STAT_BASE_UART2_CLK_Pos)             /*!< CCU2 BASE_STAT: BASE_UART2_CLK Mask */
#define CCU2_BASE_STAT_BASE_UART1_CLK_Pos                     3                                                         /*!< CCU2 BASE_STAT: BASE_UART1_CLK Position */
#define CCU2_BASE_STAT_BASE_UART1_CLK_Msk                     (0x01UL << CCU2_BASE_STAT_BASE_UART1_CLK_Pos)             /*!< CCU2 BASE_STAT: BASE_UART1_CLK Mask */
#define CCU2_BASE_STAT_BASE_UART0_CLK_Pos                     4                                                         /*!< CCU2 BASE_STAT: BASE_UART0_CLK Position */
#define CCU2_BASE_STAT_BASE_UART0_CLK_Msk                     (0x01UL << CCU2_BASE_STAT_BASE_UART0_CLK_Pos)             /*!< CCU2 BASE_STAT: BASE_UART0_CLK Mask */
#define CCU2_BASE_STAT_BASE_SSP1_CLK_Pos                      5                                                         /*!< CCU2 BASE_STAT: BASE_SSP1_CLK Position */
#define CCU2_BASE_STAT_BASE_SSP1_CLK_Msk                      (0x01UL << CCU2_BASE_STAT_BASE_SSP1_CLK_Pos)              /*!< CCU2 BASE_STAT: BASE_SSP1_CLK Mask  */
#define CCU2_BASE_STAT_BASE_SSP0_CLK_Pos                      6                                                         /*!< CCU2 BASE_STAT: BASE_SSP0_CLK Position */
#define CCU2_BASE_STAT_BASE_SSP0_CLK_Msk                      (0x01UL << CCU2_BASE_STAT_BASE_SSP0_CLK_Pos)              /*!< CCU2 BASE_STAT: BASE_SSP0_CLK Mask  */

// ------------------------------------  CCU2_CLK_APLL_CFG  ---------------------------------------
#define CCU2_CLK_APLL_CFG_RUN_Pos                             0                                                         /*!< CCU2 CLK_APLL_CFG: RUN Position     */
#define CCU2_CLK_APLL_CFG_RUN_Msk                             (0x01UL << CCU2_CLK_APLL_CFG_RUN_Pos)                     /*!< CCU2 CLK_APLL_CFG: RUN Mask         */
#define CCU2_CLK_APLL_CFG_AUTO_Pos                            1                                                         /*!< CCU2 CLK_APLL_CFG: AUTO Position    */
#define CCU2_CLK_APLL_CFG_AUTO_Msk                            (0x01UL << CCU2_CLK_APLL_CFG_AUTO_Pos)                    /*!< CCU2 CLK_APLL_CFG: AUTO Mask        */
#define CCU2_CLK_APLL_CFG_WAKEUP_Pos                          2                                                         /*!< CCU2 CLK_APLL_CFG: WAKEUP Position  */
#define CCU2_CLK_APLL_CFG_WAKEUP_Msk                          (0x01UL << CCU2_CLK_APLL_CFG_WAKEUP_Pos)                  /*!< CCU2 CLK_APLL_CFG: WAKEUP Mask      */

// -----------------------------------  CCU2_CLK_APLL_STAT  ---------------------------------------
#define CCU2_CLK_APLL_STAT_RUN_Pos                            0                                                         /*!< CCU2 CLK_APLL_STAT: RUN Position    */
#define CCU2_CLK_APLL_STAT_RUN_Msk                            (0x01UL << CCU2_CLK_APLL_STAT_RUN_Pos)                    /*!< CCU2 CLK_APLL_STAT: RUN Mask        */
#define CCU2_CLK_APLL_STAT_AUTO_Pos                           1                                                         /*!< CCU2 CLK_APLL_STAT: AUTO Position   */
#define CCU2_CLK_APLL_STAT_AUTO_Msk                           (0x01UL << CCU2_CLK_APLL_STAT_AUTO_Pos)                   /*!< CCU2 CLK_APLL_STAT: AUTO Mask       */
#define CCU2_CLK_APLL_STAT_WAKEUP_Pos                         2                                                         /*!< CCU2 CLK_APLL_STAT: WAKEUP Position */
#define CCU2_CLK_APLL_STAT_WAKEUP_Msk                         (0x01UL << CCU2_CLK_APLL_STAT_WAKEUP_Pos)                 /*!< CCU2 CLK_APLL_STAT: WAKEUP Mask     */

// --------------------------------  CCU2_CLK_APB2_USART3_CFG  ------------------------------------
#define CCU2_CLK_APB2_USART3_CFG_RUN_Pos                      0                                                         /*!< CCU2 CLK_APB2_USART3_CFG: RUN Position */
#define CCU2_CLK_APB2_USART3_CFG_RUN_Msk                      (0x01UL << CCU2_CLK_APB2_USART3_CFG_RUN_Pos)              /*!< CCU2 CLK_APB2_USART3_CFG: RUN Mask  */
#define CCU2_CLK_APB2_USART3_CFG_AUTO_Pos                     1                                                         /*!< CCU2 CLK_APB2_USART3_CFG: AUTO Position */
#define CCU2_CLK_APB2_USART3_CFG_AUTO_Msk                     (0x01UL << CCU2_CLK_APB2_USART3_CFG_AUTO_Pos)             /*!< CCU2 CLK_APB2_USART3_CFG: AUTO Mask */
#define CCU2_CLK_APB2_USART3_CFG_WAKEUP_Pos                   2                                                         /*!< CCU2 CLK_APB2_USART3_CFG: WAKEUP Position */
#define CCU2_CLK_APB2_USART3_CFG_WAKEUP_Msk                   (0x01UL << CCU2_CLK_APB2_USART3_CFG_WAKEUP_Pos)           /*!< CCU2 CLK_APB2_USART3_CFG: WAKEUP Mask */

// --------------------------------  CCU2_CLK_APB2_USART3_STAT  -----------------------------------
#define CCU2_CLK_APB2_USART3_STAT_RUN_Pos                     0                                                         /*!< CCU2 CLK_APB2_USART3_STAT: RUN Position */
#define CCU2_CLK_APB2_USART3_STAT_RUN_Msk                     (0x01UL << CCU2_CLK_APB2_USART3_STAT_RUN_Pos)             /*!< CCU2 CLK_APB2_USART3_STAT: RUN Mask */
#define CCU2_CLK_APB2_USART3_STAT_AUTO_Pos                    1                                                         /*!< CCU2 CLK_APB2_USART3_STAT: AUTO Position */
#define CCU2_CLK_APB2_USART3_STAT_AUTO_Msk                    (0x01UL << CCU2_CLK_APB2_USART3_STAT_AUTO_Pos)            /*!< CCU2 CLK_APB2_USART3_STAT: AUTO Mask */
#define CCU2_CLK_APB2_USART3_STAT_WAKEUP_Pos                  2                                                         /*!< CCU2 CLK_APB2_USART3_STAT: WAKEUP Position */
#define CCU2_CLK_APB2_USART3_STAT_WAKEUP_Msk                  (0x01UL << CCU2_CLK_APB2_USART3_STAT_WAKEUP_Pos)          /*!< CCU2 CLK_APB2_USART3_STAT: WAKEUP Mask */

// --------------------------------  CCU2_CLK_APB2_USART2_CFG  ------------------------------------
#define CCU2_CLK_APB2_USART2_CFG_RUN_Pos                      0                                                         /*!< CCU2 CLK_APB2_USART2_CFG: RUN Position */
#define CCU2_CLK_APB2_USART2_CFG_RUN_Msk                      (0x01UL << CCU2_CLK_APB2_USART2_CFG_RUN_Pos)              /*!< CCU2 CLK_APB2_USART2_CFG: RUN Mask  */
#define CCU2_CLK_APB2_USART2_CFG_AUTO_Pos                     1                                                         /*!< CCU2 CLK_APB2_USART2_CFG: AUTO Position */
#define CCU2_CLK_APB2_USART2_CFG_AUTO_Msk                     (0x01UL << CCU2_CLK_APB2_USART2_CFG_AUTO_Pos)             /*!< CCU2 CLK_APB2_USART2_CFG: AUTO Mask */
#define CCU2_CLK_APB2_USART2_CFG_WAKEUP_Pos                   2                                                         /*!< CCU2 CLK_APB2_USART2_CFG: WAKEUP Position */
#define CCU2_CLK_APB2_USART2_CFG_WAKEUP_Msk                   (0x01UL << CCU2_CLK_APB2_USART2_CFG_WAKEUP_Pos)           /*!< CCU2 CLK_APB2_USART2_CFG: WAKEUP Mask */

// --------------------------------  CCU2_CLK_APB2_USART2_STAT  -----------------------------------
#define CCU2_CLK_APB2_USART2_STAT_RUN_Pos                     0                                                         /*!< CCU2 CLK_APB2_USART2_STAT: RUN Position */
#define CCU2_CLK_APB2_USART2_STAT_RUN_Msk                     (0x01UL << CCU2_CLK_APB2_USART2_STAT_RUN_Pos)             /*!< CCU2 CLK_APB2_USART2_STAT: RUN Mask */
#define CCU2_CLK_APB2_USART2_STAT_AUTO_Pos                    1                                                         /*!< CCU2 CLK_APB2_USART2_STAT: AUTO Position */
#define CCU2_CLK_APB2_USART2_STAT_AUTO_Msk                    (0x01UL << CCU2_CLK_APB2_USART2_STAT_AUTO_Pos)            /*!< CCU2 CLK_APB2_USART2_STAT: AUTO Mask */
#define CCU2_CLK_APB2_USART2_STAT_WAKEUP_Pos                  2                                                         /*!< CCU2 CLK_APB2_USART2_STAT: WAKEUP Position */
#define CCU2_CLK_APB2_USART2_STAT_WAKEUP_Msk                  (0x01UL << CCU2_CLK_APB2_USART2_STAT_WAKEUP_Pos)          /*!< CCU2 CLK_APB2_USART2_STAT: WAKEUP Mask */

// -------------------------------  CCU2_CLK_APB0_UART1_BUS_CFG  ----------------------------------
#define CCU2_CLK_APB0_UART1_BUS_CFG_RUN_Pos                   0                                                         /*!< CCU2 CLK_APB0_UART1_BUS_CFG: RUN Position */
#define CCU2_CLK_APB0_UART1_BUS_CFG_RUN_Msk                   (0x01UL << CCU2_CLK_APB0_UART1_BUS_CFG_RUN_Pos)           /*!< CCU2 CLK_APB0_UART1_BUS_CFG: RUN Mask */
#define CCU2_CLK_APB0_UART1_BUS_CFG_AUTO_Pos                  1                                                         /*!< CCU2 CLK_APB0_UART1_BUS_CFG: AUTO Position */
#define CCU2_CLK_APB0_UART1_BUS_CFG_AUTO_Msk                  (0x01UL << CCU2_CLK_APB0_UART1_BUS_CFG_AUTO_Pos)          /*!< CCU2 CLK_APB0_UART1_BUS_CFG: AUTO Mask */
#define CCU2_CLK_APB0_UART1_BUS_CFG_WAKEUP_Pos                2                                                         /*!< CCU2 CLK_APB0_UART1_BUS_CFG: WAKEUP Position */
#define CCU2_CLK_APB0_UART1_BUS_CFG_WAKEUP_Msk                (0x01UL << CCU2_CLK_APB0_UART1_BUS_CFG_WAKEUP_Pos)        /*!< CCU2 CLK_APB0_UART1_BUS_CFG: WAKEUP Mask */

// --------------------------------  CCU2_CLK_APB0_UART1_STAT  ------------------------------------
#define CCU2_CLK_APB0_UART1_STAT_RUN_Pos                      0                                                         /*!< CCU2 CLK_APB0_UART1_STAT: RUN Position */
#define CCU2_CLK_APB0_UART1_STAT_RUN_Msk                      (0x01UL << CCU2_CLK_APB0_UART1_STAT_RUN_Pos)              /*!< CCU2 CLK_APB0_UART1_STAT: RUN Mask  */
#define CCU2_CLK_APB0_UART1_STAT_AUTO_Pos                     1                                                         /*!< CCU2 CLK_APB0_UART1_STAT: AUTO Position */
#define CCU2_CLK_APB0_UART1_STAT_AUTO_Msk                     (0x01UL << CCU2_CLK_APB0_UART1_STAT_AUTO_Pos)             /*!< CCU2 CLK_APB0_UART1_STAT: AUTO Mask */
#define CCU2_CLK_APB0_UART1_STAT_WAKEUP_Pos                   2                                                         /*!< CCU2 CLK_APB0_UART1_STAT: WAKEUP Position */
#define CCU2_CLK_APB0_UART1_STAT_WAKEUP_Msk                   (0x01UL << CCU2_CLK_APB0_UART1_STAT_WAKEUP_Pos)           /*!< CCU2 CLK_APB0_UART1_STAT: WAKEUP Mask */

// --------------------------------  CCU2_CLK_APB0_USART0_CFG  ------------------------------------
#define CCU2_CLK_APB0_USART0_CFG_RUN_Pos                      0                                                         /*!< CCU2 CLK_APB0_USART0_CFG: RUN Position */
#define CCU2_CLK_APB0_USART0_CFG_RUN_Msk                      (0x01UL << CCU2_CLK_APB0_USART0_CFG_RUN_Pos)              /*!< CCU2 CLK_APB0_USART0_CFG: RUN Mask  */
#define CCU2_CLK_APB0_USART0_CFG_AUTO_Pos                     1                                                         /*!< CCU2 CLK_APB0_USART0_CFG: AUTO Position */
#define CCU2_CLK_APB0_USART0_CFG_AUTO_Msk                     (0x01UL << CCU2_CLK_APB0_USART0_CFG_AUTO_Pos)             /*!< CCU2 CLK_APB0_USART0_CFG: AUTO Mask */
#define CCU2_CLK_APB0_USART0_CFG_WAKEUP_Pos                   2                                                         /*!< CCU2 CLK_APB0_USART0_CFG: WAKEUP Position */
#define CCU2_CLK_APB0_USART0_CFG_WAKEUP_Msk                   (0x01UL << CCU2_CLK_APB0_USART0_CFG_WAKEUP_Pos)           /*!< CCU2 CLK_APB0_USART0_CFG: WAKEUP Mask */

// --------------------------------  CCU2_CLK_APB0_USART0_STAT  -----------------------------------
#define CCU2_CLK_APB0_USART0_STAT_RUN_Pos                     0                                                         /*!< CCU2 CLK_APB0_USART0_STAT: RUN Position */
#define CCU2_CLK_APB0_USART0_STAT_RUN_Msk                     (0x01UL << CCU2_CLK_APB0_USART0_STAT_RUN_Pos)             /*!< CCU2 CLK_APB0_USART0_STAT: RUN Mask */
#define CCU2_CLK_APB0_USART0_STAT_AUTO_Pos                    1                                                         /*!< CCU2 CLK_APB0_USART0_STAT: AUTO Position */
#define CCU2_CLK_APB0_USART0_STAT_AUTO_Msk                    (0x01UL << CCU2_CLK_APB0_USART0_STAT_AUTO_Pos)            /*!< CCU2 CLK_APB0_USART0_STAT: AUTO Mask */
#define CCU2_CLK_APB0_USART0_STAT_WAKEUP_Pos                  2                                                         /*!< CCU2 CLK_APB0_USART0_STAT: WAKEUP Position */
#define CCU2_CLK_APB0_USART0_STAT_WAKEUP_Msk                  (0x01UL << CCU2_CLK_APB0_USART0_STAT_WAKEUP_Pos)          /*!< CCU2 CLK_APB0_USART0_STAT: WAKEUP Mask */

// ---------------------------------  CCU2_CLK_APB2_SSP1_CFG  -------------------------------------
#define CCU2_CLK_APB2_SSP1_CFG_RUN_Pos                        0                                                         /*!< CCU2 CLK_APB2_SSP1_CFG: RUN Position */
#define CCU2_CLK_APB2_SSP1_CFG_RUN_Msk                        (0x01UL << CCU2_CLK_APB2_SSP1_CFG_RUN_Pos)                /*!< CCU2 CLK_APB2_SSP1_CFG: RUN Mask    */
#define CCU2_CLK_APB2_SSP1_CFG_AUTO_Pos                       1                                                         /*!< CCU2 CLK_APB2_SSP1_CFG: AUTO Position */
#define CCU2_CLK_APB2_SSP1_CFG_AUTO_Msk                       (0x01UL << CCU2_CLK_APB2_SSP1_CFG_AUTO_Pos)               /*!< CCU2 CLK_APB2_SSP1_CFG: AUTO Mask   */
#define CCU2_CLK_APB2_SSP1_CFG_WAKEUP_Pos                     2                                                         /*!< CCU2 CLK_APB2_SSP1_CFG: WAKEUP Position */
#define CCU2_CLK_APB2_SSP1_CFG_WAKEUP_Msk                     (0x01UL << CCU2_CLK_APB2_SSP1_CFG_WAKEUP_Pos)             /*!< CCU2 CLK_APB2_SSP1_CFG: WAKEUP Mask */

// ---------------------------------  CCU2_CLK_APB2_SSP1_STAT  ------------------------------------
#define CCU2_CLK_APB2_SSP1_STAT_RUN_Pos                       0                                                         /*!< CCU2 CLK_APB2_SSP1_STAT: RUN Position */
#define CCU2_CLK_APB2_SSP1_STAT_RUN_Msk                       (0x01UL << CCU2_CLK_APB2_SSP1_STAT_RUN_Pos)               /*!< CCU2 CLK_APB2_SSP1_STAT: RUN Mask   */
#define CCU2_CLK_APB2_SSP1_STAT_AUTO_Pos                      1                                                         /*!< CCU2 CLK_APB2_SSP1_STAT: AUTO Position */
#define CCU2_CLK_APB2_SSP1_STAT_AUTO_Msk                      (0x01UL << CCU2_CLK_APB2_SSP1_STAT_AUTO_Pos)              /*!< CCU2 CLK_APB2_SSP1_STAT: AUTO Mask  */
#define CCU2_CLK_APB2_SSP1_STAT_WAKEUP_Pos                    2                                                         /*!< CCU2 CLK_APB2_SSP1_STAT: WAKEUP Position */
#define CCU2_CLK_APB2_SSP1_STAT_WAKEUP_Msk                    (0x01UL << CCU2_CLK_APB2_SSP1_STAT_WAKEUP_Pos)            /*!< CCU2 CLK_APB2_SSP1_STAT: WAKEUP Mask */

// ---------------------------------  CCU2_CLK_APB0_SSP0_CFG  -------------------------------------
#define CCU2_CLK_APB0_SSP0_CFG_RUN_Pos                        0                                                         /*!< CCU2 CLK_APB0_SSP0_CFG: RUN Position */
#define CCU2_CLK_APB0_SSP0_CFG_RUN_Msk                        (0x01UL << CCU2_CLK_APB0_SSP0_CFG_RUN_Pos)                /*!< CCU2 CLK_APB0_SSP0_CFG: RUN Mask    */
#define CCU2_CLK_APB0_SSP0_CFG_AUTO_Pos                       1                                                         /*!< CCU2 CLK_APB0_SSP0_CFG: AUTO Position */
#define CCU2_CLK_APB0_SSP0_CFG_AUTO_Msk                       (0x01UL << CCU2_CLK_APB0_SSP0_CFG_AUTO_Pos)               /*!< CCU2 CLK_APB0_SSP0_CFG: AUTO Mask   */
#define CCU2_CLK_APB0_SSP0_CFG_WAKEUP_Pos                     2                                                         /*!< CCU2 CLK_APB0_SSP0_CFG: WAKEUP Position */
#define CCU2_CLK_APB0_SSP0_CFG_WAKEUP_Msk                     (0x01UL << CCU2_CLK_APB0_SSP0_CFG_WAKEUP_Pos)             /*!< CCU2 CLK_APB0_SSP0_CFG: WAKEUP Mask */

// ---------------------------------  CCU2_CLK_APB0_SSP0_STAT  ------------------------------------
#define CCU2_CLK_APB0_SSP0_STAT_RUN_Pos                       0                                                         /*!< CCU2 CLK_APB0_SSP0_STAT: RUN Position */
#define CCU2_CLK_APB0_SSP0_STAT_RUN_Msk                       (0x01UL << CCU2_CLK_APB0_SSP0_STAT_RUN_Pos)               /*!< CCU2 CLK_APB0_SSP0_STAT: RUN Mask   */
#define CCU2_CLK_APB0_SSP0_STAT_AUTO_Pos                      1                                                         /*!< CCU2 CLK_APB0_SSP0_STAT: AUTO Position */
#define CCU2_CLK_APB0_SSP0_STAT_AUTO_Msk                      (0x01UL << CCU2_CLK_APB0_SSP0_STAT_AUTO_Pos)              /*!< CCU2 CLK_APB0_SSP0_STAT: AUTO Mask  */
#define CCU2_CLK_APB0_SSP0_STAT_WAKEUP_Pos                    2                                                         /*!< CCU2 CLK_APB0_SSP0_STAT: WAKEUP Position */
#define CCU2_CLK_APB0_SSP0_STAT_WAKEUP_Msk                    (0x01UL << CCU2_CLK_APB0_SSP0_STAT_WAKEUP_Pos)            /*!< CCU2 CLK_APB0_SSP0_STAT: WAKEUP Mask */

// ------------------------------------  CCU2_CLK_SDIO_CFG  ---------------------------------------
#define CCU2_CLK_SDIO_CFG_RUN_Pos                             0                                                         /*!< CCU2 CLK_SDIO_CFG: RUN Position     */
#define CCU2_CLK_SDIO_CFG_RUN_Msk                             (0x01UL << CCU2_CLK_SDIO_CFG_RUN_Pos)                     /*!< CCU2 CLK_SDIO_CFG: RUN Mask         */
#define CCU2_CLK_SDIO_CFG_AUTO_Pos                            1                                                         /*!< CCU2 CLK_SDIO_CFG: AUTO Position    */
#define CCU2_CLK_SDIO_CFG_AUTO_Msk                            (0x01UL << CCU2_CLK_SDIO_CFG_AUTO_Pos)                    /*!< CCU2 CLK_SDIO_CFG: AUTO Mask        */
#define CCU2_CLK_SDIO_CFG_WAKEUP_Pos                          2                                                         /*!< CCU2 CLK_SDIO_CFG: WAKEUP Position  */
#define CCU2_CLK_SDIO_CFG_WAKEUP_Msk                          (0x01UL << CCU2_CLK_SDIO_CFG_WAKEUP_Pos)                  /*!< CCU2 CLK_SDIO_CFG: WAKEUP Mask      */

// -----------------------------------  CCU2_CLK_SDIO_STAT  ---------------------------------------
#define CCU2_CLK_SDIO_STAT_RUN_Pos                            0                                                         /*!< CCU2 CLK_SDIO_STAT: RUN Position    */
#define CCU2_CLK_SDIO_STAT_RUN_Msk                            (0x01UL << CCU2_CLK_SDIO_STAT_RUN_Pos)                    /*!< CCU2 CLK_SDIO_STAT: RUN Mask        */
#define CCU2_CLK_SDIO_STAT_AUTO_Pos                           1                                                         /*!< CCU2 CLK_SDIO_STAT: AUTO Position   */
#define CCU2_CLK_SDIO_STAT_AUTO_Msk                           (0x01UL << CCU2_CLK_SDIO_STAT_AUTO_Pos)                   /*!< CCU2 CLK_SDIO_STAT: AUTO Mask       */
#define CCU2_CLK_SDIO_STAT_WAKEUP_Pos                         2                                                         /*!< CCU2 CLK_SDIO_STAT: WAKEUP Position */
#define CCU2_CLK_SDIO_STAT_WAKEUP_Msk                         (0x01UL << CCU2_CLK_SDIO_STAT_WAKEUP_Pos)                 /*!< CCU2 CLK_SDIO_STAT: WAKEUP Mask     */


// ------------------------------------------------------------------------------------------------
// -----                                  RGU Position & Mask                                 -----
// ------------------------------------------------------------------------------------------------


// -------------------------------------  RGU_RESET_CTRL0  ----------------------------------------
#define RGU_RESET_CTRL0_CORE_RST_Pos                          0                                                         /*!< RGU RESET_CTRL0: CORE_RST Position  */
#define RGU_RESET_CTRL0_CORE_RST_Msk                          (0x01UL << RGU_RESET_CTRL0_CORE_RST_Pos)                  /*!< RGU RESET_CTRL0: CORE_RST Mask      */
#define RGU_RESET_CTRL0_PERIPH_RST_Pos                        1                                                         /*!< RGU RESET_CTRL0: PERIPH_RST Position */
#define RGU_RESET_CTRL0_PERIPH_RST_Msk                        (0x01UL << RGU_RESET_CTRL0_PERIPH_RST_Pos)                /*!< RGU RESET_CTRL0: PERIPH_RST Mask    */
#define RGU_RESET_CTRL0_MASTER_RST_Pos                        2                                                         /*!< RGU RESET_CTRL0: MASTER_RST Position */
#define RGU_RESET_CTRL0_MASTER_RST_Msk                        (0x01UL << RGU_RESET_CTRL0_MASTER_RST_Pos)                /*!< RGU RESET_CTRL0: MASTER_RST Mask    */
#define RGU_RESET_CTRL0_WWDT_RST_Pos                          4                                                         /*!< RGU RESET_CTRL0: WWDT_RST Position  */
#define RGU_RESET_CTRL0_WWDT_RST_Msk                          (0x01UL << RGU_RESET_CTRL0_WWDT_RST_Pos)                  /*!< RGU RESET_CTRL0: WWDT_RST Mask      */
#define RGU_RESET_CTRL0_CREG_RST_Pos                          5                                                         /*!< RGU RESET_CTRL0: CREG_RST Position  */
#define RGU_RESET_CTRL0_CREG_RST_Msk                          (0x01UL << RGU_RESET_CTRL0_CREG_RST_Pos)                  /*!< RGU RESET_CTRL0: CREG_RST Mask      */
#define RGU_RESET_CTRL0_BUS_RST_Pos                           8                                                         /*!< RGU RESET_CTRL0: BUS_RST Position   */
#define RGU_RESET_CTRL0_BUS_RST_Msk                           (0x01UL << RGU_RESET_CTRL0_BUS_RST_Pos)                   /*!< RGU RESET_CTRL0: BUS_RST Mask       */
#define RGU_RESET_CTRL0_SCU_RST_Pos                           9                                                         /*!< RGU RESET_CTRL0: SCU_RST Position   */
#define RGU_RESET_CTRL0_SCU_RST_Msk                           (0x01UL << RGU_RESET_CTRL0_SCU_RST_Pos)                   /*!< RGU RESET_CTRL0: SCU_RST Mask       */
#define RGU_RESET_CTRL0_PINMUX_RST_Pos                        10                                                        /*!< RGU RESET_CTRL0: PINMUX_RST Position */
#define RGU_RESET_CTRL0_PINMUX_RST_Msk                        (0x01UL << RGU_RESET_CTRL0_PINMUX_RST_Pos)                /*!< RGU RESET_CTRL0: PINMUX_RST Mask    */
#define RGU_RESET_CTRL0_M4_RST_Pos                            13                                                        /*!< RGU RESET_CTRL0: M4_RST Position    */
#define RGU_RESET_CTRL0_M4_RST_Msk                            (0x01UL << RGU_RESET_CTRL0_M4_RST_Pos)                    /*!< RGU RESET_CTRL0: M4_RST Mask        */
#define RGU_RESET_CTRL0_LCD_RST_Pos                           16                                                        /*!< RGU RESET_CTRL0: LCD_RST Position   */
#define RGU_RESET_CTRL0_LCD_RST_Msk                           (0x01UL << RGU_RESET_CTRL0_LCD_RST_Pos)                   /*!< RGU RESET_CTRL0: LCD_RST Mask       */
#define RGU_RESET_CTRL0_USB0_RST_Pos                          17                                                        /*!< RGU RESET_CTRL0: USB0_RST Position  */
#define RGU_RESET_CTRL0_USB0_RST_Msk                          (0x01UL << RGU_RESET_CTRL0_USB0_RST_Pos)                  /*!< RGU RESET_CTRL0: USB0_RST Mask      */
#define RGU_RESET_CTRL0_USB1_RST_Pos                          18                                                        /*!< RGU RESET_CTRL0: USB1_RST Position  */
#define RGU_RESET_CTRL0_USB1_RST_Msk                          (0x01UL << RGU_RESET_CTRL0_USB1_RST_Pos)                  /*!< RGU RESET_CTRL0: USB1_RST Mask      */
#define RGU_RESET_CTRL0_DMA_RST_Pos                           19                                                        /*!< RGU RESET_CTRL0: DMA_RST Position   */
#define RGU_RESET_CTRL0_DMA_RST_Msk                           (0x01UL << RGU_RESET_CTRL0_DMA_RST_Pos)                   /*!< RGU RESET_CTRL0: DMA_RST Mask       */
#define RGU_RESET_CTRL0_SDIO_RST_Pos                          20                                                        /*!< RGU RESET_CTRL0: SDIO_RST Position  */
#define RGU_RESET_CTRL0_SDIO_RST_Msk                          (0x01UL << RGU_RESET_CTRL0_SDIO_RST_Pos)                  /*!< RGU RESET_CTRL0: SDIO_RST Mask      */
#define RGU_RESET_CTRL0_EMC_RST_Pos                           21                                                        /*!< RGU RESET_CTRL0: EMC_RST Position   */
#define RGU_RESET_CTRL0_EMC_RST_Msk                           (0x01UL << RGU_RESET_CTRL0_EMC_RST_Pos)                   /*!< RGU RESET_CTRL0: EMC_RST Mask       */
#define RGU_RESET_CTRL0_ETHERNET_RST_Pos                      22                                                        /*!< RGU RESET_CTRL0: ETHERNET_RST Position */
#define RGU_RESET_CTRL0_ETHERNET_RST_Msk                      (0x01UL << RGU_RESET_CTRL0_ETHERNET_RST_Pos)              /*!< RGU RESET_CTRL0: ETHERNET_RST Mask  */
#define RGU_RESET_CTRL0_GPIO_RST_Pos                          28                                                        /*!< RGU RESET_CTRL0: GPIO_RST Position  */
#define RGU_RESET_CTRL0_GPIO_RST_Msk                          (0x01UL << RGU_RESET_CTRL0_GPIO_RST_Pos)                  /*!< RGU RESET_CTRL0: GPIO_RST Mask      */

// -------------------------------------  RGU_RESET_CTRL1  ----------------------------------------
#define RGU_RESET_CTRL1_TIMER0_RST_Pos                        0                                                         /*!< RGU RESET_CTRL1: TIMER0_RST Position */
#define RGU_RESET_CTRL1_TIMER0_RST_Msk                        (0x01UL << RGU_RESET_CTRL1_TIMER0_RST_Pos)                /*!< RGU RESET_CTRL1: TIMER0_RST Mask    */
#define RGU_RESET_CTRL1_TIMER1_RST_Pos                        1                                                         /*!< RGU RESET_CTRL1: TIMER1_RST Position */
#define RGU_RESET_CTRL1_TIMER1_RST_Msk                        (0x01UL << RGU_RESET_CTRL1_TIMER1_RST_Pos)                /*!< RGU RESET_CTRL1: TIMER1_RST Mask    */
#define RGU_RESET_CTRL1_TIMER2_RST_Pos                        2                                                         /*!< RGU RESET_CTRL1: TIMER2_RST Position */
#define RGU_RESET_CTRL1_TIMER2_RST_Msk                        (0x01UL << RGU_RESET_CTRL1_TIMER2_RST_Pos)                /*!< RGU RESET_CTRL1: TIMER2_RST Mask    */
#define RGU_RESET_CTRL1_TIMER3_RST_Pos                        3                                                         /*!< RGU RESET_CTRL1: TIMER3_RST Position */
#define RGU_RESET_CTRL1_TIMER3_RST_Msk                        (0x01UL << RGU_RESET_CTRL1_TIMER3_RST_Pos)                /*!< RGU RESET_CTRL1: TIMER3_RST Mask    */
#define RGU_RESET_CTRL1_RITIMER_RST_Pos                       4                                                         /*!< RGU RESET_CTRL1: RITIMER_RST Position */
#define RGU_RESET_CTRL1_RITIMER_RST_Msk                       (0x01UL << RGU_RESET_CTRL1_RITIMER_RST_Pos)               /*!< RGU RESET_CTRL1: RITIMER_RST Mask   */
#define RGU_RESET_CTRL1_SCT_RST_Pos                           5                                                         /*!< RGU RESET_CTRL1: SCT_RST Position   */
#define RGU_RESET_CTRL1_SCT_RST_Msk                           (0x01UL << RGU_RESET_CTRL1_SCT_RST_Pos)                   /*!< RGU RESET_CTRL1: SCT_RST Mask       */
#define RGU_RESET_CTRL1_MOTOCONPWM_RST_Pos                    6                                                         /*!< RGU RESET_CTRL1: MOTOCONPWM_RST Position */
#define RGU_RESET_CTRL1_MOTOCONPWM_RST_Msk                    (0x01UL << RGU_RESET_CTRL1_MOTOCONPWM_RST_Pos)            /*!< RGU RESET_CTRL1: MOTOCONPWM_RST Mask */
#define RGU_RESET_CTRL1_QEI_RST_Pos                           7                                                         /*!< RGU RESET_CTRL1: QEI_RST Position   */
#define RGU_RESET_CTRL1_QEI_RST_Msk                           (0x01UL << RGU_RESET_CTRL1_QEI_RST_Pos)                   /*!< RGU RESET_CTRL1: QEI_RST Mask       */
#define RGU_RESET_CTRL1_ADC0_RST_Pos                          8                                                         /*!< RGU RESET_CTRL1: ADC0_RST Position  */
#define RGU_RESET_CTRL1_ADC0_RST_Msk                          (0x01UL << RGU_RESET_CTRL1_ADC0_RST_Pos)                  /*!< RGU RESET_CTRL1: ADC0_RST Mask      */
#define RGU_RESET_CTRL1_ADC1_RST_Pos                          9                                                         /*!< RGU RESET_CTRL1: ADC1_RST Position  */
#define RGU_RESET_CTRL1_ADC1_RST_Msk                          (0x01UL << RGU_RESET_CTRL1_ADC1_RST_Pos)                  /*!< RGU RESET_CTRL1: ADC1_RST Mask      */
#define RGU_RESET_CTRL1_DAC_RST_Pos                           10                                                        /*!< RGU RESET_CTRL1: DAC_RST Position   */
#define RGU_RESET_CTRL1_DAC_RST_Msk                           (0x01UL << RGU_RESET_CTRL1_DAC_RST_Pos)                   /*!< RGU RESET_CTRL1: DAC_RST Mask       */
#define RGU_RESET_CTRL1_UART0_RST_Pos                         12                                                        /*!< RGU RESET_CTRL1: UART0_RST Position */
#define RGU_RESET_CTRL1_UART0_RST_Msk                         (0x01UL << RGU_RESET_CTRL1_UART0_RST_Pos)                 /*!< RGU RESET_CTRL1: UART0_RST Mask     */
#define RGU_RESET_CTRL1_UART1_RST_Pos                         13                                                        /*!< RGU RESET_CTRL1: UART1_RST Position */
#define RGU_RESET_CTRL1_UART1_RST_Msk                         (0x01UL << RGU_RESET_CTRL1_UART1_RST_Pos)                 /*!< RGU RESET_CTRL1: UART1_RST Mask     */
#define RGU_RESET_CTRL1_UART2_RST_Pos                         14                                                        /*!< RGU RESET_CTRL1: UART2_RST Position */
#define RGU_RESET_CTRL1_UART2_RST_Msk                         (0x01UL << RGU_RESET_CTRL1_UART2_RST_Pos)                 /*!< RGU RESET_CTRL1: UART2_RST Mask     */
#define RGU_RESET_CTRL1_UART3_RST_Pos                         15                                                        /*!< RGU RESET_CTRL1: UART3_RST Position */
#define RGU_RESET_CTRL1_UART3_RST_Msk                         (0x01UL << RGU_RESET_CTRL1_UART3_RST_Pos)                 /*!< RGU RESET_CTRL1: UART3_RST Mask     */
#define RGU_RESET_CTRL1_I2C0_RST_Pos                          16                                                        /*!< RGU RESET_CTRL1: I2C0_RST Position  */
#define RGU_RESET_CTRL1_I2C0_RST_Msk                          (0x01UL << RGU_RESET_CTRL1_I2C0_RST_Pos)                  /*!< RGU RESET_CTRL1: I2C0_RST Mask      */
#define RGU_RESET_CTRL1_I2C1_RST_Pos                          17                                                        /*!< RGU RESET_CTRL1: I2C1_RST Position  */
#define RGU_RESET_CTRL1_I2C1_RST_Msk                          (0x01UL << RGU_RESET_CTRL1_I2C1_RST_Pos)                  /*!< RGU RESET_CTRL1: I2C1_RST Mask      */
#define RGU_RESET_CTRL1_SSP0_RST_Pos                          18                                                        /*!< RGU RESET_CTRL1: SSP0_RST Position  */
#define RGU_RESET_CTRL1_SSP0_RST_Msk                          (0x01UL << RGU_RESET_CTRL1_SSP0_RST_Pos)                  /*!< RGU RESET_CTRL1: SSP0_RST Mask      */
#define RGU_RESET_CTRL1_SSP1_RST_Pos                          19                                                        /*!< RGU RESET_CTRL1: SSP1_RST Position  */
#define RGU_RESET_CTRL1_SSP1_RST_Msk                          (0x01UL << RGU_RESET_CTRL1_SSP1_RST_Pos)                  /*!< RGU RESET_CTRL1: SSP1_RST Mask      */
#define RGU_RESET_CTRL1_I2S_RST_Pos                           20                                                        /*!< RGU RESET_CTRL1: I2S_RST Position   */
#define RGU_RESET_CTRL1_I2S_RST_Msk                           (0x01UL << RGU_RESET_CTRL1_I2S_RST_Pos)                   /*!< RGU RESET_CTRL1: I2S_RST Mask       */
#define RGU_RESET_CTRL1_SPIFI_RST_Pos                         21                                                        /*!< RGU RESET_CTRL1: SPIFI_RST Position */
#define RGU_RESET_CTRL1_SPIFI_RST_Msk                         (0x01UL << RGU_RESET_CTRL1_SPIFI_RST_Pos)                 /*!< RGU RESET_CTRL1: SPIFI_RST Mask     */
#define RGU_RESET_CTRL1_CAN1_RST_Pos                          22                                                        /*!< RGU RESET_CTRL1: CAN1_RST Position  */
#define RGU_RESET_CTRL1_CAN1_RST_Msk                          (0x01UL << RGU_RESET_CTRL1_CAN1_RST_Pos)                  /*!< RGU RESET_CTRL1: CAN1_RST Mask      */
#define RGU_RESET_CTRL1_CAN0_RST_Pos                          23                                                        /*!< RGU RESET_CTRL1: CAN0_RST Position  */
#define RGU_RESET_CTRL1_CAN0_RST_Msk                          (0x01UL << RGU_RESET_CTRL1_CAN0_RST_Pos)                  /*!< RGU RESET_CTRL1: CAN0_RST Mask      */
#define RGU_RESET_CTRL1_M0APP_RST_Pos                         24                                                        /*!< RGU RESET_CTRL1: M0APP_RST Position */
#define RGU_RESET_CTRL1_M0APP_RST_Msk                         (0x01UL << RGU_RESET_CTRL1_M0APP_RST_Pos)                 /*!< RGU RESET_CTRL1: M0APP_RST Mask     */
#define RGU_RESET_CTRL1_SGPIO_RST_Pos                         25                                                        /*!< RGU RESET_CTRL1: SGPIO_RST Position */
#define RGU_RESET_CTRL1_SGPIO_RST_Msk                         (0x01UL << RGU_RESET_CTRL1_SGPIO_RST_Pos)                 /*!< RGU RESET_CTRL1: SGPIO_RST Mask     */
#define RGU_RESET_CTRL1_SPI_RST_Pos                           26                                                        /*!< RGU RESET_CTRL1: SPI_RST Position   */
#define RGU_RESET_CTRL1_SPI_RST_Msk                           (0x01UL << RGU_RESET_CTRL1_SPI_RST_Pos)                   /*!< RGU RESET_CTRL1: SPI_RST Mask       */

// ------------------------------------  RGU_RESET_STATUS0  ---------------------------------------
#define RGU_RESET_STATUS0_CORE_RST_Pos                        0                                                         /*!< RGU RESET_STATUS0: CORE_RST Position */
#define RGU_RESET_STATUS0_CORE_RST_Msk                        (0x03UL << RGU_RESET_STATUS0_CORE_RST_Pos)                /*!< RGU RESET_STATUS0: CORE_RST Mask    */
#define RGU_RESET_STATUS0_PERIPH_RST_Pos                      2                                                         /*!< RGU RESET_STATUS0: PERIPH_RST Position */
#define RGU_RESET_STATUS0_PERIPH_RST_Msk                      (0x03UL << RGU_RESET_STATUS0_PERIPH_RST_Pos)              /*!< RGU RESET_STATUS0: PERIPH_RST Mask  */
#define RGU_RESET_STATUS0_MASTER_RST_Pos                      4                                                         /*!< RGU RESET_STATUS0: MASTER_RST Position */
#define RGU_RESET_STATUS0_MASTER_RST_Msk                      (0x03UL << RGU_RESET_STATUS0_MASTER_RST_Pos)              /*!< RGU RESET_STATUS0: MASTER_RST Mask  */
#define RGU_RESET_STATUS0_WWDT_RST_Pos                        8                                                         /*!< RGU RESET_STATUS0: WWDT_RST Position */
#define RGU_RESET_STATUS0_WWDT_RST_Msk                        (0x03UL << RGU_RESET_STATUS0_WWDT_RST_Pos)                /*!< RGU RESET_STATUS0: WWDT_RST Mask    */
#define RGU_RESET_STATUS0_CREG_RST_Pos                        10                                                        /*!< RGU RESET_STATUS0: CREG_RST Position */
#define RGU_RESET_STATUS0_CREG_RST_Msk                        (0x03UL << RGU_RESET_STATUS0_CREG_RST_Pos)                /*!< RGU RESET_STATUS0: CREG_RST Mask    */
#define RGU_RESET_STATUS0_BUS_RST_Pos                         16                                                        /*!< RGU RESET_STATUS0: BUS_RST Position */
#define RGU_RESET_STATUS0_BUS_RST_Msk                         (0x03UL << RGU_RESET_STATUS0_BUS_RST_Pos)                 /*!< RGU RESET_STATUS0: BUS_RST Mask     */
#define RGU_RESET_STATUS0_SCU_RST_Pos                         18                                                        /*!< RGU RESET_STATUS0: SCU_RST Position */
#define RGU_RESET_STATUS0_SCU_RST_Msk                         (0x03UL << RGU_RESET_STATUS0_SCU_RST_Pos)                 /*!< RGU RESET_STATUS0: SCU_RST Mask     */
#define RGU_RESET_STATUS0_M4_RST_Pos                          26                                                        /*!< RGU RESET_STATUS0: M4_RST Position  */
#define RGU_RESET_STATUS0_M4_RST_Msk                          (0x03UL << RGU_RESET_STATUS0_M4_RST_Pos)                  /*!< RGU RESET_STATUS0: M4_RST Mask      */

// ------------------------------------  RGU_RESET_STATUS1  ---------------------------------------
#define RGU_RESET_STATUS1_LCD_RST_Pos                         0                                                         /*!< RGU RESET_STATUS1: LCD_RST Position */
#define RGU_RESET_STATUS1_LCD_RST_Msk                         (0x03UL << RGU_RESET_STATUS1_LCD_RST_Pos)                 /*!< RGU RESET_STATUS1: LCD_RST Mask     */
#define RGU_RESET_STATUS1_USB0_RST_Pos                        2                                                         /*!< RGU RESET_STATUS1: USB0_RST Position */
#define RGU_RESET_STATUS1_USB0_RST_Msk                        (0x03UL << RGU_RESET_STATUS1_USB0_RST_Pos)                /*!< RGU RESET_STATUS1: USB0_RST Mask    */
#define RGU_RESET_STATUS1_USB1_RST_Pos                        4                                                         /*!< RGU RESET_STATUS1: USB1_RST Position */
#define RGU_RESET_STATUS1_USB1_RST_Msk                        (0x03UL << RGU_RESET_STATUS1_USB1_RST_Pos)                /*!< RGU RESET_STATUS1: USB1_RST Mask    */
#define RGU_RESET_STATUS1_DMA_RST_Pos                         6                                                         /*!< RGU RESET_STATUS1: DMA_RST Position */
#define RGU_RESET_STATUS1_DMA_RST_Msk                         (0x03UL << RGU_RESET_STATUS1_DMA_RST_Pos)                 /*!< RGU RESET_STATUS1: DMA_RST Mask     */
#define RGU_RESET_STATUS1_SDIO_RST_Pos                        8                                                         /*!< RGU RESET_STATUS1: SDIO_RST Position */
#define RGU_RESET_STATUS1_SDIO_RST_Msk                        (0x03UL << RGU_RESET_STATUS1_SDIO_RST_Pos)                /*!< RGU RESET_STATUS1: SDIO_RST Mask    */
#define RGU_RESET_STATUS1_EMC_RST_Pos                         10                                                        /*!< RGU RESET_STATUS1: EMC_RST Position */
#define RGU_RESET_STATUS1_EMC_RST_Msk                         (0x03UL << RGU_RESET_STATUS1_EMC_RST_Pos)                 /*!< RGU RESET_STATUS1: EMC_RST Mask     */
#define RGU_RESET_STATUS1_ETHERNET_RST_Pos                    12                                                        /*!< RGU RESET_STATUS1: ETHERNET_RST Position */
#define RGU_RESET_STATUS1_ETHERNET_RST_Msk                    (0x03UL << RGU_RESET_STATUS1_ETHERNET_RST_Pos)            /*!< RGU RESET_STATUS1: ETHERNET_RST Mask */
#define RGU_RESET_STATUS1_GPIO_RST_Pos                        24                                                        /*!< RGU RESET_STATUS1: GPIO_RST Position */
#define RGU_RESET_STATUS1_GPIO_RST_Msk                        (0x03UL << RGU_RESET_STATUS1_GPIO_RST_Pos)                /*!< RGU RESET_STATUS1: GPIO_RST Mask    */

// ------------------------------------  RGU_RESET_STATUS2  ---------------------------------------
#define RGU_RESET_STATUS2_TIMER0_RST_Pos                      0                                                         /*!< RGU RESET_STATUS2: TIMER0_RST Position */
#define RGU_RESET_STATUS2_TIMER0_RST_Msk                      (0x03UL << RGU_RESET_STATUS2_TIMER0_RST_Pos)              /*!< RGU RESET_STATUS2: TIMER0_RST Mask  */
#define RGU_RESET_STATUS2_TIMER1_RST_Pos                      2                                                         /*!< RGU RESET_STATUS2: TIMER1_RST Position */
#define RGU_RESET_STATUS2_TIMER1_RST_Msk                      (0x03UL << RGU_RESET_STATUS2_TIMER1_RST_Pos)              /*!< RGU RESET_STATUS2: TIMER1_RST Mask  */
#define RGU_RESET_STATUS2_TIMER2_RST_Pos                      4                                                         /*!< RGU RESET_STATUS2: TIMER2_RST Position */
#define RGU_RESET_STATUS2_TIMER2_RST_Msk                      (0x03UL << RGU_RESET_STATUS2_TIMER2_RST_Pos)              /*!< RGU RESET_STATUS2: TIMER2_RST Mask  */
#define RGU_RESET_STATUS2_TIMER3_RST_Pos                      6                                                         /*!< RGU RESET_STATUS2: TIMER3_RST Position */
#define RGU_RESET_STATUS2_TIMER3_RST_Msk                      (0x03UL << RGU_RESET_STATUS2_TIMER3_RST_Pos)              /*!< RGU RESET_STATUS2: TIMER3_RST Mask  */
#define RGU_RESET_STATUS2_RITIMER_RST_Pos                     8                                                         /*!< RGU RESET_STATUS2: RITIMER_RST Position */
#define RGU_RESET_STATUS2_RITIMER_RST_Msk                     (0x03UL << RGU_RESET_STATUS2_RITIMER_RST_Pos)             /*!< RGU RESET_STATUS2: RITIMER_RST Mask */
#define RGU_RESET_STATUS2_SCT_RST_Pos                         10                                                        /*!< RGU RESET_STATUS2: SCT_RST Position */
#define RGU_RESET_STATUS2_SCT_RST_Msk                         (0x03UL << RGU_RESET_STATUS2_SCT_RST_Pos)                 /*!< RGU RESET_STATUS2: SCT_RST Mask     */
#define RGU_RESET_STATUS2_MOTOCONPWM_RST_Pos                  12                                                        /*!< RGU RESET_STATUS2: MOTOCONPWM_RST Position */
#define RGU_RESET_STATUS2_MOTOCONPWM_RST_Msk                  (0x03UL << RGU_RESET_STATUS2_MOTOCONPWM_RST_Pos)          /*!< RGU RESET_STATUS2: MOTOCONPWM_RST Mask */
#define RGU_RESET_STATUS2_QEI_RST_Pos                         14                                                        /*!< RGU RESET_STATUS2: QEI_RST Position */
#define RGU_RESET_STATUS2_QEI_RST_Msk                         (0x03UL << RGU_RESET_STATUS2_QEI_RST_Pos)                 /*!< RGU RESET_STATUS2: QEI_RST Mask     */
#define RGU_RESET_STATUS2_ADC0_RST_Pos                        16                                                        /*!< RGU RESET_STATUS2: ADC0_RST Position */
#define RGU_RESET_STATUS2_ADC0_RST_Msk                        (0x03UL << RGU_RESET_STATUS2_ADC0_RST_Pos)                /*!< RGU RESET_STATUS2: ADC0_RST Mask    */
#define RGU_RESET_STATUS2_ADC1_RST_Pos                        18                                                        /*!< RGU RESET_STATUS2: ADC1_RST Position */
#define RGU_RESET_STATUS2_ADC1_RST_Msk                        (0x03UL << RGU_RESET_STATUS2_ADC1_RST_Pos)                /*!< RGU RESET_STATUS2: ADC1_RST Mask    */
#define RGU_RESET_STATUS2_DAC_RST_Pos                         20                                                        /*!< RGU RESET_STATUS2: DAC_RST Position */
#define RGU_RESET_STATUS2_DAC_RST_Msk                         (0x03UL << RGU_RESET_STATUS2_DAC_RST_Pos)                 /*!< RGU RESET_STATUS2: DAC_RST Mask     */
#define RGU_RESET_STATUS2_UART0_RST_Pos                       24                                                        /*!< RGU RESET_STATUS2: UART0_RST Position */
#define RGU_RESET_STATUS2_UART0_RST_Msk                       (0x03UL << RGU_RESET_STATUS2_UART0_RST_Pos)               /*!< RGU RESET_STATUS2: UART0_RST Mask   */
#define RGU_RESET_STATUS2_UART1_RST_Pos                       26                                                        /*!< RGU RESET_STATUS2: UART1_RST Position */
#define RGU_RESET_STATUS2_UART1_RST_Msk                       (0x03UL << RGU_RESET_STATUS2_UART1_RST_Pos)               /*!< RGU RESET_STATUS2: UART1_RST Mask   */
#define RGU_RESET_STATUS2_UART2_RST_Pos                       28                                                        /*!< RGU RESET_STATUS2: UART2_RST Position */
#define RGU_RESET_STATUS2_UART2_RST_Msk                       (0x03UL << RGU_RESET_STATUS2_UART2_RST_Pos)               /*!< RGU RESET_STATUS2: UART2_RST Mask   */
#define RGU_RESET_STATUS2_UART3_RST_Pos                       30                                                        /*!< RGU RESET_STATUS2: UART3_RST Position */
#define RGU_RESET_STATUS2_UART3_RST_Msk                       (0x03UL << RGU_RESET_STATUS2_UART3_RST_Pos)               /*!< RGU RESET_STATUS2: UART3_RST Mask   */

// ------------------------------------  RGU_RESET_STATUS3  ---------------------------------------
#define RGU_RESET_STATUS3_I2C0_RST_Pos                        0                                                         /*!< RGU RESET_STATUS3: I2C0_RST Position */
#define RGU_RESET_STATUS3_I2C0_RST_Msk                        (0x03UL << RGU_RESET_STATUS3_I2C0_RST_Pos)                /*!< RGU RESET_STATUS3: I2C0_RST Mask    */
#define RGU_RESET_STATUS3_I2C1_RST_Pos                        2                                                         /*!< RGU RESET_STATUS3: I2C1_RST Position */
#define RGU_RESET_STATUS3_I2C1_RST_Msk                        (0x03UL << RGU_RESET_STATUS3_I2C1_RST_Pos)                /*!< RGU RESET_STATUS3: I2C1_RST Mask    */
#define RGU_RESET_STATUS3_SSP0_RST_Pos                        4                                                         /*!< RGU RESET_STATUS3: SSP0_RST Position */
#define RGU_RESET_STATUS3_SSP0_RST_Msk                        (0x03UL << RGU_RESET_STATUS3_SSP0_RST_Pos)                /*!< RGU RESET_STATUS3: SSP0_RST Mask    */
#define RGU_RESET_STATUS3_SSP1_RST_Pos                        6                                                         /*!< RGU RESET_STATUS3: SSP1_RST Position */
#define RGU_RESET_STATUS3_SSP1_RST_Msk                        (0x03UL << RGU_RESET_STATUS3_SSP1_RST_Pos)                /*!< RGU RESET_STATUS3: SSP1_RST Mask    */
#define RGU_RESET_STATUS3_I2S_RST_Pos                         8                                                         /*!< RGU RESET_STATUS3: I2S_RST Position */
#define RGU_RESET_STATUS3_I2S_RST_Msk                         (0x03UL << RGU_RESET_STATUS3_I2S_RST_Pos)                 /*!< RGU RESET_STATUS3: I2S_RST Mask     */
#define RGU_RESET_STATUS3_SPIFI_RST_Pos                       10                                                        /*!< RGU RESET_STATUS3: SPIFI_RST Position */
#define RGU_RESET_STATUS3_SPIFI_RST_Msk                       (0x03UL << RGU_RESET_STATUS3_SPIFI_RST_Pos)               /*!< RGU RESET_STATUS3: SPIFI_RST Mask   */
#define RGU_RESET_STATUS3_CAN1_RST_Pos                        12                                                        /*!< RGU RESET_STATUS3: CAN1_RST Position */
#define RGU_RESET_STATUS3_CAN1_RST_Msk                        (0x03UL << RGU_RESET_STATUS3_CAN1_RST_Pos)                /*!< RGU RESET_STATUS3: CAN1_RST Mask    */
#define RGU_RESET_STATUS3_CAN0_RST_Pos                        14                                                        /*!< RGU RESET_STATUS3: CAN0_RST Position */
#define RGU_RESET_STATUS3_CAN0_RST_Msk                        (0x03UL << RGU_RESET_STATUS3_CAN0_RST_Pos)                /*!< RGU RESET_STATUS3: CAN0_RST Mask    */
#define RGU_RESET_STATUS3_M0APP_RST_Pos                       16                                                        /*!< RGU RESET_STATUS3: M0APP_RST Position */
#define RGU_RESET_STATUS3_M0APP_RST_Msk                       (0x03UL << RGU_RESET_STATUS3_M0APP_RST_Pos)               /*!< RGU RESET_STATUS3: M0APP_RST Mask   */
#define RGU_RESET_STATUS3_SGPIO_RST_Pos                       18                                                        /*!< RGU RESET_STATUS3: SGPIO_RST Position */
#define RGU_RESET_STATUS3_SGPIO_RST_Msk                       (0x03UL << RGU_RESET_STATUS3_SGPIO_RST_Pos)               /*!< RGU RESET_STATUS3: SGPIO_RST Mask   */
#define RGU_RESET_STATUS3_SPI_RST_Pos                         20                                                        /*!< RGU RESET_STATUS3: SPI_RST Position */
#define RGU_RESET_STATUS3_SPI_RST_Msk                         (0x03UL << RGU_RESET_STATUS3_SPI_RST_Pos)                 /*!< RGU RESET_STATUS3: SPI_RST Mask     */

// --------------------------------  RGU_RESET_ACTIVE_STATUS0  ------------------------------------
#define RGU_RESET_ACTIVE_STATUS0_CORE_RST_Pos                 0                                                         /*!< RGU RESET_ACTIVE_STATUS0: CORE_RST Position */
#define RGU_RESET_ACTIVE_STATUS0_CORE_RST_Msk                 (0x01UL << RGU_RESET_ACTIVE_STATUS0_CORE_RST_Pos)         /*!< RGU RESET_ACTIVE_STATUS0: CORE_RST Mask */
#define RGU_RESET_ACTIVE_STATUS0_PERIPH_RST_Pos               1                                                         /*!< RGU RESET_ACTIVE_STATUS0: PERIPH_RST Position */
#define RGU_RESET_ACTIVE_STATUS0_PERIPH_RST_Msk               (0x01UL << RGU_RESET_ACTIVE_STATUS0_PERIPH_RST_Pos)       /*!< RGU RESET_ACTIVE_STATUS0: PERIPH_RST Mask */
#define RGU_RESET_ACTIVE_STATUS0_MASTER_RST_Pos               2                                                         /*!< RGU RESET_ACTIVE_STATUS0: MASTER_RST Position */
#define RGU_RESET_ACTIVE_STATUS0_MASTER_RST_Msk               (0x01UL << RGU_RESET_ACTIVE_STATUS0_MASTER_RST_Pos)       /*!< RGU RESET_ACTIVE_STATUS0: MASTER_RST Mask */
#define RGU_RESET_ACTIVE_STATUS0_WWDT_RST_Pos                 4                                                         /*!< RGU RESET_ACTIVE_STATUS0: WWDT_RST Position */
#define RGU_RESET_ACTIVE_STATUS0_WWDT_RST_Msk                 (0x01UL << RGU_RESET_ACTIVE_STATUS0_WWDT_RST_Pos)         /*!< RGU RESET_ACTIVE_STATUS0: WWDT_RST Mask */
#define RGU_RESET_ACTIVE_STATUS0_CREG_RST_Pos                 5                                                         /*!< RGU RESET_ACTIVE_STATUS0: CREG_RST Position */
#define RGU_RESET_ACTIVE_STATUS0_CREG_RST_Msk                 (0x01UL << RGU_RESET_ACTIVE_STATUS0_CREG_RST_Pos)         /*!< RGU RESET_ACTIVE_STATUS0: CREG_RST Mask */
#define RGU_RESET_ACTIVE_STATUS0_BUS_RST_Pos                  8                                                         /*!< RGU RESET_ACTIVE_STATUS0: BUS_RST Position */
#define RGU_RESET_ACTIVE_STATUS0_BUS_RST_Msk                  (0x01UL << RGU_RESET_ACTIVE_STATUS0_BUS_RST_Pos)          /*!< RGU RESET_ACTIVE_STATUS0: BUS_RST Mask */
#define RGU_RESET_ACTIVE_STATUS0_SCU_RST_Pos                  9                                                         /*!< RGU RESET_ACTIVE_STATUS0: SCU_RST Position */
#define RGU_RESET_ACTIVE_STATUS0_SCU_RST_Msk                  (0x01UL << RGU_RESET_ACTIVE_STATUS0_SCU_RST_Pos)          /*!< RGU RESET_ACTIVE_STATUS0: SCU_RST Mask */
#define RGU_RESET_ACTIVE_STATUS0_PINMUX_RST_Pos               10                                                        /*!< RGU RESET_ACTIVE_STATUS0: PINMUX_RST Position */
#define RGU_RESET_ACTIVE_STATUS0_PINMUX_RST_Msk               (0x01UL << RGU_RESET_ACTIVE_STATUS0_PINMUX_RST_Pos)       /*!< RGU RESET_ACTIVE_STATUS0: PINMUX_RST Mask */
#define RGU_RESET_ACTIVE_STATUS0_M3_RST_Pos                   13                                                        /*!< RGU RESET_ACTIVE_STATUS0: M3_RST Position */
#define RGU_RESET_ACTIVE_STATUS0_M3_RST_Msk                   (0x01UL << RGU_RESET_ACTIVE_STATUS0_M3_RST_Pos)           /*!< RGU RESET_ACTIVE_STATUS0: M3_RST Mask */
#define RGU_RESET_ACTIVE_STATUS0_LCD_RST_Pos                  16                                                        /*!< RGU RESET_ACTIVE_STATUS0: LCD_RST Position */
#define RGU_RESET_ACTIVE_STATUS0_LCD_RST_Msk                  (0x01UL << RGU_RESET_ACTIVE_STATUS0_LCD_RST_Pos)          /*!< RGU RESET_ACTIVE_STATUS0: LCD_RST Mask */
#define RGU_RESET_ACTIVE_STATUS0_USB0_RST_Pos                 17                                                        /*!< RGU RESET_ACTIVE_STATUS0: USB0_RST Position */
#define RGU_RESET_ACTIVE_STATUS0_USB0_RST_Msk                 (0x01UL << RGU_RESET_ACTIVE_STATUS0_USB0_RST_Pos)         /*!< RGU RESET_ACTIVE_STATUS0: USB0_RST Mask */
#define RGU_RESET_ACTIVE_STATUS0_USB1_RST_Pos                 18                                                        /*!< RGU RESET_ACTIVE_STATUS0: USB1_RST Position */
#define RGU_RESET_ACTIVE_STATUS0_USB1_RST_Msk                 (0x01UL << RGU_RESET_ACTIVE_STATUS0_USB1_RST_Pos)         /*!< RGU RESET_ACTIVE_STATUS0: USB1_RST Mask */
#define RGU_RESET_ACTIVE_STATUS0_DMA_RST_Pos                  19                                                        /*!< RGU RESET_ACTIVE_STATUS0: DMA_RST Position */
#define RGU_RESET_ACTIVE_STATUS0_DMA_RST_Msk                  (0x01UL << RGU_RESET_ACTIVE_STATUS0_DMA_RST_Pos)          /*!< RGU RESET_ACTIVE_STATUS0: DMA_RST Mask */
#define RGU_RESET_ACTIVE_STATUS0_SDIO_RST_Pos                 20                                                        /*!< RGU RESET_ACTIVE_STATUS0: SDIO_RST Position */
#define RGU_RESET_ACTIVE_STATUS0_SDIO_RST_Msk                 (0x01UL << RGU_RESET_ACTIVE_STATUS0_SDIO_RST_Pos)         /*!< RGU RESET_ACTIVE_STATUS0: SDIO_RST Mask */
#define RGU_RESET_ACTIVE_STATUS0_EMC_RST_Pos                  21                                                        /*!< RGU RESET_ACTIVE_STATUS0: EMC_RST Position */
#define RGU_RESET_ACTIVE_STATUS0_EMC_RST_Msk                  (0x01UL << RGU_RESET_ACTIVE_STATUS0_EMC_RST_Pos)          /*!< RGU RESET_ACTIVE_STATUS0: EMC_RST Mask */
#define RGU_RESET_ACTIVE_STATUS0_ETHERNET_RST_Pos             22                                                        /*!< RGU RESET_ACTIVE_STATUS0: ETHERNET_RST Position */
#define RGU_RESET_ACTIVE_STATUS0_ETHERNET_RST_Msk             (0x01UL << RGU_RESET_ACTIVE_STATUS0_ETHERNET_RST_Pos)     /*!< RGU RESET_ACTIVE_STATUS0: ETHERNET_RST Mask */
#define RGU_RESET_ACTIVE_STATUS0_GPIO_RST_Pos                 28                                                        /*!< RGU RESET_ACTIVE_STATUS0: GPIO_RST Position */
#define RGU_RESET_ACTIVE_STATUS0_GPIO_RST_Msk                 (0x01UL << RGU_RESET_ACTIVE_STATUS0_GPIO_RST_Pos)         /*!< RGU RESET_ACTIVE_STATUS0: GPIO_RST Mask */

// --------------------------------  RGU_RESET_ACTIVE_STATUS1  ------------------------------------
#define RGU_RESET_ACTIVE_STATUS1_TIMER0_RST_Pos               0                                                         /*!< RGU RESET_ACTIVE_STATUS1: TIMER0_RST Position */
#define RGU_RESET_ACTIVE_STATUS1_TIMER0_RST_Msk               (0x01UL << RGU_RESET_ACTIVE_STATUS1_TIMER0_RST_Pos)       /*!< RGU RESET_ACTIVE_STATUS1: TIMER0_RST Mask */
#define RGU_RESET_ACTIVE_STATUS1_TIMER1_RST_Pos               1                                                         /*!< RGU RESET_ACTIVE_STATUS1: TIMER1_RST Position */
#define RGU_RESET_ACTIVE_STATUS1_TIMER1_RST_Msk               (0x01UL << RGU_RESET_ACTIVE_STATUS1_TIMER1_RST_Pos)       /*!< RGU RESET_ACTIVE_STATUS1: TIMER1_RST Mask */
#define RGU_RESET_ACTIVE_STATUS1_TIMER2_RST_Pos               2                                                         /*!< RGU RESET_ACTIVE_STATUS1: TIMER2_RST Position */
#define RGU_RESET_ACTIVE_STATUS1_TIMER2_RST_Msk               (0x01UL << RGU_RESET_ACTIVE_STATUS1_TIMER2_RST_Pos)       /*!< RGU RESET_ACTIVE_STATUS1: TIMER2_RST Mask */
#define RGU_RESET_ACTIVE_STATUS1_TIMER3_RST_Pos               3                                                         /*!< RGU RESET_ACTIVE_STATUS1: TIMER3_RST Position */
#define RGU_RESET_ACTIVE_STATUS1_TIMER3_RST_Msk               (0x01UL << RGU_RESET_ACTIVE_STATUS1_TIMER3_RST_Pos)       /*!< RGU RESET_ACTIVE_STATUS1: TIMER3_RST Mask */
#define RGU_RESET_ACTIVE_STATUS1_RITIMER_RST_Pos              4                                                         /*!< RGU RESET_ACTIVE_STATUS1: RITIMER_RST Position */
#define RGU_RESET_ACTIVE_STATUS1_RITIMER_RST_Msk              (0x01UL << RGU_RESET_ACTIVE_STATUS1_RITIMER_RST_Pos)      /*!< RGU RESET_ACTIVE_STATUS1: RITIMER_RST Mask */
#define RGU_RESET_ACTIVE_STATUS1_SCT_RST_Pos                  5                                                         /*!< RGU RESET_ACTIVE_STATUS1: SCT_RST Position */
#define RGU_RESET_ACTIVE_STATUS1_SCT_RST_Msk                  (0x01UL << RGU_RESET_ACTIVE_STATUS1_SCT_RST_Pos)          /*!< RGU RESET_ACTIVE_STATUS1: SCT_RST Mask */
#define RGU_RESET_ACTIVE_STATUS1_MOTOCONPWM_RST_Pos           6                                                         /*!< RGU RESET_ACTIVE_STATUS1: MOTOCONPWM_RST Position */
#define RGU_RESET_ACTIVE_STATUS1_MOTOCONPWM_RST_Msk           (0x01UL << RGU_RESET_ACTIVE_STATUS1_MOTOCONPWM_RST_Pos)   /*!< RGU RESET_ACTIVE_STATUS1: MOTOCONPWM_RST Mask */
#define RGU_RESET_ACTIVE_STATUS1_QEI_RST_Pos                  7                                                         /*!< RGU RESET_ACTIVE_STATUS1: QEI_RST Position */
#define RGU_RESET_ACTIVE_STATUS1_QEI_RST_Msk                  (0x01UL << RGU_RESET_ACTIVE_STATUS1_QEI_RST_Pos)          /*!< RGU RESET_ACTIVE_STATUS1: QEI_RST Mask */
#define RGU_RESET_ACTIVE_STATUS1_ADC0_RST_Pos                 8                                                         /*!< RGU RESET_ACTIVE_STATUS1: ADC0_RST Position */
#define RGU_RESET_ACTIVE_STATUS1_ADC0_RST_Msk                 (0x01UL << RGU_RESET_ACTIVE_STATUS1_ADC0_RST_Pos)         /*!< RGU RESET_ACTIVE_STATUS1: ADC0_RST Mask */
#define RGU_RESET_ACTIVE_STATUS1_ADC1_RST_Pos                 9                                                         /*!< RGU RESET_ACTIVE_STATUS1: ADC1_RST Position */
#define RGU_RESET_ACTIVE_STATUS1_ADC1_RST_Msk                 (0x01UL << RGU_RESET_ACTIVE_STATUS1_ADC1_RST_Pos)         /*!< RGU RESET_ACTIVE_STATUS1: ADC1_RST Mask */
#define RGU_RESET_ACTIVE_STATUS1_DAC_RST_Pos                  10                                                        /*!< RGU RESET_ACTIVE_STATUS1: DAC_RST Position */
#define RGU_RESET_ACTIVE_STATUS1_DAC_RST_Msk                  (0x01UL << RGU_RESET_ACTIVE_STATUS1_DAC_RST_Pos)          /*!< RGU RESET_ACTIVE_STATUS1: DAC_RST Mask */
#define RGU_RESET_ACTIVE_STATUS1_UART0_RST_Pos                12                                                        /*!< RGU RESET_ACTIVE_STATUS1: UART0_RST Position */
#define RGU_RESET_ACTIVE_STATUS1_UART0_RST_Msk                (0x01UL << RGU_RESET_ACTIVE_STATUS1_UART0_RST_Pos)        /*!< RGU RESET_ACTIVE_STATUS1: UART0_RST Mask */
#define RGU_RESET_ACTIVE_STATUS1_UART1_RST_Pos                13                                                        /*!< RGU RESET_ACTIVE_STATUS1: UART1_RST Position */
#define RGU_RESET_ACTIVE_STATUS1_UART1_RST_Msk                (0x01UL << RGU_RESET_ACTIVE_STATUS1_UART1_RST_Pos)        /*!< RGU RESET_ACTIVE_STATUS1: UART1_RST Mask */
#define RGU_RESET_ACTIVE_STATUS1_UART2_RST_Pos                14                                                        /*!< RGU RESET_ACTIVE_STATUS1: UART2_RST Position */
#define RGU_RESET_ACTIVE_STATUS1_UART2_RST_Msk                (0x01UL << RGU_RESET_ACTIVE_STATUS1_UART2_RST_Pos)        /*!< RGU RESET_ACTIVE_STATUS1: UART2_RST Mask */
#define RGU_RESET_ACTIVE_STATUS1_UART3_RST_Pos                15                                                        /*!< RGU RESET_ACTIVE_STATUS1: UART3_RST Position */
#define RGU_RESET_ACTIVE_STATUS1_UART3_RST_Msk                (0x01UL << RGU_RESET_ACTIVE_STATUS1_UART3_RST_Pos)        /*!< RGU RESET_ACTIVE_STATUS1: UART3_RST Mask */
#define RGU_RESET_ACTIVE_STATUS1_I2C0_RST_Pos                 16                                                        /*!< RGU RESET_ACTIVE_STATUS1: I2C0_RST Position */
#define RGU_RESET_ACTIVE_STATUS1_I2C0_RST_Msk                 (0x01UL << RGU_RESET_ACTIVE_STATUS1_I2C0_RST_Pos)         /*!< RGU RESET_ACTIVE_STATUS1: I2C0_RST Mask */
#define RGU_RESET_ACTIVE_STATUS1_I2C1_RST_Pos                 17                                                        /*!< RGU RESET_ACTIVE_STATUS1: I2C1_RST Position */
#define RGU_RESET_ACTIVE_STATUS1_I2C1_RST_Msk                 (0x01UL << RGU_RESET_ACTIVE_STATUS1_I2C1_RST_Pos)         /*!< RGU RESET_ACTIVE_STATUS1: I2C1_RST Mask */
#define RGU_RESET_ACTIVE_STATUS1_SSP0_RST_Pos                 18                                                        /*!< RGU RESET_ACTIVE_STATUS1: SSP0_RST Position */
#define RGU_RESET_ACTIVE_STATUS1_SSP0_RST_Msk                 (0x01UL << RGU_RESET_ACTIVE_STATUS1_SSP0_RST_Pos)         /*!< RGU RESET_ACTIVE_STATUS1: SSP0_RST Mask */
#define RGU_RESET_ACTIVE_STATUS1_SSP1_RST_Pos                 19                                                        /*!< RGU RESET_ACTIVE_STATUS1: SSP1_RST Position */
#define RGU_RESET_ACTIVE_STATUS1_SSP1_RST_Msk                 (0x01UL << RGU_RESET_ACTIVE_STATUS1_SSP1_RST_Pos)         /*!< RGU RESET_ACTIVE_STATUS1: SSP1_RST Mask */
#define RGU_RESET_ACTIVE_STATUS1_I2S_RST_Pos                  20                                                        /*!< RGU RESET_ACTIVE_STATUS1: I2S_RST Position */
#define RGU_RESET_ACTIVE_STATUS1_I2S_RST_Msk                  (0x01UL << RGU_RESET_ACTIVE_STATUS1_I2S_RST_Pos)          /*!< RGU RESET_ACTIVE_STATUS1: I2S_RST Mask */
#define RGU_RESET_ACTIVE_STATUS1_SPIFI_RST_Pos                21                                                        /*!< RGU RESET_ACTIVE_STATUS1: SPIFI_RST Position */
#define RGU_RESET_ACTIVE_STATUS1_SPIFI_RST_Msk                (0x01UL << RGU_RESET_ACTIVE_STATUS1_SPIFI_RST_Pos)        /*!< RGU RESET_ACTIVE_STATUS1: SPIFI_RST Mask */
#define RGU_RESET_ACTIVE_STATUS1_CAN1_RST_Pos                 22                                                        /*!< RGU RESET_ACTIVE_STATUS1: CAN1_RST Position */
#define RGU_RESET_ACTIVE_STATUS1_CAN1_RST_Msk                 (0x01UL << RGU_RESET_ACTIVE_STATUS1_CAN1_RST_Pos)         /*!< RGU RESET_ACTIVE_STATUS1: CAN1_RST Mask */
#define RGU_RESET_ACTIVE_STATUS1_CAN0_RST_Pos                 23                                                        /*!< RGU RESET_ACTIVE_STATUS1: CAN0_RST Position */
#define RGU_RESET_ACTIVE_STATUS1_CAN0_RST_Msk                 (0x01UL << RGU_RESET_ACTIVE_STATUS1_CAN0_RST_Pos)         /*!< RGU RESET_ACTIVE_STATUS1: CAN0_RST Mask */
#define RGU_RESET_ACTIVE_STATUS1_MOAPP_RST_Pos                24                                                        /*!< RGU RESET_ACTIVE_STATUS1: MOAPP_RST Position */
#define RGU_RESET_ACTIVE_STATUS1_MOAPP_RST_Msk                (0x01UL << RGU_RESET_ACTIVE_STATUS1_MOAPP_RST_Pos)        /*!< RGU RESET_ACTIVE_STATUS1: MOAPP_RST Mask */
#define RGU_RESET_ACTIVE_STATUS1_SGPIO_RST_Pos                25                                                        /*!< RGU RESET_ACTIVE_STATUS1: SGPIO_RST Position */
#define RGU_RESET_ACTIVE_STATUS1_SGPIO_RST_Msk                (0x01UL << RGU_RESET_ACTIVE_STATUS1_SGPIO_RST_Pos)        /*!< RGU RESET_ACTIVE_STATUS1: SGPIO_RST Mask */
#define RGU_RESET_ACTIVE_STATUS1_SPI_RST_Pos                  26                                                        /*!< RGU RESET_ACTIVE_STATUS1: SPI_RST Position */
#define RGU_RESET_ACTIVE_STATUS1_SPI_RST_Msk                  (0x01UL << RGU_RESET_ACTIVE_STATUS1_SPI_RST_Pos)          /*!< RGU RESET_ACTIVE_STATUS1: SPI_RST Mask */

// -----------------------------------  RGU_RESET_EXT_STAT0  --------------------------------------
#define RGU_RESET_EXT_STAT0_EXT_RESET_Pos                     0                                                         /*!< RGU RESET_EXT_STAT0: EXT_RESET Position */
#define RGU_RESET_EXT_STAT0_EXT_RESET_Msk                     (0x01UL << RGU_RESET_EXT_STAT0_EXT_RESET_Pos)             /*!< RGU RESET_EXT_STAT0: EXT_RESET Mask */
#define RGU_RESET_EXT_STAT0_BOD_RESET_Pos                     4                                                         /*!< RGU RESET_EXT_STAT0: BOD_RESET Position */
#define RGU_RESET_EXT_STAT0_BOD_RESET_Msk                     (0x01UL << RGU_RESET_EXT_STAT0_BOD_RESET_Pos)             /*!< RGU RESET_EXT_STAT0: BOD_RESET Mask */
#define RGU_RESET_EXT_STAT0_WWDT_RESET_Pos                    5                                                         /*!< RGU RESET_EXT_STAT0: WWDT_RESET Position */
#define RGU_RESET_EXT_STAT0_WWDT_RESET_Msk                    (0x01UL << RGU_RESET_EXT_STAT0_WWDT_RESET_Pos)            /*!< RGU RESET_EXT_STAT0: WWDT_RESET Mask */

// -----------------------------------  RGU_RESET_EXT_STAT1  --------------------------------------
#define RGU_RESET_EXT_STAT1_CORE_RESET_Pos                    1                                                         /*!< RGU RESET_EXT_STAT1: CORE_RESET Position */
#define RGU_RESET_EXT_STAT1_CORE_RESET_Msk                    (0x01UL << RGU_RESET_EXT_STAT1_CORE_RESET_Pos)            /*!< RGU RESET_EXT_STAT1: CORE_RESET Mask */

// -----------------------------------  RGU_RESET_EXT_STAT2  --------------------------------------
#define RGU_RESET_EXT_STAT2_PERIPHERAL_RESET_Pos              2                                                         /*!< RGU RESET_EXT_STAT2: PERIPHERAL_RESET Position */
#define RGU_RESET_EXT_STAT2_PERIPHERAL_RESET_Msk              (0x01UL << RGU_RESET_EXT_STAT2_PERIPHERAL_RESET_Pos)      /*!< RGU RESET_EXT_STAT2: PERIPHERAL_RESET Mask */

// -----------------------------------  RGU_RESET_EXT_STAT4  --------------------------------------
#define RGU_RESET_EXT_STAT4_CORE_RESET_Pos                    1                                                         /*!< RGU RESET_EXT_STAT4: CORE_RESET Position */
#define RGU_RESET_EXT_STAT4_CORE_RESET_Msk                    (0x01UL << RGU_RESET_EXT_STAT4_CORE_RESET_Pos)            /*!< RGU RESET_EXT_STAT4: CORE_RESET Mask */

// -----------------------------------  RGU_RESET_EXT_STAT5  --------------------------------------
#define RGU_RESET_EXT_STAT5_CORE_RESET_Pos                    1                                                         /*!< RGU RESET_EXT_STAT5: CORE_RESET Position */
#define RGU_RESET_EXT_STAT5_CORE_RESET_Msk                    (0x01UL << RGU_RESET_EXT_STAT5_CORE_RESET_Pos)            /*!< RGU RESET_EXT_STAT5: CORE_RESET Mask */

// -----------------------------------  RGU_RESET_EXT_STAT8  --------------------------------------
#define RGU_RESET_EXT_STAT8_PERIPHERAL_RESET_Pos              2                                                         /*!< RGU RESET_EXT_STAT8: PERIPHERAL_RESET Position */
#define RGU_RESET_EXT_STAT8_PERIPHERAL_RESET_Msk              (0x01UL << RGU_RESET_EXT_STAT8_PERIPHERAL_RESET_Pos)      /*!< RGU RESET_EXT_STAT8: PERIPHERAL_RESET Mask */

// -----------------------------------  RGU_RESET_EXT_STAT9  --------------------------------------
#define RGU_RESET_EXT_STAT9_PERIPHERAL_RESET_Pos              2                                                         /*!< RGU RESET_EXT_STAT9: PERIPHERAL_RESET Position */
#define RGU_RESET_EXT_STAT9_PERIPHERAL_RESET_Msk              (0x01UL << RGU_RESET_EXT_STAT9_PERIPHERAL_RESET_Pos)      /*!< RGU RESET_EXT_STAT9: PERIPHERAL_RESET Mask */

// ----------------------------------  RGU_RESET_EXT_STAT13  --------------------------------------
#define RGU_RESET_EXT_STAT13_MASTER_RESET_Pos                 3                                                         /*!< RGU RESET_EXT_STAT13: MASTER_RESET Position */
#define RGU_RESET_EXT_STAT13_MASTER_RESET_Msk                 (0x01UL << RGU_RESET_EXT_STAT13_MASTER_RESET_Pos)         /*!< RGU RESET_EXT_STAT13: MASTER_RESET Mask */

// ----------------------------------  RGU_RESET_EXT_STAT16  --------------------------------------
#define RGU_RESET_EXT_STAT16_MASTER_RESET_Pos                 3                                                         /*!< RGU RESET_EXT_STAT16: MASTER_RESET Position */
#define RGU_RESET_EXT_STAT16_MASTER_RESET_Msk                 (0x01UL << RGU_RESET_EXT_STAT16_MASTER_RESET_Pos)         /*!< RGU RESET_EXT_STAT16: MASTER_RESET Mask */

// ----------------------------------  RGU_RESET_EXT_STAT17  --------------------------------------
#define RGU_RESET_EXT_STAT17_MASTER_RESET_Pos                 3                                                         /*!< RGU RESET_EXT_STAT17: MASTER_RESET Position */
#define RGU_RESET_EXT_STAT17_MASTER_RESET_Msk                 (0x01UL << RGU_RESET_EXT_STAT17_MASTER_RESET_Pos)         /*!< RGU RESET_EXT_STAT17: MASTER_RESET Mask */

// ----------------------------------  RGU_RESET_EXT_STAT18  --------------------------------------
#define RGU_RESET_EXT_STAT18_MASTER_RESET_Pos                 3                                                         /*!< RGU RESET_EXT_STAT18: MASTER_RESET Position */
#define RGU_RESET_EXT_STAT18_MASTER_RESET_Msk                 (0x01UL << RGU_RESET_EXT_STAT18_MASTER_RESET_Pos)         /*!< RGU RESET_EXT_STAT18: MASTER_RESET Mask */

// ----------------------------------  RGU_RESET_EXT_STAT19  --------------------------------------
#define RGU_RESET_EXT_STAT19_MASTER_RESET_Pos                 3                                                         /*!< RGU RESET_EXT_STAT19: MASTER_RESET Position */
#define RGU_RESET_EXT_STAT19_MASTER_RESET_Msk                 (0x01UL << RGU_RESET_EXT_STAT19_MASTER_RESET_Pos)         /*!< RGU RESET_EXT_STAT19: MASTER_RESET Mask */

// ----------------------------------  RGU_RESET_EXT_STAT20  --------------------------------------
#define RGU_RESET_EXT_STAT20_MASTER_RESET_Pos                 3                                                         /*!< RGU RESET_EXT_STAT20: MASTER_RESET Position */
#define RGU_RESET_EXT_STAT20_MASTER_RESET_Msk                 (0x01UL << RGU_RESET_EXT_STAT20_MASTER_RESET_Pos)         /*!< RGU RESET_EXT_STAT20: MASTER_RESET Mask */

// ----------------------------------  RGU_RESET_EXT_STAT21  --------------------------------------
#define RGU_RESET_EXT_STAT21_MASTER_RESET_Pos                 3                                                         /*!< RGU RESET_EXT_STAT21: MASTER_RESET Position */
#define RGU_RESET_EXT_STAT21_MASTER_RESET_Msk                 (0x01UL << RGU_RESET_EXT_STAT21_MASTER_RESET_Pos)         /*!< RGU RESET_EXT_STAT21: MASTER_RESET Mask */

// ----------------------------------  RGU_RESET_EXT_STAT22  --------------------------------------
#define RGU_RESET_EXT_STAT22_MASTER_RESET_Pos                 3                                                         /*!< RGU RESET_EXT_STAT22: MASTER_RESET Position */
#define RGU_RESET_EXT_STAT22_MASTER_RESET_Msk                 (0x01UL << RGU_RESET_EXT_STAT22_MASTER_RESET_Pos)         /*!< RGU RESET_EXT_STAT22: MASTER_RESET Mask */

// ----------------------------------  RGU_RESET_EXT_STAT23  --------------------------------------
#define RGU_RESET_EXT_STAT23_MASTER_RESET_Pos                 3                                                         /*!< RGU RESET_EXT_STAT23: MASTER_RESET Position */
#define RGU_RESET_EXT_STAT23_MASTER_RESET_Msk                 (0x01UL << RGU_RESET_EXT_STAT23_MASTER_RESET_Pos)         /*!< RGU RESET_EXT_STAT23: MASTER_RESET Mask */

// ----------------------------------  RGU_RESET_EXT_STAT28  --------------------------------------
#define RGU_RESET_EXT_STAT28_PERIPHERAL_RESET_Pos             2                                                         /*!< RGU RESET_EXT_STAT28: PERIPHERAL_RESET Position */
#define RGU_RESET_EXT_STAT28_PERIPHERAL_RESET_Msk             (0x01UL << RGU_RESET_EXT_STAT28_PERIPHERAL_RESET_Pos)     /*!< RGU RESET_EXT_STAT28: PERIPHERAL_RESET Mask */

// ----------------------------------  RGU_RESET_EXT_STAT32  --------------------------------------
#define RGU_RESET_EXT_STAT32_PERIPHERAL_RESET_Pos             2                                                         /*!< RGU RESET_EXT_STAT32: PERIPHERAL_RESET Position */
#define RGU_RESET_EXT_STAT32_PERIPHERAL_RESET_Msk             (0x01UL << RGU_RESET_EXT_STAT32_PERIPHERAL_RESET_Pos)     /*!< RGU RESET_EXT_STAT32: PERIPHERAL_RESET Mask */

// ----------------------------------  RGU_RESET_EXT_STAT33  --------------------------------------
#define RGU_RESET_EXT_STAT33_PERIPHERAL_RESET_Pos             2                                                         /*!< RGU RESET_EXT_STAT33: PERIPHERAL_RESET Position */
#define RGU_RESET_EXT_STAT33_PERIPHERAL_RESET_Msk             (0x01UL << RGU_RESET_EXT_STAT33_PERIPHERAL_RESET_Pos)     /*!< RGU RESET_EXT_STAT33: PERIPHERAL_RESET Mask */

// ----------------------------------  RGU_RESET_EXT_STAT34  --------------------------------------
#define RGU_RESET_EXT_STAT34_PERIPHERAL_RESET_Pos             2                                                         /*!< RGU RESET_EXT_STAT34: PERIPHERAL_RESET Position */
#define RGU_RESET_EXT_STAT34_PERIPHERAL_RESET_Msk             (0x01UL << RGU_RESET_EXT_STAT34_PERIPHERAL_RESET_Pos)     /*!< RGU RESET_EXT_STAT34: PERIPHERAL_RESET Mask */

// ----------------------------------  RGU_RESET_EXT_STAT35  --------------------------------------
#define RGU_RESET_EXT_STAT35_PERIPHERAL_RESET_Pos             2                                                         /*!< RGU RESET_EXT_STAT35: PERIPHERAL_RESET Position */
#define RGU_RESET_EXT_STAT35_PERIPHERAL_RESET_Msk             (0x01UL << RGU_RESET_EXT_STAT35_PERIPHERAL_RESET_Pos)     /*!< RGU RESET_EXT_STAT35: PERIPHERAL_RESET Mask */

// ----------------------------------  RGU_RESET_EXT_STAT36  --------------------------------------
#define RGU_RESET_EXT_STAT36_PERIPHERAL_RESET_Pos             2                                                         /*!< RGU RESET_EXT_STAT36: PERIPHERAL_RESET Position */
#define RGU_RESET_EXT_STAT36_PERIPHERAL_RESET_Msk             (0x01UL << RGU_RESET_EXT_STAT36_PERIPHERAL_RESET_Pos)     /*!< RGU RESET_EXT_STAT36: PERIPHERAL_RESET Mask */

// ----------------------------------  RGU_RESET_EXT_STAT37  --------------------------------------
#define RGU_RESET_EXT_STAT37_PERIPHERAL_RESET_Pos             2                                                         /*!< RGU RESET_EXT_STAT37: PERIPHERAL_RESET Position */
#define RGU_RESET_EXT_STAT37_PERIPHERAL_RESET_Msk             (0x01UL << RGU_RESET_EXT_STAT37_PERIPHERAL_RESET_Pos)     /*!< RGU RESET_EXT_STAT37: PERIPHERAL_RESET Mask */

// ----------------------------------  RGU_RESET_EXT_STAT38  --------------------------------------
#define RGU_RESET_EXT_STAT38_PERIPHERAL_RESET_Pos             2                                                         /*!< RGU RESET_EXT_STAT38: PERIPHERAL_RESET Position */
#define RGU_RESET_EXT_STAT38_PERIPHERAL_RESET_Msk             (0x01UL << RGU_RESET_EXT_STAT38_PERIPHERAL_RESET_Pos)     /*!< RGU RESET_EXT_STAT38: PERIPHERAL_RESET Mask */

// ----------------------------------  RGU_RESET_EXT_STAT39  --------------------------------------
#define RGU_RESET_EXT_STAT39_PERIPHERAL_RESET_Pos             2                                                         /*!< RGU RESET_EXT_STAT39: PERIPHERAL_RESET Position */
#define RGU_RESET_EXT_STAT39_PERIPHERAL_RESET_Msk             (0x01UL << RGU_RESET_EXT_STAT39_PERIPHERAL_RESET_Pos)     /*!< RGU RESET_EXT_STAT39: PERIPHERAL_RESET Mask */

// ----------------------------------  RGU_RESET_EXT_STAT40  --------------------------------------
#define RGU_RESET_EXT_STAT40_PERIPHERAL_RESET_Pos             2                                                         /*!< RGU RESET_EXT_STAT40: PERIPHERAL_RESET Position */
#define RGU_RESET_EXT_STAT40_PERIPHERAL_RESET_Msk             (0x01UL << RGU_RESET_EXT_STAT40_PERIPHERAL_RESET_Pos)     /*!< RGU RESET_EXT_STAT40: PERIPHERAL_RESET Mask */

// ----------------------------------  RGU_RESET_EXT_STAT41  --------------------------------------
#define RGU_RESET_EXT_STAT41_PERIPHERAL_RESET_Pos             2                                                         /*!< RGU RESET_EXT_STAT41: PERIPHERAL_RESET Position */
#define RGU_RESET_EXT_STAT41_PERIPHERAL_RESET_Msk             (0x01UL << RGU_RESET_EXT_STAT41_PERIPHERAL_RESET_Pos)     /*!< RGU RESET_EXT_STAT41: PERIPHERAL_RESET Mask */

// ----------------------------------  RGU_RESET_EXT_STAT42  --------------------------------------
#define RGU_RESET_EXT_STAT42_PERIPHERAL_RESET_Pos             2                                                         /*!< RGU RESET_EXT_STAT42: PERIPHERAL_RESET Position */
#define RGU_RESET_EXT_STAT42_PERIPHERAL_RESET_Msk             (0x01UL << RGU_RESET_EXT_STAT42_PERIPHERAL_RESET_Pos)     /*!< RGU RESET_EXT_STAT42: PERIPHERAL_RESET Mask */

// ----------------------------------  RGU_RESET_EXT_STAT44  --------------------------------------
#define RGU_RESET_EXT_STAT44_PERIPHERAL_RESET_Pos             2                                                         /*!< RGU RESET_EXT_STAT44: PERIPHERAL_RESET Position */
#define RGU_RESET_EXT_STAT44_PERIPHERAL_RESET_Msk             (0x01UL << RGU_RESET_EXT_STAT44_PERIPHERAL_RESET_Pos)     /*!< RGU RESET_EXT_STAT44: PERIPHERAL_RESET Mask */

// ----------------------------------  RGU_RESET_EXT_STAT45  --------------------------------------
#define RGU_RESET_EXT_STAT45_PERIPHERAL_RESET_Pos             2                                                         /*!< RGU RESET_EXT_STAT45: PERIPHERAL_RESET Position */
#define RGU_RESET_EXT_STAT45_PERIPHERAL_RESET_Msk             (0x01UL << RGU_RESET_EXT_STAT45_PERIPHERAL_RESET_Pos)     /*!< RGU RESET_EXT_STAT45: PERIPHERAL_RESET Mask */

// ----------------------------------  RGU_RESET_EXT_STAT46  --------------------------------------
#define RGU_RESET_EXT_STAT46_PERIPHERAL_RESET_Pos             2                                                         /*!< RGU RESET_EXT_STAT46: PERIPHERAL_RESET Position */
#define RGU_RESET_EXT_STAT46_PERIPHERAL_RESET_Msk             (0x01UL << RGU_RESET_EXT_STAT46_PERIPHERAL_RESET_Pos)     /*!< RGU RESET_EXT_STAT46: PERIPHERAL_RESET Mask */

// ----------------------------------  RGU_RESET_EXT_STAT47  --------------------------------------
#define RGU_RESET_EXT_STAT47_PERIPHERAL_RESET_Pos             2                                                         /*!< RGU RESET_EXT_STAT47: PERIPHERAL_RESET Position */
#define RGU_RESET_EXT_STAT47_PERIPHERAL_RESET_Msk             (0x01UL << RGU_RESET_EXT_STAT47_PERIPHERAL_RESET_Pos)     /*!< RGU RESET_EXT_STAT47: PERIPHERAL_RESET Mask */

// ----------------------------------  RGU_RESET_EXT_STAT48  --------------------------------------
#define RGU_RESET_EXT_STAT48_PERIPHERAL_RESET_Pos             2                                                         /*!< RGU RESET_EXT_STAT48: PERIPHERAL_RESET Position */
#define RGU_RESET_EXT_STAT48_PERIPHERAL_RESET_Msk             (0x01UL << RGU_RESET_EXT_STAT48_PERIPHERAL_RESET_Pos)     /*!< RGU RESET_EXT_STAT48: PERIPHERAL_RESET Mask */

// ----------------------------------  RGU_RESET_EXT_STAT49  --------------------------------------
#define RGU_RESET_EXT_STAT49_PERIPHERAL_RESET_Pos             2                                                         /*!< RGU RESET_EXT_STAT49: PERIPHERAL_RESET Position */
#define RGU_RESET_EXT_STAT49_PERIPHERAL_RESET_Msk             (0x01UL << RGU_RESET_EXT_STAT49_PERIPHERAL_RESET_Pos)     /*!< RGU RESET_EXT_STAT49: PERIPHERAL_RESET Mask */

// ----------------------------------  RGU_RESET_EXT_STAT50  --------------------------------------
#define RGU_RESET_EXT_STAT50_PERIPHERAL_RESET_Pos             2                                                         /*!< RGU RESET_EXT_STAT50: PERIPHERAL_RESET Position */
#define RGU_RESET_EXT_STAT50_PERIPHERAL_RESET_Msk             (0x01UL << RGU_RESET_EXT_STAT50_PERIPHERAL_RESET_Pos)     /*!< RGU RESET_EXT_STAT50: PERIPHERAL_RESET Mask */

// ----------------------------------  RGU_RESET_EXT_STAT51  --------------------------------------
#define RGU_RESET_EXT_STAT51_PERIPHERAL_RESET_Pos             2                                                         /*!< RGU RESET_EXT_STAT51: PERIPHERAL_RESET Position */
#define RGU_RESET_EXT_STAT51_PERIPHERAL_RESET_Msk             (0x01UL << RGU_RESET_EXT_STAT51_PERIPHERAL_RESET_Pos)     /*!< RGU RESET_EXT_STAT51: PERIPHERAL_RESET Mask */

// ----------------------------------  RGU_RESET_EXT_STAT52  --------------------------------------
#define RGU_RESET_EXT_STAT52_PERIPHERAL_RESET_Pos             2                                                         /*!< RGU RESET_EXT_STAT52: PERIPHERAL_RESET Position */
#define RGU_RESET_EXT_STAT52_PERIPHERAL_RESET_Msk             (0x01UL << RGU_RESET_EXT_STAT52_PERIPHERAL_RESET_Pos)     /*!< RGU RESET_EXT_STAT52: PERIPHERAL_RESET Mask */

// ----------------------------------  RGU_RESET_EXT_STAT53  --------------------------------------
#define RGU_RESET_EXT_STAT53_PERIPHERAL_RESET_Pos             2                                                         /*!< RGU RESET_EXT_STAT53: PERIPHERAL_RESET Position */
#define RGU_RESET_EXT_STAT53_PERIPHERAL_RESET_Msk             (0x01UL << RGU_RESET_EXT_STAT53_PERIPHERAL_RESET_Pos)     /*!< RGU RESET_EXT_STAT53: PERIPHERAL_RESET Mask */

// ----------------------------------  RGU_RESET_EXT_STAT54  --------------------------------------
#define RGU_RESET_EXT_STAT54_PERIPHERAL_RESET_Pos             2                                                         /*!< RGU RESET_EXT_STAT54: PERIPHERAL_RESET Position */
#define RGU_RESET_EXT_STAT54_PERIPHERAL_RESET_Msk             (0x01UL << RGU_RESET_EXT_STAT54_PERIPHERAL_RESET_Pos)     /*!< RGU RESET_EXT_STAT54: PERIPHERAL_RESET Mask */

// ----------------------------------  RGU_RESET_EXT_STAT55  --------------------------------------
#define RGU_RESET_EXT_STAT55_PERIPHERAL_RESET_Pos             2                                                         /*!< RGU RESET_EXT_STAT55: PERIPHERAL_RESET Position */
#define RGU_RESET_EXT_STAT55_PERIPHERAL_RESET_Msk             (0x01UL << RGU_RESET_EXT_STAT55_PERIPHERAL_RESET_Pos)     /*!< RGU RESET_EXT_STAT55: PERIPHERAL_RESET Mask */


// ------------------------------------------------------------------------------------------------
// -----                                 WWDT Position & Mask                                 -----
// ------------------------------------------------------------------------------------------------


// ----------------------------------------  WWDT_MOD  --------------------------------------------
#define WWDT_MOD_WDEN_Pos                                     0                                                         /*!< WWDT MOD: WDEN Position             */
#define WWDT_MOD_WDEN_Msk                                     (0x01UL << WWDT_MOD_WDEN_Pos)                             /*!< WWDT MOD: WDEN Mask                 */
#define WWDT_MOD_WDRESET_Pos                                  1                                                         /*!< WWDT MOD: WDRESET Position          */
#define WWDT_MOD_WDRESET_Msk                                  (0x01UL << WWDT_MOD_WDRESET_Pos)                          /*!< WWDT MOD: WDRESET Mask              */
#define WWDT_MOD_WDTOF_Pos                                    2                                                         /*!< WWDT MOD: WDTOF Position            */
#define WWDT_MOD_WDTOF_Msk                                    (0x01UL << WWDT_MOD_WDTOF_Pos)                            /*!< WWDT MOD: WDTOF Mask                */
#define WWDT_MOD_WDINT_Pos                                    3                                                         /*!< WWDT MOD: WDINT Position            */
#define WWDT_MOD_WDINT_Msk                                    (0x01UL << WWDT_MOD_WDINT_Pos)                            /*!< WWDT MOD: WDINT Mask                */
#define WWDT_MOD_WDPROTECT_Pos                                4                                                         /*!< WWDT MOD: WDPROTECT Position        */
#define WWDT_MOD_WDPROTECT_Msk                                (0x01UL << WWDT_MOD_WDPROTECT_Pos)                        /*!< WWDT MOD: WDPROTECT Mask            */

// -----------------------------------------  WWDT_TC  --------------------------------------------
#define WWDT_TC_WDTC_Pos                                      0                                                         /*!< WWDT TC: WDTC Position              */
#define WWDT_TC_WDTC_Msk                                      (0x00ffffffUL << WWDT_TC_WDTC_Pos)                        /*!< WWDT TC: WDTC Mask                  */

// ----------------------------------------  WWDT_FEED  -------------------------------------------
#define WWDT_FEED_Feed_Pos                                    0                                                         /*!< WWDT FEED: Feed Position            */
#define WWDT_FEED_Feed_Msk                                    (0x000000ffUL << WWDT_FEED_Feed_Pos)                      /*!< WWDT FEED: Feed Mask                */

// -----------------------------------------  WWDT_TV  --------------------------------------------
#define WWDT_TV_Count_Pos                                     0                                                         /*!< WWDT TV: Count Position             */
#define WWDT_TV_Count_Msk                                     (0x00ffffffUL << WWDT_TV_Count_Pos)                       /*!< WWDT TV: Count Mask                 */

// --------------------------------------  WWDT_WARNINT  ------------------------------------------
#define WWDT_WARNINT_WDWARNINT_Pos                            0                                                         /*!< WWDT WARNINT: WDWARNINT Position    */
#define WWDT_WARNINT_WDWARNINT_Msk                            (0x000003ffUL << WWDT_WARNINT_WDWARNINT_Pos)              /*!< WWDT WARNINT: WDWARNINT Mask        */

// ---------------------------------------  WWDT_WINDOW  ------------------------------------------
#define WWDT_WINDOW_WDWINDOW_Pos                              0                                                         /*!< WWDT WINDOW: WDWINDOW Position      */
#define WWDT_WINDOW_WDWINDOW_Msk                              (0x00ffffffUL << WWDT_WINDOW_WDWINDOW_Pos)                /*!< WWDT WINDOW: WDWINDOW Mask          */


// ------------------------------------------------------------------------------------------------
// -----                                USART0 Position & Mask                                -----
// ------------------------------------------------------------------------------------------------


// ---------------------------------------  USART0_RBR  -------------------------------------------
#define USART0_RBR_RBR_Pos                                    0                                                         /*!< USART0 RBR: RBR Position            */
#define USART0_RBR_RBR_Msk                                    (0x000000ffUL << USART0_RBR_RBR_Pos)                      /*!< USART0 RBR: RBR Mask                */

// ---------------------------------------  USART0_THR  -------------------------------------------
#define USART0_THR_THR_Pos                                    0                                                         /*!< USART0 THR: THR Position            */
#define USART0_THR_THR_Msk                                    (0x000000ffUL << USART0_THR_THR_Pos)                      /*!< USART0 THR: THR Mask                */

// ---------------------------------------  USART0_DLL  -------------------------------------------
#define USART0_DLL_DLLSB_Pos                                  0                                                         /*!< USART0 DLL: DLLSB Position          */
#define USART0_DLL_DLLSB_Msk                                  (0x000000ffUL << USART0_DLL_DLLSB_Pos)                    /*!< USART0 DLL: DLLSB Mask              */

// ---------------------------------------  USART0_DLM  -------------------------------------------
#define USART0_DLM_DLMSB_Pos                                  0                                                         /*!< USART0 DLM: DLMSB Position          */
#define USART0_DLM_DLMSB_Msk                                  (0x000000ffUL << USART0_DLM_DLMSB_Pos)                    /*!< USART0 DLM: DLMSB Mask              */

// ---------------------------------------  USART0_IER  -------------------------------------------
#define USART0_IER_RBRIE_Pos                                  0                                                         /*!< USART0 IER: RBRIE Position          */
#define USART0_IER_RBRIE_Msk                                  (0x01UL << USART0_IER_RBRIE_Pos)                          /*!< USART0 IER: RBRIE Mask              */
#define USART0_IER_THREIE_Pos                                 1                                                         /*!< USART0 IER: THREIE Position         */
#define USART0_IER_THREIE_Msk                                 (0x01UL << USART0_IER_THREIE_Pos)                         /*!< USART0 IER: THREIE Mask             */
#define USART0_IER_RXIE_Pos                                   2                                                         /*!< USART0 IER: RXIE Position           */
#define USART0_IER_RXIE_Msk                                   (0x01UL << USART0_IER_RXIE_Pos)                           /*!< USART0 IER: RXIE Mask               */
#define USART0_IER_ABEOINTEN_Pos                              8                                                         /*!< USART0 IER: ABEOINTEN Position      */
#define USART0_IER_ABEOINTEN_Msk                              (0x01UL << USART0_IER_ABEOINTEN_Pos)                      /*!< USART0 IER: ABEOINTEN Mask          */
#define USART0_IER_ABTOINTEN_Pos                              9                                                         /*!< USART0 IER: ABTOINTEN Position      */
#define USART0_IER_ABTOINTEN_Msk                              (0x01UL << USART0_IER_ABTOINTEN_Pos)                      /*!< USART0 IER: ABTOINTEN Mask          */

// ---------------------------------------  USART0_IIR  -------------------------------------------
#define USART0_IIR_INTSTATUS_Pos                              0                                                         /*!< USART0 IIR: INTSTATUS Position      */
#define USART0_IIR_INTSTATUS_Msk                              (0x01UL << USART0_IIR_INTSTATUS_Pos)                      /*!< USART0 IIR: INTSTATUS Mask          */
#define USART0_IIR_INTID_Pos                                  1                                                         /*!< USART0 IIR: INTID Position          */
#define USART0_IIR_INTID_Msk                                  (0x07UL << USART0_IIR_INTID_Pos)                          /*!< USART0 IIR: INTID Mask              */
#define USART0_IIR_FIFOENABLE_Pos                             6                                                         /*!< USART0 IIR: FIFOENABLE Position     */
#define USART0_IIR_FIFOENABLE_Msk                             (0x03UL << USART0_IIR_FIFOENABLE_Pos)                     /*!< USART0 IIR: FIFOENABLE Mask         */
#define USART0_IIR_ABEOINT_Pos                                8                                                         /*!< USART0 IIR: ABEOINT Position        */
#define USART0_IIR_ABEOINT_Msk                                (0x01UL << USART0_IIR_ABEOINT_Pos)                        /*!< USART0 IIR: ABEOINT Mask            */
#define USART0_IIR_ABTOINT_Pos                                9                                                         /*!< USART0 IIR: ABTOINT Position        */
#define USART0_IIR_ABTOINT_Msk                                (0x01UL << USART0_IIR_ABTOINT_Pos)                        /*!< USART0 IIR: ABTOINT Mask            */

// ---------------------------------------  USART0_FCR  -------------------------------------------
#define USART0_FCR_FIFOEN_Pos                                 0                                                         /*!< USART0 FCR: FIFOEN Position         */
#define USART0_FCR_FIFOEN_Msk                                 (0x01UL << USART0_FCR_FIFOEN_Pos)                         /*!< USART0 FCR: FIFOEN Mask             */
#define USART0_FCR_RXFIFORES_Pos                              1                                                         /*!< USART0 FCR: RXFIFORES Position      */
#define USART0_FCR_RXFIFORES_Msk                              (0x01UL << USART0_FCR_RXFIFORES_Pos)                      /*!< USART0 FCR: RXFIFORES Mask          */
#define USART0_FCR_TXFIFORES_Pos                              2                                                         /*!< USART0 FCR: TXFIFORES Position      */
#define USART0_FCR_TXFIFORES_Msk                              (0x01UL << USART0_FCR_TXFIFORES_Pos)                      /*!< USART0 FCR: TXFIFORES Mask          */
#define USART0_FCR_DMAMODE_Pos                                3                                                         /*!< USART0 FCR: DMAMODE Position        */
#define USART0_FCR_DMAMODE_Msk                                (0x01UL << USART0_FCR_DMAMODE_Pos)                        /*!< USART0 FCR: DMAMODE Mask            */
#define USART0_FCR_RXTRIGLVL_Pos                              6                                                         /*!< USART0 FCR: RXTRIGLVL Position      */
#define USART0_FCR_RXTRIGLVL_Msk                              (0x03UL << USART0_FCR_RXTRIGLVL_Pos)                      /*!< USART0 FCR: RXTRIGLVL Mask          */

// ---------------------------------------  USART0_LCR  -------------------------------------------
#define USART0_LCR_WLS_Pos                                    0                                                         /*!< USART0 LCR: WLS Position            */
#define USART0_LCR_WLS_Msk                                    (0x03UL << USART0_LCR_WLS_Pos)                            /*!< USART0 LCR: WLS Mask                */
#define USART0_LCR_SBS_Pos                                    2                                                         /*!< USART0 LCR: SBS Position            */
#define USART0_LCR_SBS_Msk                                    (0x01UL << USART0_LCR_SBS_Pos)                            /*!< USART0 LCR: SBS Mask                */
#define USART0_LCR_PE_Pos                                     3                                                         /*!< USART0 LCR: PE Position             */
#define USART0_LCR_PE_Msk                                     (0x01UL << USART0_LCR_PE_Pos)                             /*!< USART0 LCR: PE Mask                 */
#define USART0_LCR_PS_Pos                                     4                                                         /*!< USART0 LCR: PS Position             */
#define USART0_LCR_PS_Msk                                     (0x03UL << USART0_LCR_PS_Pos)                             /*!< USART0 LCR: PS Mask                 */
#define USART0_LCR_BC_Pos                                     6                                                         /*!< USART0 LCR: BC Position             */
#define USART0_LCR_BC_Msk                                     (0x01UL << USART0_LCR_BC_Pos)                             /*!< USART0 LCR: BC Mask                 */
#define USART0_LCR_DLAB_Pos                                   7                                                         /*!< USART0 LCR: DLAB Position           */
#define USART0_LCR_DLAB_Msk                                   (0x01UL << USART0_LCR_DLAB_Pos)                           /*!< USART0 LCR: DLAB Mask               */

// ---------------------------------------  USART0_LSR  -------------------------------------------
#define USART0_LSR_RDR_Pos                                    0                                                         /*!< USART0 LSR: RDR Position            */
#define USART0_LSR_RDR_Msk                                    (0x01UL << USART0_LSR_RDR_Pos)                            /*!< USART0 LSR: RDR Mask                */
#define USART0_LSR_OE_Pos                                     1                                                         /*!< USART0 LSR: OE Position             */
#define USART0_LSR_OE_Msk                                     (0x01UL << USART0_LSR_OE_Pos)                             /*!< USART0 LSR: OE Mask                 */
#define USART0_LSR_PE_Pos                                     2                                                         /*!< USART0 LSR: PE Position             */
#define USART0_LSR_PE_Msk                                     (0x01UL << USART0_LSR_PE_Pos)                             /*!< USART0 LSR: PE Mask                 */
#define USART0_LSR_FE_Pos                                     3                                                         /*!< USART0 LSR: FE Position             */
#define USART0_LSR_FE_Msk                                     (0x01UL << USART0_LSR_FE_Pos)                             /*!< USART0 LSR: FE Mask                 */
#define USART0_LSR_BI_Pos                                     4                                                         /*!< USART0 LSR: BI Position             */
#define USART0_LSR_BI_Msk                                     (0x01UL << USART0_LSR_BI_Pos)                             /*!< USART0 LSR: BI Mask                 */
#define USART0_LSR_THRE_Pos                                   5                                                         /*!< USART0 LSR: THRE Position           */
#define USART0_LSR_THRE_Msk                                   (0x01UL << USART0_LSR_THRE_Pos)                           /*!< USART0 LSR: THRE Mask               */
#define USART0_LSR_TEMT_Pos                                   6                                                         /*!< USART0 LSR: TEMT Position           */
#define USART0_LSR_TEMT_Msk                                   (0x01UL << USART0_LSR_TEMT_Pos)                           /*!< USART0 LSR: TEMT Mask               */
#define USART0_LSR_RXFE_Pos                                   7                                                         /*!< USART0 LSR: RXFE Position           */
#define USART0_LSR_RXFE_Msk                                   (0x01UL << USART0_LSR_RXFE_Pos)                           /*!< USART0 LSR: RXFE Mask               */
#define USART0_LSR_TXERR_Pos                                  8                                                         /*!< USART0 LSR: TXERR Position          */
#define USART0_LSR_TXERR_Msk                                  (0x01UL << USART0_LSR_TXERR_Pos)                          /*!< USART0 LSR: TXERR Mask              */

// ---------------------------------------  USART0_SCR  -------------------------------------------
#define USART0_SCR_PAD_Pos                                    0                                                         /*!< USART0 SCR: PAD Position            */
#define USART0_SCR_PAD_Msk                                    (0x000000ffUL << USART0_SCR_PAD_Pos)                      /*!< USART0 SCR: PAD Mask                */

// ---------------------------------------  USART0_ACR  -------------------------------------------
#define USART0_ACR_START_Pos                                  0                                                         /*!< USART0 ACR: START Position          */
#define USART0_ACR_START_Msk                                  (0x01UL << USART0_ACR_START_Pos)                          /*!< USART0 ACR: START Mask              */
#define USART0_ACR_MODE_Pos                                   1                                                         /*!< USART0 ACR: MODE Position           */
#define USART0_ACR_MODE_Msk                                   (0x01UL << USART0_ACR_MODE_Pos)                           /*!< USART0 ACR: MODE Mask               */
#define USART0_ACR_AUTORESTART_Pos                            2                                                         /*!< USART0 ACR: AUTORESTART Position    */
#define USART0_ACR_AUTORESTART_Msk                            (0x01UL << USART0_ACR_AUTORESTART_Pos)                    /*!< USART0 ACR: AUTORESTART Mask        */
#define USART0_ACR_ABEOINTCLR_Pos                             8                                                         /*!< USART0 ACR: ABEOINTCLR Position     */
#define USART0_ACR_ABEOINTCLR_Msk                             (0x01UL << USART0_ACR_ABEOINTCLR_Pos)                     /*!< USART0 ACR: ABEOINTCLR Mask         */
#define USART0_ACR_ABTOINTCLR_Pos                             9                                                         /*!< USART0 ACR: ABTOINTCLR Position     */
#define USART0_ACR_ABTOINTCLR_Msk                             (0x01UL << USART0_ACR_ABTOINTCLR_Pos)                     /*!< USART0 ACR: ABTOINTCLR Mask         */

// ---------------------------------------  USART0_ICR  -------------------------------------------
#define USART0_ICR_IRDAEN_Pos                                 0                                                         /*!< USART0 ICR: IRDAEN Position         */
#define USART0_ICR_IRDAEN_Msk                                 (0x01UL << USART0_ICR_IRDAEN_Pos)                         /*!< USART0 ICR: IRDAEN Mask             */
#define USART0_ICR_IRDAINV_Pos                                1                                                         /*!< USART0 ICR: IRDAINV Position        */
#define USART0_ICR_IRDAINV_Msk                                (0x01UL << USART0_ICR_IRDAINV_Pos)                        /*!< USART0 ICR: IRDAINV Mask            */
#define USART0_ICR_FIXPULSEEN_Pos                             2                                                         /*!< USART0 ICR: FIXPULSEEN Position     */
#define USART0_ICR_FIXPULSEEN_Msk                             (0x01UL << USART0_ICR_FIXPULSEEN_Pos)                     /*!< USART0 ICR: FIXPULSEEN Mask         */
#define USART0_ICR_PULSEDIV_Pos                               3                                                         /*!< USART0 ICR: PULSEDIV Position       */
#define USART0_ICR_PULSEDIV_Msk                               (0x07UL << USART0_ICR_PULSEDIV_Pos)                       /*!< USART0 ICR: PULSEDIV Mask           */

// ---------------------------------------  USART0_FDR  -------------------------------------------
#define USART0_FDR_DIVADDVAL_Pos                              0                                                         /*!< USART0 FDR: DIVADDVAL Position      */
#define USART0_FDR_DIVADDVAL_Msk                              (0x0fUL << USART0_FDR_DIVADDVAL_Pos)                      /*!< USART0 FDR: DIVADDVAL Mask          */
#define USART0_FDR_MULVAL_Pos                                 4                                                         /*!< USART0 FDR: MULVAL Position         */
#define USART0_FDR_MULVAL_Msk                                 (0x0fUL << USART0_FDR_MULVAL_Pos)                         /*!< USART0 FDR: MULVAL Mask             */

// ---------------------------------------  USART0_OSR  -------------------------------------------
#define USART0_OSR_OSFRAC_Pos                                 1                                                         /*!< USART0 OSR: OSFRAC Position         */
#define USART0_OSR_OSFRAC_Msk                                 (0x07UL << USART0_OSR_OSFRAC_Pos)                         /*!< USART0 OSR: OSFRAC Mask             */
#define USART0_OSR_OSINT_Pos                                  4                                                         /*!< USART0 OSR: OSINT Position          */
#define USART0_OSR_OSINT_Msk                                  (0x0fUL << USART0_OSR_OSINT_Pos)                          /*!< USART0 OSR: OSINT Mask              */
#define USART0_OSR_FDINT_Pos                                  8                                                         /*!< USART0 OSR: FDINT Position          */
#define USART0_OSR_FDINT_Msk                                  (0x7fUL << USART0_OSR_FDINT_Pos)                          /*!< USART0 OSR: FDINT Mask              */

// ---------------------------------------  USART0_HDEN  ------------------------------------------
#define USART0_HDEN_HDEN_Pos                                  0                                                         /*!< USART0 HDEN: HDEN Position          */
#define USART0_HDEN_HDEN_Msk                                  (0x01UL << USART0_HDEN_HDEN_Pos)                          /*!< USART0 HDEN: HDEN Mask              */

// -------------------------------------  USART0_SCICTRL  -----------------------------------------
#define USART0_SCICTRL_SCIEN_Pos                              0                                                         /*!< USART0 SCICTRL: SCIEN Position      */
#define USART0_SCICTRL_SCIEN_Msk                              (0x01UL << USART0_SCICTRL_SCIEN_Pos)                      /*!< USART0 SCICTRL: SCIEN Mask          */
#define USART0_SCICTRL_NACKDIS_Pos                            1                                                         /*!< USART0 SCICTRL: NACKDIS Position    */
#define USART0_SCICTRL_NACKDIS_Msk                            (0x01UL << USART0_SCICTRL_NACKDIS_Pos)                    /*!< USART0 SCICTRL: NACKDIS Mask        */
#define USART0_SCICTRL_PROTSEL_Pos                            2                                                         /*!< USART0 SCICTRL: PROTSEL Position    */
#define USART0_SCICTRL_PROTSEL_Msk                            (0x01UL << USART0_SCICTRL_PROTSEL_Pos)                    /*!< USART0 SCICTRL: PROTSEL Mask        */
#define USART0_SCICTRL_TXRETRY_Pos                            5                                                         /*!< USART0 SCICTRL: TXRETRY Position    */
#define USART0_SCICTRL_TXRETRY_Msk                            (0x07UL << USART0_SCICTRL_TXRETRY_Pos)                    /*!< USART0 SCICTRL: TXRETRY Mask        */
#define USART0_SCICTRL_GUARDTIME_Pos                          8                                                         /*!< USART0 SCICTRL: GUARDTIME Position  */
#define USART0_SCICTRL_GUARDTIME_Msk                          (0x000000ffUL << USART0_SCICTRL_GUARDTIME_Pos)            /*!< USART0 SCICTRL: GUARDTIME Mask      */

// ------------------------------------  USART0_RS485CTRL  ----------------------------------------
#define USART0_RS485CTRL_NMMEN_Pos                            0                                                         /*!< USART0 RS485CTRL: NMMEN Position    */
#define USART0_RS485CTRL_NMMEN_Msk                            (0x01UL << USART0_RS485CTRL_NMMEN_Pos)                    /*!< USART0 RS485CTRL: NMMEN Mask        */
#define USART0_RS485CTRL_RXDIS_Pos                            1                                                         /*!< USART0 RS485CTRL: RXDIS Position    */
#define USART0_RS485CTRL_RXDIS_Msk                            (0x01UL << USART0_RS485CTRL_RXDIS_Pos)                    /*!< USART0 RS485CTRL: RXDIS Mask        */
#define USART0_RS485CTRL_AADEN_Pos                            2                                                         /*!< USART0 RS485CTRL: AADEN Position    */
#define USART0_RS485CTRL_AADEN_Msk                            (0x01UL << USART0_RS485CTRL_AADEN_Pos)                    /*!< USART0 RS485CTRL: AADEN Mask        */
#define USART0_RS485CTRL_DCTRL_Pos                            4                                                         /*!< USART0 RS485CTRL: DCTRL Position    */
#define USART0_RS485CTRL_DCTRL_Msk                            (0x01UL << USART0_RS485CTRL_DCTRL_Pos)                    /*!< USART0 RS485CTRL: DCTRL Mask        */
#define USART0_RS485CTRL_OINV_Pos                             5                                                         /*!< USART0 RS485CTRL: OINV Position     */
#define USART0_RS485CTRL_OINV_Msk                             (0x01UL << USART0_RS485CTRL_OINV_Pos)                     /*!< USART0 RS485CTRL: OINV Mask         */

// ----------------------------------  USART0_RS485ADRMATCH  --------------------------------------
#define USART0_RS485ADRMATCH_ADRMATCH_Pos                     0                                                         /*!< USART0 RS485ADRMATCH: ADRMATCH Position */
#define USART0_RS485ADRMATCH_ADRMATCH_Msk                     (0x000000ffUL << USART0_RS485ADRMATCH_ADRMATCH_Pos)       /*!< USART0 RS485ADRMATCH: ADRMATCH Mask */

// -------------------------------------  USART0_RS485DLY  ----------------------------------------
#define USART0_RS485DLY_DLY_Pos                               0                                                         /*!< USART0 RS485DLY: DLY Position       */
#define USART0_RS485DLY_DLY_Msk                               (0x000000ffUL << USART0_RS485DLY_DLY_Pos)                 /*!< USART0 RS485DLY: DLY Mask           */

// -------------------------------------  USART0_SYNCCTRL  ----------------------------------------
#define USART0_SYNCCTRL_SYNC_Pos                              0                                                         /*!< USART0 SYNCCTRL: SYNC Position      */
#define USART0_SYNCCTRL_SYNC_Msk                              (0x01UL << USART0_SYNCCTRL_SYNC_Pos)                      /*!< USART0 SYNCCTRL: SYNC Mask          */
#define USART0_SYNCCTRL_CSRC_Pos                              1                                                         /*!< USART0 SYNCCTRL: CSRC Position      */
#define USART0_SYNCCTRL_CSRC_Msk                              (0x01UL << USART0_SYNCCTRL_CSRC_Pos)                      /*!< USART0 SYNCCTRL: CSRC Mask          */
#define USART0_SYNCCTRL_FES_Pos                               2                                                         /*!< USART0 SYNCCTRL: FES Position       */
#define USART0_SYNCCTRL_FES_Msk                               (0x01UL << USART0_SYNCCTRL_FES_Pos)                       /*!< USART0 SYNCCTRL: FES Mask           */
#define USART0_SYNCCTRL_TSBYPASS_Pos                          3                                                         /*!< USART0 SYNCCTRL: TSBYPASS Position  */
#define USART0_SYNCCTRL_TSBYPASS_Msk                          (0x01UL << USART0_SYNCCTRL_TSBYPASS_Pos)                  /*!< USART0 SYNCCTRL: TSBYPASS Mask      */
#define USART0_SYNCCTRL_CSCEN_Pos                             4                                                         /*!< USART0 SYNCCTRL: CSCEN Position     */
#define USART0_SYNCCTRL_CSCEN_Msk                             (0x01UL << USART0_SYNCCTRL_CSCEN_Pos)                     /*!< USART0 SYNCCTRL: CSCEN Mask         */
#define USART0_SYNCCTRL_SSSDIS_Pos                            5                                                         /*!< USART0 SYNCCTRL: SSSDIS Position    */
#define USART0_SYNCCTRL_SSSDIS_Msk                            (0x01UL << USART0_SYNCCTRL_SSSDIS_Pos)                    /*!< USART0 SYNCCTRL: SSSDIS Mask        */
#define USART0_SYNCCTRL_CCCLR_Pos                             6                                                         /*!< USART0 SYNCCTRL: CCCLR Position     */
#define USART0_SYNCCTRL_CCCLR_Msk                             (0x01UL << USART0_SYNCCTRL_CCCLR_Pos)                     /*!< USART0 SYNCCTRL: CCCLR Mask         */

// ---------------------------------------  USART0_TER  -------------------------------------------
#define USART0_TER_TXEN_Pos                                   0                                                         /*!< USART0 TER: TXEN Position           */
#define USART0_TER_TXEN_Msk                                   (0x01UL << USART0_TER_TXEN_Pos)                           /*!< USART0 TER: TXEN Mask               */


// ------------------------------------------------------------------------------------------------
// -----                                USART2 Position & Mask                                -----
// ------------------------------------------------------------------------------------------------


// ---------------------------------------  USART2_DLL  -------------------------------------------
#define USART2_DLL_DLLSB_Pos                                  0                                                         /*!< USART2 DLL: DLLSB Position          */
#define USART2_DLL_DLLSB_Msk                                  (0x000000ffUL << USART2_DLL_DLLSB_Pos)                    /*!< USART2 DLL: DLLSB Mask              */

// ---------------------------------------  USART2_THR  -------------------------------------------
#define USART2_THR_THR_Pos                                    0                                                         /*!< USART2 THR: THR Position            */
#define USART2_THR_THR_Msk                                    (0x000000ffUL << USART2_THR_THR_Pos)                      /*!< USART2 THR: THR Mask                */

// ---------------------------------------  USART2_RBR  -------------------------------------------
#define USART2_RBR_RBR_Pos                                    0                                                         /*!< USART2 RBR: RBR Position            */
#define USART2_RBR_RBR_Msk                                    (0x000000ffUL << USART2_RBR_RBR_Pos)                      /*!< USART2 RBR: RBR Mask                */

// ---------------------------------------  USART2_IER  -------------------------------------------
#define USART2_IER_RBRIE_Pos                                  0                                                         /*!< USART2 IER: RBRIE Position          */
#define USART2_IER_RBRIE_Msk                                  (0x01UL << USART2_IER_RBRIE_Pos)                          /*!< USART2 IER: RBRIE Mask              */
#define USART2_IER_THREIE_Pos                                 1                                                         /*!< USART2 IER: THREIE Position         */
#define USART2_IER_THREIE_Msk                                 (0x01UL << USART2_IER_THREIE_Pos)                         /*!< USART2 IER: THREIE Mask             */
#define USART2_IER_RXIE_Pos                                   2                                                         /*!< USART2 IER: RXIE Position           */
#define USART2_IER_RXIE_Msk                                   (0x01UL << USART2_IER_RXIE_Pos)                           /*!< USART2 IER: RXIE Mask               */
#define USART2_IER_ABEOINTEN_Pos                              8                                                         /*!< USART2 IER: ABEOINTEN Position      */
#define USART2_IER_ABEOINTEN_Msk                              (0x01UL << USART2_IER_ABEOINTEN_Pos)                      /*!< USART2 IER: ABEOINTEN Mask          */
#define USART2_IER_ABTOINTEN_Pos                              9                                                         /*!< USART2 IER: ABTOINTEN Position      */
#define USART2_IER_ABTOINTEN_Msk                              (0x01UL << USART2_IER_ABTOINTEN_Pos)                      /*!< USART2 IER: ABTOINTEN Mask          */

// ---------------------------------------  USART2_DLM  -------------------------------------------
#define USART2_DLM_DLMSB_Pos                                  0                                                         /*!< USART2 DLM: DLMSB Position          */
#define USART2_DLM_DLMSB_Msk                                  (0x000000ffUL << USART2_DLM_DLMSB_Pos)                    /*!< USART2 DLM: DLMSB Mask              */

// ---------------------------------------  USART2_FCR  -------------------------------------------
#define USART2_FCR_FIFOEN_Pos                                 0                                                         /*!< USART2 FCR: FIFOEN Position         */
#define USART2_FCR_FIFOEN_Msk                                 (0x01UL << USART2_FCR_FIFOEN_Pos)                         /*!< USART2 FCR: FIFOEN Mask             */
#define USART2_FCR_RXFIFORES_Pos                              1                                                         /*!< USART2 FCR: RXFIFORES Position      */
#define USART2_FCR_RXFIFORES_Msk                              (0x01UL << USART2_FCR_RXFIFORES_Pos)                      /*!< USART2 FCR: RXFIFORES Mask          */
#define USART2_FCR_TXFIFORES_Pos                              2                                                         /*!< USART2 FCR: TXFIFORES Position      */
#define USART2_FCR_TXFIFORES_Msk                              (0x01UL << USART2_FCR_TXFIFORES_Pos)                      /*!< USART2 FCR: TXFIFORES Mask          */
#define USART2_FCR_DMAMODE_Pos                                3                                                         /*!< USART2 FCR: DMAMODE Position        */
#define USART2_FCR_DMAMODE_Msk                                (0x01UL << USART2_FCR_DMAMODE_Pos)                        /*!< USART2 FCR: DMAMODE Mask            */
#define USART2_FCR_RXTRIGLVL_Pos                              6                                                         /*!< USART2 FCR: RXTRIGLVL Position      */
#define USART2_FCR_RXTRIGLVL_Msk                              (0x03UL << USART2_FCR_RXTRIGLVL_Pos)                      /*!< USART2 FCR: RXTRIGLVL Mask          */

// ---------------------------------------  USART2_IIR  -------------------------------------------
#define USART2_IIR_INTSTATUS_Pos                              0                                                         /*!< USART2 IIR: INTSTATUS Position      */
#define USART2_IIR_INTSTATUS_Msk                              (0x01UL << USART2_IIR_INTSTATUS_Pos)                      /*!< USART2 IIR: INTSTATUS Mask          */
#define USART2_IIR_INTID_Pos                                  1                                                         /*!< USART2 IIR: INTID Position          */
#define USART2_IIR_INTID_Msk                                  (0x07UL << USART2_IIR_INTID_Pos)                          /*!< USART2 IIR: INTID Mask              */
#define USART2_IIR_FIFOENABLE_Pos                             6                                                         /*!< USART2 IIR: FIFOENABLE Position     */
#define USART2_IIR_FIFOENABLE_Msk                             (0x03UL << USART2_IIR_FIFOENABLE_Pos)                     /*!< USART2 IIR: FIFOENABLE Mask         */
#define USART2_IIR_ABEOINT_Pos                                8                                                         /*!< USART2 IIR: ABEOINT Position        */
#define USART2_IIR_ABEOINT_Msk                                (0x01UL << USART2_IIR_ABEOINT_Pos)                        /*!< USART2 IIR: ABEOINT Mask            */
#define USART2_IIR_ABTOINT_Pos                                9                                                         /*!< USART2 IIR: ABTOINT Position        */
#define USART2_IIR_ABTOINT_Msk                                (0x01UL << USART2_IIR_ABTOINT_Pos)                        /*!< USART2 IIR: ABTOINT Mask            */

// ---------------------------------------  USART2_LCR  -------------------------------------------
#define USART2_LCR_WLS_Pos                                    0                                                         /*!< USART2 LCR: WLS Position            */
#define USART2_LCR_WLS_Msk                                    (0x03UL << USART2_LCR_WLS_Pos)                            /*!< USART2 LCR: WLS Mask                */
#define USART2_LCR_SBS_Pos                                    2                                                         /*!< USART2 LCR: SBS Position            */
#define USART2_LCR_SBS_Msk                                    (0x01UL << USART2_LCR_SBS_Pos)                            /*!< USART2 LCR: SBS Mask                */
#define USART2_LCR_PE_Pos                                     3                                                         /*!< USART2 LCR: PE Position             */
#define USART2_LCR_PE_Msk                                     (0x01UL << USART2_LCR_PE_Pos)                             /*!< USART2 LCR: PE Mask                 */
#define USART2_LCR_PS_Pos                                     4                                                         /*!< USART2 LCR: PS Position             */
#define USART2_LCR_PS_Msk                                     (0x03UL << USART2_LCR_PS_Pos)                             /*!< USART2 LCR: PS Mask                 */
#define USART2_LCR_BC_Pos                                     6                                                         /*!< USART2 LCR: BC Position             */
#define USART2_LCR_BC_Msk                                     (0x01UL << USART2_LCR_BC_Pos)                             /*!< USART2 LCR: BC Mask                 */
#define USART2_LCR_DLAB_Pos                                   7                                                         /*!< USART2 LCR: DLAB Position           */
#define USART2_LCR_DLAB_Msk                                   (0x01UL << USART2_LCR_DLAB_Pos)                           /*!< USART2 LCR: DLAB Mask               */

// ---------------------------------------  USART2_LSR  -------------------------------------------
#define USART2_LSR_RDR_Pos                                    0                                                         /*!< USART2 LSR: RDR Position            */
#define USART2_LSR_RDR_Msk                                    (0x01UL << USART2_LSR_RDR_Pos)                            /*!< USART2 LSR: RDR Mask                */
#define USART2_LSR_OE_Pos                                     1                                                         /*!< USART2 LSR: OE Position             */
#define USART2_LSR_OE_Msk                                     (0x01UL << USART2_LSR_OE_Pos)                             /*!< USART2 LSR: OE Mask                 */
#define USART2_LSR_PE_Pos                                     2                                                         /*!< USART2 LSR: PE Position             */
#define USART2_LSR_PE_Msk                                     (0x01UL << USART2_LSR_PE_Pos)                             /*!< USART2 LSR: PE Mask                 */
#define USART2_LSR_FE_Pos                                     3                                                         /*!< USART2 LSR: FE Position             */
#define USART2_LSR_FE_Msk                                     (0x01UL << USART2_LSR_FE_Pos)                             /*!< USART2 LSR: FE Mask                 */
#define USART2_LSR_BI_Pos                                     4                                                         /*!< USART2 LSR: BI Position             */
#define USART2_LSR_BI_Msk                                     (0x01UL << USART2_LSR_BI_Pos)                             /*!< USART2 LSR: BI Mask                 */
#define USART2_LSR_THRE_Pos                                   5                                                         /*!< USART2 LSR: THRE Position           */
#define USART2_LSR_THRE_Msk                                   (0x01UL << USART2_LSR_THRE_Pos)                           /*!< USART2 LSR: THRE Mask               */
#define USART2_LSR_TEMT_Pos                                   6                                                         /*!< USART2 LSR: TEMT Position           */
#define USART2_LSR_TEMT_Msk                                   (0x01UL << USART2_LSR_TEMT_Pos)                           /*!< USART2 LSR: TEMT Mask               */
#define USART2_LSR_RXFE_Pos                                   7                                                         /*!< USART2 LSR: RXFE Position           */
#define USART2_LSR_RXFE_Msk                                   (0x01UL << USART2_LSR_RXFE_Pos)                           /*!< USART2 LSR: RXFE Mask               */
#define USART2_LSR_TXERR_Pos                                  8                                                         /*!< USART2 LSR: TXERR Position          */
#define USART2_LSR_TXERR_Msk                                  (0x01UL << USART2_LSR_TXERR_Pos)                          /*!< USART2 LSR: TXERR Mask              */

// ---------------------------------------  USART2_SCR  -------------------------------------------
#define USART2_SCR_PAD_Pos                                    0                                                         /*!< USART2 SCR: PAD Position            */
#define USART2_SCR_PAD_Msk                                    (0x000000ffUL << USART2_SCR_PAD_Pos)                      /*!< USART2 SCR: PAD Mask                */

// ---------------------------------------  USART2_ACR  -------------------------------------------
#define USART2_ACR_START_Pos                                  0                                                         /*!< USART2 ACR: START Position          */
#define USART2_ACR_START_Msk                                  (0x01UL << USART2_ACR_START_Pos)                          /*!< USART2 ACR: START Mask              */
#define USART2_ACR_MODE_Pos                                   1                                                         /*!< USART2 ACR: MODE Position           */
#define USART2_ACR_MODE_Msk                                   (0x01UL << USART2_ACR_MODE_Pos)                           /*!< USART2 ACR: MODE Mask               */
#define USART2_ACR_AUTORESTART_Pos                            2                                                         /*!< USART2 ACR: AUTORESTART Position    */
#define USART2_ACR_AUTORESTART_Msk                            (0x01UL << USART2_ACR_AUTORESTART_Pos)                    /*!< USART2 ACR: AUTORESTART Mask        */
#define USART2_ACR_ABEOINTCLR_Pos                             8                                                         /*!< USART2 ACR: ABEOINTCLR Position     */
#define USART2_ACR_ABEOINTCLR_Msk                             (0x01UL << USART2_ACR_ABEOINTCLR_Pos)                     /*!< USART2 ACR: ABEOINTCLR Mask         */
#define USART2_ACR_ABTOINTCLR_Pos                             9                                                         /*!< USART2 ACR: ABTOINTCLR Position     */
#define USART2_ACR_ABTOINTCLR_Msk                             (0x01UL << USART2_ACR_ABTOINTCLR_Pos)                     /*!< USART2 ACR: ABTOINTCLR Mask         */

// ---------------------------------------  USART2_ICR  -------------------------------------------
#define USART2_ICR_IRDAEN_Pos                                 0                                                         /*!< USART2 ICR: IRDAEN Position         */
#define USART2_ICR_IRDAEN_Msk                                 (0x01UL << USART2_ICR_IRDAEN_Pos)                         /*!< USART2 ICR: IRDAEN Mask             */
#define USART2_ICR_IRDAINV_Pos                                1                                                         /*!< USART2 ICR: IRDAINV Position        */
#define USART2_ICR_IRDAINV_Msk                                (0x01UL << USART2_ICR_IRDAINV_Pos)                        /*!< USART2 ICR: IRDAINV Mask            */
#define USART2_ICR_FIXPULSEEN_Pos                             2                                                         /*!< USART2 ICR: FIXPULSEEN Position     */
#define USART2_ICR_FIXPULSEEN_Msk                             (0x01UL << USART2_ICR_FIXPULSEEN_Pos)                     /*!< USART2 ICR: FIXPULSEEN Mask         */
#define USART2_ICR_PULSEDIV_Pos                               3                                                         /*!< USART2 ICR: PULSEDIV Position       */
#define USART2_ICR_PULSEDIV_Msk                               (0x07UL << USART2_ICR_PULSEDIV_Pos)                       /*!< USART2 ICR: PULSEDIV Mask           */

// ---------------------------------------  USART2_FDR  -------------------------------------------
#define USART2_FDR_DIVADDVAL_Pos                              0                                                         /*!< USART2 FDR: DIVADDVAL Position      */
#define USART2_FDR_DIVADDVAL_Msk                              (0x0fUL << USART2_FDR_DIVADDVAL_Pos)                      /*!< USART2 FDR: DIVADDVAL Mask          */
#define USART2_FDR_MULVAL_Pos                                 4                                                         /*!< USART2 FDR: MULVAL Position         */
#define USART2_FDR_MULVAL_Msk                                 (0x0fUL << USART2_FDR_MULVAL_Pos)                         /*!< USART2 FDR: MULVAL Mask             */

// ---------------------------------------  USART2_OSR  -------------------------------------------
#define USART2_OSR_OSFRAC_Pos                                 1                                                         /*!< USART2 OSR: OSFRAC Position         */
#define USART2_OSR_OSFRAC_Msk                                 (0x07UL << USART2_OSR_OSFRAC_Pos)                         /*!< USART2 OSR: OSFRAC Mask             */
#define USART2_OSR_OSINT_Pos                                  4                                                         /*!< USART2 OSR: OSINT Position          */
#define USART2_OSR_OSINT_Msk                                  (0x0fUL << USART2_OSR_OSINT_Pos)                          /*!< USART2 OSR: OSINT Mask              */
#define USART2_OSR_FDINT_Pos                                  8                                                         /*!< USART2 OSR: FDINT Position          */
#define USART2_OSR_FDINT_Msk                                  (0x7fUL << USART2_OSR_FDINT_Pos)                          /*!< USART2 OSR: FDINT Mask              */

// ---------------------------------------  USART2_HDEN  ------------------------------------------
#define USART2_HDEN_HDEN_Pos                                  0                                                         /*!< USART2 HDEN: HDEN Position          */
#define USART2_HDEN_HDEN_Msk                                  (0x01UL << USART2_HDEN_HDEN_Pos)                          /*!< USART2 HDEN: HDEN Mask              */

// -------------------------------------  USART2_SCICTRL  -----------------------------------------
#define USART2_SCICTRL_SCIEN_Pos                              0                                                         /*!< USART2 SCICTRL: SCIEN Position      */
#define USART2_SCICTRL_SCIEN_Msk                              (0x01UL << USART2_SCICTRL_SCIEN_Pos)                      /*!< USART2 SCICTRL: SCIEN Mask          */
#define USART2_SCICTRL_NACKDIS_Pos                            1                                                         /*!< USART2 SCICTRL: NACKDIS Position    */
#define USART2_SCICTRL_NACKDIS_Msk                            (0x01UL << USART2_SCICTRL_NACKDIS_Pos)                    /*!< USART2 SCICTRL: NACKDIS Mask        */
#define USART2_SCICTRL_PROTSEL_Pos                            2                                                         /*!< USART2 SCICTRL: PROTSEL Position    */
#define USART2_SCICTRL_PROTSEL_Msk                            (0x01UL << USART2_SCICTRL_PROTSEL_Pos)                    /*!< USART2 SCICTRL: PROTSEL Mask        */
#define USART2_SCICTRL_TXRETRY_Pos                            5                                                         /*!< USART2 SCICTRL: TXRETRY Position    */
#define USART2_SCICTRL_TXRETRY_Msk                            (0x07UL << USART2_SCICTRL_TXRETRY_Pos)                    /*!< USART2 SCICTRL: TXRETRY Mask        */
#define USART2_SCICTRL_GUARDTIME_Pos                          8                                                         /*!< USART2 SCICTRL: GUARDTIME Position  */
#define USART2_SCICTRL_GUARDTIME_Msk                          (0x000000ffUL << USART2_SCICTRL_GUARDTIME_Pos)            /*!< USART2 SCICTRL: GUARDTIME Mask      */

// ------------------------------------  USART2_RS485CTRL  ----------------------------------------
#define USART2_RS485CTRL_NMMEN_Pos                            0                                                         /*!< USART2 RS485CTRL: NMMEN Position    */
#define USART2_RS485CTRL_NMMEN_Msk                            (0x01UL << USART2_RS485CTRL_NMMEN_Pos)                    /*!< USART2 RS485CTRL: NMMEN Mask        */
#define USART2_RS485CTRL_RXDIS_Pos                            1                                                         /*!< USART2 RS485CTRL: RXDIS Position    */
#define USART2_RS485CTRL_RXDIS_Msk                            (0x01UL << USART2_RS485CTRL_RXDIS_Pos)                    /*!< USART2 RS485CTRL: RXDIS Mask        */
#define USART2_RS485CTRL_AADEN_Pos                            2                                                         /*!< USART2 RS485CTRL: AADEN Position    */
#define USART2_RS485CTRL_AADEN_Msk                            (0x01UL << USART2_RS485CTRL_AADEN_Pos)                    /*!< USART2 RS485CTRL: AADEN Mask        */
#define USART2_RS485CTRL_DCTRL_Pos                            4                                                         /*!< USART2 RS485CTRL: DCTRL Position    */
#define USART2_RS485CTRL_DCTRL_Msk                            (0x01UL << USART2_RS485CTRL_DCTRL_Pos)                    /*!< USART2 RS485CTRL: DCTRL Mask        */
#define USART2_RS485CTRL_OINV_Pos                             5                                                         /*!< USART2 RS485CTRL: OINV Position     */
#define USART2_RS485CTRL_OINV_Msk                             (0x01UL << USART2_RS485CTRL_OINV_Pos)                     /*!< USART2 RS485CTRL: OINV Mask         */

// ----------------------------------  USART2_RS485ADRMATCH  --------------------------------------
#define USART2_RS485ADRMATCH_ADRMATCH_Pos                     0                                                         /*!< USART2 RS485ADRMATCH: ADRMATCH Position */
#define USART2_RS485ADRMATCH_ADRMATCH_Msk                     (0x000000ffUL << USART2_RS485ADRMATCH_ADRMATCH_Pos)       /*!< USART2 RS485ADRMATCH: ADRMATCH Mask */

// -------------------------------------  USART2_RS485DLY  ----------------------------------------
#define USART2_RS485DLY_DLY_Pos                               0                                                         /*!< USART2 RS485DLY: DLY Position       */
#define USART2_RS485DLY_DLY_Msk                               (0x000000ffUL << USART2_RS485DLY_DLY_Pos)                 /*!< USART2 RS485DLY: DLY Mask           */

// -------------------------------------  USART2_SYNCCTRL  ----------------------------------------
#define USART2_SYNCCTRL_SYNC_Pos                              0                                                         /*!< USART2 SYNCCTRL: SYNC Position      */
#define USART2_SYNCCTRL_SYNC_Msk                              (0x01UL << USART2_SYNCCTRL_SYNC_Pos)                      /*!< USART2 SYNCCTRL: SYNC Mask          */
#define USART2_SYNCCTRL_CSRC_Pos                              1                                                         /*!< USART2 SYNCCTRL: CSRC Position      */
#define USART2_SYNCCTRL_CSRC_Msk                              (0x01UL << USART2_SYNCCTRL_CSRC_Pos)                      /*!< USART2 SYNCCTRL: CSRC Mask          */
#define USART2_SYNCCTRL_FES_Pos                               2                                                         /*!< USART2 SYNCCTRL: FES Position       */
#define USART2_SYNCCTRL_FES_Msk                               (0x01UL << USART2_SYNCCTRL_FES_Pos)                       /*!< USART2 SYNCCTRL: FES Mask           */
#define USART2_SYNCCTRL_TSBYPASS_Pos                          3                                                         /*!< USART2 SYNCCTRL: TSBYPASS Position  */
#define USART2_SYNCCTRL_TSBYPASS_Msk                          (0x01UL << USART2_SYNCCTRL_TSBYPASS_Pos)                  /*!< USART2 SYNCCTRL: TSBYPASS Mask      */
#define USART2_SYNCCTRL_CSCEN_Pos                             4                                                         /*!< USART2 SYNCCTRL: CSCEN Position     */
#define USART2_SYNCCTRL_CSCEN_Msk                             (0x01UL << USART2_SYNCCTRL_CSCEN_Pos)                     /*!< USART2 SYNCCTRL: CSCEN Mask         */
#define USART2_SYNCCTRL_SSSDIS_Pos                            5                                                         /*!< USART2 SYNCCTRL: SSSDIS Position    */
#define USART2_SYNCCTRL_SSSDIS_Msk                            (0x01UL << USART2_SYNCCTRL_SSSDIS_Pos)                    /*!< USART2 SYNCCTRL: SSSDIS Mask        */
#define USART2_SYNCCTRL_CCCLR_Pos                             6                                                         /*!< USART2 SYNCCTRL: CCCLR Position     */
#define USART2_SYNCCTRL_CCCLR_Msk                             (0x01UL << USART2_SYNCCTRL_CCCLR_Pos)                     /*!< USART2 SYNCCTRL: CCCLR Mask         */

// ---------------------------------------  USART2_TER  -------------------------------------------
#define USART2_TER_TXEN_Pos                                   0                                                         /*!< USART2 TER: TXEN Position           */
#define USART2_TER_TXEN_Msk                                   (0x01UL << USART2_TER_TXEN_Pos)                           /*!< USART2 TER: TXEN Mask               */


// ------------------------------------------------------------------------------------------------
// -----                                USART3 Position & Mask                                -----
// ------------------------------------------------------------------------------------------------


// ---------------------------------------  USART3_DLL  -------------------------------------------
#define USART3_DLL_DLLSB_Pos                                  0                                                         /*!< USART3 DLL: DLLSB Position          */
#define USART3_DLL_DLLSB_Msk                                  (0x000000ffUL << USART3_DLL_DLLSB_Pos)                    /*!< USART3 DLL: DLLSB Mask              */

// ---------------------------------------  USART3_THR  -------------------------------------------
#define USART3_THR_THR_Pos                                    0                                                         /*!< USART3 THR: THR Position            */
#define USART3_THR_THR_Msk                                    (0x000000ffUL << USART3_THR_THR_Pos)                      /*!< USART3 THR: THR Mask                */

// ---------------------------------------  USART3_RBR  -------------------------------------------
#define USART3_RBR_RBR_Pos                                    0                                                         /*!< USART3 RBR: RBR Position            */
#define USART3_RBR_RBR_Msk                                    (0x000000ffUL << USART3_RBR_RBR_Pos)                      /*!< USART3 RBR: RBR Mask                */

// ---------------------------------------  USART3_IER  -------------------------------------------
#define USART3_IER_RBRIE_Pos                                  0                                                         /*!< USART3 IER: RBRIE Position          */
#define USART3_IER_RBRIE_Msk                                  (0x01UL << USART3_IER_RBRIE_Pos)                          /*!< USART3 IER: RBRIE Mask              */
#define USART3_IER_THREIE_Pos                                 1                                                         /*!< USART3 IER: THREIE Position         */
#define USART3_IER_THREIE_Msk                                 (0x01UL << USART3_IER_THREIE_Pos)                         /*!< USART3 IER: THREIE Mask             */
#define USART3_IER_RXIE_Pos                                   2                                                         /*!< USART3 IER: RXIE Position           */
#define USART3_IER_RXIE_Msk                                   (0x01UL << USART3_IER_RXIE_Pos)                           /*!< USART3 IER: RXIE Mask               */
#define USART3_IER_ABEOINTEN_Pos                              8                                                         /*!< USART3 IER: ABEOINTEN Position      */
#define USART3_IER_ABEOINTEN_Msk                              (0x01UL << USART3_IER_ABEOINTEN_Pos)                      /*!< USART3 IER: ABEOINTEN Mask          */
#define USART3_IER_ABTOINTEN_Pos                              9                                                         /*!< USART3 IER: ABTOINTEN Position      */
#define USART3_IER_ABTOINTEN_Msk                              (0x01UL << USART3_IER_ABTOINTEN_Pos)                      /*!< USART3 IER: ABTOINTEN Mask          */

// ---------------------------------------  USART3_DLM  -------------------------------------------
#define USART3_DLM_DLMSB_Pos                                  0                                                         /*!< USART3 DLM: DLMSB Position          */
#define USART3_DLM_DLMSB_Msk                                  (0x000000ffUL << USART3_DLM_DLMSB_Pos)                    /*!< USART3 DLM: DLMSB Mask              */

// ---------------------------------------  USART3_FCR  -------------------------------------------
#define USART3_FCR_FIFOEN_Pos                                 0                                                         /*!< USART3 FCR: FIFOEN Position         */
#define USART3_FCR_FIFOEN_Msk                                 (0x01UL << USART3_FCR_FIFOEN_Pos)                         /*!< USART3 FCR: FIFOEN Mask             */
#define USART3_FCR_RXFIFORES_Pos                              1                                                         /*!< USART3 FCR: RXFIFORES Position      */
#define USART3_FCR_RXFIFORES_Msk                              (0x01UL << USART3_FCR_RXFIFORES_Pos)                      /*!< USART3 FCR: RXFIFORES Mask          */
#define USART3_FCR_TXFIFORES_Pos                              2                                                         /*!< USART3 FCR: TXFIFORES Position      */
#define USART3_FCR_TXFIFORES_Msk                              (0x01UL << USART3_FCR_TXFIFORES_Pos)                      /*!< USART3 FCR: TXFIFORES Mask          */
#define USART3_FCR_DMAMODE_Pos                                3                                                         /*!< USART3 FCR: DMAMODE Position        */
#define USART3_FCR_DMAMODE_Msk                                (0x01UL << USART3_FCR_DMAMODE_Pos)                        /*!< USART3 FCR: DMAMODE Mask            */
#define USART3_FCR_RXTRIGLVL_Pos                              6                                                         /*!< USART3 FCR: RXTRIGLVL Position      */
#define USART3_FCR_RXTRIGLVL_Msk                              (0x03UL << USART3_FCR_RXTRIGLVL_Pos)                      /*!< USART3 FCR: RXTRIGLVL Mask          */

// ---------------------------------------  USART3_IIR  -------------------------------------------
#define USART3_IIR_INTSTATUS_Pos                              0                                                         /*!< USART3 IIR: INTSTATUS Position      */
#define USART3_IIR_INTSTATUS_Msk                              (0x01UL << USART3_IIR_INTSTATUS_Pos)                      /*!< USART3 IIR: INTSTATUS Mask          */
#define USART3_IIR_INTID_Pos                                  1                                                         /*!< USART3 IIR: INTID Position          */
#define USART3_IIR_INTID_Msk                                  (0x07UL << USART3_IIR_INTID_Pos)                          /*!< USART3 IIR: INTID Mask              */
#define USART3_IIR_FIFOENABLE_Pos                             6                                                         /*!< USART3 IIR: FIFOENABLE Position     */
#define USART3_IIR_FIFOENABLE_Msk                             (0x03UL << USART3_IIR_FIFOENABLE_Pos)                     /*!< USART3 IIR: FIFOENABLE Mask         */
#define USART3_IIR_ABEOINT_Pos                                8                                                         /*!< USART3 IIR: ABEOINT Position        */
#define USART3_IIR_ABEOINT_Msk                                (0x01UL << USART3_IIR_ABEOINT_Pos)                        /*!< USART3 IIR: ABEOINT Mask            */
#define USART3_IIR_ABTOINT_Pos                                9                                                         /*!< USART3 IIR: ABTOINT Position        */
#define USART3_IIR_ABTOINT_Msk                                (0x01UL << USART3_IIR_ABTOINT_Pos)                        /*!< USART3 IIR: ABTOINT Mask            */

// ---------------------------------------  USART3_LCR  -------------------------------------------
#define USART3_LCR_WLS_Pos                                    0                                                         /*!< USART3 LCR: WLS Position            */
#define USART3_LCR_WLS_Msk                                    (0x03UL << USART3_LCR_WLS_Pos)                            /*!< USART3 LCR: WLS Mask                */
#define USART3_LCR_SBS_Pos                                    2                                                         /*!< USART3 LCR: SBS Position            */
#define USART3_LCR_SBS_Msk                                    (0x01UL << USART3_LCR_SBS_Pos)                            /*!< USART3 LCR: SBS Mask                */
#define USART3_LCR_PE_Pos                                     3                                                         /*!< USART3 LCR: PE Position             */
#define USART3_LCR_PE_Msk                                     (0x01UL << USART3_LCR_PE_Pos)                             /*!< USART3 LCR: PE Mask                 */
#define USART3_LCR_PS_Pos                                     4                                                         /*!< USART3 LCR: PS Position             */
#define USART3_LCR_PS_Msk                                     (0x03UL << USART3_LCR_PS_Pos)                             /*!< USART3 LCR: PS Mask                 */
#define USART3_LCR_BC_Pos                                     6                                                         /*!< USART3 LCR: BC Position             */
#define USART3_LCR_BC_Msk                                     (0x01UL << USART3_LCR_BC_Pos)                             /*!< USART3 LCR: BC Mask                 */
#define USART3_LCR_DLAB_Pos                                   7                                                         /*!< USART3 LCR: DLAB Position           */
#define USART3_LCR_DLAB_Msk                                   (0x01UL << USART3_LCR_DLAB_Pos)                           /*!< USART3 LCR: DLAB Mask               */

// ---------------------------------------  USART3_LSR  -------------------------------------------
#define USART3_LSR_RDR_Pos                                    0                                                         /*!< USART3 LSR: RDR Position            */
#define USART3_LSR_RDR_Msk                                    (0x01UL << USART3_LSR_RDR_Pos)                            /*!< USART3 LSR: RDR Mask                */
#define USART3_LSR_OE_Pos                                     1                                                         /*!< USART3 LSR: OE Position             */
#define USART3_LSR_OE_Msk                                     (0x01UL << USART3_LSR_OE_Pos)                             /*!< USART3 LSR: OE Mask                 */
#define USART3_LSR_PE_Pos                                     2                                                         /*!< USART3 LSR: PE Position             */
#define USART3_LSR_PE_Msk                                     (0x01UL << USART3_LSR_PE_Pos)                             /*!< USART3 LSR: PE Mask                 */
#define USART3_LSR_FE_Pos                                     3                                                         /*!< USART3 LSR: FE Position             */
#define USART3_LSR_FE_Msk                                     (0x01UL << USART3_LSR_FE_Pos)                             /*!< USART3 LSR: FE Mask                 */
#define USART3_LSR_BI_Pos                                     4                                                         /*!< USART3 LSR: BI Position             */
#define USART3_LSR_BI_Msk                                     (0x01UL << USART3_LSR_BI_Pos)                             /*!< USART3 LSR: BI Mask                 */
#define USART3_LSR_THRE_Pos                                   5                                                         /*!< USART3 LSR: THRE Position           */
#define USART3_LSR_THRE_Msk                                   (0x01UL << USART3_LSR_THRE_Pos)                           /*!< USART3 LSR: THRE Mask               */
#define USART3_LSR_TEMT_Pos                                   6                                                         /*!< USART3 LSR: TEMT Position           */
#define USART3_LSR_TEMT_Msk                                   (0x01UL << USART3_LSR_TEMT_Pos)                           /*!< USART3 LSR: TEMT Mask               */
#define USART3_LSR_RXFE_Pos                                   7                                                         /*!< USART3 LSR: RXFE Position           */
#define USART3_LSR_RXFE_Msk                                   (0x01UL << USART3_LSR_RXFE_Pos)                           /*!< USART3 LSR: RXFE Mask               */
#define USART3_LSR_TXERR_Pos                                  8                                                         /*!< USART3 LSR: TXERR Position          */
#define USART3_LSR_TXERR_Msk                                  (0x01UL << USART3_LSR_TXERR_Pos)                          /*!< USART3 LSR: TXERR Mask              */

// ---------------------------------------  USART3_SCR  -------------------------------------------
#define USART3_SCR_PAD_Pos                                    0                                                         /*!< USART3 SCR: PAD Position            */
#define USART3_SCR_PAD_Msk                                    (0x000000ffUL << USART3_SCR_PAD_Pos)                      /*!< USART3 SCR: PAD Mask                */

// ---------------------------------------  USART3_ACR  -------------------------------------------
#define USART3_ACR_START_Pos                                  0                                                         /*!< USART3 ACR: START Position          */
#define USART3_ACR_START_Msk                                  (0x01UL << USART3_ACR_START_Pos)                          /*!< USART3 ACR: START Mask              */
#define USART3_ACR_MODE_Pos                                   1                                                         /*!< USART3 ACR: MODE Position           */
#define USART3_ACR_MODE_Msk                                   (0x01UL << USART3_ACR_MODE_Pos)                           /*!< USART3 ACR: MODE Mask               */
#define USART3_ACR_AUTORESTART_Pos                            2                                                         /*!< USART3 ACR: AUTORESTART Position    */
#define USART3_ACR_AUTORESTART_Msk                            (0x01UL << USART3_ACR_AUTORESTART_Pos)                    /*!< USART3 ACR: AUTORESTART Mask        */
#define USART3_ACR_ABEOINTCLR_Pos                             8                                                         /*!< USART3 ACR: ABEOINTCLR Position     */
#define USART3_ACR_ABEOINTCLR_Msk                             (0x01UL << USART3_ACR_ABEOINTCLR_Pos)                     /*!< USART3 ACR: ABEOINTCLR Mask         */
#define USART3_ACR_ABTOINTCLR_Pos                             9                                                         /*!< USART3 ACR: ABTOINTCLR Position     */
#define USART3_ACR_ABTOINTCLR_Msk                             (0x01UL << USART3_ACR_ABTOINTCLR_Pos)                     /*!< USART3 ACR: ABTOINTCLR Mask         */

// ---------------------------------------  USART3_ICR  -------------------------------------------
#define USART3_ICR_IRDAEN_Pos                                 0                                                         /*!< USART3 ICR: IRDAEN Position         */
#define USART3_ICR_IRDAEN_Msk                                 (0x01UL << USART3_ICR_IRDAEN_Pos)                         /*!< USART3 ICR: IRDAEN Mask             */
#define USART3_ICR_IRDAINV_Pos                                1                                                         /*!< USART3 ICR: IRDAINV Position        */
#define USART3_ICR_IRDAINV_Msk                                (0x01UL << USART3_ICR_IRDAINV_Pos)                        /*!< USART3 ICR: IRDAINV Mask            */
#define USART3_ICR_FIXPULSEEN_Pos                             2                                                         /*!< USART3 ICR: FIXPULSEEN Position     */
#define USART3_ICR_FIXPULSEEN_Msk                             (0x01UL << USART3_ICR_FIXPULSEEN_Pos)                     /*!< USART3 ICR: FIXPULSEEN Mask         */
#define USART3_ICR_PULSEDIV_Pos                               3                                                         /*!< USART3 ICR: PULSEDIV Position       */
#define USART3_ICR_PULSEDIV_Msk                               (0x07UL << USART3_ICR_PULSEDIV_Pos)                       /*!< USART3 ICR: PULSEDIV Mask           */

// ---------------------------------------  USART3_FDR  -------------------------------------------
#define USART3_FDR_DIVADDVAL_Pos                              0                                                         /*!< USART3 FDR: DIVADDVAL Position      */
#define USART3_FDR_DIVADDVAL_Msk                              (0x0fUL << USART3_FDR_DIVADDVAL_Pos)                      /*!< USART3 FDR: DIVADDVAL Mask          */
#define USART3_FDR_MULVAL_Pos                                 4                                                         /*!< USART3 FDR: MULVAL Position         */
#define USART3_FDR_MULVAL_Msk                                 (0x0fUL << USART3_FDR_MULVAL_Pos)                         /*!< USART3 FDR: MULVAL Mask             */

// ---------------------------------------  USART3_OSR  -------------------------------------------
#define USART3_OSR_OSFRAC_Pos                                 1                                                         /*!< USART3 OSR: OSFRAC Position         */
#define USART3_OSR_OSFRAC_Msk                                 (0x07UL << USART3_OSR_OSFRAC_Pos)                         /*!< USART3 OSR: OSFRAC Mask             */
#define USART3_OSR_OSINT_Pos                                  4                                                         /*!< USART3 OSR: OSINT Position          */
#define USART3_OSR_OSINT_Msk                                  (0x0fUL << USART3_OSR_OSINT_Pos)                          /*!< USART3 OSR: OSINT Mask              */
#define USART3_OSR_FDINT_Pos                                  8                                                         /*!< USART3 OSR: FDINT Position          */
#define USART3_OSR_FDINT_Msk                                  (0x7fUL << USART3_OSR_FDINT_Pos)                          /*!< USART3 OSR: FDINT Mask              */

// ---------------------------------------  USART3_HDEN  ------------------------------------------
#define USART3_HDEN_HDEN_Pos                                  0                                                         /*!< USART3 HDEN: HDEN Position          */
#define USART3_HDEN_HDEN_Msk                                  (0x01UL << USART3_HDEN_HDEN_Pos)                          /*!< USART3 HDEN: HDEN Mask              */

// -------------------------------------  USART3_SCICTRL  -----------------------------------------
#define USART3_SCICTRL_SCIEN_Pos                              0                                                         /*!< USART3 SCICTRL: SCIEN Position      */
#define USART3_SCICTRL_SCIEN_Msk                              (0x01UL << USART3_SCICTRL_SCIEN_Pos)                      /*!< USART3 SCICTRL: SCIEN Mask          */
#define USART3_SCICTRL_NACKDIS_Pos                            1                                                         /*!< USART3 SCICTRL: NACKDIS Position    */
#define USART3_SCICTRL_NACKDIS_Msk                            (0x01UL << USART3_SCICTRL_NACKDIS_Pos)                    /*!< USART3 SCICTRL: NACKDIS Mask        */
#define USART3_SCICTRL_PROTSEL_Pos                            2                                                         /*!< USART3 SCICTRL: PROTSEL Position    */
#define USART3_SCICTRL_PROTSEL_Msk                            (0x01UL << USART3_SCICTRL_PROTSEL_Pos)                    /*!< USART3 SCICTRL: PROTSEL Mask        */
#define USART3_SCICTRL_TXRETRY_Pos                            5                                                         /*!< USART3 SCICTRL: TXRETRY Position    */
#define USART3_SCICTRL_TXRETRY_Msk                            (0x07UL << USART3_SCICTRL_TXRETRY_Pos)                    /*!< USART3 SCICTRL: TXRETRY Mask        */
#define USART3_SCICTRL_GUARDTIME_Pos                          8                                                         /*!< USART3 SCICTRL: GUARDTIME Position  */
#define USART3_SCICTRL_GUARDTIME_Msk                          (0x000000ffUL << USART3_SCICTRL_GUARDTIME_Pos)            /*!< USART3 SCICTRL: GUARDTIME Mask      */

// ------------------------------------  USART3_RS485CTRL  ----------------------------------------
#define USART3_RS485CTRL_NMMEN_Pos                            0                                                         /*!< USART3 RS485CTRL: NMMEN Position    */
#define USART3_RS485CTRL_NMMEN_Msk                            (0x01UL << USART3_RS485CTRL_NMMEN_Pos)                    /*!< USART3 RS485CTRL: NMMEN Mask        */
#define USART3_RS485CTRL_RXDIS_Pos                            1                                                         /*!< USART3 RS485CTRL: RXDIS Position    */
#define USART3_RS485CTRL_RXDIS_Msk                            (0x01UL << USART3_RS485CTRL_RXDIS_Pos)                    /*!< USART3 RS485CTRL: RXDIS Mask        */
#define USART3_RS485CTRL_AADEN_Pos                            2                                                         /*!< USART3 RS485CTRL: AADEN Position    */
#define USART3_RS485CTRL_AADEN_Msk                            (0x01UL << USART3_RS485CTRL_AADEN_Pos)                    /*!< USART3 RS485CTRL: AADEN Mask        */
#define USART3_RS485CTRL_DCTRL_Pos                            4                                                         /*!< USART3 RS485CTRL: DCTRL Position    */
#define USART3_RS485CTRL_DCTRL_Msk                            (0x01UL << USART3_RS485CTRL_DCTRL_Pos)                    /*!< USART3 RS485CTRL: DCTRL Mask        */
#define USART3_RS485CTRL_OINV_Pos                             5                                                         /*!< USART3 RS485CTRL: OINV Position     */
#define USART3_RS485CTRL_OINV_Msk                             (0x01UL << USART3_RS485CTRL_OINV_Pos)                     /*!< USART3 RS485CTRL: OINV Mask         */

// ----------------------------------  USART3_RS485ADRMATCH  --------------------------------------
#define USART3_RS485ADRMATCH_ADRMATCH_Pos                     0                                                         /*!< USART3 RS485ADRMATCH: ADRMATCH Position */
#define USART3_RS485ADRMATCH_ADRMATCH_Msk                     (0x000000ffUL << USART3_RS485ADRMATCH_ADRMATCH_Pos)       /*!< USART3 RS485ADRMATCH: ADRMATCH Mask */

// -------------------------------------  USART3_RS485DLY  ----------------------------------------
#define USART3_RS485DLY_DLY_Pos                               0                                                         /*!< USART3 RS485DLY: DLY Position       */
#define USART3_RS485DLY_DLY_Msk                               (0x000000ffUL << USART3_RS485DLY_DLY_Pos)                 /*!< USART3 RS485DLY: DLY Mask           */

// -------------------------------------  USART3_SYNCCTRL  ----------------------------------------
#define USART3_SYNCCTRL_SYNC_Pos                              0                                                         /*!< USART3 SYNCCTRL: SYNC Position      */
#define USART3_SYNCCTRL_SYNC_Msk                              (0x01UL << USART3_SYNCCTRL_SYNC_Pos)                      /*!< USART3 SYNCCTRL: SYNC Mask          */
#define USART3_SYNCCTRL_CSRC_Pos                              1                                                         /*!< USART3 SYNCCTRL: CSRC Position      */
#define USART3_SYNCCTRL_CSRC_Msk                              (0x01UL << USART3_SYNCCTRL_CSRC_Pos)                      /*!< USART3 SYNCCTRL: CSRC Mask          */
#define USART3_SYNCCTRL_FES_Pos                               2                                                         /*!< USART3 SYNCCTRL: FES Position       */
#define USART3_SYNCCTRL_FES_Msk                               (0x01UL << USART3_SYNCCTRL_FES_Pos)                       /*!< USART3 SYNCCTRL: FES Mask           */
#define USART3_SYNCCTRL_TSBYPASS_Pos                          3                                                         /*!< USART3 SYNCCTRL: TSBYPASS Position  */
#define USART3_SYNCCTRL_TSBYPASS_Msk                          (0x01UL << USART3_SYNCCTRL_TSBYPASS_Pos)                  /*!< USART3 SYNCCTRL: TSBYPASS Mask      */
#define USART3_SYNCCTRL_CSCEN_Pos                             4                                                         /*!< USART3 SYNCCTRL: CSCEN Position     */
#define USART3_SYNCCTRL_CSCEN_Msk                             (0x01UL << USART3_SYNCCTRL_CSCEN_Pos)                     /*!< USART3 SYNCCTRL: CSCEN Mask         */
#define USART3_SYNCCTRL_SSSDIS_Pos                            5                                                         /*!< USART3 SYNCCTRL: SSSDIS Position    */
#define USART3_SYNCCTRL_SSSDIS_Msk                            (0x01UL << USART3_SYNCCTRL_SSSDIS_Pos)                    /*!< USART3 SYNCCTRL: SSSDIS Mask        */
#define USART3_SYNCCTRL_CCCLR_Pos                             6                                                         /*!< USART3 SYNCCTRL: CCCLR Position     */
#define USART3_SYNCCTRL_CCCLR_Msk                             (0x01UL << USART3_SYNCCTRL_CCCLR_Pos)                     /*!< USART3 SYNCCTRL: CCCLR Mask         */

// ---------------------------------------  USART3_TER  -------------------------------------------
#define USART3_TER_TXEN_Pos                                   0                                                         /*!< USART3 TER: TXEN Position           */
#define USART3_TER_TXEN_Msk                                   (0x01UL << USART3_TER_TXEN_Pos)                           /*!< USART3 TER: TXEN Mask               */


// ------------------------------------------------------------------------------------------------
// -----                                 UART1 Position & Mask                                -----
// ------------------------------------------------------------------------------------------------


// ----------------------------------------  UART1_RBR  -------------------------------------------
#define UART1_RBR_RBR_Pos                                     0                                                         /*!< UART1 RBR: RBR Position             */
#define UART1_RBR_RBR_Msk                                     (0x000000ffUL << UART1_RBR_RBR_Pos)                       /*!< UART1 RBR: RBR Mask                 */

// ----------------------------------------  UART1_THR  -------------------------------------------
#define UART1_THR_THR_Pos                                     0                                                         /*!< UART1 THR: THR Position             */
#define UART1_THR_THR_Msk                                     (0x000000ffUL << UART1_THR_THR_Pos)                       /*!< UART1 THR: THR Mask                 */

// ----------------------------------------  UART1_DLL  -------------------------------------------
#define UART1_DLL_DLLSB_Pos                                   0                                                         /*!< UART1 DLL: DLLSB Position           */
#define UART1_DLL_DLLSB_Msk                                   (0x000000ffUL << UART1_DLL_DLLSB_Pos)                     /*!< UART1 DLL: DLLSB Mask               */

// ----------------------------------------  UART1_DLM  -------------------------------------------
#define UART1_DLM_DLMSB_Pos                                   0                                                         /*!< UART1 DLM: DLMSB Position           */
#define UART1_DLM_DLMSB_Msk                                   (0x000000ffUL << UART1_DLM_DLMSB_Pos)                     /*!< UART1 DLM: DLMSB Mask               */

// ----------------------------------------  UART1_IER  -------------------------------------------
#define UART1_IER_RBRIE_Pos                                   0                                                         /*!< UART1 IER: RBRIE Position           */
#define UART1_IER_RBRIE_Msk                                   (0x01UL << UART1_IER_RBRIE_Pos)                           /*!< UART1 IER: RBRIE Mask               */
#define UART1_IER_THREIE_Pos                                  1                                                         /*!< UART1 IER: THREIE Position          */
#define UART1_IER_THREIE_Msk                                  (0x01UL << UART1_IER_THREIE_Pos)                          /*!< UART1 IER: THREIE Mask              */
#define UART1_IER_RXIE_Pos                                    2                                                         /*!< UART1 IER: RXIE Position            */
#define UART1_IER_RXIE_Msk                                    (0x01UL << UART1_IER_RXIE_Pos)                            /*!< UART1 IER: RXIE Mask                */
#define UART1_IER_MSIE_Pos                                    3                                                         /*!< UART1 IER: MSIE Position            */
#define UART1_IER_MSIE_Msk                                    (0x01UL << UART1_IER_MSIE_Pos)                            /*!< UART1 IER: MSIE Mask                */
#define UART1_IER_CTSIE_Pos                                   7                                                         /*!< UART1 IER: CTSIE Position           */
#define UART1_IER_CTSIE_Msk                                   (0x01UL << UART1_IER_CTSIE_Pos)                           /*!< UART1 IER: CTSIE Mask               */
#define UART1_IER_ABEOIE_Pos                                  8                                                         /*!< UART1 IER: ABEOIE Position          */
#define UART1_IER_ABEOIE_Msk                                  (0x01UL << UART1_IER_ABEOIE_Pos)                          /*!< UART1 IER: ABEOIE Mask              */
#define UART1_IER_ABTOIE_Pos                                  9                                                         /*!< UART1 IER: ABTOIE Position          */
#define UART1_IER_ABTOIE_Msk                                  (0x01UL << UART1_IER_ABTOIE_Pos)                          /*!< UART1 IER: ABTOIE Mask              */

// ----------------------------------------  UART1_IIR  -------------------------------------------
#define UART1_IIR_INTSTATUS_Pos                               0                                                         /*!< UART1 IIR: INTSTATUS Position       */
#define UART1_IIR_INTSTATUS_Msk                               (0x01UL << UART1_IIR_INTSTATUS_Pos)                       /*!< UART1 IIR: INTSTATUS Mask           */
#define UART1_IIR_INTID_Pos                                   1                                                         /*!< UART1 IIR: INTID Position           */
#define UART1_IIR_INTID_Msk                                   (0x07UL << UART1_IIR_INTID_Pos)                           /*!< UART1 IIR: INTID Mask               */
#define UART1_IIR_FIFOENABLE_Pos                              6                                                         /*!< UART1 IIR: FIFOENABLE Position      */
#define UART1_IIR_FIFOENABLE_Msk                              (0x03UL << UART1_IIR_FIFOENABLE_Pos)                      /*!< UART1 IIR: FIFOENABLE Mask          */
#define UART1_IIR_ABEOINT_Pos                                 8                                                         /*!< UART1 IIR: ABEOINT Position         */
#define UART1_IIR_ABEOINT_Msk                                 (0x01UL << UART1_IIR_ABEOINT_Pos)                         /*!< UART1 IIR: ABEOINT Mask             */
#define UART1_IIR_ABTOINT_Pos                                 9                                                         /*!< UART1 IIR: ABTOINT Position         */
#define UART1_IIR_ABTOINT_Msk                                 (0x01UL << UART1_IIR_ABTOINT_Pos)                         /*!< UART1 IIR: ABTOINT Mask             */

// ----------------------------------------  UART1_FCR  -------------------------------------------
#define UART1_FCR_FIFOEN_Pos                                  0                                                         /*!< UART1 FCR: FIFOEN Position          */
#define UART1_FCR_FIFOEN_Msk                                  (0x01UL << UART1_FCR_FIFOEN_Pos)                          /*!< UART1 FCR: FIFOEN Mask              */
#define UART1_FCR_RXFIFORES_Pos                               1                                                         /*!< UART1 FCR: RXFIFORES Position       */
#define UART1_FCR_RXFIFORES_Msk                               (0x01UL << UART1_FCR_RXFIFORES_Pos)                       /*!< UART1 FCR: RXFIFORES Mask           */
#define UART1_FCR_TXFIFORES_Pos                               2                                                         /*!< UART1 FCR: TXFIFORES Position       */
#define UART1_FCR_TXFIFORES_Msk                               (0x01UL << UART1_FCR_TXFIFORES_Pos)                       /*!< UART1 FCR: TXFIFORES Mask           */
#define UART1_FCR_DMAMODE_Pos                                 3                                                         /*!< UART1 FCR: DMAMODE Position         */
#define UART1_FCR_DMAMODE_Msk                                 (0x01UL << UART1_FCR_DMAMODE_Pos)                         /*!< UART1 FCR: DMAMODE Mask             */
#define UART1_FCR_RXTRIGLVL_Pos                               6                                                         /*!< UART1 FCR: RXTRIGLVL Position       */
#define UART1_FCR_RXTRIGLVL_Msk                               (0x03UL << UART1_FCR_RXTRIGLVL_Pos)                       /*!< UART1 FCR: RXTRIGLVL Mask           */

// ----------------------------------------  UART1_LCR  -------------------------------------------
#define UART1_LCR_WLS_Pos                                     0                                                         /*!< UART1 LCR: WLS Position             */
#define UART1_LCR_WLS_Msk                                     (0x03UL << UART1_LCR_WLS_Pos)                             /*!< UART1 LCR: WLS Mask                 */
#define UART1_LCR_SBS_Pos                                     2                                                         /*!< UART1 LCR: SBS Position             */
#define UART1_LCR_SBS_Msk                                     (0x01UL << UART1_LCR_SBS_Pos)                             /*!< UART1 LCR: SBS Mask                 */
#define UART1_LCR_PE_Pos                                      3                                                         /*!< UART1 LCR: PE Position              */
#define UART1_LCR_PE_Msk                                      (0x01UL << UART1_LCR_PE_Pos)                              /*!< UART1 LCR: PE Mask                  */
#define UART1_LCR_PS_Pos                                      4                                                         /*!< UART1 LCR: PS Position              */
#define UART1_LCR_PS_Msk                                      (0x03UL << UART1_LCR_PS_Pos)                              /*!< UART1 LCR: PS Mask                  */
#define UART1_LCR_BC_Pos                                      6                                                         /*!< UART1 LCR: BC Position              */
#define UART1_LCR_BC_Msk                                      (0x01UL << UART1_LCR_BC_Pos)                              /*!< UART1 LCR: BC Mask                  */
#define UART1_LCR_DLAB_Pos                                    7                                                         /*!< UART1 LCR: DLAB Position            */
#define UART1_LCR_DLAB_Msk                                    (0x01UL << UART1_LCR_DLAB_Pos)                            /*!< UART1 LCR: DLAB Mask                */

// ----------------------------------------  UART1_MCR  -------------------------------------------
#define UART1_MCR_DTRCTRL_Pos                                 0                                                         /*!< UART1 MCR: DTRCTRL Position         */
#define UART1_MCR_DTRCTRL_Msk                                 (0x01UL << UART1_MCR_DTRCTRL_Pos)                         /*!< UART1 MCR: DTRCTRL Mask             */
#define UART1_MCR_RTSCTRL_Pos                                 1                                                         /*!< UART1 MCR: RTSCTRL Position         */
#define UART1_MCR_RTSCTRL_Msk                                 (0x01UL << UART1_MCR_RTSCTRL_Pos)                         /*!< UART1 MCR: RTSCTRL Mask             */
#define UART1_MCR_LMS_Pos                                     4                                                         /*!< UART1 MCR: LMS Position             */
#define UART1_MCR_LMS_Msk                                     (0x01UL << UART1_MCR_LMS_Pos)                             /*!< UART1 MCR: LMS Mask                 */
#define UART1_MCR_RTSEN_Pos                                   6                                                         /*!< UART1 MCR: RTSEN Position           */
#define UART1_MCR_RTSEN_Msk                                   (0x01UL << UART1_MCR_RTSEN_Pos)                           /*!< UART1 MCR: RTSEN Mask               */
#define UART1_MCR_CTSEN_Pos                                   7                                                         /*!< UART1 MCR: CTSEN Position           */
#define UART1_MCR_CTSEN_Msk                                   (0x01UL << UART1_MCR_CTSEN_Pos)                           /*!< UART1 MCR: CTSEN Mask               */

// ----------------------------------------  UART1_LSR  -------------------------------------------
#define UART1_LSR_RDR_Pos                                     0                                                         /*!< UART1 LSR: RDR Position             */
#define UART1_LSR_RDR_Msk                                     (0x01UL << UART1_LSR_RDR_Pos)                             /*!< UART1 LSR: RDR Mask                 */
#define UART1_LSR_OE_Pos                                      1                                                         /*!< UART1 LSR: OE Position              */
#define UART1_LSR_OE_Msk                                      (0x01UL << UART1_LSR_OE_Pos)                              /*!< UART1 LSR: OE Mask                  */
#define UART1_LSR_PE_Pos                                      2                                                         /*!< UART1 LSR: PE Position              */
#define UART1_LSR_PE_Msk                                      (0x01UL << UART1_LSR_PE_Pos)                              /*!< UART1 LSR: PE Mask                  */
#define UART1_LSR_FE_Pos                                      3                                                         /*!< UART1 LSR: FE Position              */
#define UART1_LSR_FE_Msk                                      (0x01UL << UART1_LSR_FE_Pos)                              /*!< UART1 LSR: FE Mask                  */
#define UART1_LSR_BI_Pos                                      4                                                         /*!< UART1 LSR: BI Position              */
#define UART1_LSR_BI_Msk                                      (0x01UL << UART1_LSR_BI_Pos)                              /*!< UART1 LSR: BI Mask                  */
#define UART1_LSR_THRE_Pos                                    5                                                         /*!< UART1 LSR: THRE Position            */
#define UART1_LSR_THRE_Msk                                    (0x01UL << UART1_LSR_THRE_Pos)                            /*!< UART1 LSR: THRE Mask                */
#define UART1_LSR_TEMT_Pos                                    6                                                         /*!< UART1 LSR: TEMT Position            */
#define UART1_LSR_TEMT_Msk                                    (0x01UL << UART1_LSR_TEMT_Pos)                            /*!< UART1 LSR: TEMT Mask                */
#define UART1_LSR_RXFE_Pos                                    7                                                         /*!< UART1 LSR: RXFE Position            */
#define UART1_LSR_RXFE_Msk                                    (0x01UL << UART1_LSR_RXFE_Pos)                            /*!< UART1 LSR: RXFE Mask                */

// ----------------------------------------  UART1_MSR  -------------------------------------------
#define UART1_MSR_DCTS_Pos                                    0                                                         /*!< UART1 MSR: DCTS Position            */
#define UART1_MSR_DCTS_Msk                                    (0x01UL << UART1_MSR_DCTS_Pos)                            /*!< UART1 MSR: DCTS Mask                */
#define UART1_MSR_DDSR_Pos                                    1                                                         /*!< UART1 MSR: DDSR Position            */
#define UART1_MSR_DDSR_Msk                                    (0x01UL << UART1_MSR_DDSR_Pos)                            /*!< UART1 MSR: DDSR Mask                */
#define UART1_MSR_TERI_Pos                                    2                                                         /*!< UART1 MSR: TERI Position            */
#define UART1_MSR_TERI_Msk                                    (0x01UL << UART1_MSR_TERI_Pos)                            /*!< UART1 MSR: TERI Mask                */
#define UART1_MSR_DDCD_Pos                                    3                                                         /*!< UART1 MSR: DDCD Position            */
#define UART1_MSR_DDCD_Msk                                    (0x01UL << UART1_MSR_DDCD_Pos)                            /*!< UART1 MSR: DDCD Mask                */
#define UART1_MSR_CTS_Pos                                     4                                                         /*!< UART1 MSR: CTS Position             */
#define UART1_MSR_CTS_Msk                                     (0x01UL << UART1_MSR_CTS_Pos)                             /*!< UART1 MSR: CTS Mask                 */
#define UART1_MSR_DSR_Pos                                     5                                                         /*!< UART1 MSR: DSR Position             */
#define UART1_MSR_DSR_Msk                                     (0x01UL << UART1_MSR_DSR_Pos)                             /*!< UART1 MSR: DSR Mask                 */
#define UART1_MSR_RI_Pos                                      6                                                         /*!< UART1 MSR: RI Position              */
#define UART1_MSR_RI_Msk                                      (0x01UL << UART1_MSR_RI_Pos)                              /*!< UART1 MSR: RI Mask                  */
#define UART1_MSR_DCD_Pos                                     7                                                         /*!< UART1 MSR: DCD Position             */
#define UART1_MSR_DCD_Msk                                     (0x01UL << UART1_MSR_DCD_Pos)                             /*!< UART1 MSR: DCD Mask                 */

// ----------------------------------------  UART1_SCR  -------------------------------------------
#define UART1_SCR_Pad_Pos                                     0                                                         /*!< UART1 SCR: Pad Position             */
#define UART1_SCR_Pad_Msk                                     (0x000000ffUL << UART1_SCR_Pad_Pos)                       /*!< UART1 SCR: Pad Mask                 */

// ----------------------------------------  UART1_ACR  -------------------------------------------
#define UART1_ACR_START_Pos                                   0                                                         /*!< UART1 ACR: START Position           */
#define UART1_ACR_START_Msk                                   (0x01UL << UART1_ACR_START_Pos)                           /*!< UART1 ACR: START Mask               */
#define UART1_ACR_MODE_Pos                                    1                                                         /*!< UART1 ACR: MODE Position            */
#define UART1_ACR_MODE_Msk                                    (0x01UL << UART1_ACR_MODE_Pos)                            /*!< UART1 ACR: MODE Mask                */
#define UART1_ACR_AUTORESTART_Pos                             2                                                         /*!< UART1 ACR: AUTORESTART Position     */
#define UART1_ACR_AUTORESTART_Msk                             (0x01UL << UART1_ACR_AUTORESTART_Pos)                     /*!< UART1 ACR: AUTORESTART Mask         */
#define UART1_ACR_ABEOINTCLR_Pos                              8                                                         /*!< UART1 ACR: ABEOINTCLR Position      */
#define UART1_ACR_ABEOINTCLR_Msk                              (0x01UL << UART1_ACR_ABEOINTCLR_Pos)                      /*!< UART1 ACR: ABEOINTCLR Mask          */
#define UART1_ACR_ABTOINTCLR_Pos                              9                                                         /*!< UART1 ACR: ABTOINTCLR Position      */
#define UART1_ACR_ABTOINTCLR_Msk                              (0x01UL << UART1_ACR_ABTOINTCLR_Pos)                      /*!< UART1 ACR: ABTOINTCLR Mask          */

// ----------------------------------------  UART1_FDR  -------------------------------------------
#define UART1_FDR_DIVADDVAL_Pos                               0                                                         /*!< UART1 FDR: DIVADDVAL Position       */
#define UART1_FDR_DIVADDVAL_Msk                               (0x0fUL << UART1_FDR_DIVADDVAL_Pos)                       /*!< UART1 FDR: DIVADDVAL Mask           */
#define UART1_FDR_MULVAL_Pos                                  4                                                         /*!< UART1 FDR: MULVAL Position          */
#define UART1_FDR_MULVAL_Msk                                  (0x0fUL << UART1_FDR_MULVAL_Pos)                          /*!< UART1 FDR: MULVAL Mask              */

// ----------------------------------------  UART1_TER  -------------------------------------------
#define UART1_TER_TXEN_Pos                                    7                                                         /*!< UART1 TER: TXEN Position            */
#define UART1_TER_TXEN_Msk                                    (0x01UL << UART1_TER_TXEN_Pos)                            /*!< UART1 TER: TXEN Mask                */

// -------------------------------------  UART1_RS485CTRL  ----------------------------------------
#define UART1_RS485CTRL_NMMEN_Pos                             0                                                         /*!< UART1 RS485CTRL: NMMEN Position     */
#define UART1_RS485CTRL_NMMEN_Msk                             (0x01UL << UART1_RS485CTRL_NMMEN_Pos)                     /*!< UART1 RS485CTRL: NMMEN Mask         */
#define UART1_RS485CTRL_RXDIS_Pos                             1                                                         /*!< UART1 RS485CTRL: RXDIS Position     */
#define UART1_RS485CTRL_RXDIS_Msk                             (0x01UL << UART1_RS485CTRL_RXDIS_Pos)                     /*!< UART1 RS485CTRL: RXDIS Mask         */
#define UART1_RS485CTRL_AADEN_Pos                             2                                                         /*!< UART1 RS485CTRL: AADEN Position     */
#define UART1_RS485CTRL_AADEN_Msk                             (0x01UL << UART1_RS485CTRL_AADEN_Pos)                     /*!< UART1 RS485CTRL: AADEN Mask         */
#define UART1_RS485CTRL_SEL_Pos                               3                                                         /*!< UART1 RS485CTRL: SEL Position       */
#define UART1_RS485CTRL_SEL_Msk                               (0x01UL << UART1_RS485CTRL_SEL_Pos)                       /*!< UART1 RS485CTRL: SEL Mask           */
#define UART1_RS485CTRL_DCTRL_Pos                             4                                                         /*!< UART1 RS485CTRL: DCTRL Position     */
#define UART1_RS485CTRL_DCTRL_Msk                             (0x01UL << UART1_RS485CTRL_DCTRL_Pos)                     /*!< UART1 RS485CTRL: DCTRL Mask         */
#define UART1_RS485CTRL_OINV_Pos                              5                                                         /*!< UART1 RS485CTRL: OINV Position      */
#define UART1_RS485CTRL_OINV_Msk                              (0x01UL << UART1_RS485CTRL_OINV_Pos)                      /*!< UART1 RS485CTRL: OINV Mask          */

// -----------------------------------  UART1_RS485ADRMATCH  --------------------------------------
#define UART1_RS485ADRMATCH_ADRMATCH_Pos                      0                                                         /*!< UART1 RS485ADRMATCH: ADRMATCH Position */
#define UART1_RS485ADRMATCH_ADRMATCH_Msk                      (0x000000ffUL << UART1_RS485ADRMATCH_ADRMATCH_Pos)        /*!< UART1 RS485ADRMATCH: ADRMATCH Mask  */

// -------------------------------------  UART1_RS485DLY  -----------------------------------------
#define UART1_RS485DLY_DLY_Pos                                0                                                         /*!< UART1 RS485DLY: DLY Position        */
#define UART1_RS485DLY_DLY_Msk                                (0x000000ffUL << UART1_RS485DLY_DLY_Pos)                  /*!< UART1 RS485DLY: DLY Mask            */

// --------------------------------------  UART1_FIFOLVL  -----------------------------------------
#define UART1_FIFOLVL_RXFIFILVL_Pos                           0                                                         /*!< UART1 FIFOLVL: RXFIFILVL Position   */
#define UART1_FIFOLVL_RXFIFILVL_Msk                           (0x0fUL << UART1_FIFOLVL_RXFIFILVL_Pos)                   /*!< UART1 FIFOLVL: RXFIFILVL Mask       */
#define UART1_FIFOLVL_TXFIFOLVL_Pos                           8                                                         /*!< UART1 FIFOLVL: TXFIFOLVL Position   */
#define UART1_FIFOLVL_TXFIFOLVL_Msk                           (0x0fUL << UART1_FIFOLVL_TXFIFOLVL_Pos)                   /*!< UART1 FIFOLVL: TXFIFOLVL Mask       */


// ------------------------------------------------------------------------------------------------
// -----                                 SSP0 Position & Mask                                 -----
// ------------------------------------------------------------------------------------------------


// ----------------------------------------  SSP0_CR0  --------------------------------------------
#define SSP0_CR0_DSS_Pos                                      0                                                         /*!< SSP0 CR0: DSS Position              */
#define SSP0_CR0_DSS_Msk                                      (0x0fUL << SSP0_CR0_DSS_Pos)                              /*!< SSP0 CR0: DSS Mask                  */
#define SSP0_CR0_FRF_Pos                                      4                                                         /*!< SSP0 CR0: FRF Position              */
#define SSP0_CR0_FRF_Msk                                      (0x03UL << SSP0_CR0_FRF_Pos)                              /*!< SSP0 CR0: FRF Mask                  */
#define SSP0_CR0_CPOL_Pos                                     6                                                         /*!< SSP0 CR0: CPOL Position             */
#define SSP0_CR0_CPOL_Msk                                     (0x01UL << SSP0_CR0_CPOL_Pos)                             /*!< SSP0 CR0: CPOL Mask                 */
#define SSP0_CR0_CPHA_Pos                                     7                                                         /*!< SSP0 CR0: CPHA Position             */
#define SSP0_CR0_CPHA_Msk                                     (0x01UL << SSP0_CR0_CPHA_Pos)                             /*!< SSP0 CR0: CPHA Mask                 */
#define SSP0_CR0_SCR_Pos                                      8                                                         /*!< SSP0 CR0: SCR Position              */
#define SSP0_CR0_SCR_Msk                                      (0x000000ffUL << SSP0_CR0_SCR_Pos)                        /*!< SSP0 CR0: SCR Mask                  */

// ----------------------------------------  SSP0_CR1  --------------------------------------------
#define SSP0_CR1_LBM_Pos                                      0                                                         /*!< SSP0 CR1: LBM Position              */
#define SSP0_CR1_LBM_Msk                                      (0x01UL << SSP0_CR1_LBM_Pos)                              /*!< SSP0 CR1: LBM Mask                  */
#define SSP0_CR1_SSE_Pos                                      1                                                         /*!< SSP0 CR1: SSE Position              */
#define SSP0_CR1_SSE_Msk                                      (0x01UL << SSP0_CR1_SSE_Pos)                              /*!< SSP0 CR1: SSE Mask                  */
#define SSP0_CR1_MS_Pos                                       2                                                         /*!< SSP0 CR1: MS Position               */
#define SSP0_CR1_MS_Msk                                       (0x01UL << SSP0_CR1_MS_Pos)                               /*!< SSP0 CR1: MS Mask                   */
#define SSP0_CR1_SOD_Pos                                      3                                                         /*!< SSP0 CR1: SOD Position              */
#define SSP0_CR1_SOD_Msk                                      (0x01UL << SSP0_CR1_SOD_Pos)                              /*!< SSP0 CR1: SOD Mask                  */

// -----------------------------------------  SSP0_DR  --------------------------------------------
#define SSP0_DR_DATA_Pos                                      0                                                         /*!< SSP0 DR: DATA Position              */
#define SSP0_DR_DATA_Msk                                      (0x0000ffffUL << SSP0_DR_DATA_Pos)                        /*!< SSP0 DR: DATA Mask                  */

// -----------------------------------------  SSP0_SR  --------------------------------------------
#define SSP0_SR_TFE_Pos                                       0                                                         /*!< SSP0 SR: TFE Position               */
#define SSP0_SR_TFE_Msk                                       (0x01UL << SSP0_SR_TFE_Pos)                               /*!< SSP0 SR: TFE Mask                   */
#define SSP0_SR_TNF_Pos                                       1                                                         /*!< SSP0 SR: TNF Position               */
#define SSP0_SR_TNF_Msk                                       (0x01UL << SSP0_SR_TNF_Pos)                               /*!< SSP0 SR: TNF Mask                   */
#define SSP0_SR_RNE_Pos                                       2                                                         /*!< SSP0 SR: RNE Position               */
#define SSP0_SR_RNE_Msk                                       (0x01UL << SSP0_SR_RNE_Pos)                               /*!< SSP0 SR: RNE Mask                   */
#define SSP0_SR_RFF_Pos                                       3                                                         /*!< SSP0 SR: RFF Position               */
#define SSP0_SR_RFF_Msk                                       (0x01UL << SSP0_SR_RFF_Pos)                               /*!< SSP0 SR: RFF Mask                   */
#define SSP0_SR_BSY_Pos                                       4                                                         /*!< SSP0 SR: BSY Position               */
#define SSP0_SR_BSY_Msk                                       (0x01UL << SSP0_SR_BSY_Pos)                               /*!< SSP0 SR: BSY Mask                   */

// ----------------------------------------  SSP0_CPSR  -------------------------------------------
#define SSP0_CPSR_CPSDVSR_Pos                                 0                                                         /*!< SSP0 CPSR: CPSDVSR Position         */
#define SSP0_CPSR_CPSDVSR_Msk                                 (0x000000ffUL << SSP0_CPSR_CPSDVSR_Pos)                   /*!< SSP0 CPSR: CPSDVSR Mask             */

// ----------------------------------------  SSP0_IMSC  -------------------------------------------
#define SSP0_IMSC_RORIM_Pos                                   0                                                         /*!< SSP0 IMSC: RORIM Position           */
#define SSP0_IMSC_RORIM_Msk                                   (0x01UL << SSP0_IMSC_RORIM_Pos)                           /*!< SSP0 IMSC: RORIM Mask               */
#define SSP0_IMSC_RTIM_Pos                                    1                                                         /*!< SSP0 IMSC: RTIM Position            */
#define SSP0_IMSC_RTIM_Msk                                    (0x01UL << SSP0_IMSC_RTIM_Pos)                            /*!< SSP0 IMSC: RTIM Mask                */
#define SSP0_IMSC_RXIM_Pos                                    2                                                         /*!< SSP0 IMSC: RXIM Position            */
#define SSP0_IMSC_RXIM_Msk                                    (0x01UL << SSP0_IMSC_RXIM_Pos)                            /*!< SSP0 IMSC: RXIM Mask                */
#define SSP0_IMSC_TXIM_Pos                                    3                                                         /*!< SSP0 IMSC: TXIM Position            */
#define SSP0_IMSC_TXIM_Msk                                    (0x01UL << SSP0_IMSC_TXIM_Pos)                            /*!< SSP0 IMSC: TXIM Mask                */

// ----------------------------------------  SSP0_RIS  --------------------------------------------
#define SSP0_RIS_RORRIS_Pos                                   0                                                         /*!< SSP0 RIS: RORRIS Position           */
#define SSP0_RIS_RORRIS_Msk                                   (0x01UL << SSP0_RIS_RORRIS_Pos)                           /*!< SSP0 RIS: RORRIS Mask               */
#define SSP0_RIS_RTRIS_Pos                                    1                                                         /*!< SSP0 RIS: RTRIS Position            */
#define SSP0_RIS_RTRIS_Msk                                    (0x01UL << SSP0_RIS_RTRIS_Pos)                            /*!< SSP0 RIS: RTRIS Mask                */
#define SSP0_RIS_RXRIS_Pos                                    2                                                         /*!< SSP0 RIS: RXRIS Position            */
#define SSP0_RIS_RXRIS_Msk                                    (0x01UL << SSP0_RIS_RXRIS_Pos)                            /*!< SSP0 RIS: RXRIS Mask                */
#define SSP0_RIS_TXRIS_Pos                                    3                                                         /*!< SSP0 RIS: TXRIS Position            */
#define SSP0_RIS_TXRIS_Msk                                    (0x01UL << SSP0_RIS_TXRIS_Pos)                            /*!< SSP0 RIS: TXRIS Mask                */

// ----------------------------------------  SSP0_MIS  --------------------------------------------
#define SSP0_MIS_RORMIS_Pos                                   0                                                         /*!< SSP0 MIS: RORMIS Position           */
#define SSP0_MIS_RORMIS_Msk                                   (0x01UL << SSP0_MIS_RORMIS_Pos)                           /*!< SSP0 MIS: RORMIS Mask               */
#define SSP0_MIS_RTMIS_Pos                                    1                                                         /*!< SSP0 MIS: RTMIS Position            */
#define SSP0_MIS_RTMIS_Msk                                    (0x01UL << SSP0_MIS_RTMIS_Pos)                            /*!< SSP0 MIS: RTMIS Mask                */
#define SSP0_MIS_RXMIS_Pos                                    2                                                         /*!< SSP0 MIS: RXMIS Position            */
#define SSP0_MIS_RXMIS_Msk                                    (0x01UL << SSP0_MIS_RXMIS_Pos)                            /*!< SSP0 MIS: RXMIS Mask                */
#define SSP0_MIS_TXMIS_Pos                                    3                                                         /*!< SSP0 MIS: TXMIS Position            */
#define SSP0_MIS_TXMIS_Msk                                    (0x01UL << SSP0_MIS_TXMIS_Pos)                            /*!< SSP0 MIS: TXMIS Mask                */

// ----------------------------------------  SSP0_ICR  --------------------------------------------
#define SSP0_ICR_RORIC_Pos                                    0                                                         /*!< SSP0 ICR: RORIC Position            */
#define SSP0_ICR_RORIC_Msk                                    (0x01UL << SSP0_ICR_RORIC_Pos)                            /*!< SSP0 ICR: RORIC Mask                */
#define SSP0_ICR_RTIC_Pos                                     1                                                         /*!< SSP0 ICR: RTIC Position             */
#define SSP0_ICR_RTIC_Msk                                     (0x01UL << SSP0_ICR_RTIC_Pos)                             /*!< SSP0 ICR: RTIC Mask                 */

// ---------------------------------------  SSP0_DMACR  -------------------------------------------
#define SSP0_DMACR_RXDMAE_Pos                                 0                                                         /*!< SSP0 DMACR: RXDMAE Position         */
#define SSP0_DMACR_RXDMAE_Msk                                 (0x01UL << SSP0_DMACR_RXDMAE_Pos)                         /*!< SSP0 DMACR: RXDMAE Mask             */
#define SSP0_DMACR_TXDMAE_Pos                                 1                                                         /*!< SSP0 DMACR: TXDMAE Position         */
#define SSP0_DMACR_TXDMAE_Msk                                 (0x01UL << SSP0_DMACR_TXDMAE_Pos)                         /*!< SSP0 DMACR: TXDMAE Mask             */


// ------------------------------------------------------------------------------------------------
// -----                                 SSP1 Position & Mask                                 -----
// ------------------------------------------------------------------------------------------------


// ----------------------------------------  SSP1_CR0  --------------------------------------------
#define SSP1_CR0_DSS_Pos                                      0                                                         /*!< SSP1 CR0: DSS Position              */
#define SSP1_CR0_DSS_Msk                                      (0x0fUL << SSP1_CR0_DSS_Pos)                              /*!< SSP1 CR0: DSS Mask                  */
#define SSP1_CR0_FRF_Pos                                      4                                                         /*!< SSP1 CR0: FRF Position              */
#define SSP1_CR0_FRF_Msk                                      (0x03UL << SSP1_CR0_FRF_Pos)                              /*!< SSP1 CR0: FRF Mask                  */
#define SSP1_CR0_CPOL_Pos                                     6                                                         /*!< SSP1 CR0: CPOL Position             */
#define SSP1_CR0_CPOL_Msk                                     (0x01UL << SSP1_CR0_CPOL_Pos)                             /*!< SSP1 CR0: CPOL Mask                 */
#define SSP1_CR0_CPHA_Pos                                     7                                                         /*!< SSP1 CR0: CPHA Position             */
#define SSP1_CR0_CPHA_Msk                                     (0x01UL << SSP1_CR0_CPHA_Pos)                             /*!< SSP1 CR0: CPHA Mask                 */
#define SSP1_CR0_SCR_Pos                                      8                                                         /*!< SSP1 CR0: SCR Position              */
#define SSP1_CR0_SCR_Msk                                      (0x000000ffUL << SSP1_CR0_SCR_Pos)                        /*!< SSP1 CR0: SCR Mask                  */

// ----------------------------------------  SSP1_CR1  --------------------------------------------
#define SSP1_CR1_LBM_Pos                                      0                                                         /*!< SSP1 CR1: LBM Position              */
#define SSP1_CR1_LBM_Msk                                      (0x01UL << SSP1_CR1_LBM_Pos)                              /*!< SSP1 CR1: LBM Mask                  */
#define SSP1_CR1_SSE_Pos                                      1                                                         /*!< SSP1 CR1: SSE Position              */
#define SSP1_CR1_SSE_Msk                                      (0x01UL << SSP1_CR1_SSE_Pos)                              /*!< SSP1 CR1: SSE Mask                  */
#define SSP1_CR1_MS_Pos                                       2                                                         /*!< SSP1 CR1: MS Position               */
#define SSP1_CR1_MS_Msk                                       (0x01UL << SSP1_CR1_MS_Pos)                               /*!< SSP1 CR1: MS Mask                   */
#define SSP1_CR1_SOD_Pos                                      3                                                         /*!< SSP1 CR1: SOD Position              */
#define SSP1_CR1_SOD_Msk                                      (0x01UL << SSP1_CR1_SOD_Pos)                              /*!< SSP1 CR1: SOD Mask                  */

// -----------------------------------------  SSP1_DR  --------------------------------------------
#define SSP1_DR_DATA_Pos                                      0                                                         /*!< SSP1 DR: DATA Position              */
#define SSP1_DR_DATA_Msk                                      (0x0000ffffUL << SSP1_DR_DATA_Pos)                        /*!< SSP1 DR: DATA Mask                  */

// -----------------------------------------  SSP1_SR  --------------------------------------------
#define SSP1_SR_TFE_Pos                                       0                                                         /*!< SSP1 SR: TFE Position               */
#define SSP1_SR_TFE_Msk                                       (0x01UL << SSP1_SR_TFE_Pos)                               /*!< SSP1 SR: TFE Mask                   */
#define SSP1_SR_TNF_Pos                                       1                                                         /*!< SSP1 SR: TNF Position               */
#define SSP1_SR_TNF_Msk                                       (0x01UL << SSP1_SR_TNF_Pos)                               /*!< SSP1 SR: TNF Mask                   */
#define SSP1_SR_RNE_Pos                                       2                                                         /*!< SSP1 SR: RNE Position               */
#define SSP1_SR_RNE_Msk                                       (0x01UL << SSP1_SR_RNE_Pos)                               /*!< SSP1 SR: RNE Mask                   */
#define SSP1_SR_RFF_Pos                                       3                                                         /*!< SSP1 SR: RFF Position               */
#define SSP1_SR_RFF_Msk                                       (0x01UL << SSP1_SR_RFF_Pos)                               /*!< SSP1 SR: RFF Mask                   */
#define SSP1_SR_BSY_Pos                                       4                                                         /*!< SSP1 SR: BSY Position               */
#define SSP1_SR_BSY_Msk                                       (0x01UL << SSP1_SR_BSY_Pos)                               /*!< SSP1 SR: BSY Mask                   */

// ----------------------------------------  SSP1_CPSR  -------------------------------------------
#define SSP1_CPSR_CPSDVSR_Pos                                 0                                                         /*!< SSP1 CPSR: CPSDVSR Position         */
#define SSP1_CPSR_CPSDVSR_Msk                                 (0x000000ffUL << SSP1_CPSR_CPSDVSR_Pos)                   /*!< SSP1 CPSR: CPSDVSR Mask             */

// ----------------------------------------  SSP1_IMSC  -------------------------------------------
#define SSP1_IMSC_RORIM_Pos                                   0                                                         /*!< SSP1 IMSC: RORIM Position           */
#define SSP1_IMSC_RORIM_Msk                                   (0x01UL << SSP1_IMSC_RORIM_Pos)                           /*!< SSP1 IMSC: RORIM Mask               */
#define SSP1_IMSC_RTIM_Pos                                    1                                                         /*!< SSP1 IMSC: RTIM Position            */
#define SSP1_IMSC_RTIM_Msk                                    (0x01UL << SSP1_IMSC_RTIM_Pos)                            /*!< SSP1 IMSC: RTIM Mask                */
#define SSP1_IMSC_RXIM_Pos                                    2                                                         /*!< SSP1 IMSC: RXIM Position            */
#define SSP1_IMSC_RXIM_Msk                                    (0x01UL << SSP1_IMSC_RXIM_Pos)                            /*!< SSP1 IMSC: RXIM Mask                */
#define SSP1_IMSC_TXIM_Pos                                    3                                                         /*!< SSP1 IMSC: TXIM Position            */
#define SSP1_IMSC_TXIM_Msk                                    (0x01UL << SSP1_IMSC_TXIM_Pos)                            /*!< SSP1 IMSC: TXIM Mask                */

// ----------------------------------------  SSP1_RIS  --------------------------------------------
#define SSP1_RIS_RORRIS_Pos                                   0                                                         /*!< SSP1 RIS: RORRIS Position           */
#define SSP1_RIS_RORRIS_Msk                                   (0x01UL << SSP1_RIS_RORRIS_Pos)                           /*!< SSP1 RIS: RORRIS Mask               */
#define SSP1_RIS_RTRIS_Pos                                    1                                                         /*!< SSP1 RIS: RTRIS Position            */
#define SSP1_RIS_RTRIS_Msk                                    (0x01UL << SSP1_RIS_RTRIS_Pos)                            /*!< SSP1 RIS: RTRIS Mask                */
#define SSP1_RIS_RXRIS_Pos                                    2                                                         /*!< SSP1 RIS: RXRIS Position            */
#define SSP1_RIS_RXRIS_Msk                                    (0x01UL << SSP1_RIS_RXRIS_Pos)                            /*!< SSP1 RIS: RXRIS Mask                */
#define SSP1_RIS_TXRIS_Pos                                    3                                                         /*!< SSP1 RIS: TXRIS Position            */
#define SSP1_RIS_TXRIS_Msk                                    (0x01UL << SSP1_RIS_TXRIS_Pos)                            /*!< SSP1 RIS: TXRIS Mask                */

// ----------------------------------------  SSP1_MIS  --------------------------------------------
#define SSP1_MIS_RORMIS_Pos                                   0                                                         /*!< SSP1 MIS: RORMIS Position           */
#define SSP1_MIS_RORMIS_Msk                                   (0x01UL << SSP1_MIS_RORMIS_Pos)                           /*!< SSP1 MIS: RORMIS Mask               */
#define SSP1_MIS_RTMIS_Pos                                    1                                                         /*!< SSP1 MIS: RTMIS Position            */
#define SSP1_MIS_RTMIS_Msk                                    (0x01UL << SSP1_MIS_RTMIS_Pos)                            /*!< SSP1 MIS: RTMIS Mask                */
#define SSP1_MIS_RXMIS_Pos                                    2                                                         /*!< SSP1 MIS: RXMIS Position            */
#define SSP1_MIS_RXMIS_Msk                                    (0x01UL << SSP1_MIS_RXMIS_Pos)                            /*!< SSP1 MIS: RXMIS Mask                */
#define SSP1_MIS_TXMIS_Pos                                    3                                                         /*!< SSP1 MIS: TXMIS Position            */
#define SSP1_MIS_TXMIS_Msk                                    (0x01UL << SSP1_MIS_TXMIS_Pos)                            /*!< SSP1 MIS: TXMIS Mask                */

// ----------------------------------------  SSP1_ICR  --------------------------------------------
#define SSP1_ICR_RORIC_Pos                                    0                                                         /*!< SSP1 ICR: RORIC Position            */
#define SSP1_ICR_RORIC_Msk                                    (0x01UL << SSP1_ICR_RORIC_Pos)                            /*!< SSP1 ICR: RORIC Mask                */
#define SSP1_ICR_RTIC_Pos                                     1                                                         /*!< SSP1 ICR: RTIC Position             */
#define SSP1_ICR_RTIC_Msk                                     (0x01UL << SSP1_ICR_RTIC_Pos)                             /*!< SSP1 ICR: RTIC Mask                 */

// ---------------------------------------  SSP1_DMACR  -------------------------------------------
#define SSP1_DMACR_RXDMAE_Pos                                 0                                                         /*!< SSP1 DMACR: RXDMAE Position         */
#define SSP1_DMACR_RXDMAE_Msk                                 (0x01UL << SSP1_DMACR_RXDMAE_Pos)                         /*!< SSP1 DMACR: RXDMAE Mask             */
#define SSP1_DMACR_TXDMAE_Pos                                 1                                                         /*!< SSP1 DMACR: TXDMAE Position         */
#define SSP1_DMACR_TXDMAE_Msk                                 (0x01UL << SSP1_DMACR_TXDMAE_Pos)                         /*!< SSP1 DMACR: TXDMAE Mask             */


// ------------------------------------------------------------------------------------------------
// -----                                TIMER0 Position & Mask                                -----
// ------------------------------------------------------------------------------------------------


// ----------------------------------------  TIMER0_IR  -------------------------------------------
#define TIMER0_IR_MR0INT_Pos                                  0                                                         /*!< TIMER0 IR: MR0INT Position          */
#define TIMER0_IR_MR0INT_Msk                                  (0x01UL << TIMER0_IR_MR0INT_Pos)                          /*!< TIMER0 IR: MR0INT Mask              */
#define TIMER0_IR_MR1INT_Pos                                  1                                                         /*!< TIMER0 IR: MR1INT Position          */
#define TIMER0_IR_MR1INT_Msk                                  (0x01UL << TIMER0_IR_MR1INT_Pos)                          /*!< TIMER0 IR: MR1INT Mask              */
#define TIMER0_IR_MR2INT_Pos                                  2                                                         /*!< TIMER0 IR: MR2INT Position          */
#define TIMER0_IR_MR2INT_Msk                                  (0x01UL << TIMER0_IR_MR2INT_Pos)                          /*!< TIMER0 IR: MR2INT Mask              */
#define TIMER0_IR_MR3INT_Pos                                  3                                                         /*!< TIMER0 IR: MR3INT Position          */
#define TIMER0_IR_MR3INT_Msk                                  (0x01UL << TIMER0_IR_MR3INT_Pos)                          /*!< TIMER0 IR: MR3INT Mask              */
#define TIMER0_IR_CR0INT_Pos                                  4                                                         /*!< TIMER0 IR: CR0INT Position          */
#define TIMER0_IR_CR0INT_Msk                                  (0x01UL << TIMER0_IR_CR0INT_Pos)                          /*!< TIMER0 IR: CR0INT Mask              */
#define TIMER0_IR_CR1INT_Pos                                  5                                                         /*!< TIMER0 IR: CR1INT Position          */
#define TIMER0_IR_CR1INT_Msk                                  (0x01UL << TIMER0_IR_CR1INT_Pos)                          /*!< TIMER0 IR: CR1INT Mask              */
#define TIMER0_IR_CR2INT_Pos                                  6                                                         /*!< TIMER0 IR: CR2INT Position          */
#define TIMER0_IR_CR2INT_Msk                                  (0x01UL << TIMER0_IR_CR2INT_Pos)                          /*!< TIMER0 IR: CR2INT Mask              */
#define TIMER0_IR_CR3INT_Pos                                  7                                                         /*!< TIMER0 IR: CR3INT Position          */
#define TIMER0_IR_CR3INT_Msk                                  (0x01UL << TIMER0_IR_CR3INT_Pos)                          /*!< TIMER0 IR: CR3INT Mask              */

// ---------------------------------------  TIMER0_TCR  -------------------------------------------
#define TIMER0_TCR_CEN_Pos                                    0                                                         /*!< TIMER0 TCR: CEN Position            */
#define TIMER0_TCR_CEN_Msk                                    (0x01UL << TIMER0_TCR_CEN_Pos)                            /*!< TIMER0 TCR: CEN Mask                */
#define TIMER0_TCR_CRST_Pos                                   1                                                         /*!< TIMER0 TCR: CRST Position           */
#define TIMER0_TCR_CRST_Msk                                   (0x01UL << TIMER0_TCR_CRST_Pos)                           /*!< TIMER0 TCR: CRST Mask               */

// ----------------------------------------  TIMER0_TC  -------------------------------------------
#define TIMER0_TC_TC_Pos                                      0                                                         /*!< TIMER0 TC: TC Position              */
#define TIMER0_TC_TC_Msk                                      (0xffffffffUL << TIMER0_TC_TC_Pos)                        /*!< TIMER0 TC: TC Mask                  */

// ----------------------------------------  TIMER0_PR  -------------------------------------------
#define TIMER0_PR_PM_Pos                                      0                                                         /*!< TIMER0 PR: PM Position              */
#define TIMER0_PR_PM_Msk                                      (0xffffffffUL << TIMER0_PR_PM_Pos)                        /*!< TIMER0 PR: PM Mask                  */

// ----------------------------------------  TIMER0_PC  -------------------------------------------
#define TIMER0_PC_PC_Pos                                      0                                                         /*!< TIMER0 PC: PC Position              */
#define TIMER0_PC_PC_Msk                                      (0xffffffffUL << TIMER0_PC_PC_Pos)                        /*!< TIMER0 PC: PC Mask                  */

// ---------------------------------------  TIMER0_MCR  -------------------------------------------
#define TIMER0_MCR_MR0I_Pos                                   0                                                         /*!< TIMER0 MCR: MR0I Position           */
#define TIMER0_MCR_MR0I_Msk                                   (0x01UL << TIMER0_MCR_MR0I_Pos)                           /*!< TIMER0 MCR: MR0I Mask               */
#define TIMER0_MCR_MR0R_Pos                                   1                                                         /*!< TIMER0 MCR: MR0R Position           */
#define TIMER0_MCR_MR0R_Msk                                   (0x01UL << TIMER0_MCR_MR0R_Pos)                           /*!< TIMER0 MCR: MR0R Mask               */
#define TIMER0_MCR_MR0S_Pos                                   2                                                         /*!< TIMER0 MCR: MR0S Position           */
#define TIMER0_MCR_MR0S_Msk                                   (0x01UL << TIMER0_MCR_MR0S_Pos)                           /*!< TIMER0 MCR: MR0S Mask               */
#define TIMER0_MCR_MR1I_Pos                                   3                                                         /*!< TIMER0 MCR: MR1I Position           */
#define TIMER0_MCR_MR1I_Msk                                   (0x01UL << TIMER0_MCR_MR1I_Pos)                           /*!< TIMER0 MCR: MR1I Mask               */
#define TIMER0_MCR_MR1R_Pos                                   4                                                         /*!< TIMER0 MCR: MR1R Position           */
#define TIMER0_MCR_MR1R_Msk                                   (0x01UL << TIMER0_MCR_MR1R_Pos)                           /*!< TIMER0 MCR: MR1R Mask               */
#define TIMER0_MCR_MR1S_Pos                                   5                                                         /*!< TIMER0 MCR: MR1S Position           */
#define TIMER0_MCR_MR1S_Msk                                   (0x01UL << TIMER0_MCR_MR1S_Pos)                           /*!< TIMER0 MCR: MR1S Mask               */
#define TIMER0_MCR_MR2I_Pos                                   6                                                         /*!< TIMER0 MCR: MR2I Position           */
#define TIMER0_MCR_MR2I_Msk                                   (0x01UL << TIMER0_MCR_MR2I_Pos)                           /*!< TIMER0 MCR: MR2I Mask               */
#define TIMER0_MCR_MR2R_Pos                                   7                                                         /*!< TIMER0 MCR: MR2R Position           */
#define TIMER0_MCR_MR2R_Msk                                   (0x01UL << TIMER0_MCR_MR2R_Pos)                           /*!< TIMER0 MCR: MR2R Mask               */
#define TIMER0_MCR_MR2S_Pos                                   8                                                         /*!< TIMER0 MCR: MR2S Position           */
#define TIMER0_MCR_MR2S_Msk                                   (0x01UL << TIMER0_MCR_MR2S_Pos)                           /*!< TIMER0 MCR: MR2S Mask               */
#define TIMER0_MCR_MR3I_Pos                                   9                                                         /*!< TIMER0 MCR: MR3I Position           */
#define TIMER0_MCR_MR3I_Msk                                   (0x01UL << TIMER0_MCR_MR3I_Pos)                           /*!< TIMER0 MCR: MR3I Mask               */
#define TIMER0_MCR_MR3R_Pos                                   10                                                        /*!< TIMER0 MCR: MR3R Position           */
#define TIMER0_MCR_MR3R_Msk                                   (0x01UL << TIMER0_MCR_MR3R_Pos)                           /*!< TIMER0 MCR: MR3R Mask               */
#define TIMER0_MCR_MR3S_Pos                                   11                                                        /*!< TIMER0 MCR: MR3S Position           */
#define TIMER0_MCR_MR3S_Msk                                   (0x01UL << TIMER0_MCR_MR3S_Pos)                           /*!< TIMER0 MCR: MR3S Mask               */

// ---------------------------------------  TIMER0_MR0  -------------------------------------------
#define TIMER0_MR0_MATCH_Pos                                  0                                                         /*!< TIMER0 MR0: MATCH Position          */
#define TIMER0_MR0_MATCH_Msk                                  (0xffffffffUL << TIMER0_MR0_MATCH_Pos)                    /*!< TIMER0 MR0: MATCH Mask              */

// ---------------------------------------  TIMER0_MR1  -------------------------------------------
#define TIMER0_MR1_MATCH_Pos                                  0                                                         /*!< TIMER0 MR1: MATCH Position          */
#define TIMER0_MR1_MATCH_Msk                                  (0xffffffffUL << TIMER0_MR1_MATCH_Pos)                    /*!< TIMER0 MR1: MATCH Mask              */

// ---------------------------------------  TIMER0_MR2  -------------------------------------------
#define TIMER0_MR2_MATCH_Pos                                  0                                                         /*!< TIMER0 MR2: MATCH Position          */
#define TIMER0_MR2_MATCH_Msk                                  (0xffffffffUL << TIMER0_MR2_MATCH_Pos)                    /*!< TIMER0 MR2: MATCH Mask              */

// ---------------------------------------  TIMER0_MR3  -------------------------------------------
#define TIMER0_MR3_MATCH_Pos                                  0                                                         /*!< TIMER0 MR3: MATCH Position          */
#define TIMER0_MR3_MATCH_Msk                                  (0xffffffffUL << TIMER0_MR3_MATCH_Pos)                    /*!< TIMER0 MR3: MATCH Mask              */

// ---------------------------------------  TIMER0_CCR  -------------------------------------------
#define TIMER0_CCR_CAP0RE_Pos                                 0                                                         /*!< TIMER0 CCR: CAP0RE Position         */
#define TIMER0_CCR_CAP0RE_Msk                                 (0x01UL << TIMER0_CCR_CAP0RE_Pos)                         /*!< TIMER0 CCR: CAP0RE Mask             */
#define TIMER0_CCR_CAP0FE_Pos                                 1                                                         /*!< TIMER0 CCR: CAP0FE Position         */
#define TIMER0_CCR_CAP0FE_Msk                                 (0x01UL << TIMER0_CCR_CAP0FE_Pos)                         /*!< TIMER0 CCR: CAP0FE Mask             */
#define TIMER0_CCR_CAP0I_Pos                                  2                                                         /*!< TIMER0 CCR: CAP0I Position          */
#define TIMER0_CCR_CAP0I_Msk                                  (0x01UL << TIMER0_CCR_CAP0I_Pos)                          /*!< TIMER0 CCR: CAP0I Mask              */
#define TIMER0_CCR_CAP1RE_Pos                                 3                                                         /*!< TIMER0 CCR: CAP1RE Position         */
#define TIMER0_CCR_CAP1RE_Msk                                 (0x01UL << TIMER0_CCR_CAP1RE_Pos)                         /*!< TIMER0 CCR: CAP1RE Mask             */
#define TIMER0_CCR_CAP1FE_Pos                                 4                                                         /*!< TIMER0 CCR: CAP1FE Position         */
#define TIMER0_CCR_CAP1FE_Msk                                 (0x01UL << TIMER0_CCR_CAP1FE_Pos)                         /*!< TIMER0 CCR: CAP1FE Mask             */
#define TIMER0_CCR_CAP1I_Pos                                  5                                                         /*!< TIMER0 CCR: CAP1I Position          */
#define TIMER0_CCR_CAP1I_Msk                                  (0x01UL << TIMER0_CCR_CAP1I_Pos)                          /*!< TIMER0 CCR: CAP1I Mask              */
#define TIMER0_CCR_CAP2RE_Pos                                 6                                                         /*!< TIMER0 CCR: CAP2RE Position         */
#define TIMER0_CCR_CAP2RE_Msk                                 (0x01UL << TIMER0_CCR_CAP2RE_Pos)                         /*!< TIMER0 CCR: CAP2RE Mask             */
#define TIMER0_CCR_CAP2FE_Pos                                 7                                                         /*!< TIMER0 CCR: CAP2FE Position         */
#define TIMER0_CCR_CAP2FE_Msk                                 (0x01UL << TIMER0_CCR_CAP2FE_Pos)                         /*!< TIMER0 CCR: CAP2FE Mask             */
#define TIMER0_CCR_CAP2I_Pos                                  8                                                         /*!< TIMER0 CCR: CAP2I Position          */
#define TIMER0_CCR_CAP2I_Msk                                  (0x01UL << TIMER0_CCR_CAP2I_Pos)                          /*!< TIMER0 CCR: CAP2I Mask              */
#define TIMER0_CCR_CAP3RE_Pos                                 9                                                         /*!< TIMER0 CCR: CAP3RE Position         */
#define TIMER0_CCR_CAP3RE_Msk                                 (0x01UL << TIMER0_CCR_CAP3RE_Pos)                         /*!< TIMER0 CCR: CAP3RE Mask             */
#define TIMER0_CCR_CAP3FE_Pos                                 10                                                        /*!< TIMER0 CCR: CAP3FE Position         */
#define TIMER0_CCR_CAP3FE_Msk                                 (0x01UL << TIMER0_CCR_CAP3FE_Pos)                         /*!< TIMER0 CCR: CAP3FE Mask             */
#define TIMER0_CCR_CAP3I_Pos                                  11                                                        /*!< TIMER0 CCR: CAP3I Position          */
#define TIMER0_CCR_CAP3I_Msk                                  (0x01UL << TIMER0_CCR_CAP3I_Pos)                          /*!< TIMER0 CCR: CAP3I Mask              */

// ---------------------------------------  TIMER0_CR0  -------------------------------------------
#define TIMER0_CR0_CAP_Pos                                    0                                                         /*!< TIMER0 CR0: CAP Position            */
#define TIMER0_CR0_CAP_Msk                                    (0xffffffffUL << TIMER0_CR0_CAP_Pos)                      /*!< TIMER0 CR0: CAP Mask                */

// ---------------------------------------  TIMER0_CR1  -------------------------------------------
#define TIMER0_CR1_CAP_Pos                                    0                                                         /*!< TIMER0 CR1: CAP Position            */
#define TIMER0_CR1_CAP_Msk                                    (0xffffffffUL << TIMER0_CR1_CAP_Pos)                      /*!< TIMER0 CR1: CAP Mask                */

// ---------------------------------------  TIMER0_CR2  -------------------------------------------
#define TIMER0_CR2_CAP_Pos                                    0                                                         /*!< TIMER0 CR2: CAP Position            */
#define TIMER0_CR2_CAP_Msk                                    (0xffffffffUL << TIMER0_CR2_CAP_Pos)                      /*!< TIMER0 CR2: CAP Mask                */

// ---------------------------------------  TIMER0_CR3  -------------------------------------------
#define TIMER0_CR3_CAP_Pos                                    0                                                         /*!< TIMER0 CR3: CAP Position            */
#define TIMER0_CR3_CAP_Msk                                    (0xffffffffUL << TIMER0_CR3_CAP_Pos)                      /*!< TIMER0 CR3: CAP Mask                */

// ---------------------------------------  TIMER0_EMR  -------------------------------------------
#define TIMER0_EMR_EM0_Pos                                    0                                                         /*!< TIMER0 EMR: EM0 Position            */
#define TIMER0_EMR_EM0_Msk                                    (0x01UL << TIMER0_EMR_EM0_Pos)                            /*!< TIMER0 EMR: EM0 Mask                */
#define TIMER0_EMR_EM1_Pos                                    1                                                         /*!< TIMER0 EMR: EM1 Position            */
#define TIMER0_EMR_EM1_Msk                                    (0x01UL << TIMER0_EMR_EM1_Pos)                            /*!< TIMER0 EMR: EM1 Mask                */
#define TIMER0_EMR_EM2_Pos                                    2                                                         /*!< TIMER0 EMR: EM2 Position            */
#define TIMER0_EMR_EM2_Msk                                    (0x01UL << TIMER0_EMR_EM2_Pos)                            /*!< TIMER0 EMR: EM2 Mask                */
#define TIMER0_EMR_EM3_Pos                                    3                                                         /*!< TIMER0 EMR: EM3 Position            */
#define TIMER0_EMR_EM3_Msk                                    (0x01UL << TIMER0_EMR_EM3_Pos)                            /*!< TIMER0 EMR: EM3 Mask                */
#define TIMER0_EMR_EMC0_Pos                                   4                                                         /*!< TIMER0 EMR: EMC0 Position           */
#define TIMER0_EMR_EMC0_Msk                                   (0x03UL << TIMER0_EMR_EMC0_Pos)                           /*!< TIMER0 EMR: EMC0 Mask               */
#define TIMER0_EMR_EMC1_Pos                                   6                                                         /*!< TIMER0 EMR: EMC1 Position           */
#define TIMER0_EMR_EMC1_Msk                                   (0x03UL << TIMER0_EMR_EMC1_Pos)                           /*!< TIMER0 EMR: EMC1 Mask               */
#define TIMER0_EMR_EMC2_Pos                                   8                                                         /*!< TIMER0 EMR: EMC2 Position           */
#define TIMER0_EMR_EMC2_Msk                                   (0x03UL << TIMER0_EMR_EMC2_Pos)                           /*!< TIMER0 EMR: EMC2 Mask               */
#define TIMER0_EMR_EMC3_Pos                                   10                                                        /*!< TIMER0 EMR: EMC3 Position           */
#define TIMER0_EMR_EMC3_Msk                                   (0x03UL << TIMER0_EMR_EMC3_Pos)                           /*!< TIMER0 EMR: EMC3 Mask               */

// ---------------------------------------  TIMER0_CTCR  ------------------------------------------
#define TIMER0_CTCR_CTMODE_Pos                                0                                                         /*!< TIMER0 CTCR: CTMODE Position        */
#define TIMER0_CTCR_CTMODE_Msk                                (0x03UL << TIMER0_CTCR_CTMODE_Pos)                        /*!< TIMER0 CTCR: CTMODE Mask            */
#define TIMER0_CTCR_CINSEL_Pos                                2                                                         /*!< TIMER0 CTCR: CINSEL Position        */
#define TIMER0_CTCR_CINSEL_Msk                                (0x03UL << TIMER0_CTCR_CINSEL_Pos)                        /*!< TIMER0 CTCR: CINSEL Mask            */


// ------------------------------------------------------------------------------------------------
// -----                                TIMER1 Position & Mask                                -----
// ------------------------------------------------------------------------------------------------


// ----------------------------------------  TIMER1_IR  -------------------------------------------
#define TIMER1_IR_MR0INT_Pos                                  0                                                         /*!< TIMER1 IR: MR0INT Position          */
#define TIMER1_IR_MR0INT_Msk                                  (0x01UL << TIMER1_IR_MR0INT_Pos)                          /*!< TIMER1 IR: MR0INT Mask              */
#define TIMER1_IR_MR1INT_Pos                                  1                                                         /*!< TIMER1 IR: MR1INT Position          */
#define TIMER1_IR_MR1INT_Msk                                  (0x01UL << TIMER1_IR_MR1INT_Pos)                          /*!< TIMER1 IR: MR1INT Mask              */
#define TIMER1_IR_MR2INT_Pos                                  2                                                         /*!< TIMER1 IR: MR2INT Position          */
#define TIMER1_IR_MR2INT_Msk                                  (0x01UL << TIMER1_IR_MR2INT_Pos)                          /*!< TIMER1 IR: MR2INT Mask              */
#define TIMER1_IR_MR3INT_Pos                                  3                                                         /*!< TIMER1 IR: MR3INT Position          */
#define TIMER1_IR_MR3INT_Msk                                  (0x01UL << TIMER1_IR_MR3INT_Pos)                          /*!< TIMER1 IR: MR3INT Mask              */
#define TIMER1_IR_CR0INT_Pos                                  4                                                         /*!< TIMER1 IR: CR0INT Position          */
#define TIMER1_IR_CR0INT_Msk                                  (0x01UL << TIMER1_IR_CR0INT_Pos)                          /*!< TIMER1 IR: CR0INT Mask              */
#define TIMER1_IR_CR1INT_Pos                                  5                                                         /*!< TIMER1 IR: CR1INT Position          */
#define TIMER1_IR_CR1INT_Msk                                  (0x01UL << TIMER1_IR_CR1INT_Pos)                          /*!< TIMER1 IR: CR1INT Mask              */
#define TIMER1_IR_CR2INT_Pos                                  6                                                         /*!< TIMER1 IR: CR2INT Position          */
#define TIMER1_IR_CR2INT_Msk                                  (0x01UL << TIMER1_IR_CR2INT_Pos)                          /*!< TIMER1 IR: CR2INT Mask              */
#define TIMER1_IR_CR3INT_Pos                                  7                                                         /*!< TIMER1 IR: CR3INT Position          */
#define TIMER1_IR_CR3INT_Msk                                  (0x01UL << TIMER1_IR_CR3INT_Pos)                          /*!< TIMER1 IR: CR3INT Mask              */

// ---------------------------------------  TIMER1_TCR  -------------------------------------------
#define TIMER1_TCR_CEN_Pos                                    0                                                         /*!< TIMER1 TCR: CEN Position            */
#define TIMER1_TCR_CEN_Msk                                    (0x01UL << TIMER1_TCR_CEN_Pos)                            /*!< TIMER1 TCR: CEN Mask                */
#define TIMER1_TCR_CRST_Pos                                   1                                                         /*!< TIMER1 TCR: CRST Position           */
#define TIMER1_TCR_CRST_Msk                                   (0x01UL << TIMER1_TCR_CRST_Pos)                           /*!< TIMER1 TCR: CRST Mask               */

// ----------------------------------------  TIMER1_TC  -------------------------------------------
#define TIMER1_TC_TC_Pos                                      0                                                         /*!< TIMER1 TC: TC Position              */
#define TIMER1_TC_TC_Msk                                      (0xffffffffUL << TIMER1_TC_TC_Pos)                        /*!< TIMER1 TC: TC Mask                  */

// ----------------------------------------  TIMER1_PR  -------------------------------------------
#define TIMER1_PR_PM_Pos                                      0                                                         /*!< TIMER1 PR: PM Position              */
#define TIMER1_PR_PM_Msk                                      (0xffffffffUL << TIMER1_PR_PM_Pos)                        /*!< TIMER1 PR: PM Mask                  */

// ----------------------------------------  TIMER1_PC  -------------------------------------------
#define TIMER1_PC_PC_Pos                                      0                                                         /*!< TIMER1 PC: PC Position              */
#define TIMER1_PC_PC_Msk                                      (0xffffffffUL << TIMER1_PC_PC_Pos)                        /*!< TIMER1 PC: PC Mask                  */

// ---------------------------------------  TIMER1_MCR  -------------------------------------------
#define TIMER1_MCR_MR0I_Pos                                   0                                                         /*!< TIMER1 MCR: MR0I Position           */
#define TIMER1_MCR_MR0I_Msk                                   (0x01UL << TIMER1_MCR_MR0I_Pos)                           /*!< TIMER1 MCR: MR0I Mask               */
#define TIMER1_MCR_MR0R_Pos                                   1                                                         /*!< TIMER1 MCR: MR0R Position           */
#define TIMER1_MCR_MR0R_Msk                                   (0x01UL << TIMER1_MCR_MR0R_Pos)                           /*!< TIMER1 MCR: MR0R Mask               */
#define TIMER1_MCR_MR0S_Pos                                   2                                                         /*!< TIMER1 MCR: MR0S Position           */
#define TIMER1_MCR_MR0S_Msk                                   (0x01UL << TIMER1_MCR_MR0S_Pos)                           /*!< TIMER1 MCR: MR0S Mask               */
#define TIMER1_MCR_MR1I_Pos                                   3                                                         /*!< TIMER1 MCR: MR1I Position           */
#define TIMER1_MCR_MR1I_Msk                                   (0x01UL << TIMER1_MCR_MR1I_Pos)                           /*!< TIMER1 MCR: MR1I Mask               */
#define TIMER1_MCR_MR1R_Pos                                   4                                                         /*!< TIMER1 MCR: MR1R Position           */
#define TIMER1_MCR_MR1R_Msk                                   (0x01UL << TIMER1_MCR_MR1R_Pos)                           /*!< TIMER1 MCR: MR1R Mask               */
#define TIMER1_MCR_MR1S_Pos                                   5                                                         /*!< TIMER1 MCR: MR1S Position           */
#define TIMER1_MCR_MR1S_Msk                                   (0x01UL << TIMER1_MCR_MR1S_Pos)                           /*!< TIMER1 MCR: MR1S Mask               */
#define TIMER1_MCR_MR2I_Pos                                   6                                                         /*!< TIMER1 MCR: MR2I Position           */
#define TIMER1_MCR_MR2I_Msk                                   (0x01UL << TIMER1_MCR_MR2I_Pos)                           /*!< TIMER1 MCR: MR2I Mask               */
#define TIMER1_MCR_MR2R_Pos                                   7                                                         /*!< TIMER1 MCR: MR2R Position           */
#define TIMER1_MCR_MR2R_Msk                                   (0x01UL << TIMER1_MCR_MR2R_Pos)                           /*!< TIMER1 MCR: MR2R Mask               */
#define TIMER1_MCR_MR2S_Pos                                   8                                                         /*!< TIMER1 MCR: MR2S Position           */
#define TIMER1_MCR_MR2S_Msk                                   (0x01UL << TIMER1_MCR_MR2S_Pos)                           /*!< TIMER1 MCR: MR2S Mask               */
#define TIMER1_MCR_MR3I_Pos                                   9                                                         /*!< TIMER1 MCR: MR3I Position           */
#define TIMER1_MCR_MR3I_Msk                                   (0x01UL << TIMER1_MCR_MR3I_Pos)                           /*!< TIMER1 MCR: MR3I Mask               */
#define TIMER1_MCR_MR3R_Pos                                   10                                                        /*!< TIMER1 MCR: MR3R Position           */
#define TIMER1_MCR_MR3R_Msk                                   (0x01UL << TIMER1_MCR_MR3R_Pos)                           /*!< TIMER1 MCR: MR3R Mask               */
#define TIMER1_MCR_MR3S_Pos                                   11                                                        /*!< TIMER1 MCR: MR3S Position           */
#define TIMER1_MCR_MR3S_Msk                                   (0x01UL << TIMER1_MCR_MR3S_Pos)                           /*!< TIMER1 MCR: MR3S Mask               */

// ---------------------------------------  TIMER1_MR0  -------------------------------------------
#define TIMER1_MR0_MATCH_Pos                                  0                                                         /*!< TIMER1 MR0: MATCH Position          */
#define TIMER1_MR0_MATCH_Msk                                  (0xffffffffUL << TIMER1_MR0_MATCH_Pos)                    /*!< TIMER1 MR0: MATCH Mask              */

// ---------------------------------------  TIMER1_MR1  -------------------------------------------
#define TIMER1_MR1_MATCH_Pos                                  0                                                         /*!< TIMER1 MR1: MATCH Position          */
#define TIMER1_MR1_MATCH_Msk                                  (0xffffffffUL << TIMER1_MR1_MATCH_Pos)                    /*!< TIMER1 MR1: MATCH Mask              */

// ---------------------------------------  TIMER1_MR2  -------------------------------------------
#define TIMER1_MR2_MATCH_Pos                                  0                                                         /*!< TIMER1 MR2: MATCH Position          */
#define TIMER1_MR2_MATCH_Msk                                  (0xffffffffUL << TIMER1_MR2_MATCH_Pos)                    /*!< TIMER1 MR2: MATCH Mask              */

// ---------------------------------------  TIMER1_MR3  -------------------------------------------
#define TIMER1_MR3_MATCH_Pos                                  0                                                         /*!< TIMER1 MR3: MATCH Position          */
#define TIMER1_MR3_MATCH_Msk                                  (0xffffffffUL << TIMER1_MR3_MATCH_Pos)                    /*!< TIMER1 MR3: MATCH Mask              */

// ---------------------------------------  TIMER1_CCR  -------------------------------------------
#define TIMER1_CCR_CAP0RE_Pos                                 0                                                         /*!< TIMER1 CCR: CAP0RE Position         */
#define TIMER1_CCR_CAP0RE_Msk                                 (0x01UL << TIMER1_CCR_CAP0RE_Pos)                         /*!< TIMER1 CCR: CAP0RE Mask             */
#define TIMER1_CCR_CAP0FE_Pos                                 1                                                         /*!< TIMER1 CCR: CAP0FE Position         */
#define TIMER1_CCR_CAP0FE_Msk                                 (0x01UL << TIMER1_CCR_CAP0FE_Pos)                         /*!< TIMER1 CCR: CAP0FE Mask             */
#define TIMER1_CCR_CAP0I_Pos                                  2                                                         /*!< TIMER1 CCR: CAP0I Position          */
#define TIMER1_CCR_CAP0I_Msk                                  (0x01UL << TIMER1_CCR_CAP0I_Pos)                          /*!< TIMER1 CCR: CAP0I Mask              */
#define TIMER1_CCR_CAP1RE_Pos                                 3                                                         /*!< TIMER1 CCR: CAP1RE Position         */
#define TIMER1_CCR_CAP1RE_Msk                                 (0x01UL << TIMER1_CCR_CAP1RE_Pos)                         /*!< TIMER1 CCR: CAP1RE Mask             */
#define TIMER1_CCR_CAP1FE_Pos                                 4                                                         /*!< TIMER1 CCR: CAP1FE Position         */
#define TIMER1_CCR_CAP1FE_Msk                                 (0x01UL << TIMER1_CCR_CAP1FE_Pos)                         /*!< TIMER1 CCR: CAP1FE Mask             */
#define TIMER1_CCR_CAP1I_Pos                                  5                                                         /*!< TIMER1 CCR: CAP1I Position          */
#define TIMER1_CCR_CAP1I_Msk                                  (0x01UL << TIMER1_CCR_CAP1I_Pos)                          /*!< TIMER1 CCR: CAP1I Mask              */
#define TIMER1_CCR_CAP2RE_Pos                                 6                                                         /*!< TIMER1 CCR: CAP2RE Position         */
#define TIMER1_CCR_CAP2RE_Msk                                 (0x01UL << TIMER1_CCR_CAP2RE_Pos)                         /*!< TIMER1 CCR: CAP2RE Mask             */
#define TIMER1_CCR_CAP2FE_Pos                                 7                                                         /*!< TIMER1 CCR: CAP2FE Position         */
#define TIMER1_CCR_CAP2FE_Msk                                 (0x01UL << TIMER1_CCR_CAP2FE_Pos)                         /*!< TIMER1 CCR: CAP2FE Mask             */
#define TIMER1_CCR_CAP2I_Pos                                  8                                                         /*!< TIMER1 CCR: CAP2I Position          */
#define TIMER1_CCR_CAP2I_Msk                                  (0x01UL << TIMER1_CCR_CAP2I_Pos)                          /*!< TIMER1 CCR: CAP2I Mask              */
#define TIMER1_CCR_CAP3RE_Pos                                 9                                                         /*!< TIMER1 CCR: CAP3RE Position         */
#define TIMER1_CCR_CAP3RE_Msk                                 (0x01UL << TIMER1_CCR_CAP3RE_Pos)                         /*!< TIMER1 CCR: CAP3RE Mask             */
#define TIMER1_CCR_CAP3FE_Pos                                 10                                                        /*!< TIMER1 CCR: CAP3FE Position         */
#define TIMER1_CCR_CAP3FE_Msk                                 (0x01UL << TIMER1_CCR_CAP3FE_Pos)                         /*!< TIMER1 CCR: CAP3FE Mask             */
#define TIMER1_CCR_CAP3I_Pos                                  11                                                        /*!< TIMER1 CCR: CAP3I Position          */
#define TIMER1_CCR_CAP3I_Msk                                  (0x01UL << TIMER1_CCR_CAP3I_Pos)                          /*!< TIMER1 CCR: CAP3I Mask              */

// ---------------------------------------  TIMER1_CR0  -------------------------------------------
#define TIMER1_CR0_CAP_Pos                                    0                                                         /*!< TIMER1 CR0: CAP Position            */
#define TIMER1_CR0_CAP_Msk                                    (0xffffffffUL << TIMER1_CR0_CAP_Pos)                      /*!< TIMER1 CR0: CAP Mask                */

// ---------------------------------------  TIMER1_CR1  -------------------------------------------
#define TIMER1_CR1_CAP_Pos                                    0                                                         /*!< TIMER1 CR1: CAP Position            */
#define TIMER1_CR1_CAP_Msk                                    (0xffffffffUL << TIMER1_CR1_CAP_Pos)                      /*!< TIMER1 CR1: CAP Mask                */

// ---------------------------------------  TIMER1_CR2  -------------------------------------------
#define TIMER1_CR2_CAP_Pos                                    0                                                         /*!< TIMER1 CR2: CAP Position            */
#define TIMER1_CR2_CAP_Msk                                    (0xffffffffUL << TIMER1_CR2_CAP_Pos)                      /*!< TIMER1 CR2: CAP Mask                */

// ---------------------------------------  TIMER1_CR3  -------------------------------------------
#define TIMER1_CR3_CAP_Pos                                    0                                                         /*!< TIMER1 CR3: CAP Position            */
#define TIMER1_CR3_CAP_Msk                                    (0xffffffffUL << TIMER1_CR3_CAP_Pos)                      /*!< TIMER1 CR3: CAP Mask                */

// ---------------------------------------  TIMER1_EMR  -------------------------------------------
#define TIMER1_EMR_EM0_Pos                                    0                                                         /*!< TIMER1 EMR: EM0 Position            */
#define TIMER1_EMR_EM0_Msk                                    (0x01UL << TIMER1_EMR_EM0_Pos)                            /*!< TIMER1 EMR: EM0 Mask                */
#define TIMER1_EMR_EM1_Pos                                    1                                                         /*!< TIMER1 EMR: EM1 Position            */
#define TIMER1_EMR_EM1_Msk                                    (0x01UL << TIMER1_EMR_EM1_Pos)                            /*!< TIMER1 EMR: EM1 Mask                */
#define TIMER1_EMR_EM2_Pos                                    2                                                         /*!< TIMER1 EMR: EM2 Position            */
#define TIMER1_EMR_EM2_Msk                                    (0x01UL << TIMER1_EMR_EM2_Pos)                            /*!< TIMER1 EMR: EM2 Mask                */
#define TIMER1_EMR_EM3_Pos                                    3                                                         /*!< TIMER1 EMR: EM3 Position            */
#define TIMER1_EMR_EM3_Msk                                    (0x01UL << TIMER1_EMR_EM3_Pos)                            /*!< TIMER1 EMR: EM3 Mask                */
#define TIMER1_EMR_EMC0_Pos                                   4                                                         /*!< TIMER1 EMR: EMC0 Position           */
#define TIMER1_EMR_EMC0_Msk                                   (0x03UL << TIMER1_EMR_EMC0_Pos)                           /*!< TIMER1 EMR: EMC0 Mask               */
#define TIMER1_EMR_EMC1_Pos                                   6                                                         /*!< TIMER1 EMR: EMC1 Position           */
#define TIMER1_EMR_EMC1_Msk                                   (0x03UL << TIMER1_EMR_EMC1_Pos)                           /*!< TIMER1 EMR: EMC1 Mask               */
#define TIMER1_EMR_EMC2_Pos                                   8                                                         /*!< TIMER1 EMR: EMC2 Position           */
#define TIMER1_EMR_EMC2_Msk                                   (0x03UL << TIMER1_EMR_EMC2_Pos)                           /*!< TIMER1 EMR: EMC2 Mask               */
#define TIMER1_EMR_EMC3_Pos                                   10                                                        /*!< TIMER1 EMR: EMC3 Position           */
#define TIMER1_EMR_EMC3_Msk                                   (0x03UL << TIMER1_EMR_EMC3_Pos)                           /*!< TIMER1 EMR: EMC3 Mask               */

// ---------------------------------------  TIMER1_CTCR  ------------------------------------------
#define TIMER1_CTCR_CTMODE_Pos                                0                                                         /*!< TIMER1 CTCR: CTMODE Position        */
#define TIMER1_CTCR_CTMODE_Msk                                (0x03UL << TIMER1_CTCR_CTMODE_Pos)                        /*!< TIMER1 CTCR: CTMODE Mask            */
#define TIMER1_CTCR_CINSEL_Pos                                2                                                         /*!< TIMER1 CTCR: CINSEL Position        */
#define TIMER1_CTCR_CINSEL_Msk                                (0x03UL << TIMER1_CTCR_CINSEL_Pos)                        /*!< TIMER1 CTCR: CINSEL Mask            */


// ------------------------------------------------------------------------------------------------
// -----                                TIMER2 Position & Mask                                -----
// ------------------------------------------------------------------------------------------------


// ----------------------------------------  TIMER2_IR  -------------------------------------------
#define TIMER2_IR_MR0INT_Pos                                  0                                                         /*!< TIMER2 IR: MR0INT Position          */
#define TIMER2_IR_MR0INT_Msk                                  (0x01UL << TIMER2_IR_MR0INT_Pos)                          /*!< TIMER2 IR: MR0INT Mask              */
#define TIMER2_IR_MR1INT_Pos                                  1                                                         /*!< TIMER2 IR: MR1INT Position          */
#define TIMER2_IR_MR1INT_Msk                                  (0x01UL << TIMER2_IR_MR1INT_Pos)                          /*!< TIMER2 IR: MR1INT Mask              */
#define TIMER2_IR_MR2INT_Pos                                  2                                                         /*!< TIMER2 IR: MR2INT Position          */
#define TIMER2_IR_MR2INT_Msk                                  (0x01UL << TIMER2_IR_MR2INT_Pos)                          /*!< TIMER2 IR: MR2INT Mask              */
#define TIMER2_IR_MR3INT_Pos                                  3                                                         /*!< TIMER2 IR: MR3INT Position          */
#define TIMER2_IR_MR3INT_Msk                                  (0x01UL << TIMER2_IR_MR3INT_Pos)                          /*!< TIMER2 IR: MR3INT Mask              */
#define TIMER2_IR_CR0INT_Pos                                  4                                                         /*!< TIMER2 IR: CR0INT Position          */
#define TIMER2_IR_CR0INT_Msk                                  (0x01UL << TIMER2_IR_CR0INT_Pos)                          /*!< TIMER2 IR: CR0INT Mask              */
#define TIMER2_IR_CR1INT_Pos                                  5                                                         /*!< TIMER2 IR: CR1INT Position          */
#define TIMER2_IR_CR1INT_Msk                                  (0x01UL << TIMER2_IR_CR1INT_Pos)                          /*!< TIMER2 IR: CR1INT Mask              */
#define TIMER2_IR_CR2INT_Pos                                  6                                                         /*!< TIMER2 IR: CR2INT Position          */
#define TIMER2_IR_CR2INT_Msk                                  (0x01UL << TIMER2_IR_CR2INT_Pos)                          /*!< TIMER2 IR: CR2INT Mask              */
#define TIMER2_IR_CR3INT_Pos                                  7                                                         /*!< TIMER2 IR: CR3INT Position          */
#define TIMER2_IR_CR3INT_Msk                                  (0x01UL << TIMER2_IR_CR3INT_Pos)                          /*!< TIMER2 IR: CR3INT Mask              */

// ---------------------------------------  TIMER2_TCR  -------------------------------------------
#define TIMER2_TCR_CEN_Pos                                    0                                                         /*!< TIMER2 TCR: CEN Position            */
#define TIMER2_TCR_CEN_Msk                                    (0x01UL << TIMER2_TCR_CEN_Pos)                            /*!< TIMER2 TCR: CEN Mask                */
#define TIMER2_TCR_CRST_Pos                                   1                                                         /*!< TIMER2 TCR: CRST Position           */
#define TIMER2_TCR_CRST_Msk                                   (0x01UL << TIMER2_TCR_CRST_Pos)                           /*!< TIMER2 TCR: CRST Mask               */

// ----------------------------------------  TIMER2_TC  -------------------------------------------
#define TIMER2_TC_TC_Pos                                      0                                                         /*!< TIMER2 TC: TC Position              */
#define TIMER2_TC_TC_Msk                                      (0xffffffffUL << TIMER2_TC_TC_Pos)                        /*!< TIMER2 TC: TC Mask                  */

// ----------------------------------------  TIMER2_PR  -------------------------------------------
#define TIMER2_PR_PM_Pos                                      0                                                         /*!< TIMER2 PR: PM Position              */
#define TIMER2_PR_PM_Msk                                      (0xffffffffUL << TIMER2_PR_PM_Pos)                        /*!< TIMER2 PR: PM Mask                  */

// ----------------------------------------  TIMER2_PC  -------------------------------------------
#define TIMER2_PC_PC_Pos                                      0                                                         /*!< TIMER2 PC: PC Position              */
#define TIMER2_PC_PC_Msk                                      (0xffffffffUL << TIMER2_PC_PC_Pos)                        /*!< TIMER2 PC: PC Mask                  */

// ---------------------------------------  TIMER2_MCR  -------------------------------------------
#define TIMER2_MCR_MR0I_Pos                                   0                                                         /*!< TIMER2 MCR: MR0I Position           */
#define TIMER2_MCR_MR0I_Msk                                   (0x01UL << TIMER2_MCR_MR0I_Pos)                           /*!< TIMER2 MCR: MR0I Mask               */
#define TIMER2_MCR_MR0R_Pos                                   1                                                         /*!< TIMER2 MCR: MR0R Position           */
#define TIMER2_MCR_MR0R_Msk                                   (0x01UL << TIMER2_MCR_MR0R_Pos)                           /*!< TIMER2 MCR: MR0R Mask               */
#define TIMER2_MCR_MR0S_Pos                                   2                                                         /*!< TIMER2 MCR: MR0S Position           */
#define TIMER2_MCR_MR0S_Msk                                   (0x01UL << TIMER2_MCR_MR0S_Pos)                           /*!< TIMER2 MCR: MR0S Mask               */
#define TIMER2_MCR_MR1I_Pos                                   3                                                         /*!< TIMER2 MCR: MR1I Position           */
#define TIMER2_MCR_MR1I_Msk                                   (0x01UL << TIMER2_MCR_MR1I_Pos)                           /*!< TIMER2 MCR: MR1I Mask               */
#define TIMER2_MCR_MR1R_Pos                                   4                                                         /*!< TIMER2 MCR: MR1R Position           */
#define TIMER2_MCR_MR1R_Msk                                   (0x01UL << TIMER2_MCR_MR1R_Pos)                           /*!< TIMER2 MCR: MR1R Mask               */
#define TIMER2_MCR_MR1S_Pos                                   5                                                         /*!< TIMER2 MCR: MR1S Position           */
#define TIMER2_MCR_MR1S_Msk                                   (0x01UL << TIMER2_MCR_MR1S_Pos)                           /*!< TIMER2 MCR: MR1S Mask               */
#define TIMER2_MCR_MR2I_Pos                                   6                                                         /*!< TIMER2 MCR: MR2I Position           */
#define TIMER2_MCR_MR2I_Msk                                   (0x01UL << TIMER2_MCR_MR2I_Pos)                           /*!< TIMER2 MCR: MR2I Mask               */
#define TIMER2_MCR_MR2R_Pos                                   7                                                         /*!< TIMER2 MCR: MR2R Position           */
#define TIMER2_MCR_MR2R_Msk                                   (0x01UL << TIMER2_MCR_MR2R_Pos)                           /*!< TIMER2 MCR: MR2R Mask               */
#define TIMER2_MCR_MR2S_Pos                                   8                                                         /*!< TIMER2 MCR: MR2S Position           */
#define TIMER2_MCR_MR2S_Msk                                   (0x01UL << TIMER2_MCR_MR2S_Pos)                           /*!< TIMER2 MCR: MR2S Mask               */
#define TIMER2_MCR_MR3I_Pos                                   9                                                         /*!< TIMER2 MCR: MR3I Position           */
#define TIMER2_MCR_MR3I_Msk                                   (0x01UL << TIMER2_MCR_MR3I_Pos)                           /*!< TIMER2 MCR: MR3I Mask               */
#define TIMER2_MCR_MR3R_Pos                                   10                                                        /*!< TIMER2 MCR: MR3R Position           */
#define TIMER2_MCR_MR3R_Msk                                   (0x01UL << TIMER2_MCR_MR3R_Pos)                           /*!< TIMER2 MCR: MR3R Mask               */
#define TIMER2_MCR_MR3S_Pos                                   11                                                        /*!< TIMER2 MCR: MR3S Position           */
#define TIMER2_MCR_MR3S_Msk                                   (0x01UL << TIMER2_MCR_MR3S_Pos)                           /*!< TIMER2 MCR: MR3S Mask               */

// ---------------------------------------  TIMER2_MR0  -------------------------------------------
#define TIMER2_MR0_MATCH_Pos                                  0                                                         /*!< TIMER2 MR0: MATCH Position          */
#define TIMER2_MR0_MATCH_Msk                                  (0xffffffffUL << TIMER2_MR0_MATCH_Pos)                    /*!< TIMER2 MR0: MATCH Mask              */

// ---------------------------------------  TIMER2_MR1  -------------------------------------------
#define TIMER2_MR1_MATCH_Pos                                  0                                                         /*!< TIMER2 MR1: MATCH Position          */
#define TIMER2_MR1_MATCH_Msk                                  (0xffffffffUL << TIMER2_MR1_MATCH_Pos)                    /*!< TIMER2 MR1: MATCH Mask              */

// ---------------------------------------  TIMER2_MR2  -------------------------------------------
#define TIMER2_MR2_MATCH_Pos                                  0                                                         /*!< TIMER2 MR2: MATCH Position          */
#define TIMER2_MR2_MATCH_Msk                                  (0xffffffffUL << TIMER2_MR2_MATCH_Pos)                    /*!< TIMER2 MR2: MATCH Mask              */

// ---------------------------------------  TIMER2_MR3  -------------------------------------------
#define TIMER2_MR3_MATCH_Pos                                  0                                                         /*!< TIMER2 MR3: MATCH Position          */
#define TIMER2_MR3_MATCH_Msk                                  (0xffffffffUL << TIMER2_MR3_MATCH_Pos)                    /*!< TIMER2 MR3: MATCH Mask              */

// ---------------------------------------  TIMER2_CCR  -------------------------------------------
#define TIMER2_CCR_CAP0RE_Pos                                 0                                                         /*!< TIMER2 CCR: CAP0RE Position         */
#define TIMER2_CCR_CAP0RE_Msk                                 (0x01UL << TIMER2_CCR_CAP0RE_Pos)                         /*!< TIMER2 CCR: CAP0RE Mask             */
#define TIMER2_CCR_CAP0FE_Pos                                 1                                                         /*!< TIMER2 CCR: CAP0FE Position         */
#define TIMER2_CCR_CAP0FE_Msk                                 (0x01UL << TIMER2_CCR_CAP0FE_Pos)                         /*!< TIMER2 CCR: CAP0FE Mask             */
#define TIMER2_CCR_CAP0I_Pos                                  2                                                         /*!< TIMER2 CCR: CAP0I Position          */
#define TIMER2_CCR_CAP0I_Msk                                  (0x01UL << TIMER2_CCR_CAP0I_Pos)                          /*!< TIMER2 CCR: CAP0I Mask              */
#define TIMER2_CCR_CAP1RE_Pos                                 3                                                         /*!< TIMER2 CCR: CAP1RE Position         */
#define TIMER2_CCR_CAP1RE_Msk                                 (0x01UL << TIMER2_CCR_CAP1RE_Pos)                         /*!< TIMER2 CCR: CAP1RE Mask             */
#define TIMER2_CCR_CAP1FE_Pos                                 4                                                         /*!< TIMER2 CCR: CAP1FE Position         */
#define TIMER2_CCR_CAP1FE_Msk                                 (0x01UL << TIMER2_CCR_CAP1FE_Pos)                         /*!< TIMER2 CCR: CAP1FE Mask             */
#define TIMER2_CCR_CAP1I_Pos                                  5                                                         /*!< TIMER2 CCR: CAP1I Position          */
#define TIMER2_CCR_CAP1I_Msk                                  (0x01UL << TIMER2_CCR_CAP1I_Pos)                          /*!< TIMER2 CCR: CAP1I Mask              */
#define TIMER2_CCR_CAP2RE_Pos                                 6                                                         /*!< TIMER2 CCR: CAP2RE Position         */
#define TIMER2_CCR_CAP2RE_Msk                                 (0x01UL << TIMER2_CCR_CAP2RE_Pos)                         /*!< TIMER2 CCR: CAP2RE Mask             */
#define TIMER2_CCR_CAP2FE_Pos                                 7                                                         /*!< TIMER2 CCR: CAP2FE Position         */
#define TIMER2_CCR_CAP2FE_Msk                                 (0x01UL << TIMER2_CCR_CAP2FE_Pos)                         /*!< TIMER2 CCR: CAP2FE Mask             */
#define TIMER2_CCR_CAP2I_Pos                                  8                                                         /*!< TIMER2 CCR: CAP2I Position          */
#define TIMER2_CCR_CAP2I_Msk                                  (0x01UL << TIMER2_CCR_CAP2I_Pos)                          /*!< TIMER2 CCR: CAP2I Mask              */
#define TIMER2_CCR_CAP3RE_Pos                                 9                                                         /*!< TIMER2 CCR: CAP3RE Position         */
#define TIMER2_CCR_CAP3RE_Msk                                 (0x01UL << TIMER2_CCR_CAP3RE_Pos)                         /*!< TIMER2 CCR: CAP3RE Mask             */
#define TIMER2_CCR_CAP3FE_Pos                                 10                                                        /*!< TIMER2 CCR: CAP3FE Position         */
#define TIMER2_CCR_CAP3FE_Msk                                 (0x01UL << TIMER2_CCR_CAP3FE_Pos)                         /*!< TIMER2 CCR: CAP3FE Mask             */
#define TIMER2_CCR_CAP3I_Pos                                  11                                                        /*!< TIMER2 CCR: CAP3I Position          */
#define TIMER2_CCR_CAP3I_Msk                                  (0x01UL << TIMER2_CCR_CAP3I_Pos)                          /*!< TIMER2 CCR: CAP3I Mask              */

// ---------------------------------------  TIMER2_CR0  -------------------------------------------
#define TIMER2_CR0_CAP_Pos                                    0                                                         /*!< TIMER2 CR0: CAP Position            */
#define TIMER2_CR0_CAP_Msk                                    (0xffffffffUL << TIMER2_CR0_CAP_Pos)                      /*!< TIMER2 CR0: CAP Mask                */

// ---------------------------------------  TIMER2_CR1  -------------------------------------------
#define TIMER2_CR1_CAP_Pos                                    0                                                         /*!< TIMER2 CR1: CAP Position            */
#define TIMER2_CR1_CAP_Msk                                    (0xffffffffUL << TIMER2_CR1_CAP_Pos)                      /*!< TIMER2 CR1: CAP Mask                */

// ---------------------------------------  TIMER2_CR2  -------------------------------------------
#define TIMER2_CR2_CAP_Pos                                    0                                                         /*!< TIMER2 CR2: CAP Position            */
#define TIMER2_CR2_CAP_Msk                                    (0xffffffffUL << TIMER2_CR2_CAP_Pos)                      /*!< TIMER2 CR2: CAP Mask                */

// ---------------------------------------  TIMER2_CR3  -------------------------------------------
#define TIMER2_CR3_CAP_Pos                                    0                                                         /*!< TIMER2 CR3: CAP Position            */
#define TIMER2_CR3_CAP_Msk                                    (0xffffffffUL << TIMER2_CR3_CAP_Pos)                      /*!< TIMER2 CR3: CAP Mask                */

// ---------------------------------------  TIMER2_EMR  -------------------------------------------
#define TIMER2_EMR_EM0_Pos                                    0                                                         /*!< TIMER2 EMR: EM0 Position            */
#define TIMER2_EMR_EM0_Msk                                    (0x01UL << TIMER2_EMR_EM0_Pos)                            /*!< TIMER2 EMR: EM0 Mask                */
#define TIMER2_EMR_EM1_Pos                                    1                                                         /*!< TIMER2 EMR: EM1 Position            */
#define TIMER2_EMR_EM1_Msk                                    (0x01UL << TIMER2_EMR_EM1_Pos)                            /*!< TIMER2 EMR: EM1 Mask                */
#define TIMER2_EMR_EM2_Pos                                    2                                                         /*!< TIMER2 EMR: EM2 Position            */
#define TIMER2_EMR_EM2_Msk                                    (0x01UL << TIMER2_EMR_EM2_Pos)                            /*!< TIMER2 EMR: EM2 Mask                */
#define TIMER2_EMR_EM3_Pos                                    3                                                         /*!< TIMER2 EMR: EM3 Position            */
#define TIMER2_EMR_EM3_Msk                                    (0x01UL << TIMER2_EMR_EM3_Pos)                            /*!< TIMER2 EMR: EM3 Mask                */
#define TIMER2_EMR_EMC0_Pos                                   4                                                         /*!< TIMER2 EMR: EMC0 Position           */
#define TIMER2_EMR_EMC0_Msk                                   (0x03UL << TIMER2_EMR_EMC0_Pos)                           /*!< TIMER2 EMR: EMC0 Mask               */
#define TIMER2_EMR_EMC1_Pos                                   6                                                         /*!< TIMER2 EMR: EMC1 Position           */
#define TIMER2_EMR_EMC1_Msk                                   (0x03UL << TIMER2_EMR_EMC1_Pos)                           /*!< TIMER2 EMR: EMC1 Mask               */
#define TIMER2_EMR_EMC2_Pos                                   8                                                         /*!< TIMER2 EMR: EMC2 Position           */
#define TIMER2_EMR_EMC2_Msk                                   (0x03UL << TIMER2_EMR_EMC2_Pos)                           /*!< TIMER2 EMR: EMC2 Mask               */
#define TIMER2_EMR_EMC3_Pos                                   10                                                        /*!< TIMER2 EMR: EMC3 Position           */
#define TIMER2_EMR_EMC3_Msk                                   (0x03UL << TIMER2_EMR_EMC3_Pos)                           /*!< TIMER2 EMR: EMC3 Mask               */

// ---------------------------------------  TIMER2_CTCR  ------------------------------------------
#define TIMER2_CTCR_CTMODE_Pos                                0                                                         /*!< TIMER2 CTCR: CTMODE Position        */
#define TIMER2_CTCR_CTMODE_Msk                                (0x03UL << TIMER2_CTCR_CTMODE_Pos)                        /*!< TIMER2 CTCR: CTMODE Mask            */
#define TIMER2_CTCR_CINSEL_Pos                                2                                                         /*!< TIMER2 CTCR: CINSEL Position        */
#define TIMER2_CTCR_CINSEL_Msk                                (0x03UL << TIMER2_CTCR_CINSEL_Pos)                        /*!< TIMER2 CTCR: CINSEL Mask            */


// ------------------------------------------------------------------------------------------------
// -----                                TIMER3 Position & Mask                                -----
// ------------------------------------------------------------------------------------------------


// ----------------------------------------  TIMER3_IR  -------------------------------------------
#define TIMER3_IR_MR0INT_Pos                                  0                                                         /*!< TIMER3 IR: MR0INT Position          */
#define TIMER3_IR_MR0INT_Msk                                  (0x01UL << TIMER3_IR_MR0INT_Pos)                          /*!< TIMER3 IR: MR0INT Mask              */
#define TIMER3_IR_MR1INT_Pos                                  1                                                         /*!< TIMER3 IR: MR1INT Position          */
#define TIMER3_IR_MR1INT_Msk                                  (0x01UL << TIMER3_IR_MR1INT_Pos)                          /*!< TIMER3 IR: MR1INT Mask              */
#define TIMER3_IR_MR2INT_Pos                                  2                                                         /*!< TIMER3 IR: MR2INT Position          */
#define TIMER3_IR_MR2INT_Msk                                  (0x01UL << TIMER3_IR_MR2INT_Pos)                          /*!< TIMER3 IR: MR2INT Mask              */
#define TIMER3_IR_MR3INT_Pos                                  3                                                         /*!< TIMER3 IR: MR3INT Position          */
#define TIMER3_IR_MR3INT_Msk                                  (0x01UL << TIMER3_IR_MR3INT_Pos)                          /*!< TIMER3 IR: MR3INT Mask              */
#define TIMER3_IR_CR0INT_Pos                                  4                                                         /*!< TIMER3 IR: CR0INT Position          */
#define TIMER3_IR_CR0INT_Msk                                  (0x01UL << TIMER3_IR_CR0INT_Pos)                          /*!< TIMER3 IR: CR0INT Mask              */
#define TIMER3_IR_CR1INT_Pos                                  5                                                         /*!< TIMER3 IR: CR1INT Position          */
#define TIMER3_IR_CR1INT_Msk                                  (0x01UL << TIMER3_IR_CR1INT_Pos)                          /*!< TIMER3 IR: CR1INT Mask              */
#define TIMER3_IR_CR2INT_Pos                                  6                                                         /*!< TIMER3 IR: CR2INT Position          */
#define TIMER3_IR_CR2INT_Msk                                  (0x01UL << TIMER3_IR_CR2INT_Pos)                          /*!< TIMER3 IR: CR2INT Mask              */
#define TIMER3_IR_CR3INT_Pos                                  7                                                         /*!< TIMER3 IR: CR3INT Position          */
#define TIMER3_IR_CR3INT_Msk                                  (0x01UL << TIMER3_IR_CR3INT_Pos)                          /*!< TIMER3 IR: CR3INT Mask              */

// ---------------------------------------  TIMER3_TCR  -------------------------------------------
#define TIMER3_TCR_CEN_Pos                                    0                                                         /*!< TIMER3 TCR: CEN Position            */
#define TIMER3_TCR_CEN_Msk                                    (0x01UL << TIMER3_TCR_CEN_Pos)                            /*!< TIMER3 TCR: CEN Mask                */
#define TIMER3_TCR_CRST_Pos                                   1                                                         /*!< TIMER3 TCR: CRST Position           */
#define TIMER3_TCR_CRST_Msk                                   (0x01UL << TIMER3_TCR_CRST_Pos)                           /*!< TIMER3 TCR: CRST Mask               */

// ----------------------------------------  TIMER3_TC  -------------------------------------------
#define TIMER3_TC_TC_Pos                                      0                                                         /*!< TIMER3 TC: TC Position              */
#define TIMER3_TC_TC_Msk                                      (0xffffffffUL << TIMER3_TC_TC_Pos)                        /*!< TIMER3 TC: TC Mask                  */

// ----------------------------------------  TIMER3_PR  -------------------------------------------
#define TIMER3_PR_PM_Pos                                      0                                                         /*!< TIMER3 PR: PM Position              */
#define TIMER3_PR_PM_Msk                                      (0xffffffffUL << TIMER3_PR_PM_Pos)                        /*!< TIMER3 PR: PM Mask                  */

// ----------------------------------------  TIMER3_PC  -------------------------------------------
#define TIMER3_PC_PC_Pos                                      0                                                         /*!< TIMER3 PC: PC Position              */
#define TIMER3_PC_PC_Msk                                      (0xffffffffUL << TIMER3_PC_PC_Pos)                        /*!< TIMER3 PC: PC Mask                  */

// ---------------------------------------  TIMER3_MCR  -------------------------------------------
#define TIMER3_MCR_MR0I_Pos                                   0                                                         /*!< TIMER3 MCR: MR0I Position           */
#define TIMER3_MCR_MR0I_Msk                                   (0x01UL << TIMER3_MCR_MR0I_Pos)                           /*!< TIMER3 MCR: MR0I Mask               */
#define TIMER3_MCR_MR0R_Pos                                   1                                                         /*!< TIMER3 MCR: MR0R Position           */
#define TIMER3_MCR_MR0R_Msk                                   (0x01UL << TIMER3_MCR_MR0R_Pos)                           /*!< TIMER3 MCR: MR0R Mask               */
#define TIMER3_MCR_MR0S_Pos                                   2                                                         /*!< TIMER3 MCR: MR0S Position           */
#define TIMER3_MCR_MR0S_Msk                                   (0x01UL << TIMER3_MCR_MR0S_Pos)                           /*!< TIMER3 MCR: MR0S Mask               */
#define TIMER3_MCR_MR1I_Pos                                   3                                                         /*!< TIMER3 MCR: MR1I Position           */
#define TIMER3_MCR_MR1I_Msk                                   (0x01UL << TIMER3_MCR_MR1I_Pos)                           /*!< TIMER3 MCR: MR1I Mask               */
#define TIMER3_MCR_MR1R_Pos                                   4                                                         /*!< TIMER3 MCR: MR1R Position           */
#define TIMER3_MCR_MR1R_Msk                                   (0x01UL << TIMER3_MCR_MR1R_Pos)                           /*!< TIMER3 MCR: MR1R Mask               */
#define TIMER3_MCR_MR1S_Pos                                   5                                                         /*!< TIMER3 MCR: MR1S Position           */
#define TIMER3_MCR_MR1S_Msk                                   (0x01UL << TIMER3_MCR_MR1S_Pos)                           /*!< TIMER3 MCR: MR1S Mask               */
#define TIMER3_MCR_MR2I_Pos                                   6                                                         /*!< TIMER3 MCR: MR2I Position           */
#define TIMER3_MCR_MR2I_Msk                                   (0x01UL << TIMER3_MCR_MR2I_Pos)                           /*!< TIMER3 MCR: MR2I Mask               */
#define TIMER3_MCR_MR2R_Pos                                   7                                                         /*!< TIMER3 MCR: MR2R Position           */
#define TIMER3_MCR_MR2R_Msk                                   (0x01UL << TIMER3_MCR_MR2R_Pos)                           /*!< TIMER3 MCR: MR2R Mask               */
#define TIMER3_MCR_MR2S_Pos                                   8                                                         /*!< TIMER3 MCR: MR2S Position           */
#define TIMER3_MCR_MR2S_Msk                                   (0x01UL << TIMER3_MCR_MR2S_Pos)                           /*!< TIMER3 MCR: MR2S Mask               */
#define TIMER3_MCR_MR3I_Pos                                   9                                                         /*!< TIMER3 MCR: MR3I Position           */
#define TIMER3_MCR_MR3I_Msk                                   (0x01UL << TIMER3_MCR_MR3I_Pos)                           /*!< TIMER3 MCR: MR3I Mask               */
#define TIMER3_MCR_MR3R_Pos                                   10                                                        /*!< TIMER3 MCR: MR3R Position           */
#define TIMER3_MCR_MR3R_Msk                                   (0x01UL << TIMER3_MCR_MR3R_Pos)                           /*!< TIMER3 MCR: MR3R Mask               */
#define TIMER3_MCR_MR3S_Pos                                   11                                                        /*!< TIMER3 MCR: MR3S Position           */
#define TIMER3_MCR_MR3S_Msk                                   (0x01UL << TIMER3_MCR_MR3S_Pos)                           /*!< TIMER3 MCR: MR3S Mask               */

// ---------------------------------------  TIMER3_MR0  -------------------------------------------
#define TIMER3_MR0_MATCH_Pos                                  0                                                         /*!< TIMER3 MR0: MATCH Position          */
#define TIMER3_MR0_MATCH_Msk                                  (0xffffffffUL << TIMER3_MR0_MATCH_Pos)                    /*!< TIMER3 MR0: MATCH Mask              */

// ---------------------------------------  TIMER3_MR1  -------------------------------------------
#define TIMER3_MR1_MATCH_Pos                                  0                                                         /*!< TIMER3 MR1: MATCH Position          */
#define TIMER3_MR1_MATCH_Msk                                  (0xffffffffUL << TIMER3_MR1_MATCH_Pos)                    /*!< TIMER3 MR1: MATCH Mask              */

// ---------------------------------------  TIMER3_MR2  -------------------------------------------
#define TIMER3_MR2_MATCH_Pos                                  0                                                         /*!< TIMER3 MR2: MATCH Position          */
#define TIMER3_MR2_MATCH_Msk                                  (0xffffffffUL << TIMER3_MR2_MATCH_Pos)                    /*!< TIMER3 MR2: MATCH Mask              */

// ---------------------------------------  TIMER3_MR3  -------------------------------------------
#define TIMER3_MR3_MATCH_Pos                                  0                                                         /*!< TIMER3 MR3: MATCH Position          */
#define TIMER3_MR3_MATCH_Msk                                  (0xffffffffUL << TIMER3_MR3_MATCH_Pos)                    /*!< TIMER3 MR3: MATCH Mask              */

// ---------------------------------------  TIMER3_CCR  -------------------------------------------
#define TIMER3_CCR_CAP0RE_Pos                                 0                                                         /*!< TIMER3 CCR: CAP0RE Position         */
#define TIMER3_CCR_CAP0RE_Msk                                 (0x01UL << TIMER3_CCR_CAP0RE_Pos)                         /*!< TIMER3 CCR: CAP0RE Mask             */
#define TIMER3_CCR_CAP0FE_Pos                                 1                                                         /*!< TIMER3 CCR: CAP0FE Position         */
#define TIMER3_CCR_CAP0FE_Msk                                 (0x01UL << TIMER3_CCR_CAP0FE_Pos)                         /*!< TIMER3 CCR: CAP0FE Mask             */
#define TIMER3_CCR_CAP0I_Pos                                  2                                                         /*!< TIMER3 CCR: CAP0I Position          */
#define TIMER3_CCR_CAP0I_Msk                                  (0x01UL << TIMER3_CCR_CAP0I_Pos)                          /*!< TIMER3 CCR: CAP0I Mask              */
#define TIMER3_CCR_CAP1RE_Pos                                 3                                                         /*!< TIMER3 CCR: CAP1RE Position         */
#define TIMER3_CCR_CAP1RE_Msk                                 (0x01UL << TIMER3_CCR_CAP1RE_Pos)                         /*!< TIMER3 CCR: CAP1RE Mask             */
#define TIMER3_CCR_CAP1FE_Pos                                 4                                                         /*!< TIMER3 CCR: CAP1FE Position         */
#define TIMER3_CCR_CAP1FE_Msk                                 (0x01UL << TIMER3_CCR_CAP1FE_Pos)                         /*!< TIMER3 CCR: CAP1FE Mask             */
#define TIMER3_CCR_CAP1I_Pos                                  5                                                         /*!< TIMER3 CCR: CAP1I Position          */
#define TIMER3_CCR_CAP1I_Msk                                  (0x01UL << TIMER3_CCR_CAP1I_Pos)                          /*!< TIMER3 CCR: CAP1I Mask              */
#define TIMER3_CCR_CAP2RE_Pos                                 6                                                         /*!< TIMER3 CCR: CAP2RE Position         */
#define TIMER3_CCR_CAP2RE_Msk                                 (0x01UL << TIMER3_CCR_CAP2RE_Pos)                         /*!< TIMER3 CCR: CAP2RE Mask             */
#define TIMER3_CCR_CAP2FE_Pos                                 7                                                         /*!< TIMER3 CCR: CAP2FE Position         */
#define TIMER3_CCR_CAP2FE_Msk                                 (0x01UL << TIMER3_CCR_CAP2FE_Pos)                         /*!< TIMER3 CCR: CAP2FE Mask             */
#define TIMER3_CCR_CAP2I_Pos                                  8                                                         /*!< TIMER3 CCR: CAP2I Position          */
#define TIMER3_CCR_CAP2I_Msk                                  (0x01UL << TIMER3_CCR_CAP2I_Pos)                          /*!< TIMER3 CCR: CAP2I Mask              */
#define TIMER3_CCR_CAP3RE_Pos                                 9                                                         /*!< TIMER3 CCR: CAP3RE Position         */
#define TIMER3_CCR_CAP3RE_Msk                                 (0x01UL << TIMER3_CCR_CAP3RE_Pos)                         /*!< TIMER3 CCR: CAP3RE Mask             */
#define TIMER3_CCR_CAP3FE_Pos                                 10                                                        /*!< TIMER3 CCR: CAP3FE Position         */
#define TIMER3_CCR_CAP3FE_Msk                                 (0x01UL << TIMER3_CCR_CAP3FE_Pos)                         /*!< TIMER3 CCR: CAP3FE Mask             */
#define TIMER3_CCR_CAP3I_Pos                                  11                                                        /*!< TIMER3 CCR: CAP3I Position          */
#define TIMER3_CCR_CAP3I_Msk                                  (0x01UL << TIMER3_CCR_CAP3I_Pos)                          /*!< TIMER3 CCR: CAP3I Mask              */

// ---------------------------------------  TIMER3_CR0  -------------------------------------------
#define TIMER3_CR0_CAP_Pos                                    0                                                         /*!< TIMER3 CR0: CAP Position            */
#define TIMER3_CR0_CAP_Msk                                    (0xffffffffUL << TIMER3_CR0_CAP_Pos)                      /*!< TIMER3 CR0: CAP Mask                */

// ---------------------------------------  TIMER3_CR1  -------------------------------------------
#define TIMER3_CR1_CAP_Pos                                    0                                                         /*!< TIMER3 CR1: CAP Position            */
#define TIMER3_CR1_CAP_Msk                                    (0xffffffffUL << TIMER3_CR1_CAP_Pos)                      /*!< TIMER3 CR1: CAP Mask                */

// ---------------------------------------  TIMER3_CR2  -------------------------------------------
#define TIMER3_CR2_CAP_Pos                                    0                                                         /*!< TIMER3 CR2: CAP Position            */
#define TIMER3_CR2_CAP_Msk                                    (0xffffffffUL << TIMER3_CR2_CAP_Pos)                      /*!< TIMER3 CR2: CAP Mask                */

// ---------------------------------------  TIMER3_CR3  -------------------------------------------
#define TIMER3_CR3_CAP_Pos                                    0                                                         /*!< TIMER3 CR3: CAP Position            */
#define TIMER3_CR3_CAP_Msk                                    (0xffffffffUL << TIMER3_CR3_CAP_Pos)                      /*!< TIMER3 CR3: CAP Mask                */

// ---------------------------------------  TIMER3_EMR  -------------------------------------------
#define TIMER3_EMR_EM0_Pos                                    0                                                         /*!< TIMER3 EMR: EM0 Position            */
#define TIMER3_EMR_EM0_Msk                                    (0x01UL << TIMER3_EMR_EM0_Pos)                            /*!< TIMER3 EMR: EM0 Mask                */
#define TIMER3_EMR_EM1_Pos                                    1                                                         /*!< TIMER3 EMR: EM1 Position            */
#define TIMER3_EMR_EM1_Msk                                    (0x01UL << TIMER3_EMR_EM1_Pos)                            /*!< TIMER3 EMR: EM1 Mask                */
#define TIMER3_EMR_EM2_Pos                                    2                                                         /*!< TIMER3 EMR: EM2 Position            */
#define TIMER3_EMR_EM2_Msk                                    (0x01UL << TIMER3_EMR_EM2_Pos)                            /*!< TIMER3 EMR: EM2 Mask                */
#define TIMER3_EMR_EM3_Pos                                    3                                                         /*!< TIMER3 EMR: EM3 Position            */
#define TIMER3_EMR_EM3_Msk                                    (0x01UL << TIMER3_EMR_EM3_Pos)                            /*!< TIMER3 EMR: EM3 Mask                */
#define TIMER3_EMR_EMC0_Pos                                   4                                                         /*!< TIMER3 EMR: EMC0 Position           */
#define TIMER3_EMR_EMC0_Msk                                   (0x03UL << TIMER3_EMR_EMC0_Pos)                           /*!< TIMER3 EMR: EMC0 Mask               */
#define TIMER3_EMR_EMC1_Pos                                   6                                                         /*!< TIMER3 EMR: EMC1 Position           */
#define TIMER3_EMR_EMC1_Msk                                   (0x03UL << TIMER3_EMR_EMC1_Pos)                           /*!< TIMER3 EMR: EMC1 Mask               */
#define TIMER3_EMR_EMC2_Pos                                   8                                                         /*!< TIMER3 EMR: EMC2 Position           */
#define TIMER3_EMR_EMC2_Msk                                   (0x03UL << TIMER3_EMR_EMC2_Pos)                           /*!< TIMER3 EMR: EMC2 Mask               */
#define TIMER3_EMR_EMC3_Pos                                   10                                                        /*!< TIMER3 EMR: EMC3 Position           */
#define TIMER3_EMR_EMC3_Msk                                   (0x03UL << TIMER3_EMR_EMC3_Pos)                           /*!< TIMER3 EMR: EMC3 Mask               */

// ---------------------------------------  TIMER3_CTCR  ------------------------------------------
#define TIMER3_CTCR_CTMODE_Pos                                0                                                         /*!< TIMER3 CTCR: CTMODE Position        */
#define TIMER3_CTCR_CTMODE_Msk                                (0x03UL << TIMER3_CTCR_CTMODE_Pos)                        /*!< TIMER3 CTCR: CTMODE Mask            */
#define TIMER3_CTCR_CINSEL_Pos                                2                                                         /*!< TIMER3 CTCR: CINSEL Position        */
#define TIMER3_CTCR_CINSEL_Msk                                (0x03UL << TIMER3_CTCR_CINSEL_Pos)                        /*!< TIMER3 CTCR: CINSEL Mask            */


// ------------------------------------------------------------------------------------------------
// -----                                  SCU Position & Mask                                 -----
// ------------------------------------------------------------------------------------------------


// ---------------------------------------  SCU_SFSP0_0  ------------------------------------------
#define SCU_SFSP0_0_MODE_Pos                                  0                                                         /*!< SCU SFSP0_0: MODE Position          */
#define SCU_SFSP0_0_MODE_Msk                                  (0x07UL << SCU_SFSP0_0_MODE_Pos)                          /*!< SCU SFSP0_0: MODE Mask              */
#define SCU_SFSP0_0_EPD_Pos                                   3                                                         /*!< SCU SFSP0_0: EPD Position           */
#define SCU_SFSP0_0_EPD_Msk                                   (0x01UL << SCU_SFSP0_0_EPD_Pos)                           /*!< SCU SFSP0_0: EPD Mask               */
#define SCU_SFSP0_0_EPUN_Pos                                  4                                                         /*!< SCU SFSP0_0: EPUN Position          */
#define SCU_SFSP0_0_EPUN_Msk                                  (0x01UL << SCU_SFSP0_0_EPUN_Pos)                          /*!< SCU SFSP0_0: EPUN Mask              */
#define SCU_SFSP0_0_EHS_Pos                                   5                                                         /*!< SCU SFSP0_0: EHS Position           */
#define SCU_SFSP0_0_EHS_Msk                                   (0x01UL << SCU_SFSP0_0_EHS_Pos)                           /*!< SCU SFSP0_0: EHS Mask               */
#define SCU_SFSP0_0_EZI_Pos                                   6                                                         /*!< SCU SFSP0_0: EZI Position           */
#define SCU_SFSP0_0_EZI_Msk                                   (0x01UL << SCU_SFSP0_0_EZI_Pos)                           /*!< SCU SFSP0_0: EZI Mask               */

// ---------------------------------------  SCU_SFSP0_1  ------------------------------------------
#define SCU_SFSP0_1_MODE_Pos                                  0                                                         /*!< SCU SFSP0_1: MODE Position          */
#define SCU_SFSP0_1_MODE_Msk                                  (0x07UL << SCU_SFSP0_1_MODE_Pos)                          /*!< SCU SFSP0_1: MODE Mask              */
#define SCU_SFSP0_1_EPD_Pos                                   3                                                         /*!< SCU SFSP0_1: EPD Position           */
#define SCU_SFSP0_1_EPD_Msk                                   (0x01UL << SCU_SFSP0_1_EPD_Pos)                           /*!< SCU SFSP0_1: EPD Mask               */
#define SCU_SFSP0_1_EPUN_Pos                                  4                                                         /*!< SCU SFSP0_1: EPUN Position          */
#define SCU_SFSP0_1_EPUN_Msk                                  (0x01UL << SCU_SFSP0_1_EPUN_Pos)                          /*!< SCU SFSP0_1: EPUN Mask              */
#define SCU_SFSP0_1_EHS_Pos                                   5                                                         /*!< SCU SFSP0_1: EHS Position           */
#define SCU_SFSP0_1_EHS_Msk                                   (0x01UL << SCU_SFSP0_1_EHS_Pos)                           /*!< SCU SFSP0_1: EHS Mask               */
#define SCU_SFSP0_1_EZI_Pos                                   6                                                         /*!< SCU SFSP0_1: EZI Position           */
#define SCU_SFSP0_1_EZI_Msk                                   (0x01UL << SCU_SFSP0_1_EZI_Pos)                           /*!< SCU SFSP0_1: EZI Mask               */

// ---------------------------------------  SCU_SFSP1_0  ------------------------------------------
#define SCU_SFSP1_0_MODE_Pos                                  0                                                         /*!< SCU SFSP1_0: MODE Position          */
#define SCU_SFSP1_0_MODE_Msk                                  (0x07UL << SCU_SFSP1_0_MODE_Pos)                          /*!< SCU SFSP1_0: MODE Mask              */
#define SCU_SFSP1_0_EPD_Pos                                   3                                                         /*!< SCU SFSP1_0: EPD Position           */
#define SCU_SFSP1_0_EPD_Msk                                   (0x01UL << SCU_SFSP1_0_EPD_Pos)                           /*!< SCU SFSP1_0: EPD Mask               */
#define SCU_SFSP1_0_EPUN_Pos                                  4                                                         /*!< SCU SFSP1_0: EPUN Position          */
#define SCU_SFSP1_0_EPUN_Msk                                  (0x01UL << SCU_SFSP1_0_EPUN_Pos)                          /*!< SCU SFSP1_0: EPUN Mask              */
#define SCU_SFSP1_0_EHS_Pos                                   5                                                         /*!< SCU SFSP1_0: EHS Position           */
#define SCU_SFSP1_0_EHS_Msk                                   (0x01UL << SCU_SFSP1_0_EHS_Pos)                           /*!< SCU SFSP1_0: EHS Mask               */
#define SCU_SFSP1_0_EZI_Pos                                   6                                                         /*!< SCU SFSP1_0: EZI Position           */
#define SCU_SFSP1_0_EZI_Msk                                   (0x01UL << SCU_SFSP1_0_EZI_Pos)                           /*!< SCU SFSP1_0: EZI Mask               */
#define SCU_SFSP1_0_EHD_Pos                                   8                                                         /*!< SCU SFSP1_0: EHD Position           */
#define SCU_SFSP1_0_EHD_Msk                                   (0x03UL << SCU_SFSP1_0_EHD_Pos)                           /*!< SCU SFSP1_0: EHD Mask               */

// ---------------------------------------  SCU_SFSP1_1  ------------------------------------------
#define SCU_SFSP1_1_MODE_Pos                                  0                                                         /*!< SCU SFSP1_1: MODE Position          */
#define SCU_SFSP1_1_MODE_Msk                                  (0x07UL << SCU_SFSP1_1_MODE_Pos)                          /*!< SCU SFSP1_1: MODE Mask              */
#define SCU_SFSP1_1_EPD_Pos                                   3                                                         /*!< SCU SFSP1_1: EPD Position           */
#define SCU_SFSP1_1_EPD_Msk                                   (0x01UL << SCU_SFSP1_1_EPD_Pos)                           /*!< SCU SFSP1_1: EPD Mask               */
#define SCU_SFSP1_1_EPUN_Pos                                  4                                                         /*!< SCU SFSP1_1: EPUN Position          */
#define SCU_SFSP1_1_EPUN_Msk                                  (0x01UL << SCU_SFSP1_1_EPUN_Pos)                          /*!< SCU SFSP1_1: EPUN Mask              */
#define SCU_SFSP1_1_EHS_Pos                                   5                                                         /*!< SCU SFSP1_1: EHS Position           */
#define SCU_SFSP1_1_EHS_Msk                                   (0x01UL << SCU_SFSP1_1_EHS_Pos)                           /*!< SCU SFSP1_1: EHS Mask               */
#define SCU_SFSP1_1_EZI_Pos                                   6                                                         /*!< SCU SFSP1_1: EZI Position           */
#define SCU_SFSP1_1_EZI_Msk                                   (0x01UL << SCU_SFSP1_1_EZI_Pos)                           /*!< SCU SFSP1_1: EZI Mask               */
#define SCU_SFSP1_1_EHD_Pos                                   8                                                         /*!< SCU SFSP1_1: EHD Position           */
#define SCU_SFSP1_1_EHD_Msk                                   (0x03UL << SCU_SFSP1_1_EHD_Pos)                           /*!< SCU SFSP1_1: EHD Mask               */

// ---------------------------------------  SCU_SFSP1_2  ------------------------------------------
#define SCU_SFSP1_2_MODE_Pos                                  0                                                         /*!< SCU SFSP1_2: MODE Position          */
#define SCU_SFSP1_2_MODE_Msk                                  (0x07UL << SCU_SFSP1_2_MODE_Pos)                          /*!< SCU SFSP1_2: MODE Mask              */
#define SCU_SFSP1_2_EPD_Pos                                   3                                                         /*!< SCU SFSP1_2: EPD Position           */
#define SCU_SFSP1_2_EPD_Msk                                   (0x01UL << SCU_SFSP1_2_EPD_Pos)                           /*!< SCU SFSP1_2: EPD Mask               */
#define SCU_SFSP1_2_EPUN_Pos                                  4                                                         /*!< SCU SFSP1_2: EPUN Position          */
#define SCU_SFSP1_2_EPUN_Msk                                  (0x01UL << SCU_SFSP1_2_EPUN_Pos)                          /*!< SCU SFSP1_2: EPUN Mask              */
#define SCU_SFSP1_2_EHS_Pos                                   5                                                         /*!< SCU SFSP1_2: EHS Position           */
#define SCU_SFSP1_2_EHS_Msk                                   (0x01UL << SCU_SFSP1_2_EHS_Pos)                           /*!< SCU SFSP1_2: EHS Mask               */
#define SCU_SFSP1_2_EZI_Pos                                   6                                                         /*!< SCU SFSP1_2: EZI Position           */
#define SCU_SFSP1_2_EZI_Msk                                   (0x01UL << SCU_SFSP1_2_EZI_Pos)                           /*!< SCU SFSP1_2: EZI Mask               */
#define SCU_SFSP1_2_EHD_Pos                                   8                                                         /*!< SCU SFSP1_2: EHD Position           */
#define SCU_SFSP1_2_EHD_Msk                                   (0x03UL << SCU_SFSP1_2_EHD_Pos)                           /*!< SCU SFSP1_2: EHD Mask               */

// ---------------------------------------  SCU_SFSP1_3  ------------------------------------------
#define SCU_SFSP1_3_MODE_Pos                                  0                                                         /*!< SCU SFSP1_3: MODE Position          */
#define SCU_SFSP1_3_MODE_Msk                                  (0x07UL << SCU_SFSP1_3_MODE_Pos)                          /*!< SCU SFSP1_3: MODE Mask              */
#define SCU_SFSP1_3_EPD_Pos                                   3                                                         /*!< SCU SFSP1_3: EPD Position           */
#define SCU_SFSP1_3_EPD_Msk                                   (0x01UL << SCU_SFSP1_3_EPD_Pos)                           /*!< SCU SFSP1_3: EPD Mask               */
#define SCU_SFSP1_3_EPUN_Pos                                  4                                                         /*!< SCU SFSP1_3: EPUN Position          */
#define SCU_SFSP1_3_EPUN_Msk                                  (0x01UL << SCU_SFSP1_3_EPUN_Pos)                          /*!< SCU SFSP1_3: EPUN Mask              */
#define SCU_SFSP1_3_EHS_Pos                                   5                                                         /*!< SCU SFSP1_3: EHS Position           */
#define SCU_SFSP1_3_EHS_Msk                                   (0x01UL << SCU_SFSP1_3_EHS_Pos)                           /*!< SCU SFSP1_3: EHS Mask               */
#define SCU_SFSP1_3_EZI_Pos                                   6                                                         /*!< SCU SFSP1_3: EZI Position           */
#define SCU_SFSP1_3_EZI_Msk                                   (0x01UL << SCU_SFSP1_3_EZI_Pos)                           /*!< SCU SFSP1_3: EZI Mask               */
#define SCU_SFSP1_3_EHD_Pos                                   8                                                         /*!< SCU SFSP1_3: EHD Position           */
#define SCU_SFSP1_3_EHD_Msk                                   (0x03UL << SCU_SFSP1_3_EHD_Pos)                           /*!< SCU SFSP1_3: EHD Mask               */

// ---------------------------------------  SCU_SFSP1_4  ------------------------------------------
#define SCU_SFSP1_4_MODE_Pos                                  0                                                         /*!< SCU SFSP1_4: MODE Position          */
#define SCU_SFSP1_4_MODE_Msk                                  (0x07UL << SCU_SFSP1_4_MODE_Pos)                          /*!< SCU SFSP1_4: MODE Mask              */
#define SCU_SFSP1_4_EPD_Pos                                   3                                                         /*!< SCU SFSP1_4: EPD Position           */
#define SCU_SFSP1_4_EPD_Msk                                   (0x01UL << SCU_SFSP1_4_EPD_Pos)                           /*!< SCU SFSP1_4: EPD Mask               */
#define SCU_SFSP1_4_EPUN_Pos                                  4                                                         /*!< SCU SFSP1_4: EPUN Position          */
#define SCU_SFSP1_4_EPUN_Msk                                  (0x01UL << SCU_SFSP1_4_EPUN_Pos)                          /*!< SCU SFSP1_4: EPUN Mask              */
#define SCU_SFSP1_4_EHS_Pos                                   5                                                         /*!< SCU SFSP1_4: EHS Position           */
#define SCU_SFSP1_4_EHS_Msk                                   (0x01UL << SCU_SFSP1_4_EHS_Pos)                           /*!< SCU SFSP1_4: EHS Mask               */
#define SCU_SFSP1_4_EZI_Pos                                   6                                                         /*!< SCU SFSP1_4: EZI Position           */
#define SCU_SFSP1_4_EZI_Msk                                   (0x01UL << SCU_SFSP1_4_EZI_Pos)                           /*!< SCU SFSP1_4: EZI Mask               */
#define SCU_SFSP1_4_EHD_Pos                                   8                                                         /*!< SCU SFSP1_4: EHD Position           */
#define SCU_SFSP1_4_EHD_Msk                                   (0x03UL << SCU_SFSP1_4_EHD_Pos)                           /*!< SCU SFSP1_4: EHD Mask               */

// ---------------------------------------  SCU_SFSP1_5  ------------------------------------------
#define SCU_SFSP1_5_MODE_Pos                                  0                                                         /*!< SCU SFSP1_5: MODE Position          */
#define SCU_SFSP1_5_MODE_Msk                                  (0x07UL << SCU_SFSP1_5_MODE_Pos)                          /*!< SCU SFSP1_5: MODE Mask              */
#define SCU_SFSP1_5_EPD_Pos                                   3                                                         /*!< SCU SFSP1_5: EPD Position           */
#define SCU_SFSP1_5_EPD_Msk                                   (0x01UL << SCU_SFSP1_5_EPD_Pos)                           /*!< SCU SFSP1_5: EPD Mask               */
#define SCU_SFSP1_5_EPUN_Pos                                  4                                                         /*!< SCU SFSP1_5: EPUN Position          */
#define SCU_SFSP1_5_EPUN_Msk                                  (0x01UL << SCU_SFSP1_5_EPUN_Pos)                          /*!< SCU SFSP1_5: EPUN Mask              */
#define SCU_SFSP1_5_EHS_Pos                                   5                                                         /*!< SCU SFSP1_5: EHS Position           */
#define SCU_SFSP1_5_EHS_Msk                                   (0x01UL << SCU_SFSP1_5_EHS_Pos)                           /*!< SCU SFSP1_5: EHS Mask               */
#define SCU_SFSP1_5_EZI_Pos                                   6                                                         /*!< SCU SFSP1_5: EZI Position           */
#define SCU_SFSP1_5_EZI_Msk                                   (0x01UL << SCU_SFSP1_5_EZI_Pos)                           /*!< SCU SFSP1_5: EZI Mask               */
#define SCU_SFSP1_5_EHD_Pos                                   8                                                         /*!< SCU SFSP1_5: EHD Position           */
#define SCU_SFSP1_5_EHD_Msk                                   (0x03UL << SCU_SFSP1_5_EHD_Pos)                           /*!< SCU SFSP1_5: EHD Mask               */

// ---------------------------------------  SCU_SFSP1_6  ------------------------------------------
#define SCU_SFSP1_6_MODE_Pos                                  0                                                         /*!< SCU SFSP1_6: MODE Position          */
#define SCU_SFSP1_6_MODE_Msk                                  (0x07UL << SCU_SFSP1_6_MODE_Pos)                          /*!< SCU SFSP1_6: MODE Mask              */
#define SCU_SFSP1_6_EPD_Pos                                   3                                                         /*!< SCU SFSP1_6: EPD Position           */
#define SCU_SFSP1_6_EPD_Msk                                   (0x01UL << SCU_SFSP1_6_EPD_Pos)                           /*!< SCU SFSP1_6: EPD Mask               */
#define SCU_SFSP1_6_EPUN_Pos                                  4                                                         /*!< SCU SFSP1_6: EPUN Position          */
#define SCU_SFSP1_6_EPUN_Msk                                  (0x01UL << SCU_SFSP1_6_EPUN_Pos)                          /*!< SCU SFSP1_6: EPUN Mask              */
#define SCU_SFSP1_6_EHS_Pos                                   5                                                         /*!< SCU SFSP1_6: EHS Position           */
#define SCU_SFSP1_6_EHS_Msk                                   (0x01UL << SCU_SFSP1_6_EHS_Pos)                           /*!< SCU SFSP1_6: EHS Mask               */
#define SCU_SFSP1_6_EZI_Pos                                   6                                                         /*!< SCU SFSP1_6: EZI Position           */
#define SCU_SFSP1_6_EZI_Msk                                   (0x01UL << SCU_SFSP1_6_EZI_Pos)                           /*!< SCU SFSP1_6: EZI Mask               */
#define SCU_SFSP1_6_EHD_Pos                                   8                                                         /*!< SCU SFSP1_6: EHD Position           */
#define SCU_SFSP1_6_EHD_Msk                                   (0x03UL << SCU_SFSP1_6_EHD_Pos)                           /*!< SCU SFSP1_6: EHD Mask               */

// ---------------------------------------  SCU_SFSP1_7  ------------------------------------------
#define SCU_SFSP1_7_MODE_Pos                                  0                                                         /*!< SCU SFSP1_7: MODE Position          */
#define SCU_SFSP1_7_MODE_Msk                                  (0x07UL << SCU_SFSP1_7_MODE_Pos)                          /*!< SCU SFSP1_7: MODE Mask              */
#define SCU_SFSP1_7_EPD_Pos                                   3                                                         /*!< SCU SFSP1_7: EPD Position           */
#define SCU_SFSP1_7_EPD_Msk                                   (0x01UL << SCU_SFSP1_7_EPD_Pos)                           /*!< SCU SFSP1_7: EPD Mask               */
#define SCU_SFSP1_7_EPUN_Pos                                  4                                                         /*!< SCU SFSP1_7: EPUN Position          */
#define SCU_SFSP1_7_EPUN_Msk                                  (0x01UL << SCU_SFSP1_7_EPUN_Pos)                          /*!< SCU SFSP1_7: EPUN Mask              */
#define SCU_SFSP1_7_EHS_Pos                                   5                                                         /*!< SCU SFSP1_7: EHS Position           */
#define SCU_SFSP1_7_EHS_Msk                                   (0x01UL << SCU_SFSP1_7_EHS_Pos)                           /*!< SCU SFSP1_7: EHS Mask               */
#define SCU_SFSP1_7_EZI_Pos                                   6                                                         /*!< SCU SFSP1_7: EZI Position           */
#define SCU_SFSP1_7_EZI_Msk                                   (0x01UL << SCU_SFSP1_7_EZI_Pos)                           /*!< SCU SFSP1_7: EZI Mask               */
#define SCU_SFSP1_7_EHD_Pos                                   8                                                         /*!< SCU SFSP1_7: EHD Position           */
#define SCU_SFSP1_7_EHD_Msk                                   (0x03UL << SCU_SFSP1_7_EHD_Pos)                           /*!< SCU SFSP1_7: EHD Mask               */

// ---------------------------------------  SCU_SFSP1_8  ------------------------------------------
#define SCU_SFSP1_8_MODE_Pos                                  0                                                         /*!< SCU SFSP1_8: MODE Position          */
#define SCU_SFSP1_8_MODE_Msk                                  (0x07UL << SCU_SFSP1_8_MODE_Pos)                          /*!< SCU SFSP1_8: MODE Mask              */
#define SCU_SFSP1_8_EPD_Pos                                   3                                                         /*!< SCU SFSP1_8: EPD Position           */
#define SCU_SFSP1_8_EPD_Msk                                   (0x01UL << SCU_SFSP1_8_EPD_Pos)                           /*!< SCU SFSP1_8: EPD Mask               */
#define SCU_SFSP1_8_EPUN_Pos                                  4                                                         /*!< SCU SFSP1_8: EPUN Position          */
#define SCU_SFSP1_8_EPUN_Msk                                  (0x01UL << SCU_SFSP1_8_EPUN_Pos)                          /*!< SCU SFSP1_8: EPUN Mask              */
#define SCU_SFSP1_8_EHS_Pos                                   5                                                         /*!< SCU SFSP1_8: EHS Position           */
#define SCU_SFSP1_8_EHS_Msk                                   (0x01UL << SCU_SFSP1_8_EHS_Pos)                           /*!< SCU SFSP1_8: EHS Mask               */
#define SCU_SFSP1_8_EZI_Pos                                   6                                                         /*!< SCU SFSP1_8: EZI Position           */
#define SCU_SFSP1_8_EZI_Msk                                   (0x01UL << SCU_SFSP1_8_EZI_Pos)                           /*!< SCU SFSP1_8: EZI Mask               */
#define SCU_SFSP1_8_EHD_Pos                                   8                                                         /*!< SCU SFSP1_8: EHD Position           */
#define SCU_SFSP1_8_EHD_Msk                                   (0x03UL << SCU_SFSP1_8_EHD_Pos)                           /*!< SCU SFSP1_8: EHD Mask               */

// ---------------------------------------  SCU_SFSP1_9  ------------------------------------------
#define SCU_SFSP1_9_MODE_Pos                                  0                                                         /*!< SCU SFSP1_9: MODE Position          */
#define SCU_SFSP1_9_MODE_Msk                                  (0x07UL << SCU_SFSP1_9_MODE_Pos)                          /*!< SCU SFSP1_9: MODE Mask              */
#define SCU_SFSP1_9_EPD_Pos                                   3                                                         /*!< SCU SFSP1_9: EPD Position           */
#define SCU_SFSP1_9_EPD_Msk                                   (0x01UL << SCU_SFSP1_9_EPD_Pos)                           /*!< SCU SFSP1_9: EPD Mask               */
#define SCU_SFSP1_9_EPUN_Pos                                  4                                                         /*!< SCU SFSP1_9: EPUN Position          */
#define SCU_SFSP1_9_EPUN_Msk                                  (0x01UL << SCU_SFSP1_9_EPUN_Pos)                          /*!< SCU SFSP1_9: EPUN Mask              */
#define SCU_SFSP1_9_EHS_Pos                                   5                                                         /*!< SCU SFSP1_9: EHS Position           */
#define SCU_SFSP1_9_EHS_Msk                                   (0x01UL << SCU_SFSP1_9_EHS_Pos)                           /*!< SCU SFSP1_9: EHS Mask               */
#define SCU_SFSP1_9_EZI_Pos                                   6                                                         /*!< SCU SFSP1_9: EZI Position           */
#define SCU_SFSP1_9_EZI_Msk                                   (0x01UL << SCU_SFSP1_9_EZI_Pos)                           /*!< SCU SFSP1_9: EZI Mask               */
#define SCU_SFSP1_9_EHD_Pos                                   8                                                         /*!< SCU SFSP1_9: EHD Position           */
#define SCU_SFSP1_9_EHD_Msk                                   (0x03UL << SCU_SFSP1_9_EHD_Pos)                           /*!< SCU SFSP1_9: EHD Mask               */

// --------------------------------------  SCU_SFSP1_10  ------------------------------------------
#define SCU_SFSP1_10_MODE_Pos                                 0                                                         /*!< SCU SFSP1_10: MODE Position         */
#define SCU_SFSP1_10_MODE_Msk                                 (0x07UL << SCU_SFSP1_10_MODE_Pos)                         /*!< SCU SFSP1_10: MODE Mask             */
#define SCU_SFSP1_10_EPD_Pos                                  3                                                         /*!< SCU SFSP1_10: EPD Position          */
#define SCU_SFSP1_10_EPD_Msk                                  (0x01UL << SCU_SFSP1_10_EPD_Pos)                          /*!< SCU SFSP1_10: EPD Mask              */
#define SCU_SFSP1_10_EPUN_Pos                                 4                                                         /*!< SCU SFSP1_10: EPUN Position         */
#define SCU_SFSP1_10_EPUN_Msk                                 (0x01UL << SCU_SFSP1_10_EPUN_Pos)                         /*!< SCU SFSP1_10: EPUN Mask             */
#define SCU_SFSP1_10_EHS_Pos                                  5                                                         /*!< SCU SFSP1_10: EHS Position          */
#define SCU_SFSP1_10_EHS_Msk                                  (0x01UL << SCU_SFSP1_10_EHS_Pos)                          /*!< SCU SFSP1_10: EHS Mask              */
#define SCU_SFSP1_10_EZI_Pos                                  6                                                         /*!< SCU SFSP1_10: EZI Position          */
#define SCU_SFSP1_10_EZI_Msk                                  (0x01UL << SCU_SFSP1_10_EZI_Pos)                          /*!< SCU SFSP1_10: EZI Mask              */
#define SCU_SFSP1_10_EHD_Pos                                  8                                                         /*!< SCU SFSP1_10: EHD Position          */
#define SCU_SFSP1_10_EHD_Msk                                  (0x03UL << SCU_SFSP1_10_EHD_Pos)                          /*!< SCU SFSP1_10: EHD Mask              */

// --------------------------------------  SCU_SFSP1_11  ------------------------------------------
#define SCU_SFSP1_11_MODE_Pos                                 0                                                         /*!< SCU SFSP1_11: MODE Position         */
#define SCU_SFSP1_11_MODE_Msk                                 (0x07UL << SCU_SFSP1_11_MODE_Pos)                         /*!< SCU SFSP1_11: MODE Mask             */
#define SCU_SFSP1_11_EPD_Pos                                  3                                                         /*!< SCU SFSP1_11: EPD Position          */
#define SCU_SFSP1_11_EPD_Msk                                  (0x01UL << SCU_SFSP1_11_EPD_Pos)                          /*!< SCU SFSP1_11: EPD Mask              */
#define SCU_SFSP1_11_EPUN_Pos                                 4                                                         /*!< SCU SFSP1_11: EPUN Position         */
#define SCU_SFSP1_11_EPUN_Msk                                 (0x01UL << SCU_SFSP1_11_EPUN_Pos)                         /*!< SCU SFSP1_11: EPUN Mask             */
#define SCU_SFSP1_11_EHS_Pos                                  5                                                         /*!< SCU SFSP1_11: EHS Position          */
#define SCU_SFSP1_11_EHS_Msk                                  (0x01UL << SCU_SFSP1_11_EHS_Pos)                          /*!< SCU SFSP1_11: EHS Mask              */
#define SCU_SFSP1_11_EZI_Pos                                  6                                                         /*!< SCU SFSP1_11: EZI Position          */
#define SCU_SFSP1_11_EZI_Msk                                  (0x01UL << SCU_SFSP1_11_EZI_Pos)                          /*!< SCU SFSP1_11: EZI Mask              */
#define SCU_SFSP1_11_EHD_Pos                                  8                                                         /*!< SCU SFSP1_11: EHD Position          */
#define SCU_SFSP1_11_EHD_Msk                                  (0x03UL << SCU_SFSP1_11_EHD_Pos)                          /*!< SCU SFSP1_11: EHD Mask              */

// --------------------------------------  SCU_SFSP1_12  ------------------------------------------
#define SCU_SFSP1_12_MODE_Pos                                 0                                                         /*!< SCU SFSP1_12: MODE Position         */
#define SCU_SFSP1_12_MODE_Msk                                 (0x07UL << SCU_SFSP1_12_MODE_Pos)                         /*!< SCU SFSP1_12: MODE Mask             */
#define SCU_SFSP1_12_EPD_Pos                                  3                                                         /*!< SCU SFSP1_12: EPD Position          */
#define SCU_SFSP1_12_EPD_Msk                                  (0x01UL << SCU_SFSP1_12_EPD_Pos)                          /*!< SCU SFSP1_12: EPD Mask              */
#define SCU_SFSP1_12_EPUN_Pos                                 4                                                         /*!< SCU SFSP1_12: EPUN Position         */
#define SCU_SFSP1_12_EPUN_Msk                                 (0x01UL << SCU_SFSP1_12_EPUN_Pos)                         /*!< SCU SFSP1_12: EPUN Mask             */
#define SCU_SFSP1_12_EHS_Pos                                  5                                                         /*!< SCU SFSP1_12: EHS Position          */
#define SCU_SFSP1_12_EHS_Msk                                  (0x01UL << SCU_SFSP1_12_EHS_Pos)                          /*!< SCU SFSP1_12: EHS Mask              */
#define SCU_SFSP1_12_EZI_Pos                                  6                                                         /*!< SCU SFSP1_12: EZI Position          */
#define SCU_SFSP1_12_EZI_Msk                                  (0x01UL << SCU_SFSP1_12_EZI_Pos)                          /*!< SCU SFSP1_12: EZI Mask              */
#define SCU_SFSP1_12_EHD_Pos                                  8                                                         /*!< SCU SFSP1_12: EHD Position          */
#define SCU_SFSP1_12_EHD_Msk                                  (0x03UL << SCU_SFSP1_12_EHD_Pos)                          /*!< SCU SFSP1_12: EHD Mask              */

// --------------------------------------  SCU_SFSP1_13  ------------------------------------------
#define SCU_SFSP1_13_MODE_Pos                                 0                                                         /*!< SCU SFSP1_13: MODE Position         */
#define SCU_SFSP1_13_MODE_Msk                                 (0x07UL << SCU_SFSP1_13_MODE_Pos)                         /*!< SCU SFSP1_13: MODE Mask             */
#define SCU_SFSP1_13_EPD_Pos                                  3                                                         /*!< SCU SFSP1_13: EPD Position          */
#define SCU_SFSP1_13_EPD_Msk                                  (0x01UL << SCU_SFSP1_13_EPD_Pos)                          /*!< SCU SFSP1_13: EPD Mask              */
#define SCU_SFSP1_13_EPUN_Pos                                 4                                                         /*!< SCU SFSP1_13: EPUN Position         */
#define SCU_SFSP1_13_EPUN_Msk                                 (0x01UL << SCU_SFSP1_13_EPUN_Pos)                         /*!< SCU SFSP1_13: EPUN Mask             */
#define SCU_SFSP1_13_EHS_Pos                                  5                                                         /*!< SCU SFSP1_13: EHS Position          */
#define SCU_SFSP1_13_EHS_Msk                                  (0x01UL << SCU_SFSP1_13_EHS_Pos)                          /*!< SCU SFSP1_13: EHS Mask              */
#define SCU_SFSP1_13_EZI_Pos                                  6                                                         /*!< SCU SFSP1_13: EZI Position          */
#define SCU_SFSP1_13_EZI_Msk                                  (0x01UL << SCU_SFSP1_13_EZI_Pos)                          /*!< SCU SFSP1_13: EZI Mask              */
#define SCU_SFSP1_13_EHD_Pos                                  8                                                         /*!< SCU SFSP1_13: EHD Position          */
#define SCU_SFSP1_13_EHD_Msk                                  (0x03UL << SCU_SFSP1_13_EHD_Pos)                          /*!< SCU SFSP1_13: EHD Mask              */

// --------------------------------------  SCU_SFSP1_14  ------------------------------------------
#define SCU_SFSP1_14_MODE_Pos                                 0                                                         /*!< SCU SFSP1_14: MODE Position         */
#define SCU_SFSP1_14_MODE_Msk                                 (0x07UL << SCU_SFSP1_14_MODE_Pos)                         /*!< SCU SFSP1_14: MODE Mask             */
#define SCU_SFSP1_14_EPD_Pos                                  3                                                         /*!< SCU SFSP1_14: EPD Position          */
#define SCU_SFSP1_14_EPD_Msk                                  (0x01UL << SCU_SFSP1_14_EPD_Pos)                          /*!< SCU SFSP1_14: EPD Mask              */
#define SCU_SFSP1_14_EPUN_Pos                                 4                                                         /*!< SCU SFSP1_14: EPUN Position         */
#define SCU_SFSP1_14_EPUN_Msk                                 (0x01UL << SCU_SFSP1_14_EPUN_Pos)                         /*!< SCU SFSP1_14: EPUN Mask             */
#define SCU_SFSP1_14_EHS_Pos                                  5                                                         /*!< SCU SFSP1_14: EHS Position          */
#define SCU_SFSP1_14_EHS_Msk                                  (0x01UL << SCU_SFSP1_14_EHS_Pos)                          /*!< SCU SFSP1_14: EHS Mask              */
#define SCU_SFSP1_14_EZI_Pos                                  6                                                         /*!< SCU SFSP1_14: EZI Position          */
#define SCU_SFSP1_14_EZI_Msk                                  (0x01UL << SCU_SFSP1_14_EZI_Pos)                          /*!< SCU SFSP1_14: EZI Mask              */
#define SCU_SFSP1_14_EHD_Pos                                  8                                                         /*!< SCU SFSP1_14: EHD Position          */
#define SCU_SFSP1_14_EHD_Msk                                  (0x03UL << SCU_SFSP1_14_EHD_Pos)                          /*!< SCU SFSP1_14: EHD Mask              */

// --------------------------------------  SCU_SFSP1_15  ------------------------------------------
#define SCU_SFSP1_15_MODE_Pos                                 0                                                         /*!< SCU SFSP1_15: MODE Position         */
#define SCU_SFSP1_15_MODE_Msk                                 (0x07UL << SCU_SFSP1_15_MODE_Pos)                         /*!< SCU SFSP1_15: MODE Mask             */
#define SCU_SFSP1_15_EPD_Pos                                  3                                                         /*!< SCU SFSP1_15: EPD Position          */
#define SCU_SFSP1_15_EPD_Msk                                  (0x01UL << SCU_SFSP1_15_EPD_Pos)                          /*!< SCU SFSP1_15: EPD Mask              */
#define SCU_SFSP1_15_EPUN_Pos                                 4                                                         /*!< SCU SFSP1_15: EPUN Position         */
#define SCU_SFSP1_15_EPUN_Msk                                 (0x01UL << SCU_SFSP1_15_EPUN_Pos)                         /*!< SCU SFSP1_15: EPUN Mask             */
#define SCU_SFSP1_15_EHS_Pos                                  5                                                         /*!< SCU SFSP1_15: EHS Position          */
#define SCU_SFSP1_15_EHS_Msk                                  (0x01UL << SCU_SFSP1_15_EHS_Pos)                          /*!< SCU SFSP1_15: EHS Mask              */
#define SCU_SFSP1_15_EZI_Pos                                  6                                                         /*!< SCU SFSP1_15: EZI Position          */
#define SCU_SFSP1_15_EZI_Msk                                  (0x01UL << SCU_SFSP1_15_EZI_Pos)                          /*!< SCU SFSP1_15: EZI Mask              */
#define SCU_SFSP1_15_EHD_Pos                                  8                                                         /*!< SCU SFSP1_15: EHD Position          */
#define SCU_SFSP1_15_EHD_Msk                                  (0x03UL << SCU_SFSP1_15_EHD_Pos)                          /*!< SCU SFSP1_15: EHD Mask              */

// --------------------------------------  SCU_SFSP1_16  ------------------------------------------
#define SCU_SFSP1_16_MODE_Pos                                 0                                                         /*!< SCU SFSP1_16: MODE Position         */
#define SCU_SFSP1_16_MODE_Msk                                 (0x07UL << SCU_SFSP1_16_MODE_Pos)                         /*!< SCU SFSP1_16: MODE Mask             */
#define SCU_SFSP1_16_EPD_Pos                                  3                                                         /*!< SCU SFSP1_16: EPD Position          */
#define SCU_SFSP1_16_EPD_Msk                                  (0x01UL << SCU_SFSP1_16_EPD_Pos)                          /*!< SCU SFSP1_16: EPD Mask              */
#define SCU_SFSP1_16_EPUN_Pos                                 4                                                         /*!< SCU SFSP1_16: EPUN Position         */
#define SCU_SFSP1_16_EPUN_Msk                                 (0x01UL << SCU_SFSP1_16_EPUN_Pos)                         /*!< SCU SFSP1_16: EPUN Mask             */
#define SCU_SFSP1_16_EHS_Pos                                  5                                                         /*!< SCU SFSP1_16: EHS Position          */
#define SCU_SFSP1_16_EHS_Msk                                  (0x01UL << SCU_SFSP1_16_EHS_Pos)                          /*!< SCU SFSP1_16: EHS Mask              */
#define SCU_SFSP1_16_EZI_Pos                                  6                                                         /*!< SCU SFSP1_16: EZI Position          */
#define SCU_SFSP1_16_EZI_Msk                                  (0x01UL << SCU_SFSP1_16_EZI_Pos)                          /*!< SCU SFSP1_16: EZI Mask              */
#define SCU_SFSP1_16_EHD_Pos                                  8                                                         /*!< SCU SFSP1_16: EHD Position          */
#define SCU_SFSP1_16_EHD_Msk                                  (0x03UL << SCU_SFSP1_16_EHD_Pos)                          /*!< SCU SFSP1_16: EHD Mask              */

// --------------------------------------  SCU_SFSP1_17  ------------------------------------------
#define SCU_SFSP1_17_MODE_Pos                                 0                                                         /*!< SCU SFSP1_17: MODE Position         */
#define SCU_SFSP1_17_MODE_Msk                                 (0x07UL << SCU_SFSP1_17_MODE_Pos)                         /*!< SCU SFSP1_17: MODE Mask             */
#define SCU_SFSP1_17_EPD_Pos                                  3                                                         /*!< SCU SFSP1_17: EPD Position          */
#define SCU_SFSP1_17_EPD_Msk                                  (0x01UL << SCU_SFSP1_17_EPD_Pos)                          /*!< SCU SFSP1_17: EPD Mask              */
#define SCU_SFSP1_17_EPUN_Pos                                 4                                                         /*!< SCU SFSP1_17: EPUN Position         */
#define SCU_SFSP1_17_EPUN_Msk                                 (0x01UL << SCU_SFSP1_17_EPUN_Pos)                         /*!< SCU SFSP1_17: EPUN Mask             */
#define SCU_SFSP1_17_EHS_Pos                                  5                                                         /*!< SCU SFSP1_17: EHS Position          */
#define SCU_SFSP1_17_EHS_Msk                                  (0x01UL << SCU_SFSP1_17_EHS_Pos)                          /*!< SCU SFSP1_17: EHS Mask              */
#define SCU_SFSP1_17_EZI_Pos                                  6                                                         /*!< SCU SFSP1_17: EZI Position          */
#define SCU_SFSP1_17_EZI_Msk                                  (0x01UL << SCU_SFSP1_17_EZI_Pos)                          /*!< SCU SFSP1_17: EZI Mask              */
#define SCU_SFSP1_17_EHD_Pos                                  8                                                         /*!< SCU SFSP1_17: EHD Position          */
#define SCU_SFSP1_17_EHD_Msk                                  (0x03UL << SCU_SFSP1_17_EHD_Pos)                          /*!< SCU SFSP1_17: EHD Mask              */

// --------------------------------------  SCU_SFSP1_18  ------------------------------------------
#define SCU_SFSP1_18_MODE_Pos                                 0                                                         /*!< SCU SFSP1_18: MODE Position         */
#define SCU_SFSP1_18_MODE_Msk                                 (0x07UL << SCU_SFSP1_18_MODE_Pos)                         /*!< SCU SFSP1_18: MODE Mask             */
#define SCU_SFSP1_18_EPD_Pos                                  3                                                         /*!< SCU SFSP1_18: EPD Position          */
#define SCU_SFSP1_18_EPD_Msk                                  (0x01UL << SCU_SFSP1_18_EPD_Pos)                          /*!< SCU SFSP1_18: EPD Mask              */
#define SCU_SFSP1_18_EPUN_Pos                                 4                                                         /*!< SCU SFSP1_18: EPUN Position         */
#define SCU_SFSP1_18_EPUN_Msk                                 (0x01UL << SCU_SFSP1_18_EPUN_Pos)                         /*!< SCU SFSP1_18: EPUN Mask             */
#define SCU_SFSP1_18_EHS_Pos                                  5                                                         /*!< SCU SFSP1_18: EHS Position          */
#define SCU_SFSP1_18_EHS_Msk                                  (0x01UL << SCU_SFSP1_18_EHS_Pos)                          /*!< SCU SFSP1_18: EHS Mask              */
#define SCU_SFSP1_18_EZI_Pos                                  6                                                         /*!< SCU SFSP1_18: EZI Position          */
#define SCU_SFSP1_18_EZI_Msk                                  (0x01UL << SCU_SFSP1_18_EZI_Pos)                          /*!< SCU SFSP1_18: EZI Mask              */
#define SCU_SFSP1_18_EHD_Pos                                  8                                                         /*!< SCU SFSP1_18: EHD Position          */
#define SCU_SFSP1_18_EHD_Msk                                  (0x03UL << SCU_SFSP1_18_EHD_Pos)                          /*!< SCU SFSP1_18: EHD Mask              */

// --------------------------------------  SCU_SFSP1_19  ------------------------------------------
#define SCU_SFSP1_19_MODE_Pos                                 0                                                         /*!< SCU SFSP1_19: MODE Position         */
#define SCU_SFSP1_19_MODE_Msk                                 (0x07UL << SCU_SFSP1_19_MODE_Pos)                         /*!< SCU SFSP1_19: MODE Mask             */
#define SCU_SFSP1_19_EPD_Pos                                  3                                                         /*!< SCU SFSP1_19: EPD Position          */
#define SCU_SFSP1_19_EPD_Msk                                  (0x01UL << SCU_SFSP1_19_EPD_Pos)                          /*!< SCU SFSP1_19: EPD Mask              */
#define SCU_SFSP1_19_EPUN_Pos                                 4                                                         /*!< SCU SFSP1_19: EPUN Position         */
#define SCU_SFSP1_19_EPUN_Msk                                 (0x01UL << SCU_SFSP1_19_EPUN_Pos)                         /*!< SCU SFSP1_19: EPUN Mask             */
#define SCU_SFSP1_19_EHS_Pos                                  5                                                         /*!< SCU SFSP1_19: EHS Position          */
#define SCU_SFSP1_19_EHS_Msk                                  (0x01UL << SCU_SFSP1_19_EHS_Pos)                          /*!< SCU SFSP1_19: EHS Mask              */
#define SCU_SFSP1_19_EZI_Pos                                  6                                                         /*!< SCU SFSP1_19: EZI Position          */
#define SCU_SFSP1_19_EZI_Msk                                  (0x01UL << SCU_SFSP1_19_EZI_Pos)                          /*!< SCU SFSP1_19: EZI Mask              */
#define SCU_SFSP1_19_EHD_Pos                                  8                                                         /*!< SCU SFSP1_19: EHD Position          */
#define SCU_SFSP1_19_EHD_Msk                                  (0x03UL << SCU_SFSP1_19_EHD_Pos)                          /*!< SCU SFSP1_19: EHD Mask              */

// --------------------------------------  SCU_SFSP1_20  ------------------------------------------
#define SCU_SFSP1_20_MODE_Pos                                 0                                                         /*!< SCU SFSP1_20: MODE Position         */
#define SCU_SFSP1_20_MODE_Msk                                 (0x07UL << SCU_SFSP1_20_MODE_Pos)                         /*!< SCU SFSP1_20: MODE Mask             */
#define SCU_SFSP1_20_EPD_Pos                                  3                                                         /*!< SCU SFSP1_20: EPD Position          */
#define SCU_SFSP1_20_EPD_Msk                                  (0x01UL << SCU_SFSP1_20_EPD_Pos)                          /*!< SCU SFSP1_20: EPD Mask              */
#define SCU_SFSP1_20_EPUN_Pos                                 4                                                         /*!< SCU SFSP1_20: EPUN Position         */
#define SCU_SFSP1_20_EPUN_Msk                                 (0x01UL << SCU_SFSP1_20_EPUN_Pos)                         /*!< SCU SFSP1_20: EPUN Mask             */
#define SCU_SFSP1_20_EHS_Pos                                  5                                                         /*!< SCU SFSP1_20: EHS Position          */
#define SCU_SFSP1_20_EHS_Msk                                  (0x01UL << SCU_SFSP1_20_EHS_Pos)                          /*!< SCU SFSP1_20: EHS Mask              */
#define SCU_SFSP1_20_EZI_Pos                                  6                                                         /*!< SCU SFSP1_20: EZI Position          */
#define SCU_SFSP1_20_EZI_Msk                                  (0x01UL << SCU_SFSP1_20_EZI_Pos)                          /*!< SCU SFSP1_20: EZI Mask              */
#define SCU_SFSP1_20_EHD_Pos                                  8                                                         /*!< SCU SFSP1_20: EHD Position          */
#define SCU_SFSP1_20_EHD_Msk                                  (0x03UL << SCU_SFSP1_20_EHD_Pos)                          /*!< SCU SFSP1_20: EHD Mask              */

// ---------------------------------------  SCU_SFSP2_0  ------------------------------------------
#define SCU_SFSP2_0_MODE_Pos                                  0                                                         /*!< SCU SFSP2_0: MODE Position          */
#define SCU_SFSP2_0_MODE_Msk                                  (0x07UL << SCU_SFSP2_0_MODE_Pos)                          /*!< SCU SFSP2_0: MODE Mask              */
#define SCU_SFSP2_0_EPD_Pos                                   3                                                         /*!< SCU SFSP2_0: EPD Position           */
#define SCU_SFSP2_0_EPD_Msk                                   (0x01UL << SCU_SFSP2_0_EPD_Pos)                           /*!< SCU SFSP2_0: EPD Mask               */
#define SCU_SFSP2_0_EPUN_Pos                                  4                                                         /*!< SCU SFSP2_0: EPUN Position          */
#define SCU_SFSP2_0_EPUN_Msk                                  (0x01UL << SCU_SFSP2_0_EPUN_Pos)                          /*!< SCU SFSP2_0: EPUN Mask              */
#define SCU_SFSP2_0_EHS_Pos                                   5                                                         /*!< SCU SFSP2_0: EHS Position           */
#define SCU_SFSP2_0_EHS_Msk                                   (0x01UL << SCU_SFSP2_0_EHS_Pos)                           /*!< SCU SFSP2_0: EHS Mask               */
#define SCU_SFSP2_0_EZI_Pos                                   6                                                         /*!< SCU SFSP2_0: EZI Position           */
#define SCU_SFSP2_0_EZI_Msk                                   (0x01UL << SCU_SFSP2_0_EZI_Pos)                           /*!< SCU SFSP2_0: EZI Mask               */
#define SCU_SFSP2_0_EHD_Pos                                   8                                                         /*!< SCU SFSP2_0: EHD Position           */
#define SCU_SFSP2_0_EHD_Msk                                   (0x03UL << SCU_SFSP2_0_EHD_Pos)                           /*!< SCU SFSP2_0: EHD Mask               */

// ---------------------------------------  SCU_SFSP2_1  ------------------------------------------
#define SCU_SFSP2_1_MODE_Pos                                  0                                                         /*!< SCU SFSP2_1: MODE Position          */
#define SCU_SFSP2_1_MODE_Msk                                  (0x07UL << SCU_SFSP2_1_MODE_Pos)                          /*!< SCU SFSP2_1: MODE Mask              */
#define SCU_SFSP2_1_EPD_Pos                                   3                                                         /*!< SCU SFSP2_1: EPD Position           */
#define SCU_SFSP2_1_EPD_Msk                                   (0x01UL << SCU_SFSP2_1_EPD_Pos)                           /*!< SCU SFSP2_1: EPD Mask               */
#define SCU_SFSP2_1_EPUN_Pos                                  4                                                         /*!< SCU SFSP2_1: EPUN Position          */
#define SCU_SFSP2_1_EPUN_Msk                                  (0x01UL << SCU_SFSP2_1_EPUN_Pos)                          /*!< SCU SFSP2_1: EPUN Mask              */
#define SCU_SFSP2_1_EHS_Pos                                   5                                                         /*!< SCU SFSP2_1: EHS Position           */
#define SCU_SFSP2_1_EHS_Msk                                   (0x01UL << SCU_SFSP2_1_EHS_Pos)                           /*!< SCU SFSP2_1: EHS Mask               */
#define SCU_SFSP2_1_EZI_Pos                                   6                                                         /*!< SCU SFSP2_1: EZI Position           */
#define SCU_SFSP2_1_EZI_Msk                                   (0x01UL << SCU_SFSP2_1_EZI_Pos)                           /*!< SCU SFSP2_1: EZI Mask               */
#define SCU_SFSP2_1_EHD_Pos                                   8                                                         /*!< SCU SFSP2_1: EHD Position           */
#define SCU_SFSP2_1_EHD_Msk                                   (0x03UL << SCU_SFSP2_1_EHD_Pos)                           /*!< SCU SFSP2_1: EHD Mask               */

// ---------------------------------------  SCU_SFSP2_2  ------------------------------------------
#define SCU_SFSP2_2_MODE_Pos                                  0                                                         /*!< SCU SFSP2_2: MODE Position          */
#define SCU_SFSP2_2_MODE_Msk                                  (0x07UL << SCU_SFSP2_2_MODE_Pos)                          /*!< SCU SFSP2_2: MODE Mask              */
#define SCU_SFSP2_2_EPD_Pos                                   3                                                         /*!< SCU SFSP2_2: EPD Position           */
#define SCU_SFSP2_2_EPD_Msk                                   (0x01UL << SCU_SFSP2_2_EPD_Pos)                           /*!< SCU SFSP2_2: EPD Mask               */
#define SCU_SFSP2_2_EPUN_Pos                                  4                                                         /*!< SCU SFSP2_2: EPUN Position          */
#define SCU_SFSP2_2_EPUN_Msk                                  (0x01UL << SCU_SFSP2_2_EPUN_Pos)                          /*!< SCU SFSP2_2: EPUN Mask              */
#define SCU_SFSP2_2_EHS_Pos                                   5                                                         /*!< SCU SFSP2_2: EHS Position           */
#define SCU_SFSP2_2_EHS_Msk                                   (0x01UL << SCU_SFSP2_2_EHS_Pos)                           /*!< SCU SFSP2_2: EHS Mask               */
#define SCU_SFSP2_2_EZI_Pos                                   6                                                         /*!< SCU SFSP2_2: EZI Position           */
#define SCU_SFSP2_2_EZI_Msk                                   (0x01UL << SCU_SFSP2_2_EZI_Pos)                           /*!< SCU SFSP2_2: EZI Mask               */
#define SCU_SFSP2_2_EHD_Pos                                   8                                                         /*!< SCU SFSP2_2: EHD Position           */
#define SCU_SFSP2_2_EHD_Msk                                   (0x03UL << SCU_SFSP2_2_EHD_Pos)                           /*!< SCU SFSP2_2: EHD Mask               */

// ---------------------------------------  SCU_SFSP2_3  ------------------------------------------
#define SCU_SFSP2_3_MODE_Pos                                  0                                                         /*!< SCU SFSP2_3: MODE Position          */
#define SCU_SFSP2_3_MODE_Msk                                  (0x07UL << SCU_SFSP2_3_MODE_Pos)                          /*!< SCU SFSP2_3: MODE Mask              */
#define SCU_SFSP2_3_EPD_Pos                                   3                                                         /*!< SCU SFSP2_3: EPD Position           */
#define SCU_SFSP2_3_EPD_Msk                                   (0x01UL << SCU_SFSP2_3_EPD_Pos)                           /*!< SCU SFSP2_3: EPD Mask               */
#define SCU_SFSP2_3_EPUN_Pos                                  4                                                         /*!< SCU SFSP2_3: EPUN Position          */
#define SCU_SFSP2_3_EPUN_Msk                                  (0x01UL << SCU_SFSP2_3_EPUN_Pos)                          /*!< SCU SFSP2_3: EPUN Mask              */
#define SCU_SFSP2_3_EHS_Pos                                   5                                                         /*!< SCU SFSP2_3: EHS Position           */
#define SCU_SFSP2_3_EHS_Msk                                   (0x01UL << SCU_SFSP2_3_EHS_Pos)                           /*!< SCU SFSP2_3: EHS Mask               */
#define SCU_SFSP2_3_EZI_Pos                                   6                                                         /*!< SCU SFSP2_3: EZI Position           */
#define SCU_SFSP2_3_EZI_Msk                                   (0x01UL << SCU_SFSP2_3_EZI_Pos)                           /*!< SCU SFSP2_3: EZI Mask               */
#define SCU_SFSP2_3_EHD_Pos                                   8                                                         /*!< SCU SFSP2_3: EHD Position           */
#define SCU_SFSP2_3_EHD_Msk                                   (0x03UL << SCU_SFSP2_3_EHD_Pos)                           /*!< SCU SFSP2_3: EHD Mask               */

// ---------------------------------------  SCU_SFSP2_4  ------------------------------------------
#define SCU_SFSP2_4_MODE_Pos                                  0                                                         /*!< SCU SFSP2_4: MODE Position          */
#define SCU_SFSP2_4_MODE_Msk                                  (0x07UL << SCU_SFSP2_4_MODE_Pos)                          /*!< SCU SFSP2_4: MODE Mask              */
#define SCU_SFSP2_4_EPD_Pos                                   3                                                         /*!< SCU SFSP2_4: EPD Position           */
#define SCU_SFSP2_4_EPD_Msk                                   (0x01UL << SCU_SFSP2_4_EPD_Pos)                           /*!< SCU SFSP2_4: EPD Mask               */
#define SCU_SFSP2_4_EPUN_Pos                                  4                                                         /*!< SCU SFSP2_4: EPUN Position          */
#define SCU_SFSP2_4_EPUN_Msk                                  (0x01UL << SCU_SFSP2_4_EPUN_Pos)                          /*!< SCU SFSP2_4: EPUN Mask              */
#define SCU_SFSP2_4_EHS_Pos                                   5                                                         /*!< SCU SFSP2_4: EHS Position           */
#define SCU_SFSP2_4_EHS_Msk                                   (0x01UL << SCU_SFSP2_4_EHS_Pos)                           /*!< SCU SFSP2_4: EHS Mask               */
#define SCU_SFSP2_4_EZI_Pos                                   6                                                         /*!< SCU SFSP2_4: EZI Position           */
#define SCU_SFSP2_4_EZI_Msk                                   (0x01UL << SCU_SFSP2_4_EZI_Pos)                           /*!< SCU SFSP2_4: EZI Mask               */
#define SCU_SFSP2_4_EHD_Pos                                   8                                                         /*!< SCU SFSP2_4: EHD Position           */
#define SCU_SFSP2_4_EHD_Msk                                   (0x03UL << SCU_SFSP2_4_EHD_Pos)                           /*!< SCU SFSP2_4: EHD Mask               */

// ---------------------------------------  SCU_SFSP2_5  ------------------------------------------
#define SCU_SFSP2_5_MODE_Pos                                  0                                                         /*!< SCU SFSP2_5: MODE Position          */
#define SCU_SFSP2_5_MODE_Msk                                  (0x07UL << SCU_SFSP2_5_MODE_Pos)                          /*!< SCU SFSP2_5: MODE Mask              */
#define SCU_SFSP2_5_EPD_Pos                                   3                                                         /*!< SCU SFSP2_5: EPD Position           */
#define SCU_SFSP2_5_EPD_Msk                                   (0x01UL << SCU_SFSP2_5_EPD_Pos)                           /*!< SCU SFSP2_5: EPD Mask               */
#define SCU_SFSP2_5_EPUN_Pos                                  4                                                         /*!< SCU SFSP2_5: EPUN Position          */
#define SCU_SFSP2_5_EPUN_Msk                                  (0x01UL << SCU_SFSP2_5_EPUN_Pos)                          /*!< SCU SFSP2_5: EPUN Mask              */
#define SCU_SFSP2_5_EHS_Pos                                   5                                                         /*!< SCU SFSP2_5: EHS Position           */
#define SCU_SFSP2_5_EHS_Msk                                   (0x01UL << SCU_SFSP2_5_EHS_Pos)                           /*!< SCU SFSP2_5: EHS Mask               */
#define SCU_SFSP2_5_EZI_Pos                                   6                                                         /*!< SCU SFSP2_5: EZI Position           */
#define SCU_SFSP2_5_EZI_Msk                                   (0x01UL << SCU_SFSP2_5_EZI_Pos)                           /*!< SCU SFSP2_5: EZI Mask               */
#define SCU_SFSP2_5_EHD_Pos                                   8                                                         /*!< SCU SFSP2_5: EHD Position           */
#define SCU_SFSP2_5_EHD_Msk                                   (0x03UL << SCU_SFSP2_5_EHD_Pos)                           /*!< SCU SFSP2_5: EHD Mask               */

// ---------------------------------------  SCU_SFSP2_6  ------------------------------------------
#define SCU_SFSP2_6_MODE_Pos                                  0                                                         /*!< SCU SFSP2_6: MODE Position          */
#define SCU_SFSP2_6_MODE_Msk                                  (0x07UL << SCU_SFSP2_6_MODE_Pos)                          /*!< SCU SFSP2_6: MODE Mask              */
#define SCU_SFSP2_6_EPD_Pos                                   3                                                         /*!< SCU SFSP2_6: EPD Position           */
#define SCU_SFSP2_6_EPD_Msk                                   (0x01UL << SCU_SFSP2_6_EPD_Pos)                           /*!< SCU SFSP2_6: EPD Mask               */
#define SCU_SFSP2_6_EPUN_Pos                                  4                                                         /*!< SCU SFSP2_6: EPUN Position          */
#define SCU_SFSP2_6_EPUN_Msk                                  (0x01UL << SCU_SFSP2_6_EPUN_Pos)                          /*!< SCU SFSP2_6: EPUN Mask              */
#define SCU_SFSP2_6_EHS_Pos                                   5                                                         /*!< SCU SFSP2_6: EHS Position           */
#define SCU_SFSP2_6_EHS_Msk                                   (0x01UL << SCU_SFSP2_6_EHS_Pos)                           /*!< SCU SFSP2_6: EHS Mask               */
#define SCU_SFSP2_6_EZI_Pos                                   6                                                         /*!< SCU SFSP2_6: EZI Position           */
#define SCU_SFSP2_6_EZI_Msk                                   (0x01UL << SCU_SFSP2_6_EZI_Pos)                           /*!< SCU SFSP2_6: EZI Mask               */
#define SCU_SFSP2_6_EHD_Pos                                   8                                                         /*!< SCU SFSP2_6: EHD Position           */
#define SCU_SFSP2_6_EHD_Msk                                   (0x03UL << SCU_SFSP2_6_EHD_Pos)                           /*!< SCU SFSP2_6: EHD Mask               */

// ---------------------------------------  SCU_SFSP2_7  ------------------------------------------
#define SCU_SFSP2_7_MODE_Pos                                  0                                                         /*!< SCU SFSP2_7: MODE Position          */
#define SCU_SFSP2_7_MODE_Msk                                  (0x07UL << SCU_SFSP2_7_MODE_Pos)                          /*!< SCU SFSP2_7: MODE Mask              */
#define SCU_SFSP2_7_EPD_Pos                                   3                                                         /*!< SCU SFSP2_7: EPD Position           */
#define SCU_SFSP2_7_EPD_Msk                                   (0x01UL << SCU_SFSP2_7_EPD_Pos)                           /*!< SCU SFSP2_7: EPD Mask               */
#define SCU_SFSP2_7_EPUN_Pos                                  4                                                         /*!< SCU SFSP2_7: EPUN Position          */
#define SCU_SFSP2_7_EPUN_Msk                                  (0x01UL << SCU_SFSP2_7_EPUN_Pos)                          /*!< SCU SFSP2_7: EPUN Mask              */
#define SCU_SFSP2_7_EHS_Pos                                   5                                                         /*!< SCU SFSP2_7: EHS Position           */
#define SCU_SFSP2_7_EHS_Msk                                   (0x01UL << SCU_SFSP2_7_EHS_Pos)                           /*!< SCU SFSP2_7: EHS Mask               */
#define SCU_SFSP2_7_EZI_Pos                                   6                                                         /*!< SCU SFSP2_7: EZI Position           */
#define SCU_SFSP2_7_EZI_Msk                                   (0x01UL << SCU_SFSP2_7_EZI_Pos)                           /*!< SCU SFSP2_7: EZI Mask               */
#define SCU_SFSP2_7_EHD_Pos                                   8                                                         /*!< SCU SFSP2_7: EHD Position           */
#define SCU_SFSP2_7_EHD_Msk                                   (0x03UL << SCU_SFSP2_7_EHD_Pos)                           /*!< SCU SFSP2_7: EHD Mask               */

// ---------------------------------------  SCU_SFSP2_8  ------------------------------------------
#define SCU_SFSP2_8_MODE_Pos                                  0                                                         /*!< SCU SFSP2_8: MODE Position          */
#define SCU_SFSP2_8_MODE_Msk                                  (0x07UL << SCU_SFSP2_8_MODE_Pos)                          /*!< SCU SFSP2_8: MODE Mask              */
#define SCU_SFSP2_8_EPD_Pos                                   3                                                         /*!< SCU SFSP2_8: EPD Position           */
#define SCU_SFSP2_8_EPD_Msk                                   (0x01UL << SCU_SFSP2_8_EPD_Pos)                           /*!< SCU SFSP2_8: EPD Mask               */
#define SCU_SFSP2_8_EPUN_Pos                                  4                                                         /*!< SCU SFSP2_8: EPUN Position          */
#define SCU_SFSP2_8_EPUN_Msk                                  (0x01UL << SCU_SFSP2_8_EPUN_Pos)                          /*!< SCU SFSP2_8: EPUN Mask              */
#define SCU_SFSP2_8_EHS_Pos                                   5                                                         /*!< SCU SFSP2_8: EHS Position           */
#define SCU_SFSP2_8_EHS_Msk                                   (0x01UL << SCU_SFSP2_8_EHS_Pos)                           /*!< SCU SFSP2_8: EHS Mask               */
#define SCU_SFSP2_8_EZI_Pos                                   6                                                         /*!< SCU SFSP2_8: EZI Position           */
#define SCU_SFSP2_8_EZI_Msk                                   (0x01UL << SCU_SFSP2_8_EZI_Pos)                           /*!< SCU SFSP2_8: EZI Mask               */
#define SCU_SFSP2_8_EHD_Pos                                   8                                                         /*!< SCU SFSP2_8: EHD Position           */
#define SCU_SFSP2_8_EHD_Msk                                   (0x03UL << SCU_SFSP2_8_EHD_Pos)                           /*!< SCU SFSP2_8: EHD Mask               */

// ---------------------------------------  SCU_SFSP2_9  ------------------------------------------
#define SCU_SFSP2_9_MODE_Pos                                  0                                                         /*!< SCU SFSP2_9: MODE Position          */
#define SCU_SFSP2_9_MODE_Msk                                  (0x07UL << SCU_SFSP2_9_MODE_Pos)                          /*!< SCU SFSP2_9: MODE Mask              */
#define SCU_SFSP2_9_EPD_Pos                                   3                                                         /*!< SCU SFSP2_9: EPD Position           */
#define SCU_SFSP2_9_EPD_Msk                                   (0x01UL << SCU_SFSP2_9_EPD_Pos)                           /*!< SCU SFSP2_9: EPD Mask               */
#define SCU_SFSP2_9_EPUN_Pos                                  4                                                         /*!< SCU SFSP2_9: EPUN Position          */
#define SCU_SFSP2_9_EPUN_Msk                                  (0x01UL << SCU_SFSP2_9_EPUN_Pos)                          /*!< SCU SFSP2_9: EPUN Mask              */
#define SCU_SFSP2_9_EHS_Pos                                   5                                                         /*!< SCU SFSP2_9: EHS Position           */
#define SCU_SFSP2_9_EHS_Msk                                   (0x01UL << SCU_SFSP2_9_EHS_Pos)                           /*!< SCU SFSP2_9: EHS Mask               */
#define SCU_SFSP2_9_EZI_Pos                                   6                                                         /*!< SCU SFSP2_9: EZI Position           */
#define SCU_SFSP2_9_EZI_Msk                                   (0x01UL << SCU_SFSP2_9_EZI_Pos)                           /*!< SCU SFSP2_9: EZI Mask               */
#define SCU_SFSP2_9_EHD_Pos                                   8                                                         /*!< SCU SFSP2_9: EHD Position           */
#define SCU_SFSP2_9_EHD_Msk                                   (0x03UL << SCU_SFSP2_9_EHD_Pos)                           /*!< SCU SFSP2_9: EHD Mask               */

// --------------------------------------  SCU_SFSP2_10  ------------------------------------------
#define SCU_SFSP2_10_MODE_Pos                                 0                                                         /*!< SCU SFSP2_10: MODE Position         */
#define SCU_SFSP2_10_MODE_Msk                                 (0x07UL << SCU_SFSP2_10_MODE_Pos)                         /*!< SCU SFSP2_10: MODE Mask             */
#define SCU_SFSP2_10_EPD_Pos                                  3                                                         /*!< SCU SFSP2_10: EPD Position          */
#define SCU_SFSP2_10_EPD_Msk                                  (0x01UL << SCU_SFSP2_10_EPD_Pos)                          /*!< SCU SFSP2_10: EPD Mask              */
#define SCU_SFSP2_10_EPUN_Pos                                 4                                                         /*!< SCU SFSP2_10: EPUN Position         */
#define SCU_SFSP2_10_EPUN_Msk                                 (0x01UL << SCU_SFSP2_10_EPUN_Pos)                         /*!< SCU SFSP2_10: EPUN Mask             */
#define SCU_SFSP2_10_EHS_Pos                                  5                                                         /*!< SCU SFSP2_10: EHS Position          */
#define SCU_SFSP2_10_EHS_Msk                                  (0x01UL << SCU_SFSP2_10_EHS_Pos)                          /*!< SCU SFSP2_10: EHS Mask              */
#define SCU_SFSP2_10_EZI_Pos                                  6                                                         /*!< SCU SFSP2_10: EZI Position          */
#define SCU_SFSP2_10_EZI_Msk                                  (0x01UL << SCU_SFSP2_10_EZI_Pos)                          /*!< SCU SFSP2_10: EZI Mask              */
#define SCU_SFSP2_10_EHD_Pos                                  8                                                         /*!< SCU SFSP2_10: EHD Position          */
#define SCU_SFSP2_10_EHD_Msk                                  (0x03UL << SCU_SFSP2_10_EHD_Pos)                          /*!< SCU SFSP2_10: EHD Mask              */

// --------------------------------------  SCU_SFSP2_11  ------------------------------------------
#define SCU_SFSP2_11_MODE_Pos                                 0                                                         /*!< SCU SFSP2_11: MODE Position         */
#define SCU_SFSP2_11_MODE_Msk                                 (0x07UL << SCU_SFSP2_11_MODE_Pos)                         /*!< SCU SFSP2_11: MODE Mask             */
#define SCU_SFSP2_11_EPD_Pos                                  3                                                         /*!< SCU SFSP2_11: EPD Position          */
#define SCU_SFSP2_11_EPD_Msk                                  (0x01UL << SCU_SFSP2_11_EPD_Pos)                          /*!< SCU SFSP2_11: EPD Mask              */
#define SCU_SFSP2_11_EPUN_Pos                                 4                                                         /*!< SCU SFSP2_11: EPUN Position         */
#define SCU_SFSP2_11_EPUN_Msk                                 (0x01UL << SCU_SFSP2_11_EPUN_Pos)                         /*!< SCU SFSP2_11: EPUN Mask             */
#define SCU_SFSP2_11_EHS_Pos                                  5                                                         /*!< SCU SFSP2_11: EHS Position          */
#define SCU_SFSP2_11_EHS_Msk                                  (0x01UL << SCU_SFSP2_11_EHS_Pos)                          /*!< SCU SFSP2_11: EHS Mask              */
#define SCU_SFSP2_11_EZI_Pos                                  6                                                         /*!< SCU SFSP2_11: EZI Position          */
#define SCU_SFSP2_11_EZI_Msk                                  (0x01UL << SCU_SFSP2_11_EZI_Pos)                          /*!< SCU SFSP2_11: EZI Mask              */
#define SCU_SFSP2_11_EHD_Pos                                  8                                                         /*!< SCU SFSP2_11: EHD Position          */
#define SCU_SFSP2_11_EHD_Msk                                  (0x03UL << SCU_SFSP2_11_EHD_Pos)                          /*!< SCU SFSP2_11: EHD Mask              */

// --------------------------------------  SCU_SFSP2_12  ------------------------------------------
#define SCU_SFSP2_12_MODE_Pos                                 0                                                         /*!< SCU SFSP2_12: MODE Position         */
#define SCU_SFSP2_12_MODE_Msk                                 (0x07UL << SCU_SFSP2_12_MODE_Pos)                         /*!< SCU SFSP2_12: MODE Mask             */
#define SCU_SFSP2_12_EPD_Pos                                  3                                                         /*!< SCU SFSP2_12: EPD Position          */
#define SCU_SFSP2_12_EPD_Msk                                  (0x01UL << SCU_SFSP2_12_EPD_Pos)                          /*!< SCU SFSP2_12: EPD Mask              */
#define SCU_SFSP2_12_EPUN_Pos                                 4                                                         /*!< SCU SFSP2_12: EPUN Position         */
#define SCU_SFSP2_12_EPUN_Msk                                 (0x01UL << SCU_SFSP2_12_EPUN_Pos)                         /*!< SCU SFSP2_12: EPUN Mask             */
#define SCU_SFSP2_12_EHS_Pos                                  5                                                         /*!< SCU SFSP2_12: EHS Position          */
#define SCU_SFSP2_12_EHS_Msk                                  (0x01UL << SCU_SFSP2_12_EHS_Pos)                          /*!< SCU SFSP2_12: EHS Mask              */
#define SCU_SFSP2_12_EZI_Pos                                  6                                                         /*!< SCU SFSP2_12: EZI Position          */
#define SCU_SFSP2_12_EZI_Msk                                  (0x01UL << SCU_SFSP2_12_EZI_Pos)                          /*!< SCU SFSP2_12: EZI Mask              */
#define SCU_SFSP2_12_EHD_Pos                                  8                                                         /*!< SCU SFSP2_12: EHD Position          */
#define SCU_SFSP2_12_EHD_Msk                                  (0x03UL << SCU_SFSP2_12_EHD_Pos)                          /*!< SCU SFSP2_12: EHD Mask              */

// --------------------------------------  SCU_SFSP2_13  ------------------------------------------
#define SCU_SFSP2_13_MODE_Pos                                 0                                                         /*!< SCU SFSP2_13: MODE Position         */
#define SCU_SFSP2_13_MODE_Msk                                 (0x07UL << SCU_SFSP2_13_MODE_Pos)                         /*!< SCU SFSP2_13: MODE Mask             */
#define SCU_SFSP2_13_EPD_Pos                                  3                                                         /*!< SCU SFSP2_13: EPD Position          */
#define SCU_SFSP2_13_EPD_Msk                                  (0x01UL << SCU_SFSP2_13_EPD_Pos)                          /*!< SCU SFSP2_13: EPD Mask              */
#define SCU_SFSP2_13_EPUN_Pos                                 4                                                         /*!< SCU SFSP2_13: EPUN Position         */
#define SCU_SFSP2_13_EPUN_Msk                                 (0x01UL << SCU_SFSP2_13_EPUN_Pos)                         /*!< SCU SFSP2_13: EPUN Mask             */
#define SCU_SFSP2_13_EHS_Pos                                  5                                                         /*!< SCU SFSP2_13: EHS Position          */
#define SCU_SFSP2_13_EHS_Msk                                  (0x01UL << SCU_SFSP2_13_EHS_Pos)                          /*!< SCU SFSP2_13: EHS Mask              */
#define SCU_SFSP2_13_EZI_Pos                                  6                                                         /*!< SCU SFSP2_13: EZI Position          */
#define SCU_SFSP2_13_EZI_Msk                                  (0x01UL << SCU_SFSP2_13_EZI_Pos)                          /*!< SCU SFSP2_13: EZI Mask              */
#define SCU_SFSP2_13_EHD_Pos                                  8                                                         /*!< SCU SFSP2_13: EHD Position          */
#define SCU_SFSP2_13_EHD_Msk                                  (0x03UL << SCU_SFSP2_13_EHD_Pos)                          /*!< SCU SFSP2_13: EHD Mask              */

// ---------------------------------------  SCU_SFSP3_0  ------------------------------------------
#define SCU_SFSP3_0_MODE_Pos                                  0                                                         /*!< SCU SFSP3_0: MODE Position          */
#define SCU_SFSP3_0_MODE_Msk                                  (0x07UL << SCU_SFSP3_0_MODE_Pos)                          /*!< SCU SFSP3_0: MODE Mask              */
#define SCU_SFSP3_0_EPD_Pos                                   3                                                         /*!< SCU SFSP3_0: EPD Position           */
#define SCU_SFSP3_0_EPD_Msk                                   (0x01UL << SCU_SFSP3_0_EPD_Pos)                           /*!< SCU SFSP3_0: EPD Mask               */
#define SCU_SFSP3_0_EPUN_Pos                                  4                                                         /*!< SCU SFSP3_0: EPUN Position          */
#define SCU_SFSP3_0_EPUN_Msk                                  (0x01UL << SCU_SFSP3_0_EPUN_Pos)                          /*!< SCU SFSP3_0: EPUN Mask              */
#define SCU_SFSP3_0_EHS_Pos                                   5                                                         /*!< SCU SFSP3_0: EHS Position           */
#define SCU_SFSP3_0_EHS_Msk                                   (0x01UL << SCU_SFSP3_0_EHS_Pos)                           /*!< SCU SFSP3_0: EHS Mask               */
#define SCU_SFSP3_0_EZI_Pos                                   6                                                         /*!< SCU SFSP3_0: EZI Position           */
#define SCU_SFSP3_0_EZI_Msk                                   (0x01UL << SCU_SFSP3_0_EZI_Pos)                           /*!< SCU SFSP3_0: EZI Mask               */
#define SCU_SFSP3_0_EHD_Pos                                   8                                                         /*!< SCU SFSP3_0: EHD Position           */
#define SCU_SFSP3_0_EHD_Msk                                   (0x03UL << SCU_SFSP3_0_EHD_Pos)                           /*!< SCU SFSP3_0: EHD Mask               */

// ---------------------------------------  SCU_SFSP3_1  ------------------------------------------
#define SCU_SFSP3_1_MODE_Pos                                  0                                                         /*!< SCU SFSP3_1: MODE Position          */
#define SCU_SFSP3_1_MODE_Msk                                  (0x07UL << SCU_SFSP3_1_MODE_Pos)                          /*!< SCU SFSP3_1: MODE Mask              */
#define SCU_SFSP3_1_EPD_Pos                                   3                                                         /*!< SCU SFSP3_1: EPD Position           */
#define SCU_SFSP3_1_EPD_Msk                                   (0x01UL << SCU_SFSP3_1_EPD_Pos)                           /*!< SCU SFSP3_1: EPD Mask               */
#define SCU_SFSP3_1_EPUN_Pos                                  4                                                         /*!< SCU SFSP3_1: EPUN Position          */
#define SCU_SFSP3_1_EPUN_Msk                                  (0x01UL << SCU_SFSP3_1_EPUN_Pos)                          /*!< SCU SFSP3_1: EPUN Mask              */
#define SCU_SFSP3_1_EHS_Pos                                   5                                                         /*!< SCU SFSP3_1: EHS Position           */
#define SCU_SFSP3_1_EHS_Msk                                   (0x01UL << SCU_SFSP3_1_EHS_Pos)                           /*!< SCU SFSP3_1: EHS Mask               */
#define SCU_SFSP3_1_EZI_Pos                                   6                                                         /*!< SCU SFSP3_1: EZI Position           */
#define SCU_SFSP3_1_EZI_Msk                                   (0x01UL << SCU_SFSP3_1_EZI_Pos)                           /*!< SCU SFSP3_1: EZI Mask               */
#define SCU_SFSP3_1_EHD_Pos                                   8                                                         /*!< SCU SFSP3_1: EHD Position           */
#define SCU_SFSP3_1_EHD_Msk                                   (0x03UL << SCU_SFSP3_1_EHD_Pos)                           /*!< SCU SFSP3_1: EHD Mask               */

// ---------------------------------------  SCU_SFSP3_2  ------------------------------------------
#define SCU_SFSP3_2_MODE_Pos                                  0                                                         /*!< SCU SFSP3_2: MODE Position          */
#define SCU_SFSP3_2_MODE_Msk                                  (0x07UL << SCU_SFSP3_2_MODE_Pos)                          /*!< SCU SFSP3_2: MODE Mask              */
#define SCU_SFSP3_2_EPD_Pos                                   3                                                         /*!< SCU SFSP3_2: EPD Position           */
#define SCU_SFSP3_2_EPD_Msk                                   (0x01UL << SCU_SFSP3_2_EPD_Pos)                           /*!< SCU SFSP3_2: EPD Mask               */
#define SCU_SFSP3_2_EPUN_Pos                                  4                                                         /*!< SCU SFSP3_2: EPUN Position          */
#define SCU_SFSP3_2_EPUN_Msk                                  (0x01UL << SCU_SFSP3_2_EPUN_Pos)                          /*!< SCU SFSP3_2: EPUN Mask              */
#define SCU_SFSP3_2_EHS_Pos                                   5                                                         /*!< SCU SFSP3_2: EHS Position           */
#define SCU_SFSP3_2_EHS_Msk                                   (0x01UL << SCU_SFSP3_2_EHS_Pos)                           /*!< SCU SFSP3_2: EHS Mask               */
#define SCU_SFSP3_2_EZI_Pos                                   6                                                         /*!< SCU SFSP3_2: EZI Position           */
#define SCU_SFSP3_2_EZI_Msk                                   (0x01UL << SCU_SFSP3_2_EZI_Pos)                           /*!< SCU SFSP3_2: EZI Mask               */
#define SCU_SFSP3_2_EHD_Pos                                   8                                                         /*!< SCU SFSP3_2: EHD Position           */
#define SCU_SFSP3_2_EHD_Msk                                   (0x03UL << SCU_SFSP3_2_EHD_Pos)                           /*!< SCU SFSP3_2: EHD Mask               */

// ---------------------------------------  SCU_SFSP3_3  ------------------------------------------
#define SCU_SFSP3_3_MODE_Pos                                  0                                                         /*!< SCU SFSP3_3: MODE Position          */
#define SCU_SFSP3_3_MODE_Msk                                  (0x07UL << SCU_SFSP3_3_MODE_Pos)                          /*!< SCU SFSP3_3: MODE Mask              */
#define SCU_SFSP3_3_EPD_Pos                                   3                                                         /*!< SCU SFSP3_3: EPD Position           */
#define SCU_SFSP3_3_EPD_Msk                                   (0x01UL << SCU_SFSP3_3_EPD_Pos)                           /*!< SCU SFSP3_3: EPD Mask               */
#define SCU_SFSP3_3_EPUN_Pos                                  4                                                         /*!< SCU SFSP3_3: EPUN Position          */
#define SCU_SFSP3_3_EPUN_Msk                                  (0x01UL << SCU_SFSP3_3_EPUN_Pos)                          /*!< SCU SFSP3_3: EPUN Mask              */
#define SCU_SFSP3_3_EHS_Pos                                   5                                                         /*!< SCU SFSP3_3: EHS Position           */
#define SCU_SFSP3_3_EHS_Msk                                   (0x01UL << SCU_SFSP3_3_EHS_Pos)                           /*!< SCU SFSP3_3: EHS Mask               */
#define SCU_SFSP3_3_EZI_Pos                                   6                                                         /*!< SCU SFSP3_3: EZI Position           */
#define SCU_SFSP3_3_EZI_Msk                                   (0x01UL << SCU_SFSP3_3_EZI_Pos)                           /*!< SCU SFSP3_3: EZI Mask               */
#define SCU_SFSP3_3_EHD_Pos                                   8                                                         /*!< SCU SFSP3_3: EHD Position           */
#define SCU_SFSP3_3_EHD_Msk                                   (0x03UL << SCU_SFSP3_3_EHD_Pos)                           /*!< SCU SFSP3_3: EHD Mask               */

// ---------------------------------------  SCU_SFSP3_4  ------------------------------------------
#define SCU_SFSP3_4_MODE_Pos                                  0                                                         /*!< SCU SFSP3_4: MODE Position          */
#define SCU_SFSP3_4_MODE_Msk                                  (0x07UL << SCU_SFSP3_4_MODE_Pos)                          /*!< SCU SFSP3_4: MODE Mask              */
#define SCU_SFSP3_4_EPD_Pos                                   3                                                         /*!< SCU SFSP3_4: EPD Position           */
#define SCU_SFSP3_4_EPD_Msk                                   (0x01UL << SCU_SFSP3_4_EPD_Pos)                           /*!< SCU SFSP3_4: EPD Mask               */
#define SCU_SFSP3_4_EPUN_Pos                                  4                                                         /*!< SCU SFSP3_4: EPUN Position          */
#define SCU_SFSP3_4_EPUN_Msk                                  (0x01UL << SCU_SFSP3_4_EPUN_Pos)                          /*!< SCU SFSP3_4: EPUN Mask              */
#define SCU_SFSP3_4_EHS_Pos                                   5                                                         /*!< SCU SFSP3_4: EHS Position           */
#define SCU_SFSP3_4_EHS_Msk                                   (0x01UL << SCU_SFSP3_4_EHS_Pos)                           /*!< SCU SFSP3_4: EHS Mask               */
#define SCU_SFSP3_4_EZI_Pos                                   6                                                         /*!< SCU SFSP3_4: EZI Position           */
#define SCU_SFSP3_4_EZI_Msk                                   (0x01UL << SCU_SFSP3_4_EZI_Pos)                           /*!< SCU SFSP3_4: EZI Mask               */
#define SCU_SFSP3_4_EHD_Pos                                   8                                                         /*!< SCU SFSP3_4: EHD Position           */
#define SCU_SFSP3_4_EHD_Msk                                   (0x03UL << SCU_SFSP3_4_EHD_Pos)                           /*!< SCU SFSP3_4: EHD Mask               */

// ---------------------------------------  SCU_SFSP3_5  ------------------------------------------
#define SCU_SFSP3_5_MODE_Pos                                  0                                                         /*!< SCU SFSP3_5: MODE Position          */
#define SCU_SFSP3_5_MODE_Msk                                  (0x07UL << SCU_SFSP3_5_MODE_Pos)                          /*!< SCU SFSP3_5: MODE Mask              */
#define SCU_SFSP3_5_EPD_Pos                                   3                                                         /*!< SCU SFSP3_5: EPD Position           */
#define SCU_SFSP3_5_EPD_Msk                                   (0x01UL << SCU_SFSP3_5_EPD_Pos)                           /*!< SCU SFSP3_5: EPD Mask               */
#define SCU_SFSP3_5_EPUN_Pos                                  4                                                         /*!< SCU SFSP3_5: EPUN Position          */
#define SCU_SFSP3_5_EPUN_Msk                                  (0x01UL << SCU_SFSP3_5_EPUN_Pos)                          /*!< SCU SFSP3_5: EPUN Mask              */
#define SCU_SFSP3_5_EHS_Pos                                   5                                                         /*!< SCU SFSP3_5: EHS Position           */
#define SCU_SFSP3_5_EHS_Msk                                   (0x01UL << SCU_SFSP3_5_EHS_Pos)                           /*!< SCU SFSP3_5: EHS Mask               */
#define SCU_SFSP3_5_EZI_Pos                                   6                                                         /*!< SCU SFSP3_5: EZI Position           */
#define SCU_SFSP3_5_EZI_Msk                                   (0x01UL << SCU_SFSP3_5_EZI_Pos)                           /*!< SCU SFSP3_5: EZI Mask               */
#define SCU_SFSP3_5_EHD_Pos                                   8                                                         /*!< SCU SFSP3_5: EHD Position           */
#define SCU_SFSP3_5_EHD_Msk                                   (0x03UL << SCU_SFSP3_5_EHD_Pos)                           /*!< SCU SFSP3_5: EHD Mask               */

// ---------------------------------------  SCU_SFSP3_6  ------------------------------------------
#define SCU_SFSP3_6_MODE_Pos                                  0                                                         /*!< SCU SFSP3_6: MODE Position          */
#define SCU_SFSP3_6_MODE_Msk                                  (0x07UL << SCU_SFSP3_6_MODE_Pos)                          /*!< SCU SFSP3_6: MODE Mask              */
#define SCU_SFSP3_6_EPD_Pos                                   3                                                         /*!< SCU SFSP3_6: EPD Position           */
#define SCU_SFSP3_6_EPD_Msk                                   (0x01UL << SCU_SFSP3_6_EPD_Pos)                           /*!< SCU SFSP3_6: EPD Mask               */
#define SCU_SFSP3_6_EPUN_Pos                                  4                                                         /*!< SCU SFSP3_6: EPUN Position          */
#define SCU_SFSP3_6_EPUN_Msk                                  (0x01UL << SCU_SFSP3_6_EPUN_Pos)                          /*!< SCU SFSP3_6: EPUN Mask              */
#define SCU_SFSP3_6_EHS_Pos                                   5                                                         /*!< SCU SFSP3_6: EHS Position           */
#define SCU_SFSP3_6_EHS_Msk                                   (0x01UL << SCU_SFSP3_6_EHS_Pos)                           /*!< SCU SFSP3_6: EHS Mask               */
#define SCU_SFSP3_6_EZI_Pos                                   6                                                         /*!< SCU SFSP3_6: EZI Position           */
#define SCU_SFSP3_6_EZI_Msk                                   (0x01UL << SCU_SFSP3_6_EZI_Pos)                           /*!< SCU SFSP3_6: EZI Mask               */
#define SCU_SFSP3_6_EHD_Pos                                   8                                                         /*!< SCU SFSP3_6: EHD Position           */
#define SCU_SFSP3_6_EHD_Msk                                   (0x03UL << SCU_SFSP3_6_EHD_Pos)                           /*!< SCU SFSP3_6: EHD Mask               */

// ---------------------------------------  SCU_SFSP3_7  ------------------------------------------
#define SCU_SFSP3_7_MODE_Pos                                  0                                                         /*!< SCU SFSP3_7: MODE Position          */
#define SCU_SFSP3_7_MODE_Msk                                  (0x07UL << SCU_SFSP3_7_MODE_Pos)                          /*!< SCU SFSP3_7: MODE Mask              */
#define SCU_SFSP3_7_EPD_Pos                                   3                                                         /*!< SCU SFSP3_7: EPD Position           */
#define SCU_SFSP3_7_EPD_Msk                                   (0x01UL << SCU_SFSP3_7_EPD_Pos)                           /*!< SCU SFSP3_7: EPD Mask               */
#define SCU_SFSP3_7_EPUN_Pos                                  4                                                         /*!< SCU SFSP3_7: EPUN Position          */
#define SCU_SFSP3_7_EPUN_Msk                                  (0x01UL << SCU_SFSP3_7_EPUN_Pos)                          /*!< SCU SFSP3_7: EPUN Mask              */
#define SCU_SFSP3_7_EHS_Pos                                   5                                                         /*!< SCU SFSP3_7: EHS Position           */
#define SCU_SFSP3_7_EHS_Msk                                   (0x01UL << SCU_SFSP3_7_EHS_Pos)                           /*!< SCU SFSP3_7: EHS Mask               */
#define SCU_SFSP3_7_EZI_Pos                                   6                                                         /*!< SCU SFSP3_7: EZI Position           */
#define SCU_SFSP3_7_EZI_Msk                                   (0x01UL << SCU_SFSP3_7_EZI_Pos)                           /*!< SCU SFSP3_7: EZI Mask               */
#define SCU_SFSP3_7_EHD_Pos                                   8                                                         /*!< SCU SFSP3_7: EHD Position           */
#define SCU_SFSP3_7_EHD_Msk                                   (0x03UL << SCU_SFSP3_7_EHD_Pos)                           /*!< SCU SFSP3_7: EHD Mask               */

// ---------------------------------------  SCU_SFSP3_8  ------------------------------------------
#define SCU_SFSP3_8_MODE_Pos                                  0                                                         /*!< SCU SFSP3_8: MODE Position          */
#define SCU_SFSP3_8_MODE_Msk                                  (0x07UL << SCU_SFSP3_8_MODE_Pos)                          /*!< SCU SFSP3_8: MODE Mask              */
#define SCU_SFSP3_8_EPD_Pos                                   3                                                         /*!< SCU SFSP3_8: EPD Position           */
#define SCU_SFSP3_8_EPD_Msk                                   (0x01UL << SCU_SFSP3_8_EPD_Pos)                           /*!< SCU SFSP3_8: EPD Mask               */
#define SCU_SFSP3_8_EPUN_Pos                                  4                                                         /*!< SCU SFSP3_8: EPUN Position          */
#define SCU_SFSP3_8_EPUN_Msk                                  (0x01UL << SCU_SFSP3_8_EPUN_Pos)                          /*!< SCU SFSP3_8: EPUN Mask              */
#define SCU_SFSP3_8_EHS_Pos                                   5                                                         /*!< SCU SFSP3_8: EHS Position           */
#define SCU_SFSP3_8_EHS_Msk                                   (0x01UL << SCU_SFSP3_8_EHS_Pos)                           /*!< SCU SFSP3_8: EHS Mask               */
#define SCU_SFSP3_8_EZI_Pos                                   6                                                         /*!< SCU SFSP3_8: EZI Position           */
#define SCU_SFSP3_8_EZI_Msk                                   (0x01UL << SCU_SFSP3_8_EZI_Pos)                           /*!< SCU SFSP3_8: EZI Mask               */
#define SCU_SFSP3_8_EHD_Pos                                   8                                                         /*!< SCU SFSP3_8: EHD Position           */
#define SCU_SFSP3_8_EHD_Msk                                   (0x03UL << SCU_SFSP3_8_EHD_Pos)                           /*!< SCU SFSP3_8: EHD Mask               */

// ---------------------------------------  SCU_SFSP4_0  ------------------------------------------
#define SCU_SFSP4_0_MODE_Pos                                  0                                                         /*!< SCU SFSP4_0: MODE Position          */
#define SCU_SFSP4_0_MODE_Msk                                  (0x07UL << SCU_SFSP4_0_MODE_Pos)                          /*!< SCU SFSP4_0: MODE Mask              */
#define SCU_SFSP4_0_EPD_Pos                                   3                                                         /*!< SCU SFSP4_0: EPD Position           */
#define SCU_SFSP4_0_EPD_Msk                                   (0x01UL << SCU_SFSP4_0_EPD_Pos)                           /*!< SCU SFSP4_0: EPD Mask               */
#define SCU_SFSP4_0_EPUN_Pos                                  4                                                         /*!< SCU SFSP4_0: EPUN Position          */
#define SCU_SFSP4_0_EPUN_Msk                                  (0x01UL << SCU_SFSP4_0_EPUN_Pos)                          /*!< SCU SFSP4_0: EPUN Mask              */
#define SCU_SFSP4_0_EHS_Pos                                   5                                                         /*!< SCU SFSP4_0: EHS Position           */
#define SCU_SFSP4_0_EHS_Msk                                   (0x01UL << SCU_SFSP4_0_EHS_Pos)                           /*!< SCU SFSP4_0: EHS Mask               */
#define SCU_SFSP4_0_EZI_Pos                                   6                                                         /*!< SCU SFSP4_0: EZI Position           */
#define SCU_SFSP4_0_EZI_Msk                                   (0x01UL << SCU_SFSP4_0_EZI_Pos)                           /*!< SCU SFSP4_0: EZI Mask               */
#define SCU_SFSP4_0_EHD_Pos                                   8                                                         /*!< SCU SFSP4_0: EHD Position           */
#define SCU_SFSP4_0_EHD_Msk                                   (0x03UL << SCU_SFSP4_0_EHD_Pos)                           /*!< SCU SFSP4_0: EHD Mask               */

// ---------------------------------------  SCU_SFSP4_1  ------------------------------------------
#define SCU_SFSP4_1_MODE_Pos                                  0                                                         /*!< SCU SFSP4_1: MODE Position          */
#define SCU_SFSP4_1_MODE_Msk                                  (0x07UL << SCU_SFSP4_1_MODE_Pos)                          /*!< SCU SFSP4_1: MODE Mask              */
#define SCU_SFSP4_1_EPD_Pos                                   3                                                         /*!< SCU SFSP4_1: EPD Position           */
#define SCU_SFSP4_1_EPD_Msk                                   (0x01UL << SCU_SFSP4_1_EPD_Pos)                           /*!< SCU SFSP4_1: EPD Mask               */
#define SCU_SFSP4_1_EPUN_Pos                                  4                                                         /*!< SCU SFSP4_1: EPUN Position          */
#define SCU_SFSP4_1_EPUN_Msk                                  (0x01UL << SCU_SFSP4_1_EPUN_Pos)                          /*!< SCU SFSP4_1: EPUN Mask              */
#define SCU_SFSP4_1_EHS_Pos                                   5                                                         /*!< SCU SFSP4_1: EHS Position           */
#define SCU_SFSP4_1_EHS_Msk                                   (0x01UL << SCU_SFSP4_1_EHS_Pos)                           /*!< SCU SFSP4_1: EHS Mask               */
#define SCU_SFSP4_1_EZI_Pos                                   6                                                         /*!< SCU SFSP4_1: EZI Position           */
#define SCU_SFSP4_1_EZI_Msk                                   (0x01UL << SCU_SFSP4_1_EZI_Pos)                           /*!< SCU SFSP4_1: EZI Mask               */
#define SCU_SFSP4_1_EHD_Pos                                   8                                                         /*!< SCU SFSP4_1: EHD Position           */
#define SCU_SFSP4_1_EHD_Msk                                   (0x03UL << SCU_SFSP4_1_EHD_Pos)                           /*!< SCU SFSP4_1: EHD Mask               */

// ---------------------------------------  SCU_SFSP4_2  ------------------------------------------
#define SCU_SFSP4_2_MODE_Pos                                  0                                                         /*!< SCU SFSP4_2: MODE Position          */
#define SCU_SFSP4_2_MODE_Msk                                  (0x07UL << SCU_SFSP4_2_MODE_Pos)                          /*!< SCU SFSP4_2: MODE Mask              */
#define SCU_SFSP4_2_EPD_Pos                                   3                                                         /*!< SCU SFSP4_2: EPD Position           */
#define SCU_SFSP4_2_EPD_Msk                                   (0x01UL << SCU_SFSP4_2_EPD_Pos)                           /*!< SCU SFSP4_2: EPD Mask               */
#define SCU_SFSP4_2_EPUN_Pos                                  4                                                         /*!< SCU SFSP4_2: EPUN Position          */
#define SCU_SFSP4_2_EPUN_Msk                                  (0x01UL << SCU_SFSP4_2_EPUN_Pos)                          /*!< SCU SFSP4_2: EPUN Mask              */
#define SCU_SFSP4_2_EHS_Pos                                   5                                                         /*!< SCU SFSP4_2: EHS Position           */
#define SCU_SFSP4_2_EHS_Msk                                   (0x01UL << SCU_SFSP4_2_EHS_Pos)                           /*!< SCU SFSP4_2: EHS Mask               */
#define SCU_SFSP4_2_EZI_Pos                                   6                                                         /*!< SCU SFSP4_2: EZI Position           */
#define SCU_SFSP4_2_EZI_Msk                                   (0x01UL << SCU_SFSP4_2_EZI_Pos)                           /*!< SCU SFSP4_2: EZI Mask               */
#define SCU_SFSP4_2_EHD_Pos                                   8                                                         /*!< SCU SFSP4_2: EHD Position           */
#define SCU_SFSP4_2_EHD_Msk                                   (0x03UL << SCU_SFSP4_2_EHD_Pos)                           /*!< SCU SFSP4_2: EHD Mask               */

// ---------------------------------------  SCU_SFSP4_3  ------------------------------------------
#define SCU_SFSP4_3_MODE_Pos                                  0                                                         /*!< SCU SFSP4_3: MODE Position          */
#define SCU_SFSP4_3_MODE_Msk                                  (0x07UL << SCU_SFSP4_3_MODE_Pos)                          /*!< SCU SFSP4_3: MODE Mask              */
#define SCU_SFSP4_3_EPD_Pos                                   3                                                         /*!< SCU SFSP4_3: EPD Position           */
#define SCU_SFSP4_3_EPD_Msk                                   (0x01UL << SCU_SFSP4_3_EPD_Pos)                           /*!< SCU SFSP4_3: EPD Mask               */
#define SCU_SFSP4_3_EPUN_Pos                                  4                                                         /*!< SCU SFSP4_3: EPUN Position          */
#define SCU_SFSP4_3_EPUN_Msk                                  (0x01UL << SCU_SFSP4_3_EPUN_Pos)                          /*!< SCU SFSP4_3: EPUN Mask              */
#define SCU_SFSP4_3_EHS_Pos                                   5                                                         /*!< SCU SFSP4_3: EHS Position           */
#define SCU_SFSP4_3_EHS_Msk                                   (0x01UL << SCU_SFSP4_3_EHS_Pos)                           /*!< SCU SFSP4_3: EHS Mask               */
#define SCU_SFSP4_3_EZI_Pos                                   6                                                         /*!< SCU SFSP4_3: EZI Position           */
#define SCU_SFSP4_3_EZI_Msk                                   (0x01UL << SCU_SFSP4_3_EZI_Pos)                           /*!< SCU SFSP4_3: EZI Mask               */
#define SCU_SFSP4_3_EHD_Pos                                   8                                                         /*!< SCU SFSP4_3: EHD Position           */
#define SCU_SFSP4_3_EHD_Msk                                   (0x03UL << SCU_SFSP4_3_EHD_Pos)                           /*!< SCU SFSP4_3: EHD Mask               */

// ---------------------------------------  SCU_SFSP4_4  ------------------------------------------
#define SCU_SFSP4_4_MODE_Pos                                  0                                                         /*!< SCU SFSP4_4: MODE Position          */
#define SCU_SFSP4_4_MODE_Msk                                  (0x07UL << SCU_SFSP4_4_MODE_Pos)                          /*!< SCU SFSP4_4: MODE Mask              */
#define SCU_SFSP4_4_EPD_Pos                                   3                                                         /*!< SCU SFSP4_4: EPD Position           */
#define SCU_SFSP4_4_EPD_Msk                                   (0x01UL << SCU_SFSP4_4_EPD_Pos)                           /*!< SCU SFSP4_4: EPD Mask               */
#define SCU_SFSP4_4_EPUN_Pos                                  4                                                         /*!< SCU SFSP4_4: EPUN Position          */
#define SCU_SFSP4_4_EPUN_Msk                                  (0x01UL << SCU_SFSP4_4_EPUN_Pos)                          /*!< SCU SFSP4_4: EPUN Mask              */
#define SCU_SFSP4_4_EHS_Pos                                   5                                                         /*!< SCU SFSP4_4: EHS Position           */
#define SCU_SFSP4_4_EHS_Msk                                   (0x01UL << SCU_SFSP4_4_EHS_Pos)                           /*!< SCU SFSP4_4: EHS Mask               */
#define SCU_SFSP4_4_EZI_Pos                                   6                                                         /*!< SCU SFSP4_4: EZI Position           */
#define SCU_SFSP4_4_EZI_Msk                                   (0x01UL << SCU_SFSP4_4_EZI_Pos)                           /*!< SCU SFSP4_4: EZI Mask               */
#define SCU_SFSP4_4_EHD_Pos                                   8                                                         /*!< SCU SFSP4_4: EHD Position           */
#define SCU_SFSP4_4_EHD_Msk                                   (0x03UL << SCU_SFSP4_4_EHD_Pos)                           /*!< SCU SFSP4_4: EHD Mask               */

// ---------------------------------------  SCU_SFSP4_5  ------------------------------------------
#define SCU_SFSP4_5_MODE_Pos                                  0                                                         /*!< SCU SFSP4_5: MODE Position          */
#define SCU_SFSP4_5_MODE_Msk                                  (0x07UL << SCU_SFSP4_5_MODE_Pos)                          /*!< SCU SFSP4_5: MODE Mask              */
#define SCU_SFSP4_5_EPD_Pos                                   3                                                         /*!< SCU SFSP4_5: EPD Position           */
#define SCU_SFSP4_5_EPD_Msk                                   (0x01UL << SCU_SFSP4_5_EPD_Pos)                           /*!< SCU SFSP4_5: EPD Mask               */
#define SCU_SFSP4_5_EPUN_Pos                                  4                                                         /*!< SCU SFSP4_5: EPUN Position          */
#define SCU_SFSP4_5_EPUN_Msk                                  (0x01UL << SCU_SFSP4_5_EPUN_Pos)                          /*!< SCU SFSP4_5: EPUN Mask              */
#define SCU_SFSP4_5_EHS_Pos                                   5                                                         /*!< SCU SFSP4_5: EHS Position           */
#define SCU_SFSP4_5_EHS_Msk                                   (0x01UL << SCU_SFSP4_5_EHS_Pos)                           /*!< SCU SFSP4_5: EHS Mask               */
#define SCU_SFSP4_5_EZI_Pos                                   6                                                         /*!< SCU SFSP4_5: EZI Position           */
#define SCU_SFSP4_5_EZI_Msk                                   (0x01UL << SCU_SFSP4_5_EZI_Pos)                           /*!< SCU SFSP4_5: EZI Mask               */
#define SCU_SFSP4_5_EHD_Pos                                   8                                                         /*!< SCU SFSP4_5: EHD Position           */
#define SCU_SFSP4_5_EHD_Msk                                   (0x03UL << SCU_SFSP4_5_EHD_Pos)                           /*!< SCU SFSP4_5: EHD Mask               */

// ---------------------------------------  SCU_SFSP4_6  ------------------------------------------
#define SCU_SFSP4_6_MODE_Pos                                  0                                                         /*!< SCU SFSP4_6: MODE Position          */
#define SCU_SFSP4_6_MODE_Msk                                  (0x07UL << SCU_SFSP4_6_MODE_Pos)                          /*!< SCU SFSP4_6: MODE Mask              */
#define SCU_SFSP4_6_EPD_Pos                                   3                                                         /*!< SCU SFSP4_6: EPD Position           */
#define SCU_SFSP4_6_EPD_Msk                                   (0x01UL << SCU_SFSP4_6_EPD_Pos)                           /*!< SCU SFSP4_6: EPD Mask               */
#define SCU_SFSP4_6_EPUN_Pos                                  4                                                         /*!< SCU SFSP4_6: EPUN Position          */
#define SCU_SFSP4_6_EPUN_Msk                                  (0x01UL << SCU_SFSP4_6_EPUN_Pos)                          /*!< SCU SFSP4_6: EPUN Mask              */
#define SCU_SFSP4_6_EHS_Pos                                   5                                                         /*!< SCU SFSP4_6: EHS Position           */
#define SCU_SFSP4_6_EHS_Msk                                   (0x01UL << SCU_SFSP4_6_EHS_Pos)                           /*!< SCU SFSP4_6: EHS Mask               */
#define SCU_SFSP4_6_EZI_Pos                                   6                                                         /*!< SCU SFSP4_6: EZI Position           */
#define SCU_SFSP4_6_EZI_Msk                                   (0x01UL << SCU_SFSP4_6_EZI_Pos)                           /*!< SCU SFSP4_6: EZI Mask               */
#define SCU_SFSP4_6_EHD_Pos                                   8                                                         /*!< SCU SFSP4_6: EHD Position           */
#define SCU_SFSP4_6_EHD_Msk                                   (0x03UL << SCU_SFSP4_6_EHD_Pos)                           /*!< SCU SFSP4_6: EHD Mask               */

// ---------------------------------------  SCU_SFSP4_7  ------------------------------------------
#define SCU_SFSP4_7_MODE_Pos                                  0                                                         /*!< SCU SFSP4_7: MODE Position          */
#define SCU_SFSP4_7_MODE_Msk                                  (0x07UL << SCU_SFSP4_7_MODE_Pos)                          /*!< SCU SFSP4_7: MODE Mask              */
#define SCU_SFSP4_7_EPD_Pos                                   3                                                         /*!< SCU SFSP4_7: EPD Position           */
#define SCU_SFSP4_7_EPD_Msk                                   (0x01UL << SCU_SFSP4_7_EPD_Pos)                           /*!< SCU SFSP4_7: EPD Mask               */
#define SCU_SFSP4_7_EPUN_Pos                                  4                                                         /*!< SCU SFSP4_7: EPUN Position          */
#define SCU_SFSP4_7_EPUN_Msk                                  (0x01UL << SCU_SFSP4_7_EPUN_Pos)                          /*!< SCU SFSP4_7: EPUN Mask              */
#define SCU_SFSP4_7_EHS_Pos                                   5                                                         /*!< SCU SFSP4_7: EHS Position           */
#define SCU_SFSP4_7_EHS_Msk                                   (0x01UL << SCU_SFSP4_7_EHS_Pos)                           /*!< SCU SFSP4_7: EHS Mask               */
#define SCU_SFSP4_7_EZI_Pos                                   6                                                         /*!< SCU SFSP4_7: EZI Position           */
#define SCU_SFSP4_7_EZI_Msk                                   (0x01UL << SCU_SFSP4_7_EZI_Pos)                           /*!< SCU SFSP4_7: EZI Mask               */
#define SCU_SFSP4_7_EHD_Pos                                   8                                                         /*!< SCU SFSP4_7: EHD Position           */
#define SCU_SFSP4_7_EHD_Msk                                   (0x03UL << SCU_SFSP4_7_EHD_Pos)                           /*!< SCU SFSP4_7: EHD Mask               */

// ---------------------------------------  SCU_SFSP4_8  ------------------------------------------
#define SCU_SFSP4_8_MODE_Pos                                  0                                                         /*!< SCU SFSP4_8: MODE Position          */
#define SCU_SFSP4_8_MODE_Msk                                  (0x07UL << SCU_SFSP4_8_MODE_Pos)                          /*!< SCU SFSP4_8: MODE Mask              */
#define SCU_SFSP4_8_EPD_Pos                                   3                                                         /*!< SCU SFSP4_8: EPD Position           */
#define SCU_SFSP4_8_EPD_Msk                                   (0x01UL << SCU_SFSP4_8_EPD_Pos)                           /*!< SCU SFSP4_8: EPD Mask               */
#define SCU_SFSP4_8_EPUN_Pos                                  4                                                         /*!< SCU SFSP4_8: EPUN Position          */
#define SCU_SFSP4_8_EPUN_Msk                                  (0x01UL << SCU_SFSP4_8_EPUN_Pos)                          /*!< SCU SFSP4_8: EPUN Mask              */
#define SCU_SFSP4_8_EHS_Pos                                   5                                                         /*!< SCU SFSP4_8: EHS Position           */
#define SCU_SFSP4_8_EHS_Msk                                   (0x01UL << SCU_SFSP4_8_EHS_Pos)                           /*!< SCU SFSP4_8: EHS Mask               */
#define SCU_SFSP4_8_EZI_Pos                                   6                                                         /*!< SCU SFSP4_8: EZI Position           */
#define SCU_SFSP4_8_EZI_Msk                                   (0x01UL << SCU_SFSP4_8_EZI_Pos)                           /*!< SCU SFSP4_8: EZI Mask               */
#define SCU_SFSP4_8_EHD_Pos                                   8                                                         /*!< SCU SFSP4_8: EHD Position           */
#define SCU_SFSP4_8_EHD_Msk                                   (0x03UL << SCU_SFSP4_8_EHD_Pos)                           /*!< SCU SFSP4_8: EHD Mask               */

// ---------------------------------------  SCU_SFSP4_9  ------------------------------------------
#define SCU_SFSP4_9_MODE_Pos                                  0                                                         /*!< SCU SFSP4_9: MODE Position          */
#define SCU_SFSP4_9_MODE_Msk                                  (0x07UL << SCU_SFSP4_9_MODE_Pos)                          /*!< SCU SFSP4_9: MODE Mask              */
#define SCU_SFSP4_9_EPD_Pos                                   3                                                         /*!< SCU SFSP4_9: EPD Position           */
#define SCU_SFSP4_9_EPD_Msk                                   (0x01UL << SCU_SFSP4_9_EPD_Pos)                           /*!< SCU SFSP4_9: EPD Mask               */
#define SCU_SFSP4_9_EPUN_Pos                                  4                                                         /*!< SCU SFSP4_9: EPUN Position          */
#define SCU_SFSP4_9_EPUN_Msk                                  (0x01UL << SCU_SFSP4_9_EPUN_Pos)                          /*!< SCU SFSP4_9: EPUN Mask              */
#define SCU_SFSP4_9_EHS_Pos                                   5                                                         /*!< SCU SFSP4_9: EHS Position           */
#define SCU_SFSP4_9_EHS_Msk                                   (0x01UL << SCU_SFSP4_9_EHS_Pos)                           /*!< SCU SFSP4_9: EHS Mask               */
#define SCU_SFSP4_9_EZI_Pos                                   6                                                         /*!< SCU SFSP4_9: EZI Position           */
#define SCU_SFSP4_9_EZI_Msk                                   (0x01UL << SCU_SFSP4_9_EZI_Pos)                           /*!< SCU SFSP4_9: EZI Mask               */
#define SCU_SFSP4_9_EHD_Pos                                   8                                                         /*!< SCU SFSP4_9: EHD Position           */
#define SCU_SFSP4_9_EHD_Msk                                   (0x03UL << SCU_SFSP4_9_EHD_Pos)                           /*!< SCU SFSP4_9: EHD Mask               */

// --------------------------------------  SCU_SFSP4_10  ------------------------------------------
#define SCU_SFSP4_10_MODE_Pos                                 0                                                         /*!< SCU SFSP4_10: MODE Position         */
#define SCU_SFSP4_10_MODE_Msk                                 (0x07UL << SCU_SFSP4_10_MODE_Pos)                         /*!< SCU SFSP4_10: MODE Mask             */
#define SCU_SFSP4_10_EPD_Pos                                  3                                                         /*!< SCU SFSP4_10: EPD Position          */
#define SCU_SFSP4_10_EPD_Msk                                  (0x01UL << SCU_SFSP4_10_EPD_Pos)                          /*!< SCU SFSP4_10: EPD Mask              */
#define SCU_SFSP4_10_EPUN_Pos                                 4                                                         /*!< SCU SFSP4_10: EPUN Position         */
#define SCU_SFSP4_10_EPUN_Msk                                 (0x01UL << SCU_SFSP4_10_EPUN_Pos)                         /*!< SCU SFSP4_10: EPUN Mask             */
#define SCU_SFSP4_10_EHS_Pos                                  5                                                         /*!< SCU SFSP4_10: EHS Position          */
#define SCU_SFSP4_10_EHS_Msk                                  (0x01UL << SCU_SFSP4_10_EHS_Pos)                          /*!< SCU SFSP4_10: EHS Mask              */
#define SCU_SFSP4_10_EZI_Pos                                  6                                                         /*!< SCU SFSP4_10: EZI Position          */
#define SCU_SFSP4_10_EZI_Msk                                  (0x01UL << SCU_SFSP4_10_EZI_Pos)                          /*!< SCU SFSP4_10: EZI Mask              */
#define SCU_SFSP4_10_EHD_Pos                                  8                                                         /*!< SCU SFSP4_10: EHD Position          */
#define SCU_SFSP4_10_EHD_Msk                                  (0x03UL << SCU_SFSP4_10_EHD_Pos)                          /*!< SCU SFSP4_10: EHD Mask              */

// ---------------------------------------  SCU_SFSP5_0  ------------------------------------------
#define SCU_SFSP5_0_MODE_Pos                                  0                                                         /*!< SCU SFSP5_0: MODE Position          */
#define SCU_SFSP5_0_MODE_Msk                                  (0x07UL << SCU_SFSP5_0_MODE_Pos)                          /*!< SCU SFSP5_0: MODE Mask              */
#define SCU_SFSP5_0_EPD_Pos                                   3                                                         /*!< SCU SFSP5_0: EPD Position           */
#define SCU_SFSP5_0_EPD_Msk                                   (0x01UL << SCU_SFSP5_0_EPD_Pos)                           /*!< SCU SFSP5_0: EPD Mask               */
#define SCU_SFSP5_0_EPUN_Pos                                  4                                                         /*!< SCU SFSP5_0: EPUN Position          */
#define SCU_SFSP5_0_EPUN_Msk                                  (0x01UL << SCU_SFSP5_0_EPUN_Pos)                          /*!< SCU SFSP5_0: EPUN Mask              */
#define SCU_SFSP5_0_EHS_Pos                                   5                                                         /*!< SCU SFSP5_0: EHS Position           */
#define SCU_SFSP5_0_EHS_Msk                                   (0x01UL << SCU_SFSP5_0_EHS_Pos)                           /*!< SCU SFSP5_0: EHS Mask               */
#define SCU_SFSP5_0_EZI_Pos                                   6                                                         /*!< SCU SFSP5_0: EZI Position           */
#define SCU_SFSP5_0_EZI_Msk                                   (0x01UL << SCU_SFSP5_0_EZI_Pos)                           /*!< SCU SFSP5_0: EZI Mask               */
#define SCU_SFSP5_0_EHD_Pos                                   8                                                         /*!< SCU SFSP5_0: EHD Position           */
#define SCU_SFSP5_0_EHD_Msk                                   (0x03UL << SCU_SFSP5_0_EHD_Pos)                           /*!< SCU SFSP5_0: EHD Mask               */

// ---------------------------------------  SCU_SFSP5_1  ------------------------------------------
#define SCU_SFSP5_1_MODE_Pos                                  0                                                         /*!< SCU SFSP5_1: MODE Position          */
#define SCU_SFSP5_1_MODE_Msk                                  (0x07UL << SCU_SFSP5_1_MODE_Pos)                          /*!< SCU SFSP5_1: MODE Mask              */
#define SCU_SFSP5_1_EPD_Pos                                   3                                                         /*!< SCU SFSP5_1: EPD Position           */
#define SCU_SFSP5_1_EPD_Msk                                   (0x01UL << SCU_SFSP5_1_EPD_Pos)                           /*!< SCU SFSP5_1: EPD Mask               */
#define SCU_SFSP5_1_EPUN_Pos                                  4                                                         /*!< SCU SFSP5_1: EPUN Position          */
#define SCU_SFSP5_1_EPUN_Msk                                  (0x01UL << SCU_SFSP5_1_EPUN_Pos)                          /*!< SCU SFSP5_1: EPUN Mask              */
#define SCU_SFSP5_1_EHS_Pos                                   5                                                         /*!< SCU SFSP5_1: EHS Position           */
#define SCU_SFSP5_1_EHS_Msk                                   (0x01UL << SCU_SFSP5_1_EHS_Pos)                           /*!< SCU SFSP5_1: EHS Mask               */
#define SCU_SFSP5_1_EZI_Pos                                   6                                                         /*!< SCU SFSP5_1: EZI Position           */
#define SCU_SFSP5_1_EZI_Msk                                   (0x01UL << SCU_SFSP5_1_EZI_Pos)                           /*!< SCU SFSP5_1: EZI Mask               */
#define SCU_SFSP5_1_EHD_Pos                                   8                                                         /*!< SCU SFSP5_1: EHD Position           */
#define SCU_SFSP5_1_EHD_Msk                                   (0x03UL << SCU_SFSP5_1_EHD_Pos)                           /*!< SCU SFSP5_1: EHD Mask               */

// ---------------------------------------  SCU_SFSP5_2  ------------------------------------------
#define SCU_SFSP5_2_MODE_Pos                                  0                                                         /*!< SCU SFSP5_2: MODE Position          */
#define SCU_SFSP5_2_MODE_Msk                                  (0x07UL << SCU_SFSP5_2_MODE_Pos)                          /*!< SCU SFSP5_2: MODE Mask              */
#define SCU_SFSP5_2_EPD_Pos                                   3                                                         /*!< SCU SFSP5_2: EPD Position           */
#define SCU_SFSP5_2_EPD_Msk                                   (0x01UL << SCU_SFSP5_2_EPD_Pos)                           /*!< SCU SFSP5_2: EPD Mask               */
#define SCU_SFSP5_2_EPUN_Pos                                  4                                                         /*!< SCU SFSP5_2: EPUN Position          */
#define SCU_SFSP5_2_EPUN_Msk                                  (0x01UL << SCU_SFSP5_2_EPUN_Pos)                          /*!< SCU SFSP5_2: EPUN Mask              */
#define SCU_SFSP5_2_EHS_Pos                                   5                                                         /*!< SCU SFSP5_2: EHS Position           */
#define SCU_SFSP5_2_EHS_Msk                                   (0x01UL << SCU_SFSP5_2_EHS_Pos)                           /*!< SCU SFSP5_2: EHS Mask               */
#define SCU_SFSP5_2_EZI_Pos                                   6                                                         /*!< SCU SFSP5_2: EZI Position           */
#define SCU_SFSP5_2_EZI_Msk                                   (0x01UL << SCU_SFSP5_2_EZI_Pos)                           /*!< SCU SFSP5_2: EZI Mask               */
#define SCU_SFSP5_2_EHD_Pos                                   8                                                         /*!< SCU SFSP5_2: EHD Position           */
#define SCU_SFSP5_2_EHD_Msk                                   (0x03UL << SCU_SFSP5_2_EHD_Pos)                           /*!< SCU SFSP5_2: EHD Mask               */

// ---------------------------------------  SCU_SFSP5_3  ------------------------------------------
#define SCU_SFSP5_3_MODE_Pos                                  0                                                         /*!< SCU SFSP5_3: MODE Position          */
#define SCU_SFSP5_3_MODE_Msk                                  (0x07UL << SCU_SFSP5_3_MODE_Pos)                          /*!< SCU SFSP5_3: MODE Mask              */
#define SCU_SFSP5_3_EPD_Pos                                   3                                                         /*!< SCU SFSP5_3: EPD Position           */
#define SCU_SFSP5_3_EPD_Msk                                   (0x01UL << SCU_SFSP5_3_EPD_Pos)                           /*!< SCU SFSP5_3: EPD Mask               */
#define SCU_SFSP5_3_EPUN_Pos                                  4                                                         /*!< SCU SFSP5_3: EPUN Position          */
#define SCU_SFSP5_3_EPUN_Msk                                  (0x01UL << SCU_SFSP5_3_EPUN_Pos)                          /*!< SCU SFSP5_3: EPUN Mask              */
#define SCU_SFSP5_3_EHS_Pos                                   5                                                         /*!< SCU SFSP5_3: EHS Position           */
#define SCU_SFSP5_3_EHS_Msk                                   (0x01UL << SCU_SFSP5_3_EHS_Pos)                           /*!< SCU SFSP5_3: EHS Mask               */
#define SCU_SFSP5_3_EZI_Pos                                   6                                                         /*!< SCU SFSP5_3: EZI Position           */
#define SCU_SFSP5_3_EZI_Msk                                   (0x01UL << SCU_SFSP5_3_EZI_Pos)                           /*!< SCU SFSP5_3: EZI Mask               */
#define SCU_SFSP5_3_EHD_Pos                                   8                                                         /*!< SCU SFSP5_3: EHD Position           */
#define SCU_SFSP5_3_EHD_Msk                                   (0x03UL << SCU_SFSP5_3_EHD_Pos)                           /*!< SCU SFSP5_3: EHD Mask               */

// ---------------------------------------  SCU_SFSP5_4  ------------------------------------------
#define SCU_SFSP5_4_MODE_Pos                                  0                                                         /*!< SCU SFSP5_4: MODE Position          */
#define SCU_SFSP5_4_MODE_Msk                                  (0x07UL << SCU_SFSP5_4_MODE_Pos)                          /*!< SCU SFSP5_4: MODE Mask              */
#define SCU_SFSP5_4_EPD_Pos                                   3                                                         /*!< SCU SFSP5_4: EPD Position           */
#define SCU_SFSP5_4_EPD_Msk                                   (0x01UL << SCU_SFSP5_4_EPD_Pos)                           /*!< SCU SFSP5_4: EPD Mask               */
#define SCU_SFSP5_4_EPUN_Pos                                  4                                                         /*!< SCU SFSP5_4: EPUN Position          */
#define SCU_SFSP5_4_EPUN_Msk                                  (0x01UL << SCU_SFSP5_4_EPUN_Pos)                          /*!< SCU SFSP5_4: EPUN Mask              */
#define SCU_SFSP5_4_EHS_Pos                                   5                                                         /*!< SCU SFSP5_4: EHS Position           */
#define SCU_SFSP5_4_EHS_Msk                                   (0x01UL << SCU_SFSP5_4_EHS_Pos)                           /*!< SCU SFSP5_4: EHS Mask               */
#define SCU_SFSP5_4_EZI_Pos                                   6                                                         /*!< SCU SFSP5_4: EZI Position           */
#define SCU_SFSP5_4_EZI_Msk                                   (0x01UL << SCU_SFSP5_4_EZI_Pos)                           /*!< SCU SFSP5_4: EZI Mask               */
#define SCU_SFSP5_4_EHD_Pos                                   8                                                         /*!< SCU SFSP5_4: EHD Position           */
#define SCU_SFSP5_4_EHD_Msk                                   (0x03UL << SCU_SFSP5_4_EHD_Pos)                           /*!< SCU SFSP5_4: EHD Mask               */

// ---------------------------------------  SCU_SFSP5_5  ------------------------------------------
#define SCU_SFSP5_5_MODE_Pos                                  0                                                         /*!< SCU SFSP5_5: MODE Position          */
#define SCU_SFSP5_5_MODE_Msk                                  (0x07UL << SCU_SFSP5_5_MODE_Pos)                          /*!< SCU SFSP5_5: MODE Mask              */
#define SCU_SFSP5_5_EPD_Pos                                   3                                                         /*!< SCU SFSP5_5: EPD Position           */
#define SCU_SFSP5_5_EPD_Msk                                   (0x01UL << SCU_SFSP5_5_EPD_Pos)                           /*!< SCU SFSP5_5: EPD Mask               */
#define SCU_SFSP5_5_EPUN_Pos                                  4                                                         /*!< SCU SFSP5_5: EPUN Position          */
#define SCU_SFSP5_5_EPUN_Msk                                  (0x01UL << SCU_SFSP5_5_EPUN_Pos)                          /*!< SCU SFSP5_5: EPUN Mask              */
#define SCU_SFSP5_5_EHS_Pos                                   5                                                         /*!< SCU SFSP5_5: EHS Position           */
#define SCU_SFSP5_5_EHS_Msk                                   (0x01UL << SCU_SFSP5_5_EHS_Pos)                           /*!< SCU SFSP5_5: EHS Mask               */
#define SCU_SFSP5_5_EZI_Pos                                   6                                                         /*!< SCU SFSP5_5: EZI Position           */
#define SCU_SFSP5_5_EZI_Msk                                   (0x01UL << SCU_SFSP5_5_EZI_Pos)                           /*!< SCU SFSP5_5: EZI Mask               */
#define SCU_SFSP5_5_EHD_Pos                                   8                                                         /*!< SCU SFSP5_5: EHD Position           */
#define SCU_SFSP5_5_EHD_Msk                                   (0x03UL << SCU_SFSP5_5_EHD_Pos)                           /*!< SCU SFSP5_5: EHD Mask               */

// ---------------------------------------  SCU_SFSP5_6  ------------------------------------------
#define SCU_SFSP5_6_MODE_Pos                                  0                                                         /*!< SCU SFSP5_6: MODE Position          */
#define SCU_SFSP5_6_MODE_Msk                                  (0x07UL << SCU_SFSP5_6_MODE_Pos)                          /*!< SCU SFSP5_6: MODE Mask              */
#define SCU_SFSP5_6_EPD_Pos                                   3                                                         /*!< SCU SFSP5_6: EPD Position           */
#define SCU_SFSP5_6_EPD_Msk                                   (0x01UL << SCU_SFSP5_6_EPD_Pos)                           /*!< SCU SFSP5_6: EPD Mask               */
#define SCU_SFSP5_6_EPUN_Pos                                  4                                                         /*!< SCU SFSP5_6: EPUN Position          */
#define SCU_SFSP5_6_EPUN_Msk                                  (0x01UL << SCU_SFSP5_6_EPUN_Pos)                          /*!< SCU SFSP5_6: EPUN Mask              */
#define SCU_SFSP5_6_EHS_Pos                                   5                                                         /*!< SCU SFSP5_6: EHS Position           */
#define SCU_SFSP5_6_EHS_Msk                                   (0x01UL << SCU_SFSP5_6_EHS_Pos)                           /*!< SCU SFSP5_6: EHS Mask               */
#define SCU_SFSP5_6_EZI_Pos                                   6                                                         /*!< SCU SFSP5_6: EZI Position           */
#define SCU_SFSP5_6_EZI_Msk                                   (0x01UL << SCU_SFSP5_6_EZI_Pos)                           /*!< SCU SFSP5_6: EZI Mask               */
#define SCU_SFSP5_6_EHD_Pos                                   8                                                         /*!< SCU SFSP5_6: EHD Position           */
#define SCU_SFSP5_6_EHD_Msk                                   (0x03UL << SCU_SFSP5_6_EHD_Pos)                           /*!< SCU SFSP5_6: EHD Mask               */

// ---------------------------------------  SCU_SFSP5_7  ------------------------------------------
#define SCU_SFSP5_7_MODE_Pos                                  0                                                         /*!< SCU SFSP5_7: MODE Position          */
#define SCU_SFSP5_7_MODE_Msk                                  (0x07UL << SCU_SFSP5_7_MODE_Pos)                          /*!< SCU SFSP5_7: MODE Mask              */
#define SCU_SFSP5_7_EPD_Pos                                   3                                                         /*!< SCU SFSP5_7: EPD Position           */
#define SCU_SFSP5_7_EPD_Msk                                   (0x01UL << SCU_SFSP5_7_EPD_Pos)                           /*!< SCU SFSP5_7: EPD Mask               */
#define SCU_SFSP5_7_EPUN_Pos                                  4                                                         /*!< SCU SFSP5_7: EPUN Position          */
#define SCU_SFSP5_7_EPUN_Msk                                  (0x01UL << SCU_SFSP5_7_EPUN_Pos)                          /*!< SCU SFSP5_7: EPUN Mask              */
#define SCU_SFSP5_7_EHS_Pos                                   5                                                         /*!< SCU SFSP5_7: EHS Position           */
#define SCU_SFSP5_7_EHS_Msk                                   (0x01UL << SCU_SFSP5_7_EHS_Pos)                           /*!< SCU SFSP5_7: EHS Mask               */
#define SCU_SFSP5_7_EZI_Pos                                   6                                                         /*!< SCU SFSP5_7: EZI Position           */
#define SCU_SFSP5_7_EZI_Msk                                   (0x01UL << SCU_SFSP5_7_EZI_Pos)                           /*!< SCU SFSP5_7: EZI Mask               */
#define SCU_SFSP5_7_EHD_Pos                                   8                                                         /*!< SCU SFSP5_7: EHD Position           */
#define SCU_SFSP5_7_EHD_Msk                                   (0x03UL << SCU_SFSP5_7_EHD_Pos)                           /*!< SCU SFSP5_7: EHD Mask               */

// ---------------------------------------  SCU_SFSP6_0  ------------------------------------------
#define SCU_SFSP6_0_MODE_Pos                                  0                                                         /*!< SCU SFSP6_0: MODE Position          */
#define SCU_SFSP6_0_MODE_Msk                                  (0x07UL << SCU_SFSP6_0_MODE_Pos)                          /*!< SCU SFSP6_0: MODE Mask              */
#define SCU_SFSP6_0_EPD_Pos                                   3                                                         /*!< SCU SFSP6_0: EPD Position           */
#define SCU_SFSP6_0_EPD_Msk                                   (0x01UL << SCU_SFSP6_0_EPD_Pos)                           /*!< SCU SFSP6_0: EPD Mask               */
#define SCU_SFSP6_0_EPUN_Pos                                  4                                                         /*!< SCU SFSP6_0: EPUN Position          */
#define SCU_SFSP6_0_EPUN_Msk                                  (0x01UL << SCU_SFSP6_0_EPUN_Pos)                          /*!< SCU SFSP6_0: EPUN Mask              */
#define SCU_SFSP6_0_EHS_Pos                                   5                                                         /*!< SCU SFSP6_0: EHS Position           */
#define SCU_SFSP6_0_EHS_Msk                                   (0x01UL << SCU_SFSP6_0_EHS_Pos)                           /*!< SCU SFSP6_0: EHS Mask               */
#define SCU_SFSP6_0_EZI_Pos                                   6                                                         /*!< SCU SFSP6_0: EZI Position           */
#define SCU_SFSP6_0_EZI_Msk                                   (0x01UL << SCU_SFSP6_0_EZI_Pos)                           /*!< SCU SFSP6_0: EZI Mask               */
#define SCU_SFSP6_0_EHD_Pos                                   8                                                         /*!< SCU SFSP6_0: EHD Position           */
#define SCU_SFSP6_0_EHD_Msk                                   (0x03UL << SCU_SFSP6_0_EHD_Pos)                           /*!< SCU SFSP6_0: EHD Mask               */

// ---------------------------------------  SCU_SFSP6_1  ------------------------------------------
#define SCU_SFSP6_1_MODE_Pos                                  0                                                         /*!< SCU SFSP6_1: MODE Position          */
#define SCU_SFSP6_1_MODE_Msk                                  (0x07UL << SCU_SFSP6_1_MODE_Pos)                          /*!< SCU SFSP6_1: MODE Mask              */
#define SCU_SFSP6_1_EPD_Pos                                   3                                                         /*!< SCU SFSP6_1: EPD Position           */
#define SCU_SFSP6_1_EPD_Msk                                   (0x01UL << SCU_SFSP6_1_EPD_Pos)                           /*!< SCU SFSP6_1: EPD Mask               */
#define SCU_SFSP6_1_EPUN_Pos                                  4                                                         /*!< SCU SFSP6_1: EPUN Position          */
#define SCU_SFSP6_1_EPUN_Msk                                  (0x01UL << SCU_SFSP6_1_EPUN_Pos)                          /*!< SCU SFSP6_1: EPUN Mask              */
#define SCU_SFSP6_1_EHS_Pos                                   5                                                         /*!< SCU SFSP6_1: EHS Position           */
#define SCU_SFSP6_1_EHS_Msk                                   (0x01UL << SCU_SFSP6_1_EHS_Pos)                           /*!< SCU SFSP6_1: EHS Mask               */
#define SCU_SFSP6_1_EZI_Pos                                   6                                                         /*!< SCU SFSP6_1: EZI Position           */
#define SCU_SFSP6_1_EZI_Msk                                   (0x01UL << SCU_SFSP6_1_EZI_Pos)                           /*!< SCU SFSP6_1: EZI Mask               */
#define SCU_SFSP6_1_EHD_Pos                                   8                                                         /*!< SCU SFSP6_1: EHD Position           */
#define SCU_SFSP6_1_EHD_Msk                                   (0x03UL << SCU_SFSP6_1_EHD_Pos)                           /*!< SCU SFSP6_1: EHD Mask               */

// ---------------------------------------  SCU_SFSP6_2  ------------------------------------------
#define SCU_SFSP6_2_MODE_Pos                                  0                                                         /*!< SCU SFSP6_2: MODE Position          */
#define SCU_SFSP6_2_MODE_Msk                                  (0x07UL << SCU_SFSP6_2_MODE_Pos)                          /*!< SCU SFSP6_2: MODE Mask              */
#define SCU_SFSP6_2_EPD_Pos                                   3                                                         /*!< SCU SFSP6_2: EPD Position           */
#define SCU_SFSP6_2_EPD_Msk                                   (0x01UL << SCU_SFSP6_2_EPD_Pos)                           /*!< SCU SFSP6_2: EPD Mask               */
#define SCU_SFSP6_2_EPUN_Pos                                  4                                                         /*!< SCU SFSP6_2: EPUN Position          */
#define SCU_SFSP6_2_EPUN_Msk                                  (0x01UL << SCU_SFSP6_2_EPUN_Pos)                          /*!< SCU SFSP6_2: EPUN Mask              */
#define SCU_SFSP6_2_EHS_Pos                                   5                                                         /*!< SCU SFSP6_2: EHS Position           */
#define SCU_SFSP6_2_EHS_Msk                                   (0x01UL << SCU_SFSP6_2_EHS_Pos)                           /*!< SCU SFSP6_2: EHS Mask               */
#define SCU_SFSP6_2_EZI_Pos                                   6                                                         /*!< SCU SFSP6_2: EZI Position           */
#define SCU_SFSP6_2_EZI_Msk                                   (0x01UL << SCU_SFSP6_2_EZI_Pos)                           /*!< SCU SFSP6_2: EZI Mask               */
#define SCU_SFSP6_2_EHD_Pos                                   8                                                         /*!< SCU SFSP6_2: EHD Position           */
#define SCU_SFSP6_2_EHD_Msk                                   (0x03UL << SCU_SFSP6_2_EHD_Pos)                           /*!< SCU SFSP6_2: EHD Mask               */

// ---------------------------------------  SCU_SFSP6_3  ------------------------------------------
#define SCU_SFSP6_3_MODE_Pos                                  0                                                         /*!< SCU SFSP6_3: MODE Position          */
#define SCU_SFSP6_3_MODE_Msk                                  (0x07UL << SCU_SFSP6_3_MODE_Pos)                          /*!< SCU SFSP6_3: MODE Mask              */
#define SCU_SFSP6_3_EPD_Pos                                   3                                                         /*!< SCU SFSP6_3: EPD Position           */
#define SCU_SFSP6_3_EPD_Msk                                   (0x01UL << SCU_SFSP6_3_EPD_Pos)                           /*!< SCU SFSP6_3: EPD Mask               */
#define SCU_SFSP6_3_EPUN_Pos                                  4                                                         /*!< SCU SFSP6_3: EPUN Position          */
#define SCU_SFSP6_3_EPUN_Msk                                  (0x01UL << SCU_SFSP6_3_EPUN_Pos)                          /*!< SCU SFSP6_3: EPUN Mask              */
#define SCU_SFSP6_3_EHS_Pos                                   5                                                         /*!< SCU SFSP6_3: EHS Position           */
#define SCU_SFSP6_3_EHS_Msk                                   (0x01UL << SCU_SFSP6_3_EHS_Pos)                           /*!< SCU SFSP6_3: EHS Mask               */
#define SCU_SFSP6_3_EZI_Pos                                   6                                                         /*!< SCU SFSP6_3: EZI Position           */
#define SCU_SFSP6_3_EZI_Msk                                   (0x01UL << SCU_SFSP6_3_EZI_Pos)                           /*!< SCU SFSP6_3: EZI Mask               */
#define SCU_SFSP6_3_EHD_Pos                                   8                                                         /*!< SCU SFSP6_3: EHD Position           */
#define SCU_SFSP6_3_EHD_Msk                                   (0x03UL << SCU_SFSP6_3_EHD_Pos)                           /*!< SCU SFSP6_3: EHD Mask               */

// ---------------------------------------  SCU_SFSP6_4  ------------------------------------------
#define SCU_SFSP6_4_MODE_Pos                                  0                                                         /*!< SCU SFSP6_4: MODE Position          */
#define SCU_SFSP6_4_MODE_Msk                                  (0x07UL << SCU_SFSP6_4_MODE_Pos)                          /*!< SCU SFSP6_4: MODE Mask              */
#define SCU_SFSP6_4_EPD_Pos                                   3                                                         /*!< SCU SFSP6_4: EPD Position           */
#define SCU_SFSP6_4_EPD_Msk                                   (0x01UL << SCU_SFSP6_4_EPD_Pos)                           /*!< SCU SFSP6_4: EPD Mask               */
#define SCU_SFSP6_4_EPUN_Pos                                  4                                                         /*!< SCU SFSP6_4: EPUN Position          */
#define SCU_SFSP6_4_EPUN_Msk                                  (0x01UL << SCU_SFSP6_4_EPUN_Pos)                          /*!< SCU SFSP6_4: EPUN Mask              */
#define SCU_SFSP6_4_EHS_Pos                                   5                                                         /*!< SCU SFSP6_4: EHS Position           */
#define SCU_SFSP6_4_EHS_Msk                                   (0x01UL << SCU_SFSP6_4_EHS_Pos)                           /*!< SCU SFSP6_4: EHS Mask               */
#define SCU_SFSP6_4_EZI_Pos                                   6                                                         /*!< SCU SFSP6_4: EZI Position           */
#define SCU_SFSP6_4_EZI_Msk                                   (0x01UL << SCU_SFSP6_4_EZI_Pos)                           /*!< SCU SFSP6_4: EZI Mask               */
#define SCU_SFSP6_4_EHD_Pos                                   8                                                         /*!< SCU SFSP6_4: EHD Position           */
#define SCU_SFSP6_4_EHD_Msk                                   (0x03UL << SCU_SFSP6_4_EHD_Pos)                           /*!< SCU SFSP6_4: EHD Mask               */

// ---------------------------------------  SCU_SFSP6_5  ------------------------------------------
#define SCU_SFSP6_5_MODE_Pos                                  0                                                         /*!< SCU SFSP6_5: MODE Position          */
#define SCU_SFSP6_5_MODE_Msk                                  (0x07UL << SCU_SFSP6_5_MODE_Pos)                          /*!< SCU SFSP6_5: MODE Mask              */
#define SCU_SFSP6_5_EPD_Pos                                   3                                                         /*!< SCU SFSP6_5: EPD Position           */
#define SCU_SFSP6_5_EPD_Msk                                   (0x01UL << SCU_SFSP6_5_EPD_Pos)                           /*!< SCU SFSP6_5: EPD Mask               */
#define SCU_SFSP6_5_EPUN_Pos                                  4                                                         /*!< SCU SFSP6_5: EPUN Position          */
#define SCU_SFSP6_5_EPUN_Msk                                  (0x01UL << SCU_SFSP6_5_EPUN_Pos)                          /*!< SCU SFSP6_5: EPUN Mask              */
#define SCU_SFSP6_5_EHS_Pos                                   5                                                         /*!< SCU SFSP6_5: EHS Position           */
#define SCU_SFSP6_5_EHS_Msk                                   (0x01UL << SCU_SFSP6_5_EHS_Pos)                           /*!< SCU SFSP6_5: EHS Mask               */
#define SCU_SFSP6_5_EZI_Pos                                   6                                                         /*!< SCU SFSP6_5: EZI Position           */
#define SCU_SFSP6_5_EZI_Msk                                   (0x01UL << SCU_SFSP6_5_EZI_Pos)                           /*!< SCU SFSP6_5: EZI Mask               */
#define SCU_SFSP6_5_EHD_Pos                                   8                                                         /*!< SCU SFSP6_5: EHD Position           */
#define SCU_SFSP6_5_EHD_Msk                                   (0x03UL << SCU_SFSP6_5_EHD_Pos)                           /*!< SCU SFSP6_5: EHD Mask               */

// ---------------------------------------  SCU_SFSP6_6  ------------------------------------------
#define SCU_SFSP6_6_MODE_Pos                                  0                                                         /*!< SCU SFSP6_6: MODE Position          */
#define SCU_SFSP6_6_MODE_Msk                                  (0x07UL << SCU_SFSP6_6_MODE_Pos)                          /*!< SCU SFSP6_6: MODE Mask              */
#define SCU_SFSP6_6_EPD_Pos                                   3                                                         /*!< SCU SFSP6_6: EPD Position           */
#define SCU_SFSP6_6_EPD_Msk                                   (0x01UL << SCU_SFSP6_6_EPD_Pos)                           /*!< SCU SFSP6_6: EPD Mask               */
#define SCU_SFSP6_6_EPUN_Pos                                  4                                                         /*!< SCU SFSP6_6: EPUN Position          */
#define SCU_SFSP6_6_EPUN_Msk                                  (0x01UL << SCU_SFSP6_6_EPUN_Pos)                          /*!< SCU SFSP6_6: EPUN Mask              */
#define SCU_SFSP6_6_EHS_Pos                                   5                                                         /*!< SCU SFSP6_6: EHS Position           */
#define SCU_SFSP6_6_EHS_Msk                                   (0x01UL << SCU_SFSP6_6_EHS_Pos)                           /*!< SCU SFSP6_6: EHS Mask               */
#define SCU_SFSP6_6_EZI_Pos                                   6                                                         /*!< SCU SFSP6_6: EZI Position           */
#define SCU_SFSP6_6_EZI_Msk                                   (0x01UL << SCU_SFSP6_6_EZI_Pos)                           /*!< SCU SFSP6_6: EZI Mask               */
#define SCU_SFSP6_6_EHD_Pos                                   8                                                         /*!< SCU SFSP6_6: EHD Position           */
#define SCU_SFSP6_6_EHD_Msk                                   (0x03UL << SCU_SFSP6_6_EHD_Pos)                           /*!< SCU SFSP6_6: EHD Mask               */

// ---------------------------------------  SCU_SFSP6_7  ------------------------------------------
#define SCU_SFSP6_7_MODE_Pos                                  0                                                         /*!< SCU SFSP6_7: MODE Position          */
#define SCU_SFSP6_7_MODE_Msk                                  (0x07UL << SCU_SFSP6_7_MODE_Pos)                          /*!< SCU SFSP6_7: MODE Mask              */
#define SCU_SFSP6_7_EPD_Pos                                   3                                                         /*!< SCU SFSP6_7: EPD Position           */
#define SCU_SFSP6_7_EPD_Msk                                   (0x01UL << SCU_SFSP6_7_EPD_Pos)                           /*!< SCU SFSP6_7: EPD Mask               */
#define SCU_SFSP6_7_EPUN_Pos                                  4                                                         /*!< SCU SFSP6_7: EPUN Position          */
#define SCU_SFSP6_7_EPUN_Msk                                  (0x01UL << SCU_SFSP6_7_EPUN_Pos)                          /*!< SCU SFSP6_7: EPUN Mask              */
#define SCU_SFSP6_7_EHS_Pos                                   5                                                         /*!< SCU SFSP6_7: EHS Position           */
#define SCU_SFSP6_7_EHS_Msk                                   (0x01UL << SCU_SFSP6_7_EHS_Pos)                           /*!< SCU SFSP6_7: EHS Mask               */
#define SCU_SFSP6_7_EZI_Pos                                   6                                                         /*!< SCU SFSP6_7: EZI Position           */
#define SCU_SFSP6_7_EZI_Msk                                   (0x01UL << SCU_SFSP6_7_EZI_Pos)                           /*!< SCU SFSP6_7: EZI Mask               */
#define SCU_SFSP6_7_EHD_Pos                                   8                                                         /*!< SCU SFSP6_7: EHD Position           */
#define SCU_SFSP6_7_EHD_Msk                                   (0x03UL << SCU_SFSP6_7_EHD_Pos)                           /*!< SCU SFSP6_7: EHD Mask               */

// ---------------------------------------  SCU_SFSP6_8  ------------------------------------------
#define SCU_SFSP6_8_MODE_Pos                                  0                                                         /*!< SCU SFSP6_8: MODE Position          */
#define SCU_SFSP6_8_MODE_Msk                                  (0x07UL << SCU_SFSP6_8_MODE_Pos)                          /*!< SCU SFSP6_8: MODE Mask              */
#define SCU_SFSP6_8_EPD_Pos                                   3                                                         /*!< SCU SFSP6_8: EPD Position           */
#define SCU_SFSP6_8_EPD_Msk                                   (0x01UL << SCU_SFSP6_8_EPD_Pos)                           /*!< SCU SFSP6_8: EPD Mask               */
#define SCU_SFSP6_8_EPUN_Pos                                  4                                                         /*!< SCU SFSP6_8: EPUN Position          */
#define SCU_SFSP6_8_EPUN_Msk                                  (0x01UL << SCU_SFSP6_8_EPUN_Pos)                          /*!< SCU SFSP6_8: EPUN Mask              */
#define SCU_SFSP6_8_EHS_Pos                                   5                                                         /*!< SCU SFSP6_8: EHS Position           */
#define SCU_SFSP6_8_EHS_Msk                                   (0x01UL << SCU_SFSP6_8_EHS_Pos)                           /*!< SCU SFSP6_8: EHS Mask               */
#define SCU_SFSP6_8_EZI_Pos                                   6                                                         /*!< SCU SFSP6_8: EZI Position           */
#define SCU_SFSP6_8_EZI_Msk                                   (0x01UL << SCU_SFSP6_8_EZI_Pos)                           /*!< SCU SFSP6_8: EZI Mask               */
#define SCU_SFSP6_8_EHD_Pos                                   8                                                         /*!< SCU SFSP6_8: EHD Position           */
#define SCU_SFSP6_8_EHD_Msk                                   (0x03UL << SCU_SFSP6_8_EHD_Pos)                           /*!< SCU SFSP6_8: EHD Mask               */

// ---------------------------------------  SCU_SFSP6_9  ------------------------------------------
#define SCU_SFSP6_9_MODE_Pos                                  0                                                         /*!< SCU SFSP6_9: MODE Position          */
#define SCU_SFSP6_9_MODE_Msk                                  (0x07UL << SCU_SFSP6_9_MODE_Pos)                          /*!< SCU SFSP6_9: MODE Mask              */
#define SCU_SFSP6_9_EPD_Pos                                   3                                                         /*!< SCU SFSP6_9: EPD Position           */
#define SCU_SFSP6_9_EPD_Msk                                   (0x01UL << SCU_SFSP6_9_EPD_Pos)                           /*!< SCU SFSP6_9: EPD Mask               */
#define SCU_SFSP6_9_EPUN_Pos                                  4                                                         /*!< SCU SFSP6_9: EPUN Position          */
#define SCU_SFSP6_9_EPUN_Msk                                  (0x01UL << SCU_SFSP6_9_EPUN_Pos)                          /*!< SCU SFSP6_9: EPUN Mask              */
#define SCU_SFSP6_9_EHS_Pos                                   5                                                         /*!< SCU SFSP6_9: EHS Position           */
#define SCU_SFSP6_9_EHS_Msk                                   (0x01UL << SCU_SFSP6_9_EHS_Pos)                           /*!< SCU SFSP6_9: EHS Mask               */
#define SCU_SFSP6_9_EZI_Pos                                   6                                                         /*!< SCU SFSP6_9: EZI Position           */
#define SCU_SFSP6_9_EZI_Msk                                   (0x01UL << SCU_SFSP6_9_EZI_Pos)                           /*!< SCU SFSP6_9: EZI Mask               */
#define SCU_SFSP6_9_EHD_Pos                                   8                                                         /*!< SCU SFSP6_9: EHD Position           */
#define SCU_SFSP6_9_EHD_Msk                                   (0x03UL << SCU_SFSP6_9_EHD_Pos)                           /*!< SCU SFSP6_9: EHD Mask               */

// --------------------------------------  SCU_SFSP6_10  ------------------------------------------
#define SCU_SFSP6_10_MODE_Pos                                 0                                                         /*!< SCU SFSP6_10: MODE Position         */
#define SCU_SFSP6_10_MODE_Msk                                 (0x07UL << SCU_SFSP6_10_MODE_Pos)                         /*!< SCU SFSP6_10: MODE Mask             */
#define SCU_SFSP6_10_EPD_Pos                                  3                                                         /*!< SCU SFSP6_10: EPD Position          */
#define SCU_SFSP6_10_EPD_Msk                                  (0x01UL << SCU_SFSP6_10_EPD_Pos)                          /*!< SCU SFSP6_10: EPD Mask              */
#define SCU_SFSP6_10_EPUN_Pos                                 4                                                         /*!< SCU SFSP6_10: EPUN Position         */
#define SCU_SFSP6_10_EPUN_Msk                                 (0x01UL << SCU_SFSP6_10_EPUN_Pos)                         /*!< SCU SFSP6_10: EPUN Mask             */
#define SCU_SFSP6_10_EHS_Pos                                  5                                                         /*!< SCU SFSP6_10: EHS Position          */
#define SCU_SFSP6_10_EHS_Msk                                  (0x01UL << SCU_SFSP6_10_EHS_Pos)                          /*!< SCU SFSP6_10: EHS Mask              */
#define SCU_SFSP6_10_EZI_Pos                                  6                                                         /*!< SCU SFSP6_10: EZI Position          */
#define SCU_SFSP6_10_EZI_Msk                                  (0x01UL << SCU_SFSP6_10_EZI_Pos)                          /*!< SCU SFSP6_10: EZI Mask              */
#define SCU_SFSP6_10_EHD_Pos                                  8                                                         /*!< SCU SFSP6_10: EHD Position          */
#define SCU_SFSP6_10_EHD_Msk                                  (0x03UL << SCU_SFSP6_10_EHD_Pos)                          /*!< SCU SFSP6_10: EHD Mask              */

// --------------------------------------  SCU_SFSP6_11  ------------------------------------------
#define SCU_SFSP6_11_MODE_Pos                                 0                                                         /*!< SCU SFSP6_11: MODE Position         */
#define SCU_SFSP6_11_MODE_Msk                                 (0x07UL << SCU_SFSP6_11_MODE_Pos)                         /*!< SCU SFSP6_11: MODE Mask             */
#define SCU_SFSP6_11_EPD_Pos                                  3                                                         /*!< SCU SFSP6_11: EPD Position          */
#define SCU_SFSP6_11_EPD_Msk                                  (0x01UL << SCU_SFSP6_11_EPD_Pos)                          /*!< SCU SFSP6_11: EPD Mask              */
#define SCU_SFSP6_11_EPUN_Pos                                 4                                                         /*!< SCU SFSP6_11: EPUN Position         */
#define SCU_SFSP6_11_EPUN_Msk                                 (0x01UL << SCU_SFSP6_11_EPUN_Pos)                         /*!< SCU SFSP6_11: EPUN Mask             */
#define SCU_SFSP6_11_EHS_Pos                                  5                                                         /*!< SCU SFSP6_11: EHS Position          */
#define SCU_SFSP6_11_EHS_Msk                                  (0x01UL << SCU_SFSP6_11_EHS_Pos)                          /*!< SCU SFSP6_11: EHS Mask              */
#define SCU_SFSP6_11_EZI_Pos                                  6                                                         /*!< SCU SFSP6_11: EZI Position          */
#define SCU_SFSP6_11_EZI_Msk                                  (0x01UL << SCU_SFSP6_11_EZI_Pos)                          /*!< SCU SFSP6_11: EZI Mask              */
#define SCU_SFSP6_11_EHD_Pos                                  8                                                         /*!< SCU SFSP6_11: EHD Position          */
#define SCU_SFSP6_11_EHD_Msk                                  (0x03UL << SCU_SFSP6_11_EHD_Pos)                          /*!< SCU SFSP6_11: EHD Mask              */

// --------------------------------------  SCU_SFSP6_12  ------------------------------------------
#define SCU_SFSP6_12_MODE_Pos                                 0                                                         /*!< SCU SFSP6_12: MODE Position         */
#define SCU_SFSP6_12_MODE_Msk                                 (0x07UL << SCU_SFSP6_12_MODE_Pos)                         /*!< SCU SFSP6_12: MODE Mask             */
#define SCU_SFSP6_12_EPD_Pos                                  3                                                         /*!< SCU SFSP6_12: EPD Position          */
#define SCU_SFSP6_12_EPD_Msk                                  (0x01UL << SCU_SFSP6_12_EPD_Pos)                          /*!< SCU SFSP6_12: EPD Mask              */
#define SCU_SFSP6_12_EPUN_Pos                                 4                                                         /*!< SCU SFSP6_12: EPUN Position         */
#define SCU_SFSP6_12_EPUN_Msk                                 (0x01UL << SCU_SFSP6_12_EPUN_Pos)                         /*!< SCU SFSP6_12: EPUN Mask             */
#define SCU_SFSP6_12_EHS_Pos                                  5                                                         /*!< SCU SFSP6_12: EHS Position          */
#define SCU_SFSP6_12_EHS_Msk                                  (0x01UL << SCU_SFSP6_12_EHS_Pos)                          /*!< SCU SFSP6_12: EHS Mask              */
#define SCU_SFSP6_12_EZI_Pos                                  6                                                         /*!< SCU SFSP6_12: EZI Position          */
#define SCU_SFSP6_12_EZI_Msk                                  (0x01UL << SCU_SFSP6_12_EZI_Pos)                          /*!< SCU SFSP6_12: EZI Mask              */
#define SCU_SFSP6_12_EHD_Pos                                  8                                                         /*!< SCU SFSP6_12: EHD Position          */
#define SCU_SFSP6_12_EHD_Msk                                  (0x03UL << SCU_SFSP6_12_EHD_Pos)                          /*!< SCU SFSP6_12: EHD Mask              */

// ---------------------------------------  SCU_SFSP7_0  ------------------------------------------
#define SCU_SFSP7_0_MODE_Pos                                  0                                                         /*!< SCU SFSP7_0: MODE Position          */
#define SCU_SFSP7_0_MODE_Msk                                  (0x07UL << SCU_SFSP7_0_MODE_Pos)                          /*!< SCU SFSP7_0: MODE Mask              */
#define SCU_SFSP7_0_EPD_Pos                                   3                                                         /*!< SCU SFSP7_0: EPD Position           */
#define SCU_SFSP7_0_EPD_Msk                                   (0x01UL << SCU_SFSP7_0_EPD_Pos)                           /*!< SCU SFSP7_0: EPD Mask               */
#define SCU_SFSP7_0_EPUN_Pos                                  4                                                         /*!< SCU SFSP7_0: EPUN Position          */
#define SCU_SFSP7_0_EPUN_Msk                                  (0x01UL << SCU_SFSP7_0_EPUN_Pos)                          /*!< SCU SFSP7_0: EPUN Mask              */
#define SCU_SFSP7_0_EHS_Pos                                   5                                                         /*!< SCU SFSP7_0: EHS Position           */
#define SCU_SFSP7_0_EHS_Msk                                   (0x01UL << SCU_SFSP7_0_EHS_Pos)                           /*!< SCU SFSP7_0: EHS Mask               */
#define SCU_SFSP7_0_EZI_Pos                                   6                                                         /*!< SCU SFSP7_0: EZI Position           */
#define SCU_SFSP7_0_EZI_Msk                                   (0x01UL << SCU_SFSP7_0_EZI_Pos)                           /*!< SCU SFSP7_0: EZI Mask               */
#define SCU_SFSP7_0_EHD_Pos                                   8                                                         /*!< SCU SFSP7_0: EHD Position           */
#define SCU_SFSP7_0_EHD_Msk                                   (0x03UL << SCU_SFSP7_0_EHD_Pos)                           /*!< SCU SFSP7_0: EHD Mask               */

// ---------------------------------------  SCU_SFSP7_1  ------------------------------------------
#define SCU_SFSP7_1_MODE_Pos                                  0                                                         /*!< SCU SFSP7_1: MODE Position          */
#define SCU_SFSP7_1_MODE_Msk                                  (0x07UL << SCU_SFSP7_1_MODE_Pos)                          /*!< SCU SFSP7_1: MODE Mask              */
#define SCU_SFSP7_1_EPD_Pos                                   3                                                         /*!< SCU SFSP7_1: EPD Position           */
#define SCU_SFSP7_1_EPD_Msk                                   (0x01UL << SCU_SFSP7_1_EPD_Pos)                           /*!< SCU SFSP7_1: EPD Mask               */
#define SCU_SFSP7_1_EPUN_Pos                                  4                                                         /*!< SCU SFSP7_1: EPUN Position          */
#define SCU_SFSP7_1_EPUN_Msk                                  (0x01UL << SCU_SFSP7_1_EPUN_Pos)                          /*!< SCU SFSP7_1: EPUN Mask              */
#define SCU_SFSP7_1_EHS_Pos                                   5                                                         /*!< SCU SFSP7_1: EHS Position           */
#define SCU_SFSP7_1_EHS_Msk                                   (0x01UL << SCU_SFSP7_1_EHS_Pos)                           /*!< SCU SFSP7_1: EHS Mask               */
#define SCU_SFSP7_1_EZI_Pos                                   6                                                         /*!< SCU SFSP7_1: EZI Position           */
#define SCU_SFSP7_1_EZI_Msk                                   (0x01UL << SCU_SFSP7_1_EZI_Pos)                           /*!< SCU SFSP7_1: EZI Mask               */
#define SCU_SFSP7_1_EHD_Pos                                   8                                                         /*!< SCU SFSP7_1: EHD Position           */
#define SCU_SFSP7_1_EHD_Msk                                   (0x03UL << SCU_SFSP7_1_EHD_Pos)                           /*!< SCU SFSP7_1: EHD Mask               */

// ---------------------------------------  SCU_SFSP7_2  ------------------------------------------
#define SCU_SFSP7_2_MODE_Pos                                  0                                                         /*!< SCU SFSP7_2: MODE Position          */
#define SCU_SFSP7_2_MODE_Msk                                  (0x07UL << SCU_SFSP7_2_MODE_Pos)                          /*!< SCU SFSP7_2: MODE Mask              */
#define SCU_SFSP7_2_EPD_Pos                                   3                                                         /*!< SCU SFSP7_2: EPD Position           */
#define SCU_SFSP7_2_EPD_Msk                                   (0x01UL << SCU_SFSP7_2_EPD_Pos)                           /*!< SCU SFSP7_2: EPD Mask               */
#define SCU_SFSP7_2_EPUN_Pos                                  4                                                         /*!< SCU SFSP7_2: EPUN Position          */
#define SCU_SFSP7_2_EPUN_Msk                                  (0x01UL << SCU_SFSP7_2_EPUN_Pos)                          /*!< SCU SFSP7_2: EPUN Mask              */
#define SCU_SFSP7_2_EHS_Pos                                   5                                                         /*!< SCU SFSP7_2: EHS Position           */
#define SCU_SFSP7_2_EHS_Msk                                   (0x01UL << SCU_SFSP7_2_EHS_Pos)                           /*!< SCU SFSP7_2: EHS Mask               */
#define SCU_SFSP7_2_EZI_Pos                                   6                                                         /*!< SCU SFSP7_2: EZI Position           */
#define SCU_SFSP7_2_EZI_Msk                                   (0x01UL << SCU_SFSP7_2_EZI_Pos)                           /*!< SCU SFSP7_2: EZI Mask               */
#define SCU_SFSP7_2_EHD_Pos                                   8                                                         /*!< SCU SFSP7_2: EHD Position           */
#define SCU_SFSP7_2_EHD_Msk                                   (0x03UL << SCU_SFSP7_2_EHD_Pos)                           /*!< SCU SFSP7_2: EHD Mask               */

// ---------------------------------------  SCU_SFSP7_3  ------------------------------------------
#define SCU_SFSP7_3_MODE_Pos                                  0                                                         /*!< SCU SFSP7_3: MODE Position          */
#define SCU_SFSP7_3_MODE_Msk                                  (0x07UL << SCU_SFSP7_3_MODE_Pos)                          /*!< SCU SFSP7_3: MODE Mask              */
#define SCU_SFSP7_3_EPD_Pos                                   3                                                         /*!< SCU SFSP7_3: EPD Position           */
#define SCU_SFSP7_3_EPD_Msk                                   (0x01UL << SCU_SFSP7_3_EPD_Pos)                           /*!< SCU SFSP7_3: EPD Mask               */
#define SCU_SFSP7_3_EPUN_Pos                                  4                                                         /*!< SCU SFSP7_3: EPUN Position          */
#define SCU_SFSP7_3_EPUN_Msk                                  (0x01UL << SCU_SFSP7_3_EPUN_Pos)                          /*!< SCU SFSP7_3: EPUN Mask              */
#define SCU_SFSP7_3_EHS_Pos                                   5                                                         /*!< SCU SFSP7_3: EHS Position           */
#define SCU_SFSP7_3_EHS_Msk                                   (0x01UL << SCU_SFSP7_3_EHS_Pos)                           /*!< SCU SFSP7_3: EHS Mask               */
#define SCU_SFSP7_3_EZI_Pos                                   6                                                         /*!< SCU SFSP7_3: EZI Position           */
#define SCU_SFSP7_3_EZI_Msk                                   (0x01UL << SCU_SFSP7_3_EZI_Pos)                           /*!< SCU SFSP7_3: EZI Mask               */
#define SCU_SFSP7_3_EHD_Pos                                   8                                                         /*!< SCU SFSP7_3: EHD Position           */
#define SCU_SFSP7_3_EHD_Msk                                   (0x03UL << SCU_SFSP7_3_EHD_Pos)                           /*!< SCU SFSP7_3: EHD Mask               */

// ---------------------------------------  SCU_SFSP7_4  ------------------------------------------
#define SCU_SFSP7_4_MODE_Pos                                  0                                                         /*!< SCU SFSP7_4: MODE Position          */
#define SCU_SFSP7_4_MODE_Msk                                  (0x07UL << SCU_SFSP7_4_MODE_Pos)                          /*!< SCU SFSP7_4: MODE Mask              */
#define SCU_SFSP7_4_EPD_Pos                                   3                                                         /*!< SCU SFSP7_4: EPD Position           */
#define SCU_SFSP7_4_EPD_Msk                                   (0x01UL << SCU_SFSP7_4_EPD_Pos)                           /*!< SCU SFSP7_4: EPD Mask               */
#define SCU_SFSP7_4_EPUN_Pos                                  4                                                         /*!< SCU SFSP7_4: EPUN Position          */
#define SCU_SFSP7_4_EPUN_Msk                                  (0x01UL << SCU_SFSP7_4_EPUN_Pos)                          /*!< SCU SFSP7_4: EPUN Mask              */
#define SCU_SFSP7_4_EHS_Pos                                   5                                                         /*!< SCU SFSP7_4: EHS Position           */
#define SCU_SFSP7_4_EHS_Msk                                   (0x01UL << SCU_SFSP7_4_EHS_Pos)                           /*!< SCU SFSP7_4: EHS Mask               */
#define SCU_SFSP7_4_EZI_Pos                                   6                                                         /*!< SCU SFSP7_4: EZI Position           */
#define SCU_SFSP7_4_EZI_Msk                                   (0x01UL << SCU_SFSP7_4_EZI_Pos)                           /*!< SCU SFSP7_4: EZI Mask               */
#define SCU_SFSP7_4_EHD_Pos                                   8                                                         /*!< SCU SFSP7_4: EHD Position           */
#define SCU_SFSP7_4_EHD_Msk                                   (0x03UL << SCU_SFSP7_4_EHD_Pos)                           /*!< SCU SFSP7_4: EHD Mask               */

// ---------------------------------------  SCU_SFSP7_5  ------------------------------------------
#define SCU_SFSP7_5_MODE_Pos                                  0                                                         /*!< SCU SFSP7_5: MODE Position          */
#define SCU_SFSP7_5_MODE_Msk                                  (0x07UL << SCU_SFSP7_5_MODE_Pos)                          /*!< SCU SFSP7_5: MODE Mask              */
#define SCU_SFSP7_5_EPD_Pos                                   3                                                         /*!< SCU SFSP7_5: EPD Position           */
#define SCU_SFSP7_5_EPD_Msk                                   (0x01UL << SCU_SFSP7_5_EPD_Pos)                           /*!< SCU SFSP7_5: EPD Mask               */
#define SCU_SFSP7_5_EPUN_Pos                                  4                                                         /*!< SCU SFSP7_5: EPUN Position          */
#define SCU_SFSP7_5_EPUN_Msk                                  (0x01UL << SCU_SFSP7_5_EPUN_Pos)                          /*!< SCU SFSP7_5: EPUN Mask              */
#define SCU_SFSP7_5_EHS_Pos                                   5                                                         /*!< SCU SFSP7_5: EHS Position           */
#define SCU_SFSP7_5_EHS_Msk                                   (0x01UL << SCU_SFSP7_5_EHS_Pos)                           /*!< SCU SFSP7_5: EHS Mask               */
#define SCU_SFSP7_5_EZI_Pos                                   6                                                         /*!< SCU SFSP7_5: EZI Position           */
#define SCU_SFSP7_5_EZI_Msk                                   (0x01UL << SCU_SFSP7_5_EZI_Pos)                           /*!< SCU SFSP7_5: EZI Mask               */
#define SCU_SFSP7_5_EHD_Pos                                   8                                                         /*!< SCU SFSP7_5: EHD Position           */
#define SCU_SFSP7_5_EHD_Msk                                   (0x03UL << SCU_SFSP7_5_EHD_Pos)                           /*!< SCU SFSP7_5: EHD Mask               */

// ---------------------------------------  SCU_SFSP7_6  ------------------------------------------
#define SCU_SFSP7_6_MODE_Pos                                  0                                                         /*!< SCU SFSP7_6: MODE Position          */
#define SCU_SFSP7_6_MODE_Msk                                  (0x07UL << SCU_SFSP7_6_MODE_Pos)                          /*!< SCU SFSP7_6: MODE Mask              */
#define SCU_SFSP7_6_EPD_Pos                                   3                                                         /*!< SCU SFSP7_6: EPD Position           */
#define SCU_SFSP7_6_EPD_Msk                                   (0x01UL << SCU_SFSP7_6_EPD_Pos)                           /*!< SCU SFSP7_6: EPD Mask               */
#define SCU_SFSP7_6_EPUN_Pos                                  4                                                         /*!< SCU SFSP7_6: EPUN Position          */
#define SCU_SFSP7_6_EPUN_Msk                                  (0x01UL << SCU_SFSP7_6_EPUN_Pos)                          /*!< SCU SFSP7_6: EPUN Mask              */
#define SCU_SFSP7_6_EHS_Pos                                   5                                                         /*!< SCU SFSP7_6: EHS Position           */
#define SCU_SFSP7_6_EHS_Msk                                   (0x01UL << SCU_SFSP7_6_EHS_Pos)                           /*!< SCU SFSP7_6: EHS Mask               */
#define SCU_SFSP7_6_EZI_Pos                                   6                                                         /*!< SCU SFSP7_6: EZI Position           */
#define SCU_SFSP7_6_EZI_Msk                                   (0x01UL << SCU_SFSP7_6_EZI_Pos)                           /*!< SCU SFSP7_6: EZI Mask               */
#define SCU_SFSP7_6_EHD_Pos                                   8                                                         /*!< SCU SFSP7_6: EHD Position           */
#define SCU_SFSP7_6_EHD_Msk                                   (0x03UL << SCU_SFSP7_6_EHD_Pos)                           /*!< SCU SFSP7_6: EHD Mask               */

// ---------------------------------------  SCU_SFSP7_7  ------------------------------------------
#define SCU_SFSP7_7_MODE_Pos                                  0                                                         /*!< SCU SFSP7_7: MODE Position          */
#define SCU_SFSP7_7_MODE_Msk                                  (0x07UL << SCU_SFSP7_7_MODE_Pos)                          /*!< SCU SFSP7_7: MODE Mask              */
#define SCU_SFSP7_7_EPD_Pos                                   3                                                         /*!< SCU SFSP7_7: EPD Position           */
#define SCU_SFSP7_7_EPD_Msk                                   (0x01UL << SCU_SFSP7_7_EPD_Pos)                           /*!< SCU SFSP7_7: EPD Mask               */
#define SCU_SFSP7_7_EPUN_Pos                                  4                                                         /*!< SCU SFSP7_7: EPUN Position          */
#define SCU_SFSP7_7_EPUN_Msk                                  (0x01UL << SCU_SFSP7_7_EPUN_Pos)                          /*!< SCU SFSP7_7: EPUN Mask              */
#define SCU_SFSP7_7_EHS_Pos                                   5                                                         /*!< SCU SFSP7_7: EHS Position           */
#define SCU_SFSP7_7_EHS_Msk                                   (0x01UL << SCU_SFSP7_7_EHS_Pos)                           /*!< SCU SFSP7_7: EHS Mask               */
#define SCU_SFSP7_7_EZI_Pos                                   6                                                         /*!< SCU SFSP7_7: EZI Position           */
#define SCU_SFSP7_7_EZI_Msk                                   (0x01UL << SCU_SFSP7_7_EZI_Pos)                           /*!< SCU SFSP7_7: EZI Mask               */
#define SCU_SFSP7_7_EHD_Pos                                   8                                                         /*!< SCU SFSP7_7: EHD Position           */
#define SCU_SFSP7_7_EHD_Msk                                   (0x03UL << SCU_SFSP7_7_EHD_Pos)                           /*!< SCU SFSP7_7: EHD Mask               */

// ---------------------------------------  SCU_SFSP8_0  ------------------------------------------
#define SCU_SFSP8_0_MODE_Pos                                  0                                                         /*!< SCU SFSP8_0: MODE Position          */
#define SCU_SFSP8_0_MODE_Msk                                  (0x07UL << SCU_SFSP8_0_MODE_Pos)                          /*!< SCU SFSP8_0: MODE Mask              */
#define SCU_SFSP8_0_EPD_Pos                                   3                                                         /*!< SCU SFSP8_0: EPD Position           */
#define SCU_SFSP8_0_EPD_Msk                                   (0x01UL << SCU_SFSP8_0_EPD_Pos)                           /*!< SCU SFSP8_0: EPD Mask               */
#define SCU_SFSP8_0_EPUN_Pos                                  4                                                         /*!< SCU SFSP8_0: EPUN Position          */
#define SCU_SFSP8_0_EPUN_Msk                                  (0x01UL << SCU_SFSP8_0_EPUN_Pos)                          /*!< SCU SFSP8_0: EPUN Mask              */
#define SCU_SFSP8_0_EHS_Pos                                   5                                                         /*!< SCU SFSP8_0: EHS Position           */
#define SCU_SFSP8_0_EHS_Msk                                   (0x01UL << SCU_SFSP8_0_EHS_Pos)                           /*!< SCU SFSP8_0: EHS Mask               */
#define SCU_SFSP8_0_EZI_Pos                                   6                                                         /*!< SCU SFSP8_0: EZI Position           */
#define SCU_SFSP8_0_EZI_Msk                                   (0x01UL << SCU_SFSP8_0_EZI_Pos)                           /*!< SCU SFSP8_0: EZI Mask               */
#define SCU_SFSP8_0_EHD_Pos                                   8                                                         /*!< SCU SFSP8_0: EHD Position           */
#define SCU_SFSP8_0_EHD_Msk                                   (0x03UL << SCU_SFSP8_0_EHD_Pos)                           /*!< SCU SFSP8_0: EHD Mask               */

// ---------------------------------------  SCU_SFSP8_1  ------------------------------------------
#define SCU_SFSP8_1_MODE_Pos                                  0                                                         /*!< SCU SFSP8_1: MODE Position          */
#define SCU_SFSP8_1_MODE_Msk                                  (0x07UL << SCU_SFSP8_1_MODE_Pos)                          /*!< SCU SFSP8_1: MODE Mask              */
#define SCU_SFSP8_1_EPD_Pos                                   3                                                         /*!< SCU SFSP8_1: EPD Position           */
#define SCU_SFSP8_1_EPD_Msk                                   (0x01UL << SCU_SFSP8_1_EPD_Pos)                           /*!< SCU SFSP8_1: EPD Mask               */
#define SCU_SFSP8_1_EPUN_Pos                                  4                                                         /*!< SCU SFSP8_1: EPUN Position          */
#define SCU_SFSP8_1_EPUN_Msk                                  (0x01UL << SCU_SFSP8_1_EPUN_Pos)                          /*!< SCU SFSP8_1: EPUN Mask              */
#define SCU_SFSP8_1_EHS_Pos                                   5                                                         /*!< SCU SFSP8_1: EHS Position           */
#define SCU_SFSP8_1_EHS_Msk                                   (0x01UL << SCU_SFSP8_1_EHS_Pos)                           /*!< SCU SFSP8_1: EHS Mask               */
#define SCU_SFSP8_1_EZI_Pos                                   6                                                         /*!< SCU SFSP8_1: EZI Position           */
#define SCU_SFSP8_1_EZI_Msk                                   (0x01UL << SCU_SFSP8_1_EZI_Pos)                           /*!< SCU SFSP8_1: EZI Mask               */
#define SCU_SFSP8_1_EHD_Pos                                   8                                                         /*!< SCU SFSP8_1: EHD Position           */
#define SCU_SFSP8_1_EHD_Msk                                   (0x03UL << SCU_SFSP8_1_EHD_Pos)                           /*!< SCU SFSP8_1: EHD Mask               */

// ---------------------------------------  SCU_SFSP8_2  ------------------------------------------
#define SCU_SFSP8_2_MODE_Pos                                  0                                                         /*!< SCU SFSP8_2: MODE Position          */
#define SCU_SFSP8_2_MODE_Msk                                  (0x07UL << SCU_SFSP8_2_MODE_Pos)                          /*!< SCU SFSP8_2: MODE Mask              */
#define SCU_SFSP8_2_EPD_Pos                                   3                                                         /*!< SCU SFSP8_2: EPD Position           */
#define SCU_SFSP8_2_EPD_Msk                                   (0x01UL << SCU_SFSP8_2_EPD_Pos)                           /*!< SCU SFSP8_2: EPD Mask               */
#define SCU_SFSP8_2_EPUN_Pos                                  4                                                         /*!< SCU SFSP8_2: EPUN Position          */
#define SCU_SFSP8_2_EPUN_Msk                                  (0x01UL << SCU_SFSP8_2_EPUN_Pos)                          /*!< SCU SFSP8_2: EPUN Mask              */
#define SCU_SFSP8_2_EHS_Pos                                   5                                                         /*!< SCU SFSP8_2: EHS Position           */
#define SCU_SFSP8_2_EHS_Msk                                   (0x01UL << SCU_SFSP8_2_EHS_Pos)                           /*!< SCU SFSP8_2: EHS Mask               */
#define SCU_SFSP8_2_EZI_Pos                                   6                                                         /*!< SCU SFSP8_2: EZI Position           */
#define SCU_SFSP8_2_EZI_Msk                                   (0x01UL << SCU_SFSP8_2_EZI_Pos)                           /*!< SCU SFSP8_2: EZI Mask               */
#define SCU_SFSP8_2_EHD_Pos                                   8                                                         /*!< SCU SFSP8_2: EHD Position           */
#define SCU_SFSP8_2_EHD_Msk                                   (0x03UL << SCU_SFSP8_2_EHD_Pos)                           /*!< SCU SFSP8_2: EHD Mask               */

// ---------------------------------------  SCU_SFSP8_3  ------------------------------------------
#define SCU_SFSP8_3_MODE_Pos                                  0                                                         /*!< SCU SFSP8_3: MODE Position          */
#define SCU_SFSP8_3_MODE_Msk                                  (0x07UL << SCU_SFSP8_3_MODE_Pos)                          /*!< SCU SFSP8_3: MODE Mask              */
#define SCU_SFSP8_3_EPD_Pos                                   3                                                         /*!< SCU SFSP8_3: EPD Position           */
#define SCU_SFSP8_3_EPD_Msk                                   (0x01UL << SCU_SFSP8_3_EPD_Pos)                           /*!< SCU SFSP8_3: EPD Mask               */
#define SCU_SFSP8_3_EPUN_Pos                                  4                                                         /*!< SCU SFSP8_3: EPUN Position          */
#define SCU_SFSP8_3_EPUN_Msk                                  (0x01UL << SCU_SFSP8_3_EPUN_Pos)                          /*!< SCU SFSP8_3: EPUN Mask              */
#define SCU_SFSP8_3_EHS_Pos                                   5                                                         /*!< SCU SFSP8_3: EHS Position           */
#define SCU_SFSP8_3_EHS_Msk                                   (0x01UL << SCU_SFSP8_3_EHS_Pos)                           /*!< SCU SFSP8_3: EHS Mask               */
#define SCU_SFSP8_3_EZI_Pos                                   6                                                         /*!< SCU SFSP8_3: EZI Position           */
#define SCU_SFSP8_3_EZI_Msk                                   (0x01UL << SCU_SFSP8_3_EZI_Pos)                           /*!< SCU SFSP8_3: EZI Mask               */
#define SCU_SFSP8_3_EHD_Pos                                   8                                                         /*!< SCU SFSP8_3: EHD Position           */
#define SCU_SFSP8_3_EHD_Msk                                   (0x03UL << SCU_SFSP8_3_EHD_Pos)                           /*!< SCU SFSP8_3: EHD Mask               */

// ---------------------------------------  SCU_SFSP8_4  ------------------------------------------
#define SCU_SFSP8_4_MODE_Pos                                  0                                                         /*!< SCU SFSP8_4: MODE Position          */
#define SCU_SFSP8_4_MODE_Msk                                  (0x07UL << SCU_SFSP8_4_MODE_Pos)                          /*!< SCU SFSP8_4: MODE Mask              */
#define SCU_SFSP8_4_EPD_Pos                                   3                                                         /*!< SCU SFSP8_4: EPD Position           */
#define SCU_SFSP8_4_EPD_Msk                                   (0x01UL << SCU_SFSP8_4_EPD_Pos)                           /*!< SCU SFSP8_4: EPD Mask               */
#define SCU_SFSP8_4_EPUN_Pos                                  4                                                         /*!< SCU SFSP8_4: EPUN Position          */
#define SCU_SFSP8_4_EPUN_Msk                                  (0x01UL << SCU_SFSP8_4_EPUN_Pos)                          /*!< SCU SFSP8_4: EPUN Mask              */
#define SCU_SFSP8_4_EHS_Pos                                   5                                                         /*!< SCU SFSP8_4: EHS Position           */
#define SCU_SFSP8_4_EHS_Msk                                   (0x01UL << SCU_SFSP8_4_EHS_Pos)                           /*!< SCU SFSP8_4: EHS Mask               */
#define SCU_SFSP8_4_EZI_Pos                                   6                                                         /*!< SCU SFSP8_4: EZI Position           */
#define SCU_SFSP8_4_EZI_Msk                                   (0x01UL << SCU_SFSP8_4_EZI_Pos)                           /*!< SCU SFSP8_4: EZI Mask               */
#define SCU_SFSP8_4_EHD_Pos                                   8                                                         /*!< SCU SFSP8_4: EHD Position           */
#define SCU_SFSP8_4_EHD_Msk                                   (0x03UL << SCU_SFSP8_4_EHD_Pos)                           /*!< SCU SFSP8_4: EHD Mask               */

// ---------------------------------------  SCU_SFSP8_5  ------------------------------------------
#define SCU_SFSP8_5_MODE_Pos                                  0                                                         /*!< SCU SFSP8_5: MODE Position          */
#define SCU_SFSP8_5_MODE_Msk                                  (0x07UL << SCU_SFSP8_5_MODE_Pos)                          /*!< SCU SFSP8_5: MODE Mask              */
#define SCU_SFSP8_5_EPD_Pos                                   3                                                         /*!< SCU SFSP8_5: EPD Position           */
#define SCU_SFSP8_5_EPD_Msk                                   (0x01UL << SCU_SFSP8_5_EPD_Pos)                           /*!< SCU SFSP8_5: EPD Mask               */
#define SCU_SFSP8_5_EPUN_Pos                                  4                                                         /*!< SCU SFSP8_5: EPUN Position          */
#define SCU_SFSP8_5_EPUN_Msk                                  (0x01UL << SCU_SFSP8_5_EPUN_Pos)                          /*!< SCU SFSP8_5: EPUN Mask              */
#define SCU_SFSP8_5_EHS_Pos                                   5                                                         /*!< SCU SFSP8_5: EHS Position           */
#define SCU_SFSP8_5_EHS_Msk                                   (0x01UL << SCU_SFSP8_5_EHS_Pos)                           /*!< SCU SFSP8_5: EHS Mask               */
#define SCU_SFSP8_5_EZI_Pos                                   6                                                         /*!< SCU SFSP8_5: EZI Position           */
#define SCU_SFSP8_5_EZI_Msk                                   (0x01UL << SCU_SFSP8_5_EZI_Pos)                           /*!< SCU SFSP8_5: EZI Mask               */
#define SCU_SFSP8_5_EHD_Pos                                   8                                                         /*!< SCU SFSP8_5: EHD Position           */
#define SCU_SFSP8_5_EHD_Msk                                   (0x03UL << SCU_SFSP8_5_EHD_Pos)                           /*!< SCU SFSP8_5: EHD Mask               */

// ---------------------------------------  SCU_SFSP8_6  ------------------------------------------
#define SCU_SFSP8_6_MODE_Pos                                  0                                                         /*!< SCU SFSP8_6: MODE Position          */
#define SCU_SFSP8_6_MODE_Msk                                  (0x07UL << SCU_SFSP8_6_MODE_Pos)                          /*!< SCU SFSP8_6: MODE Mask              */
#define SCU_SFSP8_6_EPD_Pos                                   3                                                         /*!< SCU SFSP8_6: EPD Position           */
#define SCU_SFSP8_6_EPD_Msk                                   (0x01UL << SCU_SFSP8_6_EPD_Pos)                           /*!< SCU SFSP8_6: EPD Mask               */
#define SCU_SFSP8_6_EPUN_Pos                                  4                                                         /*!< SCU SFSP8_6: EPUN Position          */
#define SCU_SFSP8_6_EPUN_Msk                                  (0x01UL << SCU_SFSP8_6_EPUN_Pos)                          /*!< SCU SFSP8_6: EPUN Mask              */
#define SCU_SFSP8_6_EHS_Pos                                   5                                                         /*!< SCU SFSP8_6: EHS Position           */
#define SCU_SFSP8_6_EHS_Msk                                   (0x01UL << SCU_SFSP8_6_EHS_Pos)                           /*!< SCU SFSP8_6: EHS Mask               */
#define SCU_SFSP8_6_EZI_Pos                                   6                                                         /*!< SCU SFSP8_6: EZI Position           */
#define SCU_SFSP8_6_EZI_Msk                                   (0x01UL << SCU_SFSP8_6_EZI_Pos)                           /*!< SCU SFSP8_6: EZI Mask               */
#define SCU_SFSP8_6_EHD_Pos                                   8                                                         /*!< SCU SFSP8_6: EHD Position           */
#define SCU_SFSP8_6_EHD_Msk                                   (0x03UL << SCU_SFSP8_6_EHD_Pos)                           /*!< SCU SFSP8_6: EHD Mask               */

// ---------------------------------------  SCU_SFSP8_7  ------------------------------------------
#define SCU_SFSP8_7_MODE_Pos                                  0                                                         /*!< SCU SFSP8_7: MODE Position          */
#define SCU_SFSP8_7_MODE_Msk                                  (0x07UL << SCU_SFSP8_7_MODE_Pos)                          /*!< SCU SFSP8_7: MODE Mask              */
#define SCU_SFSP8_7_EPD_Pos                                   3                                                         /*!< SCU SFSP8_7: EPD Position           */
#define SCU_SFSP8_7_EPD_Msk                                   (0x01UL << SCU_SFSP8_7_EPD_Pos)                           /*!< SCU SFSP8_7: EPD Mask               */
#define SCU_SFSP8_7_EPUN_Pos                                  4                                                         /*!< SCU SFSP8_7: EPUN Position          */
#define SCU_SFSP8_7_EPUN_Msk                                  (0x01UL << SCU_SFSP8_7_EPUN_Pos)                          /*!< SCU SFSP8_7: EPUN Mask              */
#define SCU_SFSP8_7_EHS_Pos                                   5                                                         /*!< SCU SFSP8_7: EHS Position           */
#define SCU_SFSP8_7_EHS_Msk                                   (0x01UL << SCU_SFSP8_7_EHS_Pos)                           /*!< SCU SFSP8_7: EHS Mask               */
#define SCU_SFSP8_7_EZI_Pos                                   6                                                         /*!< SCU SFSP8_7: EZI Position           */
#define SCU_SFSP8_7_EZI_Msk                                   (0x01UL << SCU_SFSP8_7_EZI_Pos)                           /*!< SCU SFSP8_7: EZI Mask               */
#define SCU_SFSP8_7_EHD_Pos                                   8                                                         /*!< SCU SFSP8_7: EHD Position           */
#define SCU_SFSP8_7_EHD_Msk                                   (0x03UL << SCU_SFSP8_7_EHD_Pos)                           /*!< SCU SFSP8_7: EHD Mask               */

// ---------------------------------------  SCU_SFSP8_8  ------------------------------------------
#define SCU_SFSP8_8_MODE_Pos                                  0                                                         /*!< SCU SFSP8_8: MODE Position          */
#define SCU_SFSP8_8_MODE_Msk                                  (0x07UL << SCU_SFSP8_8_MODE_Pos)                          /*!< SCU SFSP8_8: MODE Mask              */
#define SCU_SFSP8_8_EPD_Pos                                   3                                                         /*!< SCU SFSP8_8: EPD Position           */
#define SCU_SFSP8_8_EPD_Msk                                   (0x01UL << SCU_SFSP8_8_EPD_Pos)                           /*!< SCU SFSP8_8: EPD Mask               */
#define SCU_SFSP8_8_EPUN_Pos                                  4                                                         /*!< SCU SFSP8_8: EPUN Position          */
#define SCU_SFSP8_8_EPUN_Msk                                  (0x01UL << SCU_SFSP8_8_EPUN_Pos)                          /*!< SCU SFSP8_8: EPUN Mask              */
#define SCU_SFSP8_8_EHS_Pos                                   5                                                         /*!< SCU SFSP8_8: EHS Position           */
#define SCU_SFSP8_8_EHS_Msk                                   (0x01UL << SCU_SFSP8_8_EHS_Pos)                           /*!< SCU SFSP8_8: EHS Mask               */
#define SCU_SFSP8_8_EZI_Pos                                   6                                                         /*!< SCU SFSP8_8: EZI Position           */
#define SCU_SFSP8_8_EZI_Msk                                   (0x01UL << SCU_SFSP8_8_EZI_Pos)                           /*!< SCU SFSP8_8: EZI Mask               */
#define SCU_SFSP8_8_EHD_Pos                                   8                                                         /*!< SCU SFSP8_8: EHD Position           */
#define SCU_SFSP8_8_EHD_Msk                                   (0x03UL << SCU_SFSP8_8_EHD_Pos)                           /*!< SCU SFSP8_8: EHD Mask               */

// ---------------------------------------  SCU_SFSP9_0  ------------------------------------------
#define SCU_SFSP9_0_MODE_Pos                                  0                                                         /*!< SCU SFSP9_0: MODE Position          */
#define SCU_SFSP9_0_MODE_Msk                                  (0x07UL << SCU_SFSP9_0_MODE_Pos)                          /*!< SCU SFSP9_0: MODE Mask              */
#define SCU_SFSP9_0_EPD_Pos                                   3                                                         /*!< SCU SFSP9_0: EPD Position           */
#define SCU_SFSP9_0_EPD_Msk                                   (0x01UL << SCU_SFSP9_0_EPD_Pos)                           /*!< SCU SFSP9_0: EPD Mask               */
#define SCU_SFSP9_0_EPUN_Pos                                  4                                                         /*!< SCU SFSP9_0: EPUN Position          */
#define SCU_SFSP9_0_EPUN_Msk                                  (0x01UL << SCU_SFSP9_0_EPUN_Pos)                          /*!< SCU SFSP9_0: EPUN Mask              */
#define SCU_SFSP9_0_EHS_Pos                                   5                                                         /*!< SCU SFSP9_0: EHS Position           */
#define SCU_SFSP9_0_EHS_Msk                                   (0x01UL << SCU_SFSP9_0_EHS_Pos)                           /*!< SCU SFSP9_0: EHS Mask               */
#define SCU_SFSP9_0_EZI_Pos                                   6                                                         /*!< SCU SFSP9_0: EZI Position           */
#define SCU_SFSP9_0_EZI_Msk                                   (0x01UL << SCU_SFSP9_0_EZI_Pos)                           /*!< SCU SFSP9_0: EZI Mask               */
#define SCU_SFSP9_0_EHD_Pos                                   8                                                         /*!< SCU SFSP9_0: EHD Position           */
#define SCU_SFSP9_0_EHD_Msk                                   (0x03UL << SCU_SFSP9_0_EHD_Pos)                           /*!< SCU SFSP9_0: EHD Mask               */

// ---------------------------------------  SCU_SFSP9_1  ------------------------------------------
#define SCU_SFSP9_1_MODE_Pos                                  0                                                         /*!< SCU SFSP9_1: MODE Position          */
#define SCU_SFSP9_1_MODE_Msk                                  (0x07UL << SCU_SFSP9_1_MODE_Pos)                          /*!< SCU SFSP9_1: MODE Mask              */
#define SCU_SFSP9_1_EPD_Pos                                   3                                                         /*!< SCU SFSP9_1: EPD Position           */
#define SCU_SFSP9_1_EPD_Msk                                   (0x01UL << SCU_SFSP9_1_EPD_Pos)                           /*!< SCU SFSP9_1: EPD Mask               */
#define SCU_SFSP9_1_EPUN_Pos                                  4                                                         /*!< SCU SFSP9_1: EPUN Position          */
#define SCU_SFSP9_1_EPUN_Msk                                  (0x01UL << SCU_SFSP9_1_EPUN_Pos)                          /*!< SCU SFSP9_1: EPUN Mask              */
#define SCU_SFSP9_1_EHS_Pos                                   5                                                         /*!< SCU SFSP9_1: EHS Position           */
#define SCU_SFSP9_1_EHS_Msk                                   (0x01UL << SCU_SFSP9_1_EHS_Pos)                           /*!< SCU SFSP9_1: EHS Mask               */
#define SCU_SFSP9_1_EZI_Pos                                   6                                                         /*!< SCU SFSP9_1: EZI Position           */
#define SCU_SFSP9_1_EZI_Msk                                   (0x01UL << SCU_SFSP9_1_EZI_Pos)                           /*!< SCU SFSP9_1: EZI Mask               */
#define SCU_SFSP9_1_EHD_Pos                                   8                                                         /*!< SCU SFSP9_1: EHD Position           */
#define SCU_SFSP9_1_EHD_Msk                                   (0x03UL << SCU_SFSP9_1_EHD_Pos)                           /*!< SCU SFSP9_1: EHD Mask               */

// ---------------------------------------  SCU_SFSP9_2  ------------------------------------------
#define SCU_SFSP9_2_MODE_Pos                                  0                                                         /*!< SCU SFSP9_2: MODE Position          */
#define SCU_SFSP9_2_MODE_Msk                                  (0x07UL << SCU_SFSP9_2_MODE_Pos)                          /*!< SCU SFSP9_2: MODE Mask              */
#define SCU_SFSP9_2_EPD_Pos                                   3                                                         /*!< SCU SFSP9_2: EPD Position           */
#define SCU_SFSP9_2_EPD_Msk                                   (0x01UL << SCU_SFSP9_2_EPD_Pos)                           /*!< SCU SFSP9_2: EPD Mask               */
#define SCU_SFSP9_2_EPUN_Pos                                  4                                                         /*!< SCU SFSP9_2: EPUN Position          */
#define SCU_SFSP9_2_EPUN_Msk                                  (0x01UL << SCU_SFSP9_2_EPUN_Pos)                          /*!< SCU SFSP9_2: EPUN Mask              */
#define SCU_SFSP9_2_EHS_Pos                                   5                                                         /*!< SCU SFSP9_2: EHS Position           */
#define SCU_SFSP9_2_EHS_Msk                                   (0x01UL << SCU_SFSP9_2_EHS_Pos)                           /*!< SCU SFSP9_2: EHS Mask               */
#define SCU_SFSP9_2_EZI_Pos                                   6                                                         /*!< SCU SFSP9_2: EZI Position           */
#define SCU_SFSP9_2_EZI_Msk                                   (0x01UL << SCU_SFSP9_2_EZI_Pos)                           /*!< SCU SFSP9_2: EZI Mask               */
#define SCU_SFSP9_2_EHD_Pos                                   8                                                         /*!< SCU SFSP9_2: EHD Position           */
#define SCU_SFSP9_2_EHD_Msk                                   (0x03UL << SCU_SFSP9_2_EHD_Pos)                           /*!< SCU SFSP9_2: EHD Mask               */

// ---------------------------------------  SCU_SFSP9_3  ------------------------------------------
#define SCU_SFSP9_3_MODE_Pos                                  0                                                         /*!< SCU SFSP9_3: MODE Position          */
#define SCU_SFSP9_3_MODE_Msk                                  (0x07UL << SCU_SFSP9_3_MODE_Pos)                          /*!< SCU SFSP9_3: MODE Mask              */
#define SCU_SFSP9_3_EPD_Pos                                   3                                                         /*!< SCU SFSP9_3: EPD Position           */
#define SCU_SFSP9_3_EPD_Msk                                   (0x01UL << SCU_SFSP9_3_EPD_Pos)                           /*!< SCU SFSP9_3: EPD Mask               */
#define SCU_SFSP9_3_EPUN_Pos                                  4                                                         /*!< SCU SFSP9_3: EPUN Position          */
#define SCU_SFSP9_3_EPUN_Msk                                  (0x01UL << SCU_SFSP9_3_EPUN_Pos)                          /*!< SCU SFSP9_3: EPUN Mask              */
#define SCU_SFSP9_3_EHS_Pos                                   5                                                         /*!< SCU SFSP9_3: EHS Position           */
#define SCU_SFSP9_3_EHS_Msk                                   (0x01UL << SCU_SFSP9_3_EHS_Pos)                           /*!< SCU SFSP9_3: EHS Mask               */
#define SCU_SFSP9_3_EZI_Pos                                   6                                                         /*!< SCU SFSP9_3: EZI Position           */
#define SCU_SFSP9_3_EZI_Msk                                   (0x01UL << SCU_SFSP9_3_EZI_Pos)                           /*!< SCU SFSP9_3: EZI Mask               */
#define SCU_SFSP9_3_EHD_Pos                                   8                                                         /*!< SCU SFSP9_3: EHD Position           */
#define SCU_SFSP9_3_EHD_Msk                                   (0x03UL << SCU_SFSP9_3_EHD_Pos)                           /*!< SCU SFSP9_3: EHD Mask               */

// ---------------------------------------  SCU_SFSP9_4  ------------------------------------------
#define SCU_SFSP9_4_MODE_Pos                                  0                                                         /*!< SCU SFSP9_4: MODE Position          */
#define SCU_SFSP9_4_MODE_Msk                                  (0x07UL << SCU_SFSP9_4_MODE_Pos)                          /*!< SCU SFSP9_4: MODE Mask              */
#define SCU_SFSP9_4_EPD_Pos                                   3                                                         /*!< SCU SFSP9_4: EPD Position           */
#define SCU_SFSP9_4_EPD_Msk                                   (0x01UL << SCU_SFSP9_4_EPD_Pos)                           /*!< SCU SFSP9_4: EPD Mask               */
#define SCU_SFSP9_4_EPUN_Pos                                  4                                                         /*!< SCU SFSP9_4: EPUN Position          */
#define SCU_SFSP9_4_EPUN_Msk                                  (0x01UL << SCU_SFSP9_4_EPUN_Pos)                          /*!< SCU SFSP9_4: EPUN Mask              */
#define SCU_SFSP9_4_EHS_Pos                                   5                                                         /*!< SCU SFSP9_4: EHS Position           */
#define SCU_SFSP9_4_EHS_Msk                                   (0x01UL << SCU_SFSP9_4_EHS_Pos)                           /*!< SCU SFSP9_4: EHS Mask               */
#define SCU_SFSP9_4_EZI_Pos                                   6                                                         /*!< SCU SFSP9_4: EZI Position           */
#define SCU_SFSP9_4_EZI_Msk                                   (0x01UL << SCU_SFSP9_4_EZI_Pos)                           /*!< SCU SFSP9_4: EZI Mask               */
#define SCU_SFSP9_4_EHD_Pos                                   8                                                         /*!< SCU SFSP9_4: EHD Position           */
#define SCU_SFSP9_4_EHD_Msk                                   (0x03UL << SCU_SFSP9_4_EHD_Pos)                           /*!< SCU SFSP9_4: EHD Mask               */

// ---------------------------------------  SCU_SFSP9_5  ------------------------------------------
#define SCU_SFSP9_5_MODE_Pos                                  0                                                         /*!< SCU SFSP9_5: MODE Position          */
#define SCU_SFSP9_5_MODE_Msk                                  (0x07UL << SCU_SFSP9_5_MODE_Pos)                          /*!< SCU SFSP9_5: MODE Mask              */
#define SCU_SFSP9_5_EPD_Pos                                   3                                                         /*!< SCU SFSP9_5: EPD Position           */
#define SCU_SFSP9_5_EPD_Msk                                   (0x01UL << SCU_SFSP9_5_EPD_Pos)                           /*!< SCU SFSP9_5: EPD Mask               */
#define SCU_SFSP9_5_EPUN_Pos                                  4                                                         /*!< SCU SFSP9_5: EPUN Position          */
#define SCU_SFSP9_5_EPUN_Msk                                  (0x01UL << SCU_SFSP9_5_EPUN_Pos)                          /*!< SCU SFSP9_5: EPUN Mask              */
#define SCU_SFSP9_5_EHS_Pos                                   5                                                         /*!< SCU SFSP9_5: EHS Position           */
#define SCU_SFSP9_5_EHS_Msk                                   (0x01UL << SCU_SFSP9_5_EHS_Pos)                           /*!< SCU SFSP9_5: EHS Mask               */
#define SCU_SFSP9_5_EZI_Pos                                   6                                                         /*!< SCU SFSP9_5: EZI Position           */
#define SCU_SFSP9_5_EZI_Msk                                   (0x01UL << SCU_SFSP9_5_EZI_Pos)                           /*!< SCU SFSP9_5: EZI Mask               */
#define SCU_SFSP9_5_EHD_Pos                                   8                                                         /*!< SCU SFSP9_5: EHD Position           */
#define SCU_SFSP9_5_EHD_Msk                                   (0x03UL << SCU_SFSP9_5_EHD_Pos)                           /*!< SCU SFSP9_5: EHD Mask               */

// ---------------------------------------  SCU_SFSP9_6  ------------------------------------------
#define SCU_SFSP9_6_MODE_Pos                                  0                                                         /*!< SCU SFSP9_6: MODE Position          */
#define SCU_SFSP9_6_MODE_Msk                                  (0x07UL << SCU_SFSP9_6_MODE_Pos)                          /*!< SCU SFSP9_6: MODE Mask              */
#define SCU_SFSP9_6_EPD_Pos                                   3                                                         /*!< SCU SFSP9_6: EPD Position           */
#define SCU_SFSP9_6_EPD_Msk                                   (0x01UL << SCU_SFSP9_6_EPD_Pos)                           /*!< SCU SFSP9_6: EPD Mask               */
#define SCU_SFSP9_6_EPUN_Pos                                  4                                                         /*!< SCU SFSP9_6: EPUN Position          */
#define SCU_SFSP9_6_EPUN_Msk                                  (0x01UL << SCU_SFSP9_6_EPUN_Pos)                          /*!< SCU SFSP9_6: EPUN Mask              */
#define SCU_SFSP9_6_EHS_Pos                                   5                                                         /*!< SCU SFSP9_6: EHS Position           */
#define SCU_SFSP9_6_EHS_Msk                                   (0x01UL << SCU_SFSP9_6_EHS_Pos)                           /*!< SCU SFSP9_6: EHS Mask               */
#define SCU_SFSP9_6_EZI_Pos                                   6                                                         /*!< SCU SFSP9_6: EZI Position           */
#define SCU_SFSP9_6_EZI_Msk                                   (0x01UL << SCU_SFSP9_6_EZI_Pos)                           /*!< SCU SFSP9_6: EZI Mask               */
#define SCU_SFSP9_6_EHD_Pos                                   8                                                         /*!< SCU SFSP9_6: EHD Position           */
#define SCU_SFSP9_6_EHD_Msk                                   (0x03UL << SCU_SFSP9_6_EHD_Pos)                           /*!< SCU SFSP9_6: EHD Mask               */

// ---------------------------------------  SCU_SFSPA_0  ------------------------------------------
#define SCU_SFSPA_0_MODE_Pos                                  0                                                         /*!< SCU SFSPA_0: MODE Position          */
#define SCU_SFSPA_0_MODE_Msk                                  (0x07UL << SCU_SFSPA_0_MODE_Pos)                          /*!< SCU SFSPA_0: MODE Mask              */
#define SCU_SFSPA_0_EPD_Pos                                   3                                                         /*!< SCU SFSPA_0: EPD Position           */
#define SCU_SFSPA_0_EPD_Msk                                   (0x01UL << SCU_SFSPA_0_EPD_Pos)                           /*!< SCU SFSPA_0: EPD Mask               */
#define SCU_SFSPA_0_EPUN_Pos                                  4                                                         /*!< SCU SFSPA_0: EPUN Position          */
#define SCU_SFSPA_0_EPUN_Msk                                  (0x01UL << SCU_SFSPA_0_EPUN_Pos)                          /*!< SCU SFSPA_0: EPUN Mask              */
#define SCU_SFSPA_0_EHS_Pos                                   5                                                         /*!< SCU SFSPA_0: EHS Position           */
#define SCU_SFSPA_0_EHS_Msk                                   (0x01UL << SCU_SFSPA_0_EHS_Pos)                           /*!< SCU SFSPA_0: EHS Mask               */
#define SCU_SFSPA_0_EZI_Pos                                   6                                                         /*!< SCU SFSPA_0: EZI Position           */
#define SCU_SFSPA_0_EZI_Msk                                   (0x01UL << SCU_SFSPA_0_EZI_Pos)                           /*!< SCU SFSPA_0: EZI Mask               */
#define SCU_SFSPA_0_EHD_Pos                                   8                                                         /*!< SCU SFSPA_0: EHD Position           */
#define SCU_SFSPA_0_EHD_Msk                                   (0x03UL << SCU_SFSPA_0_EHD_Pos)                           /*!< SCU SFSPA_0: EHD Mask               */

// ---------------------------------------  SCU_SFSPA_1  ------------------------------------------
#define SCU_SFSPA_1_MODE_Pos                                  0                                                         /*!< SCU SFSPA_1: MODE Position          */
#define SCU_SFSPA_1_MODE_Msk                                  (0x07UL << SCU_SFSPA_1_MODE_Pos)                          /*!< SCU SFSPA_1: MODE Mask              */
#define SCU_SFSPA_1_EPD_Pos                                   3                                                         /*!< SCU SFSPA_1: EPD Position           */
#define SCU_SFSPA_1_EPD_Msk                                   (0x01UL << SCU_SFSPA_1_EPD_Pos)                           /*!< SCU SFSPA_1: EPD Mask               */
#define SCU_SFSPA_1_EPUN_Pos                                  4                                                         /*!< SCU SFSPA_1: EPUN Position          */
#define SCU_SFSPA_1_EPUN_Msk                                  (0x01UL << SCU_SFSPA_1_EPUN_Pos)                          /*!< SCU SFSPA_1: EPUN Mask              */
#define SCU_SFSPA_1_EHS_Pos                                   5                                                         /*!< SCU SFSPA_1: EHS Position           */
#define SCU_SFSPA_1_EHS_Msk                                   (0x01UL << SCU_SFSPA_1_EHS_Pos)                           /*!< SCU SFSPA_1: EHS Mask               */
#define SCU_SFSPA_1_EZI_Pos                                   6                                                         /*!< SCU SFSPA_1: EZI Position           */
#define SCU_SFSPA_1_EZI_Msk                                   (0x01UL << SCU_SFSPA_1_EZI_Pos)                           /*!< SCU SFSPA_1: EZI Mask               */
#define SCU_SFSPA_1_EHD_Pos                                   8                                                         /*!< SCU SFSPA_1: EHD Position           */
#define SCU_SFSPA_1_EHD_Msk                                   (0x03UL << SCU_SFSPA_1_EHD_Pos)                           /*!< SCU SFSPA_1: EHD Mask               */

// ---------------------------------------  SCU_SFSPA_2  ------------------------------------------
#define SCU_SFSPA_2_MODE_Pos                                  0                                                         /*!< SCU SFSPA_2: MODE Position          */
#define SCU_SFSPA_2_MODE_Msk                                  (0x07UL << SCU_SFSPA_2_MODE_Pos)                          /*!< SCU SFSPA_2: MODE Mask              */
#define SCU_SFSPA_2_EPD_Pos                                   3                                                         /*!< SCU SFSPA_2: EPD Position           */
#define SCU_SFSPA_2_EPD_Msk                                   (0x01UL << SCU_SFSPA_2_EPD_Pos)                           /*!< SCU SFSPA_2: EPD Mask               */
#define SCU_SFSPA_2_EPUN_Pos                                  4                                                         /*!< SCU SFSPA_2: EPUN Position          */
#define SCU_SFSPA_2_EPUN_Msk                                  (0x01UL << SCU_SFSPA_2_EPUN_Pos)                          /*!< SCU SFSPA_2: EPUN Mask              */
#define SCU_SFSPA_2_EHS_Pos                                   5                                                         /*!< SCU SFSPA_2: EHS Position           */
#define SCU_SFSPA_2_EHS_Msk                                   (0x01UL << SCU_SFSPA_2_EHS_Pos)                           /*!< SCU SFSPA_2: EHS Mask               */
#define SCU_SFSPA_2_EZI_Pos                                   6                                                         /*!< SCU SFSPA_2: EZI Position           */
#define SCU_SFSPA_2_EZI_Msk                                   (0x01UL << SCU_SFSPA_2_EZI_Pos)                           /*!< SCU SFSPA_2: EZI Mask               */
#define SCU_SFSPA_2_EHD_Pos                                   8                                                         /*!< SCU SFSPA_2: EHD Position           */
#define SCU_SFSPA_2_EHD_Msk                                   (0x03UL << SCU_SFSPA_2_EHD_Pos)                           /*!< SCU SFSPA_2: EHD Mask               */

// ---------------------------------------  SCU_SFSPA_3  ------------------------------------------
#define SCU_SFSPA_3_MODE_Pos                                  0                                                         /*!< SCU SFSPA_3: MODE Position          */
#define SCU_SFSPA_3_MODE_Msk                                  (0x07UL << SCU_SFSPA_3_MODE_Pos)                          /*!< SCU SFSPA_3: MODE Mask              */
#define SCU_SFSPA_3_EPD_Pos                                   3                                                         /*!< SCU SFSPA_3: EPD Position           */
#define SCU_SFSPA_3_EPD_Msk                                   (0x01UL << SCU_SFSPA_3_EPD_Pos)                           /*!< SCU SFSPA_3: EPD Mask               */
#define SCU_SFSPA_3_EPUN_Pos                                  4                                                         /*!< SCU SFSPA_3: EPUN Position          */
#define SCU_SFSPA_3_EPUN_Msk                                  (0x01UL << SCU_SFSPA_3_EPUN_Pos)                          /*!< SCU SFSPA_3: EPUN Mask              */
#define SCU_SFSPA_3_EHS_Pos                                   5                                                         /*!< SCU SFSPA_3: EHS Position           */
#define SCU_SFSPA_3_EHS_Msk                                   (0x01UL << SCU_SFSPA_3_EHS_Pos)                           /*!< SCU SFSPA_3: EHS Mask               */
#define SCU_SFSPA_3_EZI_Pos                                   6                                                         /*!< SCU SFSPA_3: EZI Position           */
#define SCU_SFSPA_3_EZI_Msk                                   (0x01UL << SCU_SFSPA_3_EZI_Pos)                           /*!< SCU SFSPA_3: EZI Mask               */
#define SCU_SFSPA_3_EHD_Pos                                   8                                                         /*!< SCU SFSPA_3: EHD Position           */
#define SCU_SFSPA_3_EHD_Msk                                   (0x03UL << SCU_SFSPA_3_EHD_Pos)                           /*!< SCU SFSPA_3: EHD Mask               */

// ---------------------------------------  SCU_SFSPA_4  ------------------------------------------
#define SCU_SFSPA_4_MODE_Pos                                  0                                                         /*!< SCU SFSPA_4: MODE Position          */
#define SCU_SFSPA_4_MODE_Msk                                  (0x07UL << SCU_SFSPA_4_MODE_Pos)                          /*!< SCU SFSPA_4: MODE Mask              */
#define SCU_SFSPA_4_EPD_Pos                                   3                                                         /*!< SCU SFSPA_4: EPD Position           */
#define SCU_SFSPA_4_EPD_Msk                                   (0x01UL << SCU_SFSPA_4_EPD_Pos)                           /*!< SCU SFSPA_4: EPD Mask               */
#define SCU_SFSPA_4_EPUN_Pos                                  4                                                         /*!< SCU SFSPA_4: EPUN Position          */
#define SCU_SFSPA_4_EPUN_Msk                                  (0x01UL << SCU_SFSPA_4_EPUN_Pos)                          /*!< SCU SFSPA_4: EPUN Mask              */
#define SCU_SFSPA_4_EHS_Pos                                   5                                                         /*!< SCU SFSPA_4: EHS Position           */
#define SCU_SFSPA_4_EHS_Msk                                   (0x01UL << SCU_SFSPA_4_EHS_Pos)                           /*!< SCU SFSPA_4: EHS Mask               */
#define SCU_SFSPA_4_EZI_Pos                                   6                                                         /*!< SCU SFSPA_4: EZI Position           */
#define SCU_SFSPA_4_EZI_Msk                                   (0x01UL << SCU_SFSPA_4_EZI_Pos)                           /*!< SCU SFSPA_4: EZI Mask               */
#define SCU_SFSPA_4_EHD_Pos                                   8                                                         /*!< SCU SFSPA_4: EHD Position           */
#define SCU_SFSPA_4_EHD_Msk                                   (0x03UL << SCU_SFSPA_4_EHD_Pos)                           /*!< SCU SFSPA_4: EHD Mask               */

// ---------------------------------------  SCU_SFSPB_0  ------------------------------------------
#define SCU_SFSPB_0_MODE_Pos                                  0                                                         /*!< SCU SFSPB_0: MODE Position          */
#define SCU_SFSPB_0_MODE_Msk                                  (0x07UL << SCU_SFSPB_0_MODE_Pos)                          /*!< SCU SFSPB_0: MODE Mask              */
#define SCU_SFSPB_0_EPD_Pos                                   3                                                         /*!< SCU SFSPB_0: EPD Position           */
#define SCU_SFSPB_0_EPD_Msk                                   (0x01UL << SCU_SFSPB_0_EPD_Pos)                           /*!< SCU SFSPB_0: EPD Mask               */
#define SCU_SFSPB_0_EPUN_Pos                                  4                                                         /*!< SCU SFSPB_0: EPUN Position          */
#define SCU_SFSPB_0_EPUN_Msk                                  (0x01UL << SCU_SFSPB_0_EPUN_Pos)                          /*!< SCU SFSPB_0: EPUN Mask              */
#define SCU_SFSPB_0_EHS_Pos                                   5                                                         /*!< SCU SFSPB_0: EHS Position           */
#define SCU_SFSPB_0_EHS_Msk                                   (0x01UL << SCU_SFSPB_0_EHS_Pos)                           /*!< SCU SFSPB_0: EHS Mask               */
#define SCU_SFSPB_0_EZI_Pos                                   6                                                         /*!< SCU SFSPB_0: EZI Position           */
#define SCU_SFSPB_0_EZI_Msk                                   (0x01UL << SCU_SFSPB_0_EZI_Pos)                           /*!< SCU SFSPB_0: EZI Mask               */
#define SCU_SFSPB_0_EHD_Pos                                   8                                                         /*!< SCU SFSPB_0: EHD Position           */
#define SCU_SFSPB_0_EHD_Msk                                   (0x03UL << SCU_SFSPB_0_EHD_Pos)                           /*!< SCU SFSPB_0: EHD Mask               */

// ---------------------------------------  SCU_SFSPB_1  ------------------------------------------
#define SCU_SFSPB_1_MODE_Pos                                  0                                                         /*!< SCU SFSPB_1: MODE Position          */
#define SCU_SFSPB_1_MODE_Msk                                  (0x07UL << SCU_SFSPB_1_MODE_Pos)                          /*!< SCU SFSPB_1: MODE Mask              */
#define SCU_SFSPB_1_EPD_Pos                                   3                                                         /*!< SCU SFSPB_1: EPD Position           */
#define SCU_SFSPB_1_EPD_Msk                                   (0x01UL << SCU_SFSPB_1_EPD_Pos)                           /*!< SCU SFSPB_1: EPD Mask               */
#define SCU_SFSPB_1_EPUN_Pos                                  4                                                         /*!< SCU SFSPB_1: EPUN Position          */
#define SCU_SFSPB_1_EPUN_Msk                                  (0x01UL << SCU_SFSPB_1_EPUN_Pos)                          /*!< SCU SFSPB_1: EPUN Mask              */
#define SCU_SFSPB_1_EHS_Pos                                   5                                                         /*!< SCU SFSPB_1: EHS Position           */
#define SCU_SFSPB_1_EHS_Msk                                   (0x01UL << SCU_SFSPB_1_EHS_Pos)                           /*!< SCU SFSPB_1: EHS Mask               */
#define SCU_SFSPB_1_EZI_Pos                                   6                                                         /*!< SCU SFSPB_1: EZI Position           */
#define SCU_SFSPB_1_EZI_Msk                                   (0x01UL << SCU_SFSPB_1_EZI_Pos)                           /*!< SCU SFSPB_1: EZI Mask               */
#define SCU_SFSPB_1_EHD_Pos                                   8                                                         /*!< SCU SFSPB_1: EHD Position           */
#define SCU_SFSPB_1_EHD_Msk                                   (0x03UL << SCU_SFSPB_1_EHD_Pos)                           /*!< SCU SFSPB_1: EHD Mask               */

// ---------------------------------------  SCU_SFSPB_2  ------------------------------------------
#define SCU_SFSPB_2_MODE_Pos                                  0                                                         /*!< SCU SFSPB_2: MODE Position          */
#define SCU_SFSPB_2_MODE_Msk                                  (0x07UL << SCU_SFSPB_2_MODE_Pos)                          /*!< SCU SFSPB_2: MODE Mask              */
#define SCU_SFSPB_2_EPD_Pos                                   3                                                         /*!< SCU SFSPB_2: EPD Position           */
#define SCU_SFSPB_2_EPD_Msk                                   (0x01UL << SCU_SFSPB_2_EPD_Pos)                           /*!< SCU SFSPB_2: EPD Mask               */
#define SCU_SFSPB_2_EPUN_Pos                                  4                                                         /*!< SCU SFSPB_2: EPUN Position          */
#define SCU_SFSPB_2_EPUN_Msk                                  (0x01UL << SCU_SFSPB_2_EPUN_Pos)                          /*!< SCU SFSPB_2: EPUN Mask              */
#define SCU_SFSPB_2_EHS_Pos                                   5                                                         /*!< SCU SFSPB_2: EHS Position           */
#define SCU_SFSPB_2_EHS_Msk                                   (0x01UL << SCU_SFSPB_2_EHS_Pos)                           /*!< SCU SFSPB_2: EHS Mask               */
#define SCU_SFSPB_2_EZI_Pos                                   6                                                         /*!< SCU SFSPB_2: EZI Position           */
#define SCU_SFSPB_2_EZI_Msk                                   (0x01UL << SCU_SFSPB_2_EZI_Pos)                           /*!< SCU SFSPB_2: EZI Mask               */
#define SCU_SFSPB_2_EHD_Pos                                   8                                                         /*!< SCU SFSPB_2: EHD Position           */
#define SCU_SFSPB_2_EHD_Msk                                   (0x03UL << SCU_SFSPB_2_EHD_Pos)                           /*!< SCU SFSPB_2: EHD Mask               */

// ---------------------------------------  SCU_SFSPB_3  ------------------------------------------
#define SCU_SFSPB_3_MODE_Pos                                  0                                                         /*!< SCU SFSPB_3: MODE Position          */
#define SCU_SFSPB_3_MODE_Msk                                  (0x07UL << SCU_SFSPB_3_MODE_Pos)                          /*!< SCU SFSPB_3: MODE Mask              */
#define SCU_SFSPB_3_EPD_Pos                                   3                                                         /*!< SCU SFSPB_3: EPD Position           */
#define SCU_SFSPB_3_EPD_Msk                                   (0x01UL << SCU_SFSPB_3_EPD_Pos)                           /*!< SCU SFSPB_3: EPD Mask               */
#define SCU_SFSPB_3_EPUN_Pos                                  4                                                         /*!< SCU SFSPB_3: EPUN Position          */
#define SCU_SFSPB_3_EPUN_Msk                                  (0x01UL << SCU_SFSPB_3_EPUN_Pos)                          /*!< SCU SFSPB_3: EPUN Mask              */
#define SCU_SFSPB_3_EHS_Pos                                   5                                                         /*!< SCU SFSPB_3: EHS Position           */
#define SCU_SFSPB_3_EHS_Msk                                   (0x01UL << SCU_SFSPB_3_EHS_Pos)                           /*!< SCU SFSPB_3: EHS Mask               */
#define SCU_SFSPB_3_EZI_Pos                                   6                                                         /*!< SCU SFSPB_3: EZI Position           */
#define SCU_SFSPB_3_EZI_Msk                                   (0x01UL << SCU_SFSPB_3_EZI_Pos)                           /*!< SCU SFSPB_3: EZI Mask               */
#define SCU_SFSPB_3_EHD_Pos                                   8                                                         /*!< SCU SFSPB_3: EHD Position           */
#define SCU_SFSPB_3_EHD_Msk                                   (0x03UL << SCU_SFSPB_3_EHD_Pos)                           /*!< SCU SFSPB_3: EHD Mask               */

// ---------------------------------------  SCU_SFSPB_4  ------------------------------------------
#define SCU_SFSPB_4_MODE_Pos                                  0                                                         /*!< SCU SFSPB_4: MODE Position          */
#define SCU_SFSPB_4_MODE_Msk                                  (0x07UL << SCU_SFSPB_4_MODE_Pos)                          /*!< SCU SFSPB_4: MODE Mask              */
#define SCU_SFSPB_4_EPD_Pos                                   3                                                         /*!< SCU SFSPB_4: EPD Position           */
#define SCU_SFSPB_4_EPD_Msk                                   (0x01UL << SCU_SFSPB_4_EPD_Pos)                           /*!< SCU SFSPB_4: EPD Mask               */
#define SCU_SFSPB_4_EPUN_Pos                                  4                                                         /*!< SCU SFSPB_4: EPUN Position          */
#define SCU_SFSPB_4_EPUN_Msk                                  (0x01UL << SCU_SFSPB_4_EPUN_Pos)                          /*!< SCU SFSPB_4: EPUN Mask              */
#define SCU_SFSPB_4_EHS_Pos                                   5                                                         /*!< SCU SFSPB_4: EHS Position           */
#define SCU_SFSPB_4_EHS_Msk                                   (0x01UL << SCU_SFSPB_4_EHS_Pos)                           /*!< SCU SFSPB_4: EHS Mask               */
#define SCU_SFSPB_4_EZI_Pos                                   6                                                         /*!< SCU SFSPB_4: EZI Position           */
#define SCU_SFSPB_4_EZI_Msk                                   (0x01UL << SCU_SFSPB_4_EZI_Pos)                           /*!< SCU SFSPB_4: EZI Mask               */
#define SCU_SFSPB_4_EHD_Pos                                   8                                                         /*!< SCU SFSPB_4: EHD Position           */
#define SCU_SFSPB_4_EHD_Msk                                   (0x03UL << SCU_SFSPB_4_EHD_Pos)                           /*!< SCU SFSPB_4: EHD Mask               */

// ---------------------------------------  SCU_SFSPB_5  ------------------------------------------
#define SCU_SFSPB_5_MODE_Pos                                  0                                                         /*!< SCU SFSPB_5: MODE Position          */
#define SCU_SFSPB_5_MODE_Msk                                  (0x07UL << SCU_SFSPB_5_MODE_Pos)                          /*!< SCU SFSPB_5: MODE Mask              */
#define SCU_SFSPB_5_EPD_Pos                                   3                                                         /*!< SCU SFSPB_5: EPD Position           */
#define SCU_SFSPB_5_EPD_Msk                                   (0x01UL << SCU_SFSPB_5_EPD_Pos)                           /*!< SCU SFSPB_5: EPD Mask               */
#define SCU_SFSPB_5_EPUN_Pos                                  4                                                         /*!< SCU SFSPB_5: EPUN Position          */
#define SCU_SFSPB_5_EPUN_Msk                                  (0x01UL << SCU_SFSPB_5_EPUN_Pos)                          /*!< SCU SFSPB_5: EPUN Mask              */
#define SCU_SFSPB_5_EHS_Pos                                   5                                                         /*!< SCU SFSPB_5: EHS Position           */
#define SCU_SFSPB_5_EHS_Msk                                   (0x01UL << SCU_SFSPB_5_EHS_Pos)                           /*!< SCU SFSPB_5: EHS Mask               */
#define SCU_SFSPB_5_EZI_Pos                                   6                                                         /*!< SCU SFSPB_5: EZI Position           */
#define SCU_SFSPB_5_EZI_Msk                                   (0x01UL << SCU_SFSPB_5_EZI_Pos)                           /*!< SCU SFSPB_5: EZI Mask               */
#define SCU_SFSPB_5_EHD_Pos                                   8                                                         /*!< SCU SFSPB_5: EHD Position           */
#define SCU_SFSPB_5_EHD_Msk                                   (0x03UL << SCU_SFSPB_5_EHD_Pos)                           /*!< SCU SFSPB_5: EHD Mask               */

// ---------------------------------------  SCU_SFSPB_6  ------------------------------------------
#define SCU_SFSPB_6_MODE_Pos                                  0                                                         /*!< SCU SFSPB_6: MODE Position          */
#define SCU_SFSPB_6_MODE_Msk                                  (0x07UL << SCU_SFSPB_6_MODE_Pos)                          /*!< SCU SFSPB_6: MODE Mask              */
#define SCU_SFSPB_6_EPD_Pos                                   3                                                         /*!< SCU SFSPB_6: EPD Position           */
#define SCU_SFSPB_6_EPD_Msk                                   (0x01UL << SCU_SFSPB_6_EPD_Pos)                           /*!< SCU SFSPB_6: EPD Mask               */
#define SCU_SFSPB_6_EPUN_Pos                                  4                                                         /*!< SCU SFSPB_6: EPUN Position          */
#define SCU_SFSPB_6_EPUN_Msk                                  (0x01UL << SCU_SFSPB_6_EPUN_Pos)                          /*!< SCU SFSPB_6: EPUN Mask              */
#define SCU_SFSPB_6_EHS_Pos                                   5                                                         /*!< SCU SFSPB_6: EHS Position           */
#define SCU_SFSPB_6_EHS_Msk                                   (0x01UL << SCU_SFSPB_6_EHS_Pos)                           /*!< SCU SFSPB_6: EHS Mask               */
#define SCU_SFSPB_6_EZI_Pos                                   6                                                         /*!< SCU SFSPB_6: EZI Position           */
#define SCU_SFSPB_6_EZI_Msk                                   (0x01UL << SCU_SFSPB_6_EZI_Pos)                           /*!< SCU SFSPB_6: EZI Mask               */
#define SCU_SFSPB_6_EHD_Pos                                   8                                                         /*!< SCU SFSPB_6: EHD Position           */
#define SCU_SFSPB_6_EHD_Msk                                   (0x03UL << SCU_SFSPB_6_EHD_Pos)                           /*!< SCU SFSPB_6: EHD Mask               */

// ---------------------------------------  SCU_SFSPC_0  ------------------------------------------
#define SCU_SFSPC_0_MODE_Pos                                  0                                                         /*!< SCU SFSPC_0: MODE Position          */
#define SCU_SFSPC_0_MODE_Msk                                  (0x07UL << SCU_SFSPC_0_MODE_Pos)                          /*!< SCU SFSPC_0: MODE Mask              */
#define SCU_SFSPC_0_EPD_Pos                                   3                                                         /*!< SCU SFSPC_0: EPD Position           */
#define SCU_SFSPC_0_EPD_Msk                                   (0x01UL << SCU_SFSPC_0_EPD_Pos)                           /*!< SCU SFSPC_0: EPD Mask               */
#define SCU_SFSPC_0_EPUN_Pos                                  4                                                         /*!< SCU SFSPC_0: EPUN Position          */
#define SCU_SFSPC_0_EPUN_Msk                                  (0x01UL << SCU_SFSPC_0_EPUN_Pos)                          /*!< SCU SFSPC_0: EPUN Mask              */
#define SCU_SFSPC_0_EHS_Pos                                   5                                                         /*!< SCU SFSPC_0: EHS Position           */
#define SCU_SFSPC_0_EHS_Msk                                   (0x01UL << SCU_SFSPC_0_EHS_Pos)                           /*!< SCU SFSPC_0: EHS Mask               */
#define SCU_SFSPC_0_EZI_Pos                                   6                                                         /*!< SCU SFSPC_0: EZI Position           */
#define SCU_SFSPC_0_EZI_Msk                                   (0x01UL << SCU_SFSPC_0_EZI_Pos)                           /*!< SCU SFSPC_0: EZI Mask               */
#define SCU_SFSPC_0_EHD_Pos                                   8                                                         /*!< SCU SFSPC_0: EHD Position           */
#define SCU_SFSPC_0_EHD_Msk                                   (0x03UL << SCU_SFSPC_0_EHD_Pos)                           /*!< SCU SFSPC_0: EHD Mask               */

// ---------------------------------------  SCU_SFSPC_1  ------------------------------------------
#define SCU_SFSPC_1_MODE_Pos                                  0                                                         /*!< SCU SFSPC_1: MODE Position          */
#define SCU_SFSPC_1_MODE_Msk                                  (0x07UL << SCU_SFSPC_1_MODE_Pos)                          /*!< SCU SFSPC_1: MODE Mask              */
#define SCU_SFSPC_1_EPD_Pos                                   3                                                         /*!< SCU SFSPC_1: EPD Position           */
#define SCU_SFSPC_1_EPD_Msk                                   (0x01UL << SCU_SFSPC_1_EPD_Pos)                           /*!< SCU SFSPC_1: EPD Mask               */
#define SCU_SFSPC_1_EPUN_Pos                                  4                                                         /*!< SCU SFSPC_1: EPUN Position          */
#define SCU_SFSPC_1_EPUN_Msk                                  (0x01UL << SCU_SFSPC_1_EPUN_Pos)                          /*!< SCU SFSPC_1: EPUN Mask              */
#define SCU_SFSPC_1_EHS_Pos                                   5                                                         /*!< SCU SFSPC_1: EHS Position           */
#define SCU_SFSPC_1_EHS_Msk                                   (0x01UL << SCU_SFSPC_1_EHS_Pos)                           /*!< SCU SFSPC_1: EHS Mask               */
#define SCU_SFSPC_1_EZI_Pos                                   6                                                         /*!< SCU SFSPC_1: EZI Position           */
#define SCU_SFSPC_1_EZI_Msk                                   (0x01UL << SCU_SFSPC_1_EZI_Pos)                           /*!< SCU SFSPC_1: EZI Mask               */
#define SCU_SFSPC_1_EHD_Pos                                   8                                                         /*!< SCU SFSPC_1: EHD Position           */
#define SCU_SFSPC_1_EHD_Msk                                   (0x03UL << SCU_SFSPC_1_EHD_Pos)                           /*!< SCU SFSPC_1: EHD Mask               */

// ---------------------------------------  SCU_SFSPC_2  ------------------------------------------
#define SCU_SFSPC_2_MODE_Pos                                  0                                                         /*!< SCU SFSPC_2: MODE Position          */
#define SCU_SFSPC_2_MODE_Msk                                  (0x07UL << SCU_SFSPC_2_MODE_Pos)                          /*!< SCU SFSPC_2: MODE Mask              */
#define SCU_SFSPC_2_EPD_Pos                                   3                                                         /*!< SCU SFSPC_2: EPD Position           */
#define SCU_SFSPC_2_EPD_Msk                                   (0x01UL << SCU_SFSPC_2_EPD_Pos)                           /*!< SCU SFSPC_2: EPD Mask               */
#define SCU_SFSPC_2_EPUN_Pos                                  4                                                         /*!< SCU SFSPC_2: EPUN Position          */
#define SCU_SFSPC_2_EPUN_Msk                                  (0x01UL << SCU_SFSPC_2_EPUN_Pos)                          /*!< SCU SFSPC_2: EPUN Mask              */
#define SCU_SFSPC_2_EHS_Pos                                   5                                                         /*!< SCU SFSPC_2: EHS Position           */
#define SCU_SFSPC_2_EHS_Msk                                   (0x01UL << SCU_SFSPC_2_EHS_Pos)                           /*!< SCU SFSPC_2: EHS Mask               */
#define SCU_SFSPC_2_EZI_Pos                                   6                                                         /*!< SCU SFSPC_2: EZI Position           */
#define SCU_SFSPC_2_EZI_Msk                                   (0x01UL << SCU_SFSPC_2_EZI_Pos)                           /*!< SCU SFSPC_2: EZI Mask               */
#define SCU_SFSPC_2_EHD_Pos                                   8                                                         /*!< SCU SFSPC_2: EHD Position           */
#define SCU_SFSPC_2_EHD_Msk                                   (0x03UL << SCU_SFSPC_2_EHD_Pos)                           /*!< SCU SFSPC_2: EHD Mask               */

// ---------------------------------------  SCU_SFSPC_3  ------------------------------------------
#define SCU_SFSPC_3_MODE_Pos                                  0                                                         /*!< SCU SFSPC_3: MODE Position          */
#define SCU_SFSPC_3_MODE_Msk                                  (0x07UL << SCU_SFSPC_3_MODE_Pos)                          /*!< SCU SFSPC_3: MODE Mask              */
#define SCU_SFSPC_3_EPD_Pos                                   3                                                         /*!< SCU SFSPC_3: EPD Position           */
#define SCU_SFSPC_3_EPD_Msk                                   (0x01UL << SCU_SFSPC_3_EPD_Pos)                           /*!< SCU SFSPC_3: EPD Mask               */
#define SCU_SFSPC_3_EPUN_Pos                                  4                                                         /*!< SCU SFSPC_3: EPUN Position          */
#define SCU_SFSPC_3_EPUN_Msk                                  (0x01UL << SCU_SFSPC_3_EPUN_Pos)                          /*!< SCU SFSPC_3: EPUN Mask              */
#define SCU_SFSPC_3_EHS_Pos                                   5                                                         /*!< SCU SFSPC_3: EHS Position           */
#define SCU_SFSPC_3_EHS_Msk                                   (0x01UL << SCU_SFSPC_3_EHS_Pos)                           /*!< SCU SFSPC_3: EHS Mask               */
#define SCU_SFSPC_3_EZI_Pos                                   6                                                         /*!< SCU SFSPC_3: EZI Position           */
#define SCU_SFSPC_3_EZI_Msk                                   (0x01UL << SCU_SFSPC_3_EZI_Pos)                           /*!< SCU SFSPC_3: EZI Mask               */
#define SCU_SFSPC_3_EHD_Pos                                   8                                                         /*!< SCU SFSPC_3: EHD Position           */
#define SCU_SFSPC_3_EHD_Msk                                   (0x03UL << SCU_SFSPC_3_EHD_Pos)                           /*!< SCU SFSPC_3: EHD Mask               */

// ---------------------------------------  SCU_SFSPC_4  ------------------------------------------
#define SCU_SFSPC_4_MODE_Pos                                  0                                                         /*!< SCU SFSPC_4: MODE Position          */
#define SCU_SFSPC_4_MODE_Msk                                  (0x07UL << SCU_SFSPC_4_MODE_Pos)                          /*!< SCU SFSPC_4: MODE Mask              */
#define SCU_SFSPC_4_EPD_Pos                                   3                                                         /*!< SCU SFSPC_4: EPD Position           */
#define SCU_SFSPC_4_EPD_Msk                                   (0x01UL << SCU_SFSPC_4_EPD_Pos)                           /*!< SCU SFSPC_4: EPD Mask               */
#define SCU_SFSPC_4_EPUN_Pos                                  4                                                         /*!< SCU SFSPC_4: EPUN Position          */
#define SCU_SFSPC_4_EPUN_Msk                                  (0x01UL << SCU_SFSPC_4_EPUN_Pos)                          /*!< SCU SFSPC_4: EPUN Mask              */
#define SCU_SFSPC_4_EHS_Pos                                   5                                                         /*!< SCU SFSPC_4: EHS Position           */
#define SCU_SFSPC_4_EHS_Msk                                   (0x01UL << SCU_SFSPC_4_EHS_Pos)                           /*!< SCU SFSPC_4: EHS Mask               */
#define SCU_SFSPC_4_EZI_Pos                                   6                                                         /*!< SCU SFSPC_4: EZI Position           */
#define SCU_SFSPC_4_EZI_Msk                                   (0x01UL << SCU_SFSPC_4_EZI_Pos)                           /*!< SCU SFSPC_4: EZI Mask               */
#define SCU_SFSPC_4_EHD_Pos                                   8                                                         /*!< SCU SFSPC_4: EHD Position           */
#define SCU_SFSPC_4_EHD_Msk                                   (0x03UL << SCU_SFSPC_4_EHD_Pos)                           /*!< SCU SFSPC_4: EHD Mask               */

// ---------------------------------------  SCU_SFSPC_5  ------------------------------------------
#define SCU_SFSPC_5_MODE_Pos                                  0                                                         /*!< SCU SFSPC_5: MODE Position          */
#define SCU_SFSPC_5_MODE_Msk                                  (0x07UL << SCU_SFSPC_5_MODE_Pos)                          /*!< SCU SFSPC_5: MODE Mask              */
#define SCU_SFSPC_5_EPD_Pos                                   3                                                         /*!< SCU SFSPC_5: EPD Position           */
#define SCU_SFSPC_5_EPD_Msk                                   (0x01UL << SCU_SFSPC_5_EPD_Pos)                           /*!< SCU SFSPC_5: EPD Mask               */
#define SCU_SFSPC_5_EPUN_Pos                                  4                                                         /*!< SCU SFSPC_5: EPUN Position          */
#define SCU_SFSPC_5_EPUN_Msk                                  (0x01UL << SCU_SFSPC_5_EPUN_Pos)                          /*!< SCU SFSPC_5: EPUN Mask              */
#define SCU_SFSPC_5_EHS_Pos                                   5                                                         /*!< SCU SFSPC_5: EHS Position           */
#define SCU_SFSPC_5_EHS_Msk                                   (0x01UL << SCU_SFSPC_5_EHS_Pos)                           /*!< SCU SFSPC_5: EHS Mask               */
#define SCU_SFSPC_5_EZI_Pos                                   6                                                         /*!< SCU SFSPC_5: EZI Position           */
#define SCU_SFSPC_5_EZI_Msk                                   (0x01UL << SCU_SFSPC_5_EZI_Pos)                           /*!< SCU SFSPC_5: EZI Mask               */
#define SCU_SFSPC_5_EHD_Pos                                   8                                                         /*!< SCU SFSPC_5: EHD Position           */
#define SCU_SFSPC_5_EHD_Msk                                   (0x03UL << SCU_SFSPC_5_EHD_Pos)                           /*!< SCU SFSPC_5: EHD Mask               */

// ---------------------------------------  SCU_SFSPC_6  ------------------------------------------
#define SCU_SFSPC_6_MODE_Pos                                  0                                                         /*!< SCU SFSPC_6: MODE Position          */
#define SCU_SFSPC_6_MODE_Msk                                  (0x07UL << SCU_SFSPC_6_MODE_Pos)                          /*!< SCU SFSPC_6: MODE Mask              */
#define SCU_SFSPC_6_EPD_Pos                                   3                                                         /*!< SCU SFSPC_6: EPD Position           */
#define SCU_SFSPC_6_EPD_Msk                                   (0x01UL << SCU_SFSPC_6_EPD_Pos)                           /*!< SCU SFSPC_6: EPD Mask               */
#define SCU_SFSPC_6_EPUN_Pos                                  4                                                         /*!< SCU SFSPC_6: EPUN Position          */
#define SCU_SFSPC_6_EPUN_Msk                                  (0x01UL << SCU_SFSPC_6_EPUN_Pos)                          /*!< SCU SFSPC_6: EPUN Mask              */
#define SCU_SFSPC_6_EHS_Pos                                   5                                                         /*!< SCU SFSPC_6: EHS Position           */
#define SCU_SFSPC_6_EHS_Msk                                   (0x01UL << SCU_SFSPC_6_EHS_Pos)                           /*!< SCU SFSPC_6: EHS Mask               */
#define SCU_SFSPC_6_EZI_Pos                                   6                                                         /*!< SCU SFSPC_6: EZI Position           */
#define SCU_SFSPC_6_EZI_Msk                                   (0x01UL << SCU_SFSPC_6_EZI_Pos)                           /*!< SCU SFSPC_6: EZI Mask               */
#define SCU_SFSPC_6_EHD_Pos                                   8                                                         /*!< SCU SFSPC_6: EHD Position           */
#define SCU_SFSPC_6_EHD_Msk                                   (0x03UL << SCU_SFSPC_6_EHD_Pos)                           /*!< SCU SFSPC_6: EHD Mask               */

// ---------------------------------------  SCU_SFSPC_7  ------------------------------------------
#define SCU_SFSPC_7_MODE_Pos                                  0                                                         /*!< SCU SFSPC_7: MODE Position          */
#define SCU_SFSPC_7_MODE_Msk                                  (0x07UL << SCU_SFSPC_7_MODE_Pos)                          /*!< SCU SFSPC_7: MODE Mask              */
#define SCU_SFSPC_7_EPD_Pos                                   3                                                         /*!< SCU SFSPC_7: EPD Position           */
#define SCU_SFSPC_7_EPD_Msk                                   (0x01UL << SCU_SFSPC_7_EPD_Pos)                           /*!< SCU SFSPC_7: EPD Mask               */
#define SCU_SFSPC_7_EPUN_Pos                                  4                                                         /*!< SCU SFSPC_7: EPUN Position          */
#define SCU_SFSPC_7_EPUN_Msk                                  (0x01UL << SCU_SFSPC_7_EPUN_Pos)                          /*!< SCU SFSPC_7: EPUN Mask              */
#define SCU_SFSPC_7_EHS_Pos                                   5                                                         /*!< SCU SFSPC_7: EHS Position           */
#define SCU_SFSPC_7_EHS_Msk                                   (0x01UL << SCU_SFSPC_7_EHS_Pos)                           /*!< SCU SFSPC_7: EHS Mask               */
#define SCU_SFSPC_7_EZI_Pos                                   6                                                         /*!< SCU SFSPC_7: EZI Position           */
#define SCU_SFSPC_7_EZI_Msk                                   (0x01UL << SCU_SFSPC_7_EZI_Pos)                           /*!< SCU SFSPC_7: EZI Mask               */
#define SCU_SFSPC_7_EHD_Pos                                   8                                                         /*!< SCU SFSPC_7: EHD Position           */
#define SCU_SFSPC_7_EHD_Msk                                   (0x03UL << SCU_SFSPC_7_EHD_Pos)                           /*!< SCU SFSPC_7: EHD Mask               */

// ---------------------------------------  SCU_SFSPC_8  ------------------------------------------
#define SCU_SFSPC_8_MODE_Pos                                  0                                                         /*!< SCU SFSPC_8: MODE Position          */
#define SCU_SFSPC_8_MODE_Msk                                  (0x07UL << SCU_SFSPC_8_MODE_Pos)                          /*!< SCU SFSPC_8: MODE Mask              */
#define SCU_SFSPC_8_EPD_Pos                                   3                                                         /*!< SCU SFSPC_8: EPD Position           */
#define SCU_SFSPC_8_EPD_Msk                                   (0x01UL << SCU_SFSPC_8_EPD_Pos)                           /*!< SCU SFSPC_8: EPD Mask               */
#define SCU_SFSPC_8_EPUN_Pos                                  4                                                         /*!< SCU SFSPC_8: EPUN Position          */
#define SCU_SFSPC_8_EPUN_Msk                                  (0x01UL << SCU_SFSPC_8_EPUN_Pos)                          /*!< SCU SFSPC_8: EPUN Mask              */
#define SCU_SFSPC_8_EHS_Pos                                   5                                                         /*!< SCU SFSPC_8: EHS Position           */
#define SCU_SFSPC_8_EHS_Msk                                   (0x01UL << SCU_SFSPC_8_EHS_Pos)                           /*!< SCU SFSPC_8: EHS Mask               */
#define SCU_SFSPC_8_EZI_Pos                                   6                                                         /*!< SCU SFSPC_8: EZI Position           */
#define SCU_SFSPC_8_EZI_Msk                                   (0x01UL << SCU_SFSPC_8_EZI_Pos)                           /*!< SCU SFSPC_8: EZI Mask               */
#define SCU_SFSPC_8_EHD_Pos                                   8                                                         /*!< SCU SFSPC_8: EHD Position           */
#define SCU_SFSPC_8_EHD_Msk                                   (0x03UL << SCU_SFSPC_8_EHD_Pos)                           /*!< SCU SFSPC_8: EHD Mask               */

// ---------------------------------------  SCU_SFSPC_9  ------------------------------------------
#define SCU_SFSPC_9_MODE_Pos                                  0                                                         /*!< SCU SFSPC_9: MODE Position          */
#define SCU_SFSPC_9_MODE_Msk                                  (0x07UL << SCU_SFSPC_9_MODE_Pos)                          /*!< SCU SFSPC_9: MODE Mask              */
#define SCU_SFSPC_9_EPD_Pos                                   3                                                         /*!< SCU SFSPC_9: EPD Position           */
#define SCU_SFSPC_9_EPD_Msk                                   (0x01UL << SCU_SFSPC_9_EPD_Pos)                           /*!< SCU SFSPC_9: EPD Mask               */
#define SCU_SFSPC_9_EPUN_Pos                                  4                                                         /*!< SCU SFSPC_9: EPUN Position          */
#define SCU_SFSPC_9_EPUN_Msk                                  (0x01UL << SCU_SFSPC_9_EPUN_Pos)                          /*!< SCU SFSPC_9: EPUN Mask              */
#define SCU_SFSPC_9_EHS_Pos                                   5                                                         /*!< SCU SFSPC_9: EHS Position           */
#define SCU_SFSPC_9_EHS_Msk                                   (0x01UL << SCU_SFSPC_9_EHS_Pos)                           /*!< SCU SFSPC_9: EHS Mask               */
#define SCU_SFSPC_9_EZI_Pos                                   6                                                         /*!< SCU SFSPC_9: EZI Position           */
#define SCU_SFSPC_9_EZI_Msk                                   (0x01UL << SCU_SFSPC_9_EZI_Pos)                           /*!< SCU SFSPC_9: EZI Mask               */
#define SCU_SFSPC_9_EHD_Pos                                   8                                                         /*!< SCU SFSPC_9: EHD Position           */
#define SCU_SFSPC_9_EHD_Msk                                   (0x03UL << SCU_SFSPC_9_EHD_Pos)                           /*!< SCU SFSPC_9: EHD Mask               */

// --------------------------------------  SCU_SFSPC_10  ------------------------------------------
#define SCU_SFSPC_10_MODE_Pos                                 0                                                         /*!< SCU SFSPC_10: MODE Position         */
#define SCU_SFSPC_10_MODE_Msk                                 (0x07UL << SCU_SFSPC_10_MODE_Pos)                         /*!< SCU SFSPC_10: MODE Mask             */
#define SCU_SFSPC_10_EPD_Pos                                  3                                                         /*!< SCU SFSPC_10: EPD Position          */
#define SCU_SFSPC_10_EPD_Msk                                  (0x01UL << SCU_SFSPC_10_EPD_Pos)                          /*!< SCU SFSPC_10: EPD Mask              */
#define SCU_SFSPC_10_EPUN_Pos                                 4                                                         /*!< SCU SFSPC_10: EPUN Position         */
#define SCU_SFSPC_10_EPUN_Msk                                 (0x01UL << SCU_SFSPC_10_EPUN_Pos)                         /*!< SCU SFSPC_10: EPUN Mask             */
#define SCU_SFSPC_10_EHS_Pos                                  5                                                         /*!< SCU SFSPC_10: EHS Position          */
#define SCU_SFSPC_10_EHS_Msk                                  (0x01UL << SCU_SFSPC_10_EHS_Pos)                          /*!< SCU SFSPC_10: EHS Mask              */
#define SCU_SFSPC_10_EZI_Pos                                  6                                                         /*!< SCU SFSPC_10: EZI Position          */
#define SCU_SFSPC_10_EZI_Msk                                  (0x01UL << SCU_SFSPC_10_EZI_Pos)                          /*!< SCU SFSPC_10: EZI Mask              */
#define SCU_SFSPC_10_EHD_Pos                                  8                                                         /*!< SCU SFSPC_10: EHD Position          */
#define SCU_SFSPC_10_EHD_Msk                                  (0x03UL << SCU_SFSPC_10_EHD_Pos)                          /*!< SCU SFSPC_10: EHD Mask              */

// --------------------------------------  SCU_SFSPC_11  ------------------------------------------
#define SCU_SFSPC_11_MODE_Pos                                 0                                                         /*!< SCU SFSPC_11: MODE Position         */
#define SCU_SFSPC_11_MODE_Msk                                 (0x07UL << SCU_SFSPC_11_MODE_Pos)                         /*!< SCU SFSPC_11: MODE Mask             */
#define SCU_SFSPC_11_EPD_Pos                                  3                                                         /*!< SCU SFSPC_11: EPD Position          */
#define SCU_SFSPC_11_EPD_Msk                                  (0x01UL << SCU_SFSPC_11_EPD_Pos)                          /*!< SCU SFSPC_11: EPD Mask              */
#define SCU_SFSPC_11_EPUN_Pos                                 4                                                         /*!< SCU SFSPC_11: EPUN Position         */
#define SCU_SFSPC_11_EPUN_Msk                                 (0x01UL << SCU_SFSPC_11_EPUN_Pos)                         /*!< SCU SFSPC_11: EPUN Mask             */
#define SCU_SFSPC_11_EHS_Pos                                  5                                                         /*!< SCU SFSPC_11: EHS Position          */
#define SCU_SFSPC_11_EHS_Msk                                  (0x01UL << SCU_SFSPC_11_EHS_Pos)                          /*!< SCU SFSPC_11: EHS Mask              */
#define SCU_SFSPC_11_EZI_Pos                                  6                                                         /*!< SCU SFSPC_11: EZI Position          */
#define SCU_SFSPC_11_EZI_Msk                                  (0x01UL << SCU_SFSPC_11_EZI_Pos)                          /*!< SCU SFSPC_11: EZI Mask              */
#define SCU_SFSPC_11_EHD_Pos                                  8                                                         /*!< SCU SFSPC_11: EHD Position          */
#define SCU_SFSPC_11_EHD_Msk                                  (0x03UL << SCU_SFSPC_11_EHD_Pos)                          /*!< SCU SFSPC_11: EHD Mask              */

// --------------------------------------  SCU_SFSPC_12  ------------------------------------------
#define SCU_SFSPC_12_MODE_Pos                                 0                                                         /*!< SCU SFSPC_12: MODE Position         */
#define SCU_SFSPC_12_MODE_Msk                                 (0x07UL << SCU_SFSPC_12_MODE_Pos)                         /*!< SCU SFSPC_12: MODE Mask             */
#define SCU_SFSPC_12_EPD_Pos                                  3                                                         /*!< SCU SFSPC_12: EPD Position          */
#define SCU_SFSPC_12_EPD_Msk                                  (0x01UL << SCU_SFSPC_12_EPD_Pos)                          /*!< SCU SFSPC_12: EPD Mask              */
#define SCU_SFSPC_12_EPUN_Pos                                 4                                                         /*!< SCU SFSPC_12: EPUN Position         */
#define SCU_SFSPC_12_EPUN_Msk                                 (0x01UL << SCU_SFSPC_12_EPUN_Pos)                         /*!< SCU SFSPC_12: EPUN Mask             */
#define SCU_SFSPC_12_EHS_Pos                                  5                                                         /*!< SCU SFSPC_12: EHS Position          */
#define SCU_SFSPC_12_EHS_Msk                                  (0x01UL << SCU_SFSPC_12_EHS_Pos)                          /*!< SCU SFSPC_12: EHS Mask              */
#define SCU_SFSPC_12_EZI_Pos                                  6                                                         /*!< SCU SFSPC_12: EZI Position          */
#define SCU_SFSPC_12_EZI_Msk                                  (0x01UL << SCU_SFSPC_12_EZI_Pos)                          /*!< SCU SFSPC_12: EZI Mask              */
#define SCU_SFSPC_12_EHD_Pos                                  8                                                         /*!< SCU SFSPC_12: EHD Position          */
#define SCU_SFSPC_12_EHD_Msk                                  (0x03UL << SCU_SFSPC_12_EHD_Pos)                          /*!< SCU SFSPC_12: EHD Mask              */

// --------------------------------------  SCU_SFSPC_13  ------------------------------------------
#define SCU_SFSPC_13_MODE_Pos                                 0                                                         /*!< SCU SFSPC_13: MODE Position         */
#define SCU_SFSPC_13_MODE_Msk                                 (0x07UL << SCU_SFSPC_13_MODE_Pos)                         /*!< SCU SFSPC_13: MODE Mask             */
#define SCU_SFSPC_13_EPD_Pos                                  3                                                         /*!< SCU SFSPC_13: EPD Position          */
#define SCU_SFSPC_13_EPD_Msk                                  (0x01UL << SCU_SFSPC_13_EPD_Pos)                          /*!< SCU SFSPC_13: EPD Mask              */
#define SCU_SFSPC_13_EPUN_Pos                                 4                                                         /*!< SCU SFSPC_13: EPUN Position         */
#define SCU_SFSPC_13_EPUN_Msk                                 (0x01UL << SCU_SFSPC_13_EPUN_Pos)                         /*!< SCU SFSPC_13: EPUN Mask             */
#define SCU_SFSPC_13_EHS_Pos                                  5                                                         /*!< SCU SFSPC_13: EHS Position          */
#define SCU_SFSPC_13_EHS_Msk                                  (0x01UL << SCU_SFSPC_13_EHS_Pos)                          /*!< SCU SFSPC_13: EHS Mask              */
#define SCU_SFSPC_13_EZI_Pos                                  6                                                         /*!< SCU SFSPC_13: EZI Position          */
#define SCU_SFSPC_13_EZI_Msk                                  (0x01UL << SCU_SFSPC_13_EZI_Pos)                          /*!< SCU SFSPC_13: EZI Mask              */
#define SCU_SFSPC_13_EHD_Pos                                  8                                                         /*!< SCU SFSPC_13: EHD Position          */
#define SCU_SFSPC_13_EHD_Msk                                  (0x03UL << SCU_SFSPC_13_EHD_Pos)                          /*!< SCU SFSPC_13: EHD Mask              */

// --------------------------------------  SCU_SFSPC_14  ------------------------------------------
#define SCU_SFSPC_14_MODE_Pos                                 0                                                         /*!< SCU SFSPC_14: MODE Position         */
#define SCU_SFSPC_14_MODE_Msk                                 (0x07UL << SCU_SFSPC_14_MODE_Pos)                         /*!< SCU SFSPC_14: MODE Mask             */
#define SCU_SFSPC_14_EPD_Pos                                  3                                                         /*!< SCU SFSPC_14: EPD Position          */
#define SCU_SFSPC_14_EPD_Msk                                  (0x01UL << SCU_SFSPC_14_EPD_Pos)                          /*!< SCU SFSPC_14: EPD Mask              */
#define SCU_SFSPC_14_EPUN_Pos                                 4                                                         /*!< SCU SFSPC_14: EPUN Position         */
#define SCU_SFSPC_14_EPUN_Msk                                 (0x01UL << SCU_SFSPC_14_EPUN_Pos)                         /*!< SCU SFSPC_14: EPUN Mask             */
#define SCU_SFSPC_14_EHS_Pos                                  5                                                         /*!< SCU SFSPC_14: EHS Position          */
#define SCU_SFSPC_14_EHS_Msk                                  (0x01UL << SCU_SFSPC_14_EHS_Pos)                          /*!< SCU SFSPC_14: EHS Mask              */
#define SCU_SFSPC_14_EZI_Pos                                  6                                                         /*!< SCU SFSPC_14: EZI Position          */
#define SCU_SFSPC_14_EZI_Msk                                  (0x01UL << SCU_SFSPC_14_EZI_Pos)                          /*!< SCU SFSPC_14: EZI Mask              */
#define SCU_SFSPC_14_EHD_Pos                                  8                                                         /*!< SCU SFSPC_14: EHD Position          */
#define SCU_SFSPC_14_EHD_Msk                                  (0x03UL << SCU_SFSPC_14_EHD_Pos)                          /*!< SCU SFSPC_14: EHD Mask              */

// ---------------------------------------  SCU_SFSPD_0  ------------------------------------------
#define SCU_SFSPD_0_MODE_Pos                                  0                                                         /*!< SCU SFSPD_0: MODE Position          */
#define SCU_SFSPD_0_MODE_Msk                                  (0x07UL << SCU_SFSPD_0_MODE_Pos)                          /*!< SCU SFSPD_0: MODE Mask              */
#define SCU_SFSPD_0_EPD_Pos                                   3                                                         /*!< SCU SFSPD_0: EPD Position           */
#define SCU_SFSPD_0_EPD_Msk                                   (0x01UL << SCU_SFSPD_0_EPD_Pos)                           /*!< SCU SFSPD_0: EPD Mask               */
#define SCU_SFSPD_0_EPUN_Pos                                  4                                                         /*!< SCU SFSPD_0: EPUN Position          */
#define SCU_SFSPD_0_EPUN_Msk                                  (0x01UL << SCU_SFSPD_0_EPUN_Pos)                          /*!< SCU SFSPD_0: EPUN Mask              */
#define SCU_SFSPD_0_EHS_Pos                                   5                                                         /*!< SCU SFSPD_0: EHS Position           */
#define SCU_SFSPD_0_EHS_Msk                                   (0x01UL << SCU_SFSPD_0_EHS_Pos)                           /*!< SCU SFSPD_0: EHS Mask               */
#define SCU_SFSPD_0_EZI_Pos                                   6                                                         /*!< SCU SFSPD_0: EZI Position           */
#define SCU_SFSPD_0_EZI_Msk                                   (0x01UL << SCU_SFSPD_0_EZI_Pos)                           /*!< SCU SFSPD_0: EZI Mask               */
#define SCU_SFSPD_0_EHD_Pos                                   8                                                         /*!< SCU SFSPD_0: EHD Position           */
#define SCU_SFSPD_0_EHD_Msk                                   (0x03UL << SCU_SFSPD_0_EHD_Pos)                           /*!< SCU SFSPD_0: EHD Mask               */

// ---------------------------------------  SCU_SFSPD_1  ------------------------------------------
#define SCU_SFSPD_1_MODE_Pos                                  0                                                         /*!< SCU SFSPD_1: MODE Position          */
#define SCU_SFSPD_1_MODE_Msk                                  (0x07UL << SCU_SFSPD_1_MODE_Pos)                          /*!< SCU SFSPD_1: MODE Mask              */
#define SCU_SFSPD_1_EPD_Pos                                   3                                                         /*!< SCU SFSPD_1: EPD Position           */
#define SCU_SFSPD_1_EPD_Msk                                   (0x01UL << SCU_SFSPD_1_EPD_Pos)                           /*!< SCU SFSPD_1: EPD Mask               */
#define SCU_SFSPD_1_EPUN_Pos                                  4                                                         /*!< SCU SFSPD_1: EPUN Position          */
#define SCU_SFSPD_1_EPUN_Msk                                  (0x01UL << SCU_SFSPD_1_EPUN_Pos)                          /*!< SCU SFSPD_1: EPUN Mask              */
#define SCU_SFSPD_1_EHS_Pos                                   5                                                         /*!< SCU SFSPD_1: EHS Position           */
#define SCU_SFSPD_1_EHS_Msk                                   (0x01UL << SCU_SFSPD_1_EHS_Pos)                           /*!< SCU SFSPD_1: EHS Mask               */
#define SCU_SFSPD_1_EZI_Pos                                   6                                                         /*!< SCU SFSPD_1: EZI Position           */
#define SCU_SFSPD_1_EZI_Msk                                   (0x01UL << SCU_SFSPD_1_EZI_Pos)                           /*!< SCU SFSPD_1: EZI Mask               */
#define SCU_SFSPD_1_EHD_Pos                                   8                                                         /*!< SCU SFSPD_1: EHD Position           */
#define SCU_SFSPD_1_EHD_Msk                                   (0x03UL << SCU_SFSPD_1_EHD_Pos)                           /*!< SCU SFSPD_1: EHD Mask               */

// ---------------------------------------  SCU_SFSPD_2  ------------------------------------------
#define SCU_SFSPD_2_MODE_Pos                                  0                                                         /*!< SCU SFSPD_2: MODE Position          */
#define SCU_SFSPD_2_MODE_Msk                                  (0x07UL << SCU_SFSPD_2_MODE_Pos)                          /*!< SCU SFSPD_2: MODE Mask              */
#define SCU_SFSPD_2_EPD_Pos                                   3                                                         /*!< SCU SFSPD_2: EPD Position           */
#define SCU_SFSPD_2_EPD_Msk                                   (0x01UL << SCU_SFSPD_2_EPD_Pos)                           /*!< SCU SFSPD_2: EPD Mask               */
#define SCU_SFSPD_2_EPUN_Pos                                  4                                                         /*!< SCU SFSPD_2: EPUN Position          */
#define SCU_SFSPD_2_EPUN_Msk                                  (0x01UL << SCU_SFSPD_2_EPUN_Pos)                          /*!< SCU SFSPD_2: EPUN Mask              */
#define SCU_SFSPD_2_EHS_Pos                                   5                                                         /*!< SCU SFSPD_2: EHS Position           */
#define SCU_SFSPD_2_EHS_Msk                                   (0x01UL << SCU_SFSPD_2_EHS_Pos)                           /*!< SCU SFSPD_2: EHS Mask               */
#define SCU_SFSPD_2_EZI_Pos                                   6                                                         /*!< SCU SFSPD_2: EZI Position           */
#define SCU_SFSPD_2_EZI_Msk                                   (0x01UL << SCU_SFSPD_2_EZI_Pos)                           /*!< SCU SFSPD_2: EZI Mask               */
#define SCU_SFSPD_2_EHD_Pos                                   8                                                         /*!< SCU SFSPD_2: EHD Position           */
#define SCU_SFSPD_2_EHD_Msk                                   (0x03UL << SCU_SFSPD_2_EHD_Pos)                           /*!< SCU SFSPD_2: EHD Mask               */

// ---------------------------------------  SCU_SFSPD_3  ------------------------------------------
#define SCU_SFSPD_3_MODE_Pos                                  0                                                         /*!< SCU SFSPD_3: MODE Position          */
#define SCU_SFSPD_3_MODE_Msk                                  (0x07UL << SCU_SFSPD_3_MODE_Pos)                          /*!< SCU SFSPD_3: MODE Mask              */
#define SCU_SFSPD_3_EPD_Pos                                   3                                                         /*!< SCU SFSPD_3: EPD Position           */
#define SCU_SFSPD_3_EPD_Msk                                   (0x01UL << SCU_SFSPD_3_EPD_Pos)                           /*!< SCU SFSPD_3: EPD Mask               */
#define SCU_SFSPD_3_EPUN_Pos                                  4                                                         /*!< SCU SFSPD_3: EPUN Position          */
#define SCU_SFSPD_3_EPUN_Msk                                  (0x01UL << SCU_SFSPD_3_EPUN_Pos)                          /*!< SCU SFSPD_3: EPUN Mask              */
#define SCU_SFSPD_3_EHS_Pos                                   5                                                         /*!< SCU SFSPD_3: EHS Position           */
#define SCU_SFSPD_3_EHS_Msk                                   (0x01UL << SCU_SFSPD_3_EHS_Pos)                           /*!< SCU SFSPD_3: EHS Mask               */
#define SCU_SFSPD_3_EZI_Pos                                   6                                                         /*!< SCU SFSPD_3: EZI Position           */
#define SCU_SFSPD_3_EZI_Msk                                   (0x01UL << SCU_SFSPD_3_EZI_Pos)                           /*!< SCU SFSPD_3: EZI Mask               */
#define SCU_SFSPD_3_EHD_Pos                                   8                                                         /*!< SCU SFSPD_3: EHD Position           */
#define SCU_SFSPD_3_EHD_Msk                                   (0x03UL << SCU_SFSPD_3_EHD_Pos)                           /*!< SCU SFSPD_3: EHD Mask               */

// ---------------------------------------  SCU_SFSPD_4  ------------------------------------------
#define SCU_SFSPD_4_MODE_Pos                                  0                                                         /*!< SCU SFSPD_4: MODE Position          */
#define SCU_SFSPD_4_MODE_Msk                                  (0x07UL << SCU_SFSPD_4_MODE_Pos)                          /*!< SCU SFSPD_4: MODE Mask              */
#define SCU_SFSPD_4_EPD_Pos                                   3                                                         /*!< SCU SFSPD_4: EPD Position           */
#define SCU_SFSPD_4_EPD_Msk                                   (0x01UL << SCU_SFSPD_4_EPD_Pos)                           /*!< SCU SFSPD_4: EPD Mask               */
#define SCU_SFSPD_4_EPUN_Pos                                  4                                                         /*!< SCU SFSPD_4: EPUN Position          */
#define SCU_SFSPD_4_EPUN_Msk                                  (0x01UL << SCU_SFSPD_4_EPUN_Pos)                          /*!< SCU SFSPD_4: EPUN Mask              */
#define SCU_SFSPD_4_EHS_Pos                                   5                                                         /*!< SCU SFSPD_4: EHS Position           */
#define SCU_SFSPD_4_EHS_Msk                                   (0x01UL << SCU_SFSPD_4_EHS_Pos)                           /*!< SCU SFSPD_4: EHS Mask               */
#define SCU_SFSPD_4_EZI_Pos                                   6                                                         /*!< SCU SFSPD_4: EZI Position           */
#define SCU_SFSPD_4_EZI_Msk                                   (0x01UL << SCU_SFSPD_4_EZI_Pos)                           /*!< SCU SFSPD_4: EZI Mask               */
#define SCU_SFSPD_4_EHD_Pos                                   8                                                         /*!< SCU SFSPD_4: EHD Position           */
#define SCU_SFSPD_4_EHD_Msk                                   (0x03UL << SCU_SFSPD_4_EHD_Pos)                           /*!< SCU SFSPD_4: EHD Mask               */

// ---------------------------------------  SCU_SFSPD_5  ------------------------------------------
#define SCU_SFSPD_5_MODE_Pos                                  0                                                         /*!< SCU SFSPD_5: MODE Position          */
#define SCU_SFSPD_5_MODE_Msk                                  (0x07UL << SCU_SFSPD_5_MODE_Pos)                          /*!< SCU SFSPD_5: MODE Mask              */
#define SCU_SFSPD_5_EPD_Pos                                   3                                                         /*!< SCU SFSPD_5: EPD Position           */
#define SCU_SFSPD_5_EPD_Msk                                   (0x01UL << SCU_SFSPD_5_EPD_Pos)                           /*!< SCU SFSPD_5: EPD Mask               */
#define SCU_SFSPD_5_EPUN_Pos                                  4                                                         /*!< SCU SFSPD_5: EPUN Position          */
#define SCU_SFSPD_5_EPUN_Msk                                  (0x01UL << SCU_SFSPD_5_EPUN_Pos)                          /*!< SCU SFSPD_5: EPUN Mask              */
#define SCU_SFSPD_5_EHS_Pos                                   5                                                         /*!< SCU SFSPD_5: EHS Position           */
#define SCU_SFSPD_5_EHS_Msk                                   (0x01UL << SCU_SFSPD_5_EHS_Pos)                           /*!< SCU SFSPD_5: EHS Mask               */
#define SCU_SFSPD_5_EZI_Pos                                   6                                                         /*!< SCU SFSPD_5: EZI Position           */
#define SCU_SFSPD_5_EZI_Msk                                   (0x01UL << SCU_SFSPD_5_EZI_Pos)                           /*!< SCU SFSPD_5: EZI Mask               */
#define SCU_SFSPD_5_EHD_Pos                                   8                                                         /*!< SCU SFSPD_5: EHD Position           */
#define SCU_SFSPD_5_EHD_Msk                                   (0x03UL << SCU_SFSPD_5_EHD_Pos)                           /*!< SCU SFSPD_5: EHD Mask               */

// ---------------------------------------  SCU_SFSPD_6  ------------------------------------------
#define SCU_SFSPD_6_MODE_Pos                                  0                                                         /*!< SCU SFSPD_6: MODE Position          */
#define SCU_SFSPD_6_MODE_Msk                                  (0x07UL << SCU_SFSPD_6_MODE_Pos)                          /*!< SCU SFSPD_6: MODE Mask              */
#define SCU_SFSPD_6_EPD_Pos                                   3                                                         /*!< SCU SFSPD_6: EPD Position           */
#define SCU_SFSPD_6_EPD_Msk                                   (0x01UL << SCU_SFSPD_6_EPD_Pos)                           /*!< SCU SFSPD_6: EPD Mask               */
#define SCU_SFSPD_6_EPUN_Pos                                  4                                                         /*!< SCU SFSPD_6: EPUN Position          */
#define SCU_SFSPD_6_EPUN_Msk                                  (0x01UL << SCU_SFSPD_6_EPUN_Pos)                          /*!< SCU SFSPD_6: EPUN Mask              */
#define SCU_SFSPD_6_EHS_Pos                                   5                                                         /*!< SCU SFSPD_6: EHS Position           */
#define SCU_SFSPD_6_EHS_Msk                                   (0x01UL << SCU_SFSPD_6_EHS_Pos)                           /*!< SCU SFSPD_6: EHS Mask               */
#define SCU_SFSPD_6_EZI_Pos                                   6                                                         /*!< SCU SFSPD_6: EZI Position           */
#define SCU_SFSPD_6_EZI_Msk                                   (0x01UL << SCU_SFSPD_6_EZI_Pos)                           /*!< SCU SFSPD_6: EZI Mask               */
#define SCU_SFSPD_6_EHD_Pos                                   8                                                         /*!< SCU SFSPD_6: EHD Position           */
#define SCU_SFSPD_6_EHD_Msk                                   (0x03UL << SCU_SFSPD_6_EHD_Pos)                           /*!< SCU SFSPD_6: EHD Mask               */

// ---------------------------------------  SCU_SFSPD_7  ------------------------------------------
#define SCU_SFSPD_7_MODE_Pos                                  0                                                         /*!< SCU SFSPD_7: MODE Position          */
#define SCU_SFSPD_7_MODE_Msk                                  (0x07UL << SCU_SFSPD_7_MODE_Pos)                          /*!< SCU SFSPD_7: MODE Mask              */
#define SCU_SFSPD_7_EPD_Pos                                   3                                                         /*!< SCU SFSPD_7: EPD Position           */
#define SCU_SFSPD_7_EPD_Msk                                   (0x01UL << SCU_SFSPD_7_EPD_Pos)                           /*!< SCU SFSPD_7: EPD Mask               */
#define SCU_SFSPD_7_EPUN_Pos                                  4                                                         /*!< SCU SFSPD_7: EPUN Position          */
#define SCU_SFSPD_7_EPUN_Msk                                  (0x01UL << SCU_SFSPD_7_EPUN_Pos)                          /*!< SCU SFSPD_7: EPUN Mask              */
#define SCU_SFSPD_7_EHS_Pos                                   5                                                         /*!< SCU SFSPD_7: EHS Position           */
#define SCU_SFSPD_7_EHS_Msk                                   (0x01UL << SCU_SFSPD_7_EHS_Pos)                           /*!< SCU SFSPD_7: EHS Mask               */
#define SCU_SFSPD_7_EZI_Pos                                   6                                                         /*!< SCU SFSPD_7: EZI Position           */
#define SCU_SFSPD_7_EZI_Msk                                   (0x01UL << SCU_SFSPD_7_EZI_Pos)                           /*!< SCU SFSPD_7: EZI Mask               */
#define SCU_SFSPD_7_EHD_Pos                                   8                                                         /*!< SCU SFSPD_7: EHD Position           */
#define SCU_SFSPD_7_EHD_Msk                                   (0x03UL << SCU_SFSPD_7_EHD_Pos)                           /*!< SCU SFSPD_7: EHD Mask               */

// ---------------------------------------  SCU_SFSPD_8  ------------------------------------------
#define SCU_SFSPD_8_MODE_Pos                                  0                                                         /*!< SCU SFSPD_8: MODE Position          */
#define SCU_SFSPD_8_MODE_Msk                                  (0x07UL << SCU_SFSPD_8_MODE_Pos)                          /*!< SCU SFSPD_8: MODE Mask              */
#define SCU_SFSPD_8_EPD_Pos                                   3                                                         /*!< SCU SFSPD_8: EPD Position           */
#define SCU_SFSPD_8_EPD_Msk                                   (0x01UL << SCU_SFSPD_8_EPD_Pos)                           /*!< SCU SFSPD_8: EPD Mask               */
#define SCU_SFSPD_8_EPUN_Pos                                  4                                                         /*!< SCU SFSPD_8: EPUN Position          */
#define SCU_SFSPD_8_EPUN_Msk                                  (0x01UL << SCU_SFSPD_8_EPUN_Pos)                          /*!< SCU SFSPD_8: EPUN Mask              */
#define SCU_SFSPD_8_EHS_Pos                                   5                                                         /*!< SCU SFSPD_8: EHS Position           */
#define SCU_SFSPD_8_EHS_Msk                                   (0x01UL << SCU_SFSPD_8_EHS_Pos)                           /*!< SCU SFSPD_8: EHS Mask               */
#define SCU_SFSPD_8_EZI_Pos                                   6                                                         /*!< SCU SFSPD_8: EZI Position           */
#define SCU_SFSPD_8_EZI_Msk                                   (0x01UL << SCU_SFSPD_8_EZI_Pos)                           /*!< SCU SFSPD_8: EZI Mask               */
#define SCU_SFSPD_8_EHD_Pos                                   8                                                         /*!< SCU SFSPD_8: EHD Position           */
#define SCU_SFSPD_8_EHD_Msk                                   (0x03UL << SCU_SFSPD_8_EHD_Pos)                           /*!< SCU SFSPD_8: EHD Mask               */

// ---------------------------------------  SCU_SFSPD_9  ------------------------------------------
#define SCU_SFSPD_9_MODE_Pos                                  0                                                         /*!< SCU SFSPD_9: MODE Position          */
#define SCU_SFSPD_9_MODE_Msk                                  (0x07UL << SCU_SFSPD_9_MODE_Pos)                          /*!< SCU SFSPD_9: MODE Mask              */
#define SCU_SFSPD_9_EPD_Pos                                   3                                                         /*!< SCU SFSPD_9: EPD Position           */
#define SCU_SFSPD_9_EPD_Msk                                   (0x01UL << SCU_SFSPD_9_EPD_Pos)                           /*!< SCU SFSPD_9: EPD Mask               */
#define SCU_SFSPD_9_EPUN_Pos                                  4                                                         /*!< SCU SFSPD_9: EPUN Position          */
#define SCU_SFSPD_9_EPUN_Msk                                  (0x01UL << SCU_SFSPD_9_EPUN_Pos)                          /*!< SCU SFSPD_9: EPUN Mask              */
#define SCU_SFSPD_9_EHS_Pos                                   5                                                         /*!< SCU SFSPD_9: EHS Position           */
#define SCU_SFSPD_9_EHS_Msk                                   (0x01UL << SCU_SFSPD_9_EHS_Pos)                           /*!< SCU SFSPD_9: EHS Mask               */
#define SCU_SFSPD_9_EZI_Pos                                   6                                                         /*!< SCU SFSPD_9: EZI Position           */
#define SCU_SFSPD_9_EZI_Msk                                   (0x01UL << SCU_SFSPD_9_EZI_Pos)                           /*!< SCU SFSPD_9: EZI Mask               */
#define SCU_SFSPD_9_EHD_Pos                                   8                                                         /*!< SCU SFSPD_9: EHD Position           */
#define SCU_SFSPD_9_EHD_Msk                                   (0x03UL << SCU_SFSPD_9_EHD_Pos)                           /*!< SCU SFSPD_9: EHD Mask               */

// --------------------------------------  SCU_SFSPD_10  ------------------------------------------
#define SCU_SFSPD_10_MODE_Pos                                 0                                                         /*!< SCU SFSPD_10: MODE Position         */
#define SCU_SFSPD_10_MODE_Msk                                 (0x07UL << SCU_SFSPD_10_MODE_Pos)                         /*!< SCU SFSPD_10: MODE Mask             */
#define SCU_SFSPD_10_EPD_Pos                                  3                                                         /*!< SCU SFSPD_10: EPD Position          */
#define SCU_SFSPD_10_EPD_Msk                                  (0x01UL << SCU_SFSPD_10_EPD_Pos)                          /*!< SCU SFSPD_10: EPD Mask              */
#define SCU_SFSPD_10_EPUN_Pos                                 4                                                         /*!< SCU SFSPD_10: EPUN Position         */
#define SCU_SFSPD_10_EPUN_Msk                                 (0x01UL << SCU_SFSPD_10_EPUN_Pos)                         /*!< SCU SFSPD_10: EPUN Mask             */
#define SCU_SFSPD_10_EHS_Pos                                  5                                                         /*!< SCU SFSPD_10: EHS Position          */
#define SCU_SFSPD_10_EHS_Msk                                  (0x01UL << SCU_SFSPD_10_EHS_Pos)                          /*!< SCU SFSPD_10: EHS Mask              */
#define SCU_SFSPD_10_EZI_Pos                                  6                                                         /*!< SCU SFSPD_10: EZI Position          */
#define SCU_SFSPD_10_EZI_Msk                                  (0x01UL << SCU_SFSPD_10_EZI_Pos)                          /*!< SCU SFSPD_10: EZI Mask              */
#define SCU_SFSPD_10_EHD_Pos                                  8                                                         /*!< SCU SFSPD_10: EHD Position          */
#define SCU_SFSPD_10_EHD_Msk                                  (0x03UL << SCU_SFSPD_10_EHD_Pos)                          /*!< SCU SFSPD_10: EHD Mask              */

// --------------------------------------  SCU_SFSPD_11  ------------------------------------------
#define SCU_SFSPD_11_MODE_Pos                                 0                                                         /*!< SCU SFSPD_11: MODE Position         */
#define SCU_SFSPD_11_MODE_Msk                                 (0x07UL << SCU_SFSPD_11_MODE_Pos)                         /*!< SCU SFSPD_11: MODE Mask             */
#define SCU_SFSPD_11_EPD_Pos                                  3                                                         /*!< SCU SFSPD_11: EPD Position          */
#define SCU_SFSPD_11_EPD_Msk                                  (0x01UL << SCU_SFSPD_11_EPD_Pos)                          /*!< SCU SFSPD_11: EPD Mask              */
#define SCU_SFSPD_11_EPUN_Pos                                 4                                                         /*!< SCU SFSPD_11: EPUN Position         */
#define SCU_SFSPD_11_EPUN_Msk                                 (0x01UL << SCU_SFSPD_11_EPUN_Pos)                         /*!< SCU SFSPD_11: EPUN Mask             */
#define SCU_SFSPD_11_EHS_Pos                                  5                                                         /*!< SCU SFSPD_11: EHS Position          */
#define SCU_SFSPD_11_EHS_Msk                                  (0x01UL << SCU_SFSPD_11_EHS_Pos)                          /*!< SCU SFSPD_11: EHS Mask              */
#define SCU_SFSPD_11_EZI_Pos                                  6                                                         /*!< SCU SFSPD_11: EZI Position          */
#define SCU_SFSPD_11_EZI_Msk                                  (0x01UL << SCU_SFSPD_11_EZI_Pos)                          /*!< SCU SFSPD_11: EZI Mask              */
#define SCU_SFSPD_11_EHD_Pos                                  8                                                         /*!< SCU SFSPD_11: EHD Position          */
#define SCU_SFSPD_11_EHD_Msk                                  (0x03UL << SCU_SFSPD_11_EHD_Pos)                          /*!< SCU SFSPD_11: EHD Mask              */

// --------------------------------------  SCU_SFSPD_12  ------------------------------------------
#define SCU_SFSPD_12_MODE_Pos                                 0                                                         /*!< SCU SFSPD_12: MODE Position         */
#define SCU_SFSPD_12_MODE_Msk                                 (0x07UL << SCU_SFSPD_12_MODE_Pos)                         /*!< SCU SFSPD_12: MODE Mask             */
#define SCU_SFSPD_12_EPD_Pos                                  3                                                         /*!< SCU SFSPD_12: EPD Position          */
#define SCU_SFSPD_12_EPD_Msk                                  (0x01UL << SCU_SFSPD_12_EPD_Pos)                          /*!< SCU SFSPD_12: EPD Mask              */
#define SCU_SFSPD_12_EPUN_Pos                                 4                                                         /*!< SCU SFSPD_12: EPUN Position         */
#define SCU_SFSPD_12_EPUN_Msk                                 (0x01UL << SCU_SFSPD_12_EPUN_Pos)                         /*!< SCU SFSPD_12: EPUN Mask             */
#define SCU_SFSPD_12_EHS_Pos                                  5                                                         /*!< SCU SFSPD_12: EHS Position          */
#define SCU_SFSPD_12_EHS_Msk                                  (0x01UL << SCU_SFSPD_12_EHS_Pos)                          /*!< SCU SFSPD_12: EHS Mask              */
#define SCU_SFSPD_12_EZI_Pos                                  6                                                         /*!< SCU SFSPD_12: EZI Position          */
#define SCU_SFSPD_12_EZI_Msk                                  (0x01UL << SCU_SFSPD_12_EZI_Pos)                          /*!< SCU SFSPD_12: EZI Mask              */
#define SCU_SFSPD_12_EHD_Pos                                  8                                                         /*!< SCU SFSPD_12: EHD Position          */
#define SCU_SFSPD_12_EHD_Msk                                  (0x03UL << SCU_SFSPD_12_EHD_Pos)                          /*!< SCU SFSPD_12: EHD Mask              */

// --------------------------------------  SCU_SFSPD_13  ------------------------------------------
#define SCU_SFSPD_13_MODE_Pos                                 0                                                         /*!< SCU SFSPD_13: MODE Position         */
#define SCU_SFSPD_13_MODE_Msk                                 (0x07UL << SCU_SFSPD_13_MODE_Pos)                         /*!< SCU SFSPD_13: MODE Mask             */
#define SCU_SFSPD_13_EPD_Pos                                  3                                                         /*!< SCU SFSPD_13: EPD Position          */
#define SCU_SFSPD_13_EPD_Msk                                  (0x01UL << SCU_SFSPD_13_EPD_Pos)                          /*!< SCU SFSPD_13: EPD Mask              */
#define SCU_SFSPD_13_EPUN_Pos                                 4                                                         /*!< SCU SFSPD_13: EPUN Position         */
#define SCU_SFSPD_13_EPUN_Msk                                 (0x01UL << SCU_SFSPD_13_EPUN_Pos)                         /*!< SCU SFSPD_13: EPUN Mask             */
#define SCU_SFSPD_13_EHS_Pos                                  5                                                         /*!< SCU SFSPD_13: EHS Position          */
#define SCU_SFSPD_13_EHS_Msk                                  (0x01UL << SCU_SFSPD_13_EHS_Pos)                          /*!< SCU SFSPD_13: EHS Mask              */
#define SCU_SFSPD_13_EZI_Pos                                  6                                                         /*!< SCU SFSPD_13: EZI Position          */
#define SCU_SFSPD_13_EZI_Msk                                  (0x01UL << SCU_SFSPD_13_EZI_Pos)                          /*!< SCU SFSPD_13: EZI Mask              */
#define SCU_SFSPD_13_EHD_Pos                                  8                                                         /*!< SCU SFSPD_13: EHD Position          */
#define SCU_SFSPD_13_EHD_Msk                                  (0x03UL << SCU_SFSPD_13_EHD_Pos)                          /*!< SCU SFSPD_13: EHD Mask              */

// --------------------------------------  SCU_SFSPD_14  ------------------------------------------
#define SCU_SFSPD_14_MODE_Pos                                 0                                                         /*!< SCU SFSPD_14: MODE Position         */
#define SCU_SFSPD_14_MODE_Msk                                 (0x07UL << SCU_SFSPD_14_MODE_Pos)                         /*!< SCU SFSPD_14: MODE Mask             */
#define SCU_SFSPD_14_EPD_Pos                                  3                                                         /*!< SCU SFSPD_14: EPD Position          */
#define SCU_SFSPD_14_EPD_Msk                                  (0x01UL << SCU_SFSPD_14_EPD_Pos)                          /*!< SCU SFSPD_14: EPD Mask              */
#define SCU_SFSPD_14_EPUN_Pos                                 4                                                         /*!< SCU SFSPD_14: EPUN Position         */
#define SCU_SFSPD_14_EPUN_Msk                                 (0x01UL << SCU_SFSPD_14_EPUN_Pos)                         /*!< SCU SFSPD_14: EPUN Mask             */
#define SCU_SFSPD_14_EHS_Pos                                  5                                                         /*!< SCU SFSPD_14: EHS Position          */
#define SCU_SFSPD_14_EHS_Msk                                  (0x01UL << SCU_SFSPD_14_EHS_Pos)                          /*!< SCU SFSPD_14: EHS Mask              */
#define SCU_SFSPD_14_EZI_Pos                                  6                                                         /*!< SCU SFSPD_14: EZI Position          */
#define SCU_SFSPD_14_EZI_Msk                                  (0x01UL << SCU_SFSPD_14_EZI_Pos)                          /*!< SCU SFSPD_14: EZI Mask              */
#define SCU_SFSPD_14_EHD_Pos                                  8                                                         /*!< SCU SFSPD_14: EHD Position          */
#define SCU_SFSPD_14_EHD_Msk                                  (0x03UL << SCU_SFSPD_14_EHD_Pos)                          /*!< SCU SFSPD_14: EHD Mask              */

// --------------------------------------  SCU_SFSPD_15  ------------------------------------------
#define SCU_SFSPD_15_MODE_Pos                                 0                                                         /*!< SCU SFSPD_15: MODE Position         */
#define SCU_SFSPD_15_MODE_Msk                                 (0x07UL << SCU_SFSPD_15_MODE_Pos)                         /*!< SCU SFSPD_15: MODE Mask             */
#define SCU_SFSPD_15_EPD_Pos                                  3                                                         /*!< SCU SFSPD_15: EPD Position          */
#define SCU_SFSPD_15_EPD_Msk                                  (0x01UL << SCU_SFSPD_15_EPD_Pos)                          /*!< SCU SFSPD_15: EPD Mask              */
#define SCU_SFSPD_15_EPUN_Pos                                 4                                                         /*!< SCU SFSPD_15: EPUN Position         */
#define SCU_SFSPD_15_EPUN_Msk                                 (0x01UL << SCU_SFSPD_15_EPUN_Pos)                         /*!< SCU SFSPD_15: EPUN Mask             */
#define SCU_SFSPD_15_EHS_Pos                                  5                                                         /*!< SCU SFSPD_15: EHS Position          */
#define SCU_SFSPD_15_EHS_Msk                                  (0x01UL << SCU_SFSPD_15_EHS_Pos)                          /*!< SCU SFSPD_15: EHS Mask              */
#define SCU_SFSPD_15_EZI_Pos                                  6                                                         /*!< SCU SFSPD_15: EZI Position          */
#define SCU_SFSPD_15_EZI_Msk                                  (0x01UL << SCU_SFSPD_15_EZI_Pos)                          /*!< SCU SFSPD_15: EZI Mask              */
#define SCU_SFSPD_15_EHD_Pos                                  8                                                         /*!< SCU SFSPD_15: EHD Position          */
#define SCU_SFSPD_15_EHD_Msk                                  (0x03UL << SCU_SFSPD_15_EHD_Pos)                          /*!< SCU SFSPD_15: EHD Mask              */

// --------------------------------------  SCU_SFSPD_16  ------------------------------------------
#define SCU_SFSPD_16_MODE_Pos                                 0                                                         /*!< SCU SFSPD_16: MODE Position         */
#define SCU_SFSPD_16_MODE_Msk                                 (0x07UL << SCU_SFSPD_16_MODE_Pos)                         /*!< SCU SFSPD_16: MODE Mask             */
#define SCU_SFSPD_16_EPD_Pos                                  3                                                         /*!< SCU SFSPD_16: EPD Position          */
#define SCU_SFSPD_16_EPD_Msk                                  (0x01UL << SCU_SFSPD_16_EPD_Pos)                          /*!< SCU SFSPD_16: EPD Mask              */
#define SCU_SFSPD_16_EPUN_Pos                                 4                                                         /*!< SCU SFSPD_16: EPUN Position         */
#define SCU_SFSPD_16_EPUN_Msk                                 (0x01UL << SCU_SFSPD_16_EPUN_Pos)                         /*!< SCU SFSPD_16: EPUN Mask             */
#define SCU_SFSPD_16_EHS_Pos                                  5                                                         /*!< SCU SFSPD_16: EHS Position          */
#define SCU_SFSPD_16_EHS_Msk                                  (0x01UL << SCU_SFSPD_16_EHS_Pos)                          /*!< SCU SFSPD_16: EHS Mask              */
#define SCU_SFSPD_16_EZI_Pos                                  6                                                         /*!< SCU SFSPD_16: EZI Position          */
#define SCU_SFSPD_16_EZI_Msk                                  (0x01UL << SCU_SFSPD_16_EZI_Pos)                          /*!< SCU SFSPD_16: EZI Mask              */
#define SCU_SFSPD_16_EHD_Pos                                  8                                                         /*!< SCU SFSPD_16: EHD Position          */
#define SCU_SFSPD_16_EHD_Msk                                  (0x03UL << SCU_SFSPD_16_EHD_Pos)                          /*!< SCU SFSPD_16: EHD Mask              */

// ---------------------------------------  SCU_SFSPE_0  ------------------------------------------
#define SCU_SFSPE_0_MODE_Pos                                  0                                                         /*!< SCU SFSPE_0: MODE Position          */
#define SCU_SFSPE_0_MODE_Msk                                  (0x07UL << SCU_SFSPE_0_MODE_Pos)                          /*!< SCU SFSPE_0: MODE Mask              */
#define SCU_SFSPE_0_EPD_Pos                                   3                                                         /*!< SCU SFSPE_0: EPD Position           */
#define SCU_SFSPE_0_EPD_Msk                                   (0x01UL << SCU_SFSPE_0_EPD_Pos)                           /*!< SCU SFSPE_0: EPD Mask               */
#define SCU_SFSPE_0_EPUN_Pos                                  4                                                         /*!< SCU SFSPE_0: EPUN Position          */
#define SCU_SFSPE_0_EPUN_Msk                                  (0x01UL << SCU_SFSPE_0_EPUN_Pos)                          /*!< SCU SFSPE_0: EPUN Mask              */
#define SCU_SFSPE_0_EHS_Pos                                   5                                                         /*!< SCU SFSPE_0: EHS Position           */
#define SCU_SFSPE_0_EHS_Msk                                   (0x01UL << SCU_SFSPE_0_EHS_Pos)                           /*!< SCU SFSPE_0: EHS Mask               */
#define SCU_SFSPE_0_EZI_Pos                                   6                                                         /*!< SCU SFSPE_0: EZI Position           */
#define SCU_SFSPE_0_EZI_Msk                                   (0x01UL << SCU_SFSPE_0_EZI_Pos)                           /*!< SCU SFSPE_0: EZI Mask               */
#define SCU_SFSPE_0_EHD_Pos                                   8                                                         /*!< SCU SFSPE_0: EHD Position           */
#define SCU_SFSPE_0_EHD_Msk                                   (0x03UL << SCU_SFSPE_0_EHD_Pos)                           /*!< SCU SFSPE_0: EHD Mask               */

// ---------------------------------------  SCU_SFSPE_1  ------------------------------------------
#define SCU_SFSPE_1_MODE_Pos                                  0                                                         /*!< SCU SFSPE_1: MODE Position          */
#define SCU_SFSPE_1_MODE_Msk                                  (0x07UL << SCU_SFSPE_1_MODE_Pos)                          /*!< SCU SFSPE_1: MODE Mask              */
#define SCU_SFSPE_1_EPD_Pos                                   3                                                         /*!< SCU SFSPE_1: EPD Position           */
#define SCU_SFSPE_1_EPD_Msk                                   (0x01UL << SCU_SFSPE_1_EPD_Pos)                           /*!< SCU SFSPE_1: EPD Mask               */
#define SCU_SFSPE_1_EPUN_Pos                                  4                                                         /*!< SCU SFSPE_1: EPUN Position          */
#define SCU_SFSPE_1_EPUN_Msk                                  (0x01UL << SCU_SFSPE_1_EPUN_Pos)                          /*!< SCU SFSPE_1: EPUN Mask              */
#define SCU_SFSPE_1_EHS_Pos                                   5                                                         /*!< SCU SFSPE_1: EHS Position           */
#define SCU_SFSPE_1_EHS_Msk                                   (0x01UL << SCU_SFSPE_1_EHS_Pos)                           /*!< SCU SFSPE_1: EHS Mask               */
#define SCU_SFSPE_1_EZI_Pos                                   6                                                         /*!< SCU SFSPE_1: EZI Position           */
#define SCU_SFSPE_1_EZI_Msk                                   (0x01UL << SCU_SFSPE_1_EZI_Pos)                           /*!< SCU SFSPE_1: EZI Mask               */
#define SCU_SFSPE_1_EHD_Pos                                   8                                                         /*!< SCU SFSPE_1: EHD Position           */
#define SCU_SFSPE_1_EHD_Msk                                   (0x03UL << SCU_SFSPE_1_EHD_Pos)                           /*!< SCU SFSPE_1: EHD Mask               */

// ---------------------------------------  SCU_SFSPE_2  ------------------------------------------
#define SCU_SFSPE_2_MODE_Pos                                  0                                                         /*!< SCU SFSPE_2: MODE Position          */
#define SCU_SFSPE_2_MODE_Msk                                  (0x07UL << SCU_SFSPE_2_MODE_Pos)                          /*!< SCU SFSPE_2: MODE Mask              */
#define SCU_SFSPE_2_EPD_Pos                                   3                                                         /*!< SCU SFSPE_2: EPD Position           */
#define SCU_SFSPE_2_EPD_Msk                                   (0x01UL << SCU_SFSPE_2_EPD_Pos)                           /*!< SCU SFSPE_2: EPD Mask               */
#define SCU_SFSPE_2_EPUN_Pos                                  4                                                         /*!< SCU SFSPE_2: EPUN Position          */
#define SCU_SFSPE_2_EPUN_Msk                                  (0x01UL << SCU_SFSPE_2_EPUN_Pos)                          /*!< SCU SFSPE_2: EPUN Mask              */
#define SCU_SFSPE_2_EHS_Pos                                   5                                                         /*!< SCU SFSPE_2: EHS Position           */
#define SCU_SFSPE_2_EHS_Msk                                   (0x01UL << SCU_SFSPE_2_EHS_Pos)                           /*!< SCU SFSPE_2: EHS Mask               */
#define SCU_SFSPE_2_EZI_Pos                                   6                                                         /*!< SCU SFSPE_2: EZI Position           */
#define SCU_SFSPE_2_EZI_Msk                                   (0x01UL << SCU_SFSPE_2_EZI_Pos)                           /*!< SCU SFSPE_2: EZI Mask               */
#define SCU_SFSPE_2_EHD_Pos                                   8                                                         /*!< SCU SFSPE_2: EHD Position           */
#define SCU_SFSPE_2_EHD_Msk                                   (0x03UL << SCU_SFSPE_2_EHD_Pos)                           /*!< SCU SFSPE_2: EHD Mask               */

// ---------------------------------------  SCU_SFSPE_3  ------------------------------------------
#define SCU_SFSPE_3_MODE_Pos                                  0                                                         /*!< SCU SFSPE_3: MODE Position          */
#define SCU_SFSPE_3_MODE_Msk                                  (0x07UL << SCU_SFSPE_3_MODE_Pos)                          /*!< SCU SFSPE_3: MODE Mask              */
#define SCU_SFSPE_3_EPD_Pos                                   3                                                         /*!< SCU SFSPE_3: EPD Position           */
#define SCU_SFSPE_3_EPD_Msk                                   (0x01UL << SCU_SFSPE_3_EPD_Pos)                           /*!< SCU SFSPE_3: EPD Mask               */
#define SCU_SFSPE_3_EPUN_Pos                                  4                                                         /*!< SCU SFSPE_3: EPUN Position          */
#define SCU_SFSPE_3_EPUN_Msk                                  (0x01UL << SCU_SFSPE_3_EPUN_Pos)                          /*!< SCU SFSPE_3: EPUN Mask              */
#define SCU_SFSPE_3_EHS_Pos                                   5                                                         /*!< SCU SFSPE_3: EHS Position           */
#define SCU_SFSPE_3_EHS_Msk                                   (0x01UL << SCU_SFSPE_3_EHS_Pos)                           /*!< SCU SFSPE_3: EHS Mask               */
#define SCU_SFSPE_3_EZI_Pos                                   6                                                         /*!< SCU SFSPE_3: EZI Position           */
#define SCU_SFSPE_3_EZI_Msk                                   (0x01UL << SCU_SFSPE_3_EZI_Pos)                           /*!< SCU SFSPE_3: EZI Mask               */
#define SCU_SFSPE_3_EHD_Pos                                   8                                                         /*!< SCU SFSPE_3: EHD Position           */
#define SCU_SFSPE_3_EHD_Msk                                   (0x03UL << SCU_SFSPE_3_EHD_Pos)                           /*!< SCU SFSPE_3: EHD Mask               */

// ---------------------------------------  SCU_SFSPE_4  ------------------------------------------
#define SCU_SFSPE_4_MODE_Pos                                  0                                                         /*!< SCU SFSPE_4: MODE Position          */
#define SCU_SFSPE_4_MODE_Msk                                  (0x07UL << SCU_SFSPE_4_MODE_Pos)                          /*!< SCU SFSPE_4: MODE Mask              */
#define SCU_SFSPE_4_EPD_Pos                                   3                                                         /*!< SCU SFSPE_4: EPD Position           */
#define SCU_SFSPE_4_EPD_Msk                                   (0x01UL << SCU_SFSPE_4_EPD_Pos)                           /*!< SCU SFSPE_4: EPD Mask               */
#define SCU_SFSPE_4_EPUN_Pos                                  4                                                         /*!< SCU SFSPE_4: EPUN Position          */
#define SCU_SFSPE_4_EPUN_Msk                                  (0x01UL << SCU_SFSPE_4_EPUN_Pos)                          /*!< SCU SFSPE_4: EPUN Mask              */
#define SCU_SFSPE_4_EHS_Pos                                   5                                                         /*!< SCU SFSPE_4: EHS Position           */
#define SCU_SFSPE_4_EHS_Msk                                   (0x01UL << SCU_SFSPE_4_EHS_Pos)                           /*!< SCU SFSPE_4: EHS Mask               */
#define SCU_SFSPE_4_EZI_Pos                                   6                                                         /*!< SCU SFSPE_4: EZI Position           */
#define SCU_SFSPE_4_EZI_Msk                                   (0x01UL << SCU_SFSPE_4_EZI_Pos)                           /*!< SCU SFSPE_4: EZI Mask               */
#define SCU_SFSPE_4_EHD_Pos                                   8                                                         /*!< SCU SFSPE_4: EHD Position           */
#define SCU_SFSPE_4_EHD_Msk                                   (0x03UL << SCU_SFSPE_4_EHD_Pos)                           /*!< SCU SFSPE_4: EHD Mask               */

// ---------------------------------------  SCU_SFSPE_5  ------------------------------------------
#define SCU_SFSPE_5_MODE_Pos                                  0                                                         /*!< SCU SFSPE_5: MODE Position          */
#define SCU_SFSPE_5_MODE_Msk                                  (0x07UL << SCU_SFSPE_5_MODE_Pos)                          /*!< SCU SFSPE_5: MODE Mask              */
#define SCU_SFSPE_5_EPD_Pos                                   3                                                         /*!< SCU SFSPE_5: EPD Position           */
#define SCU_SFSPE_5_EPD_Msk                                   (0x01UL << SCU_SFSPE_5_EPD_Pos)                           /*!< SCU SFSPE_5: EPD Mask               */
#define SCU_SFSPE_5_EPUN_Pos                                  4                                                         /*!< SCU SFSPE_5: EPUN Position          */
#define SCU_SFSPE_5_EPUN_Msk                                  (0x01UL << SCU_SFSPE_5_EPUN_Pos)                          /*!< SCU SFSPE_5: EPUN Mask              */
#define SCU_SFSPE_5_EHS_Pos                                   5                                                         /*!< SCU SFSPE_5: EHS Position           */
#define SCU_SFSPE_5_EHS_Msk                                   (0x01UL << SCU_SFSPE_5_EHS_Pos)                           /*!< SCU SFSPE_5: EHS Mask               */
#define SCU_SFSPE_5_EZI_Pos                                   6                                                         /*!< SCU SFSPE_5: EZI Position           */
#define SCU_SFSPE_5_EZI_Msk                                   (0x01UL << SCU_SFSPE_5_EZI_Pos)                           /*!< SCU SFSPE_5: EZI Mask               */
#define SCU_SFSPE_5_EHD_Pos                                   8                                                         /*!< SCU SFSPE_5: EHD Position           */
#define SCU_SFSPE_5_EHD_Msk                                   (0x03UL << SCU_SFSPE_5_EHD_Pos)                           /*!< SCU SFSPE_5: EHD Mask               */

// ---------------------------------------  SCU_SFSPE_6  ------------------------------------------
#define SCU_SFSPE_6_MODE_Pos                                  0                                                         /*!< SCU SFSPE_6: MODE Position          */
#define SCU_SFSPE_6_MODE_Msk                                  (0x07UL << SCU_SFSPE_6_MODE_Pos)                          /*!< SCU SFSPE_6: MODE Mask              */
#define SCU_SFSPE_6_EPD_Pos                                   3                                                         /*!< SCU SFSPE_6: EPD Position           */
#define SCU_SFSPE_6_EPD_Msk                                   (0x01UL << SCU_SFSPE_6_EPD_Pos)                           /*!< SCU SFSPE_6: EPD Mask               */
#define SCU_SFSPE_6_EPUN_Pos                                  4                                                         /*!< SCU SFSPE_6: EPUN Position          */
#define SCU_SFSPE_6_EPUN_Msk                                  (0x01UL << SCU_SFSPE_6_EPUN_Pos)                          /*!< SCU SFSPE_6: EPUN Mask              */
#define SCU_SFSPE_6_EHS_Pos                                   5                                                         /*!< SCU SFSPE_6: EHS Position           */
#define SCU_SFSPE_6_EHS_Msk                                   (0x01UL << SCU_SFSPE_6_EHS_Pos)                           /*!< SCU SFSPE_6: EHS Mask               */
#define SCU_SFSPE_6_EZI_Pos                                   6                                                         /*!< SCU SFSPE_6: EZI Position           */
#define SCU_SFSPE_6_EZI_Msk                                   (0x01UL << SCU_SFSPE_6_EZI_Pos)                           /*!< SCU SFSPE_6: EZI Mask               */
#define SCU_SFSPE_6_EHD_Pos                                   8                                                         /*!< SCU SFSPE_6: EHD Position           */
#define SCU_SFSPE_6_EHD_Msk                                   (0x03UL << SCU_SFSPE_6_EHD_Pos)                           /*!< SCU SFSPE_6: EHD Mask               */

// ---------------------------------------  SCU_SFSPE_7  ------------------------------------------
#define SCU_SFSPE_7_MODE_Pos                                  0                                                         /*!< SCU SFSPE_7: MODE Position          */
#define SCU_SFSPE_7_MODE_Msk                                  (0x07UL << SCU_SFSPE_7_MODE_Pos)                          /*!< SCU SFSPE_7: MODE Mask              */
#define SCU_SFSPE_7_EPD_Pos                                   3                                                         /*!< SCU SFSPE_7: EPD Position           */
#define SCU_SFSPE_7_EPD_Msk                                   (0x01UL << SCU_SFSPE_7_EPD_Pos)                           /*!< SCU SFSPE_7: EPD Mask               */
#define SCU_SFSPE_7_EPUN_Pos                                  4                                                         /*!< SCU SFSPE_7: EPUN Position          */
#define SCU_SFSPE_7_EPUN_Msk                                  (0x01UL << SCU_SFSPE_7_EPUN_Pos)                          /*!< SCU SFSPE_7: EPUN Mask              */
#define SCU_SFSPE_7_EHS_Pos                                   5                                                         /*!< SCU SFSPE_7: EHS Position           */
#define SCU_SFSPE_7_EHS_Msk                                   (0x01UL << SCU_SFSPE_7_EHS_Pos)                           /*!< SCU SFSPE_7: EHS Mask               */
#define SCU_SFSPE_7_EZI_Pos                                   6                                                         /*!< SCU SFSPE_7: EZI Position           */
#define SCU_SFSPE_7_EZI_Msk                                   (0x01UL << SCU_SFSPE_7_EZI_Pos)                           /*!< SCU SFSPE_7: EZI Mask               */
#define SCU_SFSPE_7_EHD_Pos                                   8                                                         /*!< SCU SFSPE_7: EHD Position           */
#define SCU_SFSPE_7_EHD_Msk                                   (0x03UL << SCU_SFSPE_7_EHD_Pos)                           /*!< SCU SFSPE_7: EHD Mask               */

// ---------------------------------------  SCU_SFSPE_8  ------------------------------------------
#define SCU_SFSPE_8_MODE_Pos                                  0                                                         /*!< SCU SFSPE_8: MODE Position          */
#define SCU_SFSPE_8_MODE_Msk                                  (0x07UL << SCU_SFSPE_8_MODE_Pos)                          /*!< SCU SFSPE_8: MODE Mask              */
#define SCU_SFSPE_8_EPD_Pos                                   3                                                         /*!< SCU SFSPE_8: EPD Position           */
#define SCU_SFSPE_8_EPD_Msk                                   (0x01UL << SCU_SFSPE_8_EPD_Pos)                           /*!< SCU SFSPE_8: EPD Mask               */
#define SCU_SFSPE_8_EPUN_Pos                                  4                                                         /*!< SCU SFSPE_8: EPUN Position          */
#define SCU_SFSPE_8_EPUN_Msk                                  (0x01UL << SCU_SFSPE_8_EPUN_Pos)                          /*!< SCU SFSPE_8: EPUN Mask              */
#define SCU_SFSPE_8_EHS_Pos                                   5                                                         /*!< SCU SFSPE_8: EHS Position           */
#define SCU_SFSPE_8_EHS_Msk                                   (0x01UL << SCU_SFSPE_8_EHS_Pos)                           /*!< SCU SFSPE_8: EHS Mask               */
#define SCU_SFSPE_8_EZI_Pos                                   6                                                         /*!< SCU SFSPE_8: EZI Position           */
#define SCU_SFSPE_8_EZI_Msk                                   (0x01UL << SCU_SFSPE_8_EZI_Pos)                           /*!< SCU SFSPE_8: EZI Mask               */
#define SCU_SFSPE_8_EHD_Pos                                   8                                                         /*!< SCU SFSPE_8: EHD Position           */
#define SCU_SFSPE_8_EHD_Msk                                   (0x03UL << SCU_SFSPE_8_EHD_Pos)                           /*!< SCU SFSPE_8: EHD Mask               */

// ---------------------------------------  SCU_SFSPE_9  ------------------------------------------
#define SCU_SFSPE_9_MODE_Pos                                  0                                                         /*!< SCU SFSPE_9: MODE Position          */
#define SCU_SFSPE_9_MODE_Msk                                  (0x07UL << SCU_SFSPE_9_MODE_Pos)                          /*!< SCU SFSPE_9: MODE Mask              */
#define SCU_SFSPE_9_EPD_Pos                                   3                                                         /*!< SCU SFSPE_9: EPD Position           */
#define SCU_SFSPE_9_EPD_Msk                                   (0x01UL << SCU_SFSPE_9_EPD_Pos)                           /*!< SCU SFSPE_9: EPD Mask               */
#define SCU_SFSPE_9_EPUN_Pos                                  4                                                         /*!< SCU SFSPE_9: EPUN Position          */
#define SCU_SFSPE_9_EPUN_Msk                                  (0x01UL << SCU_SFSPE_9_EPUN_Pos)                          /*!< SCU SFSPE_9: EPUN Mask              */
#define SCU_SFSPE_9_EHS_Pos                                   5                                                         /*!< SCU SFSPE_9: EHS Position           */
#define SCU_SFSPE_9_EHS_Msk                                   (0x01UL << SCU_SFSPE_9_EHS_Pos)                           /*!< SCU SFSPE_9: EHS Mask               */
#define SCU_SFSPE_9_EZI_Pos                                   6                                                         /*!< SCU SFSPE_9: EZI Position           */
#define SCU_SFSPE_9_EZI_Msk                                   (0x01UL << SCU_SFSPE_9_EZI_Pos)                           /*!< SCU SFSPE_9: EZI Mask               */
#define SCU_SFSPE_9_EHD_Pos                                   8                                                         /*!< SCU SFSPE_9: EHD Position           */
#define SCU_SFSPE_9_EHD_Msk                                   (0x03UL << SCU_SFSPE_9_EHD_Pos)                           /*!< SCU SFSPE_9: EHD Mask               */

// --------------------------------------  SCU_SFSPE_10  ------------------------------------------
#define SCU_SFSPE_10_MODE_Pos                                 0                                                         /*!< SCU SFSPE_10: MODE Position         */
#define SCU_SFSPE_10_MODE_Msk                                 (0x07UL << SCU_SFSPE_10_MODE_Pos)                         /*!< SCU SFSPE_10: MODE Mask             */
#define SCU_SFSPE_10_EPD_Pos                                  3                                                         /*!< SCU SFSPE_10: EPD Position          */
#define SCU_SFSPE_10_EPD_Msk                                  (0x01UL << SCU_SFSPE_10_EPD_Pos)                          /*!< SCU SFSPE_10: EPD Mask              */
#define SCU_SFSPE_10_EPUN_Pos                                 4                                                         /*!< SCU SFSPE_10: EPUN Position         */
#define SCU_SFSPE_10_EPUN_Msk                                 (0x01UL << SCU_SFSPE_10_EPUN_Pos)                         /*!< SCU SFSPE_10: EPUN Mask             */
#define SCU_SFSPE_10_EHS_Pos                                  5                                                         /*!< SCU SFSPE_10: EHS Position          */
#define SCU_SFSPE_10_EHS_Msk                                  (0x01UL << SCU_SFSPE_10_EHS_Pos)                          /*!< SCU SFSPE_10: EHS Mask              */
#define SCU_SFSPE_10_EZI_Pos                                  6                                                         /*!< SCU SFSPE_10: EZI Position          */
#define SCU_SFSPE_10_EZI_Msk                                  (0x01UL << SCU_SFSPE_10_EZI_Pos)                          /*!< SCU SFSPE_10: EZI Mask              */
#define SCU_SFSPE_10_EHD_Pos                                  8                                                         /*!< SCU SFSPE_10: EHD Position          */
#define SCU_SFSPE_10_EHD_Msk                                  (0x03UL << SCU_SFSPE_10_EHD_Pos)                          /*!< SCU SFSPE_10: EHD Mask              */

// --------------------------------------  SCU_SFSPE_11  ------------------------------------------
#define SCU_SFSPE_11_MODE_Pos                                 0                                                         /*!< SCU SFSPE_11: MODE Position         */
#define SCU_SFSPE_11_MODE_Msk                                 (0x07UL << SCU_SFSPE_11_MODE_Pos)                         /*!< SCU SFSPE_11: MODE Mask             */
#define SCU_SFSPE_11_EPD_Pos                                  3                                                         /*!< SCU SFSPE_11: EPD Position          */
#define SCU_SFSPE_11_EPD_Msk                                  (0x01UL << SCU_SFSPE_11_EPD_Pos)                          /*!< SCU SFSPE_11: EPD Mask              */
#define SCU_SFSPE_11_EPUN_Pos                                 4                                                         /*!< SCU SFSPE_11: EPUN Position         */
#define SCU_SFSPE_11_EPUN_Msk                                 (0x01UL << SCU_SFSPE_11_EPUN_Pos)                         /*!< SCU SFSPE_11: EPUN Mask             */
#define SCU_SFSPE_11_EHS_Pos                                  5                                                         /*!< SCU SFSPE_11: EHS Position          */
#define SCU_SFSPE_11_EHS_Msk                                  (0x01UL << SCU_SFSPE_11_EHS_Pos)                          /*!< SCU SFSPE_11: EHS Mask              */
#define SCU_SFSPE_11_EZI_Pos                                  6                                                         /*!< SCU SFSPE_11: EZI Position          */
#define SCU_SFSPE_11_EZI_Msk                                  (0x01UL << SCU_SFSPE_11_EZI_Pos)                          /*!< SCU SFSPE_11: EZI Mask              */
#define SCU_SFSPE_11_EHD_Pos                                  8                                                         /*!< SCU SFSPE_11: EHD Position          */
#define SCU_SFSPE_11_EHD_Msk                                  (0x03UL << SCU_SFSPE_11_EHD_Pos)                          /*!< SCU SFSPE_11: EHD Mask              */

// --------------------------------------  SCU_SFSPE_12  ------------------------------------------
#define SCU_SFSPE_12_MODE_Pos                                 0                                                         /*!< SCU SFSPE_12: MODE Position         */
#define SCU_SFSPE_12_MODE_Msk                                 (0x07UL << SCU_SFSPE_12_MODE_Pos)                         /*!< SCU SFSPE_12: MODE Mask             */
#define SCU_SFSPE_12_EPD_Pos                                  3                                                         /*!< SCU SFSPE_12: EPD Position          */
#define SCU_SFSPE_12_EPD_Msk                                  (0x01UL << SCU_SFSPE_12_EPD_Pos)                          /*!< SCU SFSPE_12: EPD Mask              */
#define SCU_SFSPE_12_EPUN_Pos                                 4                                                         /*!< SCU SFSPE_12: EPUN Position         */
#define SCU_SFSPE_12_EPUN_Msk                                 (0x01UL << SCU_SFSPE_12_EPUN_Pos)                         /*!< SCU SFSPE_12: EPUN Mask             */
#define SCU_SFSPE_12_EHS_Pos                                  5                                                         /*!< SCU SFSPE_12: EHS Position          */
#define SCU_SFSPE_12_EHS_Msk                                  (0x01UL << SCU_SFSPE_12_EHS_Pos)                          /*!< SCU SFSPE_12: EHS Mask              */
#define SCU_SFSPE_12_EZI_Pos                                  6                                                         /*!< SCU SFSPE_12: EZI Position          */
#define SCU_SFSPE_12_EZI_Msk                                  (0x01UL << SCU_SFSPE_12_EZI_Pos)                          /*!< SCU SFSPE_12: EZI Mask              */
#define SCU_SFSPE_12_EHD_Pos                                  8                                                         /*!< SCU SFSPE_12: EHD Position          */
#define SCU_SFSPE_12_EHD_Msk                                  (0x03UL << SCU_SFSPE_12_EHD_Pos)                          /*!< SCU SFSPE_12: EHD Mask              */

// --------------------------------------  SCU_SFSPE_13  ------------------------------------------
#define SCU_SFSPE_13_MODE_Pos                                 0                                                         /*!< SCU SFSPE_13: MODE Position         */
#define SCU_SFSPE_13_MODE_Msk                                 (0x07UL << SCU_SFSPE_13_MODE_Pos)                         /*!< SCU SFSPE_13: MODE Mask             */
#define SCU_SFSPE_13_EPD_Pos                                  3                                                         /*!< SCU SFSPE_13: EPD Position          */
#define SCU_SFSPE_13_EPD_Msk                                  (0x01UL << SCU_SFSPE_13_EPD_Pos)                          /*!< SCU SFSPE_13: EPD Mask              */
#define SCU_SFSPE_13_EPUN_Pos                                 4                                                         /*!< SCU SFSPE_13: EPUN Position         */
#define SCU_SFSPE_13_EPUN_Msk                                 (0x01UL << SCU_SFSPE_13_EPUN_Pos)                         /*!< SCU SFSPE_13: EPUN Mask             */
#define SCU_SFSPE_13_EHS_Pos                                  5                                                         /*!< SCU SFSPE_13: EHS Position          */
#define SCU_SFSPE_13_EHS_Msk                                  (0x01UL << SCU_SFSPE_13_EHS_Pos)                          /*!< SCU SFSPE_13: EHS Mask              */
#define SCU_SFSPE_13_EZI_Pos                                  6                                                         /*!< SCU SFSPE_13: EZI Position          */
#define SCU_SFSPE_13_EZI_Msk                                  (0x01UL << SCU_SFSPE_13_EZI_Pos)                          /*!< SCU SFSPE_13: EZI Mask              */
#define SCU_SFSPE_13_EHD_Pos                                  8                                                         /*!< SCU SFSPE_13: EHD Position          */
#define SCU_SFSPE_13_EHD_Msk                                  (0x03UL << SCU_SFSPE_13_EHD_Pos)                          /*!< SCU SFSPE_13: EHD Mask              */

// --------------------------------------  SCU_SFSPE_14  ------------------------------------------
#define SCU_SFSPE_14_MODE_Pos                                 0                                                         /*!< SCU SFSPE_14: MODE Position         */
#define SCU_SFSPE_14_MODE_Msk                                 (0x07UL << SCU_SFSPE_14_MODE_Pos)                         /*!< SCU SFSPE_14: MODE Mask             */
#define SCU_SFSPE_14_EPD_Pos                                  3                                                         /*!< SCU SFSPE_14: EPD Position          */
#define SCU_SFSPE_14_EPD_Msk                                  (0x01UL << SCU_SFSPE_14_EPD_Pos)                          /*!< SCU SFSPE_14: EPD Mask              */
#define SCU_SFSPE_14_EPUN_Pos                                 4                                                         /*!< SCU SFSPE_14: EPUN Position         */
#define SCU_SFSPE_14_EPUN_Msk                                 (0x01UL << SCU_SFSPE_14_EPUN_Pos)                         /*!< SCU SFSPE_14: EPUN Mask             */
#define SCU_SFSPE_14_EHS_Pos                                  5                                                         /*!< SCU SFSPE_14: EHS Position          */
#define SCU_SFSPE_14_EHS_Msk                                  (0x01UL << SCU_SFSPE_14_EHS_Pos)                          /*!< SCU SFSPE_14: EHS Mask              */
#define SCU_SFSPE_14_EZI_Pos                                  6                                                         /*!< SCU SFSPE_14: EZI Position          */
#define SCU_SFSPE_14_EZI_Msk                                  (0x01UL << SCU_SFSPE_14_EZI_Pos)                          /*!< SCU SFSPE_14: EZI Mask              */
#define SCU_SFSPE_14_EHD_Pos                                  8                                                         /*!< SCU SFSPE_14: EHD Position          */
#define SCU_SFSPE_14_EHD_Msk                                  (0x03UL << SCU_SFSPE_14_EHD_Pos)                          /*!< SCU SFSPE_14: EHD Mask              */

// --------------------------------------  SCU_SFSPE_15  ------------------------------------------
#define SCU_SFSPE_15_MODE_Pos                                 0                                                         /*!< SCU SFSPE_15: MODE Position         */
#define SCU_SFSPE_15_MODE_Msk                                 (0x07UL << SCU_SFSPE_15_MODE_Pos)                         /*!< SCU SFSPE_15: MODE Mask             */
#define SCU_SFSPE_15_EPD_Pos                                  3                                                         /*!< SCU SFSPE_15: EPD Position          */
#define SCU_SFSPE_15_EPD_Msk                                  (0x01UL << SCU_SFSPE_15_EPD_Pos)                          /*!< SCU SFSPE_15: EPD Mask              */
#define SCU_SFSPE_15_EPUN_Pos                                 4                                                         /*!< SCU SFSPE_15: EPUN Position         */
#define SCU_SFSPE_15_EPUN_Msk                                 (0x01UL << SCU_SFSPE_15_EPUN_Pos)                         /*!< SCU SFSPE_15: EPUN Mask             */
#define SCU_SFSPE_15_EHS_Pos                                  5                                                         /*!< SCU SFSPE_15: EHS Position          */
#define SCU_SFSPE_15_EHS_Msk                                  (0x01UL << SCU_SFSPE_15_EHS_Pos)                          /*!< SCU SFSPE_15: EHS Mask              */
#define SCU_SFSPE_15_EZI_Pos                                  6                                                         /*!< SCU SFSPE_15: EZI Position          */
#define SCU_SFSPE_15_EZI_Msk                                  (0x01UL << SCU_SFSPE_15_EZI_Pos)                          /*!< SCU SFSPE_15: EZI Mask              */
#define SCU_SFSPE_15_EHD_Pos                                  8                                                         /*!< SCU SFSPE_15: EHD Position          */
#define SCU_SFSPE_15_EHD_Msk                                  (0x03UL << SCU_SFSPE_15_EHD_Pos)                          /*!< SCU SFSPE_15: EHD Mask              */

// ---------------------------------------  SCU_SFSPF_0  ------------------------------------------
#define SCU_SFSPF_0_MODE_Pos                                  0                                                         /*!< SCU SFSPF_0: MODE Position          */
#define SCU_SFSPF_0_MODE_Msk                                  (0x07UL << SCU_SFSPF_0_MODE_Pos)                          /*!< SCU SFSPF_0: MODE Mask              */
#define SCU_SFSPF_0_EPD_Pos                                   3                                                         /*!< SCU SFSPF_0: EPD Position           */
#define SCU_SFSPF_0_EPD_Msk                                   (0x01UL << SCU_SFSPF_0_EPD_Pos)                           /*!< SCU SFSPF_0: EPD Mask               */
#define SCU_SFSPF_0_EPUN_Pos                                  4                                                         /*!< SCU SFSPF_0: EPUN Position          */
#define SCU_SFSPF_0_EPUN_Msk                                  (0x01UL << SCU_SFSPF_0_EPUN_Pos)                          /*!< SCU SFSPF_0: EPUN Mask              */
#define SCU_SFSPF_0_EHS_Pos                                   5                                                         /*!< SCU SFSPF_0: EHS Position           */
#define SCU_SFSPF_0_EHS_Msk                                   (0x01UL << SCU_SFSPF_0_EHS_Pos)                           /*!< SCU SFSPF_0: EHS Mask               */
#define SCU_SFSPF_0_EZI_Pos                                   6                                                         /*!< SCU SFSPF_0: EZI Position           */
#define SCU_SFSPF_0_EZI_Msk                                   (0x01UL << SCU_SFSPF_0_EZI_Pos)                           /*!< SCU SFSPF_0: EZI Mask               */
#define SCU_SFSPF_0_EHD_Pos                                   8                                                         /*!< SCU SFSPF_0: EHD Position           */
#define SCU_SFSPF_0_EHD_Msk                                   (0x03UL << SCU_SFSPF_0_EHD_Pos)                           /*!< SCU SFSPF_0: EHD Mask               */

// ---------------------------------------  SCU_SFSPF_1  ------------------------------------------
#define SCU_SFSPF_1_MODE_Pos                                  0                                                         /*!< SCU SFSPF_1: MODE Position          */
#define SCU_SFSPF_1_MODE_Msk                                  (0x07UL << SCU_SFSPF_1_MODE_Pos)                          /*!< SCU SFSPF_1: MODE Mask              */
#define SCU_SFSPF_1_EPD_Pos                                   3                                                         /*!< SCU SFSPF_1: EPD Position           */
#define SCU_SFSPF_1_EPD_Msk                                   (0x01UL << SCU_SFSPF_1_EPD_Pos)                           /*!< SCU SFSPF_1: EPD Mask               */
#define SCU_SFSPF_1_EPUN_Pos                                  4                                                         /*!< SCU SFSPF_1: EPUN Position          */
#define SCU_SFSPF_1_EPUN_Msk                                  (0x01UL << SCU_SFSPF_1_EPUN_Pos)                          /*!< SCU SFSPF_1: EPUN Mask              */
#define SCU_SFSPF_1_EHS_Pos                                   5                                                         /*!< SCU SFSPF_1: EHS Position           */
#define SCU_SFSPF_1_EHS_Msk                                   (0x01UL << SCU_SFSPF_1_EHS_Pos)                           /*!< SCU SFSPF_1: EHS Mask               */
#define SCU_SFSPF_1_EZI_Pos                                   6                                                         /*!< SCU SFSPF_1: EZI Position           */
#define SCU_SFSPF_1_EZI_Msk                                   (0x01UL << SCU_SFSPF_1_EZI_Pos)                           /*!< SCU SFSPF_1: EZI Mask               */
#define SCU_SFSPF_1_EHD_Pos                                   8                                                         /*!< SCU SFSPF_1: EHD Position           */
#define SCU_SFSPF_1_EHD_Msk                                   (0x03UL << SCU_SFSPF_1_EHD_Pos)                           /*!< SCU SFSPF_1: EHD Mask               */

// ---------------------------------------  SCU_SFSPF_2  ------------------------------------------
#define SCU_SFSPF_2_MODE_Pos                                  0                                                         /*!< SCU SFSPF_2: MODE Position          */
#define SCU_SFSPF_2_MODE_Msk                                  (0x07UL << SCU_SFSPF_2_MODE_Pos)                          /*!< SCU SFSPF_2: MODE Mask              */
#define SCU_SFSPF_2_EPD_Pos                                   3                                                         /*!< SCU SFSPF_2: EPD Position           */
#define SCU_SFSPF_2_EPD_Msk                                   (0x01UL << SCU_SFSPF_2_EPD_Pos)                           /*!< SCU SFSPF_2: EPD Mask               */
#define SCU_SFSPF_2_EPUN_Pos                                  4                                                         /*!< SCU SFSPF_2: EPUN Position          */
#define SCU_SFSPF_2_EPUN_Msk                                  (0x01UL << SCU_SFSPF_2_EPUN_Pos)                          /*!< SCU SFSPF_2: EPUN Mask              */
#define SCU_SFSPF_2_EHS_Pos                                   5                                                         /*!< SCU SFSPF_2: EHS Position           */
#define SCU_SFSPF_2_EHS_Msk                                   (0x01UL << SCU_SFSPF_2_EHS_Pos)                           /*!< SCU SFSPF_2: EHS Mask               */
#define SCU_SFSPF_2_EZI_Pos                                   6                                                         /*!< SCU SFSPF_2: EZI Position           */
#define SCU_SFSPF_2_EZI_Msk                                   (0x01UL << SCU_SFSPF_2_EZI_Pos)                           /*!< SCU SFSPF_2: EZI Mask               */
#define SCU_SFSPF_2_EHD_Pos                                   8                                                         /*!< SCU SFSPF_2: EHD Position           */
#define SCU_SFSPF_2_EHD_Msk                                   (0x03UL << SCU_SFSPF_2_EHD_Pos)                           /*!< SCU SFSPF_2: EHD Mask               */

// ---------------------------------------  SCU_SFSPF_3  ------------------------------------------
#define SCU_SFSPF_3_MODE_Pos                                  0                                                         /*!< SCU SFSPF_3: MODE Position          */
#define SCU_SFSPF_3_MODE_Msk                                  (0x07UL << SCU_SFSPF_3_MODE_Pos)                          /*!< SCU SFSPF_3: MODE Mask              */
#define SCU_SFSPF_3_EPD_Pos                                   3                                                         /*!< SCU SFSPF_3: EPD Position           */
#define SCU_SFSPF_3_EPD_Msk                                   (0x01UL << SCU_SFSPF_3_EPD_Pos)                           /*!< SCU SFSPF_3: EPD Mask               */
#define SCU_SFSPF_3_EPUN_Pos                                  4                                                         /*!< SCU SFSPF_3: EPUN Position          */
#define SCU_SFSPF_3_EPUN_Msk                                  (0x01UL << SCU_SFSPF_3_EPUN_Pos)                          /*!< SCU SFSPF_3: EPUN Mask              */
#define SCU_SFSPF_3_EHS_Pos                                   5                                                         /*!< SCU SFSPF_3: EHS Position           */
#define SCU_SFSPF_3_EHS_Msk                                   (0x01UL << SCU_SFSPF_3_EHS_Pos)                           /*!< SCU SFSPF_3: EHS Mask               */
#define SCU_SFSPF_3_EZI_Pos                                   6                                                         /*!< SCU SFSPF_3: EZI Position           */
#define SCU_SFSPF_3_EZI_Msk                                   (0x01UL << SCU_SFSPF_3_EZI_Pos)                           /*!< SCU SFSPF_3: EZI Mask               */
#define SCU_SFSPF_3_EHD_Pos                                   8                                                         /*!< SCU SFSPF_3: EHD Position           */
#define SCU_SFSPF_3_EHD_Msk                                   (0x03UL << SCU_SFSPF_3_EHD_Pos)                           /*!< SCU SFSPF_3: EHD Mask               */

// ---------------------------------------  SCU_SFSPF_4  ------------------------------------------
#define SCU_SFSPF_4_MODE_Pos                                  0                                                         /*!< SCU SFSPF_4: MODE Position          */
#define SCU_SFSPF_4_MODE_Msk                                  (0x07UL << SCU_SFSPF_4_MODE_Pos)                          /*!< SCU SFSPF_4: MODE Mask              */
#define SCU_SFSPF_4_EPD_Pos                                   3                                                         /*!< SCU SFSPF_4: EPD Position           */
#define SCU_SFSPF_4_EPD_Msk                                   (0x01UL << SCU_SFSPF_4_EPD_Pos)                           /*!< SCU SFSPF_4: EPD Mask               */
#define SCU_SFSPF_4_EPUN_Pos                                  4                                                         /*!< SCU SFSPF_4: EPUN Position          */
#define SCU_SFSPF_4_EPUN_Msk                                  (0x01UL << SCU_SFSPF_4_EPUN_Pos)                          /*!< SCU SFSPF_4: EPUN Mask              */
#define SCU_SFSPF_4_EHS_Pos                                   5                                                         /*!< SCU SFSPF_4: EHS Position           */
#define SCU_SFSPF_4_EHS_Msk                                   (0x01UL << SCU_SFSPF_4_EHS_Pos)                           /*!< SCU SFSPF_4: EHS Mask               */
#define SCU_SFSPF_4_EZI_Pos                                   6                                                         /*!< SCU SFSPF_4: EZI Position           */
#define SCU_SFSPF_4_EZI_Msk                                   (0x01UL << SCU_SFSPF_4_EZI_Pos)                           /*!< SCU SFSPF_4: EZI Mask               */
#define SCU_SFSPF_4_EHD_Pos                                   8                                                         /*!< SCU SFSPF_4: EHD Position           */
#define SCU_SFSPF_4_EHD_Msk                                   (0x03UL << SCU_SFSPF_4_EHD_Pos)                           /*!< SCU SFSPF_4: EHD Mask               */

// ---------------------------------------  SCU_SFSPF_5  ------------------------------------------
#define SCU_SFSPF_5_MODE_Pos                                  0                                                         /*!< SCU SFSPF_5: MODE Position          */
#define SCU_SFSPF_5_MODE_Msk                                  (0x07UL << SCU_SFSPF_5_MODE_Pos)                          /*!< SCU SFSPF_5: MODE Mask              */
#define SCU_SFSPF_5_EPD_Pos                                   3                                                         /*!< SCU SFSPF_5: EPD Position           */
#define SCU_SFSPF_5_EPD_Msk                                   (0x01UL << SCU_SFSPF_5_EPD_Pos)                           /*!< SCU SFSPF_5: EPD Mask               */
#define SCU_SFSPF_5_EPUN_Pos                                  4                                                         /*!< SCU SFSPF_5: EPUN Position          */
#define SCU_SFSPF_5_EPUN_Msk                                  (0x01UL << SCU_SFSPF_5_EPUN_Pos)                          /*!< SCU SFSPF_5: EPUN Mask              */
#define SCU_SFSPF_5_EHS_Pos                                   5                                                         /*!< SCU SFSPF_5: EHS Position           */
#define SCU_SFSPF_5_EHS_Msk                                   (0x01UL << SCU_SFSPF_5_EHS_Pos)                           /*!< SCU SFSPF_5: EHS Mask               */
#define SCU_SFSPF_5_EZI_Pos                                   6                                                         /*!< SCU SFSPF_5: EZI Position           */
#define SCU_SFSPF_5_EZI_Msk                                   (0x01UL << SCU_SFSPF_5_EZI_Pos)                           /*!< SCU SFSPF_5: EZI Mask               */
#define SCU_SFSPF_5_EHD_Pos                                   8                                                         /*!< SCU SFSPF_5: EHD Position           */
#define SCU_SFSPF_5_EHD_Msk                                   (0x03UL << SCU_SFSPF_5_EHD_Pos)                           /*!< SCU SFSPF_5: EHD Mask               */

// ---------------------------------------  SCU_SFSPF_6  ------------------------------------------
#define SCU_SFSPF_6_MODE_Pos                                  0                                                         /*!< SCU SFSPF_6: MODE Position          */
#define SCU_SFSPF_6_MODE_Msk                                  (0x07UL << SCU_SFSPF_6_MODE_Pos)                          /*!< SCU SFSPF_6: MODE Mask              */
#define SCU_SFSPF_6_EPD_Pos                                   3                                                         /*!< SCU SFSPF_6: EPD Position           */
#define SCU_SFSPF_6_EPD_Msk                                   (0x01UL << SCU_SFSPF_6_EPD_Pos)                           /*!< SCU SFSPF_6: EPD Mask               */
#define SCU_SFSPF_6_EPUN_Pos                                  4                                                         /*!< SCU SFSPF_6: EPUN Position          */
#define SCU_SFSPF_6_EPUN_Msk                                  (0x01UL << SCU_SFSPF_6_EPUN_Pos)                          /*!< SCU SFSPF_6: EPUN Mask              */
#define SCU_SFSPF_6_EHS_Pos                                   5                                                         /*!< SCU SFSPF_6: EHS Position           */
#define SCU_SFSPF_6_EHS_Msk                                   (0x01UL << SCU_SFSPF_6_EHS_Pos)                           /*!< SCU SFSPF_6: EHS Mask               */
#define SCU_SFSPF_6_EZI_Pos                                   6                                                         /*!< SCU SFSPF_6: EZI Position           */
#define SCU_SFSPF_6_EZI_Msk                                   (0x01UL << SCU_SFSPF_6_EZI_Pos)                           /*!< SCU SFSPF_6: EZI Mask               */
#define SCU_SFSPF_6_EHD_Pos                                   8                                                         /*!< SCU SFSPF_6: EHD Position           */
#define SCU_SFSPF_6_EHD_Msk                                   (0x03UL << SCU_SFSPF_6_EHD_Pos)                           /*!< SCU SFSPF_6: EHD Mask               */

// ---------------------------------------  SCU_SFSPF_7  ------------------------------------------
#define SCU_SFSPF_7_MODE_Pos                                  0                                                         /*!< SCU SFSPF_7: MODE Position          */
#define SCU_SFSPF_7_MODE_Msk                                  (0x07UL << SCU_SFSPF_7_MODE_Pos)                          /*!< SCU SFSPF_7: MODE Mask              */
#define SCU_SFSPF_7_EPD_Pos                                   3                                                         /*!< SCU SFSPF_7: EPD Position           */
#define SCU_SFSPF_7_EPD_Msk                                   (0x01UL << SCU_SFSPF_7_EPD_Pos)                           /*!< SCU SFSPF_7: EPD Mask               */
#define SCU_SFSPF_7_EPUN_Pos                                  4                                                         /*!< SCU SFSPF_7: EPUN Position          */
#define SCU_SFSPF_7_EPUN_Msk                                  (0x01UL << SCU_SFSPF_7_EPUN_Pos)                          /*!< SCU SFSPF_7: EPUN Mask              */
#define SCU_SFSPF_7_EHS_Pos                                   5                                                         /*!< SCU SFSPF_7: EHS Position           */
#define SCU_SFSPF_7_EHS_Msk                                   (0x01UL << SCU_SFSPF_7_EHS_Pos)                           /*!< SCU SFSPF_7: EHS Mask               */
#define SCU_SFSPF_7_EZI_Pos                                   6                                                         /*!< SCU SFSPF_7: EZI Position           */
#define SCU_SFSPF_7_EZI_Msk                                   (0x01UL << SCU_SFSPF_7_EZI_Pos)                           /*!< SCU SFSPF_7: EZI Mask               */
#define SCU_SFSPF_7_EHD_Pos                                   8                                                         /*!< SCU SFSPF_7: EHD Position           */
#define SCU_SFSPF_7_EHD_Msk                                   (0x03UL << SCU_SFSPF_7_EHD_Pos)                           /*!< SCU SFSPF_7: EHD Mask               */

// ---------------------------------------  SCU_SFSPF_8  ------------------------------------------
#define SCU_SFSPF_8_MODE_Pos                                  0                                                         /*!< SCU SFSPF_8: MODE Position          */
#define SCU_SFSPF_8_MODE_Msk                                  (0x07UL << SCU_SFSPF_8_MODE_Pos)                          /*!< SCU SFSPF_8: MODE Mask              */
#define SCU_SFSPF_8_EPD_Pos                                   3                                                         /*!< SCU SFSPF_8: EPD Position           */
#define SCU_SFSPF_8_EPD_Msk                                   (0x01UL << SCU_SFSPF_8_EPD_Pos)                           /*!< SCU SFSPF_8: EPD Mask               */
#define SCU_SFSPF_8_EPUN_Pos                                  4                                                         /*!< SCU SFSPF_8: EPUN Position          */
#define SCU_SFSPF_8_EPUN_Msk                                  (0x01UL << SCU_SFSPF_8_EPUN_Pos)                          /*!< SCU SFSPF_8: EPUN Mask              */
#define SCU_SFSPF_8_EHS_Pos                                   5                                                         /*!< SCU SFSPF_8: EHS Position           */
#define SCU_SFSPF_8_EHS_Msk                                   (0x01UL << SCU_SFSPF_8_EHS_Pos)                           /*!< SCU SFSPF_8: EHS Mask               */
#define SCU_SFSPF_8_EZI_Pos                                   6                                                         /*!< SCU SFSPF_8: EZI Position           */
#define SCU_SFSPF_8_EZI_Msk                                   (0x01UL << SCU_SFSPF_8_EZI_Pos)                           /*!< SCU SFSPF_8: EZI Mask               */
#define SCU_SFSPF_8_EHD_Pos                                   8                                                         /*!< SCU SFSPF_8: EHD Position           */
#define SCU_SFSPF_8_EHD_Msk                                   (0x03UL << SCU_SFSPF_8_EHD_Pos)                           /*!< SCU SFSPF_8: EHD Mask               */

// ---------------------------------------  SCU_SFSPF_9  ------------------------------------------
#define SCU_SFSPF_9_MODE_Pos                                  0                                                         /*!< SCU SFSPF_9: MODE Position          */
#define SCU_SFSPF_9_MODE_Msk                                  (0x07UL << SCU_SFSPF_9_MODE_Pos)                          /*!< SCU SFSPF_9: MODE Mask              */
#define SCU_SFSPF_9_EPD_Pos                                   3                                                         /*!< SCU SFSPF_9: EPD Position           */
#define SCU_SFSPF_9_EPD_Msk                                   (0x01UL << SCU_SFSPF_9_EPD_Pos)                           /*!< SCU SFSPF_9: EPD Mask               */
#define SCU_SFSPF_9_EPUN_Pos                                  4                                                         /*!< SCU SFSPF_9: EPUN Position          */
#define SCU_SFSPF_9_EPUN_Msk                                  (0x01UL << SCU_SFSPF_9_EPUN_Pos)                          /*!< SCU SFSPF_9: EPUN Mask              */
#define SCU_SFSPF_9_EHS_Pos                                   5                                                         /*!< SCU SFSPF_9: EHS Position           */
#define SCU_SFSPF_9_EHS_Msk                                   (0x01UL << SCU_SFSPF_9_EHS_Pos)                           /*!< SCU SFSPF_9: EHS Mask               */
#define SCU_SFSPF_9_EZI_Pos                                   6                                                         /*!< SCU SFSPF_9: EZI Position           */
#define SCU_SFSPF_9_EZI_Msk                                   (0x01UL << SCU_SFSPF_9_EZI_Pos)                           /*!< SCU SFSPF_9: EZI Mask               */
#define SCU_SFSPF_9_EHD_Pos                                   8                                                         /*!< SCU SFSPF_9: EHD Position           */
#define SCU_SFSPF_9_EHD_Msk                                   (0x03UL << SCU_SFSPF_9_EHD_Pos)                           /*!< SCU SFSPF_9: EHD Mask               */

// --------------------------------------  SCU_SFSPF_10  ------------------------------------------
#define SCU_SFSPF_10_MODE_Pos                                 0                                                         /*!< SCU SFSPF_10: MODE Position         */
#define SCU_SFSPF_10_MODE_Msk                                 (0x07UL << SCU_SFSPF_10_MODE_Pos)                         /*!< SCU SFSPF_10: MODE Mask             */
#define SCU_SFSPF_10_EPD_Pos                                  3                                                         /*!< SCU SFSPF_10: EPD Position          */
#define SCU_SFSPF_10_EPD_Msk                                  (0x01UL << SCU_SFSPF_10_EPD_Pos)                          /*!< SCU SFSPF_10: EPD Mask              */
#define SCU_SFSPF_10_EPUN_Pos                                 4                                                         /*!< SCU SFSPF_10: EPUN Position         */
#define SCU_SFSPF_10_EPUN_Msk                                 (0x01UL << SCU_SFSPF_10_EPUN_Pos)                         /*!< SCU SFSPF_10: EPUN Mask             */
#define SCU_SFSPF_10_EHS_Pos                                  5                                                         /*!< SCU SFSPF_10: EHS Position          */
#define SCU_SFSPF_10_EHS_Msk                                  (0x01UL << SCU_SFSPF_10_EHS_Pos)                          /*!< SCU SFSPF_10: EHS Mask              */
#define SCU_SFSPF_10_EZI_Pos                                  6                                                         /*!< SCU SFSPF_10: EZI Position          */
#define SCU_SFSPF_10_EZI_Msk                                  (0x01UL << SCU_SFSPF_10_EZI_Pos)                          /*!< SCU SFSPF_10: EZI Mask              */
#define SCU_SFSPF_10_EHD_Pos                                  8                                                         /*!< SCU SFSPF_10: EHD Position          */
#define SCU_SFSPF_10_EHD_Msk                                  (0x03UL << SCU_SFSPF_10_EHD_Pos)                          /*!< SCU SFSPF_10: EHD Mask              */

// --------------------------------------  SCU_SFSPF_11  ------------------------------------------
#define SCU_SFSPF_11_MODE_Pos                                 0                                                         /*!< SCU SFSPF_11: MODE Position         */
#define SCU_SFSPF_11_MODE_Msk                                 (0x07UL << SCU_SFSPF_11_MODE_Pos)                         /*!< SCU SFSPF_11: MODE Mask             */
#define SCU_SFSPF_11_EPD_Pos                                  3                                                         /*!< SCU SFSPF_11: EPD Position          */
#define SCU_SFSPF_11_EPD_Msk                                  (0x01UL << SCU_SFSPF_11_EPD_Pos)                          /*!< SCU SFSPF_11: EPD Mask              */
#define SCU_SFSPF_11_EPUN_Pos                                 4                                                         /*!< SCU SFSPF_11: EPUN Position         */
#define SCU_SFSPF_11_EPUN_Msk                                 (0x01UL << SCU_SFSPF_11_EPUN_Pos)                         /*!< SCU SFSPF_11: EPUN Mask             */
#define SCU_SFSPF_11_EHS_Pos                                  5                                                         /*!< SCU SFSPF_11: EHS Position          */
#define SCU_SFSPF_11_EHS_Msk                                  (0x01UL << SCU_SFSPF_11_EHS_Pos)                          /*!< SCU SFSPF_11: EHS Mask              */
#define SCU_SFSPF_11_EZI_Pos                                  6                                                         /*!< SCU SFSPF_11: EZI Position          */
#define SCU_SFSPF_11_EZI_Msk                                  (0x01UL << SCU_SFSPF_11_EZI_Pos)                          /*!< SCU SFSPF_11: EZI Mask              */
#define SCU_SFSPF_11_EHD_Pos                                  8                                                         /*!< SCU SFSPF_11: EHD Position          */
#define SCU_SFSPF_11_EHD_Msk                                  (0x03UL << SCU_SFSPF_11_EHD_Pos)                          /*!< SCU SFSPF_11: EHD Mask              */

// --------------------------------------  SCU_SFSCLK_0  ------------------------------------------
#define SCU_SFSCLK_0_MODE_Pos                                 0                                                         /*!< SCU SFSCLK_0: MODE Position         */
#define SCU_SFSCLK_0_MODE_Msk                                 (0x07UL << SCU_SFSCLK_0_MODE_Pos)                         /*!< SCU SFSCLK_0: MODE Mask             */
#define SCU_SFSCLK_0_EPD_Pos                                  3                                                         /*!< SCU SFSCLK_0: EPD Position          */
#define SCU_SFSCLK_0_EPD_Msk                                  (0x01UL << SCU_SFSCLK_0_EPD_Pos)                          /*!< SCU SFSCLK_0: EPD Mask              */
#define SCU_SFSCLK_0_EPUN_Pos                                 4                                                         /*!< SCU SFSCLK_0: EPUN Position         */
#define SCU_SFSCLK_0_EPUN_Msk                                 (0x01UL << SCU_SFSCLK_0_EPUN_Pos)                         /*!< SCU SFSCLK_0: EPUN Mask             */
#define SCU_SFSCLK_0_EHS_Pos                                  5                                                         /*!< SCU SFSCLK_0: EHS Position          */
#define SCU_SFSCLK_0_EHS_Msk                                  (0x01UL << SCU_SFSCLK_0_EHS_Pos)                          /*!< SCU SFSCLK_0: EHS Mask              */
#define SCU_SFSCLK_0_EZI_Pos                                  6                                                         /*!< SCU SFSCLK_0: EZI Position          */
#define SCU_SFSCLK_0_EZI_Msk                                  (0x01UL << SCU_SFSCLK_0_EZI_Pos)                          /*!< SCU SFSCLK_0: EZI Mask              */
#define SCU_SFSCLK_0_EHD_Pos                                  8                                                         /*!< SCU SFSCLK_0: EHD Position          */
#define SCU_SFSCLK_0_EHD_Msk                                  (0x03UL << SCU_SFSCLK_0_EHD_Pos)                          /*!< SCU SFSCLK_0: EHD Mask              */

// --------------------------------------  SCU_SFSCLK_1  ------------------------------------------
#define SCU_SFSCLK_1_MODE_Pos                                 0                                                         /*!< SCU SFSCLK_1: MODE Position         */
#define SCU_SFSCLK_1_MODE_Msk                                 (0x07UL << SCU_SFSCLK_1_MODE_Pos)                         /*!< SCU SFSCLK_1: MODE Mask             */
#define SCU_SFSCLK_1_EPD_Pos                                  3                                                         /*!< SCU SFSCLK_1: EPD Position          */
#define SCU_SFSCLK_1_EPD_Msk                                  (0x01UL << SCU_SFSCLK_1_EPD_Pos)                          /*!< SCU SFSCLK_1: EPD Mask              */
#define SCU_SFSCLK_1_EPUN_Pos                                 4                                                         /*!< SCU SFSCLK_1: EPUN Position         */
#define SCU_SFSCLK_1_EPUN_Msk                                 (0x01UL << SCU_SFSCLK_1_EPUN_Pos)                         /*!< SCU SFSCLK_1: EPUN Mask             */
#define SCU_SFSCLK_1_EHS_Pos                                  5                                                         /*!< SCU SFSCLK_1: EHS Position          */
#define SCU_SFSCLK_1_EHS_Msk                                  (0x01UL << SCU_SFSCLK_1_EHS_Pos)                          /*!< SCU SFSCLK_1: EHS Mask              */
#define SCU_SFSCLK_1_EZI_Pos                                  6                                                         /*!< SCU SFSCLK_1: EZI Position          */
#define SCU_SFSCLK_1_EZI_Msk                                  (0x01UL << SCU_SFSCLK_1_EZI_Pos)                          /*!< SCU SFSCLK_1: EZI Mask              */
#define SCU_SFSCLK_1_EHD_Pos                                  8                                                         /*!< SCU SFSCLK_1: EHD Position          */
#define SCU_SFSCLK_1_EHD_Msk                                  (0x03UL << SCU_SFSCLK_1_EHD_Pos)                          /*!< SCU SFSCLK_1: EHD Mask              */

// --------------------------------------  SCU_SFSCLK_2  ------------------------------------------
#define SCU_SFSCLK_2_MODE_Pos                                 0                                                         /*!< SCU SFSCLK_2: MODE Position         */
#define SCU_SFSCLK_2_MODE_Msk                                 (0x07UL << SCU_SFSCLK_2_MODE_Pos)                         /*!< SCU SFSCLK_2: MODE Mask             */
#define SCU_SFSCLK_2_EPD_Pos                                  3                                                         /*!< SCU SFSCLK_2: EPD Position          */
#define SCU_SFSCLK_2_EPD_Msk                                  (0x01UL << SCU_SFSCLK_2_EPD_Pos)                          /*!< SCU SFSCLK_2: EPD Mask              */
#define SCU_SFSCLK_2_EPUN_Pos                                 4                                                         /*!< SCU SFSCLK_2: EPUN Position         */
#define SCU_SFSCLK_2_EPUN_Msk                                 (0x01UL << SCU_SFSCLK_2_EPUN_Pos)                         /*!< SCU SFSCLK_2: EPUN Mask             */
#define SCU_SFSCLK_2_EHS_Pos                                  5                                                         /*!< SCU SFSCLK_2: EHS Position          */
#define SCU_SFSCLK_2_EHS_Msk                                  (0x01UL << SCU_SFSCLK_2_EHS_Pos)                          /*!< SCU SFSCLK_2: EHS Mask              */
#define SCU_SFSCLK_2_EZI_Pos                                  6                                                         /*!< SCU SFSCLK_2: EZI Position          */
#define SCU_SFSCLK_2_EZI_Msk                                  (0x01UL << SCU_SFSCLK_2_EZI_Pos)                          /*!< SCU SFSCLK_2: EZI Mask              */
#define SCU_SFSCLK_2_EHD_Pos                                  8                                                         /*!< SCU SFSCLK_2: EHD Position          */
#define SCU_SFSCLK_2_EHD_Msk                                  (0x03UL << SCU_SFSCLK_2_EHD_Pos)                          /*!< SCU SFSCLK_2: EHD Mask              */

// --------------------------------------  SCU_SFSCLK_3  ------------------------------------------
#define SCU_SFSCLK_3_MODE_Pos                                 0                                                         /*!< SCU SFSCLK_3: MODE Position         */
#define SCU_SFSCLK_3_MODE_Msk                                 (0x07UL << SCU_SFSCLK_3_MODE_Pos)                         /*!< SCU SFSCLK_3: MODE Mask             */
#define SCU_SFSCLK_3_EPD_Pos                                  3                                                         /*!< SCU SFSCLK_3: EPD Position          */
#define SCU_SFSCLK_3_EPD_Msk                                  (0x01UL << SCU_SFSCLK_3_EPD_Pos)                          /*!< SCU SFSCLK_3: EPD Mask              */
#define SCU_SFSCLK_3_EPUN_Pos                                 4                                                         /*!< SCU SFSCLK_3: EPUN Position         */
#define SCU_SFSCLK_3_EPUN_Msk                                 (0x01UL << SCU_SFSCLK_3_EPUN_Pos)                         /*!< SCU SFSCLK_3: EPUN Mask             */
#define SCU_SFSCLK_3_EHS_Pos                                  5                                                         /*!< SCU SFSCLK_3: EHS Position          */
#define SCU_SFSCLK_3_EHS_Msk                                  (0x01UL << SCU_SFSCLK_3_EHS_Pos)                          /*!< SCU SFSCLK_3: EHS Mask              */
#define SCU_SFSCLK_3_EZI_Pos                                  6                                                         /*!< SCU SFSCLK_3: EZI Position          */
#define SCU_SFSCLK_3_EZI_Msk                                  (0x01UL << SCU_SFSCLK_3_EZI_Pos)                          /*!< SCU SFSCLK_3: EZI Mask              */
#define SCU_SFSCLK_3_EHD_Pos                                  8                                                         /*!< SCU SFSCLK_3: EHD Position          */
#define SCU_SFSCLK_3_EHD_Msk                                  (0x03UL << SCU_SFSCLK_3_EHD_Pos)                          /*!< SCU SFSCLK_3: EHD Mask              */

// ---------------------------------------  SCU_SFSUSB  -------------------------------------------
#define SCU_SFSUSB_USB_AIM_Pos                                0                                                         /*!< SCU SFSUSB: USB_AIM Position        */
#define SCU_SFSUSB_USB_AIM_Msk                                (0x01UL << SCU_SFSUSB_USB_AIM_Pos)                        /*!< SCU SFSUSB: USB_AIM Mask            */
#define SCU_SFSUSB_USB_ESEA_Pos                               1                                                         /*!< SCU SFSUSB: USB_ESEA Position       */
#define SCU_SFSUSB_USB_ESEA_Msk                               (0x01UL << SCU_SFSUSB_USB_ESEA_Pos)                       /*!< SCU SFSUSB: USB_ESEA Mask           */

// ---------------------------------------  SCU_SFSI2C0  ------------------------------------------
#define SCU_SFSI2C0_SDA_EHS_Pos                               0                                                         /*!< SCU SFSI2C0: SDA_EHS Position       */
#define SCU_SFSI2C0_SDA_EHS_Msk                               (0x01UL << SCU_SFSI2C0_SDA_EHS_Pos)                       /*!< SCU SFSI2C0: SDA_EHS Mask           */
#define SCU_SFSI2C0_SCL_EHS_Pos                               1                                                         /*!< SCU SFSI2C0: SCL_EHS Position       */
#define SCU_SFSI2C0_SCL_EHS_Msk                               (0x01UL << SCU_SFSI2C0_SCL_EHS_Pos)                       /*!< SCU SFSI2C0: SCL_EHS Mask           */
#define SCU_SFSI2C0_SCL_ECS_Pos                               2                                                         /*!< SCU SFSI2C0: SCL_ECS Position       */
#define SCU_SFSI2C0_SCL_ECS_Msk                               (0x01UL << SCU_SFSI2C0_SCL_ECS_Pos)                       /*!< SCU SFSI2C0: SCL_ECS Mask           */

// ---------------------------------------  SCU_ENAIO0  -------------------------------------------
#define SCU_ENAIO0_ADC0_0_Pos                                 0                                                         /*!< SCU ENAIO0: ADC0_0 Position         */
#define SCU_ENAIO0_ADC0_0_Msk                                 (0x01UL << SCU_ENAIO0_ADC0_0_Pos)                         /*!< SCU ENAIO0: ADC0_0 Mask             */
#define SCU_ENAIO0_ADC0_1_Pos                                 1                                                         /*!< SCU ENAIO0: ADC0_1 Position         */
#define SCU_ENAIO0_ADC0_1_Msk                                 (0x01UL << SCU_ENAIO0_ADC0_1_Pos)                         /*!< SCU ENAIO0: ADC0_1 Mask             */
#define SCU_ENAIO0_ADC0_2_Pos                                 2                                                         /*!< SCU ENAIO0: ADC0_2 Position         */
#define SCU_ENAIO0_ADC0_2_Msk                                 (0x01UL << SCU_ENAIO0_ADC0_2_Pos)                         /*!< SCU ENAIO0: ADC0_2 Mask             */
#define SCU_ENAIO0_ADC0_3_Pos                                 3                                                         /*!< SCU ENAIO0: ADC0_3 Position         */
#define SCU_ENAIO0_ADC0_3_Msk                                 (0x01UL << SCU_ENAIO0_ADC0_3_Pos)                         /*!< SCU ENAIO0: ADC0_3 Mask             */
#define SCU_ENAIO0_ADC0_4_Pos                                 4                                                         /*!< SCU ENAIO0: ADC0_4 Position         */
#define SCU_ENAIO0_ADC0_4_Msk                                 (0x01UL << SCU_ENAIO0_ADC0_4_Pos)                         /*!< SCU ENAIO0: ADC0_4 Mask             */
#define SCU_ENAIO0_ADC0_5_Pos                                 5                                                         /*!< SCU ENAIO0: ADC0_5 Position         */
#define SCU_ENAIO0_ADC0_5_Msk                                 (0x01UL << SCU_ENAIO0_ADC0_5_Pos)                         /*!< SCU ENAIO0: ADC0_5 Mask             */
#define SCU_ENAIO0_ADC0_6_Pos                                 6                                                         /*!< SCU ENAIO0: ADC0_6 Position         */
#define SCU_ENAIO0_ADC0_6_Msk                                 (0x01UL << SCU_ENAIO0_ADC0_6_Pos)                         /*!< SCU ENAIO0: ADC0_6 Mask             */

// ---------------------------------------  SCU_ENAIO1  -------------------------------------------
#define SCU_ENAIO1_ADC1_0_Pos                                 0                                                         /*!< SCU ENAIO1: ADC1_0 Position         */
#define SCU_ENAIO1_ADC1_0_Msk                                 (0x01UL << SCU_ENAIO1_ADC1_0_Pos)                         /*!< SCU ENAIO1: ADC1_0 Mask             */
#define SCU_ENAIO1_ADC1_1_Pos                                 1                                                         /*!< SCU ENAIO1: ADC1_1 Position         */
#define SCU_ENAIO1_ADC1_1_Msk                                 (0x01UL << SCU_ENAIO1_ADC1_1_Pos)                         /*!< SCU ENAIO1: ADC1_1 Mask             */
#define SCU_ENAIO1_ADC1_2_Pos                                 2                                                         /*!< SCU ENAIO1: ADC1_2 Position         */
#define SCU_ENAIO1_ADC1_2_Msk                                 (0x01UL << SCU_ENAIO1_ADC1_2_Pos)                         /*!< SCU ENAIO1: ADC1_2 Mask             */
#define SCU_ENAIO1_ADC1_3_Pos                                 3                                                         /*!< SCU ENAIO1: ADC1_3 Position         */
#define SCU_ENAIO1_ADC1_3_Msk                                 (0x01UL << SCU_ENAIO1_ADC1_3_Pos)                         /*!< SCU ENAIO1: ADC1_3 Mask             */
#define SCU_ENAIO1_ADC1_4_Pos                                 4                                                         /*!< SCU ENAIO1: ADC1_4 Position         */
#define SCU_ENAIO1_ADC1_4_Msk                                 (0x01UL << SCU_ENAIO1_ADC1_4_Pos)                         /*!< SCU ENAIO1: ADC1_4 Mask             */
#define SCU_ENAIO1_ADC1_5_Pos                                 5                                                         /*!< SCU ENAIO1: ADC1_5 Position         */
#define SCU_ENAIO1_ADC1_5_Msk                                 (0x01UL << SCU_ENAIO1_ADC1_5_Pos)                         /*!< SCU ENAIO1: ADC1_5 Mask             */
#define SCU_ENAIO1_ADC1_6_Pos                                 6                                                         /*!< SCU ENAIO1: ADC1_6 Position         */
#define SCU_ENAIO1_ADC1_6_Msk                                 (0x01UL << SCU_ENAIO1_ADC1_6_Pos)                         /*!< SCU ENAIO1: ADC1_6 Mask             */
#define SCU_ENAIO1_ADC1_7_Pos                                 7                                                         /*!< SCU ENAIO1: ADC1_7 Position         */
#define SCU_ENAIO1_ADC1_7_Msk                                 (0x01UL << SCU_ENAIO1_ADC1_7_Pos)                         /*!< SCU ENAIO1: ADC1_7 Mask             */

// ---------------------------------------  SCU_ENAIO2  -------------------------------------------
#define SCU_ENAIO2_DAC_Pos                                    0                                                         /*!< SCU ENAIO2: DAC Position            */
#define SCU_ENAIO2_DAC_Msk                                    (0x01UL << SCU_ENAIO2_DAC_Pos)                            /*!< SCU ENAIO2: DAC Mask                */
#define SCU_ENAIO2_BG_Pos                                     4                                                         /*!< SCU ENAIO2: BG Position             */
#define SCU_ENAIO2_BG_Msk                                     (0x01UL << SCU_ENAIO2_BG_Pos)                             /*!< SCU ENAIO2: BG Mask                 */

// -------------------------------------  SCU_EMCDELAYCLK  ----------------------------------------
#define SCU_EMCDELAYCLK_CLK0_DELAY_Pos                        0                                                         /*!< SCU EMCDELAYCLK: CLK0_DELAY Position */
#define SCU_EMCDELAYCLK_CLK0_DELAY_Msk                        (0x07UL << SCU_EMCDELAYCLK_CLK0_DELAY_Pos)                /*!< SCU EMCDELAYCLK: CLK0_DELAY Mask    */
#define SCU_EMCDELAYCLK_CLK1_DELAY_Pos                        4                                                         /*!< SCU EMCDELAYCLK: CLK1_DELAY Position */
#define SCU_EMCDELAYCLK_CLK1_DELAY_Msk                        (0x07UL << SCU_EMCDELAYCLK_CLK1_DELAY_Pos)                /*!< SCU EMCDELAYCLK: CLK1_DELAY Mask    */
#define SCU_EMCDELAYCLK_CLK2_DELAY_Pos                        8                                                         /*!< SCU EMCDELAYCLK: CLK2_DELAY Position */
#define SCU_EMCDELAYCLK_CLK2_DELAY_Msk                        (0x07UL << SCU_EMCDELAYCLK_CLK2_DELAY_Pos)                /*!< SCU EMCDELAYCLK: CLK2_DELAY Mask    */
#define SCU_EMCDELAYCLK_CLK3_DELAY_Pos                        12                                                        /*!< SCU EMCDELAYCLK: CLK3_DELAY Position */
#define SCU_EMCDELAYCLK_CLK3_DELAY_Msk                        (0x07UL << SCU_EMCDELAYCLK_CLK3_DELAY_Pos)                /*!< SCU EMCDELAYCLK: CLK3_DELAY Mask    */
#define SCU_EMCDELAYCLK_CKE0_DELAY_Pos                        16                                                        /*!< SCU EMCDELAYCLK: CKE0_DELAY Position */
#define SCU_EMCDELAYCLK_CKE0_DELAY_Msk                        (0x07UL << SCU_EMCDELAYCLK_CKE0_DELAY_Pos)                /*!< SCU EMCDELAYCLK: CKE0_DELAY Mask    */
#define SCU_EMCDELAYCLK_CKE1_DELAY_Pos                        20                                                        /*!< SCU EMCDELAYCLK: CKE1_DELAY Position */
#define SCU_EMCDELAYCLK_CKE1_DELAY_Msk                        (0x07UL << SCU_EMCDELAYCLK_CKE1_DELAY_Pos)                /*!< SCU EMCDELAYCLK: CKE1_DELAY Mask    */
#define SCU_EMCDELAYCLK_CKE2_DELAY_Pos                        24                                                        /*!< SCU EMCDELAYCLK: CKE2_DELAY Position */
#define SCU_EMCDELAYCLK_CKE2_DELAY_Msk                        (0x07UL << SCU_EMCDELAYCLK_CKE2_DELAY_Pos)                /*!< SCU EMCDELAYCLK: CKE2_DELAY Mask    */
#define SCU_EMCDELAYCLK_CKE3_DELAY_Pos                        28                                                        /*!< SCU EMCDELAYCLK: CKE3_DELAY Position */
#define SCU_EMCDELAYCLK_CKE3_DELAY_Msk                        (0x07UL << SCU_EMCDELAYCLK_CKE3_DELAY_Pos)                /*!< SCU EMCDELAYCLK: CKE3_DELAY Mask    */

// --------------------------------------  SCU_PINTSEL0  ------------------------------------------
#define SCU_PINTSEL0_INTPIN0_Pos                              0                                                         /*!< SCU PINTSEL0: INTPIN0 Position      */
#define SCU_PINTSEL0_INTPIN0_Msk                              (0x1fUL << SCU_PINTSEL0_INTPIN0_Pos)                      /*!< SCU PINTSEL0: INTPIN0 Mask          */
#define SCU_PINTSEL0_PORTSEL0_Pos                             5                                                         /*!< SCU PINTSEL0: PORTSEL0 Position     */
#define SCU_PINTSEL0_PORTSEL0_Msk                             (0x07UL << SCU_PINTSEL0_PORTSEL0_Pos)                     /*!< SCU PINTSEL0: PORTSEL0 Mask         */
#define SCU_PINTSEL0_INTPIN1_Pos                              8                                                         /*!< SCU PINTSEL0: INTPIN1 Position      */
#define SCU_PINTSEL0_INTPIN1_Msk                              (0x1fUL << SCU_PINTSEL0_INTPIN1_Pos)                      /*!< SCU PINTSEL0: INTPIN1 Mask          */
#define SCU_PINTSEL0_PORTSEL1_Pos                             13                                                        /*!< SCU PINTSEL0: PORTSEL1 Position     */
#define SCU_PINTSEL0_PORTSEL1_Msk                             (0x07UL << SCU_PINTSEL0_PORTSEL1_Pos)                     /*!< SCU PINTSEL0: PORTSEL1 Mask         */
#define SCU_PINTSEL0_INTPIN2_Pos                              16                                                        /*!< SCU PINTSEL0: INTPIN2 Position      */
#define SCU_PINTSEL0_INTPIN2_Msk                              (0x1fUL << SCU_PINTSEL0_INTPIN2_Pos)                      /*!< SCU PINTSEL0: INTPIN2 Mask          */
#define SCU_PINTSEL0_PORTSEL2_Pos                             21                                                        /*!< SCU PINTSEL0: PORTSEL2 Position     */
#define SCU_PINTSEL0_PORTSEL2_Msk                             (0x07UL << SCU_PINTSEL0_PORTSEL2_Pos)                     /*!< SCU PINTSEL0: PORTSEL2 Mask         */
#define SCU_PINTSEL0_INTPIN3_Pos                              24                                                        /*!< SCU PINTSEL0: INTPIN3 Position      */
#define SCU_PINTSEL0_INTPIN3_Msk                              (0x1fUL << SCU_PINTSEL0_INTPIN3_Pos)                      /*!< SCU PINTSEL0: INTPIN3 Mask          */
#define SCU_PINTSEL0_PORTSEL3_Pos                             29                                                        /*!< SCU PINTSEL0: PORTSEL3 Position     */
#define SCU_PINTSEL0_PORTSEL3_Msk                             (0x07UL << SCU_PINTSEL0_PORTSEL3_Pos)                     /*!< SCU PINTSEL0: PORTSEL3 Mask         */

// --------------------------------------  SCU_PINTSEL1  ------------------------------------------
#define SCU_PINTSEL1_INTPIN4_Pos                              0                                                         /*!< SCU PINTSEL1: INTPIN4 Position      */
#define SCU_PINTSEL1_INTPIN4_Msk                              (0x1fUL << SCU_PINTSEL1_INTPIN4_Pos)                      /*!< SCU PINTSEL1: INTPIN4 Mask          */
#define SCU_PINTSEL1_PORTSEL4_Pos                             5                                                         /*!< SCU PINTSEL1: PORTSEL4 Position     */
#define SCU_PINTSEL1_PORTSEL4_Msk                             (0x07UL << SCU_PINTSEL1_PORTSEL4_Pos)                     /*!< SCU PINTSEL1: PORTSEL4 Mask         */
#define SCU_PINTSEL1_INTPIN5_Pos                              8                                                         /*!< SCU PINTSEL1: INTPIN5 Position      */
#define SCU_PINTSEL1_INTPIN5_Msk                              (0x1fUL << SCU_PINTSEL1_INTPIN5_Pos)                      /*!< SCU PINTSEL1: INTPIN5 Mask          */
#define SCU_PINTSEL1_PORTSEL5_Pos                             13                                                        /*!< SCU PINTSEL1: PORTSEL5 Position     */
#define SCU_PINTSEL1_PORTSEL5_Msk                             (0x07UL << SCU_PINTSEL1_PORTSEL5_Pos)                     /*!< SCU PINTSEL1: PORTSEL5 Mask         */
#define SCU_PINTSEL1_INTPIN6_Pos                              16                                                        /*!< SCU PINTSEL1: INTPIN6 Position      */
#define SCU_PINTSEL1_INTPIN6_Msk                              (0x1fUL << SCU_PINTSEL1_INTPIN6_Pos)                      /*!< SCU PINTSEL1: INTPIN6 Mask          */
#define SCU_PINTSEL1_PORTSEL6_Pos                             21                                                        /*!< SCU PINTSEL1: PORTSEL6 Position     */
#define SCU_PINTSEL1_PORTSEL6_Msk                             (0x07UL << SCU_PINTSEL1_PORTSEL6_Pos)                     /*!< SCU PINTSEL1: PORTSEL6 Mask         */
#define SCU_PINTSEL1_INTPIN7_Pos                              24                                                        /*!< SCU PINTSEL1: INTPIN7 Position      */
#define SCU_PINTSEL1_INTPIN7_Msk                              (0x1fUL << SCU_PINTSEL1_INTPIN7_Pos)                      /*!< SCU PINTSEL1: INTPIN7 Mask          */
#define SCU_PINTSEL1_PORTSEL7_Pos                             29                                                        /*!< SCU PINTSEL1: PORTSEL7 Position     */
#define SCU_PINTSEL1_PORTSEL7_Msk                             (0x07UL << SCU_PINTSEL1_PORTSEL7_Pos)                     /*!< SCU PINTSEL1: PORTSEL7 Mask         */


// ------------------------------------------------------------------------------------------------
// -----                             GPIO_PIN_INT Position & Mask                             -----
// ------------------------------------------------------------------------------------------------


// ------------------------------------  GPIO_PIN_INT_ISEL  ---------------------------------------
#define GPIO_PIN_INT_ISEL_PMODE0_Pos                          0                                                         /*!< GPIO_PIN_INT ISEL: PMODE0 Position  */
#define GPIO_PIN_INT_ISEL_PMODE0_Msk                          (0x01UL << GPIO_PIN_INT_ISEL_PMODE0_Pos)                  /*!< GPIO_PIN_INT ISEL: PMODE0 Mask      */
#define GPIO_PIN_INT_ISEL_PMODE1_Pos                          1                                                         /*!< GPIO_PIN_INT ISEL: PMODE1 Position  */
#define GPIO_PIN_INT_ISEL_PMODE1_Msk                          (0x01UL << GPIO_PIN_INT_ISEL_PMODE1_Pos)                  /*!< GPIO_PIN_INT ISEL: PMODE1 Mask      */
#define GPIO_PIN_INT_ISEL_PMODE2_Pos                          2                                                         /*!< GPIO_PIN_INT ISEL: PMODE2 Position  */
#define GPIO_PIN_INT_ISEL_PMODE2_Msk                          (0x01UL << GPIO_PIN_INT_ISEL_PMODE2_Pos)                  /*!< GPIO_PIN_INT ISEL: PMODE2 Mask      */
#define GPIO_PIN_INT_ISEL_PMODE3_Pos                          3                                                         /*!< GPIO_PIN_INT ISEL: PMODE3 Position  */
#define GPIO_PIN_INT_ISEL_PMODE3_Msk                          (0x01UL << GPIO_PIN_INT_ISEL_PMODE3_Pos)                  /*!< GPIO_PIN_INT ISEL: PMODE3 Mask      */
#define GPIO_PIN_INT_ISEL_PMODE4_Pos                          4                                                         /*!< GPIO_PIN_INT ISEL: PMODE4 Position  */
#define GPIO_PIN_INT_ISEL_PMODE4_Msk                          (0x01UL << GPIO_PIN_INT_ISEL_PMODE4_Pos)                  /*!< GPIO_PIN_INT ISEL: PMODE4 Mask      */
#define GPIO_PIN_INT_ISEL_PMODE5_Pos                          5                                                         /*!< GPIO_PIN_INT ISEL: PMODE5 Position  */
#define GPIO_PIN_INT_ISEL_PMODE5_Msk                          (0x01UL << GPIO_PIN_INT_ISEL_PMODE5_Pos)                  /*!< GPIO_PIN_INT ISEL: PMODE5 Mask      */
#define GPIO_PIN_INT_ISEL_PMODE6_Pos                          6                                                         /*!< GPIO_PIN_INT ISEL: PMODE6 Position  */
#define GPIO_PIN_INT_ISEL_PMODE6_Msk                          (0x01UL << GPIO_PIN_INT_ISEL_PMODE6_Pos)                  /*!< GPIO_PIN_INT ISEL: PMODE6 Mask      */
#define GPIO_PIN_INT_ISEL_PMODE7_Pos                          7                                                         /*!< GPIO_PIN_INT ISEL: PMODE7 Position  */
#define GPIO_PIN_INT_ISEL_PMODE7_Msk                          (0x01UL << GPIO_PIN_INT_ISEL_PMODE7_Pos)                  /*!< GPIO_PIN_INT ISEL: PMODE7 Mask      */

// ------------------------------------  GPIO_PIN_INT_IENR  ---------------------------------------
#define GPIO_PIN_INT_IENR_ENRL0_Pos                           0                                                         /*!< GPIO_PIN_INT IENR: ENRL0 Position   */
#define GPIO_PIN_INT_IENR_ENRL0_Msk                           (0x01UL << GPIO_PIN_INT_IENR_ENRL0_Pos)                   /*!< GPIO_PIN_INT IENR: ENRL0 Mask       */
#define GPIO_PIN_INT_IENR_ENRL1_Pos                           1                                                         /*!< GPIO_PIN_INT IENR: ENRL1 Position   */
#define GPIO_PIN_INT_IENR_ENRL1_Msk                           (0x01UL << GPIO_PIN_INT_IENR_ENRL1_Pos)                   /*!< GPIO_PIN_INT IENR: ENRL1 Mask       */
#define GPIO_PIN_INT_IENR_ENRL2_Pos                           2                                                         /*!< GPIO_PIN_INT IENR: ENRL2 Position   */
#define GPIO_PIN_INT_IENR_ENRL2_Msk                           (0x01UL << GPIO_PIN_INT_IENR_ENRL2_Pos)                   /*!< GPIO_PIN_INT IENR: ENRL2 Mask       */
#define GPIO_PIN_INT_IENR_ENRL3_Pos                           3                                                         /*!< GPIO_PIN_INT IENR: ENRL3 Position   */
#define GPIO_PIN_INT_IENR_ENRL3_Msk                           (0x01UL << GPIO_PIN_INT_IENR_ENRL3_Pos)                   /*!< GPIO_PIN_INT IENR: ENRL3 Mask       */
#define GPIO_PIN_INT_IENR_ENRL4_Pos                           4                                                         /*!< GPIO_PIN_INT IENR: ENRL4 Position   */
#define GPIO_PIN_INT_IENR_ENRL4_Msk                           (0x01UL << GPIO_PIN_INT_IENR_ENRL4_Pos)                   /*!< GPIO_PIN_INT IENR: ENRL4 Mask       */
#define GPIO_PIN_INT_IENR_ENRL5_Pos                           5                                                         /*!< GPIO_PIN_INT IENR: ENRL5 Position   */
#define GPIO_PIN_INT_IENR_ENRL5_Msk                           (0x01UL << GPIO_PIN_INT_IENR_ENRL5_Pos)                   /*!< GPIO_PIN_INT IENR: ENRL5 Mask       */
#define GPIO_PIN_INT_IENR_ENRL6_Pos                           6                                                         /*!< GPIO_PIN_INT IENR: ENRL6 Position   */
#define GPIO_PIN_INT_IENR_ENRL6_Msk                           (0x01UL << GPIO_PIN_INT_IENR_ENRL6_Pos)                   /*!< GPIO_PIN_INT IENR: ENRL6 Mask       */
#define GPIO_PIN_INT_IENR_ENRL7_Pos                           7                                                         /*!< GPIO_PIN_INT IENR: ENRL7 Position   */
#define GPIO_PIN_INT_IENR_ENRL7_Msk                           (0x01UL << GPIO_PIN_INT_IENR_ENRL7_Pos)                   /*!< GPIO_PIN_INT IENR: ENRL7 Mask       */

// -----------------------------------  GPIO_PIN_INT_SIENR  ---------------------------------------
#define GPIO_PIN_INT_SIENR_SETENRL0_Pos                       0                                                         /*!< GPIO_PIN_INT SIENR: SETENRL0 Position */
#define GPIO_PIN_INT_SIENR_SETENRL0_Msk                       (0x01UL << GPIO_PIN_INT_SIENR_SETENRL0_Pos)               /*!< GPIO_PIN_INT SIENR: SETENRL0 Mask   */
#define GPIO_PIN_INT_SIENR_SETENRL1_Pos                       1                                                         /*!< GPIO_PIN_INT SIENR: SETENRL1 Position */
#define GPIO_PIN_INT_SIENR_SETENRL1_Msk                       (0x01UL << GPIO_PIN_INT_SIENR_SETENRL1_Pos)               /*!< GPIO_PIN_INT SIENR: SETENRL1 Mask   */
#define GPIO_PIN_INT_SIENR_SETENRL2_Pos                       2                                                         /*!< GPIO_PIN_INT SIENR: SETENRL2 Position */
#define GPIO_PIN_INT_SIENR_SETENRL2_Msk                       (0x01UL << GPIO_PIN_INT_SIENR_SETENRL2_Pos)               /*!< GPIO_PIN_INT SIENR: SETENRL2 Mask   */
#define GPIO_PIN_INT_SIENR_SETENRL3_Pos                       3                                                         /*!< GPIO_PIN_INT SIENR: SETENRL3 Position */
#define GPIO_PIN_INT_SIENR_SETENRL3_Msk                       (0x01UL << GPIO_PIN_INT_SIENR_SETENRL3_Pos)               /*!< GPIO_PIN_INT SIENR: SETENRL3 Mask   */
#define GPIO_PIN_INT_SIENR_SETENRL4_Pos                       4                                                         /*!< GPIO_PIN_INT SIENR: SETENRL4 Position */
#define GPIO_PIN_INT_SIENR_SETENRL4_Msk                       (0x01UL << GPIO_PIN_INT_SIENR_SETENRL4_Pos)               /*!< GPIO_PIN_INT SIENR: SETENRL4 Mask   */
#define GPIO_PIN_INT_SIENR_SETENRL5_Pos                       5                                                         /*!< GPIO_PIN_INT SIENR: SETENRL5 Position */
#define GPIO_PIN_INT_SIENR_SETENRL5_Msk                       (0x01UL << GPIO_PIN_INT_SIENR_SETENRL5_Pos)               /*!< GPIO_PIN_INT SIENR: SETENRL5 Mask   */
#define GPIO_PIN_INT_SIENR_SETENRL6_Pos                       6                                                         /*!< GPIO_PIN_INT SIENR: SETENRL6 Position */
#define GPIO_PIN_INT_SIENR_SETENRL6_Msk                       (0x01UL << GPIO_PIN_INT_SIENR_SETENRL6_Pos)               /*!< GPIO_PIN_INT SIENR: SETENRL6 Mask   */
#define GPIO_PIN_INT_SIENR_SETENRL7_Pos                       7                                                         /*!< GPIO_PIN_INT SIENR: SETENRL7 Position */
#define GPIO_PIN_INT_SIENR_SETENRL7_Msk                       (0x01UL << GPIO_PIN_INT_SIENR_SETENRL7_Pos)               /*!< GPIO_PIN_INT SIENR: SETENRL7 Mask   */

// -----------------------------------  GPIO_PIN_INT_CIENR  ---------------------------------------
#define GPIO_PIN_INT_CIENR_CENRL0_Pos                         0                                                         /*!< GPIO_PIN_INT CIENR: CENRL0 Position */
#define GPIO_PIN_INT_CIENR_CENRL0_Msk                         (0x01UL << GPIO_PIN_INT_CIENR_CENRL0_Pos)                 /*!< GPIO_PIN_INT CIENR: CENRL0 Mask     */
#define GPIO_PIN_INT_CIENR_CENRL1_Pos                         1                                                         /*!< GPIO_PIN_INT CIENR: CENRL1 Position */
#define GPIO_PIN_INT_CIENR_CENRL1_Msk                         (0x01UL << GPIO_PIN_INT_CIENR_CENRL1_Pos)                 /*!< GPIO_PIN_INT CIENR: CENRL1 Mask     */
#define GPIO_PIN_INT_CIENR_CENRL2_Pos                         2                                                         /*!< GPIO_PIN_INT CIENR: CENRL2 Position */
#define GPIO_PIN_INT_CIENR_CENRL2_Msk                         (0x01UL << GPIO_PIN_INT_CIENR_CENRL2_Pos)                 /*!< GPIO_PIN_INT CIENR: CENRL2 Mask     */
#define GPIO_PIN_INT_CIENR_CENRL3_Pos                         3                                                         /*!< GPIO_PIN_INT CIENR: CENRL3 Position */
#define GPIO_PIN_INT_CIENR_CENRL3_Msk                         (0x01UL << GPIO_PIN_INT_CIENR_CENRL3_Pos)                 /*!< GPIO_PIN_INT CIENR: CENRL3 Mask     */
#define GPIO_PIN_INT_CIENR_CENRL4_Pos                         4                                                         /*!< GPIO_PIN_INT CIENR: CENRL4 Position */
#define GPIO_PIN_INT_CIENR_CENRL4_Msk                         (0x01UL << GPIO_PIN_INT_CIENR_CENRL4_Pos)                 /*!< GPIO_PIN_INT CIENR: CENRL4 Mask     */
#define GPIO_PIN_INT_CIENR_CENRL5_Pos                         5                                                         /*!< GPIO_PIN_INT CIENR: CENRL5 Position */
#define GPIO_PIN_INT_CIENR_CENRL5_Msk                         (0x01UL << GPIO_PIN_INT_CIENR_CENRL5_Pos)                 /*!< GPIO_PIN_INT CIENR: CENRL5 Mask     */
#define GPIO_PIN_INT_CIENR_CENRL6_Pos                         6                                                         /*!< GPIO_PIN_INT CIENR: CENRL6 Position */
#define GPIO_PIN_INT_CIENR_CENRL6_Msk                         (0x01UL << GPIO_PIN_INT_CIENR_CENRL6_Pos)                 /*!< GPIO_PIN_INT CIENR: CENRL6 Mask     */
#define GPIO_PIN_INT_CIENR_CENRL7_Pos                         7                                                         /*!< GPIO_PIN_INT CIENR: CENRL7 Position */
#define GPIO_PIN_INT_CIENR_CENRL7_Msk                         (0x01UL << GPIO_PIN_INT_CIENR_CENRL7_Pos)                 /*!< GPIO_PIN_INT CIENR: CENRL7 Mask     */

// ------------------------------------  GPIO_PIN_INT_IENF  ---------------------------------------
#define GPIO_PIN_INT_IENF_ENAF0_Pos                           0                                                         /*!< GPIO_PIN_INT IENF: ENAF0 Position   */
#define GPIO_PIN_INT_IENF_ENAF0_Msk                           (0x01UL << GPIO_PIN_INT_IENF_ENAF0_Pos)                   /*!< GPIO_PIN_INT IENF: ENAF0 Mask       */
#define GPIO_PIN_INT_IENF_ENAF1_Pos                           1                                                         /*!< GPIO_PIN_INT IENF: ENAF1 Position   */
#define GPIO_PIN_INT_IENF_ENAF1_Msk                           (0x01UL << GPIO_PIN_INT_IENF_ENAF1_Pos)                   /*!< GPIO_PIN_INT IENF: ENAF1 Mask       */
#define GPIO_PIN_INT_IENF_ENAF2_Pos                           2                                                         /*!< GPIO_PIN_INT IENF: ENAF2 Position   */
#define GPIO_PIN_INT_IENF_ENAF2_Msk                           (0x01UL << GPIO_PIN_INT_IENF_ENAF2_Pos)                   /*!< GPIO_PIN_INT IENF: ENAF2 Mask       */
#define GPIO_PIN_INT_IENF_ENAF3_Pos                           3                                                         /*!< GPIO_PIN_INT IENF: ENAF3 Position   */
#define GPIO_PIN_INT_IENF_ENAF3_Msk                           (0x01UL << GPIO_PIN_INT_IENF_ENAF3_Pos)                   /*!< GPIO_PIN_INT IENF: ENAF3 Mask       */
#define GPIO_PIN_INT_IENF_ENAF4_Pos                           4                                                         /*!< GPIO_PIN_INT IENF: ENAF4 Position   */
#define GPIO_PIN_INT_IENF_ENAF4_Msk                           (0x01UL << GPIO_PIN_INT_IENF_ENAF4_Pos)                   /*!< GPIO_PIN_INT IENF: ENAF4 Mask       */
#define GPIO_PIN_INT_IENF_ENAF5_Pos                           5                                                         /*!< GPIO_PIN_INT IENF: ENAF5 Position   */
#define GPIO_PIN_INT_IENF_ENAF5_Msk                           (0x01UL << GPIO_PIN_INT_IENF_ENAF5_Pos)                   /*!< GPIO_PIN_INT IENF: ENAF5 Mask       */
#define GPIO_PIN_INT_IENF_ENAF6_Pos                           6                                                         /*!< GPIO_PIN_INT IENF: ENAF6 Position   */
#define GPIO_PIN_INT_IENF_ENAF6_Msk                           (0x01UL << GPIO_PIN_INT_IENF_ENAF6_Pos)                   /*!< GPIO_PIN_INT IENF: ENAF6 Mask       */
#define GPIO_PIN_INT_IENF_ENAF7_Pos                           7                                                         /*!< GPIO_PIN_INT IENF: ENAF7 Position   */
#define GPIO_PIN_INT_IENF_ENAF7_Msk                           (0x01UL << GPIO_PIN_INT_IENF_ENAF7_Pos)                   /*!< GPIO_PIN_INT IENF: ENAF7 Mask       */

// -----------------------------------  GPIO_PIN_INT_SIENF  ---------------------------------------
#define GPIO_PIN_INT_SIENF_SETENAF0_Pos                       0                                                         /*!< GPIO_PIN_INT SIENF: SETENAF0 Position */
#define GPIO_PIN_INT_SIENF_SETENAF0_Msk                       (0x01UL << GPIO_PIN_INT_SIENF_SETENAF0_Pos)               /*!< GPIO_PIN_INT SIENF: SETENAF0 Mask   */
#define GPIO_PIN_INT_SIENF_SETENAF1_Pos                       1                                                         /*!< GPIO_PIN_INT SIENF: SETENAF1 Position */
#define GPIO_PIN_INT_SIENF_SETENAF1_Msk                       (0x01UL << GPIO_PIN_INT_SIENF_SETENAF1_Pos)               /*!< GPIO_PIN_INT SIENF: SETENAF1 Mask   */
#define GPIO_PIN_INT_SIENF_SETENAF2_Pos                       2                                                         /*!< GPIO_PIN_INT SIENF: SETENAF2 Position */
#define GPIO_PIN_INT_SIENF_SETENAF2_Msk                       (0x01UL << GPIO_PIN_INT_SIENF_SETENAF2_Pos)               /*!< GPIO_PIN_INT SIENF: SETENAF2 Mask   */
#define GPIO_PIN_INT_SIENF_SETENAF3_Pos                       3                                                         /*!< GPIO_PIN_INT SIENF: SETENAF3 Position */
#define GPIO_PIN_INT_SIENF_SETENAF3_Msk                       (0x01UL << GPIO_PIN_INT_SIENF_SETENAF3_Pos)               /*!< GPIO_PIN_INT SIENF: SETENAF3 Mask   */
#define GPIO_PIN_INT_SIENF_SETENAF4_Pos                       4                                                         /*!< GPIO_PIN_INT SIENF: SETENAF4 Position */
#define GPIO_PIN_INT_SIENF_SETENAF4_Msk                       (0x01UL << GPIO_PIN_INT_SIENF_SETENAF4_Pos)               /*!< GPIO_PIN_INT SIENF: SETENAF4 Mask   */
#define GPIO_PIN_INT_SIENF_SETENAF5_Pos                       5                                                         /*!< GPIO_PIN_INT SIENF: SETENAF5 Position */
#define GPIO_PIN_INT_SIENF_SETENAF5_Msk                       (0x01UL << GPIO_PIN_INT_SIENF_SETENAF5_Pos)               /*!< GPIO_PIN_INT SIENF: SETENAF5 Mask   */
#define GPIO_PIN_INT_SIENF_SETENAF6_Pos                       6                                                         /*!< GPIO_PIN_INT SIENF: SETENAF6 Position */
#define GPIO_PIN_INT_SIENF_SETENAF6_Msk                       (0x01UL << GPIO_PIN_INT_SIENF_SETENAF6_Pos)               /*!< GPIO_PIN_INT SIENF: SETENAF6 Mask   */
#define GPIO_PIN_INT_SIENF_SETENAF7_Pos                       7                                                         /*!< GPIO_PIN_INT SIENF: SETENAF7 Position */
#define GPIO_PIN_INT_SIENF_SETENAF7_Msk                       (0x01UL << GPIO_PIN_INT_SIENF_SETENAF7_Pos)               /*!< GPIO_PIN_INT SIENF: SETENAF7 Mask   */

// -----------------------------------  GPIO_PIN_INT_CIENF  ---------------------------------------
#define GPIO_PIN_INT_CIENF_CENAF0_Pos                         0                                                         /*!< GPIO_PIN_INT CIENF: CENAF0 Position */
#define GPIO_PIN_INT_CIENF_CENAF0_Msk                         (0x01UL << GPIO_PIN_INT_CIENF_CENAF0_Pos)                 /*!< GPIO_PIN_INT CIENF: CENAF0 Mask     */
#define GPIO_PIN_INT_CIENF_CENAF1_Pos                         1                                                         /*!< GPIO_PIN_INT CIENF: CENAF1 Position */
#define GPIO_PIN_INT_CIENF_CENAF1_Msk                         (0x01UL << GPIO_PIN_INT_CIENF_CENAF1_Pos)                 /*!< GPIO_PIN_INT CIENF: CENAF1 Mask     */
#define GPIO_PIN_INT_CIENF_CENAF2_Pos                         2                                                         /*!< GPIO_PIN_INT CIENF: CENAF2 Position */
#define GPIO_PIN_INT_CIENF_CENAF2_Msk                         (0x01UL << GPIO_PIN_INT_CIENF_CENAF2_Pos)                 /*!< GPIO_PIN_INT CIENF: CENAF2 Mask     */
#define GPIO_PIN_INT_CIENF_CENAF3_Pos                         3                                                         /*!< GPIO_PIN_INT CIENF: CENAF3 Position */
#define GPIO_PIN_INT_CIENF_CENAF3_Msk                         (0x01UL << GPIO_PIN_INT_CIENF_CENAF3_Pos)                 /*!< GPIO_PIN_INT CIENF: CENAF3 Mask     */
#define GPIO_PIN_INT_CIENF_CENAF4_Pos                         4                                                         /*!< GPIO_PIN_INT CIENF: CENAF4 Position */
#define GPIO_PIN_INT_CIENF_CENAF4_Msk                         (0x01UL << GPIO_PIN_INT_CIENF_CENAF4_Pos)                 /*!< GPIO_PIN_INT CIENF: CENAF4 Mask     */
#define GPIO_PIN_INT_CIENF_CENAF5_Pos                         5                                                         /*!< GPIO_PIN_INT CIENF: CENAF5 Position */
#define GPIO_PIN_INT_CIENF_CENAF5_Msk                         (0x01UL << GPIO_PIN_INT_CIENF_CENAF5_Pos)                 /*!< GPIO_PIN_INT CIENF: CENAF5 Mask     */
#define GPIO_PIN_INT_CIENF_CENAF6_Pos                         6                                                         /*!< GPIO_PIN_INT CIENF: CENAF6 Position */
#define GPIO_PIN_INT_CIENF_CENAF6_Msk                         (0x01UL << GPIO_PIN_INT_CIENF_CENAF6_Pos)                 /*!< GPIO_PIN_INT CIENF: CENAF6 Mask     */
#define GPIO_PIN_INT_CIENF_CENAF7_Pos                         7                                                         /*!< GPIO_PIN_INT CIENF: CENAF7 Position */
#define GPIO_PIN_INT_CIENF_CENAF7_Msk                         (0x01UL << GPIO_PIN_INT_CIENF_CENAF7_Pos)                 /*!< GPIO_PIN_INT CIENF: CENAF7 Mask     */

// ------------------------------------  GPIO_PIN_INT_RISE  ---------------------------------------
#define GPIO_PIN_INT_RISE_RDET0_Pos                           0                                                         /*!< GPIO_PIN_INT RISE: RDET0 Position   */
#define GPIO_PIN_INT_RISE_RDET0_Msk                           (0x01UL << GPIO_PIN_INT_RISE_RDET0_Pos)                   /*!< GPIO_PIN_INT RISE: RDET0 Mask       */
#define GPIO_PIN_INT_RISE_RDET1_Pos                           1                                                         /*!< GPIO_PIN_INT RISE: RDET1 Position   */
#define GPIO_PIN_INT_RISE_RDET1_Msk                           (0x01UL << GPIO_PIN_INT_RISE_RDET1_Pos)                   /*!< GPIO_PIN_INT RISE: RDET1 Mask       */
#define GPIO_PIN_INT_RISE_RDET2_Pos                           2                                                         /*!< GPIO_PIN_INT RISE: RDET2 Position   */
#define GPIO_PIN_INT_RISE_RDET2_Msk                           (0x01UL << GPIO_PIN_INT_RISE_RDET2_Pos)                   /*!< GPIO_PIN_INT RISE: RDET2 Mask       */
#define GPIO_PIN_INT_RISE_RDET3_Pos                           3                                                         /*!< GPIO_PIN_INT RISE: RDET3 Position   */
#define GPIO_PIN_INT_RISE_RDET3_Msk                           (0x01UL << GPIO_PIN_INT_RISE_RDET3_Pos)                   /*!< GPIO_PIN_INT RISE: RDET3 Mask       */
#define GPIO_PIN_INT_RISE_RDET4_Pos                           4                                                         /*!< GPIO_PIN_INT RISE: RDET4 Position   */
#define GPIO_PIN_INT_RISE_RDET4_Msk                           (0x01UL << GPIO_PIN_INT_RISE_RDET4_Pos)                   /*!< GPIO_PIN_INT RISE: RDET4 Mask       */
#define GPIO_PIN_INT_RISE_RDET5_Pos                           5                                                         /*!< GPIO_PIN_INT RISE: RDET5 Position   */
#define GPIO_PIN_INT_RISE_RDET5_Msk                           (0x01UL << GPIO_PIN_INT_RISE_RDET5_Pos)                   /*!< GPIO_PIN_INT RISE: RDET5 Mask       */
#define GPIO_PIN_INT_RISE_RDET6_Pos                           6                                                         /*!< GPIO_PIN_INT RISE: RDET6 Position   */
#define GPIO_PIN_INT_RISE_RDET6_Msk                           (0x01UL << GPIO_PIN_INT_RISE_RDET6_Pos)                   /*!< GPIO_PIN_INT RISE: RDET6 Mask       */
#define GPIO_PIN_INT_RISE_RDET7_Pos                           7                                                         /*!< GPIO_PIN_INT RISE: RDET7 Position   */
#define GPIO_PIN_INT_RISE_RDET7_Msk                           (0x01UL << GPIO_PIN_INT_RISE_RDET7_Pos)                   /*!< GPIO_PIN_INT RISE: RDET7 Mask       */

// ------------------------------------  GPIO_PIN_INT_FALL  ---------------------------------------
#define GPIO_PIN_INT_FALL_FDET0_Pos                           0                                                         /*!< GPIO_PIN_INT FALL: FDET0 Position   */
#define GPIO_PIN_INT_FALL_FDET0_Msk                           (0x01UL << GPIO_PIN_INT_FALL_FDET0_Pos)                   /*!< GPIO_PIN_INT FALL: FDET0 Mask       */
#define GPIO_PIN_INT_FALL_FDET1_Pos                           1                                                         /*!< GPIO_PIN_INT FALL: FDET1 Position   */
#define GPIO_PIN_INT_FALL_FDET1_Msk                           (0x01UL << GPIO_PIN_INT_FALL_FDET1_Pos)                   /*!< GPIO_PIN_INT FALL: FDET1 Mask       */
#define GPIO_PIN_INT_FALL_FDET2_Pos                           2                                                         /*!< GPIO_PIN_INT FALL: FDET2 Position   */
#define GPIO_PIN_INT_FALL_FDET2_Msk                           (0x01UL << GPIO_PIN_INT_FALL_FDET2_Pos)                   /*!< GPIO_PIN_INT FALL: FDET2 Mask       */
#define GPIO_PIN_INT_FALL_FDET3_Pos                           3                                                         /*!< GPIO_PIN_INT FALL: FDET3 Position   */
#define GPIO_PIN_INT_FALL_FDET3_Msk                           (0x01UL << GPIO_PIN_INT_FALL_FDET3_Pos)                   /*!< GPIO_PIN_INT FALL: FDET3 Mask       */
#define GPIO_PIN_INT_FALL_FDET4_Pos                           4                                                         /*!< GPIO_PIN_INT FALL: FDET4 Position   */
#define GPIO_PIN_INT_FALL_FDET4_Msk                           (0x01UL << GPIO_PIN_INT_FALL_FDET4_Pos)                   /*!< GPIO_PIN_INT FALL: FDET4 Mask       */
#define GPIO_PIN_INT_FALL_FDET5_Pos                           5                                                         /*!< GPIO_PIN_INT FALL: FDET5 Position   */
#define GPIO_PIN_INT_FALL_FDET5_Msk                           (0x01UL << GPIO_PIN_INT_FALL_FDET5_Pos)                   /*!< GPIO_PIN_INT FALL: FDET5 Mask       */
#define GPIO_PIN_INT_FALL_FDET6_Pos                           6                                                         /*!< GPIO_PIN_INT FALL: FDET6 Position   */
#define GPIO_PIN_INT_FALL_FDET6_Msk                           (0x01UL << GPIO_PIN_INT_FALL_FDET6_Pos)                   /*!< GPIO_PIN_INT FALL: FDET6 Mask       */
#define GPIO_PIN_INT_FALL_FDET7_Pos                           7                                                         /*!< GPIO_PIN_INT FALL: FDET7 Position   */
#define GPIO_PIN_INT_FALL_FDET7_Msk                           (0x01UL << GPIO_PIN_INT_FALL_FDET7_Pos)                   /*!< GPIO_PIN_INT FALL: FDET7 Mask       */

// ------------------------------------  GPIO_PIN_INT_IST  ----------------------------------------
#define GPIO_PIN_INT_IST_PSTAT0_Pos                           0                                                         /*!< GPIO_PIN_INT IST: PSTAT0 Position   */
#define GPIO_PIN_INT_IST_PSTAT0_Msk                           (0x01UL << GPIO_PIN_INT_IST_PSTAT0_Pos)                   /*!< GPIO_PIN_INT IST: PSTAT0 Mask       */
#define GPIO_PIN_INT_IST_PSTAT1_Pos                           1                                                         /*!< GPIO_PIN_INT IST: PSTAT1 Position   */
#define GPIO_PIN_INT_IST_PSTAT1_Msk                           (0x01UL << GPIO_PIN_INT_IST_PSTAT1_Pos)                   /*!< GPIO_PIN_INT IST: PSTAT1 Mask       */
#define GPIO_PIN_INT_IST_PSTAT2_Pos                           2                                                         /*!< GPIO_PIN_INT IST: PSTAT2 Position   */
#define GPIO_PIN_INT_IST_PSTAT2_Msk                           (0x01UL << GPIO_PIN_INT_IST_PSTAT2_Pos)                   /*!< GPIO_PIN_INT IST: PSTAT2 Mask       */
#define GPIO_PIN_INT_IST_PSTAT3_Pos                           3                                                         /*!< GPIO_PIN_INT IST: PSTAT3 Position   */
#define GPIO_PIN_INT_IST_PSTAT3_Msk                           (0x01UL << GPIO_PIN_INT_IST_PSTAT3_Pos)                   /*!< GPIO_PIN_INT IST: PSTAT3 Mask       */
#define GPIO_PIN_INT_IST_PSTAT4_Pos                           4                                                         /*!< GPIO_PIN_INT IST: PSTAT4 Position   */
#define GPIO_PIN_INT_IST_PSTAT4_Msk                           (0x01UL << GPIO_PIN_INT_IST_PSTAT4_Pos)                   /*!< GPIO_PIN_INT IST: PSTAT4 Mask       */
#define GPIO_PIN_INT_IST_PSTAT5_Pos                           5                                                         /*!< GPIO_PIN_INT IST: PSTAT5 Position   */
#define GPIO_PIN_INT_IST_PSTAT5_Msk                           (0x01UL << GPIO_PIN_INT_IST_PSTAT5_Pos)                   /*!< GPIO_PIN_INT IST: PSTAT5 Mask       */
#define GPIO_PIN_INT_IST_PSTAT6_Pos                           6                                                         /*!< GPIO_PIN_INT IST: PSTAT6 Position   */
#define GPIO_PIN_INT_IST_PSTAT6_Msk                           (0x01UL << GPIO_PIN_INT_IST_PSTAT6_Pos)                   /*!< GPIO_PIN_INT IST: PSTAT6 Mask       */
#define GPIO_PIN_INT_IST_PSTAT7_Pos                           7                                                         /*!< GPIO_PIN_INT IST: PSTAT7 Position   */
#define GPIO_PIN_INT_IST_PSTAT7_Msk                           (0x01UL << GPIO_PIN_INT_IST_PSTAT7_Pos)                   /*!< GPIO_PIN_INT IST: PSTAT7 Mask       */


// ------------------------------------------------------------------------------------------------
// -----                            GPIO_GROUP_INTn Position & Mask                           -----
// ------------------------------------------------------------------------------------------------


// ----------------------------------  GPIO_GROUP_INTn_CTRL  --------------------------------------
#define GPIO_GROUP_INTn_CTRL_INT_Pos                          0                                                         /*!< GPIO_GROUP_INTn CTRL: INT Position  */
#define GPIO_GROUP_INTn_CTRL_INT_Msk                          (0x01UL << GPIO_GROUP_INTn_CTRL_INT_Pos)                  /*!< GPIO_GROUP_INTn CTRL: INT Mask      */
#define GPIO_GROUP_INTn_CTRL_COMB_Pos                         1                                                         /*!< GPIO_GROUP_INTn CTRL: COMB Position */
#define GPIO_GROUP_INTn_CTRL_COMB_Msk                         (0x01UL << GPIO_GROUP_INTn_CTRL_COMB_Pos)                 /*!< GPIO_GROUP_INTn CTRL: COMB Mask     */
#define GPIO_GROUP_INTn_CTRL_TRIG_Pos                         2                                                         /*!< GPIO_GROUP_INTn CTRL: TRIG Position */
#define GPIO_GROUP_INTn_CTRL_TRIG_Msk                         (0x01UL << GPIO_GROUP_INTn_CTRL_TRIG_Pos)                 /*!< GPIO_GROUP_INTn CTRL: TRIG Mask     */

// --------------------------------  GPIO_GROUP_INTn_PORT_POL0  -----------------------------------
#define GPIO_GROUP_INTn_PORT_POL0_POL_0_Pos                   0                                                         /*!< GPIO_GROUP_INTn PORT_POL0: POL_0 Position */
#define GPIO_GROUP_INTn_PORT_POL0_POL_0_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_0_Pos)           /*!< GPIO_GROUP_INTn PORT_POL0: POL_0 Mask */
#define GPIO_GROUP_INTn_PORT_POL0_POL_1_Pos                   1                                                         /*!< GPIO_GROUP_INTn PORT_POL0: POL_1 Position */
#define GPIO_GROUP_INTn_PORT_POL0_POL_1_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_1_Pos)           /*!< GPIO_GROUP_INTn PORT_POL0: POL_1 Mask */
#define GPIO_GROUP_INTn_PORT_POL0_POL_2_Pos                   2                                                         /*!< GPIO_GROUP_INTn PORT_POL0: POL_2 Position */
#define GPIO_GROUP_INTn_PORT_POL0_POL_2_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_2_Pos)           /*!< GPIO_GROUP_INTn PORT_POL0: POL_2 Mask */
#define GPIO_GROUP_INTn_PORT_POL0_POL_3_Pos                   3                                                         /*!< GPIO_GROUP_INTn PORT_POL0: POL_3 Position */
#define GPIO_GROUP_INTn_PORT_POL0_POL_3_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_3_Pos)           /*!< GPIO_GROUP_INTn PORT_POL0: POL_3 Mask */
#define GPIO_GROUP_INTn_PORT_POL0_POL_4_Pos                   4                                                         /*!< GPIO_GROUP_INTn PORT_POL0: POL_4 Position */
#define GPIO_GROUP_INTn_PORT_POL0_POL_4_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_4_Pos)           /*!< GPIO_GROUP_INTn PORT_POL0: POL_4 Mask */
#define GPIO_GROUP_INTn_PORT_POL0_POL_5_Pos                   5                                                         /*!< GPIO_GROUP_INTn PORT_POL0: POL_5 Position */
#define GPIO_GROUP_INTn_PORT_POL0_POL_5_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_5_Pos)           /*!< GPIO_GROUP_INTn PORT_POL0: POL_5 Mask */
#define GPIO_GROUP_INTn_PORT_POL0_POL_6_Pos                   6                                                         /*!< GPIO_GROUP_INTn PORT_POL0: POL_6 Position */
#define GPIO_GROUP_INTn_PORT_POL0_POL_6_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_6_Pos)           /*!< GPIO_GROUP_INTn PORT_POL0: POL_6 Mask */
#define GPIO_GROUP_INTn_PORT_POL0_POL_7_Pos                   7                                                         /*!< GPIO_GROUP_INTn PORT_POL0: POL_7 Position */
#define GPIO_GROUP_INTn_PORT_POL0_POL_7_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_7_Pos)           /*!< GPIO_GROUP_INTn PORT_POL0: POL_7 Mask */
#define GPIO_GROUP_INTn_PORT_POL0_POL_8_Pos                   8                                                         /*!< GPIO_GROUP_INTn PORT_POL0: POL_8 Position */
#define GPIO_GROUP_INTn_PORT_POL0_POL_8_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_8_Pos)           /*!< GPIO_GROUP_INTn PORT_POL0: POL_8 Mask */
#define GPIO_GROUP_INTn_PORT_POL0_POL_9_Pos                   9                                                         /*!< GPIO_GROUP_INTn PORT_POL0: POL_9 Position */
#define GPIO_GROUP_INTn_PORT_POL0_POL_9_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_9_Pos)           /*!< GPIO_GROUP_INTn PORT_POL0: POL_9 Mask */
#define GPIO_GROUP_INTn_PORT_POL0_POL_10_Pos                  10                                                        /*!< GPIO_GROUP_INTn PORT_POL0: POL_10 Position */
#define GPIO_GROUP_INTn_PORT_POL0_POL_10_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_10_Pos)          /*!< GPIO_GROUP_INTn PORT_POL0: POL_10 Mask */
#define GPIO_GROUP_INTn_PORT_POL0_POL_11_Pos                  11                                                        /*!< GPIO_GROUP_INTn PORT_POL0: POL_11 Position */
#define GPIO_GROUP_INTn_PORT_POL0_POL_11_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_11_Pos)          /*!< GPIO_GROUP_INTn PORT_POL0: POL_11 Mask */
#define GPIO_GROUP_INTn_PORT_POL0_POL_12_Pos                  12                                                        /*!< GPIO_GROUP_INTn PORT_POL0: POL_12 Position */
#define GPIO_GROUP_INTn_PORT_POL0_POL_12_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_12_Pos)          /*!< GPIO_GROUP_INTn PORT_POL0: POL_12 Mask */
#define GPIO_GROUP_INTn_PORT_POL0_POL_13_Pos                  13                                                        /*!< GPIO_GROUP_INTn PORT_POL0: POL_13 Position */
#define GPIO_GROUP_INTn_PORT_POL0_POL_13_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_13_Pos)          /*!< GPIO_GROUP_INTn PORT_POL0: POL_13 Mask */
#define GPIO_GROUP_INTn_PORT_POL0_POL_14_Pos                  14                                                        /*!< GPIO_GROUP_INTn PORT_POL0: POL_14 Position */
#define GPIO_GROUP_INTn_PORT_POL0_POL_14_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_14_Pos)          /*!< GPIO_GROUP_INTn PORT_POL0: POL_14 Mask */
#define GPIO_GROUP_INTn_PORT_POL0_POL_15_Pos                  15                                                        /*!< GPIO_GROUP_INTn PORT_POL0: POL_15 Position */
#define GPIO_GROUP_INTn_PORT_POL0_POL_15_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_15_Pos)          /*!< GPIO_GROUP_INTn PORT_POL0: POL_15 Mask */
#define GPIO_GROUP_INTn_PORT_POL0_POL_16_Pos                  16                                                        /*!< GPIO_GROUP_INTn PORT_POL0: POL_16 Position */
#define GPIO_GROUP_INTn_PORT_POL0_POL_16_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_16_Pos)          /*!< GPIO_GROUP_INTn PORT_POL0: POL_16 Mask */
#define GPIO_GROUP_INTn_PORT_POL0_POL_17_Pos                  17                                                        /*!< GPIO_GROUP_INTn PORT_POL0: POL_17 Position */
#define GPIO_GROUP_INTn_PORT_POL0_POL_17_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_17_Pos)          /*!< GPIO_GROUP_INTn PORT_POL0: POL_17 Mask */
#define GPIO_GROUP_INTn_PORT_POL0_POL_18_Pos                  18                                                        /*!< GPIO_GROUP_INTn PORT_POL0: POL_18 Position */
#define GPIO_GROUP_INTn_PORT_POL0_POL_18_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_18_Pos)          /*!< GPIO_GROUP_INTn PORT_POL0: POL_18 Mask */
#define GPIO_GROUP_INTn_PORT_POL0_POL_19_Pos                  19                                                        /*!< GPIO_GROUP_INTn PORT_POL0: POL_19 Position */
#define GPIO_GROUP_INTn_PORT_POL0_POL_19_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_19_Pos)          /*!< GPIO_GROUP_INTn PORT_POL0: POL_19 Mask */
#define GPIO_GROUP_INTn_PORT_POL0_POL_20_Pos                  20                                                        /*!< GPIO_GROUP_INTn PORT_POL0: POL_20 Position */
#define GPIO_GROUP_INTn_PORT_POL0_POL_20_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_20_Pos)          /*!< GPIO_GROUP_INTn PORT_POL0: POL_20 Mask */
#define GPIO_GROUP_INTn_PORT_POL0_POL_21_Pos                  21                                                        /*!< GPIO_GROUP_INTn PORT_POL0: POL_21 Position */
#define GPIO_GROUP_INTn_PORT_POL0_POL_21_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_21_Pos)          /*!< GPIO_GROUP_INTn PORT_POL0: POL_21 Mask */
#define GPIO_GROUP_INTn_PORT_POL0_POL_22_Pos                  22                                                        /*!< GPIO_GROUP_INTn PORT_POL0: POL_22 Position */
#define GPIO_GROUP_INTn_PORT_POL0_POL_22_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_22_Pos)          /*!< GPIO_GROUP_INTn PORT_POL0: POL_22 Mask */
#define GPIO_GROUP_INTn_PORT_POL0_POL_23_Pos                  23                                                        /*!< GPIO_GROUP_INTn PORT_POL0: POL_23 Position */
#define GPIO_GROUP_INTn_PORT_POL0_POL_23_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_23_Pos)          /*!< GPIO_GROUP_INTn PORT_POL0: POL_23 Mask */
#define GPIO_GROUP_INTn_PORT_POL0_POL_24_Pos                  24                                                        /*!< GPIO_GROUP_INTn PORT_POL0: POL_24 Position */
#define GPIO_GROUP_INTn_PORT_POL0_POL_24_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_24_Pos)          /*!< GPIO_GROUP_INTn PORT_POL0: POL_24 Mask */
#define GPIO_GROUP_INTn_PORT_POL0_POL_25_Pos                  25                                                        /*!< GPIO_GROUP_INTn PORT_POL0: POL_25 Position */
#define GPIO_GROUP_INTn_PORT_POL0_POL_25_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_25_Pos)          /*!< GPIO_GROUP_INTn PORT_POL0: POL_25 Mask */
#define GPIO_GROUP_INTn_PORT_POL0_POL_26_Pos                  26                                                        /*!< GPIO_GROUP_INTn PORT_POL0: POL_26 Position */
#define GPIO_GROUP_INTn_PORT_POL0_POL_26_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_26_Pos)          /*!< GPIO_GROUP_INTn PORT_POL0: POL_26 Mask */
#define GPIO_GROUP_INTn_PORT_POL0_POL_27_Pos                  27                                                        /*!< GPIO_GROUP_INTn PORT_POL0: POL_27 Position */
#define GPIO_GROUP_INTn_PORT_POL0_POL_27_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_27_Pos)          /*!< GPIO_GROUP_INTn PORT_POL0: POL_27 Mask */
#define GPIO_GROUP_INTn_PORT_POL0_POL_28_Pos                  28                                                        /*!< GPIO_GROUP_INTn PORT_POL0: POL_28 Position */
#define GPIO_GROUP_INTn_PORT_POL0_POL_28_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_28_Pos)          /*!< GPIO_GROUP_INTn PORT_POL0: POL_28 Mask */
#define GPIO_GROUP_INTn_PORT_POL0_POL_29_Pos                  29                                                        /*!< GPIO_GROUP_INTn PORT_POL0: POL_29 Position */
#define GPIO_GROUP_INTn_PORT_POL0_POL_29_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_29_Pos)          /*!< GPIO_GROUP_INTn PORT_POL0: POL_29 Mask */
#define GPIO_GROUP_INTn_PORT_POL0_POL_30_Pos                  30                                                        /*!< GPIO_GROUP_INTn PORT_POL0: POL_30 Position */
#define GPIO_GROUP_INTn_PORT_POL0_POL_30_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_30_Pos)          /*!< GPIO_GROUP_INTn PORT_POL0: POL_30 Mask */
#define GPIO_GROUP_INTn_PORT_POL0_POL_31_Pos                  31                                                        /*!< GPIO_GROUP_INTn PORT_POL0: POL_31 Position */
#define GPIO_GROUP_INTn_PORT_POL0_POL_31_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_31_Pos)          /*!< GPIO_GROUP_INTn PORT_POL0: POL_31 Mask */

// --------------------------------  GPIO_GROUP_INTn_PORT_POL1  -----------------------------------
#define GPIO_GROUP_INTn_PORT_POL1_POL_0_Pos                   0                                                         /*!< GPIO_GROUP_INTn PORT_POL1: POL_0 Position */
#define GPIO_GROUP_INTn_PORT_POL1_POL_0_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_0_Pos)           /*!< GPIO_GROUP_INTn PORT_POL1: POL_0 Mask */
#define GPIO_GROUP_INTn_PORT_POL1_POL_1_Pos                   1                                                         /*!< GPIO_GROUP_INTn PORT_POL1: POL_1 Position */
#define GPIO_GROUP_INTn_PORT_POL1_POL_1_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_1_Pos)           /*!< GPIO_GROUP_INTn PORT_POL1: POL_1 Mask */
#define GPIO_GROUP_INTn_PORT_POL1_POL_2_Pos                   2                                                         /*!< GPIO_GROUP_INTn PORT_POL1: POL_2 Position */
#define GPIO_GROUP_INTn_PORT_POL1_POL_2_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_2_Pos)           /*!< GPIO_GROUP_INTn PORT_POL1: POL_2 Mask */
#define GPIO_GROUP_INTn_PORT_POL1_POL_3_Pos                   3                                                         /*!< GPIO_GROUP_INTn PORT_POL1: POL_3 Position */
#define GPIO_GROUP_INTn_PORT_POL1_POL_3_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_3_Pos)           /*!< GPIO_GROUP_INTn PORT_POL1: POL_3 Mask */
#define GPIO_GROUP_INTn_PORT_POL1_POL_4_Pos                   4                                                         /*!< GPIO_GROUP_INTn PORT_POL1: POL_4 Position */
#define GPIO_GROUP_INTn_PORT_POL1_POL_4_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_4_Pos)           /*!< GPIO_GROUP_INTn PORT_POL1: POL_4 Mask */
#define GPIO_GROUP_INTn_PORT_POL1_POL_5_Pos                   5                                                         /*!< GPIO_GROUP_INTn PORT_POL1: POL_5 Position */
#define GPIO_GROUP_INTn_PORT_POL1_POL_5_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_5_Pos)           /*!< GPIO_GROUP_INTn PORT_POL1: POL_5 Mask */
#define GPIO_GROUP_INTn_PORT_POL1_POL_6_Pos                   6                                                         /*!< GPIO_GROUP_INTn PORT_POL1: POL_6 Position */
#define GPIO_GROUP_INTn_PORT_POL1_POL_6_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_6_Pos)           /*!< GPIO_GROUP_INTn PORT_POL1: POL_6 Mask */
#define GPIO_GROUP_INTn_PORT_POL1_POL_7_Pos                   7                                                         /*!< GPIO_GROUP_INTn PORT_POL1: POL_7 Position */
#define GPIO_GROUP_INTn_PORT_POL1_POL_7_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_7_Pos)           /*!< GPIO_GROUP_INTn PORT_POL1: POL_7 Mask */
#define GPIO_GROUP_INTn_PORT_POL1_POL_8_Pos                   8                                                         /*!< GPIO_GROUP_INTn PORT_POL1: POL_8 Position */
#define GPIO_GROUP_INTn_PORT_POL1_POL_8_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_8_Pos)           /*!< GPIO_GROUP_INTn PORT_POL1: POL_8 Mask */
#define GPIO_GROUP_INTn_PORT_POL1_POL_9_Pos                   9                                                         /*!< GPIO_GROUP_INTn PORT_POL1: POL_9 Position */
#define GPIO_GROUP_INTn_PORT_POL1_POL_9_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_9_Pos)           /*!< GPIO_GROUP_INTn PORT_POL1: POL_9 Mask */
#define GPIO_GROUP_INTn_PORT_POL1_POL_10_Pos                  10                                                        /*!< GPIO_GROUP_INTn PORT_POL1: POL_10 Position */
#define GPIO_GROUP_INTn_PORT_POL1_POL_10_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_10_Pos)          /*!< GPIO_GROUP_INTn PORT_POL1: POL_10 Mask */
#define GPIO_GROUP_INTn_PORT_POL1_POL_11_Pos                  11                                                        /*!< GPIO_GROUP_INTn PORT_POL1: POL_11 Position */
#define GPIO_GROUP_INTn_PORT_POL1_POL_11_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_11_Pos)          /*!< GPIO_GROUP_INTn PORT_POL1: POL_11 Mask */
#define GPIO_GROUP_INTn_PORT_POL1_POL_12_Pos                  12                                                        /*!< GPIO_GROUP_INTn PORT_POL1: POL_12 Position */
#define GPIO_GROUP_INTn_PORT_POL1_POL_12_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_12_Pos)          /*!< GPIO_GROUP_INTn PORT_POL1: POL_12 Mask */
#define GPIO_GROUP_INTn_PORT_POL1_POL_13_Pos                  13                                                        /*!< GPIO_GROUP_INTn PORT_POL1: POL_13 Position */
#define GPIO_GROUP_INTn_PORT_POL1_POL_13_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_13_Pos)          /*!< GPIO_GROUP_INTn PORT_POL1: POL_13 Mask */
#define GPIO_GROUP_INTn_PORT_POL1_POL_14_Pos                  14                                                        /*!< GPIO_GROUP_INTn PORT_POL1: POL_14 Position */
#define GPIO_GROUP_INTn_PORT_POL1_POL_14_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_14_Pos)          /*!< GPIO_GROUP_INTn PORT_POL1: POL_14 Mask */
#define GPIO_GROUP_INTn_PORT_POL1_POL_15_Pos                  15                                                        /*!< GPIO_GROUP_INTn PORT_POL1: POL_15 Position */
#define GPIO_GROUP_INTn_PORT_POL1_POL_15_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_15_Pos)          /*!< GPIO_GROUP_INTn PORT_POL1: POL_15 Mask */
#define GPIO_GROUP_INTn_PORT_POL1_POL_16_Pos                  16                                                        /*!< GPIO_GROUP_INTn PORT_POL1: POL_16 Position */
#define GPIO_GROUP_INTn_PORT_POL1_POL_16_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_16_Pos)          /*!< GPIO_GROUP_INTn PORT_POL1: POL_16 Mask */
#define GPIO_GROUP_INTn_PORT_POL1_POL_17_Pos                  17                                                        /*!< GPIO_GROUP_INTn PORT_POL1: POL_17 Position */
#define GPIO_GROUP_INTn_PORT_POL1_POL_17_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_17_Pos)          /*!< GPIO_GROUP_INTn PORT_POL1: POL_17 Mask */
#define GPIO_GROUP_INTn_PORT_POL1_POL_18_Pos                  18                                                        /*!< GPIO_GROUP_INTn PORT_POL1: POL_18 Position */
#define GPIO_GROUP_INTn_PORT_POL1_POL_18_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_18_Pos)          /*!< GPIO_GROUP_INTn PORT_POL1: POL_18 Mask */
#define GPIO_GROUP_INTn_PORT_POL1_POL_19_Pos                  19                                                        /*!< GPIO_GROUP_INTn PORT_POL1: POL_19 Position */
#define GPIO_GROUP_INTn_PORT_POL1_POL_19_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_19_Pos)          /*!< GPIO_GROUP_INTn PORT_POL1: POL_19 Mask */
#define GPIO_GROUP_INTn_PORT_POL1_POL_20_Pos                  20                                                        /*!< GPIO_GROUP_INTn PORT_POL1: POL_20 Position */
#define GPIO_GROUP_INTn_PORT_POL1_POL_20_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_20_Pos)          /*!< GPIO_GROUP_INTn PORT_POL1: POL_20 Mask */
#define GPIO_GROUP_INTn_PORT_POL1_POL_21_Pos                  21                                                        /*!< GPIO_GROUP_INTn PORT_POL1: POL_21 Position */
#define GPIO_GROUP_INTn_PORT_POL1_POL_21_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_21_Pos)          /*!< GPIO_GROUP_INTn PORT_POL1: POL_21 Mask */
#define GPIO_GROUP_INTn_PORT_POL1_POL_22_Pos                  22                                                        /*!< GPIO_GROUP_INTn PORT_POL1: POL_22 Position */
#define GPIO_GROUP_INTn_PORT_POL1_POL_22_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_22_Pos)          /*!< GPIO_GROUP_INTn PORT_POL1: POL_22 Mask */
#define GPIO_GROUP_INTn_PORT_POL1_POL_23_Pos                  23                                                        /*!< GPIO_GROUP_INTn PORT_POL1: POL_23 Position */
#define GPIO_GROUP_INTn_PORT_POL1_POL_23_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_23_Pos)          /*!< GPIO_GROUP_INTn PORT_POL1: POL_23 Mask */
#define GPIO_GROUP_INTn_PORT_POL1_POL_24_Pos                  24                                                        /*!< GPIO_GROUP_INTn PORT_POL1: POL_24 Position */
#define GPIO_GROUP_INTn_PORT_POL1_POL_24_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_24_Pos)          /*!< GPIO_GROUP_INTn PORT_POL1: POL_24 Mask */
#define GPIO_GROUP_INTn_PORT_POL1_POL_25_Pos                  25                                                        /*!< GPIO_GROUP_INTn PORT_POL1: POL_25 Position */
#define GPIO_GROUP_INTn_PORT_POL1_POL_25_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_25_Pos)          /*!< GPIO_GROUP_INTn PORT_POL1: POL_25 Mask */
#define GPIO_GROUP_INTn_PORT_POL1_POL_26_Pos                  26                                                        /*!< GPIO_GROUP_INTn PORT_POL1: POL_26 Position */
#define GPIO_GROUP_INTn_PORT_POL1_POL_26_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_26_Pos)          /*!< GPIO_GROUP_INTn PORT_POL1: POL_26 Mask */
#define GPIO_GROUP_INTn_PORT_POL1_POL_27_Pos                  27                                                        /*!< GPIO_GROUP_INTn PORT_POL1: POL_27 Position */
#define GPIO_GROUP_INTn_PORT_POL1_POL_27_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_27_Pos)          /*!< GPIO_GROUP_INTn PORT_POL1: POL_27 Mask */
#define GPIO_GROUP_INTn_PORT_POL1_POL_28_Pos                  28                                                        /*!< GPIO_GROUP_INTn PORT_POL1: POL_28 Position */
#define GPIO_GROUP_INTn_PORT_POL1_POL_28_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_28_Pos)          /*!< GPIO_GROUP_INTn PORT_POL1: POL_28 Mask */
#define GPIO_GROUP_INTn_PORT_POL1_POL_29_Pos                  29                                                        /*!< GPIO_GROUP_INTn PORT_POL1: POL_29 Position */
#define GPIO_GROUP_INTn_PORT_POL1_POL_29_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_29_Pos)          /*!< GPIO_GROUP_INTn PORT_POL1: POL_29 Mask */
#define GPIO_GROUP_INTn_PORT_POL1_POL_30_Pos                  30                                                        /*!< GPIO_GROUP_INTn PORT_POL1: POL_30 Position */
#define GPIO_GROUP_INTn_PORT_POL1_POL_30_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_30_Pos)          /*!< GPIO_GROUP_INTn PORT_POL1: POL_30 Mask */
#define GPIO_GROUP_INTn_PORT_POL1_POL_31_Pos                  31                                                        /*!< GPIO_GROUP_INTn PORT_POL1: POL_31 Position */
#define GPIO_GROUP_INTn_PORT_POL1_POL_31_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_31_Pos)          /*!< GPIO_GROUP_INTn PORT_POL1: POL_31 Mask */

// --------------------------------  GPIO_GROUP_INTn_PORT_POL2  -----------------------------------
#define GPIO_GROUP_INTn_PORT_POL2_POL_0_Pos                   0                                                         /*!< GPIO_GROUP_INTn PORT_POL2: POL_0 Position */
#define GPIO_GROUP_INTn_PORT_POL2_POL_0_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_0_Pos)           /*!< GPIO_GROUP_INTn PORT_POL2: POL_0 Mask */
#define GPIO_GROUP_INTn_PORT_POL2_POL_1_Pos                   1                                                         /*!< GPIO_GROUP_INTn PORT_POL2: POL_1 Position */
#define GPIO_GROUP_INTn_PORT_POL2_POL_1_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_1_Pos)           /*!< GPIO_GROUP_INTn PORT_POL2: POL_1 Mask */
#define GPIO_GROUP_INTn_PORT_POL2_POL_2_Pos                   2                                                         /*!< GPIO_GROUP_INTn PORT_POL2: POL_2 Position */
#define GPIO_GROUP_INTn_PORT_POL2_POL_2_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_2_Pos)           /*!< GPIO_GROUP_INTn PORT_POL2: POL_2 Mask */
#define GPIO_GROUP_INTn_PORT_POL2_POL_3_Pos                   3                                                         /*!< GPIO_GROUP_INTn PORT_POL2: POL_3 Position */
#define GPIO_GROUP_INTn_PORT_POL2_POL_3_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_3_Pos)           /*!< GPIO_GROUP_INTn PORT_POL2: POL_3 Mask */
#define GPIO_GROUP_INTn_PORT_POL2_POL_4_Pos                   4                                                         /*!< GPIO_GROUP_INTn PORT_POL2: POL_4 Position */
#define GPIO_GROUP_INTn_PORT_POL2_POL_4_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_4_Pos)           /*!< GPIO_GROUP_INTn PORT_POL2: POL_4 Mask */
#define GPIO_GROUP_INTn_PORT_POL2_POL_5_Pos                   5                                                         /*!< GPIO_GROUP_INTn PORT_POL2: POL_5 Position */
#define GPIO_GROUP_INTn_PORT_POL2_POL_5_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_5_Pos)           /*!< GPIO_GROUP_INTn PORT_POL2: POL_5 Mask */
#define GPIO_GROUP_INTn_PORT_POL2_POL_6_Pos                   6                                                         /*!< GPIO_GROUP_INTn PORT_POL2: POL_6 Position */
#define GPIO_GROUP_INTn_PORT_POL2_POL_6_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_6_Pos)           /*!< GPIO_GROUP_INTn PORT_POL2: POL_6 Mask */
#define GPIO_GROUP_INTn_PORT_POL2_POL_7_Pos                   7                                                         /*!< GPIO_GROUP_INTn PORT_POL2: POL_7 Position */
#define GPIO_GROUP_INTn_PORT_POL2_POL_7_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_7_Pos)           /*!< GPIO_GROUP_INTn PORT_POL2: POL_7 Mask */
#define GPIO_GROUP_INTn_PORT_POL2_POL_8_Pos                   8                                                         /*!< GPIO_GROUP_INTn PORT_POL2: POL_8 Position */
#define GPIO_GROUP_INTn_PORT_POL2_POL_8_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_8_Pos)           /*!< GPIO_GROUP_INTn PORT_POL2: POL_8 Mask */
#define GPIO_GROUP_INTn_PORT_POL2_POL_9_Pos                   9                                                         /*!< GPIO_GROUP_INTn PORT_POL2: POL_9 Position */
#define GPIO_GROUP_INTn_PORT_POL2_POL_9_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_9_Pos)           /*!< GPIO_GROUP_INTn PORT_POL2: POL_9 Mask */
#define GPIO_GROUP_INTn_PORT_POL2_POL_10_Pos                  10                                                        /*!< GPIO_GROUP_INTn PORT_POL2: POL_10 Position */
#define GPIO_GROUP_INTn_PORT_POL2_POL_10_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_10_Pos)          /*!< GPIO_GROUP_INTn PORT_POL2: POL_10 Mask */
#define GPIO_GROUP_INTn_PORT_POL2_POL_11_Pos                  11                                                        /*!< GPIO_GROUP_INTn PORT_POL2: POL_11 Position */
#define GPIO_GROUP_INTn_PORT_POL2_POL_11_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_11_Pos)          /*!< GPIO_GROUP_INTn PORT_POL2: POL_11 Mask */
#define GPIO_GROUP_INTn_PORT_POL2_POL_12_Pos                  12                                                        /*!< GPIO_GROUP_INTn PORT_POL2: POL_12 Position */
#define GPIO_GROUP_INTn_PORT_POL2_POL_12_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_12_Pos)          /*!< GPIO_GROUP_INTn PORT_POL2: POL_12 Mask */
#define GPIO_GROUP_INTn_PORT_POL2_POL_13_Pos                  13                                                        /*!< GPIO_GROUP_INTn PORT_POL2: POL_13 Position */
#define GPIO_GROUP_INTn_PORT_POL2_POL_13_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_13_Pos)          /*!< GPIO_GROUP_INTn PORT_POL2: POL_13 Mask */
#define GPIO_GROUP_INTn_PORT_POL2_POL_14_Pos                  14                                                        /*!< GPIO_GROUP_INTn PORT_POL2: POL_14 Position */
#define GPIO_GROUP_INTn_PORT_POL2_POL_14_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_14_Pos)          /*!< GPIO_GROUP_INTn PORT_POL2: POL_14 Mask */
#define GPIO_GROUP_INTn_PORT_POL2_POL_15_Pos                  15                                                        /*!< GPIO_GROUP_INTn PORT_POL2: POL_15 Position */
#define GPIO_GROUP_INTn_PORT_POL2_POL_15_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_15_Pos)          /*!< GPIO_GROUP_INTn PORT_POL2: POL_15 Mask */
#define GPIO_GROUP_INTn_PORT_POL2_POL_16_Pos                  16                                                        /*!< GPIO_GROUP_INTn PORT_POL2: POL_16 Position */
#define GPIO_GROUP_INTn_PORT_POL2_POL_16_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_16_Pos)          /*!< GPIO_GROUP_INTn PORT_POL2: POL_16 Mask */
#define GPIO_GROUP_INTn_PORT_POL2_POL_17_Pos                  17                                                        /*!< GPIO_GROUP_INTn PORT_POL2: POL_17 Position */
#define GPIO_GROUP_INTn_PORT_POL2_POL_17_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_17_Pos)          /*!< GPIO_GROUP_INTn PORT_POL2: POL_17 Mask */
#define GPIO_GROUP_INTn_PORT_POL2_POL_18_Pos                  18                                                        /*!< GPIO_GROUP_INTn PORT_POL2: POL_18 Position */
#define GPIO_GROUP_INTn_PORT_POL2_POL_18_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_18_Pos)          /*!< GPIO_GROUP_INTn PORT_POL2: POL_18 Mask */
#define GPIO_GROUP_INTn_PORT_POL2_POL_19_Pos                  19                                                        /*!< GPIO_GROUP_INTn PORT_POL2: POL_19 Position */
#define GPIO_GROUP_INTn_PORT_POL2_POL_19_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_19_Pos)          /*!< GPIO_GROUP_INTn PORT_POL2: POL_19 Mask */
#define GPIO_GROUP_INTn_PORT_POL2_POL_20_Pos                  20                                                        /*!< GPIO_GROUP_INTn PORT_POL2: POL_20 Position */
#define GPIO_GROUP_INTn_PORT_POL2_POL_20_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_20_Pos)          /*!< GPIO_GROUP_INTn PORT_POL2: POL_20 Mask */
#define GPIO_GROUP_INTn_PORT_POL2_POL_21_Pos                  21                                                        /*!< GPIO_GROUP_INTn PORT_POL2: POL_21 Position */
#define GPIO_GROUP_INTn_PORT_POL2_POL_21_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_21_Pos)          /*!< GPIO_GROUP_INTn PORT_POL2: POL_21 Mask */
#define GPIO_GROUP_INTn_PORT_POL2_POL_22_Pos                  22                                                        /*!< GPIO_GROUP_INTn PORT_POL2: POL_22 Position */
#define GPIO_GROUP_INTn_PORT_POL2_POL_22_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_22_Pos)          /*!< GPIO_GROUP_INTn PORT_POL2: POL_22 Mask */
#define GPIO_GROUP_INTn_PORT_POL2_POL_23_Pos                  23                                                        /*!< GPIO_GROUP_INTn PORT_POL2: POL_23 Position */
#define GPIO_GROUP_INTn_PORT_POL2_POL_23_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_23_Pos)          /*!< GPIO_GROUP_INTn PORT_POL2: POL_23 Mask */
#define GPIO_GROUP_INTn_PORT_POL2_POL_24_Pos                  24                                                        /*!< GPIO_GROUP_INTn PORT_POL2: POL_24 Position */
#define GPIO_GROUP_INTn_PORT_POL2_POL_24_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_24_Pos)          /*!< GPIO_GROUP_INTn PORT_POL2: POL_24 Mask */
#define GPIO_GROUP_INTn_PORT_POL2_POL_25_Pos                  25                                                        /*!< GPIO_GROUP_INTn PORT_POL2: POL_25 Position */
#define GPIO_GROUP_INTn_PORT_POL2_POL_25_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_25_Pos)          /*!< GPIO_GROUP_INTn PORT_POL2: POL_25 Mask */
#define GPIO_GROUP_INTn_PORT_POL2_POL_26_Pos                  26                                                        /*!< GPIO_GROUP_INTn PORT_POL2: POL_26 Position */
#define GPIO_GROUP_INTn_PORT_POL2_POL_26_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_26_Pos)          /*!< GPIO_GROUP_INTn PORT_POL2: POL_26 Mask */
#define GPIO_GROUP_INTn_PORT_POL2_POL_27_Pos                  27                                                        /*!< GPIO_GROUP_INTn PORT_POL2: POL_27 Position */
#define GPIO_GROUP_INTn_PORT_POL2_POL_27_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_27_Pos)          /*!< GPIO_GROUP_INTn PORT_POL2: POL_27 Mask */
#define GPIO_GROUP_INTn_PORT_POL2_POL_28_Pos                  28                                                        /*!< GPIO_GROUP_INTn PORT_POL2: POL_28 Position */
#define GPIO_GROUP_INTn_PORT_POL2_POL_28_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_28_Pos)          /*!< GPIO_GROUP_INTn PORT_POL2: POL_28 Mask */
#define GPIO_GROUP_INTn_PORT_POL2_POL_29_Pos                  29                                                        /*!< GPIO_GROUP_INTn PORT_POL2: POL_29 Position */
#define GPIO_GROUP_INTn_PORT_POL2_POL_29_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_29_Pos)          /*!< GPIO_GROUP_INTn PORT_POL2: POL_29 Mask */
#define GPIO_GROUP_INTn_PORT_POL2_POL_30_Pos                  30                                                        /*!< GPIO_GROUP_INTn PORT_POL2: POL_30 Position */
#define GPIO_GROUP_INTn_PORT_POL2_POL_30_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_30_Pos)          /*!< GPIO_GROUP_INTn PORT_POL2: POL_30 Mask */
#define GPIO_GROUP_INTn_PORT_POL2_POL_31_Pos                  31                                                        /*!< GPIO_GROUP_INTn PORT_POL2: POL_31 Position */
#define GPIO_GROUP_INTn_PORT_POL2_POL_31_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_31_Pos)          /*!< GPIO_GROUP_INTn PORT_POL2: POL_31 Mask */

// --------------------------------  GPIO_GROUP_INTn_PORT_POL3  -----------------------------------
#define GPIO_GROUP_INTn_PORT_POL3_POL_0_Pos                   0                                                         /*!< GPIO_GROUP_INTn PORT_POL3: POL_0 Position */
#define GPIO_GROUP_INTn_PORT_POL3_POL_0_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_0_Pos)           /*!< GPIO_GROUP_INTn PORT_POL3: POL_0 Mask */
#define GPIO_GROUP_INTn_PORT_POL3_POL_1_Pos                   1                                                         /*!< GPIO_GROUP_INTn PORT_POL3: POL_1 Position */
#define GPIO_GROUP_INTn_PORT_POL3_POL_1_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_1_Pos)           /*!< GPIO_GROUP_INTn PORT_POL3: POL_1 Mask */
#define GPIO_GROUP_INTn_PORT_POL3_POL_2_Pos                   2                                                         /*!< GPIO_GROUP_INTn PORT_POL3: POL_2 Position */
#define GPIO_GROUP_INTn_PORT_POL3_POL_2_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_2_Pos)           /*!< GPIO_GROUP_INTn PORT_POL3: POL_2 Mask */
#define GPIO_GROUP_INTn_PORT_POL3_POL_3_Pos                   3                                                         /*!< GPIO_GROUP_INTn PORT_POL3: POL_3 Position */
#define GPIO_GROUP_INTn_PORT_POL3_POL_3_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_3_Pos)           /*!< GPIO_GROUP_INTn PORT_POL3: POL_3 Mask */
#define GPIO_GROUP_INTn_PORT_POL3_POL_4_Pos                   4                                                         /*!< GPIO_GROUP_INTn PORT_POL3: POL_4 Position */
#define GPIO_GROUP_INTn_PORT_POL3_POL_4_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_4_Pos)           /*!< GPIO_GROUP_INTn PORT_POL3: POL_4 Mask */
#define GPIO_GROUP_INTn_PORT_POL3_POL_5_Pos                   5                                                         /*!< GPIO_GROUP_INTn PORT_POL3: POL_5 Position */
#define GPIO_GROUP_INTn_PORT_POL3_POL_5_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_5_Pos)           /*!< GPIO_GROUP_INTn PORT_POL3: POL_5 Mask */
#define GPIO_GROUP_INTn_PORT_POL3_POL_6_Pos                   6                                                         /*!< GPIO_GROUP_INTn PORT_POL3: POL_6 Position */
#define GPIO_GROUP_INTn_PORT_POL3_POL_6_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_6_Pos)           /*!< GPIO_GROUP_INTn PORT_POL3: POL_6 Mask */
#define GPIO_GROUP_INTn_PORT_POL3_POL_7_Pos                   7                                                         /*!< GPIO_GROUP_INTn PORT_POL3: POL_7 Position */
#define GPIO_GROUP_INTn_PORT_POL3_POL_7_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_7_Pos)           /*!< GPIO_GROUP_INTn PORT_POL3: POL_7 Mask */
#define GPIO_GROUP_INTn_PORT_POL3_POL_8_Pos                   8                                                         /*!< GPIO_GROUP_INTn PORT_POL3: POL_8 Position */
#define GPIO_GROUP_INTn_PORT_POL3_POL_8_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_8_Pos)           /*!< GPIO_GROUP_INTn PORT_POL3: POL_8 Mask */
#define GPIO_GROUP_INTn_PORT_POL3_POL_9_Pos                   9                                                         /*!< GPIO_GROUP_INTn PORT_POL3: POL_9 Position */
#define GPIO_GROUP_INTn_PORT_POL3_POL_9_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_9_Pos)           /*!< GPIO_GROUP_INTn PORT_POL3: POL_9 Mask */
#define GPIO_GROUP_INTn_PORT_POL3_POL_10_Pos                  10                                                        /*!< GPIO_GROUP_INTn PORT_POL3: POL_10 Position */
#define GPIO_GROUP_INTn_PORT_POL3_POL_10_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_10_Pos)          /*!< GPIO_GROUP_INTn PORT_POL3: POL_10 Mask */
#define GPIO_GROUP_INTn_PORT_POL3_POL_11_Pos                  11                                                        /*!< GPIO_GROUP_INTn PORT_POL3: POL_11 Position */
#define GPIO_GROUP_INTn_PORT_POL3_POL_11_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_11_Pos)          /*!< GPIO_GROUP_INTn PORT_POL3: POL_11 Mask */
#define GPIO_GROUP_INTn_PORT_POL3_POL_12_Pos                  12                                                        /*!< GPIO_GROUP_INTn PORT_POL3: POL_12 Position */
#define GPIO_GROUP_INTn_PORT_POL3_POL_12_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_12_Pos)          /*!< GPIO_GROUP_INTn PORT_POL3: POL_12 Mask */
#define GPIO_GROUP_INTn_PORT_POL3_POL_13_Pos                  13                                                        /*!< GPIO_GROUP_INTn PORT_POL3: POL_13 Position */
#define GPIO_GROUP_INTn_PORT_POL3_POL_13_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_13_Pos)          /*!< GPIO_GROUP_INTn PORT_POL3: POL_13 Mask */
#define GPIO_GROUP_INTn_PORT_POL3_POL_14_Pos                  14                                                        /*!< GPIO_GROUP_INTn PORT_POL3: POL_14 Position */
#define GPIO_GROUP_INTn_PORT_POL3_POL_14_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_14_Pos)          /*!< GPIO_GROUP_INTn PORT_POL3: POL_14 Mask */
#define GPIO_GROUP_INTn_PORT_POL3_POL_15_Pos                  15                                                        /*!< GPIO_GROUP_INTn PORT_POL3: POL_15 Position */
#define GPIO_GROUP_INTn_PORT_POL3_POL_15_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_15_Pos)          /*!< GPIO_GROUP_INTn PORT_POL3: POL_15 Mask */
#define GPIO_GROUP_INTn_PORT_POL3_POL_16_Pos                  16                                                        /*!< GPIO_GROUP_INTn PORT_POL3: POL_16 Position */
#define GPIO_GROUP_INTn_PORT_POL3_POL_16_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_16_Pos)          /*!< GPIO_GROUP_INTn PORT_POL3: POL_16 Mask */
#define GPIO_GROUP_INTn_PORT_POL3_POL_17_Pos                  17                                                        /*!< GPIO_GROUP_INTn PORT_POL3: POL_17 Position */
#define GPIO_GROUP_INTn_PORT_POL3_POL_17_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_17_Pos)          /*!< GPIO_GROUP_INTn PORT_POL3: POL_17 Mask */
#define GPIO_GROUP_INTn_PORT_POL3_POL_18_Pos                  18                                                        /*!< GPIO_GROUP_INTn PORT_POL3: POL_18 Position */
#define GPIO_GROUP_INTn_PORT_POL3_POL_18_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_18_Pos)          /*!< GPIO_GROUP_INTn PORT_POL3: POL_18 Mask */
#define GPIO_GROUP_INTn_PORT_POL3_POL_19_Pos                  19                                                        /*!< GPIO_GROUP_INTn PORT_POL3: POL_19 Position */
#define GPIO_GROUP_INTn_PORT_POL3_POL_19_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_19_Pos)          /*!< GPIO_GROUP_INTn PORT_POL3: POL_19 Mask */
#define GPIO_GROUP_INTn_PORT_POL3_POL_20_Pos                  20                                                        /*!< GPIO_GROUP_INTn PORT_POL3: POL_20 Position */
#define GPIO_GROUP_INTn_PORT_POL3_POL_20_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_20_Pos)          /*!< GPIO_GROUP_INTn PORT_POL3: POL_20 Mask */
#define GPIO_GROUP_INTn_PORT_POL3_POL_21_Pos                  21                                                        /*!< GPIO_GROUP_INTn PORT_POL3: POL_21 Position */
#define GPIO_GROUP_INTn_PORT_POL3_POL_21_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_21_Pos)          /*!< GPIO_GROUP_INTn PORT_POL3: POL_21 Mask */
#define GPIO_GROUP_INTn_PORT_POL3_POL_22_Pos                  22                                                        /*!< GPIO_GROUP_INTn PORT_POL3: POL_22 Position */
#define GPIO_GROUP_INTn_PORT_POL3_POL_22_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_22_Pos)          /*!< GPIO_GROUP_INTn PORT_POL3: POL_22 Mask */
#define GPIO_GROUP_INTn_PORT_POL3_POL_23_Pos                  23                                                        /*!< GPIO_GROUP_INTn PORT_POL3: POL_23 Position */
#define GPIO_GROUP_INTn_PORT_POL3_POL_23_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_23_Pos)          /*!< GPIO_GROUP_INTn PORT_POL3: POL_23 Mask */
#define GPIO_GROUP_INTn_PORT_POL3_POL_24_Pos                  24                                                        /*!< GPIO_GROUP_INTn PORT_POL3: POL_24 Position */
#define GPIO_GROUP_INTn_PORT_POL3_POL_24_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_24_Pos)          /*!< GPIO_GROUP_INTn PORT_POL3: POL_24 Mask */
#define GPIO_GROUP_INTn_PORT_POL3_POL_25_Pos                  25                                                        /*!< GPIO_GROUP_INTn PORT_POL3: POL_25 Position */
#define GPIO_GROUP_INTn_PORT_POL3_POL_25_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_25_Pos)          /*!< GPIO_GROUP_INTn PORT_POL3: POL_25 Mask */
#define GPIO_GROUP_INTn_PORT_POL3_POL_26_Pos                  26                                                        /*!< GPIO_GROUP_INTn PORT_POL3: POL_26 Position */
#define GPIO_GROUP_INTn_PORT_POL3_POL_26_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_26_Pos)          /*!< GPIO_GROUP_INTn PORT_POL3: POL_26 Mask */
#define GPIO_GROUP_INTn_PORT_POL3_POL_27_Pos                  27                                                        /*!< GPIO_GROUP_INTn PORT_POL3: POL_27 Position */
#define GPIO_GROUP_INTn_PORT_POL3_POL_27_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_27_Pos)          /*!< GPIO_GROUP_INTn PORT_POL3: POL_27 Mask */
#define GPIO_GROUP_INTn_PORT_POL3_POL_28_Pos                  28                                                        /*!< GPIO_GROUP_INTn PORT_POL3: POL_28 Position */
#define GPIO_GROUP_INTn_PORT_POL3_POL_28_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_28_Pos)          /*!< GPIO_GROUP_INTn PORT_POL3: POL_28 Mask */
#define GPIO_GROUP_INTn_PORT_POL3_POL_29_Pos                  29                                                        /*!< GPIO_GROUP_INTn PORT_POL3: POL_29 Position */
#define GPIO_GROUP_INTn_PORT_POL3_POL_29_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_29_Pos)          /*!< GPIO_GROUP_INTn PORT_POL3: POL_29 Mask */
#define GPIO_GROUP_INTn_PORT_POL3_POL_30_Pos                  30                                                        /*!< GPIO_GROUP_INTn PORT_POL3: POL_30 Position */
#define GPIO_GROUP_INTn_PORT_POL3_POL_30_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_30_Pos)          /*!< GPIO_GROUP_INTn PORT_POL3: POL_30 Mask */
#define GPIO_GROUP_INTn_PORT_POL3_POL_31_Pos                  31                                                        /*!< GPIO_GROUP_INTn PORT_POL3: POL_31 Position */
#define GPIO_GROUP_INTn_PORT_POL3_POL_31_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_31_Pos)          /*!< GPIO_GROUP_INTn PORT_POL3: POL_31 Mask */

// --------------------------------  GPIO_GROUP_INTn_PORT_POL4  -----------------------------------
#define GPIO_GROUP_INTn_PORT_POL4_POL_0_Pos                   0                                                         /*!< GPIO_GROUP_INTn PORT_POL4: POL_0 Position */
#define GPIO_GROUP_INTn_PORT_POL4_POL_0_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_0_Pos)           /*!< GPIO_GROUP_INTn PORT_POL4: POL_0 Mask */
#define GPIO_GROUP_INTn_PORT_POL4_POL_1_Pos                   1                                                         /*!< GPIO_GROUP_INTn PORT_POL4: POL_1 Position */
#define GPIO_GROUP_INTn_PORT_POL4_POL_1_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_1_Pos)           /*!< GPIO_GROUP_INTn PORT_POL4: POL_1 Mask */
#define GPIO_GROUP_INTn_PORT_POL4_POL_2_Pos                   2                                                         /*!< GPIO_GROUP_INTn PORT_POL4: POL_2 Position */
#define GPIO_GROUP_INTn_PORT_POL4_POL_2_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_2_Pos)           /*!< GPIO_GROUP_INTn PORT_POL4: POL_2 Mask */
#define GPIO_GROUP_INTn_PORT_POL4_POL_3_Pos                   3                                                         /*!< GPIO_GROUP_INTn PORT_POL4: POL_3 Position */
#define GPIO_GROUP_INTn_PORT_POL4_POL_3_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_3_Pos)           /*!< GPIO_GROUP_INTn PORT_POL4: POL_3 Mask */
#define GPIO_GROUP_INTn_PORT_POL4_POL_4_Pos                   4                                                         /*!< GPIO_GROUP_INTn PORT_POL4: POL_4 Position */
#define GPIO_GROUP_INTn_PORT_POL4_POL_4_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_4_Pos)           /*!< GPIO_GROUP_INTn PORT_POL4: POL_4 Mask */
#define GPIO_GROUP_INTn_PORT_POL4_POL_5_Pos                   5                                                         /*!< GPIO_GROUP_INTn PORT_POL4: POL_5 Position */
#define GPIO_GROUP_INTn_PORT_POL4_POL_5_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_5_Pos)           /*!< GPIO_GROUP_INTn PORT_POL4: POL_5 Mask */
#define GPIO_GROUP_INTn_PORT_POL4_POL_6_Pos                   6                                                         /*!< GPIO_GROUP_INTn PORT_POL4: POL_6 Position */
#define GPIO_GROUP_INTn_PORT_POL4_POL_6_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_6_Pos)           /*!< GPIO_GROUP_INTn PORT_POL4: POL_6 Mask */
#define GPIO_GROUP_INTn_PORT_POL4_POL_7_Pos                   7                                                         /*!< GPIO_GROUP_INTn PORT_POL4: POL_7 Position */
#define GPIO_GROUP_INTn_PORT_POL4_POL_7_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_7_Pos)           /*!< GPIO_GROUP_INTn PORT_POL4: POL_7 Mask */
#define GPIO_GROUP_INTn_PORT_POL4_POL_8_Pos                   8                                                         /*!< GPIO_GROUP_INTn PORT_POL4: POL_8 Position */
#define GPIO_GROUP_INTn_PORT_POL4_POL_8_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_8_Pos)           /*!< GPIO_GROUP_INTn PORT_POL4: POL_8 Mask */
#define GPIO_GROUP_INTn_PORT_POL4_POL_9_Pos                   9                                                         /*!< GPIO_GROUP_INTn PORT_POL4: POL_9 Position */
#define GPIO_GROUP_INTn_PORT_POL4_POL_9_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_9_Pos)           /*!< GPIO_GROUP_INTn PORT_POL4: POL_9 Mask */
#define GPIO_GROUP_INTn_PORT_POL4_POL_10_Pos                  10                                                        /*!< GPIO_GROUP_INTn PORT_POL4: POL_10 Position */
#define GPIO_GROUP_INTn_PORT_POL4_POL_10_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_10_Pos)          /*!< GPIO_GROUP_INTn PORT_POL4: POL_10 Mask */
#define GPIO_GROUP_INTn_PORT_POL4_POL_11_Pos                  11                                                        /*!< GPIO_GROUP_INTn PORT_POL4: POL_11 Position */
#define GPIO_GROUP_INTn_PORT_POL4_POL_11_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_11_Pos)          /*!< GPIO_GROUP_INTn PORT_POL4: POL_11 Mask */
#define GPIO_GROUP_INTn_PORT_POL4_POL_12_Pos                  12                                                        /*!< GPIO_GROUP_INTn PORT_POL4: POL_12 Position */
#define GPIO_GROUP_INTn_PORT_POL4_POL_12_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_12_Pos)          /*!< GPIO_GROUP_INTn PORT_POL4: POL_12 Mask */
#define GPIO_GROUP_INTn_PORT_POL4_POL_13_Pos                  13                                                        /*!< GPIO_GROUP_INTn PORT_POL4: POL_13 Position */
#define GPIO_GROUP_INTn_PORT_POL4_POL_13_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_13_Pos)          /*!< GPIO_GROUP_INTn PORT_POL4: POL_13 Mask */
#define GPIO_GROUP_INTn_PORT_POL4_POL_14_Pos                  14                                                        /*!< GPIO_GROUP_INTn PORT_POL4: POL_14 Position */
#define GPIO_GROUP_INTn_PORT_POL4_POL_14_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_14_Pos)          /*!< GPIO_GROUP_INTn PORT_POL4: POL_14 Mask */
#define GPIO_GROUP_INTn_PORT_POL4_POL_15_Pos                  15                                                        /*!< GPIO_GROUP_INTn PORT_POL4: POL_15 Position */
#define GPIO_GROUP_INTn_PORT_POL4_POL_15_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_15_Pos)          /*!< GPIO_GROUP_INTn PORT_POL4: POL_15 Mask */
#define GPIO_GROUP_INTn_PORT_POL4_POL_16_Pos                  16                                                        /*!< GPIO_GROUP_INTn PORT_POL4: POL_16 Position */
#define GPIO_GROUP_INTn_PORT_POL4_POL_16_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_16_Pos)          /*!< GPIO_GROUP_INTn PORT_POL4: POL_16 Mask */
#define GPIO_GROUP_INTn_PORT_POL4_POL_17_Pos                  17                                                        /*!< GPIO_GROUP_INTn PORT_POL4: POL_17 Position */
#define GPIO_GROUP_INTn_PORT_POL4_POL_17_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_17_Pos)          /*!< GPIO_GROUP_INTn PORT_POL4: POL_17 Mask */
#define GPIO_GROUP_INTn_PORT_POL4_POL_18_Pos                  18                                                        /*!< GPIO_GROUP_INTn PORT_POL4: POL_18 Position */
#define GPIO_GROUP_INTn_PORT_POL4_POL_18_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_18_Pos)          /*!< GPIO_GROUP_INTn PORT_POL4: POL_18 Mask */
#define GPIO_GROUP_INTn_PORT_POL4_POL_19_Pos                  19                                                        /*!< GPIO_GROUP_INTn PORT_POL4: POL_19 Position */
#define GPIO_GROUP_INTn_PORT_POL4_POL_19_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_19_Pos)          /*!< GPIO_GROUP_INTn PORT_POL4: POL_19 Mask */
#define GPIO_GROUP_INTn_PORT_POL4_POL_20_Pos                  20                                                        /*!< GPIO_GROUP_INTn PORT_POL4: POL_20 Position */
#define GPIO_GROUP_INTn_PORT_POL4_POL_20_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_20_Pos)          /*!< GPIO_GROUP_INTn PORT_POL4: POL_20 Mask */
#define GPIO_GROUP_INTn_PORT_POL4_POL_21_Pos                  21                                                        /*!< GPIO_GROUP_INTn PORT_POL4: POL_21 Position */
#define GPIO_GROUP_INTn_PORT_POL4_POL_21_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_21_Pos)          /*!< GPIO_GROUP_INTn PORT_POL4: POL_21 Mask */
#define GPIO_GROUP_INTn_PORT_POL4_POL_22_Pos                  22                                                        /*!< GPIO_GROUP_INTn PORT_POL4: POL_22 Position */
#define GPIO_GROUP_INTn_PORT_POL4_POL_22_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_22_Pos)          /*!< GPIO_GROUP_INTn PORT_POL4: POL_22 Mask */
#define GPIO_GROUP_INTn_PORT_POL4_POL_23_Pos                  23                                                        /*!< GPIO_GROUP_INTn PORT_POL4: POL_23 Position */
#define GPIO_GROUP_INTn_PORT_POL4_POL_23_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_23_Pos)          /*!< GPIO_GROUP_INTn PORT_POL4: POL_23 Mask */
#define GPIO_GROUP_INTn_PORT_POL4_POL_24_Pos                  24                                                        /*!< GPIO_GROUP_INTn PORT_POL4: POL_24 Position */
#define GPIO_GROUP_INTn_PORT_POL4_POL_24_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_24_Pos)          /*!< GPIO_GROUP_INTn PORT_POL4: POL_24 Mask */
#define GPIO_GROUP_INTn_PORT_POL4_POL_25_Pos                  25                                                        /*!< GPIO_GROUP_INTn PORT_POL4: POL_25 Position */
#define GPIO_GROUP_INTn_PORT_POL4_POL_25_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_25_Pos)          /*!< GPIO_GROUP_INTn PORT_POL4: POL_25 Mask */
#define GPIO_GROUP_INTn_PORT_POL4_POL_26_Pos                  26                                                        /*!< GPIO_GROUP_INTn PORT_POL4: POL_26 Position */
#define GPIO_GROUP_INTn_PORT_POL4_POL_26_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_26_Pos)          /*!< GPIO_GROUP_INTn PORT_POL4: POL_26 Mask */
#define GPIO_GROUP_INTn_PORT_POL4_POL_27_Pos                  27                                                        /*!< GPIO_GROUP_INTn PORT_POL4: POL_27 Position */
#define GPIO_GROUP_INTn_PORT_POL4_POL_27_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_27_Pos)          /*!< GPIO_GROUP_INTn PORT_POL4: POL_27 Mask */
#define GPIO_GROUP_INTn_PORT_POL4_POL_28_Pos                  28                                                        /*!< GPIO_GROUP_INTn PORT_POL4: POL_28 Position */
#define GPIO_GROUP_INTn_PORT_POL4_POL_28_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_28_Pos)          /*!< GPIO_GROUP_INTn PORT_POL4: POL_28 Mask */
#define GPIO_GROUP_INTn_PORT_POL4_POL_29_Pos                  29                                                        /*!< GPIO_GROUP_INTn PORT_POL4: POL_29 Position */
#define GPIO_GROUP_INTn_PORT_POL4_POL_29_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_29_Pos)          /*!< GPIO_GROUP_INTn PORT_POL4: POL_29 Mask */
#define GPIO_GROUP_INTn_PORT_POL4_POL_30_Pos                  30                                                        /*!< GPIO_GROUP_INTn PORT_POL4: POL_30 Position */
#define GPIO_GROUP_INTn_PORT_POL4_POL_30_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_30_Pos)          /*!< GPIO_GROUP_INTn PORT_POL4: POL_30 Mask */
#define GPIO_GROUP_INTn_PORT_POL4_POL_31_Pos                  31                                                        /*!< GPIO_GROUP_INTn PORT_POL4: POL_31 Position */
#define GPIO_GROUP_INTn_PORT_POL4_POL_31_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_31_Pos)          /*!< GPIO_GROUP_INTn PORT_POL4: POL_31 Mask */

// --------------------------------  GPIO_GROUP_INTn_PORT_POL5  -----------------------------------
#define GPIO_GROUP_INTn_PORT_POL5_POL_0_Pos                   0                                                         /*!< GPIO_GROUP_INTn PORT_POL5: POL_0 Position */
#define GPIO_GROUP_INTn_PORT_POL5_POL_0_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_0_Pos)           /*!< GPIO_GROUP_INTn PORT_POL5: POL_0 Mask */
#define GPIO_GROUP_INTn_PORT_POL5_POL_1_Pos                   1                                                         /*!< GPIO_GROUP_INTn PORT_POL5: POL_1 Position */
#define GPIO_GROUP_INTn_PORT_POL5_POL_1_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_1_Pos)           /*!< GPIO_GROUP_INTn PORT_POL5: POL_1 Mask */
#define GPIO_GROUP_INTn_PORT_POL5_POL_2_Pos                   2                                                         /*!< GPIO_GROUP_INTn PORT_POL5: POL_2 Position */
#define GPIO_GROUP_INTn_PORT_POL5_POL_2_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_2_Pos)           /*!< GPIO_GROUP_INTn PORT_POL5: POL_2 Mask */
#define GPIO_GROUP_INTn_PORT_POL5_POL_3_Pos                   3                                                         /*!< GPIO_GROUP_INTn PORT_POL5: POL_3 Position */
#define GPIO_GROUP_INTn_PORT_POL5_POL_3_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_3_Pos)           /*!< GPIO_GROUP_INTn PORT_POL5: POL_3 Mask */
#define GPIO_GROUP_INTn_PORT_POL5_POL_4_Pos                   4                                                         /*!< GPIO_GROUP_INTn PORT_POL5: POL_4 Position */
#define GPIO_GROUP_INTn_PORT_POL5_POL_4_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_4_Pos)           /*!< GPIO_GROUP_INTn PORT_POL5: POL_4 Mask */
#define GPIO_GROUP_INTn_PORT_POL5_POL_5_Pos                   5                                                         /*!< GPIO_GROUP_INTn PORT_POL5: POL_5 Position */
#define GPIO_GROUP_INTn_PORT_POL5_POL_5_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_5_Pos)           /*!< GPIO_GROUP_INTn PORT_POL5: POL_5 Mask */
#define GPIO_GROUP_INTn_PORT_POL5_POL_6_Pos                   6                                                         /*!< GPIO_GROUP_INTn PORT_POL5: POL_6 Position */
#define GPIO_GROUP_INTn_PORT_POL5_POL_6_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_6_Pos)           /*!< GPIO_GROUP_INTn PORT_POL5: POL_6 Mask */
#define GPIO_GROUP_INTn_PORT_POL5_POL_7_Pos                   7                                                         /*!< GPIO_GROUP_INTn PORT_POL5: POL_7 Position */
#define GPIO_GROUP_INTn_PORT_POL5_POL_7_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_7_Pos)           /*!< GPIO_GROUP_INTn PORT_POL5: POL_7 Mask */
#define GPIO_GROUP_INTn_PORT_POL5_POL_8_Pos                   8                                                         /*!< GPIO_GROUP_INTn PORT_POL5: POL_8 Position */
#define GPIO_GROUP_INTn_PORT_POL5_POL_8_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_8_Pos)           /*!< GPIO_GROUP_INTn PORT_POL5: POL_8 Mask */
#define GPIO_GROUP_INTn_PORT_POL5_POL_9_Pos                   9                                                         /*!< GPIO_GROUP_INTn PORT_POL5: POL_9 Position */
#define GPIO_GROUP_INTn_PORT_POL5_POL_9_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_9_Pos)           /*!< GPIO_GROUP_INTn PORT_POL5: POL_9 Mask */
#define GPIO_GROUP_INTn_PORT_POL5_POL_10_Pos                  10                                                        /*!< GPIO_GROUP_INTn PORT_POL5: POL_10 Position */
#define GPIO_GROUP_INTn_PORT_POL5_POL_10_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_10_Pos)          /*!< GPIO_GROUP_INTn PORT_POL5: POL_10 Mask */
#define GPIO_GROUP_INTn_PORT_POL5_POL_11_Pos                  11                                                        /*!< GPIO_GROUP_INTn PORT_POL5: POL_11 Position */
#define GPIO_GROUP_INTn_PORT_POL5_POL_11_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_11_Pos)          /*!< GPIO_GROUP_INTn PORT_POL5: POL_11 Mask */
#define GPIO_GROUP_INTn_PORT_POL5_POL_12_Pos                  12                                                        /*!< GPIO_GROUP_INTn PORT_POL5: POL_12 Position */
#define GPIO_GROUP_INTn_PORT_POL5_POL_12_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_12_Pos)          /*!< GPIO_GROUP_INTn PORT_POL5: POL_12 Mask */
#define GPIO_GROUP_INTn_PORT_POL5_POL_13_Pos                  13                                                        /*!< GPIO_GROUP_INTn PORT_POL5: POL_13 Position */
#define GPIO_GROUP_INTn_PORT_POL5_POL_13_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_13_Pos)          /*!< GPIO_GROUP_INTn PORT_POL5: POL_13 Mask */
#define GPIO_GROUP_INTn_PORT_POL5_POL_14_Pos                  14                                                        /*!< GPIO_GROUP_INTn PORT_POL5: POL_14 Position */
#define GPIO_GROUP_INTn_PORT_POL5_POL_14_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_14_Pos)          /*!< GPIO_GROUP_INTn PORT_POL5: POL_14 Mask */
#define GPIO_GROUP_INTn_PORT_POL5_POL_15_Pos                  15                                                        /*!< GPIO_GROUP_INTn PORT_POL5: POL_15 Position */
#define GPIO_GROUP_INTn_PORT_POL5_POL_15_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_15_Pos)          /*!< GPIO_GROUP_INTn PORT_POL5: POL_15 Mask */
#define GPIO_GROUP_INTn_PORT_POL5_POL_16_Pos                  16                                                        /*!< GPIO_GROUP_INTn PORT_POL5: POL_16 Position */
#define GPIO_GROUP_INTn_PORT_POL5_POL_16_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_16_Pos)          /*!< GPIO_GROUP_INTn PORT_POL5: POL_16 Mask */
#define GPIO_GROUP_INTn_PORT_POL5_POL_17_Pos                  17                                                        /*!< GPIO_GROUP_INTn PORT_POL5: POL_17 Position */
#define GPIO_GROUP_INTn_PORT_POL5_POL_17_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_17_Pos)          /*!< GPIO_GROUP_INTn PORT_POL5: POL_17 Mask */
#define GPIO_GROUP_INTn_PORT_POL5_POL_18_Pos                  18                                                        /*!< GPIO_GROUP_INTn PORT_POL5: POL_18 Position */
#define GPIO_GROUP_INTn_PORT_POL5_POL_18_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_18_Pos)          /*!< GPIO_GROUP_INTn PORT_POL5: POL_18 Mask */
#define GPIO_GROUP_INTn_PORT_POL5_POL_19_Pos                  19                                                        /*!< GPIO_GROUP_INTn PORT_POL5: POL_19 Position */
#define GPIO_GROUP_INTn_PORT_POL5_POL_19_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_19_Pos)          /*!< GPIO_GROUP_INTn PORT_POL5: POL_19 Mask */
#define GPIO_GROUP_INTn_PORT_POL5_POL_20_Pos                  20                                                        /*!< GPIO_GROUP_INTn PORT_POL5: POL_20 Position */
#define GPIO_GROUP_INTn_PORT_POL5_POL_20_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_20_Pos)          /*!< GPIO_GROUP_INTn PORT_POL5: POL_20 Mask */
#define GPIO_GROUP_INTn_PORT_POL5_POL_21_Pos                  21                                                        /*!< GPIO_GROUP_INTn PORT_POL5: POL_21 Position */
#define GPIO_GROUP_INTn_PORT_POL5_POL_21_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_21_Pos)          /*!< GPIO_GROUP_INTn PORT_POL5: POL_21 Mask */
#define GPIO_GROUP_INTn_PORT_POL5_POL_22_Pos                  22                                                        /*!< GPIO_GROUP_INTn PORT_POL5: POL_22 Position */
#define GPIO_GROUP_INTn_PORT_POL5_POL_22_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_22_Pos)          /*!< GPIO_GROUP_INTn PORT_POL5: POL_22 Mask */
#define GPIO_GROUP_INTn_PORT_POL5_POL_23_Pos                  23                                                        /*!< GPIO_GROUP_INTn PORT_POL5: POL_23 Position */
#define GPIO_GROUP_INTn_PORT_POL5_POL_23_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_23_Pos)          /*!< GPIO_GROUP_INTn PORT_POL5: POL_23 Mask */
#define GPIO_GROUP_INTn_PORT_POL5_POL_24_Pos                  24                                                        /*!< GPIO_GROUP_INTn PORT_POL5: POL_24 Position */
#define GPIO_GROUP_INTn_PORT_POL5_POL_24_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_24_Pos)          /*!< GPIO_GROUP_INTn PORT_POL5: POL_24 Mask */
#define GPIO_GROUP_INTn_PORT_POL5_POL_25_Pos                  25                                                        /*!< GPIO_GROUP_INTn PORT_POL5: POL_25 Position */
#define GPIO_GROUP_INTn_PORT_POL5_POL_25_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_25_Pos)          /*!< GPIO_GROUP_INTn PORT_POL5: POL_25 Mask */
#define GPIO_GROUP_INTn_PORT_POL5_POL_26_Pos                  26                                                        /*!< GPIO_GROUP_INTn PORT_POL5: POL_26 Position */
#define GPIO_GROUP_INTn_PORT_POL5_POL_26_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_26_Pos)          /*!< GPIO_GROUP_INTn PORT_POL5: POL_26 Mask */
#define GPIO_GROUP_INTn_PORT_POL5_POL_27_Pos                  27                                                        /*!< GPIO_GROUP_INTn PORT_POL5: POL_27 Position */
#define GPIO_GROUP_INTn_PORT_POL5_POL_27_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_27_Pos)          /*!< GPIO_GROUP_INTn PORT_POL5: POL_27 Mask */
#define GPIO_GROUP_INTn_PORT_POL5_POL_28_Pos                  28                                                        /*!< GPIO_GROUP_INTn PORT_POL5: POL_28 Position */
#define GPIO_GROUP_INTn_PORT_POL5_POL_28_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_28_Pos)          /*!< GPIO_GROUP_INTn PORT_POL5: POL_28 Mask */
#define GPIO_GROUP_INTn_PORT_POL5_POL_29_Pos                  29                                                        /*!< GPIO_GROUP_INTn PORT_POL5: POL_29 Position */
#define GPIO_GROUP_INTn_PORT_POL5_POL_29_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_29_Pos)          /*!< GPIO_GROUP_INTn PORT_POL5: POL_29 Mask */
#define GPIO_GROUP_INTn_PORT_POL5_POL_30_Pos                  30                                                        /*!< GPIO_GROUP_INTn PORT_POL5: POL_30 Position */
#define GPIO_GROUP_INTn_PORT_POL5_POL_30_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_30_Pos)          /*!< GPIO_GROUP_INTn PORT_POL5: POL_30 Mask */
#define GPIO_GROUP_INTn_PORT_POL5_POL_31_Pos                  31                                                        /*!< GPIO_GROUP_INTn PORT_POL5: POL_31 Position */
#define GPIO_GROUP_INTn_PORT_POL5_POL_31_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_31_Pos)          /*!< GPIO_GROUP_INTn PORT_POL5: POL_31 Mask */

// --------------------------------  GPIO_GROUP_INTn_PORT_POL6  -----------------------------------
#define GPIO_GROUP_INTn_PORT_POL6_POL_0_Pos                   0                                                         /*!< GPIO_GROUP_INTn PORT_POL6: POL_0 Position */
#define GPIO_GROUP_INTn_PORT_POL6_POL_0_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_0_Pos)           /*!< GPIO_GROUP_INTn PORT_POL6: POL_0 Mask */
#define GPIO_GROUP_INTn_PORT_POL6_POL_1_Pos                   1                                                         /*!< GPIO_GROUP_INTn PORT_POL6: POL_1 Position */
#define GPIO_GROUP_INTn_PORT_POL6_POL_1_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_1_Pos)           /*!< GPIO_GROUP_INTn PORT_POL6: POL_1 Mask */
#define GPIO_GROUP_INTn_PORT_POL6_POL_2_Pos                   2                                                         /*!< GPIO_GROUP_INTn PORT_POL6: POL_2 Position */
#define GPIO_GROUP_INTn_PORT_POL6_POL_2_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_2_Pos)           /*!< GPIO_GROUP_INTn PORT_POL6: POL_2 Mask */
#define GPIO_GROUP_INTn_PORT_POL6_POL_3_Pos                   3                                                         /*!< GPIO_GROUP_INTn PORT_POL6: POL_3 Position */
#define GPIO_GROUP_INTn_PORT_POL6_POL_3_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_3_Pos)           /*!< GPIO_GROUP_INTn PORT_POL6: POL_3 Mask */
#define GPIO_GROUP_INTn_PORT_POL6_POL_4_Pos                   4                                                         /*!< GPIO_GROUP_INTn PORT_POL6: POL_4 Position */
#define GPIO_GROUP_INTn_PORT_POL6_POL_4_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_4_Pos)           /*!< GPIO_GROUP_INTn PORT_POL6: POL_4 Mask */
#define GPIO_GROUP_INTn_PORT_POL6_POL_5_Pos                   5                                                         /*!< GPIO_GROUP_INTn PORT_POL6: POL_5 Position */
#define GPIO_GROUP_INTn_PORT_POL6_POL_5_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_5_Pos)           /*!< GPIO_GROUP_INTn PORT_POL6: POL_5 Mask */
#define GPIO_GROUP_INTn_PORT_POL6_POL_6_Pos                   6                                                         /*!< GPIO_GROUP_INTn PORT_POL6: POL_6 Position */
#define GPIO_GROUP_INTn_PORT_POL6_POL_6_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_6_Pos)           /*!< GPIO_GROUP_INTn PORT_POL6: POL_6 Mask */
#define GPIO_GROUP_INTn_PORT_POL6_POL_7_Pos                   7                                                         /*!< GPIO_GROUP_INTn PORT_POL6: POL_7 Position */
#define GPIO_GROUP_INTn_PORT_POL6_POL_7_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_7_Pos)           /*!< GPIO_GROUP_INTn PORT_POL6: POL_7 Mask */
#define GPIO_GROUP_INTn_PORT_POL6_POL_8_Pos                   8                                                         /*!< GPIO_GROUP_INTn PORT_POL6: POL_8 Position */
#define GPIO_GROUP_INTn_PORT_POL6_POL_8_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_8_Pos)           /*!< GPIO_GROUP_INTn PORT_POL6: POL_8 Mask */
#define GPIO_GROUP_INTn_PORT_POL6_POL_9_Pos                   9                                                         /*!< GPIO_GROUP_INTn PORT_POL6: POL_9 Position */
#define GPIO_GROUP_INTn_PORT_POL6_POL_9_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_9_Pos)           /*!< GPIO_GROUP_INTn PORT_POL6: POL_9 Mask */
#define GPIO_GROUP_INTn_PORT_POL6_POL_10_Pos                  10                                                        /*!< GPIO_GROUP_INTn PORT_POL6: POL_10 Position */
#define GPIO_GROUP_INTn_PORT_POL6_POL_10_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_10_Pos)          /*!< GPIO_GROUP_INTn PORT_POL6: POL_10 Mask */
#define GPIO_GROUP_INTn_PORT_POL6_POL_11_Pos                  11                                                        /*!< GPIO_GROUP_INTn PORT_POL6: POL_11 Position */
#define GPIO_GROUP_INTn_PORT_POL6_POL_11_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_11_Pos)          /*!< GPIO_GROUP_INTn PORT_POL6: POL_11 Mask */
#define GPIO_GROUP_INTn_PORT_POL6_POL_12_Pos                  12                                                        /*!< GPIO_GROUP_INTn PORT_POL6: POL_12 Position */
#define GPIO_GROUP_INTn_PORT_POL6_POL_12_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_12_Pos)          /*!< GPIO_GROUP_INTn PORT_POL6: POL_12 Mask */
#define GPIO_GROUP_INTn_PORT_POL6_POL_13_Pos                  13                                                        /*!< GPIO_GROUP_INTn PORT_POL6: POL_13 Position */
#define GPIO_GROUP_INTn_PORT_POL6_POL_13_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_13_Pos)          /*!< GPIO_GROUP_INTn PORT_POL6: POL_13 Mask */
#define GPIO_GROUP_INTn_PORT_POL6_POL_14_Pos                  14                                                        /*!< GPIO_GROUP_INTn PORT_POL6: POL_14 Position */
#define GPIO_GROUP_INTn_PORT_POL6_POL_14_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_14_Pos)          /*!< GPIO_GROUP_INTn PORT_POL6: POL_14 Mask */
#define GPIO_GROUP_INTn_PORT_POL6_POL_15_Pos                  15                                                        /*!< GPIO_GROUP_INTn PORT_POL6: POL_15 Position */
#define GPIO_GROUP_INTn_PORT_POL6_POL_15_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_15_Pos)          /*!< GPIO_GROUP_INTn PORT_POL6: POL_15 Mask */
#define GPIO_GROUP_INTn_PORT_POL6_POL_16_Pos                  16                                                        /*!< GPIO_GROUP_INTn PORT_POL6: POL_16 Position */
#define GPIO_GROUP_INTn_PORT_POL6_POL_16_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_16_Pos)          /*!< GPIO_GROUP_INTn PORT_POL6: POL_16 Mask */
#define GPIO_GROUP_INTn_PORT_POL6_POL_17_Pos                  17                                                        /*!< GPIO_GROUP_INTn PORT_POL6: POL_17 Position */
#define GPIO_GROUP_INTn_PORT_POL6_POL_17_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_17_Pos)          /*!< GPIO_GROUP_INTn PORT_POL6: POL_17 Mask */
#define GPIO_GROUP_INTn_PORT_POL6_POL_18_Pos                  18                                                        /*!< GPIO_GROUP_INTn PORT_POL6: POL_18 Position */
#define GPIO_GROUP_INTn_PORT_POL6_POL_18_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_18_Pos)          /*!< GPIO_GROUP_INTn PORT_POL6: POL_18 Mask */
#define GPIO_GROUP_INTn_PORT_POL6_POL_19_Pos                  19                                                        /*!< GPIO_GROUP_INTn PORT_POL6: POL_19 Position */
#define GPIO_GROUP_INTn_PORT_POL6_POL_19_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_19_Pos)          /*!< GPIO_GROUP_INTn PORT_POL6: POL_19 Mask */
#define GPIO_GROUP_INTn_PORT_POL6_POL_20_Pos                  20                                                        /*!< GPIO_GROUP_INTn PORT_POL6: POL_20 Position */
#define GPIO_GROUP_INTn_PORT_POL6_POL_20_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_20_Pos)          /*!< GPIO_GROUP_INTn PORT_POL6: POL_20 Mask */
#define GPIO_GROUP_INTn_PORT_POL6_POL_21_Pos                  21                                                        /*!< GPIO_GROUP_INTn PORT_POL6: POL_21 Position */
#define GPIO_GROUP_INTn_PORT_POL6_POL_21_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_21_Pos)          /*!< GPIO_GROUP_INTn PORT_POL6: POL_21 Mask */
#define GPIO_GROUP_INTn_PORT_POL6_POL_22_Pos                  22                                                        /*!< GPIO_GROUP_INTn PORT_POL6: POL_22 Position */
#define GPIO_GROUP_INTn_PORT_POL6_POL_22_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_22_Pos)          /*!< GPIO_GROUP_INTn PORT_POL6: POL_22 Mask */
#define GPIO_GROUP_INTn_PORT_POL6_POL_23_Pos                  23                                                        /*!< GPIO_GROUP_INTn PORT_POL6: POL_23 Position */
#define GPIO_GROUP_INTn_PORT_POL6_POL_23_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_23_Pos)          /*!< GPIO_GROUP_INTn PORT_POL6: POL_23 Mask */
#define GPIO_GROUP_INTn_PORT_POL6_POL_24_Pos                  24                                                        /*!< GPIO_GROUP_INTn PORT_POL6: POL_24 Position */
#define GPIO_GROUP_INTn_PORT_POL6_POL_24_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_24_Pos)          /*!< GPIO_GROUP_INTn PORT_POL6: POL_24 Mask */
#define GPIO_GROUP_INTn_PORT_POL6_POL_25_Pos                  25                                                        /*!< GPIO_GROUP_INTn PORT_POL6: POL_25 Position */
#define GPIO_GROUP_INTn_PORT_POL6_POL_25_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_25_Pos)          /*!< GPIO_GROUP_INTn PORT_POL6: POL_25 Mask */
#define GPIO_GROUP_INTn_PORT_POL6_POL_26_Pos                  26                                                        /*!< GPIO_GROUP_INTn PORT_POL6: POL_26 Position */
#define GPIO_GROUP_INTn_PORT_POL6_POL_26_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_26_Pos)          /*!< GPIO_GROUP_INTn PORT_POL6: POL_26 Mask */
#define GPIO_GROUP_INTn_PORT_POL6_POL_27_Pos                  27                                                        /*!< GPIO_GROUP_INTn PORT_POL6: POL_27 Position */
#define GPIO_GROUP_INTn_PORT_POL6_POL_27_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_27_Pos)          /*!< GPIO_GROUP_INTn PORT_POL6: POL_27 Mask */
#define GPIO_GROUP_INTn_PORT_POL6_POL_28_Pos                  28                                                        /*!< GPIO_GROUP_INTn PORT_POL6: POL_28 Position */
#define GPIO_GROUP_INTn_PORT_POL6_POL_28_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_28_Pos)          /*!< GPIO_GROUP_INTn PORT_POL6: POL_28 Mask */
#define GPIO_GROUP_INTn_PORT_POL6_POL_29_Pos                  29                                                        /*!< GPIO_GROUP_INTn PORT_POL6: POL_29 Position */
#define GPIO_GROUP_INTn_PORT_POL6_POL_29_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_29_Pos)          /*!< GPIO_GROUP_INTn PORT_POL6: POL_29 Mask */
#define GPIO_GROUP_INTn_PORT_POL6_POL_30_Pos                  30                                                        /*!< GPIO_GROUP_INTn PORT_POL6: POL_30 Position */
#define GPIO_GROUP_INTn_PORT_POL6_POL_30_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_30_Pos)          /*!< GPIO_GROUP_INTn PORT_POL6: POL_30 Mask */
#define GPIO_GROUP_INTn_PORT_POL6_POL_31_Pos                  31                                                        /*!< GPIO_GROUP_INTn PORT_POL6: POL_31 Position */
#define GPIO_GROUP_INTn_PORT_POL6_POL_31_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_31_Pos)          /*!< GPIO_GROUP_INTn PORT_POL6: POL_31 Mask */

// --------------------------------  GPIO_GROUP_INTn_PORT_POL7  -----------------------------------
#define GPIO_GROUP_INTn_PORT_POL7_POL_0_Pos                   0                                                         /*!< GPIO_GROUP_INTn PORT_POL7: POL_0 Position */
#define GPIO_GROUP_INTn_PORT_POL7_POL_0_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_0_Pos)           /*!< GPIO_GROUP_INTn PORT_POL7: POL_0 Mask */
#define GPIO_GROUP_INTn_PORT_POL7_POL_1_Pos                   1                                                         /*!< GPIO_GROUP_INTn PORT_POL7: POL_1 Position */
#define GPIO_GROUP_INTn_PORT_POL7_POL_1_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_1_Pos)           /*!< GPIO_GROUP_INTn PORT_POL7: POL_1 Mask */
#define GPIO_GROUP_INTn_PORT_POL7_POL_2_Pos                   2                                                         /*!< GPIO_GROUP_INTn PORT_POL7: POL_2 Position */
#define GPIO_GROUP_INTn_PORT_POL7_POL_2_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_2_Pos)           /*!< GPIO_GROUP_INTn PORT_POL7: POL_2 Mask */
#define GPIO_GROUP_INTn_PORT_POL7_POL_3_Pos                   3                                                         /*!< GPIO_GROUP_INTn PORT_POL7: POL_3 Position */
#define GPIO_GROUP_INTn_PORT_POL7_POL_3_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_3_Pos)           /*!< GPIO_GROUP_INTn PORT_POL7: POL_3 Mask */
#define GPIO_GROUP_INTn_PORT_POL7_POL_4_Pos                   4                                                         /*!< GPIO_GROUP_INTn PORT_POL7: POL_4 Position */
#define GPIO_GROUP_INTn_PORT_POL7_POL_4_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_4_Pos)           /*!< GPIO_GROUP_INTn PORT_POL7: POL_4 Mask */
#define GPIO_GROUP_INTn_PORT_POL7_POL_5_Pos                   5                                                         /*!< GPIO_GROUP_INTn PORT_POL7: POL_5 Position */
#define GPIO_GROUP_INTn_PORT_POL7_POL_5_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_5_Pos)           /*!< GPIO_GROUP_INTn PORT_POL7: POL_5 Mask */
#define GPIO_GROUP_INTn_PORT_POL7_POL_6_Pos                   6                                                         /*!< GPIO_GROUP_INTn PORT_POL7: POL_6 Position */
#define GPIO_GROUP_INTn_PORT_POL7_POL_6_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_6_Pos)           /*!< GPIO_GROUP_INTn PORT_POL7: POL_6 Mask */
#define GPIO_GROUP_INTn_PORT_POL7_POL_7_Pos                   7                                                         /*!< GPIO_GROUP_INTn PORT_POL7: POL_7 Position */
#define GPIO_GROUP_INTn_PORT_POL7_POL_7_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_7_Pos)           /*!< GPIO_GROUP_INTn PORT_POL7: POL_7 Mask */
#define GPIO_GROUP_INTn_PORT_POL7_POL_8_Pos                   8                                                         /*!< GPIO_GROUP_INTn PORT_POL7: POL_8 Position */
#define GPIO_GROUP_INTn_PORT_POL7_POL_8_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_8_Pos)           /*!< GPIO_GROUP_INTn PORT_POL7: POL_8 Mask */
#define GPIO_GROUP_INTn_PORT_POL7_POL_9_Pos                   9                                                         /*!< GPIO_GROUP_INTn PORT_POL7: POL_9 Position */
#define GPIO_GROUP_INTn_PORT_POL7_POL_9_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_9_Pos)           /*!< GPIO_GROUP_INTn PORT_POL7: POL_9 Mask */
#define GPIO_GROUP_INTn_PORT_POL7_POL_10_Pos                  10                                                        /*!< GPIO_GROUP_INTn PORT_POL7: POL_10 Position */
#define GPIO_GROUP_INTn_PORT_POL7_POL_10_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_10_Pos)          /*!< GPIO_GROUP_INTn PORT_POL7: POL_10 Mask */
#define GPIO_GROUP_INTn_PORT_POL7_POL_11_Pos                  11                                                        /*!< GPIO_GROUP_INTn PORT_POL7: POL_11 Position */
#define GPIO_GROUP_INTn_PORT_POL7_POL_11_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_11_Pos)          /*!< GPIO_GROUP_INTn PORT_POL7: POL_11 Mask */
#define GPIO_GROUP_INTn_PORT_POL7_POL_12_Pos                  12                                                        /*!< GPIO_GROUP_INTn PORT_POL7: POL_12 Position */
#define GPIO_GROUP_INTn_PORT_POL7_POL_12_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_12_Pos)          /*!< GPIO_GROUP_INTn PORT_POL7: POL_12 Mask */
#define GPIO_GROUP_INTn_PORT_POL7_POL_13_Pos                  13                                                        /*!< GPIO_GROUP_INTn PORT_POL7: POL_13 Position */
#define GPIO_GROUP_INTn_PORT_POL7_POL_13_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_13_Pos)          /*!< GPIO_GROUP_INTn PORT_POL7: POL_13 Mask */
#define GPIO_GROUP_INTn_PORT_POL7_POL_14_Pos                  14                                                        /*!< GPIO_GROUP_INTn PORT_POL7: POL_14 Position */
#define GPIO_GROUP_INTn_PORT_POL7_POL_14_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_14_Pos)          /*!< GPIO_GROUP_INTn PORT_POL7: POL_14 Mask */
#define GPIO_GROUP_INTn_PORT_POL7_POL_15_Pos                  15                                                        /*!< GPIO_GROUP_INTn PORT_POL7: POL_15 Position */
#define GPIO_GROUP_INTn_PORT_POL7_POL_15_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_15_Pos)          /*!< GPIO_GROUP_INTn PORT_POL7: POL_15 Mask */
#define GPIO_GROUP_INTn_PORT_POL7_POL_16_Pos                  16                                                        /*!< GPIO_GROUP_INTn PORT_POL7: POL_16 Position */
#define GPIO_GROUP_INTn_PORT_POL7_POL_16_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_16_Pos)          /*!< GPIO_GROUP_INTn PORT_POL7: POL_16 Mask */
#define GPIO_GROUP_INTn_PORT_POL7_POL_17_Pos                  17                                                        /*!< GPIO_GROUP_INTn PORT_POL7: POL_17 Position */
#define GPIO_GROUP_INTn_PORT_POL7_POL_17_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_17_Pos)          /*!< GPIO_GROUP_INTn PORT_POL7: POL_17 Mask */
#define GPIO_GROUP_INTn_PORT_POL7_POL_18_Pos                  18                                                        /*!< GPIO_GROUP_INTn PORT_POL7: POL_18 Position */
#define GPIO_GROUP_INTn_PORT_POL7_POL_18_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_18_Pos)          /*!< GPIO_GROUP_INTn PORT_POL7: POL_18 Mask */
#define GPIO_GROUP_INTn_PORT_POL7_POL_19_Pos                  19                                                        /*!< GPIO_GROUP_INTn PORT_POL7: POL_19 Position */
#define GPIO_GROUP_INTn_PORT_POL7_POL_19_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_19_Pos)          /*!< GPIO_GROUP_INTn PORT_POL7: POL_19 Mask */
#define GPIO_GROUP_INTn_PORT_POL7_POL_20_Pos                  20                                                        /*!< GPIO_GROUP_INTn PORT_POL7: POL_20 Position */
#define GPIO_GROUP_INTn_PORT_POL7_POL_20_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_20_Pos)          /*!< GPIO_GROUP_INTn PORT_POL7: POL_20 Mask */
#define GPIO_GROUP_INTn_PORT_POL7_POL_21_Pos                  21                                                        /*!< GPIO_GROUP_INTn PORT_POL7: POL_21 Position */
#define GPIO_GROUP_INTn_PORT_POL7_POL_21_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_21_Pos)          /*!< GPIO_GROUP_INTn PORT_POL7: POL_21 Mask */
#define GPIO_GROUP_INTn_PORT_POL7_POL_22_Pos                  22                                                        /*!< GPIO_GROUP_INTn PORT_POL7: POL_22 Position */
#define GPIO_GROUP_INTn_PORT_POL7_POL_22_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_22_Pos)          /*!< GPIO_GROUP_INTn PORT_POL7: POL_22 Mask */
#define GPIO_GROUP_INTn_PORT_POL7_POL_23_Pos                  23                                                        /*!< GPIO_GROUP_INTn PORT_POL7: POL_23 Position */
#define GPIO_GROUP_INTn_PORT_POL7_POL_23_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_23_Pos)          /*!< GPIO_GROUP_INTn PORT_POL7: POL_23 Mask */
#define GPIO_GROUP_INTn_PORT_POL7_POL_24_Pos                  24                                                        /*!< GPIO_GROUP_INTn PORT_POL7: POL_24 Position */
#define GPIO_GROUP_INTn_PORT_POL7_POL_24_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_24_Pos)          /*!< GPIO_GROUP_INTn PORT_POL7: POL_24 Mask */
#define GPIO_GROUP_INTn_PORT_POL7_POL_25_Pos                  25                                                        /*!< GPIO_GROUP_INTn PORT_POL7: POL_25 Position */
#define GPIO_GROUP_INTn_PORT_POL7_POL_25_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_25_Pos)          /*!< GPIO_GROUP_INTn PORT_POL7: POL_25 Mask */
#define GPIO_GROUP_INTn_PORT_POL7_POL_26_Pos                  26                                                        /*!< GPIO_GROUP_INTn PORT_POL7: POL_26 Position */
#define GPIO_GROUP_INTn_PORT_POL7_POL_26_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_26_Pos)          /*!< GPIO_GROUP_INTn PORT_POL7: POL_26 Mask */
#define GPIO_GROUP_INTn_PORT_POL7_POL_27_Pos                  27                                                        /*!< GPIO_GROUP_INTn PORT_POL7: POL_27 Position */
#define GPIO_GROUP_INTn_PORT_POL7_POL_27_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_27_Pos)          /*!< GPIO_GROUP_INTn PORT_POL7: POL_27 Mask */
#define GPIO_GROUP_INTn_PORT_POL7_POL_28_Pos                  28                                                        /*!< GPIO_GROUP_INTn PORT_POL7: POL_28 Position */
#define GPIO_GROUP_INTn_PORT_POL7_POL_28_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_28_Pos)          /*!< GPIO_GROUP_INTn PORT_POL7: POL_28 Mask */
#define GPIO_GROUP_INTn_PORT_POL7_POL_29_Pos                  29                                                        /*!< GPIO_GROUP_INTn PORT_POL7: POL_29 Position */
#define GPIO_GROUP_INTn_PORT_POL7_POL_29_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_29_Pos)          /*!< GPIO_GROUP_INTn PORT_POL7: POL_29 Mask */
#define GPIO_GROUP_INTn_PORT_POL7_POL_30_Pos                  30                                                        /*!< GPIO_GROUP_INTn PORT_POL7: POL_30 Position */
#define GPIO_GROUP_INTn_PORT_POL7_POL_30_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_30_Pos)          /*!< GPIO_GROUP_INTn PORT_POL7: POL_30 Mask */
#define GPIO_GROUP_INTn_PORT_POL7_POL_31_Pos                  31                                                        /*!< GPIO_GROUP_INTn PORT_POL7: POL_31 Position */
#define GPIO_GROUP_INTn_PORT_POL7_POL_31_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_31_Pos)          /*!< GPIO_GROUP_INTn PORT_POL7: POL_31 Mask */

// --------------------------------  GPIO_GROUP_INTn_PORT_ENA0  -----------------------------------
#define GPIO_GROUP_INTn_PORT_ENA0_ENA_0_Pos                   0                                                         /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_0 Position */
#define GPIO_GROUP_INTn_PORT_ENA0_ENA_0_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_0_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_0 Mask */
#define GPIO_GROUP_INTn_PORT_ENA0_ENA_1_Pos                   1                                                         /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_1 Position */
#define GPIO_GROUP_INTn_PORT_ENA0_ENA_1_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_1_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_1 Mask */
#define GPIO_GROUP_INTn_PORT_ENA0_ENA_2_Pos                   2                                                         /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_2 Position */
#define GPIO_GROUP_INTn_PORT_ENA0_ENA_2_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_2_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_2 Mask */
#define GPIO_GROUP_INTn_PORT_ENA0_ENA_3_Pos                   3                                                         /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_3 Position */
#define GPIO_GROUP_INTn_PORT_ENA0_ENA_3_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_3_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_3 Mask */
#define GPIO_GROUP_INTn_PORT_ENA0_ENA_4_Pos                   4                                                         /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_4 Position */
#define GPIO_GROUP_INTn_PORT_ENA0_ENA_4_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_4_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_4 Mask */
#define GPIO_GROUP_INTn_PORT_ENA0_ENA_5_Pos                   5                                                         /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_5 Position */
#define GPIO_GROUP_INTn_PORT_ENA0_ENA_5_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_5_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_5 Mask */
#define GPIO_GROUP_INTn_PORT_ENA0_ENA_6_Pos                   6                                                         /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_6 Position */
#define GPIO_GROUP_INTn_PORT_ENA0_ENA_6_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_6_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_6 Mask */
#define GPIO_GROUP_INTn_PORT_ENA0_ENA_7_Pos                   7                                                         /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_7 Position */
#define GPIO_GROUP_INTn_PORT_ENA0_ENA_7_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_7_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_7 Mask */
#define GPIO_GROUP_INTn_PORT_ENA0_ENA_8_Pos                   8                                                         /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_8 Position */
#define GPIO_GROUP_INTn_PORT_ENA0_ENA_8_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_8_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_8 Mask */
#define GPIO_GROUP_INTn_PORT_ENA0_ENA_9_Pos                   9                                                         /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_9 Position */
#define GPIO_GROUP_INTn_PORT_ENA0_ENA_9_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_9_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_9 Mask */
#define GPIO_GROUP_INTn_PORT_ENA0_ENA_10_Pos                  10                                                        /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_10 Position */
#define GPIO_GROUP_INTn_PORT_ENA0_ENA_10_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_10_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_10 Mask */
#define GPIO_GROUP_INTn_PORT_ENA0_ENA_11_Pos                  11                                                        /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_11 Position */
#define GPIO_GROUP_INTn_PORT_ENA0_ENA_11_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_11_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_11 Mask */
#define GPIO_GROUP_INTn_PORT_ENA0_ENA_12_Pos                  12                                                        /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_12 Position */
#define GPIO_GROUP_INTn_PORT_ENA0_ENA_12_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_12_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_12 Mask */
#define GPIO_GROUP_INTn_PORT_ENA0_ENA_13_Pos                  13                                                        /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_13 Position */
#define GPIO_GROUP_INTn_PORT_ENA0_ENA_13_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_13_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_13 Mask */
#define GPIO_GROUP_INTn_PORT_ENA0_ENA_14_Pos                  14                                                        /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_14 Position */
#define GPIO_GROUP_INTn_PORT_ENA0_ENA_14_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_14_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_14 Mask */
#define GPIO_GROUP_INTn_PORT_ENA0_ENA_15_Pos                  15                                                        /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_15 Position */
#define GPIO_GROUP_INTn_PORT_ENA0_ENA_15_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_15_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_15 Mask */
#define GPIO_GROUP_INTn_PORT_ENA0_ENA_16_Pos                  16                                                        /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_16 Position */
#define GPIO_GROUP_INTn_PORT_ENA0_ENA_16_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_16_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_16 Mask */
#define GPIO_GROUP_INTn_PORT_ENA0_ENA_17_Pos                  17                                                        /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_17 Position */
#define GPIO_GROUP_INTn_PORT_ENA0_ENA_17_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_17_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_17 Mask */
#define GPIO_GROUP_INTn_PORT_ENA0_ENA_18_Pos                  18                                                        /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_18 Position */
#define GPIO_GROUP_INTn_PORT_ENA0_ENA_18_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_18_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_18 Mask */
#define GPIO_GROUP_INTn_PORT_ENA0_ENA_19_Pos                  19                                                        /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_19 Position */
#define GPIO_GROUP_INTn_PORT_ENA0_ENA_19_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_19_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_19 Mask */
#define GPIO_GROUP_INTn_PORT_ENA0_ENA_20_Pos                  20                                                        /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_20 Position */
#define GPIO_GROUP_INTn_PORT_ENA0_ENA_20_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_20_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_20 Mask */
#define GPIO_GROUP_INTn_PORT_ENA0_ENA_21_Pos                  21                                                        /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_21 Position */
#define GPIO_GROUP_INTn_PORT_ENA0_ENA_21_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_21_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_21 Mask */
#define GPIO_GROUP_INTn_PORT_ENA0_ENA_22_Pos                  22                                                        /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_22 Position */
#define GPIO_GROUP_INTn_PORT_ENA0_ENA_22_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_22_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_22 Mask */
#define GPIO_GROUP_INTn_PORT_ENA0_ENA_23_Pos                  23                                                        /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_23 Position */
#define GPIO_GROUP_INTn_PORT_ENA0_ENA_23_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_23_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_23 Mask */
#define GPIO_GROUP_INTn_PORT_ENA0_ENA_24_Pos                  24                                                        /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_24 Position */
#define GPIO_GROUP_INTn_PORT_ENA0_ENA_24_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_24_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_24 Mask */
#define GPIO_GROUP_INTn_PORT_ENA0_ENA_25_Pos                  25                                                        /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_25 Position */
#define GPIO_GROUP_INTn_PORT_ENA0_ENA_25_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_25_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_25 Mask */
#define GPIO_GROUP_INTn_PORT_ENA0_ENA_26_Pos                  26                                                        /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_26 Position */
#define GPIO_GROUP_INTn_PORT_ENA0_ENA_26_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_26_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_26 Mask */
#define GPIO_GROUP_INTn_PORT_ENA0_ENA_27_Pos                  27                                                        /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_27 Position */
#define GPIO_GROUP_INTn_PORT_ENA0_ENA_27_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_27_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_27 Mask */
#define GPIO_GROUP_INTn_PORT_ENA0_ENA_28_Pos                  28                                                        /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_28 Position */
#define GPIO_GROUP_INTn_PORT_ENA0_ENA_28_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_28_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_28 Mask */
#define GPIO_GROUP_INTn_PORT_ENA0_ENA_29_Pos                  29                                                        /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_29 Position */
#define GPIO_GROUP_INTn_PORT_ENA0_ENA_29_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_29_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_29 Mask */
#define GPIO_GROUP_INTn_PORT_ENA0_ENA_30_Pos                  30                                                        /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_30 Position */
#define GPIO_GROUP_INTn_PORT_ENA0_ENA_30_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_30_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_30 Mask */
#define GPIO_GROUP_INTn_PORT_ENA0_ENA_31_Pos                  31                                                        /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_31 Position */
#define GPIO_GROUP_INTn_PORT_ENA0_ENA_31_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_31_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_31 Mask */

// --------------------------------  GPIO_GROUP_INTn_PORT_ENA1  -----------------------------------
#define GPIO_GROUP_INTn_PORT_ENA1_ENA_0_Pos                   0                                                         /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_0 Position */
#define GPIO_GROUP_INTn_PORT_ENA1_ENA_0_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_0_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_0 Mask */
#define GPIO_GROUP_INTn_PORT_ENA1_ENA_1_Pos                   1                                                         /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_1 Position */
#define GPIO_GROUP_INTn_PORT_ENA1_ENA_1_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_1_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_1 Mask */
#define GPIO_GROUP_INTn_PORT_ENA1_ENA_2_Pos                   2                                                         /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_2 Position */
#define GPIO_GROUP_INTn_PORT_ENA1_ENA_2_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_2_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_2 Mask */
#define GPIO_GROUP_INTn_PORT_ENA1_ENA_3_Pos                   3                                                         /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_3 Position */
#define GPIO_GROUP_INTn_PORT_ENA1_ENA_3_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_3_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_3 Mask */
#define GPIO_GROUP_INTn_PORT_ENA1_ENA_4_Pos                   4                                                         /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_4 Position */
#define GPIO_GROUP_INTn_PORT_ENA1_ENA_4_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_4_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_4 Mask */
#define GPIO_GROUP_INTn_PORT_ENA1_ENA_5_Pos                   5                                                         /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_5 Position */
#define GPIO_GROUP_INTn_PORT_ENA1_ENA_5_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_5_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_5 Mask */
#define GPIO_GROUP_INTn_PORT_ENA1_ENA_6_Pos                   6                                                         /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_6 Position */
#define GPIO_GROUP_INTn_PORT_ENA1_ENA_6_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_6_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_6 Mask */
#define GPIO_GROUP_INTn_PORT_ENA1_ENA_7_Pos                   7                                                         /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_7 Position */
#define GPIO_GROUP_INTn_PORT_ENA1_ENA_7_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_7_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_7 Mask */
#define GPIO_GROUP_INTn_PORT_ENA1_ENA_8_Pos                   8                                                         /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_8 Position */
#define GPIO_GROUP_INTn_PORT_ENA1_ENA_8_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_8_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_8 Mask */
#define GPIO_GROUP_INTn_PORT_ENA1_ENA_9_Pos                   9                                                         /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_9 Position */
#define GPIO_GROUP_INTn_PORT_ENA1_ENA_9_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_9_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_9 Mask */
#define GPIO_GROUP_INTn_PORT_ENA1_ENA_10_Pos                  10                                                        /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_10 Position */
#define GPIO_GROUP_INTn_PORT_ENA1_ENA_10_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_10_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_10 Mask */
#define GPIO_GROUP_INTn_PORT_ENA1_ENA_11_Pos                  11                                                        /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_11 Position */
#define GPIO_GROUP_INTn_PORT_ENA1_ENA_11_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_11_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_11 Mask */
#define GPIO_GROUP_INTn_PORT_ENA1_ENA_12_Pos                  12                                                        /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_12 Position */
#define GPIO_GROUP_INTn_PORT_ENA1_ENA_12_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_12_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_12 Mask */
#define GPIO_GROUP_INTn_PORT_ENA1_ENA_13_Pos                  13                                                        /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_13 Position */
#define GPIO_GROUP_INTn_PORT_ENA1_ENA_13_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_13_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_13 Mask */
#define GPIO_GROUP_INTn_PORT_ENA1_ENA_14_Pos                  14                                                        /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_14 Position */
#define GPIO_GROUP_INTn_PORT_ENA1_ENA_14_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_14_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_14 Mask */
#define GPIO_GROUP_INTn_PORT_ENA1_ENA_15_Pos                  15                                                        /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_15 Position */
#define GPIO_GROUP_INTn_PORT_ENA1_ENA_15_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_15_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_15 Mask */
#define GPIO_GROUP_INTn_PORT_ENA1_ENA_16_Pos                  16                                                        /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_16 Position */
#define GPIO_GROUP_INTn_PORT_ENA1_ENA_16_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_16_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_16 Mask */
#define GPIO_GROUP_INTn_PORT_ENA1_ENA_17_Pos                  17                                                        /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_17 Position */
#define GPIO_GROUP_INTn_PORT_ENA1_ENA_17_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_17_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_17 Mask */
#define GPIO_GROUP_INTn_PORT_ENA1_ENA_18_Pos                  18                                                        /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_18 Position */
#define GPIO_GROUP_INTn_PORT_ENA1_ENA_18_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_18_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_18 Mask */
#define GPIO_GROUP_INTn_PORT_ENA1_ENA_19_Pos                  19                                                        /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_19 Position */
#define GPIO_GROUP_INTn_PORT_ENA1_ENA_19_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_19_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_19 Mask */
#define GPIO_GROUP_INTn_PORT_ENA1_ENA_20_Pos                  20                                                        /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_20 Position */
#define GPIO_GROUP_INTn_PORT_ENA1_ENA_20_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_20_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_20 Mask */
#define GPIO_GROUP_INTn_PORT_ENA1_ENA_21_Pos                  21                                                        /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_21 Position */
#define GPIO_GROUP_INTn_PORT_ENA1_ENA_21_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_21_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_21 Mask */
#define GPIO_GROUP_INTn_PORT_ENA1_ENA_22_Pos                  22                                                        /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_22 Position */
#define GPIO_GROUP_INTn_PORT_ENA1_ENA_22_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_22_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_22 Mask */
#define GPIO_GROUP_INTn_PORT_ENA1_ENA_23_Pos                  23                                                        /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_23 Position */
#define GPIO_GROUP_INTn_PORT_ENA1_ENA_23_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_23_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_23 Mask */
#define GPIO_GROUP_INTn_PORT_ENA1_ENA_24_Pos                  24                                                        /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_24 Position */
#define GPIO_GROUP_INTn_PORT_ENA1_ENA_24_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_24_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_24 Mask */
#define GPIO_GROUP_INTn_PORT_ENA1_ENA_25_Pos                  25                                                        /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_25 Position */
#define GPIO_GROUP_INTn_PORT_ENA1_ENA_25_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_25_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_25 Mask */
#define GPIO_GROUP_INTn_PORT_ENA1_ENA_26_Pos                  26                                                        /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_26 Position */
#define GPIO_GROUP_INTn_PORT_ENA1_ENA_26_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_26_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_26 Mask */
#define GPIO_GROUP_INTn_PORT_ENA1_ENA_27_Pos                  27                                                        /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_27 Position */
#define GPIO_GROUP_INTn_PORT_ENA1_ENA_27_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_27_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_27 Mask */
#define GPIO_GROUP_INTn_PORT_ENA1_ENA_28_Pos                  28                                                        /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_28 Position */
#define GPIO_GROUP_INTn_PORT_ENA1_ENA_28_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_28_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_28 Mask */
#define GPIO_GROUP_INTn_PORT_ENA1_ENA_29_Pos                  29                                                        /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_29 Position */
#define GPIO_GROUP_INTn_PORT_ENA1_ENA_29_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_29_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_29 Mask */
#define GPIO_GROUP_INTn_PORT_ENA1_ENA_30_Pos                  30                                                        /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_30 Position */
#define GPIO_GROUP_INTn_PORT_ENA1_ENA_30_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_30_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_30 Mask */
#define GPIO_GROUP_INTn_PORT_ENA1_ENA_31_Pos                  31                                                        /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_31 Position */
#define GPIO_GROUP_INTn_PORT_ENA1_ENA_31_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_31_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_31 Mask */

// --------------------------------  GPIO_GROUP_INTn_PORT_ENA2  -----------------------------------
#define GPIO_GROUP_INTn_PORT_ENA2_ENA_0_Pos                   0                                                         /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_0 Position */
#define GPIO_GROUP_INTn_PORT_ENA2_ENA_0_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_0_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_0 Mask */
#define GPIO_GROUP_INTn_PORT_ENA2_ENA_1_Pos                   1                                                         /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_1 Position */
#define GPIO_GROUP_INTn_PORT_ENA2_ENA_1_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_1_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_1 Mask */
#define GPIO_GROUP_INTn_PORT_ENA2_ENA_2_Pos                   2                                                         /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_2 Position */
#define GPIO_GROUP_INTn_PORT_ENA2_ENA_2_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_2_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_2 Mask */
#define GPIO_GROUP_INTn_PORT_ENA2_ENA_3_Pos                   3                                                         /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_3 Position */
#define GPIO_GROUP_INTn_PORT_ENA2_ENA_3_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_3_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_3 Mask */
#define GPIO_GROUP_INTn_PORT_ENA2_ENA_4_Pos                   4                                                         /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_4 Position */
#define GPIO_GROUP_INTn_PORT_ENA2_ENA_4_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_4_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_4 Mask */
#define GPIO_GROUP_INTn_PORT_ENA2_ENA_5_Pos                   5                                                         /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_5 Position */
#define GPIO_GROUP_INTn_PORT_ENA2_ENA_5_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_5_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_5 Mask */
#define GPIO_GROUP_INTn_PORT_ENA2_ENA_6_Pos                   6                                                         /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_6 Position */
#define GPIO_GROUP_INTn_PORT_ENA2_ENA_6_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_6_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_6 Mask */
#define GPIO_GROUP_INTn_PORT_ENA2_ENA_7_Pos                   7                                                         /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_7 Position */
#define GPIO_GROUP_INTn_PORT_ENA2_ENA_7_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_7_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_7 Mask */
#define GPIO_GROUP_INTn_PORT_ENA2_ENA_8_Pos                   8                                                         /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_8 Position */
#define GPIO_GROUP_INTn_PORT_ENA2_ENA_8_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_8_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_8 Mask */
#define GPIO_GROUP_INTn_PORT_ENA2_ENA_9_Pos                   9                                                         /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_9 Position */
#define GPIO_GROUP_INTn_PORT_ENA2_ENA_9_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_9_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_9 Mask */
#define GPIO_GROUP_INTn_PORT_ENA2_ENA_10_Pos                  10                                                        /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_10 Position */
#define GPIO_GROUP_INTn_PORT_ENA2_ENA_10_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_10_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_10 Mask */
#define GPIO_GROUP_INTn_PORT_ENA2_ENA_11_Pos                  11                                                        /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_11 Position */
#define GPIO_GROUP_INTn_PORT_ENA2_ENA_11_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_11_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_11 Mask */
#define GPIO_GROUP_INTn_PORT_ENA2_ENA_12_Pos                  12                                                        /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_12 Position */
#define GPIO_GROUP_INTn_PORT_ENA2_ENA_12_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_12_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_12 Mask */
#define GPIO_GROUP_INTn_PORT_ENA2_ENA_13_Pos                  13                                                        /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_13 Position */
#define GPIO_GROUP_INTn_PORT_ENA2_ENA_13_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_13_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_13 Mask */
#define GPIO_GROUP_INTn_PORT_ENA2_ENA_14_Pos                  14                                                        /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_14 Position */
#define GPIO_GROUP_INTn_PORT_ENA2_ENA_14_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_14_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_14 Mask */
#define GPIO_GROUP_INTn_PORT_ENA2_ENA_15_Pos                  15                                                        /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_15 Position */
#define GPIO_GROUP_INTn_PORT_ENA2_ENA_15_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_15_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_15 Mask */
#define GPIO_GROUP_INTn_PORT_ENA2_ENA_16_Pos                  16                                                        /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_16 Position */
#define GPIO_GROUP_INTn_PORT_ENA2_ENA_16_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_16_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_16 Mask */
#define GPIO_GROUP_INTn_PORT_ENA2_ENA_17_Pos                  17                                                        /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_17 Position */
#define GPIO_GROUP_INTn_PORT_ENA2_ENA_17_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_17_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_17 Mask */
#define GPIO_GROUP_INTn_PORT_ENA2_ENA_18_Pos                  18                                                        /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_18 Position */
#define GPIO_GROUP_INTn_PORT_ENA2_ENA_18_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_18_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_18 Mask */
#define GPIO_GROUP_INTn_PORT_ENA2_ENA_19_Pos                  19                                                        /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_19 Position */
#define GPIO_GROUP_INTn_PORT_ENA2_ENA_19_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_19_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_19 Mask */
#define GPIO_GROUP_INTn_PORT_ENA2_ENA_20_Pos                  20                                                        /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_20 Position */
#define GPIO_GROUP_INTn_PORT_ENA2_ENA_20_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_20_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_20 Mask */
#define GPIO_GROUP_INTn_PORT_ENA2_ENA_21_Pos                  21                                                        /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_21 Position */
#define GPIO_GROUP_INTn_PORT_ENA2_ENA_21_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_21_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_21 Mask */
#define GPIO_GROUP_INTn_PORT_ENA2_ENA_22_Pos                  22                                                        /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_22 Position */
#define GPIO_GROUP_INTn_PORT_ENA2_ENA_22_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_22_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_22 Mask */
#define GPIO_GROUP_INTn_PORT_ENA2_ENA_23_Pos                  23                                                        /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_23 Position */
#define GPIO_GROUP_INTn_PORT_ENA2_ENA_23_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_23_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_23 Mask */
#define GPIO_GROUP_INTn_PORT_ENA2_ENA_24_Pos                  24                                                        /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_24 Position */
#define GPIO_GROUP_INTn_PORT_ENA2_ENA_24_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_24_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_24 Mask */
#define GPIO_GROUP_INTn_PORT_ENA2_ENA_25_Pos                  25                                                        /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_25 Position */
#define GPIO_GROUP_INTn_PORT_ENA2_ENA_25_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_25_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_25 Mask */
#define GPIO_GROUP_INTn_PORT_ENA2_ENA_26_Pos                  26                                                        /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_26 Position */
#define GPIO_GROUP_INTn_PORT_ENA2_ENA_26_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_26_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_26 Mask */
#define GPIO_GROUP_INTn_PORT_ENA2_ENA_27_Pos                  27                                                        /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_27 Position */
#define GPIO_GROUP_INTn_PORT_ENA2_ENA_27_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_27_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_27 Mask */
#define GPIO_GROUP_INTn_PORT_ENA2_ENA_28_Pos                  28                                                        /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_28 Position */
#define GPIO_GROUP_INTn_PORT_ENA2_ENA_28_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_28_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_28 Mask */
#define GPIO_GROUP_INTn_PORT_ENA2_ENA_29_Pos                  29                                                        /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_29 Position */
#define GPIO_GROUP_INTn_PORT_ENA2_ENA_29_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_29_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_29 Mask */
#define GPIO_GROUP_INTn_PORT_ENA2_ENA_30_Pos                  30                                                        /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_30 Position */
#define GPIO_GROUP_INTn_PORT_ENA2_ENA_30_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_30_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_30 Mask */
#define GPIO_GROUP_INTn_PORT_ENA2_ENA_31_Pos                  31                                                        /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_31 Position */
#define GPIO_GROUP_INTn_PORT_ENA2_ENA_31_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_31_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_31 Mask */

// --------------------------------  GPIO_GROUP_INTn_PORT_ENA3  -----------------------------------
#define GPIO_GROUP_INTn_PORT_ENA3_ENA_0_Pos                   0                                                         /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_0 Position */
#define GPIO_GROUP_INTn_PORT_ENA3_ENA_0_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_0_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_0 Mask */
#define GPIO_GROUP_INTn_PORT_ENA3_ENA_1_Pos                   1                                                         /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_1 Position */
#define GPIO_GROUP_INTn_PORT_ENA3_ENA_1_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_1_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_1 Mask */
#define GPIO_GROUP_INTn_PORT_ENA3_ENA_2_Pos                   2                                                         /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_2 Position */
#define GPIO_GROUP_INTn_PORT_ENA3_ENA_2_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_2_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_2 Mask */
#define GPIO_GROUP_INTn_PORT_ENA3_ENA_3_Pos                   3                                                         /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_3 Position */
#define GPIO_GROUP_INTn_PORT_ENA3_ENA_3_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_3_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_3 Mask */
#define GPIO_GROUP_INTn_PORT_ENA3_ENA_4_Pos                   4                                                         /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_4 Position */
#define GPIO_GROUP_INTn_PORT_ENA3_ENA_4_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_4_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_4 Mask */
#define GPIO_GROUP_INTn_PORT_ENA3_ENA_5_Pos                   5                                                         /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_5 Position */
#define GPIO_GROUP_INTn_PORT_ENA3_ENA_5_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_5_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_5 Mask */
#define GPIO_GROUP_INTn_PORT_ENA3_ENA_6_Pos                   6                                                         /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_6 Position */
#define GPIO_GROUP_INTn_PORT_ENA3_ENA_6_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_6_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_6 Mask */
#define GPIO_GROUP_INTn_PORT_ENA3_ENA_7_Pos                   7                                                         /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_7 Position */
#define GPIO_GROUP_INTn_PORT_ENA3_ENA_7_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_7_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_7 Mask */
#define GPIO_GROUP_INTn_PORT_ENA3_ENA_8_Pos                   8                                                         /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_8 Position */
#define GPIO_GROUP_INTn_PORT_ENA3_ENA_8_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_8_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_8 Mask */
#define GPIO_GROUP_INTn_PORT_ENA3_ENA_9_Pos                   9                                                         /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_9 Position */
#define GPIO_GROUP_INTn_PORT_ENA3_ENA_9_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_9_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_9 Mask */
#define GPIO_GROUP_INTn_PORT_ENA3_ENA_10_Pos                  10                                                        /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_10 Position */
#define GPIO_GROUP_INTn_PORT_ENA3_ENA_10_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_10_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_10 Mask */
#define GPIO_GROUP_INTn_PORT_ENA3_ENA_11_Pos                  11                                                        /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_11 Position */
#define GPIO_GROUP_INTn_PORT_ENA3_ENA_11_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_11_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_11 Mask */
#define GPIO_GROUP_INTn_PORT_ENA3_ENA_12_Pos                  12                                                        /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_12 Position */
#define GPIO_GROUP_INTn_PORT_ENA3_ENA_12_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_12_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_12 Mask */
#define GPIO_GROUP_INTn_PORT_ENA3_ENA_13_Pos                  13                                                        /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_13 Position */
#define GPIO_GROUP_INTn_PORT_ENA3_ENA_13_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_13_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_13 Mask */
#define GPIO_GROUP_INTn_PORT_ENA3_ENA_14_Pos                  14                                                        /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_14 Position */
#define GPIO_GROUP_INTn_PORT_ENA3_ENA_14_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_14_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_14 Mask */
#define GPIO_GROUP_INTn_PORT_ENA3_ENA_15_Pos                  15                                                        /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_15 Position */
#define GPIO_GROUP_INTn_PORT_ENA3_ENA_15_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_15_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_15 Mask */
#define GPIO_GROUP_INTn_PORT_ENA3_ENA_16_Pos                  16                                                        /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_16 Position */
#define GPIO_GROUP_INTn_PORT_ENA3_ENA_16_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_16_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_16 Mask */
#define GPIO_GROUP_INTn_PORT_ENA3_ENA_17_Pos                  17                                                        /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_17 Position */
#define GPIO_GROUP_INTn_PORT_ENA3_ENA_17_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_17_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_17 Mask */
#define GPIO_GROUP_INTn_PORT_ENA3_ENA_18_Pos                  18                                                        /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_18 Position */
#define GPIO_GROUP_INTn_PORT_ENA3_ENA_18_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_18_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_18 Mask */
#define GPIO_GROUP_INTn_PORT_ENA3_ENA_19_Pos                  19                                                        /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_19 Position */
#define GPIO_GROUP_INTn_PORT_ENA3_ENA_19_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_19_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_19 Mask */
#define GPIO_GROUP_INTn_PORT_ENA3_ENA_20_Pos                  20                                                        /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_20 Position */
#define GPIO_GROUP_INTn_PORT_ENA3_ENA_20_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_20_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_20 Mask */
#define GPIO_GROUP_INTn_PORT_ENA3_ENA_21_Pos                  21                                                        /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_21 Position */
#define GPIO_GROUP_INTn_PORT_ENA3_ENA_21_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_21_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_21 Mask */
#define GPIO_GROUP_INTn_PORT_ENA3_ENA_22_Pos                  22                                                        /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_22 Position */
#define GPIO_GROUP_INTn_PORT_ENA3_ENA_22_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_22_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_22 Mask */
#define GPIO_GROUP_INTn_PORT_ENA3_ENA_23_Pos                  23                                                        /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_23 Position */
#define GPIO_GROUP_INTn_PORT_ENA3_ENA_23_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_23_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_23 Mask */
#define GPIO_GROUP_INTn_PORT_ENA3_ENA_24_Pos                  24                                                        /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_24 Position */
#define GPIO_GROUP_INTn_PORT_ENA3_ENA_24_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_24_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_24 Mask */
#define GPIO_GROUP_INTn_PORT_ENA3_ENA_25_Pos                  25                                                        /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_25 Position */
#define GPIO_GROUP_INTn_PORT_ENA3_ENA_25_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_25_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_25 Mask */
#define GPIO_GROUP_INTn_PORT_ENA3_ENA_26_Pos                  26                                                        /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_26 Position */
#define GPIO_GROUP_INTn_PORT_ENA3_ENA_26_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_26_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_26 Mask */
#define GPIO_GROUP_INTn_PORT_ENA3_ENA_27_Pos                  27                                                        /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_27 Position */
#define GPIO_GROUP_INTn_PORT_ENA3_ENA_27_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_27_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_27 Mask */
#define GPIO_GROUP_INTn_PORT_ENA3_ENA_28_Pos                  28                                                        /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_28 Position */
#define GPIO_GROUP_INTn_PORT_ENA3_ENA_28_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_28_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_28 Mask */
#define GPIO_GROUP_INTn_PORT_ENA3_ENA_29_Pos                  29                                                        /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_29 Position */
#define GPIO_GROUP_INTn_PORT_ENA3_ENA_29_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_29_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_29 Mask */
#define GPIO_GROUP_INTn_PORT_ENA3_ENA_30_Pos                  30                                                        /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_30 Position */
#define GPIO_GROUP_INTn_PORT_ENA3_ENA_30_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_30_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_30 Mask */
#define GPIO_GROUP_INTn_PORT_ENA3_ENA_31_Pos                  31                                                        /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_31 Position */
#define GPIO_GROUP_INTn_PORT_ENA3_ENA_31_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_31_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_31 Mask */

// --------------------------------  GPIO_GROUP_INTn_PORT_ENA4  -----------------------------------
#define GPIO_GROUP_INTn_PORT_ENA4_ENA_0_Pos                   0                                                         /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_0 Position */
#define GPIO_GROUP_INTn_PORT_ENA4_ENA_0_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_0_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_0 Mask */
#define GPIO_GROUP_INTn_PORT_ENA4_ENA_1_Pos                   1                                                         /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_1 Position */
#define GPIO_GROUP_INTn_PORT_ENA4_ENA_1_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_1_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_1 Mask */
#define GPIO_GROUP_INTn_PORT_ENA4_ENA_2_Pos                   2                                                         /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_2 Position */
#define GPIO_GROUP_INTn_PORT_ENA4_ENA_2_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_2_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_2 Mask */
#define GPIO_GROUP_INTn_PORT_ENA4_ENA_3_Pos                   3                                                         /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_3 Position */
#define GPIO_GROUP_INTn_PORT_ENA4_ENA_3_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_3_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_3 Mask */
#define GPIO_GROUP_INTn_PORT_ENA4_ENA_4_Pos                   4                                                         /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_4 Position */
#define GPIO_GROUP_INTn_PORT_ENA4_ENA_4_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_4_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_4 Mask */
#define GPIO_GROUP_INTn_PORT_ENA4_ENA_5_Pos                   5                                                         /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_5 Position */
#define GPIO_GROUP_INTn_PORT_ENA4_ENA_5_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_5_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_5 Mask */
#define GPIO_GROUP_INTn_PORT_ENA4_ENA_6_Pos                   6                                                         /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_6 Position */
#define GPIO_GROUP_INTn_PORT_ENA4_ENA_6_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_6_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_6 Mask */
#define GPIO_GROUP_INTn_PORT_ENA4_ENA_7_Pos                   7                                                         /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_7 Position */
#define GPIO_GROUP_INTn_PORT_ENA4_ENA_7_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_7_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_7 Mask */
#define GPIO_GROUP_INTn_PORT_ENA4_ENA_8_Pos                   8                                                         /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_8 Position */
#define GPIO_GROUP_INTn_PORT_ENA4_ENA_8_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_8_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_8 Mask */
#define GPIO_GROUP_INTn_PORT_ENA4_ENA_9_Pos                   9                                                         /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_9 Position */
#define GPIO_GROUP_INTn_PORT_ENA4_ENA_9_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_9_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_9 Mask */
#define GPIO_GROUP_INTn_PORT_ENA4_ENA_10_Pos                  10                                                        /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_10 Position */
#define GPIO_GROUP_INTn_PORT_ENA4_ENA_10_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_10_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_10 Mask */
#define GPIO_GROUP_INTn_PORT_ENA4_ENA_11_Pos                  11                                                        /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_11 Position */
#define GPIO_GROUP_INTn_PORT_ENA4_ENA_11_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_11_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_11 Mask */
#define GPIO_GROUP_INTn_PORT_ENA4_ENA_12_Pos                  12                                                        /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_12 Position */
#define GPIO_GROUP_INTn_PORT_ENA4_ENA_12_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_12_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_12 Mask */
#define GPIO_GROUP_INTn_PORT_ENA4_ENA_13_Pos                  13                                                        /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_13 Position */
#define GPIO_GROUP_INTn_PORT_ENA4_ENA_13_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_13_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_13 Mask */
#define GPIO_GROUP_INTn_PORT_ENA4_ENA_14_Pos                  14                                                        /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_14 Position */
#define GPIO_GROUP_INTn_PORT_ENA4_ENA_14_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_14_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_14 Mask */
#define GPIO_GROUP_INTn_PORT_ENA4_ENA_15_Pos                  15                                                        /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_15 Position */
#define GPIO_GROUP_INTn_PORT_ENA4_ENA_15_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_15_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_15 Mask */
#define GPIO_GROUP_INTn_PORT_ENA4_ENA_16_Pos                  16                                                        /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_16 Position */
#define GPIO_GROUP_INTn_PORT_ENA4_ENA_16_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_16_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_16 Mask */
#define GPIO_GROUP_INTn_PORT_ENA4_ENA_17_Pos                  17                                                        /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_17 Position */
#define GPIO_GROUP_INTn_PORT_ENA4_ENA_17_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_17_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_17 Mask */
#define GPIO_GROUP_INTn_PORT_ENA4_ENA_18_Pos                  18                                                        /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_18 Position */
#define GPIO_GROUP_INTn_PORT_ENA4_ENA_18_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_18_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_18 Mask */
#define GPIO_GROUP_INTn_PORT_ENA4_ENA_19_Pos                  19                                                        /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_19 Position */
#define GPIO_GROUP_INTn_PORT_ENA4_ENA_19_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_19_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_19 Mask */
#define GPIO_GROUP_INTn_PORT_ENA4_ENA_20_Pos                  20                                                        /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_20 Position */
#define GPIO_GROUP_INTn_PORT_ENA4_ENA_20_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_20_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_20 Mask */
#define GPIO_GROUP_INTn_PORT_ENA4_ENA_21_Pos                  21                                                        /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_21 Position */
#define GPIO_GROUP_INTn_PORT_ENA4_ENA_21_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_21_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_21 Mask */
#define GPIO_GROUP_INTn_PORT_ENA4_ENA_22_Pos                  22                                                        /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_22 Position */
#define GPIO_GROUP_INTn_PORT_ENA4_ENA_22_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_22_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_22 Mask */
#define GPIO_GROUP_INTn_PORT_ENA4_ENA_23_Pos                  23                                                        /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_23 Position */
#define GPIO_GROUP_INTn_PORT_ENA4_ENA_23_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_23_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_23 Mask */
#define GPIO_GROUP_INTn_PORT_ENA4_ENA_24_Pos                  24                                                        /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_24 Position */
#define GPIO_GROUP_INTn_PORT_ENA4_ENA_24_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_24_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_24 Mask */
#define GPIO_GROUP_INTn_PORT_ENA4_ENA_25_Pos                  25                                                        /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_25 Position */
#define GPIO_GROUP_INTn_PORT_ENA4_ENA_25_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_25_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_25 Mask */
#define GPIO_GROUP_INTn_PORT_ENA4_ENA_26_Pos                  26                                                        /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_26 Position */
#define GPIO_GROUP_INTn_PORT_ENA4_ENA_26_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_26_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_26 Mask */
#define GPIO_GROUP_INTn_PORT_ENA4_ENA_27_Pos                  27                                                        /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_27 Position */
#define GPIO_GROUP_INTn_PORT_ENA4_ENA_27_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_27_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_27 Mask */
#define GPIO_GROUP_INTn_PORT_ENA4_ENA_28_Pos                  28                                                        /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_28 Position */
#define GPIO_GROUP_INTn_PORT_ENA4_ENA_28_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_28_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_28 Mask */
#define GPIO_GROUP_INTn_PORT_ENA4_ENA_29_Pos                  29                                                        /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_29 Position */
#define GPIO_GROUP_INTn_PORT_ENA4_ENA_29_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_29_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_29 Mask */
#define GPIO_GROUP_INTn_PORT_ENA4_ENA_30_Pos                  30                                                        /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_30 Position */
#define GPIO_GROUP_INTn_PORT_ENA4_ENA_30_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_30_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_30 Mask */
#define GPIO_GROUP_INTn_PORT_ENA4_ENA_31_Pos                  31                                                        /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_31 Position */
#define GPIO_GROUP_INTn_PORT_ENA4_ENA_31_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_31_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_31 Mask */

// --------------------------------  GPIO_GROUP_INTn_PORT_ENA5  -----------------------------------
#define GPIO_GROUP_INTn_PORT_ENA5_ENA_0_Pos                   0                                                         /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_0 Position */
#define GPIO_GROUP_INTn_PORT_ENA5_ENA_0_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_0_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_0 Mask */
#define GPIO_GROUP_INTn_PORT_ENA5_ENA_1_Pos                   1                                                         /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_1 Position */
#define GPIO_GROUP_INTn_PORT_ENA5_ENA_1_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_1_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_1 Mask */
#define GPIO_GROUP_INTn_PORT_ENA5_ENA_2_Pos                   2                                                         /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_2 Position */
#define GPIO_GROUP_INTn_PORT_ENA5_ENA_2_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_2_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_2 Mask */
#define GPIO_GROUP_INTn_PORT_ENA5_ENA_3_Pos                   3                                                         /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_3 Position */
#define GPIO_GROUP_INTn_PORT_ENA5_ENA_3_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_3_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_3 Mask */
#define GPIO_GROUP_INTn_PORT_ENA5_ENA_4_Pos                   4                                                         /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_4 Position */
#define GPIO_GROUP_INTn_PORT_ENA5_ENA_4_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_4_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_4 Mask */
#define GPIO_GROUP_INTn_PORT_ENA5_ENA_5_Pos                   5                                                         /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_5 Position */
#define GPIO_GROUP_INTn_PORT_ENA5_ENA_5_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_5_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_5 Mask */
#define GPIO_GROUP_INTn_PORT_ENA5_ENA_6_Pos                   6                                                         /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_6 Position */
#define GPIO_GROUP_INTn_PORT_ENA5_ENA_6_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_6_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_6 Mask */
#define GPIO_GROUP_INTn_PORT_ENA5_ENA_7_Pos                   7                                                         /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_7 Position */
#define GPIO_GROUP_INTn_PORT_ENA5_ENA_7_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_7_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_7 Mask */
#define GPIO_GROUP_INTn_PORT_ENA5_ENA_8_Pos                   8                                                         /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_8 Position */
#define GPIO_GROUP_INTn_PORT_ENA5_ENA_8_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_8_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_8 Mask */
#define GPIO_GROUP_INTn_PORT_ENA5_ENA_9_Pos                   9                                                         /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_9 Position */
#define GPIO_GROUP_INTn_PORT_ENA5_ENA_9_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_9_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_9 Mask */
#define GPIO_GROUP_INTn_PORT_ENA5_ENA_10_Pos                  10                                                        /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_10 Position */
#define GPIO_GROUP_INTn_PORT_ENA5_ENA_10_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_10_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_10 Mask */
#define GPIO_GROUP_INTn_PORT_ENA5_ENA_11_Pos                  11                                                        /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_11 Position */
#define GPIO_GROUP_INTn_PORT_ENA5_ENA_11_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_11_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_11 Mask */
#define GPIO_GROUP_INTn_PORT_ENA5_ENA_12_Pos                  12                                                        /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_12 Position */
#define GPIO_GROUP_INTn_PORT_ENA5_ENA_12_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_12_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_12 Mask */
#define GPIO_GROUP_INTn_PORT_ENA5_ENA_13_Pos                  13                                                        /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_13 Position */
#define GPIO_GROUP_INTn_PORT_ENA5_ENA_13_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_13_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_13 Mask */
#define GPIO_GROUP_INTn_PORT_ENA5_ENA_14_Pos                  14                                                        /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_14 Position */
#define GPIO_GROUP_INTn_PORT_ENA5_ENA_14_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_14_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_14 Mask */
#define GPIO_GROUP_INTn_PORT_ENA5_ENA_15_Pos                  15                                                        /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_15 Position */
#define GPIO_GROUP_INTn_PORT_ENA5_ENA_15_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_15_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_15 Mask */
#define GPIO_GROUP_INTn_PORT_ENA5_ENA_16_Pos                  16                                                        /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_16 Position */
#define GPIO_GROUP_INTn_PORT_ENA5_ENA_16_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_16_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_16 Mask */
#define GPIO_GROUP_INTn_PORT_ENA5_ENA_17_Pos                  17                                                        /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_17 Position */
#define GPIO_GROUP_INTn_PORT_ENA5_ENA_17_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_17_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_17 Mask */
#define GPIO_GROUP_INTn_PORT_ENA5_ENA_18_Pos                  18                                                        /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_18 Position */
#define GPIO_GROUP_INTn_PORT_ENA5_ENA_18_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_18_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_18 Mask */
#define GPIO_GROUP_INTn_PORT_ENA5_ENA_19_Pos                  19                                                        /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_19 Position */
#define GPIO_GROUP_INTn_PORT_ENA5_ENA_19_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_19_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_19 Mask */
#define GPIO_GROUP_INTn_PORT_ENA5_ENA_20_Pos                  20                                                        /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_20 Position */
#define GPIO_GROUP_INTn_PORT_ENA5_ENA_20_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_20_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_20 Mask */
#define GPIO_GROUP_INTn_PORT_ENA5_ENA_21_Pos                  21                                                        /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_21 Position */
#define GPIO_GROUP_INTn_PORT_ENA5_ENA_21_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_21_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_21 Mask */
#define GPIO_GROUP_INTn_PORT_ENA5_ENA_22_Pos                  22                                                        /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_22 Position */
#define GPIO_GROUP_INTn_PORT_ENA5_ENA_22_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_22_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_22 Mask */
#define GPIO_GROUP_INTn_PORT_ENA5_ENA_23_Pos                  23                                                        /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_23 Position */
#define GPIO_GROUP_INTn_PORT_ENA5_ENA_23_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_23_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_23 Mask */
#define GPIO_GROUP_INTn_PORT_ENA5_ENA_24_Pos                  24                                                        /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_24 Position */
#define GPIO_GROUP_INTn_PORT_ENA5_ENA_24_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_24_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_24 Mask */
#define GPIO_GROUP_INTn_PORT_ENA5_ENA_25_Pos                  25                                                        /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_25 Position */
#define GPIO_GROUP_INTn_PORT_ENA5_ENA_25_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_25_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_25 Mask */
#define GPIO_GROUP_INTn_PORT_ENA5_ENA_26_Pos                  26                                                        /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_26 Position */
#define GPIO_GROUP_INTn_PORT_ENA5_ENA_26_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_26_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_26 Mask */
#define GPIO_GROUP_INTn_PORT_ENA5_ENA_27_Pos                  27                                                        /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_27 Position */
#define GPIO_GROUP_INTn_PORT_ENA5_ENA_27_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_27_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_27 Mask */
#define GPIO_GROUP_INTn_PORT_ENA5_ENA_28_Pos                  28                                                        /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_28 Position */
#define GPIO_GROUP_INTn_PORT_ENA5_ENA_28_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_28_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_28 Mask */
#define GPIO_GROUP_INTn_PORT_ENA5_ENA_29_Pos                  29                                                        /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_29 Position */
#define GPIO_GROUP_INTn_PORT_ENA5_ENA_29_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_29_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_29 Mask */
#define GPIO_GROUP_INTn_PORT_ENA5_ENA_30_Pos                  30                                                        /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_30 Position */
#define GPIO_GROUP_INTn_PORT_ENA5_ENA_30_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_30_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_30 Mask */
#define GPIO_GROUP_INTn_PORT_ENA5_ENA_31_Pos                  31                                                        /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_31 Position */
#define GPIO_GROUP_INTn_PORT_ENA5_ENA_31_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_31_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_31 Mask */

// --------------------------------  GPIO_GROUP_INTn_PORT_ENA6  -----------------------------------
#define GPIO_GROUP_INTn_PORT_ENA6_ENA_0_Pos                   0                                                         /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_0 Position */
#define GPIO_GROUP_INTn_PORT_ENA6_ENA_0_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_0_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_0 Mask */
#define GPIO_GROUP_INTn_PORT_ENA6_ENA_1_Pos                   1                                                         /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_1 Position */
#define GPIO_GROUP_INTn_PORT_ENA6_ENA_1_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_1_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_1 Mask */
#define GPIO_GROUP_INTn_PORT_ENA6_ENA_2_Pos                   2                                                         /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_2 Position */
#define GPIO_GROUP_INTn_PORT_ENA6_ENA_2_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_2_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_2 Mask */
#define GPIO_GROUP_INTn_PORT_ENA6_ENA_3_Pos                   3                                                         /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_3 Position */
#define GPIO_GROUP_INTn_PORT_ENA6_ENA_3_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_3_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_3 Mask */
#define GPIO_GROUP_INTn_PORT_ENA6_ENA_4_Pos                   4                                                         /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_4 Position */
#define GPIO_GROUP_INTn_PORT_ENA6_ENA_4_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_4_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_4 Mask */
#define GPIO_GROUP_INTn_PORT_ENA6_ENA_5_Pos                   5                                                         /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_5 Position */
#define GPIO_GROUP_INTn_PORT_ENA6_ENA_5_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_5_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_5 Mask */
#define GPIO_GROUP_INTn_PORT_ENA6_ENA_6_Pos                   6                                                         /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_6 Position */
#define GPIO_GROUP_INTn_PORT_ENA6_ENA_6_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_6_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_6 Mask */
#define GPIO_GROUP_INTn_PORT_ENA6_ENA_7_Pos                   7                                                         /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_7 Position */
#define GPIO_GROUP_INTn_PORT_ENA6_ENA_7_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_7_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_7 Mask */
#define GPIO_GROUP_INTn_PORT_ENA6_ENA_8_Pos                   8                                                         /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_8 Position */
#define GPIO_GROUP_INTn_PORT_ENA6_ENA_8_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_8_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_8 Mask */
#define GPIO_GROUP_INTn_PORT_ENA6_ENA_9_Pos                   9                                                         /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_9 Position */
#define GPIO_GROUP_INTn_PORT_ENA6_ENA_9_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_9_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_9 Mask */
#define GPIO_GROUP_INTn_PORT_ENA6_ENA_10_Pos                  10                                                        /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_10 Position */
#define GPIO_GROUP_INTn_PORT_ENA6_ENA_10_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_10_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_10 Mask */
#define GPIO_GROUP_INTn_PORT_ENA6_ENA_11_Pos                  11                                                        /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_11 Position */
#define GPIO_GROUP_INTn_PORT_ENA6_ENA_11_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_11_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_11 Mask */
#define GPIO_GROUP_INTn_PORT_ENA6_ENA_12_Pos                  12                                                        /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_12 Position */
#define GPIO_GROUP_INTn_PORT_ENA6_ENA_12_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_12_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_12 Mask */
#define GPIO_GROUP_INTn_PORT_ENA6_ENA_13_Pos                  13                                                        /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_13 Position */
#define GPIO_GROUP_INTn_PORT_ENA6_ENA_13_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_13_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_13 Mask */
#define GPIO_GROUP_INTn_PORT_ENA6_ENA_14_Pos                  14                                                        /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_14 Position */
#define GPIO_GROUP_INTn_PORT_ENA6_ENA_14_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_14_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_14 Mask */
#define GPIO_GROUP_INTn_PORT_ENA6_ENA_15_Pos                  15                                                        /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_15 Position */
#define GPIO_GROUP_INTn_PORT_ENA6_ENA_15_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_15_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_15 Mask */
#define GPIO_GROUP_INTn_PORT_ENA6_ENA_16_Pos                  16                                                        /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_16 Position */
#define GPIO_GROUP_INTn_PORT_ENA6_ENA_16_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_16_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_16 Mask */
#define GPIO_GROUP_INTn_PORT_ENA6_ENA_17_Pos                  17                                                        /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_17 Position */
#define GPIO_GROUP_INTn_PORT_ENA6_ENA_17_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_17_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_17 Mask */
#define GPIO_GROUP_INTn_PORT_ENA6_ENA_18_Pos                  18                                                        /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_18 Position */
#define GPIO_GROUP_INTn_PORT_ENA6_ENA_18_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_18_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_18 Mask */
#define GPIO_GROUP_INTn_PORT_ENA6_ENA_19_Pos                  19                                                        /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_19 Position */
#define GPIO_GROUP_INTn_PORT_ENA6_ENA_19_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_19_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_19 Mask */
#define GPIO_GROUP_INTn_PORT_ENA6_ENA_20_Pos                  20                                                        /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_20 Position */
#define GPIO_GROUP_INTn_PORT_ENA6_ENA_20_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_20_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_20 Mask */
#define GPIO_GROUP_INTn_PORT_ENA6_ENA_21_Pos                  21                                                        /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_21 Position */
#define GPIO_GROUP_INTn_PORT_ENA6_ENA_21_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_21_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_21 Mask */
#define GPIO_GROUP_INTn_PORT_ENA6_ENA_22_Pos                  22                                                        /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_22 Position */
#define GPIO_GROUP_INTn_PORT_ENA6_ENA_22_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_22_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_22 Mask */
#define GPIO_GROUP_INTn_PORT_ENA6_ENA_23_Pos                  23                                                        /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_23 Position */
#define GPIO_GROUP_INTn_PORT_ENA6_ENA_23_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_23_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_23 Mask */
#define GPIO_GROUP_INTn_PORT_ENA6_ENA_24_Pos                  24                                                        /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_24 Position */
#define GPIO_GROUP_INTn_PORT_ENA6_ENA_24_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_24_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_24 Mask */
#define GPIO_GROUP_INTn_PORT_ENA6_ENA_25_Pos                  25                                                        /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_25 Position */
#define GPIO_GROUP_INTn_PORT_ENA6_ENA_25_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_25_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_25 Mask */
#define GPIO_GROUP_INTn_PORT_ENA6_ENA_26_Pos                  26                                                        /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_26 Position */
#define GPIO_GROUP_INTn_PORT_ENA6_ENA_26_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_26_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_26 Mask */
#define GPIO_GROUP_INTn_PORT_ENA6_ENA_27_Pos                  27                                                        /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_27 Position */
#define GPIO_GROUP_INTn_PORT_ENA6_ENA_27_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_27_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_27 Mask */
#define GPIO_GROUP_INTn_PORT_ENA6_ENA_28_Pos                  28                                                        /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_28 Position */
#define GPIO_GROUP_INTn_PORT_ENA6_ENA_28_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_28_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_28 Mask */
#define GPIO_GROUP_INTn_PORT_ENA6_ENA_29_Pos                  29                                                        /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_29 Position */
#define GPIO_GROUP_INTn_PORT_ENA6_ENA_29_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_29_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_29 Mask */
#define GPIO_GROUP_INTn_PORT_ENA6_ENA_30_Pos                  30                                                        /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_30 Position */
#define GPIO_GROUP_INTn_PORT_ENA6_ENA_30_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_30_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_30 Mask */
#define GPIO_GROUP_INTn_PORT_ENA6_ENA_31_Pos                  31                                                        /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_31 Position */
#define GPIO_GROUP_INTn_PORT_ENA6_ENA_31_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_31_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_31 Mask */

// --------------------------------  GPIO_GROUP_INTn_PORT_ENA7  -----------------------------------
#define GPIO_GROUP_INTn_PORT_ENA7_ENA_0_Pos                   0                                                         /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_0 Position */
#define GPIO_GROUP_INTn_PORT_ENA7_ENA_0_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_0_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_0 Mask */
#define GPIO_GROUP_INTn_PORT_ENA7_ENA_1_Pos                   1                                                         /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_1 Position */
#define GPIO_GROUP_INTn_PORT_ENA7_ENA_1_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_1_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_1 Mask */
#define GPIO_GROUP_INTn_PORT_ENA7_ENA_2_Pos                   2                                                         /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_2 Position */
#define GPIO_GROUP_INTn_PORT_ENA7_ENA_2_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_2_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_2 Mask */
#define GPIO_GROUP_INTn_PORT_ENA7_ENA_3_Pos                   3                                                         /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_3 Position */
#define GPIO_GROUP_INTn_PORT_ENA7_ENA_3_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_3_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_3 Mask */
#define GPIO_GROUP_INTn_PORT_ENA7_ENA_4_Pos                   4                                                         /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_4 Position */
#define GPIO_GROUP_INTn_PORT_ENA7_ENA_4_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_4_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_4 Mask */
#define GPIO_GROUP_INTn_PORT_ENA7_ENA_5_Pos                   5                                                         /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_5 Position */
#define GPIO_GROUP_INTn_PORT_ENA7_ENA_5_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_5_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_5 Mask */
#define GPIO_GROUP_INTn_PORT_ENA7_ENA_6_Pos                   6                                                         /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_6 Position */
#define GPIO_GROUP_INTn_PORT_ENA7_ENA_6_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_6_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_6 Mask */
#define GPIO_GROUP_INTn_PORT_ENA7_ENA_7_Pos                   7                                                         /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_7 Position */
#define GPIO_GROUP_INTn_PORT_ENA7_ENA_7_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_7_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_7 Mask */
#define GPIO_GROUP_INTn_PORT_ENA7_ENA_8_Pos                   8                                                         /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_8 Position */
#define GPIO_GROUP_INTn_PORT_ENA7_ENA_8_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_8_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_8 Mask */
#define GPIO_GROUP_INTn_PORT_ENA7_ENA_9_Pos                   9                                                         /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_9 Position */
#define GPIO_GROUP_INTn_PORT_ENA7_ENA_9_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_9_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_9 Mask */
#define GPIO_GROUP_INTn_PORT_ENA7_ENA_10_Pos                  10                                                        /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_10 Position */
#define GPIO_GROUP_INTn_PORT_ENA7_ENA_10_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_10_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_10 Mask */
#define GPIO_GROUP_INTn_PORT_ENA7_ENA_11_Pos                  11                                                        /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_11 Position */
#define GPIO_GROUP_INTn_PORT_ENA7_ENA_11_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_11_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_11 Mask */
#define GPIO_GROUP_INTn_PORT_ENA7_ENA_12_Pos                  12                                                        /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_12 Position */
#define GPIO_GROUP_INTn_PORT_ENA7_ENA_12_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_12_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_12 Mask */
#define GPIO_GROUP_INTn_PORT_ENA7_ENA_13_Pos                  13                                                        /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_13 Position */
#define GPIO_GROUP_INTn_PORT_ENA7_ENA_13_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_13_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_13 Mask */
#define GPIO_GROUP_INTn_PORT_ENA7_ENA_14_Pos                  14                                                        /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_14 Position */
#define GPIO_GROUP_INTn_PORT_ENA7_ENA_14_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_14_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_14 Mask */
#define GPIO_GROUP_INTn_PORT_ENA7_ENA_15_Pos                  15                                                        /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_15 Position */
#define GPIO_GROUP_INTn_PORT_ENA7_ENA_15_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_15_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_15 Mask */
#define GPIO_GROUP_INTn_PORT_ENA7_ENA_16_Pos                  16                                                        /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_16 Position */
#define GPIO_GROUP_INTn_PORT_ENA7_ENA_16_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_16_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_16 Mask */
#define GPIO_GROUP_INTn_PORT_ENA7_ENA_17_Pos                  17                                                        /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_17 Position */
#define GPIO_GROUP_INTn_PORT_ENA7_ENA_17_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_17_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_17 Mask */
#define GPIO_GROUP_INTn_PORT_ENA7_ENA_18_Pos                  18                                                        /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_18 Position */
#define GPIO_GROUP_INTn_PORT_ENA7_ENA_18_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_18_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_18 Mask */
#define GPIO_GROUP_INTn_PORT_ENA7_ENA_19_Pos                  19                                                        /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_19 Position */
#define GPIO_GROUP_INTn_PORT_ENA7_ENA_19_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_19_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_19 Mask */
#define GPIO_GROUP_INTn_PORT_ENA7_ENA_20_Pos                  20                                                        /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_20 Position */
#define GPIO_GROUP_INTn_PORT_ENA7_ENA_20_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_20_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_20 Mask */
#define GPIO_GROUP_INTn_PORT_ENA7_ENA_21_Pos                  21                                                        /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_21 Position */
#define GPIO_GROUP_INTn_PORT_ENA7_ENA_21_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_21_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_21 Mask */
#define GPIO_GROUP_INTn_PORT_ENA7_ENA_22_Pos                  22                                                        /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_22 Position */
#define GPIO_GROUP_INTn_PORT_ENA7_ENA_22_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_22_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_22 Mask */
#define GPIO_GROUP_INTn_PORT_ENA7_ENA_23_Pos                  23                                                        /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_23 Position */
#define GPIO_GROUP_INTn_PORT_ENA7_ENA_23_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_23_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_23 Mask */
#define GPIO_GROUP_INTn_PORT_ENA7_ENA_24_Pos                  24                                                        /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_24 Position */
#define GPIO_GROUP_INTn_PORT_ENA7_ENA_24_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_24_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_24 Mask */
#define GPIO_GROUP_INTn_PORT_ENA7_ENA_25_Pos                  25                                                        /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_25 Position */
#define GPIO_GROUP_INTn_PORT_ENA7_ENA_25_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_25_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_25 Mask */
#define GPIO_GROUP_INTn_PORT_ENA7_ENA_26_Pos                  26                                                        /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_26 Position */
#define GPIO_GROUP_INTn_PORT_ENA7_ENA_26_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_26_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_26 Mask */
#define GPIO_GROUP_INTn_PORT_ENA7_ENA_27_Pos                  27                                                        /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_27 Position */
#define GPIO_GROUP_INTn_PORT_ENA7_ENA_27_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_27_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_27 Mask */
#define GPIO_GROUP_INTn_PORT_ENA7_ENA_28_Pos                  28                                                        /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_28 Position */
#define GPIO_GROUP_INTn_PORT_ENA7_ENA_28_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_28_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_28 Mask */
#define GPIO_GROUP_INTn_PORT_ENA7_ENA_29_Pos                  29                                                        /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_29 Position */
#define GPIO_GROUP_INTn_PORT_ENA7_ENA_29_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_29_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_29 Mask */
#define GPIO_GROUP_INTn_PORT_ENA7_ENA_30_Pos                  30                                                        /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_30 Position */
#define GPIO_GROUP_INTn_PORT_ENA7_ENA_30_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_30_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_30 Mask */
#define GPIO_GROUP_INTn_PORT_ENA7_ENA_31_Pos                  31                                                        /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_31 Position */
#define GPIO_GROUP_INTn_PORT_ENA7_ENA_31_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_31_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_31 Mask */


// ------------------------------------------------------------------------------------------------
// -----                            GPIO_GROUP_INT1 Position & Mask                           -----
// ------------------------------------------------------------------------------------------------


// ----------------------------------  GPIO_GROUP_INT1_CTRL  --------------------------------------
#define GPIO_GROUP_INT1_CTRL_INT_Pos                          0                                                         /*!< GPIO_GROUP_INT1 CTRL: INT Position  */
#define GPIO_GROUP_INT1_CTRL_INT_Msk                          (0x01UL << GPIO_GROUP_INT1_CTRL_INT_Pos)                  /*!< GPIO_GROUP_INT1 CTRL: INT Mask      */
#define GPIO_GROUP_INT1_CTRL_COMB_Pos                         1                                                         /*!< GPIO_GROUP_INT1 CTRL: COMB Position */
#define GPIO_GROUP_INT1_CTRL_COMB_Msk                         (0x01UL << GPIO_GROUP_INT1_CTRL_COMB_Pos)                 /*!< GPIO_GROUP_INT1 CTRL: COMB Mask     */
#define GPIO_GROUP_INT1_CTRL_TRIG_Pos                         2                                                         /*!< GPIO_GROUP_INT1 CTRL: TRIG Position */
#define GPIO_GROUP_INT1_CTRL_TRIG_Msk                         (0x01UL << GPIO_GROUP_INT1_CTRL_TRIG_Pos)                 /*!< GPIO_GROUP_INT1 CTRL: TRIG Mask     */

// --------------------------------  GPIO_GROUP_INT1_PORT_POL0  -----------------------------------
#define GPIO_GROUP_INT1_PORT_POL0_POL_0_Pos                   0                                                         /*!< GPIO_GROUP_INT1 PORT_POL0: POL_0 Position */
#define GPIO_GROUP_INT1_PORT_POL0_POL_0_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_0_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL0: POL_0 Mask */
#define GPIO_GROUP_INT1_PORT_POL0_POL_1_Pos                   1                                                         /*!< GPIO_GROUP_INT1 PORT_POL0: POL_1 Position */
#define GPIO_GROUP_INT1_PORT_POL0_POL_1_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_1_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL0: POL_1 Mask */
#define GPIO_GROUP_INT1_PORT_POL0_POL_2_Pos                   2                                                         /*!< GPIO_GROUP_INT1 PORT_POL0: POL_2 Position */
#define GPIO_GROUP_INT1_PORT_POL0_POL_2_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_2_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL0: POL_2 Mask */
#define GPIO_GROUP_INT1_PORT_POL0_POL_3_Pos                   3                                                         /*!< GPIO_GROUP_INT1 PORT_POL0: POL_3 Position */
#define GPIO_GROUP_INT1_PORT_POL0_POL_3_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_3_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL0: POL_3 Mask */
#define GPIO_GROUP_INT1_PORT_POL0_POL_4_Pos                   4                                                         /*!< GPIO_GROUP_INT1 PORT_POL0: POL_4 Position */
#define GPIO_GROUP_INT1_PORT_POL0_POL_4_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_4_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL0: POL_4 Mask */
#define GPIO_GROUP_INT1_PORT_POL0_POL_5_Pos                   5                                                         /*!< GPIO_GROUP_INT1 PORT_POL0: POL_5 Position */
#define GPIO_GROUP_INT1_PORT_POL0_POL_5_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_5_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL0: POL_5 Mask */
#define GPIO_GROUP_INT1_PORT_POL0_POL_6_Pos                   6                                                         /*!< GPIO_GROUP_INT1 PORT_POL0: POL_6 Position */
#define GPIO_GROUP_INT1_PORT_POL0_POL_6_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_6_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL0: POL_6 Mask */
#define GPIO_GROUP_INT1_PORT_POL0_POL_7_Pos                   7                                                         /*!< GPIO_GROUP_INT1 PORT_POL0: POL_7 Position */
#define GPIO_GROUP_INT1_PORT_POL0_POL_7_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_7_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL0: POL_7 Mask */
#define GPIO_GROUP_INT1_PORT_POL0_POL_8_Pos                   8                                                         /*!< GPIO_GROUP_INT1 PORT_POL0: POL_8 Position */
#define GPIO_GROUP_INT1_PORT_POL0_POL_8_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_8_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL0: POL_8 Mask */
#define GPIO_GROUP_INT1_PORT_POL0_POL_9_Pos                   9                                                         /*!< GPIO_GROUP_INT1 PORT_POL0: POL_9 Position */
#define GPIO_GROUP_INT1_PORT_POL0_POL_9_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_9_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL0: POL_9 Mask */
#define GPIO_GROUP_INT1_PORT_POL0_POL_10_Pos                  10                                                        /*!< GPIO_GROUP_INT1 PORT_POL0: POL_10 Position */
#define GPIO_GROUP_INT1_PORT_POL0_POL_10_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_10_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL0: POL_10 Mask */
#define GPIO_GROUP_INT1_PORT_POL0_POL_11_Pos                  11                                                        /*!< GPIO_GROUP_INT1 PORT_POL0: POL_11 Position */
#define GPIO_GROUP_INT1_PORT_POL0_POL_11_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_11_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL0: POL_11 Mask */
#define GPIO_GROUP_INT1_PORT_POL0_POL_12_Pos                  12                                                        /*!< GPIO_GROUP_INT1 PORT_POL0: POL_12 Position */
#define GPIO_GROUP_INT1_PORT_POL0_POL_12_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_12_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL0: POL_12 Mask */
#define GPIO_GROUP_INT1_PORT_POL0_POL_13_Pos                  13                                                        /*!< GPIO_GROUP_INT1 PORT_POL0: POL_13 Position */
#define GPIO_GROUP_INT1_PORT_POL0_POL_13_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_13_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL0: POL_13 Mask */
#define GPIO_GROUP_INT1_PORT_POL0_POL_14_Pos                  14                                                        /*!< GPIO_GROUP_INT1 PORT_POL0: POL_14 Position */
#define GPIO_GROUP_INT1_PORT_POL0_POL_14_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_14_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL0: POL_14 Mask */
#define GPIO_GROUP_INT1_PORT_POL0_POL_15_Pos                  15                                                        /*!< GPIO_GROUP_INT1 PORT_POL0: POL_15 Position */
#define GPIO_GROUP_INT1_PORT_POL0_POL_15_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_15_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL0: POL_15 Mask */
#define GPIO_GROUP_INT1_PORT_POL0_POL_16_Pos                  16                                                        /*!< GPIO_GROUP_INT1 PORT_POL0: POL_16 Position */
#define GPIO_GROUP_INT1_PORT_POL0_POL_16_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_16_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL0: POL_16 Mask */
#define GPIO_GROUP_INT1_PORT_POL0_POL_17_Pos                  17                                                        /*!< GPIO_GROUP_INT1 PORT_POL0: POL_17 Position */
#define GPIO_GROUP_INT1_PORT_POL0_POL_17_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_17_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL0: POL_17 Mask */
#define GPIO_GROUP_INT1_PORT_POL0_POL_18_Pos                  18                                                        /*!< GPIO_GROUP_INT1 PORT_POL0: POL_18 Position */
#define GPIO_GROUP_INT1_PORT_POL0_POL_18_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_18_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL0: POL_18 Mask */
#define GPIO_GROUP_INT1_PORT_POL0_POL_19_Pos                  19                                                        /*!< GPIO_GROUP_INT1 PORT_POL0: POL_19 Position */
#define GPIO_GROUP_INT1_PORT_POL0_POL_19_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_19_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL0: POL_19 Mask */
#define GPIO_GROUP_INT1_PORT_POL0_POL_20_Pos                  20                                                        /*!< GPIO_GROUP_INT1 PORT_POL0: POL_20 Position */
#define GPIO_GROUP_INT1_PORT_POL0_POL_20_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_20_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL0: POL_20 Mask */
#define GPIO_GROUP_INT1_PORT_POL0_POL_21_Pos                  21                                                        /*!< GPIO_GROUP_INT1 PORT_POL0: POL_21 Position */
#define GPIO_GROUP_INT1_PORT_POL0_POL_21_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_21_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL0: POL_21 Mask */
#define GPIO_GROUP_INT1_PORT_POL0_POL_22_Pos                  22                                                        /*!< GPIO_GROUP_INT1 PORT_POL0: POL_22 Position */
#define GPIO_GROUP_INT1_PORT_POL0_POL_22_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_22_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL0: POL_22 Mask */
#define GPIO_GROUP_INT1_PORT_POL0_POL_23_Pos                  23                                                        /*!< GPIO_GROUP_INT1 PORT_POL0: POL_23 Position */
#define GPIO_GROUP_INT1_PORT_POL0_POL_23_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_23_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL0: POL_23 Mask */
#define GPIO_GROUP_INT1_PORT_POL0_POL_24_Pos                  24                                                        /*!< GPIO_GROUP_INT1 PORT_POL0: POL_24 Position */
#define GPIO_GROUP_INT1_PORT_POL0_POL_24_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_24_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL0: POL_24 Mask */
#define GPIO_GROUP_INT1_PORT_POL0_POL_25_Pos                  25                                                        /*!< GPIO_GROUP_INT1 PORT_POL0: POL_25 Position */
#define GPIO_GROUP_INT1_PORT_POL0_POL_25_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_25_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL0: POL_25 Mask */
#define GPIO_GROUP_INT1_PORT_POL0_POL_26_Pos                  26                                                        /*!< GPIO_GROUP_INT1 PORT_POL0: POL_26 Position */
#define GPIO_GROUP_INT1_PORT_POL0_POL_26_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_26_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL0: POL_26 Mask */
#define GPIO_GROUP_INT1_PORT_POL0_POL_27_Pos                  27                                                        /*!< GPIO_GROUP_INT1 PORT_POL0: POL_27 Position */
#define GPIO_GROUP_INT1_PORT_POL0_POL_27_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_27_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL0: POL_27 Mask */
#define GPIO_GROUP_INT1_PORT_POL0_POL_28_Pos                  28                                                        /*!< GPIO_GROUP_INT1 PORT_POL0: POL_28 Position */
#define GPIO_GROUP_INT1_PORT_POL0_POL_28_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_28_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL0: POL_28 Mask */
#define GPIO_GROUP_INT1_PORT_POL0_POL_29_Pos                  29                                                        /*!< GPIO_GROUP_INT1 PORT_POL0: POL_29 Position */
#define GPIO_GROUP_INT1_PORT_POL0_POL_29_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_29_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL0: POL_29 Mask */
#define GPIO_GROUP_INT1_PORT_POL0_POL_30_Pos                  30                                                        /*!< GPIO_GROUP_INT1 PORT_POL0: POL_30 Position */
#define GPIO_GROUP_INT1_PORT_POL0_POL_30_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_30_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL0: POL_30 Mask */
#define GPIO_GROUP_INT1_PORT_POL0_POL_31_Pos                  31                                                        /*!< GPIO_GROUP_INT1 PORT_POL0: POL_31 Position */
#define GPIO_GROUP_INT1_PORT_POL0_POL_31_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_31_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL0: POL_31 Mask */

// --------------------------------  GPIO_GROUP_INT1_PORT_POL1  -----------------------------------
#define GPIO_GROUP_INT1_PORT_POL1_POL_0_Pos                   0                                                         /*!< GPIO_GROUP_INT1 PORT_POL1: POL_0 Position */
#define GPIO_GROUP_INT1_PORT_POL1_POL_0_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_0_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL1: POL_0 Mask */
#define GPIO_GROUP_INT1_PORT_POL1_POL_1_Pos                   1                                                         /*!< GPIO_GROUP_INT1 PORT_POL1: POL_1 Position */
#define GPIO_GROUP_INT1_PORT_POL1_POL_1_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_1_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL1: POL_1 Mask */
#define GPIO_GROUP_INT1_PORT_POL1_POL_2_Pos                   2                                                         /*!< GPIO_GROUP_INT1 PORT_POL1: POL_2 Position */
#define GPIO_GROUP_INT1_PORT_POL1_POL_2_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_2_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL1: POL_2 Mask */
#define GPIO_GROUP_INT1_PORT_POL1_POL_3_Pos                   3                                                         /*!< GPIO_GROUP_INT1 PORT_POL1: POL_3 Position */
#define GPIO_GROUP_INT1_PORT_POL1_POL_3_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_3_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL1: POL_3 Mask */
#define GPIO_GROUP_INT1_PORT_POL1_POL_4_Pos                   4                                                         /*!< GPIO_GROUP_INT1 PORT_POL1: POL_4 Position */
#define GPIO_GROUP_INT1_PORT_POL1_POL_4_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_4_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL1: POL_4 Mask */
#define GPIO_GROUP_INT1_PORT_POL1_POL_5_Pos                   5                                                         /*!< GPIO_GROUP_INT1 PORT_POL1: POL_5 Position */
#define GPIO_GROUP_INT1_PORT_POL1_POL_5_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_5_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL1: POL_5 Mask */
#define GPIO_GROUP_INT1_PORT_POL1_POL_6_Pos                   6                                                         /*!< GPIO_GROUP_INT1 PORT_POL1: POL_6 Position */
#define GPIO_GROUP_INT1_PORT_POL1_POL_6_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_6_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL1: POL_6 Mask */
#define GPIO_GROUP_INT1_PORT_POL1_POL_7_Pos                   7                                                         /*!< GPIO_GROUP_INT1 PORT_POL1: POL_7 Position */
#define GPIO_GROUP_INT1_PORT_POL1_POL_7_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_7_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL1: POL_7 Mask */
#define GPIO_GROUP_INT1_PORT_POL1_POL_8_Pos                   8                                                         /*!< GPIO_GROUP_INT1 PORT_POL1: POL_8 Position */
#define GPIO_GROUP_INT1_PORT_POL1_POL_8_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_8_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL1: POL_8 Mask */
#define GPIO_GROUP_INT1_PORT_POL1_POL_9_Pos                   9                                                         /*!< GPIO_GROUP_INT1 PORT_POL1: POL_9 Position */
#define GPIO_GROUP_INT1_PORT_POL1_POL_9_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_9_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL1: POL_9 Mask */
#define GPIO_GROUP_INT1_PORT_POL1_POL_10_Pos                  10                                                        /*!< GPIO_GROUP_INT1 PORT_POL1: POL_10 Position */
#define GPIO_GROUP_INT1_PORT_POL1_POL_10_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_10_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL1: POL_10 Mask */
#define GPIO_GROUP_INT1_PORT_POL1_POL_11_Pos                  11                                                        /*!< GPIO_GROUP_INT1 PORT_POL1: POL_11 Position */
#define GPIO_GROUP_INT1_PORT_POL1_POL_11_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_11_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL1: POL_11 Mask */
#define GPIO_GROUP_INT1_PORT_POL1_POL_12_Pos                  12                                                        /*!< GPIO_GROUP_INT1 PORT_POL1: POL_12 Position */
#define GPIO_GROUP_INT1_PORT_POL1_POL_12_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_12_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL1: POL_12 Mask */
#define GPIO_GROUP_INT1_PORT_POL1_POL_13_Pos                  13                                                        /*!< GPIO_GROUP_INT1 PORT_POL1: POL_13 Position */
#define GPIO_GROUP_INT1_PORT_POL1_POL_13_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_13_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL1: POL_13 Mask */
#define GPIO_GROUP_INT1_PORT_POL1_POL_14_Pos                  14                                                        /*!< GPIO_GROUP_INT1 PORT_POL1: POL_14 Position */
#define GPIO_GROUP_INT1_PORT_POL1_POL_14_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_14_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL1: POL_14 Mask */
#define GPIO_GROUP_INT1_PORT_POL1_POL_15_Pos                  15                                                        /*!< GPIO_GROUP_INT1 PORT_POL1: POL_15 Position */
#define GPIO_GROUP_INT1_PORT_POL1_POL_15_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_15_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL1: POL_15 Mask */
#define GPIO_GROUP_INT1_PORT_POL1_POL_16_Pos                  16                                                        /*!< GPIO_GROUP_INT1 PORT_POL1: POL_16 Position */
#define GPIO_GROUP_INT1_PORT_POL1_POL_16_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_16_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL1: POL_16 Mask */
#define GPIO_GROUP_INT1_PORT_POL1_POL_17_Pos                  17                                                        /*!< GPIO_GROUP_INT1 PORT_POL1: POL_17 Position */
#define GPIO_GROUP_INT1_PORT_POL1_POL_17_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_17_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL1: POL_17 Mask */
#define GPIO_GROUP_INT1_PORT_POL1_POL_18_Pos                  18                                                        /*!< GPIO_GROUP_INT1 PORT_POL1: POL_18 Position */
#define GPIO_GROUP_INT1_PORT_POL1_POL_18_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_18_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL1: POL_18 Mask */
#define GPIO_GROUP_INT1_PORT_POL1_POL_19_Pos                  19                                                        /*!< GPIO_GROUP_INT1 PORT_POL1: POL_19 Position */
#define GPIO_GROUP_INT1_PORT_POL1_POL_19_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_19_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL1: POL_19 Mask */
#define GPIO_GROUP_INT1_PORT_POL1_POL_20_Pos                  20                                                        /*!< GPIO_GROUP_INT1 PORT_POL1: POL_20 Position */
#define GPIO_GROUP_INT1_PORT_POL1_POL_20_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_20_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL1: POL_20 Mask */
#define GPIO_GROUP_INT1_PORT_POL1_POL_21_Pos                  21                                                        /*!< GPIO_GROUP_INT1 PORT_POL1: POL_21 Position */
#define GPIO_GROUP_INT1_PORT_POL1_POL_21_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_21_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL1: POL_21 Mask */
#define GPIO_GROUP_INT1_PORT_POL1_POL_22_Pos                  22                                                        /*!< GPIO_GROUP_INT1 PORT_POL1: POL_22 Position */
#define GPIO_GROUP_INT1_PORT_POL1_POL_22_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_22_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL1: POL_22 Mask */
#define GPIO_GROUP_INT1_PORT_POL1_POL_23_Pos                  23                                                        /*!< GPIO_GROUP_INT1 PORT_POL1: POL_23 Position */
#define GPIO_GROUP_INT1_PORT_POL1_POL_23_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_23_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL1: POL_23 Mask */
#define GPIO_GROUP_INT1_PORT_POL1_POL_24_Pos                  24                                                        /*!< GPIO_GROUP_INT1 PORT_POL1: POL_24 Position */
#define GPIO_GROUP_INT1_PORT_POL1_POL_24_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_24_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL1: POL_24 Mask */
#define GPIO_GROUP_INT1_PORT_POL1_POL_25_Pos                  25                                                        /*!< GPIO_GROUP_INT1 PORT_POL1: POL_25 Position */
#define GPIO_GROUP_INT1_PORT_POL1_POL_25_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_25_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL1: POL_25 Mask */
#define GPIO_GROUP_INT1_PORT_POL1_POL_26_Pos                  26                                                        /*!< GPIO_GROUP_INT1 PORT_POL1: POL_26 Position */
#define GPIO_GROUP_INT1_PORT_POL1_POL_26_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_26_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL1: POL_26 Mask */
#define GPIO_GROUP_INT1_PORT_POL1_POL_27_Pos                  27                                                        /*!< GPIO_GROUP_INT1 PORT_POL1: POL_27 Position */
#define GPIO_GROUP_INT1_PORT_POL1_POL_27_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_27_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL1: POL_27 Mask */
#define GPIO_GROUP_INT1_PORT_POL1_POL_28_Pos                  28                                                        /*!< GPIO_GROUP_INT1 PORT_POL1: POL_28 Position */
#define GPIO_GROUP_INT1_PORT_POL1_POL_28_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_28_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL1: POL_28 Mask */
#define GPIO_GROUP_INT1_PORT_POL1_POL_29_Pos                  29                                                        /*!< GPIO_GROUP_INT1 PORT_POL1: POL_29 Position */
#define GPIO_GROUP_INT1_PORT_POL1_POL_29_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_29_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL1: POL_29 Mask */
#define GPIO_GROUP_INT1_PORT_POL1_POL_30_Pos                  30                                                        /*!< GPIO_GROUP_INT1 PORT_POL1: POL_30 Position */
#define GPIO_GROUP_INT1_PORT_POL1_POL_30_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_30_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL1: POL_30 Mask */
#define GPIO_GROUP_INT1_PORT_POL1_POL_31_Pos                  31                                                        /*!< GPIO_GROUP_INT1 PORT_POL1: POL_31 Position */
#define GPIO_GROUP_INT1_PORT_POL1_POL_31_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_31_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL1: POL_31 Mask */

// --------------------------------  GPIO_GROUP_INT1_PORT_POL2  -----------------------------------
#define GPIO_GROUP_INT1_PORT_POL2_POL_0_Pos                   0                                                         /*!< GPIO_GROUP_INT1 PORT_POL2: POL_0 Position */
#define GPIO_GROUP_INT1_PORT_POL2_POL_0_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_0_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL2: POL_0 Mask */
#define GPIO_GROUP_INT1_PORT_POL2_POL_1_Pos                   1                                                         /*!< GPIO_GROUP_INT1 PORT_POL2: POL_1 Position */
#define GPIO_GROUP_INT1_PORT_POL2_POL_1_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_1_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL2: POL_1 Mask */
#define GPIO_GROUP_INT1_PORT_POL2_POL_2_Pos                   2                                                         /*!< GPIO_GROUP_INT1 PORT_POL2: POL_2 Position */
#define GPIO_GROUP_INT1_PORT_POL2_POL_2_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_2_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL2: POL_2 Mask */
#define GPIO_GROUP_INT1_PORT_POL2_POL_3_Pos                   3                                                         /*!< GPIO_GROUP_INT1 PORT_POL2: POL_3 Position */
#define GPIO_GROUP_INT1_PORT_POL2_POL_3_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_3_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL2: POL_3 Mask */
#define GPIO_GROUP_INT1_PORT_POL2_POL_4_Pos                   4                                                         /*!< GPIO_GROUP_INT1 PORT_POL2: POL_4 Position */
#define GPIO_GROUP_INT1_PORT_POL2_POL_4_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_4_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL2: POL_4 Mask */
#define GPIO_GROUP_INT1_PORT_POL2_POL_5_Pos                   5                                                         /*!< GPIO_GROUP_INT1 PORT_POL2: POL_5 Position */
#define GPIO_GROUP_INT1_PORT_POL2_POL_5_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_5_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL2: POL_5 Mask */
#define GPIO_GROUP_INT1_PORT_POL2_POL_6_Pos                   6                                                         /*!< GPIO_GROUP_INT1 PORT_POL2: POL_6 Position */
#define GPIO_GROUP_INT1_PORT_POL2_POL_6_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_6_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL2: POL_6 Mask */
#define GPIO_GROUP_INT1_PORT_POL2_POL_7_Pos                   7                                                         /*!< GPIO_GROUP_INT1 PORT_POL2: POL_7 Position */
#define GPIO_GROUP_INT1_PORT_POL2_POL_7_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_7_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL2: POL_7 Mask */
#define GPIO_GROUP_INT1_PORT_POL2_POL_8_Pos                   8                                                         /*!< GPIO_GROUP_INT1 PORT_POL2: POL_8 Position */
#define GPIO_GROUP_INT1_PORT_POL2_POL_8_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_8_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL2: POL_8 Mask */
#define GPIO_GROUP_INT1_PORT_POL2_POL_9_Pos                   9                                                         /*!< GPIO_GROUP_INT1 PORT_POL2: POL_9 Position */
#define GPIO_GROUP_INT1_PORT_POL2_POL_9_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_9_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL2: POL_9 Mask */
#define GPIO_GROUP_INT1_PORT_POL2_POL_10_Pos                  10                                                        /*!< GPIO_GROUP_INT1 PORT_POL2: POL_10 Position */
#define GPIO_GROUP_INT1_PORT_POL2_POL_10_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_10_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL2: POL_10 Mask */
#define GPIO_GROUP_INT1_PORT_POL2_POL_11_Pos                  11                                                        /*!< GPIO_GROUP_INT1 PORT_POL2: POL_11 Position */
#define GPIO_GROUP_INT1_PORT_POL2_POL_11_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_11_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL2: POL_11 Mask */
#define GPIO_GROUP_INT1_PORT_POL2_POL_12_Pos                  12                                                        /*!< GPIO_GROUP_INT1 PORT_POL2: POL_12 Position */
#define GPIO_GROUP_INT1_PORT_POL2_POL_12_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_12_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL2: POL_12 Mask */
#define GPIO_GROUP_INT1_PORT_POL2_POL_13_Pos                  13                                                        /*!< GPIO_GROUP_INT1 PORT_POL2: POL_13 Position */
#define GPIO_GROUP_INT1_PORT_POL2_POL_13_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_13_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL2: POL_13 Mask */
#define GPIO_GROUP_INT1_PORT_POL2_POL_14_Pos                  14                                                        /*!< GPIO_GROUP_INT1 PORT_POL2: POL_14 Position */
#define GPIO_GROUP_INT1_PORT_POL2_POL_14_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_14_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL2: POL_14 Mask */
#define GPIO_GROUP_INT1_PORT_POL2_POL_15_Pos                  15                                                        /*!< GPIO_GROUP_INT1 PORT_POL2: POL_15 Position */
#define GPIO_GROUP_INT1_PORT_POL2_POL_15_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_15_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL2: POL_15 Mask */
#define GPIO_GROUP_INT1_PORT_POL2_POL_16_Pos                  16                                                        /*!< GPIO_GROUP_INT1 PORT_POL2: POL_16 Position */
#define GPIO_GROUP_INT1_PORT_POL2_POL_16_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_16_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL2: POL_16 Mask */
#define GPIO_GROUP_INT1_PORT_POL2_POL_17_Pos                  17                                                        /*!< GPIO_GROUP_INT1 PORT_POL2: POL_17 Position */
#define GPIO_GROUP_INT1_PORT_POL2_POL_17_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_17_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL2: POL_17 Mask */
#define GPIO_GROUP_INT1_PORT_POL2_POL_18_Pos                  18                                                        /*!< GPIO_GROUP_INT1 PORT_POL2: POL_18 Position */
#define GPIO_GROUP_INT1_PORT_POL2_POL_18_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_18_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL2: POL_18 Mask */
#define GPIO_GROUP_INT1_PORT_POL2_POL_19_Pos                  19                                                        /*!< GPIO_GROUP_INT1 PORT_POL2: POL_19 Position */
#define GPIO_GROUP_INT1_PORT_POL2_POL_19_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_19_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL2: POL_19 Mask */
#define GPIO_GROUP_INT1_PORT_POL2_POL_20_Pos                  20                                                        /*!< GPIO_GROUP_INT1 PORT_POL2: POL_20 Position */
#define GPIO_GROUP_INT1_PORT_POL2_POL_20_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_20_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL2: POL_20 Mask */
#define GPIO_GROUP_INT1_PORT_POL2_POL_21_Pos                  21                                                        /*!< GPIO_GROUP_INT1 PORT_POL2: POL_21 Position */
#define GPIO_GROUP_INT1_PORT_POL2_POL_21_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_21_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL2: POL_21 Mask */
#define GPIO_GROUP_INT1_PORT_POL2_POL_22_Pos                  22                                                        /*!< GPIO_GROUP_INT1 PORT_POL2: POL_22 Position */
#define GPIO_GROUP_INT1_PORT_POL2_POL_22_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_22_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL2: POL_22 Mask */
#define GPIO_GROUP_INT1_PORT_POL2_POL_23_Pos                  23                                                        /*!< GPIO_GROUP_INT1 PORT_POL2: POL_23 Position */
#define GPIO_GROUP_INT1_PORT_POL2_POL_23_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_23_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL2: POL_23 Mask */
#define GPIO_GROUP_INT1_PORT_POL2_POL_24_Pos                  24                                                        /*!< GPIO_GROUP_INT1 PORT_POL2: POL_24 Position */
#define GPIO_GROUP_INT1_PORT_POL2_POL_24_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_24_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL2: POL_24 Mask */
#define GPIO_GROUP_INT1_PORT_POL2_POL_25_Pos                  25                                                        /*!< GPIO_GROUP_INT1 PORT_POL2: POL_25 Position */
#define GPIO_GROUP_INT1_PORT_POL2_POL_25_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_25_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL2: POL_25 Mask */
#define GPIO_GROUP_INT1_PORT_POL2_POL_26_Pos                  26                                                        /*!< GPIO_GROUP_INT1 PORT_POL2: POL_26 Position */
#define GPIO_GROUP_INT1_PORT_POL2_POL_26_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_26_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL2: POL_26 Mask */
#define GPIO_GROUP_INT1_PORT_POL2_POL_27_Pos                  27                                                        /*!< GPIO_GROUP_INT1 PORT_POL2: POL_27 Position */
#define GPIO_GROUP_INT1_PORT_POL2_POL_27_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_27_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL2: POL_27 Mask */
#define GPIO_GROUP_INT1_PORT_POL2_POL_28_Pos                  28                                                        /*!< GPIO_GROUP_INT1 PORT_POL2: POL_28 Position */
#define GPIO_GROUP_INT1_PORT_POL2_POL_28_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_28_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL2: POL_28 Mask */
#define GPIO_GROUP_INT1_PORT_POL2_POL_29_Pos                  29                                                        /*!< GPIO_GROUP_INT1 PORT_POL2: POL_29 Position */
#define GPIO_GROUP_INT1_PORT_POL2_POL_29_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_29_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL2: POL_29 Mask */
#define GPIO_GROUP_INT1_PORT_POL2_POL_30_Pos                  30                                                        /*!< GPIO_GROUP_INT1 PORT_POL2: POL_30 Position */
#define GPIO_GROUP_INT1_PORT_POL2_POL_30_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_30_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL2: POL_30 Mask */
#define GPIO_GROUP_INT1_PORT_POL2_POL_31_Pos                  31                                                        /*!< GPIO_GROUP_INT1 PORT_POL2: POL_31 Position */
#define GPIO_GROUP_INT1_PORT_POL2_POL_31_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_31_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL2: POL_31 Mask */

// --------------------------------  GPIO_GROUP_INT1_PORT_POL3  -----------------------------------
#define GPIO_GROUP_INT1_PORT_POL3_POL_0_Pos                   0                                                         /*!< GPIO_GROUP_INT1 PORT_POL3: POL_0 Position */
#define GPIO_GROUP_INT1_PORT_POL3_POL_0_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_0_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL3: POL_0 Mask */
#define GPIO_GROUP_INT1_PORT_POL3_POL_1_Pos                   1                                                         /*!< GPIO_GROUP_INT1 PORT_POL3: POL_1 Position */
#define GPIO_GROUP_INT1_PORT_POL3_POL_1_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_1_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL3: POL_1 Mask */
#define GPIO_GROUP_INT1_PORT_POL3_POL_2_Pos                   2                                                         /*!< GPIO_GROUP_INT1 PORT_POL3: POL_2 Position */
#define GPIO_GROUP_INT1_PORT_POL3_POL_2_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_2_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL3: POL_2 Mask */
#define GPIO_GROUP_INT1_PORT_POL3_POL_3_Pos                   3                                                         /*!< GPIO_GROUP_INT1 PORT_POL3: POL_3 Position */
#define GPIO_GROUP_INT1_PORT_POL3_POL_3_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_3_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL3: POL_3 Mask */
#define GPIO_GROUP_INT1_PORT_POL3_POL_4_Pos                   4                                                         /*!< GPIO_GROUP_INT1 PORT_POL3: POL_4 Position */
#define GPIO_GROUP_INT1_PORT_POL3_POL_4_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_4_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL3: POL_4 Mask */
#define GPIO_GROUP_INT1_PORT_POL3_POL_5_Pos                   5                                                         /*!< GPIO_GROUP_INT1 PORT_POL3: POL_5 Position */
#define GPIO_GROUP_INT1_PORT_POL3_POL_5_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_5_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL3: POL_5 Mask */
#define GPIO_GROUP_INT1_PORT_POL3_POL_6_Pos                   6                                                         /*!< GPIO_GROUP_INT1 PORT_POL3: POL_6 Position */
#define GPIO_GROUP_INT1_PORT_POL3_POL_6_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_6_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL3: POL_6 Mask */
#define GPIO_GROUP_INT1_PORT_POL3_POL_7_Pos                   7                                                         /*!< GPIO_GROUP_INT1 PORT_POL3: POL_7 Position */
#define GPIO_GROUP_INT1_PORT_POL3_POL_7_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_7_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL3: POL_7 Mask */
#define GPIO_GROUP_INT1_PORT_POL3_POL_8_Pos                   8                                                         /*!< GPIO_GROUP_INT1 PORT_POL3: POL_8 Position */
#define GPIO_GROUP_INT1_PORT_POL3_POL_8_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_8_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL3: POL_8 Mask */
#define GPIO_GROUP_INT1_PORT_POL3_POL_9_Pos                   9                                                         /*!< GPIO_GROUP_INT1 PORT_POL3: POL_9 Position */
#define GPIO_GROUP_INT1_PORT_POL3_POL_9_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_9_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL3: POL_9 Mask */
#define GPIO_GROUP_INT1_PORT_POL3_POL_10_Pos                  10                                                        /*!< GPIO_GROUP_INT1 PORT_POL3: POL_10 Position */
#define GPIO_GROUP_INT1_PORT_POL3_POL_10_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_10_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL3: POL_10 Mask */
#define GPIO_GROUP_INT1_PORT_POL3_POL_11_Pos                  11                                                        /*!< GPIO_GROUP_INT1 PORT_POL3: POL_11 Position */
#define GPIO_GROUP_INT1_PORT_POL3_POL_11_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_11_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL3: POL_11 Mask */
#define GPIO_GROUP_INT1_PORT_POL3_POL_12_Pos                  12                                                        /*!< GPIO_GROUP_INT1 PORT_POL3: POL_12 Position */
#define GPIO_GROUP_INT1_PORT_POL3_POL_12_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_12_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL3: POL_12 Mask */
#define GPIO_GROUP_INT1_PORT_POL3_POL_13_Pos                  13                                                        /*!< GPIO_GROUP_INT1 PORT_POL3: POL_13 Position */
#define GPIO_GROUP_INT1_PORT_POL3_POL_13_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_13_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL3: POL_13 Mask */
#define GPIO_GROUP_INT1_PORT_POL3_POL_14_Pos                  14                                                        /*!< GPIO_GROUP_INT1 PORT_POL3: POL_14 Position */
#define GPIO_GROUP_INT1_PORT_POL3_POL_14_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_14_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL3: POL_14 Mask */
#define GPIO_GROUP_INT1_PORT_POL3_POL_15_Pos                  15                                                        /*!< GPIO_GROUP_INT1 PORT_POL3: POL_15 Position */
#define GPIO_GROUP_INT1_PORT_POL3_POL_15_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_15_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL3: POL_15 Mask */
#define GPIO_GROUP_INT1_PORT_POL3_POL_16_Pos                  16                                                        /*!< GPIO_GROUP_INT1 PORT_POL3: POL_16 Position */
#define GPIO_GROUP_INT1_PORT_POL3_POL_16_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_16_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL3: POL_16 Mask */
#define GPIO_GROUP_INT1_PORT_POL3_POL_17_Pos                  17                                                        /*!< GPIO_GROUP_INT1 PORT_POL3: POL_17 Position */
#define GPIO_GROUP_INT1_PORT_POL3_POL_17_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_17_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL3: POL_17 Mask */
#define GPIO_GROUP_INT1_PORT_POL3_POL_18_Pos                  18                                                        /*!< GPIO_GROUP_INT1 PORT_POL3: POL_18 Position */
#define GPIO_GROUP_INT1_PORT_POL3_POL_18_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_18_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL3: POL_18 Mask */
#define GPIO_GROUP_INT1_PORT_POL3_POL_19_Pos                  19                                                        /*!< GPIO_GROUP_INT1 PORT_POL3: POL_19 Position */
#define GPIO_GROUP_INT1_PORT_POL3_POL_19_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_19_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL3: POL_19 Mask */
#define GPIO_GROUP_INT1_PORT_POL3_POL_20_Pos                  20                                                        /*!< GPIO_GROUP_INT1 PORT_POL3: POL_20 Position */
#define GPIO_GROUP_INT1_PORT_POL3_POL_20_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_20_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL3: POL_20 Mask */
#define GPIO_GROUP_INT1_PORT_POL3_POL_21_Pos                  21                                                        /*!< GPIO_GROUP_INT1 PORT_POL3: POL_21 Position */
#define GPIO_GROUP_INT1_PORT_POL3_POL_21_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_21_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL3: POL_21 Mask */
#define GPIO_GROUP_INT1_PORT_POL3_POL_22_Pos                  22                                                        /*!< GPIO_GROUP_INT1 PORT_POL3: POL_22 Position */
#define GPIO_GROUP_INT1_PORT_POL3_POL_22_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_22_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL3: POL_22 Mask */
#define GPIO_GROUP_INT1_PORT_POL3_POL_23_Pos                  23                                                        /*!< GPIO_GROUP_INT1 PORT_POL3: POL_23 Position */
#define GPIO_GROUP_INT1_PORT_POL3_POL_23_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_23_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL3: POL_23 Mask */
#define GPIO_GROUP_INT1_PORT_POL3_POL_24_Pos                  24                                                        /*!< GPIO_GROUP_INT1 PORT_POL3: POL_24 Position */
#define GPIO_GROUP_INT1_PORT_POL3_POL_24_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_24_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL3: POL_24 Mask */
#define GPIO_GROUP_INT1_PORT_POL3_POL_25_Pos                  25                                                        /*!< GPIO_GROUP_INT1 PORT_POL3: POL_25 Position */
#define GPIO_GROUP_INT1_PORT_POL3_POL_25_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_25_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL3: POL_25 Mask */
#define GPIO_GROUP_INT1_PORT_POL3_POL_26_Pos                  26                                                        /*!< GPIO_GROUP_INT1 PORT_POL3: POL_26 Position */
#define GPIO_GROUP_INT1_PORT_POL3_POL_26_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_26_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL3: POL_26 Mask */
#define GPIO_GROUP_INT1_PORT_POL3_POL_27_Pos                  27                                                        /*!< GPIO_GROUP_INT1 PORT_POL3: POL_27 Position */
#define GPIO_GROUP_INT1_PORT_POL3_POL_27_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_27_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL3: POL_27 Mask */
#define GPIO_GROUP_INT1_PORT_POL3_POL_28_Pos                  28                                                        /*!< GPIO_GROUP_INT1 PORT_POL3: POL_28 Position */
#define GPIO_GROUP_INT1_PORT_POL3_POL_28_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_28_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL3: POL_28 Mask */
#define GPIO_GROUP_INT1_PORT_POL3_POL_29_Pos                  29                                                        /*!< GPIO_GROUP_INT1 PORT_POL3: POL_29 Position */
#define GPIO_GROUP_INT1_PORT_POL3_POL_29_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_29_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL3: POL_29 Mask */
#define GPIO_GROUP_INT1_PORT_POL3_POL_30_Pos                  30                                                        /*!< GPIO_GROUP_INT1 PORT_POL3: POL_30 Position */
#define GPIO_GROUP_INT1_PORT_POL3_POL_30_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_30_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL3: POL_30 Mask */
#define GPIO_GROUP_INT1_PORT_POL3_POL_31_Pos                  31                                                        /*!< GPIO_GROUP_INT1 PORT_POL3: POL_31 Position */
#define GPIO_GROUP_INT1_PORT_POL3_POL_31_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_31_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL3: POL_31 Mask */

// --------------------------------  GPIO_GROUP_INT1_PORT_POL4  -----------------------------------
#define GPIO_GROUP_INT1_PORT_POL4_POL_0_Pos                   0                                                         /*!< GPIO_GROUP_INT1 PORT_POL4: POL_0 Position */
#define GPIO_GROUP_INT1_PORT_POL4_POL_0_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_0_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL4: POL_0 Mask */
#define GPIO_GROUP_INT1_PORT_POL4_POL_1_Pos                   1                                                         /*!< GPIO_GROUP_INT1 PORT_POL4: POL_1 Position */
#define GPIO_GROUP_INT1_PORT_POL4_POL_1_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_1_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL4: POL_1 Mask */
#define GPIO_GROUP_INT1_PORT_POL4_POL_2_Pos                   2                                                         /*!< GPIO_GROUP_INT1 PORT_POL4: POL_2 Position */
#define GPIO_GROUP_INT1_PORT_POL4_POL_2_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_2_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL4: POL_2 Mask */
#define GPIO_GROUP_INT1_PORT_POL4_POL_3_Pos                   3                                                         /*!< GPIO_GROUP_INT1 PORT_POL4: POL_3 Position */
#define GPIO_GROUP_INT1_PORT_POL4_POL_3_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_3_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL4: POL_3 Mask */
#define GPIO_GROUP_INT1_PORT_POL4_POL_4_Pos                   4                                                         /*!< GPIO_GROUP_INT1 PORT_POL4: POL_4 Position */
#define GPIO_GROUP_INT1_PORT_POL4_POL_4_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_4_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL4: POL_4 Mask */
#define GPIO_GROUP_INT1_PORT_POL4_POL_5_Pos                   5                                                         /*!< GPIO_GROUP_INT1 PORT_POL4: POL_5 Position */
#define GPIO_GROUP_INT1_PORT_POL4_POL_5_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_5_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL4: POL_5 Mask */
#define GPIO_GROUP_INT1_PORT_POL4_POL_6_Pos                   6                                                         /*!< GPIO_GROUP_INT1 PORT_POL4: POL_6 Position */
#define GPIO_GROUP_INT1_PORT_POL4_POL_6_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_6_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL4: POL_6 Mask */
#define GPIO_GROUP_INT1_PORT_POL4_POL_7_Pos                   7                                                         /*!< GPIO_GROUP_INT1 PORT_POL4: POL_7 Position */
#define GPIO_GROUP_INT1_PORT_POL4_POL_7_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_7_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL4: POL_7 Mask */
#define GPIO_GROUP_INT1_PORT_POL4_POL_8_Pos                   8                                                         /*!< GPIO_GROUP_INT1 PORT_POL4: POL_8 Position */
#define GPIO_GROUP_INT1_PORT_POL4_POL_8_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_8_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL4: POL_8 Mask */
#define GPIO_GROUP_INT1_PORT_POL4_POL_9_Pos                   9                                                         /*!< GPIO_GROUP_INT1 PORT_POL4: POL_9 Position */
#define GPIO_GROUP_INT1_PORT_POL4_POL_9_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_9_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL4: POL_9 Mask */
#define GPIO_GROUP_INT1_PORT_POL4_POL_10_Pos                  10                                                        /*!< GPIO_GROUP_INT1 PORT_POL4: POL_10 Position */
#define GPIO_GROUP_INT1_PORT_POL4_POL_10_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_10_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL4: POL_10 Mask */
#define GPIO_GROUP_INT1_PORT_POL4_POL_11_Pos                  11                                                        /*!< GPIO_GROUP_INT1 PORT_POL4: POL_11 Position */
#define GPIO_GROUP_INT1_PORT_POL4_POL_11_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_11_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL4: POL_11 Mask */
#define GPIO_GROUP_INT1_PORT_POL4_POL_12_Pos                  12                                                        /*!< GPIO_GROUP_INT1 PORT_POL4: POL_12 Position */
#define GPIO_GROUP_INT1_PORT_POL4_POL_12_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_12_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL4: POL_12 Mask */
#define GPIO_GROUP_INT1_PORT_POL4_POL_13_Pos                  13                                                        /*!< GPIO_GROUP_INT1 PORT_POL4: POL_13 Position */
#define GPIO_GROUP_INT1_PORT_POL4_POL_13_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_13_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL4: POL_13 Mask */
#define GPIO_GROUP_INT1_PORT_POL4_POL_14_Pos                  14                                                        /*!< GPIO_GROUP_INT1 PORT_POL4: POL_14 Position */
#define GPIO_GROUP_INT1_PORT_POL4_POL_14_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_14_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL4: POL_14 Mask */
#define GPIO_GROUP_INT1_PORT_POL4_POL_15_Pos                  15                                                        /*!< GPIO_GROUP_INT1 PORT_POL4: POL_15 Position */
#define GPIO_GROUP_INT1_PORT_POL4_POL_15_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_15_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL4: POL_15 Mask */
#define GPIO_GROUP_INT1_PORT_POL4_POL_16_Pos                  16                                                        /*!< GPIO_GROUP_INT1 PORT_POL4: POL_16 Position */
#define GPIO_GROUP_INT1_PORT_POL4_POL_16_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_16_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL4: POL_16 Mask */
#define GPIO_GROUP_INT1_PORT_POL4_POL_17_Pos                  17                                                        /*!< GPIO_GROUP_INT1 PORT_POL4: POL_17 Position */
#define GPIO_GROUP_INT1_PORT_POL4_POL_17_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_17_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL4: POL_17 Mask */
#define GPIO_GROUP_INT1_PORT_POL4_POL_18_Pos                  18                                                        /*!< GPIO_GROUP_INT1 PORT_POL4: POL_18 Position */
#define GPIO_GROUP_INT1_PORT_POL4_POL_18_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_18_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL4: POL_18 Mask */
#define GPIO_GROUP_INT1_PORT_POL4_POL_19_Pos                  19                                                        /*!< GPIO_GROUP_INT1 PORT_POL4: POL_19 Position */
#define GPIO_GROUP_INT1_PORT_POL4_POL_19_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_19_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL4: POL_19 Mask */
#define GPIO_GROUP_INT1_PORT_POL4_POL_20_Pos                  20                                                        /*!< GPIO_GROUP_INT1 PORT_POL4: POL_20 Position */
#define GPIO_GROUP_INT1_PORT_POL4_POL_20_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_20_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL4: POL_20 Mask */
#define GPIO_GROUP_INT1_PORT_POL4_POL_21_Pos                  21                                                        /*!< GPIO_GROUP_INT1 PORT_POL4: POL_21 Position */
#define GPIO_GROUP_INT1_PORT_POL4_POL_21_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_21_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL4: POL_21 Mask */
#define GPIO_GROUP_INT1_PORT_POL4_POL_22_Pos                  22                                                        /*!< GPIO_GROUP_INT1 PORT_POL4: POL_22 Position */
#define GPIO_GROUP_INT1_PORT_POL4_POL_22_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_22_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL4: POL_22 Mask */
#define GPIO_GROUP_INT1_PORT_POL4_POL_23_Pos                  23                                                        /*!< GPIO_GROUP_INT1 PORT_POL4: POL_23 Position */
#define GPIO_GROUP_INT1_PORT_POL4_POL_23_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_23_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL4: POL_23 Mask */
#define GPIO_GROUP_INT1_PORT_POL4_POL_24_Pos                  24                                                        /*!< GPIO_GROUP_INT1 PORT_POL4: POL_24 Position */
#define GPIO_GROUP_INT1_PORT_POL4_POL_24_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_24_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL4: POL_24 Mask */
#define GPIO_GROUP_INT1_PORT_POL4_POL_25_Pos                  25                                                        /*!< GPIO_GROUP_INT1 PORT_POL4: POL_25 Position */
#define GPIO_GROUP_INT1_PORT_POL4_POL_25_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_25_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL4: POL_25 Mask */
#define GPIO_GROUP_INT1_PORT_POL4_POL_26_Pos                  26                                                        /*!< GPIO_GROUP_INT1 PORT_POL4: POL_26 Position */
#define GPIO_GROUP_INT1_PORT_POL4_POL_26_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_26_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL4: POL_26 Mask */
#define GPIO_GROUP_INT1_PORT_POL4_POL_27_Pos                  27                                                        /*!< GPIO_GROUP_INT1 PORT_POL4: POL_27 Position */
#define GPIO_GROUP_INT1_PORT_POL4_POL_27_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_27_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL4: POL_27 Mask */
#define GPIO_GROUP_INT1_PORT_POL4_POL_28_Pos                  28                                                        /*!< GPIO_GROUP_INT1 PORT_POL4: POL_28 Position */
#define GPIO_GROUP_INT1_PORT_POL4_POL_28_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_28_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL4: POL_28 Mask */
#define GPIO_GROUP_INT1_PORT_POL4_POL_29_Pos                  29                                                        /*!< GPIO_GROUP_INT1 PORT_POL4: POL_29 Position */
#define GPIO_GROUP_INT1_PORT_POL4_POL_29_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_29_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL4: POL_29 Mask */
#define GPIO_GROUP_INT1_PORT_POL4_POL_30_Pos                  30                                                        /*!< GPIO_GROUP_INT1 PORT_POL4: POL_30 Position */
#define GPIO_GROUP_INT1_PORT_POL4_POL_30_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_30_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL4: POL_30 Mask */
#define GPIO_GROUP_INT1_PORT_POL4_POL_31_Pos                  31                                                        /*!< GPIO_GROUP_INT1 PORT_POL4: POL_31 Position */
#define GPIO_GROUP_INT1_PORT_POL4_POL_31_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_31_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL4: POL_31 Mask */

// --------------------------------  GPIO_GROUP_INT1_PORT_POL5  -----------------------------------
#define GPIO_GROUP_INT1_PORT_POL5_POL_0_Pos                   0                                                         /*!< GPIO_GROUP_INT1 PORT_POL5: POL_0 Position */
#define GPIO_GROUP_INT1_PORT_POL5_POL_0_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_0_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL5: POL_0 Mask */
#define GPIO_GROUP_INT1_PORT_POL5_POL_1_Pos                   1                                                         /*!< GPIO_GROUP_INT1 PORT_POL5: POL_1 Position */
#define GPIO_GROUP_INT1_PORT_POL5_POL_1_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_1_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL5: POL_1 Mask */
#define GPIO_GROUP_INT1_PORT_POL5_POL_2_Pos                   2                                                         /*!< GPIO_GROUP_INT1 PORT_POL5: POL_2 Position */
#define GPIO_GROUP_INT1_PORT_POL5_POL_2_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_2_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL5: POL_2 Mask */
#define GPIO_GROUP_INT1_PORT_POL5_POL_3_Pos                   3                                                         /*!< GPIO_GROUP_INT1 PORT_POL5: POL_3 Position */
#define GPIO_GROUP_INT1_PORT_POL5_POL_3_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_3_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL5: POL_3 Mask */
#define GPIO_GROUP_INT1_PORT_POL5_POL_4_Pos                   4                                                         /*!< GPIO_GROUP_INT1 PORT_POL5: POL_4 Position */
#define GPIO_GROUP_INT1_PORT_POL5_POL_4_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_4_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL5: POL_4 Mask */
#define GPIO_GROUP_INT1_PORT_POL5_POL_5_Pos                   5                                                         /*!< GPIO_GROUP_INT1 PORT_POL5: POL_5 Position */
#define GPIO_GROUP_INT1_PORT_POL5_POL_5_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_5_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL5: POL_5 Mask */
#define GPIO_GROUP_INT1_PORT_POL5_POL_6_Pos                   6                                                         /*!< GPIO_GROUP_INT1 PORT_POL5: POL_6 Position */
#define GPIO_GROUP_INT1_PORT_POL5_POL_6_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_6_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL5: POL_6 Mask */
#define GPIO_GROUP_INT1_PORT_POL5_POL_7_Pos                   7                                                         /*!< GPIO_GROUP_INT1 PORT_POL5: POL_7 Position */
#define GPIO_GROUP_INT1_PORT_POL5_POL_7_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_7_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL5: POL_7 Mask */
#define GPIO_GROUP_INT1_PORT_POL5_POL_8_Pos                   8                                                         /*!< GPIO_GROUP_INT1 PORT_POL5: POL_8 Position */
#define GPIO_GROUP_INT1_PORT_POL5_POL_8_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_8_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL5: POL_8 Mask */
#define GPIO_GROUP_INT1_PORT_POL5_POL_9_Pos                   9                                                         /*!< GPIO_GROUP_INT1 PORT_POL5: POL_9 Position */
#define GPIO_GROUP_INT1_PORT_POL5_POL_9_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_9_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL5: POL_9 Mask */
#define GPIO_GROUP_INT1_PORT_POL5_POL_10_Pos                  10                                                        /*!< GPIO_GROUP_INT1 PORT_POL5: POL_10 Position */
#define GPIO_GROUP_INT1_PORT_POL5_POL_10_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_10_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL5: POL_10 Mask */
#define GPIO_GROUP_INT1_PORT_POL5_POL_11_Pos                  11                                                        /*!< GPIO_GROUP_INT1 PORT_POL5: POL_11 Position */
#define GPIO_GROUP_INT1_PORT_POL5_POL_11_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_11_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL5: POL_11 Mask */
#define GPIO_GROUP_INT1_PORT_POL5_POL_12_Pos                  12                                                        /*!< GPIO_GROUP_INT1 PORT_POL5: POL_12 Position */
#define GPIO_GROUP_INT1_PORT_POL5_POL_12_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_12_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL5: POL_12 Mask */
#define GPIO_GROUP_INT1_PORT_POL5_POL_13_Pos                  13                                                        /*!< GPIO_GROUP_INT1 PORT_POL5: POL_13 Position */
#define GPIO_GROUP_INT1_PORT_POL5_POL_13_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_13_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL5: POL_13 Mask */
#define GPIO_GROUP_INT1_PORT_POL5_POL_14_Pos                  14                                                        /*!< GPIO_GROUP_INT1 PORT_POL5: POL_14 Position */
#define GPIO_GROUP_INT1_PORT_POL5_POL_14_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_14_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL5: POL_14 Mask */
#define GPIO_GROUP_INT1_PORT_POL5_POL_15_Pos                  15                                                        /*!< GPIO_GROUP_INT1 PORT_POL5: POL_15 Position */
#define GPIO_GROUP_INT1_PORT_POL5_POL_15_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_15_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL5: POL_15 Mask */
#define GPIO_GROUP_INT1_PORT_POL5_POL_16_Pos                  16                                                        /*!< GPIO_GROUP_INT1 PORT_POL5: POL_16 Position */
#define GPIO_GROUP_INT1_PORT_POL5_POL_16_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_16_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL5: POL_16 Mask */
#define GPIO_GROUP_INT1_PORT_POL5_POL_17_Pos                  17                                                        /*!< GPIO_GROUP_INT1 PORT_POL5: POL_17 Position */
#define GPIO_GROUP_INT1_PORT_POL5_POL_17_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_17_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL5: POL_17 Mask */
#define GPIO_GROUP_INT1_PORT_POL5_POL_18_Pos                  18                                                        /*!< GPIO_GROUP_INT1 PORT_POL5: POL_18 Position */
#define GPIO_GROUP_INT1_PORT_POL5_POL_18_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_18_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL5: POL_18 Mask */
#define GPIO_GROUP_INT1_PORT_POL5_POL_19_Pos                  19                                                        /*!< GPIO_GROUP_INT1 PORT_POL5: POL_19 Position */
#define GPIO_GROUP_INT1_PORT_POL5_POL_19_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_19_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL5: POL_19 Mask */
#define GPIO_GROUP_INT1_PORT_POL5_POL_20_Pos                  20                                                        /*!< GPIO_GROUP_INT1 PORT_POL5: POL_20 Position */
#define GPIO_GROUP_INT1_PORT_POL5_POL_20_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_20_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL5: POL_20 Mask */
#define GPIO_GROUP_INT1_PORT_POL5_POL_21_Pos                  21                                                        /*!< GPIO_GROUP_INT1 PORT_POL5: POL_21 Position */
#define GPIO_GROUP_INT1_PORT_POL5_POL_21_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_21_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL5: POL_21 Mask */
#define GPIO_GROUP_INT1_PORT_POL5_POL_22_Pos                  22                                                        /*!< GPIO_GROUP_INT1 PORT_POL5: POL_22 Position */
#define GPIO_GROUP_INT1_PORT_POL5_POL_22_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_22_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL5: POL_22 Mask */
#define GPIO_GROUP_INT1_PORT_POL5_POL_23_Pos                  23                                                        /*!< GPIO_GROUP_INT1 PORT_POL5: POL_23 Position */
#define GPIO_GROUP_INT1_PORT_POL5_POL_23_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_23_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL5: POL_23 Mask */
#define GPIO_GROUP_INT1_PORT_POL5_POL_24_Pos                  24                                                        /*!< GPIO_GROUP_INT1 PORT_POL5: POL_24 Position */
#define GPIO_GROUP_INT1_PORT_POL5_POL_24_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_24_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL5: POL_24 Mask */
#define GPIO_GROUP_INT1_PORT_POL5_POL_25_Pos                  25                                                        /*!< GPIO_GROUP_INT1 PORT_POL5: POL_25 Position */
#define GPIO_GROUP_INT1_PORT_POL5_POL_25_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_25_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL5: POL_25 Mask */
#define GPIO_GROUP_INT1_PORT_POL5_POL_26_Pos                  26                                                        /*!< GPIO_GROUP_INT1 PORT_POL5: POL_26 Position */
#define GPIO_GROUP_INT1_PORT_POL5_POL_26_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_26_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL5: POL_26 Mask */
#define GPIO_GROUP_INT1_PORT_POL5_POL_27_Pos                  27                                                        /*!< GPIO_GROUP_INT1 PORT_POL5: POL_27 Position */
#define GPIO_GROUP_INT1_PORT_POL5_POL_27_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_27_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL5: POL_27 Mask */
#define GPIO_GROUP_INT1_PORT_POL5_POL_28_Pos                  28                                                        /*!< GPIO_GROUP_INT1 PORT_POL5: POL_28 Position */
#define GPIO_GROUP_INT1_PORT_POL5_POL_28_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_28_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL5: POL_28 Mask */
#define GPIO_GROUP_INT1_PORT_POL5_POL_29_Pos                  29                                                        /*!< GPIO_GROUP_INT1 PORT_POL5: POL_29 Position */
#define GPIO_GROUP_INT1_PORT_POL5_POL_29_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_29_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL5: POL_29 Mask */
#define GPIO_GROUP_INT1_PORT_POL5_POL_30_Pos                  30                                                        /*!< GPIO_GROUP_INT1 PORT_POL5: POL_30 Position */
#define GPIO_GROUP_INT1_PORT_POL5_POL_30_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_30_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL5: POL_30 Mask */
#define GPIO_GROUP_INT1_PORT_POL5_POL_31_Pos                  31                                                        /*!< GPIO_GROUP_INT1 PORT_POL5: POL_31 Position */
#define GPIO_GROUP_INT1_PORT_POL5_POL_31_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_31_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL5: POL_31 Mask */

// --------------------------------  GPIO_GROUP_INT1_PORT_POL6  -----------------------------------
#define GPIO_GROUP_INT1_PORT_POL6_POL_0_Pos                   0                                                         /*!< GPIO_GROUP_INT1 PORT_POL6: POL_0 Position */
#define GPIO_GROUP_INT1_PORT_POL6_POL_0_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_0_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL6: POL_0 Mask */
#define GPIO_GROUP_INT1_PORT_POL6_POL_1_Pos                   1                                                         /*!< GPIO_GROUP_INT1 PORT_POL6: POL_1 Position */
#define GPIO_GROUP_INT1_PORT_POL6_POL_1_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_1_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL6: POL_1 Mask */
#define GPIO_GROUP_INT1_PORT_POL6_POL_2_Pos                   2                                                         /*!< GPIO_GROUP_INT1 PORT_POL6: POL_2 Position */
#define GPIO_GROUP_INT1_PORT_POL6_POL_2_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_2_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL6: POL_2 Mask */
#define GPIO_GROUP_INT1_PORT_POL6_POL_3_Pos                   3                                                         /*!< GPIO_GROUP_INT1 PORT_POL6: POL_3 Position */
#define GPIO_GROUP_INT1_PORT_POL6_POL_3_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_3_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL6: POL_3 Mask */
#define GPIO_GROUP_INT1_PORT_POL6_POL_4_Pos                   4                                                         /*!< GPIO_GROUP_INT1 PORT_POL6: POL_4 Position */
#define GPIO_GROUP_INT1_PORT_POL6_POL_4_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_4_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL6: POL_4 Mask */
#define GPIO_GROUP_INT1_PORT_POL6_POL_5_Pos                   5                                                         /*!< GPIO_GROUP_INT1 PORT_POL6: POL_5 Position */
#define GPIO_GROUP_INT1_PORT_POL6_POL_5_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_5_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL6: POL_5 Mask */
#define GPIO_GROUP_INT1_PORT_POL6_POL_6_Pos                   6                                                         /*!< GPIO_GROUP_INT1 PORT_POL6: POL_6 Position */
#define GPIO_GROUP_INT1_PORT_POL6_POL_6_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_6_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL6: POL_6 Mask */
#define GPIO_GROUP_INT1_PORT_POL6_POL_7_Pos                   7                                                         /*!< GPIO_GROUP_INT1 PORT_POL6: POL_7 Position */
#define GPIO_GROUP_INT1_PORT_POL6_POL_7_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_7_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL6: POL_7 Mask */
#define GPIO_GROUP_INT1_PORT_POL6_POL_8_Pos                   8                                                         /*!< GPIO_GROUP_INT1 PORT_POL6: POL_8 Position */
#define GPIO_GROUP_INT1_PORT_POL6_POL_8_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_8_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL6: POL_8 Mask */
#define GPIO_GROUP_INT1_PORT_POL6_POL_9_Pos                   9                                                         /*!< GPIO_GROUP_INT1 PORT_POL6: POL_9 Position */
#define GPIO_GROUP_INT1_PORT_POL6_POL_9_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_9_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL6: POL_9 Mask */
#define GPIO_GROUP_INT1_PORT_POL6_POL_10_Pos                  10                                                        /*!< GPIO_GROUP_INT1 PORT_POL6: POL_10 Position */
#define GPIO_GROUP_INT1_PORT_POL6_POL_10_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_10_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL6: POL_10 Mask */
#define GPIO_GROUP_INT1_PORT_POL6_POL_11_Pos                  11                                                        /*!< GPIO_GROUP_INT1 PORT_POL6: POL_11 Position */
#define GPIO_GROUP_INT1_PORT_POL6_POL_11_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_11_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL6: POL_11 Mask */
#define GPIO_GROUP_INT1_PORT_POL6_POL_12_Pos                  12                                                        /*!< GPIO_GROUP_INT1 PORT_POL6: POL_12 Position */
#define GPIO_GROUP_INT1_PORT_POL6_POL_12_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_12_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL6: POL_12 Mask */
#define GPIO_GROUP_INT1_PORT_POL6_POL_13_Pos                  13                                                        /*!< GPIO_GROUP_INT1 PORT_POL6: POL_13 Position */
#define GPIO_GROUP_INT1_PORT_POL6_POL_13_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_13_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL6: POL_13 Mask */
#define GPIO_GROUP_INT1_PORT_POL6_POL_14_Pos                  14                                                        /*!< GPIO_GROUP_INT1 PORT_POL6: POL_14 Position */
#define GPIO_GROUP_INT1_PORT_POL6_POL_14_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_14_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL6: POL_14 Mask */
#define GPIO_GROUP_INT1_PORT_POL6_POL_15_Pos                  15                                                        /*!< GPIO_GROUP_INT1 PORT_POL6: POL_15 Position */
#define GPIO_GROUP_INT1_PORT_POL6_POL_15_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_15_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL6: POL_15 Mask */
#define GPIO_GROUP_INT1_PORT_POL6_POL_16_Pos                  16                                                        /*!< GPIO_GROUP_INT1 PORT_POL6: POL_16 Position */
#define GPIO_GROUP_INT1_PORT_POL6_POL_16_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_16_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL6: POL_16 Mask */
#define GPIO_GROUP_INT1_PORT_POL6_POL_17_Pos                  17                                                        /*!< GPIO_GROUP_INT1 PORT_POL6: POL_17 Position */
#define GPIO_GROUP_INT1_PORT_POL6_POL_17_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_17_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL6: POL_17 Mask */
#define GPIO_GROUP_INT1_PORT_POL6_POL_18_Pos                  18                                                        /*!< GPIO_GROUP_INT1 PORT_POL6: POL_18 Position */
#define GPIO_GROUP_INT1_PORT_POL6_POL_18_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_18_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL6: POL_18 Mask */
#define GPIO_GROUP_INT1_PORT_POL6_POL_19_Pos                  19                                                        /*!< GPIO_GROUP_INT1 PORT_POL6: POL_19 Position */
#define GPIO_GROUP_INT1_PORT_POL6_POL_19_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_19_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL6: POL_19 Mask */
#define GPIO_GROUP_INT1_PORT_POL6_POL_20_Pos                  20                                                        /*!< GPIO_GROUP_INT1 PORT_POL6: POL_20 Position */
#define GPIO_GROUP_INT1_PORT_POL6_POL_20_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_20_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL6: POL_20 Mask */
#define GPIO_GROUP_INT1_PORT_POL6_POL_21_Pos                  21                                                        /*!< GPIO_GROUP_INT1 PORT_POL6: POL_21 Position */
#define GPIO_GROUP_INT1_PORT_POL6_POL_21_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_21_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL6: POL_21 Mask */
#define GPIO_GROUP_INT1_PORT_POL6_POL_22_Pos                  22                                                        /*!< GPIO_GROUP_INT1 PORT_POL6: POL_22 Position */
#define GPIO_GROUP_INT1_PORT_POL6_POL_22_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_22_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL6: POL_22 Mask */
#define GPIO_GROUP_INT1_PORT_POL6_POL_23_Pos                  23                                                        /*!< GPIO_GROUP_INT1 PORT_POL6: POL_23 Position */
#define GPIO_GROUP_INT1_PORT_POL6_POL_23_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_23_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL6: POL_23 Mask */
#define GPIO_GROUP_INT1_PORT_POL6_POL_24_Pos                  24                                                        /*!< GPIO_GROUP_INT1 PORT_POL6: POL_24 Position */
#define GPIO_GROUP_INT1_PORT_POL6_POL_24_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_24_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL6: POL_24 Mask */
#define GPIO_GROUP_INT1_PORT_POL6_POL_25_Pos                  25                                                        /*!< GPIO_GROUP_INT1 PORT_POL6: POL_25 Position */
#define GPIO_GROUP_INT1_PORT_POL6_POL_25_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_25_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL6: POL_25 Mask */
#define GPIO_GROUP_INT1_PORT_POL6_POL_26_Pos                  26                                                        /*!< GPIO_GROUP_INT1 PORT_POL6: POL_26 Position */
#define GPIO_GROUP_INT1_PORT_POL6_POL_26_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_26_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL6: POL_26 Mask */
#define GPIO_GROUP_INT1_PORT_POL6_POL_27_Pos                  27                                                        /*!< GPIO_GROUP_INT1 PORT_POL6: POL_27 Position */
#define GPIO_GROUP_INT1_PORT_POL6_POL_27_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_27_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL6: POL_27 Mask */
#define GPIO_GROUP_INT1_PORT_POL6_POL_28_Pos                  28                                                        /*!< GPIO_GROUP_INT1 PORT_POL6: POL_28 Position */
#define GPIO_GROUP_INT1_PORT_POL6_POL_28_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_28_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL6: POL_28 Mask */
#define GPIO_GROUP_INT1_PORT_POL6_POL_29_Pos                  29                                                        /*!< GPIO_GROUP_INT1 PORT_POL6: POL_29 Position */
#define GPIO_GROUP_INT1_PORT_POL6_POL_29_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_29_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL6: POL_29 Mask */
#define GPIO_GROUP_INT1_PORT_POL6_POL_30_Pos                  30                                                        /*!< GPIO_GROUP_INT1 PORT_POL6: POL_30 Position */
#define GPIO_GROUP_INT1_PORT_POL6_POL_30_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_30_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL6: POL_30 Mask */
#define GPIO_GROUP_INT1_PORT_POL6_POL_31_Pos                  31                                                        /*!< GPIO_GROUP_INT1 PORT_POL6: POL_31 Position */
#define GPIO_GROUP_INT1_PORT_POL6_POL_31_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_31_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL6: POL_31 Mask */

// --------------------------------  GPIO_GROUP_INT1_PORT_POL7  -----------------------------------
#define GPIO_GROUP_INT1_PORT_POL7_POL_0_Pos                   0                                                         /*!< GPIO_GROUP_INT1 PORT_POL7: POL_0 Position */
#define GPIO_GROUP_INT1_PORT_POL7_POL_0_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_0_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL7: POL_0 Mask */
#define GPIO_GROUP_INT1_PORT_POL7_POL_1_Pos                   1                                                         /*!< GPIO_GROUP_INT1 PORT_POL7: POL_1 Position */
#define GPIO_GROUP_INT1_PORT_POL7_POL_1_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_1_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL7: POL_1 Mask */
#define GPIO_GROUP_INT1_PORT_POL7_POL_2_Pos                   2                                                         /*!< GPIO_GROUP_INT1 PORT_POL7: POL_2 Position */
#define GPIO_GROUP_INT1_PORT_POL7_POL_2_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_2_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL7: POL_2 Mask */
#define GPIO_GROUP_INT1_PORT_POL7_POL_3_Pos                   3                                                         /*!< GPIO_GROUP_INT1 PORT_POL7: POL_3 Position */
#define GPIO_GROUP_INT1_PORT_POL7_POL_3_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_3_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL7: POL_3 Mask */
#define GPIO_GROUP_INT1_PORT_POL7_POL_4_Pos                   4                                                         /*!< GPIO_GROUP_INT1 PORT_POL7: POL_4 Position */
#define GPIO_GROUP_INT1_PORT_POL7_POL_4_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_4_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL7: POL_4 Mask */
#define GPIO_GROUP_INT1_PORT_POL7_POL_5_Pos                   5                                                         /*!< GPIO_GROUP_INT1 PORT_POL7: POL_5 Position */
#define GPIO_GROUP_INT1_PORT_POL7_POL_5_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_5_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL7: POL_5 Mask */
#define GPIO_GROUP_INT1_PORT_POL7_POL_6_Pos                   6                                                         /*!< GPIO_GROUP_INT1 PORT_POL7: POL_6 Position */
#define GPIO_GROUP_INT1_PORT_POL7_POL_6_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_6_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL7: POL_6 Mask */
#define GPIO_GROUP_INT1_PORT_POL7_POL_7_Pos                   7                                                         /*!< GPIO_GROUP_INT1 PORT_POL7: POL_7 Position */
#define GPIO_GROUP_INT1_PORT_POL7_POL_7_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_7_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL7: POL_7 Mask */
#define GPIO_GROUP_INT1_PORT_POL7_POL_8_Pos                   8                                                         /*!< GPIO_GROUP_INT1 PORT_POL7: POL_8 Position */
#define GPIO_GROUP_INT1_PORT_POL7_POL_8_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_8_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL7: POL_8 Mask */
#define GPIO_GROUP_INT1_PORT_POL7_POL_9_Pos                   9                                                         /*!< GPIO_GROUP_INT1 PORT_POL7: POL_9 Position */
#define GPIO_GROUP_INT1_PORT_POL7_POL_9_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_9_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL7: POL_9 Mask */
#define GPIO_GROUP_INT1_PORT_POL7_POL_10_Pos                  10                                                        /*!< GPIO_GROUP_INT1 PORT_POL7: POL_10 Position */
#define GPIO_GROUP_INT1_PORT_POL7_POL_10_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_10_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL7: POL_10 Mask */
#define GPIO_GROUP_INT1_PORT_POL7_POL_11_Pos                  11                                                        /*!< GPIO_GROUP_INT1 PORT_POL7: POL_11 Position */
#define GPIO_GROUP_INT1_PORT_POL7_POL_11_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_11_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL7: POL_11 Mask */
#define GPIO_GROUP_INT1_PORT_POL7_POL_12_Pos                  12                                                        /*!< GPIO_GROUP_INT1 PORT_POL7: POL_12 Position */
#define GPIO_GROUP_INT1_PORT_POL7_POL_12_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_12_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL7: POL_12 Mask */
#define GPIO_GROUP_INT1_PORT_POL7_POL_13_Pos                  13                                                        /*!< GPIO_GROUP_INT1 PORT_POL7: POL_13 Position */
#define GPIO_GROUP_INT1_PORT_POL7_POL_13_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_13_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL7: POL_13 Mask */
#define GPIO_GROUP_INT1_PORT_POL7_POL_14_Pos                  14                                                        /*!< GPIO_GROUP_INT1 PORT_POL7: POL_14 Position */
#define GPIO_GROUP_INT1_PORT_POL7_POL_14_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_14_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL7: POL_14 Mask */
#define GPIO_GROUP_INT1_PORT_POL7_POL_15_Pos                  15                                                        /*!< GPIO_GROUP_INT1 PORT_POL7: POL_15 Position */
#define GPIO_GROUP_INT1_PORT_POL7_POL_15_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_15_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL7: POL_15 Mask */
#define GPIO_GROUP_INT1_PORT_POL7_POL_16_Pos                  16                                                        /*!< GPIO_GROUP_INT1 PORT_POL7: POL_16 Position */
#define GPIO_GROUP_INT1_PORT_POL7_POL_16_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_16_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL7: POL_16 Mask */
#define GPIO_GROUP_INT1_PORT_POL7_POL_17_Pos                  17                                                        /*!< GPIO_GROUP_INT1 PORT_POL7: POL_17 Position */
#define GPIO_GROUP_INT1_PORT_POL7_POL_17_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_17_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL7: POL_17 Mask */
#define GPIO_GROUP_INT1_PORT_POL7_POL_18_Pos                  18                                                        /*!< GPIO_GROUP_INT1 PORT_POL7: POL_18 Position */
#define GPIO_GROUP_INT1_PORT_POL7_POL_18_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_18_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL7: POL_18 Mask */
#define GPIO_GROUP_INT1_PORT_POL7_POL_19_Pos                  19                                                        /*!< GPIO_GROUP_INT1 PORT_POL7: POL_19 Position */
#define GPIO_GROUP_INT1_PORT_POL7_POL_19_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_19_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL7: POL_19 Mask */
#define GPIO_GROUP_INT1_PORT_POL7_POL_20_Pos                  20                                                        /*!< GPIO_GROUP_INT1 PORT_POL7: POL_20 Position */
#define GPIO_GROUP_INT1_PORT_POL7_POL_20_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_20_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL7: POL_20 Mask */
#define GPIO_GROUP_INT1_PORT_POL7_POL_21_Pos                  21                                                        /*!< GPIO_GROUP_INT1 PORT_POL7: POL_21 Position */
#define GPIO_GROUP_INT1_PORT_POL7_POL_21_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_21_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL7: POL_21 Mask */
#define GPIO_GROUP_INT1_PORT_POL7_POL_22_Pos                  22                                                        /*!< GPIO_GROUP_INT1 PORT_POL7: POL_22 Position */
#define GPIO_GROUP_INT1_PORT_POL7_POL_22_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_22_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL7: POL_22 Mask */
#define GPIO_GROUP_INT1_PORT_POL7_POL_23_Pos                  23                                                        /*!< GPIO_GROUP_INT1 PORT_POL7: POL_23 Position */
#define GPIO_GROUP_INT1_PORT_POL7_POL_23_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_23_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL7: POL_23 Mask */
#define GPIO_GROUP_INT1_PORT_POL7_POL_24_Pos                  24                                                        /*!< GPIO_GROUP_INT1 PORT_POL7: POL_24 Position */
#define GPIO_GROUP_INT1_PORT_POL7_POL_24_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_24_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL7: POL_24 Mask */
#define GPIO_GROUP_INT1_PORT_POL7_POL_25_Pos                  25                                                        /*!< GPIO_GROUP_INT1 PORT_POL7: POL_25 Position */
#define GPIO_GROUP_INT1_PORT_POL7_POL_25_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_25_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL7: POL_25 Mask */
#define GPIO_GROUP_INT1_PORT_POL7_POL_26_Pos                  26                                                        /*!< GPIO_GROUP_INT1 PORT_POL7: POL_26 Position */
#define GPIO_GROUP_INT1_PORT_POL7_POL_26_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_26_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL7: POL_26 Mask */
#define GPIO_GROUP_INT1_PORT_POL7_POL_27_Pos                  27                                                        /*!< GPIO_GROUP_INT1 PORT_POL7: POL_27 Position */
#define GPIO_GROUP_INT1_PORT_POL7_POL_27_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_27_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL7: POL_27 Mask */
#define GPIO_GROUP_INT1_PORT_POL7_POL_28_Pos                  28                                                        /*!< GPIO_GROUP_INT1 PORT_POL7: POL_28 Position */
#define GPIO_GROUP_INT1_PORT_POL7_POL_28_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_28_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL7: POL_28 Mask */
#define GPIO_GROUP_INT1_PORT_POL7_POL_29_Pos                  29                                                        /*!< GPIO_GROUP_INT1 PORT_POL7: POL_29 Position */
#define GPIO_GROUP_INT1_PORT_POL7_POL_29_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_29_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL7: POL_29 Mask */
#define GPIO_GROUP_INT1_PORT_POL7_POL_30_Pos                  30                                                        /*!< GPIO_GROUP_INT1 PORT_POL7: POL_30 Position */
#define GPIO_GROUP_INT1_PORT_POL7_POL_30_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_30_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL7: POL_30 Mask */
#define GPIO_GROUP_INT1_PORT_POL7_POL_31_Pos                  31                                                        /*!< GPIO_GROUP_INT1 PORT_POL7: POL_31 Position */
#define GPIO_GROUP_INT1_PORT_POL7_POL_31_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_31_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL7: POL_31 Mask */

// --------------------------------  GPIO_GROUP_INT1_PORT_ENA0  -----------------------------------
#define GPIO_GROUP_INT1_PORT_ENA0_ENA_0_Pos                   0                                                         /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_0 Position */
#define GPIO_GROUP_INT1_PORT_ENA0_ENA_0_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_0_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_0 Mask */
#define GPIO_GROUP_INT1_PORT_ENA0_ENA_1_Pos                   1                                                         /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_1 Position */
#define GPIO_GROUP_INT1_PORT_ENA0_ENA_1_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_1_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_1 Mask */
#define GPIO_GROUP_INT1_PORT_ENA0_ENA_2_Pos                   2                                                         /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_2 Position */
#define GPIO_GROUP_INT1_PORT_ENA0_ENA_2_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_2_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_2 Mask */
#define GPIO_GROUP_INT1_PORT_ENA0_ENA_3_Pos                   3                                                         /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_3 Position */
#define GPIO_GROUP_INT1_PORT_ENA0_ENA_3_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_3_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_3 Mask */
#define GPIO_GROUP_INT1_PORT_ENA0_ENA_4_Pos                   4                                                         /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_4 Position */
#define GPIO_GROUP_INT1_PORT_ENA0_ENA_4_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_4_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_4 Mask */
#define GPIO_GROUP_INT1_PORT_ENA0_ENA_5_Pos                   5                                                         /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_5 Position */
#define GPIO_GROUP_INT1_PORT_ENA0_ENA_5_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_5_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_5 Mask */
#define GPIO_GROUP_INT1_PORT_ENA0_ENA_6_Pos                   6                                                         /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_6 Position */
#define GPIO_GROUP_INT1_PORT_ENA0_ENA_6_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_6_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_6 Mask */
#define GPIO_GROUP_INT1_PORT_ENA0_ENA_7_Pos                   7                                                         /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_7 Position */
#define GPIO_GROUP_INT1_PORT_ENA0_ENA_7_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_7_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_7 Mask */
#define GPIO_GROUP_INT1_PORT_ENA0_ENA_8_Pos                   8                                                         /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_8 Position */
#define GPIO_GROUP_INT1_PORT_ENA0_ENA_8_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_8_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_8 Mask */
#define GPIO_GROUP_INT1_PORT_ENA0_ENA_9_Pos                   9                                                         /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_9 Position */
#define GPIO_GROUP_INT1_PORT_ENA0_ENA_9_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_9_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_9 Mask */
#define GPIO_GROUP_INT1_PORT_ENA0_ENA_10_Pos                  10                                                        /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_10 Position */
#define GPIO_GROUP_INT1_PORT_ENA0_ENA_10_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_10_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_10 Mask */
#define GPIO_GROUP_INT1_PORT_ENA0_ENA_11_Pos                  11                                                        /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_11 Position */
#define GPIO_GROUP_INT1_PORT_ENA0_ENA_11_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_11_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_11 Mask */
#define GPIO_GROUP_INT1_PORT_ENA0_ENA_12_Pos                  12                                                        /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_12 Position */
#define GPIO_GROUP_INT1_PORT_ENA0_ENA_12_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_12_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_12 Mask */
#define GPIO_GROUP_INT1_PORT_ENA0_ENA_13_Pos                  13                                                        /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_13 Position */
#define GPIO_GROUP_INT1_PORT_ENA0_ENA_13_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_13_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_13 Mask */
#define GPIO_GROUP_INT1_PORT_ENA0_ENA_14_Pos                  14                                                        /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_14 Position */
#define GPIO_GROUP_INT1_PORT_ENA0_ENA_14_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_14_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_14 Mask */
#define GPIO_GROUP_INT1_PORT_ENA0_ENA_15_Pos                  15                                                        /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_15 Position */
#define GPIO_GROUP_INT1_PORT_ENA0_ENA_15_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_15_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_15 Mask */
#define GPIO_GROUP_INT1_PORT_ENA0_ENA_16_Pos                  16                                                        /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_16 Position */
#define GPIO_GROUP_INT1_PORT_ENA0_ENA_16_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_16_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_16 Mask */
#define GPIO_GROUP_INT1_PORT_ENA0_ENA_17_Pos                  17                                                        /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_17 Position */
#define GPIO_GROUP_INT1_PORT_ENA0_ENA_17_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_17_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_17 Mask */
#define GPIO_GROUP_INT1_PORT_ENA0_ENA_18_Pos                  18                                                        /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_18 Position */
#define GPIO_GROUP_INT1_PORT_ENA0_ENA_18_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_18_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_18 Mask */
#define GPIO_GROUP_INT1_PORT_ENA0_ENA_19_Pos                  19                                                        /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_19 Position */
#define GPIO_GROUP_INT1_PORT_ENA0_ENA_19_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_19_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_19 Mask */
#define GPIO_GROUP_INT1_PORT_ENA0_ENA_20_Pos                  20                                                        /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_20 Position */
#define GPIO_GROUP_INT1_PORT_ENA0_ENA_20_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_20_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_20 Mask */
#define GPIO_GROUP_INT1_PORT_ENA0_ENA_21_Pos                  21                                                        /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_21 Position */
#define GPIO_GROUP_INT1_PORT_ENA0_ENA_21_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_21_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_21 Mask */
#define GPIO_GROUP_INT1_PORT_ENA0_ENA_22_Pos                  22                                                        /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_22 Position */
#define GPIO_GROUP_INT1_PORT_ENA0_ENA_22_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_22_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_22 Mask */
#define GPIO_GROUP_INT1_PORT_ENA0_ENA_23_Pos                  23                                                        /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_23 Position */
#define GPIO_GROUP_INT1_PORT_ENA0_ENA_23_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_23_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_23 Mask */
#define GPIO_GROUP_INT1_PORT_ENA0_ENA_24_Pos                  24                                                        /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_24 Position */
#define GPIO_GROUP_INT1_PORT_ENA0_ENA_24_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_24_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_24 Mask */
#define GPIO_GROUP_INT1_PORT_ENA0_ENA_25_Pos                  25                                                        /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_25 Position */
#define GPIO_GROUP_INT1_PORT_ENA0_ENA_25_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_25_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_25 Mask */
#define GPIO_GROUP_INT1_PORT_ENA0_ENA_26_Pos                  26                                                        /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_26 Position */
#define GPIO_GROUP_INT1_PORT_ENA0_ENA_26_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_26_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_26 Mask */
#define GPIO_GROUP_INT1_PORT_ENA0_ENA_27_Pos                  27                                                        /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_27 Position */
#define GPIO_GROUP_INT1_PORT_ENA0_ENA_27_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_27_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_27 Mask */
#define GPIO_GROUP_INT1_PORT_ENA0_ENA_28_Pos                  28                                                        /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_28 Position */
#define GPIO_GROUP_INT1_PORT_ENA0_ENA_28_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_28_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_28 Mask */
#define GPIO_GROUP_INT1_PORT_ENA0_ENA_29_Pos                  29                                                        /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_29 Position */
#define GPIO_GROUP_INT1_PORT_ENA0_ENA_29_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_29_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_29 Mask */
#define GPIO_GROUP_INT1_PORT_ENA0_ENA_30_Pos                  30                                                        /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_30 Position */
#define GPIO_GROUP_INT1_PORT_ENA0_ENA_30_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_30_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_30 Mask */
#define GPIO_GROUP_INT1_PORT_ENA0_ENA_31_Pos                  31                                                        /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_31 Position */
#define GPIO_GROUP_INT1_PORT_ENA0_ENA_31_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_31_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_31 Mask */

// --------------------------------  GPIO_GROUP_INT1_PORT_ENA1  -----------------------------------
#define GPIO_GROUP_INT1_PORT_ENA1_ENA_0_Pos                   0                                                         /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_0 Position */
#define GPIO_GROUP_INT1_PORT_ENA1_ENA_0_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_0_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_0 Mask */
#define GPIO_GROUP_INT1_PORT_ENA1_ENA_1_Pos                   1                                                         /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_1 Position */
#define GPIO_GROUP_INT1_PORT_ENA1_ENA_1_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_1_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_1 Mask */
#define GPIO_GROUP_INT1_PORT_ENA1_ENA_2_Pos                   2                                                         /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_2 Position */
#define GPIO_GROUP_INT1_PORT_ENA1_ENA_2_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_2_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_2 Mask */
#define GPIO_GROUP_INT1_PORT_ENA1_ENA_3_Pos                   3                                                         /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_3 Position */
#define GPIO_GROUP_INT1_PORT_ENA1_ENA_3_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_3_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_3 Mask */
#define GPIO_GROUP_INT1_PORT_ENA1_ENA_4_Pos                   4                                                         /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_4 Position */
#define GPIO_GROUP_INT1_PORT_ENA1_ENA_4_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_4_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_4 Mask */
#define GPIO_GROUP_INT1_PORT_ENA1_ENA_5_Pos                   5                                                         /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_5 Position */
#define GPIO_GROUP_INT1_PORT_ENA1_ENA_5_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_5_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_5 Mask */
#define GPIO_GROUP_INT1_PORT_ENA1_ENA_6_Pos                   6                                                         /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_6 Position */
#define GPIO_GROUP_INT1_PORT_ENA1_ENA_6_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_6_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_6 Mask */
#define GPIO_GROUP_INT1_PORT_ENA1_ENA_7_Pos                   7                                                         /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_7 Position */
#define GPIO_GROUP_INT1_PORT_ENA1_ENA_7_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_7_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_7 Mask */
#define GPIO_GROUP_INT1_PORT_ENA1_ENA_8_Pos                   8                                                         /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_8 Position */
#define GPIO_GROUP_INT1_PORT_ENA1_ENA_8_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_8_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_8 Mask */
#define GPIO_GROUP_INT1_PORT_ENA1_ENA_9_Pos                   9                                                         /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_9 Position */
#define GPIO_GROUP_INT1_PORT_ENA1_ENA_9_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_9_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_9 Mask */
#define GPIO_GROUP_INT1_PORT_ENA1_ENA_10_Pos                  10                                                        /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_10 Position */
#define GPIO_GROUP_INT1_PORT_ENA1_ENA_10_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_10_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_10 Mask */
#define GPIO_GROUP_INT1_PORT_ENA1_ENA_11_Pos                  11                                                        /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_11 Position */
#define GPIO_GROUP_INT1_PORT_ENA1_ENA_11_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_11_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_11 Mask */
#define GPIO_GROUP_INT1_PORT_ENA1_ENA_12_Pos                  12                                                        /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_12 Position */
#define GPIO_GROUP_INT1_PORT_ENA1_ENA_12_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_12_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_12 Mask */
#define GPIO_GROUP_INT1_PORT_ENA1_ENA_13_Pos                  13                                                        /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_13 Position */
#define GPIO_GROUP_INT1_PORT_ENA1_ENA_13_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_13_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_13 Mask */
#define GPIO_GROUP_INT1_PORT_ENA1_ENA_14_Pos                  14                                                        /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_14 Position */
#define GPIO_GROUP_INT1_PORT_ENA1_ENA_14_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_14_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_14 Mask */
#define GPIO_GROUP_INT1_PORT_ENA1_ENA_15_Pos                  15                                                        /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_15 Position */
#define GPIO_GROUP_INT1_PORT_ENA1_ENA_15_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_15_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_15 Mask */
#define GPIO_GROUP_INT1_PORT_ENA1_ENA_16_Pos                  16                                                        /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_16 Position */
#define GPIO_GROUP_INT1_PORT_ENA1_ENA_16_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_16_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_16 Mask */
#define GPIO_GROUP_INT1_PORT_ENA1_ENA_17_Pos                  17                                                        /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_17 Position */
#define GPIO_GROUP_INT1_PORT_ENA1_ENA_17_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_17_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_17 Mask */
#define GPIO_GROUP_INT1_PORT_ENA1_ENA_18_Pos                  18                                                        /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_18 Position */
#define GPIO_GROUP_INT1_PORT_ENA1_ENA_18_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_18_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_18 Mask */
#define GPIO_GROUP_INT1_PORT_ENA1_ENA_19_Pos                  19                                                        /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_19 Position */
#define GPIO_GROUP_INT1_PORT_ENA1_ENA_19_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_19_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_19 Mask */
#define GPIO_GROUP_INT1_PORT_ENA1_ENA_20_Pos                  20                                                        /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_20 Position */
#define GPIO_GROUP_INT1_PORT_ENA1_ENA_20_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_20_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_20 Mask */
#define GPIO_GROUP_INT1_PORT_ENA1_ENA_21_Pos                  21                                                        /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_21 Position */
#define GPIO_GROUP_INT1_PORT_ENA1_ENA_21_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_21_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_21 Mask */
#define GPIO_GROUP_INT1_PORT_ENA1_ENA_22_Pos                  22                                                        /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_22 Position */
#define GPIO_GROUP_INT1_PORT_ENA1_ENA_22_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_22_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_22 Mask */
#define GPIO_GROUP_INT1_PORT_ENA1_ENA_23_Pos                  23                                                        /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_23 Position */
#define GPIO_GROUP_INT1_PORT_ENA1_ENA_23_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_23_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_23 Mask */
#define GPIO_GROUP_INT1_PORT_ENA1_ENA_24_Pos                  24                                                        /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_24 Position */
#define GPIO_GROUP_INT1_PORT_ENA1_ENA_24_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_24_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_24 Mask */
#define GPIO_GROUP_INT1_PORT_ENA1_ENA_25_Pos                  25                                                        /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_25 Position */
#define GPIO_GROUP_INT1_PORT_ENA1_ENA_25_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_25_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_25 Mask */
#define GPIO_GROUP_INT1_PORT_ENA1_ENA_26_Pos                  26                                                        /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_26 Position */
#define GPIO_GROUP_INT1_PORT_ENA1_ENA_26_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_26_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_26 Mask */
#define GPIO_GROUP_INT1_PORT_ENA1_ENA_27_Pos                  27                                                        /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_27 Position */
#define GPIO_GROUP_INT1_PORT_ENA1_ENA_27_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_27_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_27 Mask */
#define GPIO_GROUP_INT1_PORT_ENA1_ENA_28_Pos                  28                                                        /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_28 Position */
#define GPIO_GROUP_INT1_PORT_ENA1_ENA_28_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_28_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_28 Mask */
#define GPIO_GROUP_INT1_PORT_ENA1_ENA_29_Pos                  29                                                        /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_29 Position */
#define GPIO_GROUP_INT1_PORT_ENA1_ENA_29_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_29_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_29 Mask */
#define GPIO_GROUP_INT1_PORT_ENA1_ENA_30_Pos                  30                                                        /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_30 Position */
#define GPIO_GROUP_INT1_PORT_ENA1_ENA_30_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_30_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_30 Mask */
#define GPIO_GROUP_INT1_PORT_ENA1_ENA_31_Pos                  31                                                        /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_31 Position */
#define GPIO_GROUP_INT1_PORT_ENA1_ENA_31_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_31_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_31 Mask */

// --------------------------------  GPIO_GROUP_INT1_PORT_ENA2  -----------------------------------
#define GPIO_GROUP_INT1_PORT_ENA2_ENA_0_Pos                   0                                                         /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_0 Position */
#define GPIO_GROUP_INT1_PORT_ENA2_ENA_0_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_0_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_0 Mask */
#define GPIO_GROUP_INT1_PORT_ENA2_ENA_1_Pos                   1                                                         /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_1 Position */
#define GPIO_GROUP_INT1_PORT_ENA2_ENA_1_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_1_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_1 Mask */
#define GPIO_GROUP_INT1_PORT_ENA2_ENA_2_Pos                   2                                                         /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_2 Position */
#define GPIO_GROUP_INT1_PORT_ENA2_ENA_2_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_2_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_2 Mask */
#define GPIO_GROUP_INT1_PORT_ENA2_ENA_3_Pos                   3                                                         /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_3 Position */
#define GPIO_GROUP_INT1_PORT_ENA2_ENA_3_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_3_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_3 Mask */
#define GPIO_GROUP_INT1_PORT_ENA2_ENA_4_Pos                   4                                                         /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_4 Position */
#define GPIO_GROUP_INT1_PORT_ENA2_ENA_4_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_4_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_4 Mask */
#define GPIO_GROUP_INT1_PORT_ENA2_ENA_5_Pos                   5                                                         /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_5 Position */
#define GPIO_GROUP_INT1_PORT_ENA2_ENA_5_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_5_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_5 Mask */
#define GPIO_GROUP_INT1_PORT_ENA2_ENA_6_Pos                   6                                                         /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_6 Position */
#define GPIO_GROUP_INT1_PORT_ENA2_ENA_6_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_6_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_6 Mask */
#define GPIO_GROUP_INT1_PORT_ENA2_ENA_7_Pos                   7                                                         /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_7 Position */
#define GPIO_GROUP_INT1_PORT_ENA2_ENA_7_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_7_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_7 Mask */
#define GPIO_GROUP_INT1_PORT_ENA2_ENA_8_Pos                   8                                                         /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_8 Position */
#define GPIO_GROUP_INT1_PORT_ENA2_ENA_8_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_8_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_8 Mask */
#define GPIO_GROUP_INT1_PORT_ENA2_ENA_9_Pos                   9                                                         /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_9 Position */
#define GPIO_GROUP_INT1_PORT_ENA2_ENA_9_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_9_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_9 Mask */
#define GPIO_GROUP_INT1_PORT_ENA2_ENA_10_Pos                  10                                                        /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_10 Position */
#define GPIO_GROUP_INT1_PORT_ENA2_ENA_10_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_10_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_10 Mask */
#define GPIO_GROUP_INT1_PORT_ENA2_ENA_11_Pos                  11                                                        /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_11 Position */
#define GPIO_GROUP_INT1_PORT_ENA2_ENA_11_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_11_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_11 Mask */
#define GPIO_GROUP_INT1_PORT_ENA2_ENA_12_Pos                  12                                                        /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_12 Position */
#define GPIO_GROUP_INT1_PORT_ENA2_ENA_12_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_12_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_12 Mask */
#define GPIO_GROUP_INT1_PORT_ENA2_ENA_13_Pos                  13                                                        /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_13 Position */
#define GPIO_GROUP_INT1_PORT_ENA2_ENA_13_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_13_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_13 Mask */
#define GPIO_GROUP_INT1_PORT_ENA2_ENA_14_Pos                  14                                                        /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_14 Position */
#define GPIO_GROUP_INT1_PORT_ENA2_ENA_14_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_14_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_14 Mask */
#define GPIO_GROUP_INT1_PORT_ENA2_ENA_15_Pos                  15                                                        /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_15 Position */
#define GPIO_GROUP_INT1_PORT_ENA2_ENA_15_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_15_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_15 Mask */
#define GPIO_GROUP_INT1_PORT_ENA2_ENA_16_Pos                  16                                                        /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_16 Position */
#define GPIO_GROUP_INT1_PORT_ENA2_ENA_16_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_16_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_16 Mask */
#define GPIO_GROUP_INT1_PORT_ENA2_ENA_17_Pos                  17                                                        /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_17 Position */
#define GPIO_GROUP_INT1_PORT_ENA2_ENA_17_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_17_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_17 Mask */
#define GPIO_GROUP_INT1_PORT_ENA2_ENA_18_Pos                  18                                                        /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_18 Position */
#define GPIO_GROUP_INT1_PORT_ENA2_ENA_18_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_18_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_18 Mask */
#define GPIO_GROUP_INT1_PORT_ENA2_ENA_19_Pos                  19                                                        /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_19 Position */
#define GPIO_GROUP_INT1_PORT_ENA2_ENA_19_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_19_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_19 Mask */
#define GPIO_GROUP_INT1_PORT_ENA2_ENA_20_Pos                  20                                                        /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_20 Position */
#define GPIO_GROUP_INT1_PORT_ENA2_ENA_20_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_20_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_20 Mask */
#define GPIO_GROUP_INT1_PORT_ENA2_ENA_21_Pos                  21                                                        /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_21 Position */
#define GPIO_GROUP_INT1_PORT_ENA2_ENA_21_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_21_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_21 Mask */
#define GPIO_GROUP_INT1_PORT_ENA2_ENA_22_Pos                  22                                                        /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_22 Position */
#define GPIO_GROUP_INT1_PORT_ENA2_ENA_22_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_22_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_22 Mask */
#define GPIO_GROUP_INT1_PORT_ENA2_ENA_23_Pos                  23                                                        /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_23 Position */
#define GPIO_GROUP_INT1_PORT_ENA2_ENA_23_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_23_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_23 Mask */
#define GPIO_GROUP_INT1_PORT_ENA2_ENA_24_Pos                  24                                                        /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_24 Position */
#define GPIO_GROUP_INT1_PORT_ENA2_ENA_24_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_24_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_24 Mask */
#define GPIO_GROUP_INT1_PORT_ENA2_ENA_25_Pos                  25                                                        /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_25 Position */
#define GPIO_GROUP_INT1_PORT_ENA2_ENA_25_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_25_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_25 Mask */
#define GPIO_GROUP_INT1_PORT_ENA2_ENA_26_Pos                  26                                                        /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_26 Position */
#define GPIO_GROUP_INT1_PORT_ENA2_ENA_26_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_26_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_26 Mask */
#define GPIO_GROUP_INT1_PORT_ENA2_ENA_27_Pos                  27                                                        /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_27 Position */
#define GPIO_GROUP_INT1_PORT_ENA2_ENA_27_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_27_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_27 Mask */
#define GPIO_GROUP_INT1_PORT_ENA2_ENA_28_Pos                  28                                                        /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_28 Position */
#define GPIO_GROUP_INT1_PORT_ENA2_ENA_28_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_28_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_28 Mask */
#define GPIO_GROUP_INT1_PORT_ENA2_ENA_29_Pos                  29                                                        /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_29 Position */
#define GPIO_GROUP_INT1_PORT_ENA2_ENA_29_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_29_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_29 Mask */
#define GPIO_GROUP_INT1_PORT_ENA2_ENA_30_Pos                  30                                                        /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_30 Position */
#define GPIO_GROUP_INT1_PORT_ENA2_ENA_30_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_30_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_30 Mask */
#define GPIO_GROUP_INT1_PORT_ENA2_ENA_31_Pos                  31                                                        /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_31 Position */
#define GPIO_GROUP_INT1_PORT_ENA2_ENA_31_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_31_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_31 Mask */

// --------------------------------  GPIO_GROUP_INT1_PORT_ENA3  -----------------------------------
#define GPIO_GROUP_INT1_PORT_ENA3_ENA_0_Pos                   0                                                         /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_0 Position */
#define GPIO_GROUP_INT1_PORT_ENA3_ENA_0_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_0_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_0 Mask */
#define GPIO_GROUP_INT1_PORT_ENA3_ENA_1_Pos                   1                                                         /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_1 Position */
#define GPIO_GROUP_INT1_PORT_ENA3_ENA_1_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_1_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_1 Mask */
#define GPIO_GROUP_INT1_PORT_ENA3_ENA_2_Pos                   2                                                         /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_2 Position */
#define GPIO_GROUP_INT1_PORT_ENA3_ENA_2_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_2_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_2 Mask */
#define GPIO_GROUP_INT1_PORT_ENA3_ENA_3_Pos                   3                                                         /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_3 Position */
#define GPIO_GROUP_INT1_PORT_ENA3_ENA_3_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_3_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_3 Mask */
#define GPIO_GROUP_INT1_PORT_ENA3_ENA_4_Pos                   4                                                         /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_4 Position */
#define GPIO_GROUP_INT1_PORT_ENA3_ENA_4_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_4_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_4 Mask */
#define GPIO_GROUP_INT1_PORT_ENA3_ENA_5_Pos                   5                                                         /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_5 Position */
#define GPIO_GROUP_INT1_PORT_ENA3_ENA_5_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_5_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_5 Mask */
#define GPIO_GROUP_INT1_PORT_ENA3_ENA_6_Pos                   6                                                         /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_6 Position */
#define GPIO_GROUP_INT1_PORT_ENA3_ENA_6_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_6_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_6 Mask */
#define GPIO_GROUP_INT1_PORT_ENA3_ENA_7_Pos                   7                                                         /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_7 Position */
#define GPIO_GROUP_INT1_PORT_ENA3_ENA_7_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_7_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_7 Mask */
#define GPIO_GROUP_INT1_PORT_ENA3_ENA_8_Pos                   8                                                         /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_8 Position */
#define GPIO_GROUP_INT1_PORT_ENA3_ENA_8_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_8_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_8 Mask */
#define GPIO_GROUP_INT1_PORT_ENA3_ENA_9_Pos                   9                                                         /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_9 Position */
#define GPIO_GROUP_INT1_PORT_ENA3_ENA_9_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_9_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_9 Mask */
#define GPIO_GROUP_INT1_PORT_ENA3_ENA_10_Pos                  10                                                        /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_10 Position */
#define GPIO_GROUP_INT1_PORT_ENA3_ENA_10_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_10_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_10 Mask */
#define GPIO_GROUP_INT1_PORT_ENA3_ENA_11_Pos                  11                                                        /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_11 Position */
#define GPIO_GROUP_INT1_PORT_ENA3_ENA_11_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_11_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_11 Mask */
#define GPIO_GROUP_INT1_PORT_ENA3_ENA_12_Pos                  12                                                        /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_12 Position */
#define GPIO_GROUP_INT1_PORT_ENA3_ENA_12_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_12_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_12 Mask */
#define GPIO_GROUP_INT1_PORT_ENA3_ENA_13_Pos                  13                                                        /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_13 Position */
#define GPIO_GROUP_INT1_PORT_ENA3_ENA_13_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_13_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_13 Mask */
#define GPIO_GROUP_INT1_PORT_ENA3_ENA_14_Pos                  14                                                        /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_14 Position */
#define GPIO_GROUP_INT1_PORT_ENA3_ENA_14_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_14_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_14 Mask */
#define GPIO_GROUP_INT1_PORT_ENA3_ENA_15_Pos                  15                                                        /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_15 Position */
#define GPIO_GROUP_INT1_PORT_ENA3_ENA_15_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_15_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_15 Mask */
#define GPIO_GROUP_INT1_PORT_ENA3_ENA_16_Pos                  16                                                        /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_16 Position */
#define GPIO_GROUP_INT1_PORT_ENA3_ENA_16_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_16_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_16 Mask */
#define GPIO_GROUP_INT1_PORT_ENA3_ENA_17_Pos                  17                                                        /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_17 Position */
#define GPIO_GROUP_INT1_PORT_ENA3_ENA_17_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_17_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_17 Mask */
#define GPIO_GROUP_INT1_PORT_ENA3_ENA_18_Pos                  18                                                        /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_18 Position */
#define GPIO_GROUP_INT1_PORT_ENA3_ENA_18_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_18_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_18 Mask */
#define GPIO_GROUP_INT1_PORT_ENA3_ENA_19_Pos                  19                                                        /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_19 Position */
#define GPIO_GROUP_INT1_PORT_ENA3_ENA_19_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_19_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_19 Mask */
#define GPIO_GROUP_INT1_PORT_ENA3_ENA_20_Pos                  20                                                        /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_20 Position */
#define GPIO_GROUP_INT1_PORT_ENA3_ENA_20_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_20_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_20 Mask */
#define GPIO_GROUP_INT1_PORT_ENA3_ENA_21_Pos                  21                                                        /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_21 Position */
#define GPIO_GROUP_INT1_PORT_ENA3_ENA_21_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_21_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_21 Mask */
#define GPIO_GROUP_INT1_PORT_ENA3_ENA_22_Pos                  22                                                        /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_22 Position */
#define GPIO_GROUP_INT1_PORT_ENA3_ENA_22_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_22_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_22 Mask */
#define GPIO_GROUP_INT1_PORT_ENA3_ENA_23_Pos                  23                                                        /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_23 Position */
#define GPIO_GROUP_INT1_PORT_ENA3_ENA_23_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_23_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_23 Mask */
#define GPIO_GROUP_INT1_PORT_ENA3_ENA_24_Pos                  24                                                        /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_24 Position */
#define GPIO_GROUP_INT1_PORT_ENA3_ENA_24_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_24_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_24 Mask */
#define GPIO_GROUP_INT1_PORT_ENA3_ENA_25_Pos                  25                                                        /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_25 Position */
#define GPIO_GROUP_INT1_PORT_ENA3_ENA_25_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_25_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_25 Mask */
#define GPIO_GROUP_INT1_PORT_ENA3_ENA_26_Pos                  26                                                        /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_26 Position */
#define GPIO_GROUP_INT1_PORT_ENA3_ENA_26_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_26_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_26 Mask */
#define GPIO_GROUP_INT1_PORT_ENA3_ENA_27_Pos                  27                                                        /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_27 Position */
#define GPIO_GROUP_INT1_PORT_ENA3_ENA_27_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_27_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_27 Mask */
#define GPIO_GROUP_INT1_PORT_ENA3_ENA_28_Pos                  28                                                        /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_28 Position */
#define GPIO_GROUP_INT1_PORT_ENA3_ENA_28_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_28_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_28 Mask */
#define GPIO_GROUP_INT1_PORT_ENA3_ENA_29_Pos                  29                                                        /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_29 Position */
#define GPIO_GROUP_INT1_PORT_ENA3_ENA_29_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_29_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_29 Mask */
#define GPIO_GROUP_INT1_PORT_ENA3_ENA_30_Pos                  30                                                        /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_30 Position */
#define GPIO_GROUP_INT1_PORT_ENA3_ENA_30_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_30_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_30 Mask */
#define GPIO_GROUP_INT1_PORT_ENA3_ENA_31_Pos                  31                                                        /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_31 Position */
#define GPIO_GROUP_INT1_PORT_ENA3_ENA_31_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_31_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_31 Mask */

// --------------------------------  GPIO_GROUP_INT1_PORT_ENA4  -----------------------------------
#define GPIO_GROUP_INT1_PORT_ENA4_ENA_0_Pos                   0                                                         /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_0 Position */
#define GPIO_GROUP_INT1_PORT_ENA4_ENA_0_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_0_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_0 Mask */
#define GPIO_GROUP_INT1_PORT_ENA4_ENA_1_Pos                   1                                                         /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_1 Position */
#define GPIO_GROUP_INT1_PORT_ENA4_ENA_1_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_1_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_1 Mask */
#define GPIO_GROUP_INT1_PORT_ENA4_ENA_2_Pos                   2                                                         /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_2 Position */
#define GPIO_GROUP_INT1_PORT_ENA4_ENA_2_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_2_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_2 Mask */
#define GPIO_GROUP_INT1_PORT_ENA4_ENA_3_Pos                   3                                                         /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_3 Position */
#define GPIO_GROUP_INT1_PORT_ENA4_ENA_3_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_3_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_3 Mask */
#define GPIO_GROUP_INT1_PORT_ENA4_ENA_4_Pos                   4                                                         /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_4 Position */
#define GPIO_GROUP_INT1_PORT_ENA4_ENA_4_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_4_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_4 Mask */
#define GPIO_GROUP_INT1_PORT_ENA4_ENA_5_Pos                   5                                                         /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_5 Position */
#define GPIO_GROUP_INT1_PORT_ENA4_ENA_5_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_5_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_5 Mask */
#define GPIO_GROUP_INT1_PORT_ENA4_ENA_6_Pos                   6                                                         /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_6 Position */
#define GPIO_GROUP_INT1_PORT_ENA4_ENA_6_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_6_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_6 Mask */
#define GPIO_GROUP_INT1_PORT_ENA4_ENA_7_Pos                   7                                                         /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_7 Position */
#define GPIO_GROUP_INT1_PORT_ENA4_ENA_7_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_7_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_7 Mask */
#define GPIO_GROUP_INT1_PORT_ENA4_ENA_8_Pos                   8                                                         /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_8 Position */
#define GPIO_GROUP_INT1_PORT_ENA4_ENA_8_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_8_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_8 Mask */
#define GPIO_GROUP_INT1_PORT_ENA4_ENA_9_Pos                   9                                                         /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_9 Position */
#define GPIO_GROUP_INT1_PORT_ENA4_ENA_9_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_9_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_9 Mask */
#define GPIO_GROUP_INT1_PORT_ENA4_ENA_10_Pos                  10                                                        /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_10 Position */
#define GPIO_GROUP_INT1_PORT_ENA4_ENA_10_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_10_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_10 Mask */
#define GPIO_GROUP_INT1_PORT_ENA4_ENA_11_Pos                  11                                                        /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_11 Position */
#define GPIO_GROUP_INT1_PORT_ENA4_ENA_11_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_11_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_11 Mask */
#define GPIO_GROUP_INT1_PORT_ENA4_ENA_12_Pos                  12                                                        /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_12 Position */
#define GPIO_GROUP_INT1_PORT_ENA4_ENA_12_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_12_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_12 Mask */
#define GPIO_GROUP_INT1_PORT_ENA4_ENA_13_Pos                  13                                                        /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_13 Position */
#define GPIO_GROUP_INT1_PORT_ENA4_ENA_13_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_13_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_13 Mask */
#define GPIO_GROUP_INT1_PORT_ENA4_ENA_14_Pos                  14                                                        /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_14 Position */
#define GPIO_GROUP_INT1_PORT_ENA4_ENA_14_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_14_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_14 Mask */
#define GPIO_GROUP_INT1_PORT_ENA4_ENA_15_Pos                  15                                                        /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_15 Position */
#define GPIO_GROUP_INT1_PORT_ENA4_ENA_15_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_15_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_15 Mask */
#define GPIO_GROUP_INT1_PORT_ENA4_ENA_16_Pos                  16                                                        /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_16 Position */
#define GPIO_GROUP_INT1_PORT_ENA4_ENA_16_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_16_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_16 Mask */
#define GPIO_GROUP_INT1_PORT_ENA4_ENA_17_Pos                  17                                                        /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_17 Position */
#define GPIO_GROUP_INT1_PORT_ENA4_ENA_17_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_17_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_17 Mask */
#define GPIO_GROUP_INT1_PORT_ENA4_ENA_18_Pos                  18                                                        /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_18 Position */
#define GPIO_GROUP_INT1_PORT_ENA4_ENA_18_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_18_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_18 Mask */
#define GPIO_GROUP_INT1_PORT_ENA4_ENA_19_Pos                  19                                                        /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_19 Position */
#define GPIO_GROUP_INT1_PORT_ENA4_ENA_19_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_19_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_19 Mask */
#define GPIO_GROUP_INT1_PORT_ENA4_ENA_20_Pos                  20                                                        /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_20 Position */
#define GPIO_GROUP_INT1_PORT_ENA4_ENA_20_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_20_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_20 Mask */
#define GPIO_GROUP_INT1_PORT_ENA4_ENA_21_Pos                  21                                                        /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_21 Position */
#define GPIO_GROUP_INT1_PORT_ENA4_ENA_21_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_21_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_21 Mask */
#define GPIO_GROUP_INT1_PORT_ENA4_ENA_22_Pos                  22                                                        /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_22 Position */
#define GPIO_GROUP_INT1_PORT_ENA4_ENA_22_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_22_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_22 Mask */
#define GPIO_GROUP_INT1_PORT_ENA4_ENA_23_Pos                  23                                                        /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_23 Position */
#define GPIO_GROUP_INT1_PORT_ENA4_ENA_23_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_23_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_23 Mask */
#define GPIO_GROUP_INT1_PORT_ENA4_ENA_24_Pos                  24                                                        /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_24 Position */
#define GPIO_GROUP_INT1_PORT_ENA4_ENA_24_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_24_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_24 Mask */
#define GPIO_GROUP_INT1_PORT_ENA4_ENA_25_Pos                  25                                                        /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_25 Position */
#define GPIO_GROUP_INT1_PORT_ENA4_ENA_25_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_25_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_25 Mask */
#define GPIO_GROUP_INT1_PORT_ENA4_ENA_26_Pos                  26                                                        /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_26 Position */
#define GPIO_GROUP_INT1_PORT_ENA4_ENA_26_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_26_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_26 Mask */
#define GPIO_GROUP_INT1_PORT_ENA4_ENA_27_Pos                  27                                                        /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_27 Position */
#define GPIO_GROUP_INT1_PORT_ENA4_ENA_27_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_27_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_27 Mask */
#define GPIO_GROUP_INT1_PORT_ENA4_ENA_28_Pos                  28                                                        /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_28 Position */
#define GPIO_GROUP_INT1_PORT_ENA4_ENA_28_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_28_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_28 Mask */
#define GPIO_GROUP_INT1_PORT_ENA4_ENA_29_Pos                  29                                                        /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_29 Position */
#define GPIO_GROUP_INT1_PORT_ENA4_ENA_29_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_29_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_29 Mask */
#define GPIO_GROUP_INT1_PORT_ENA4_ENA_30_Pos                  30                                                        /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_30 Position */
#define GPIO_GROUP_INT1_PORT_ENA4_ENA_30_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_30_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_30 Mask */
#define GPIO_GROUP_INT1_PORT_ENA4_ENA_31_Pos                  31                                                        /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_31 Position */
#define GPIO_GROUP_INT1_PORT_ENA4_ENA_31_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_31_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_31 Mask */

// --------------------------------  GPIO_GROUP_INT1_PORT_ENA5  -----------------------------------
#define GPIO_GROUP_INT1_PORT_ENA5_ENA_0_Pos                   0                                                         /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_0 Position */
#define GPIO_GROUP_INT1_PORT_ENA5_ENA_0_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_0_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_0 Mask */
#define GPIO_GROUP_INT1_PORT_ENA5_ENA_1_Pos                   1                                                         /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_1 Position */
#define GPIO_GROUP_INT1_PORT_ENA5_ENA_1_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_1_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_1 Mask */
#define GPIO_GROUP_INT1_PORT_ENA5_ENA_2_Pos                   2                                                         /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_2 Position */
#define GPIO_GROUP_INT1_PORT_ENA5_ENA_2_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_2_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_2 Mask */
#define GPIO_GROUP_INT1_PORT_ENA5_ENA_3_Pos                   3                                                         /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_3 Position */
#define GPIO_GROUP_INT1_PORT_ENA5_ENA_3_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_3_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_3 Mask */
#define GPIO_GROUP_INT1_PORT_ENA5_ENA_4_Pos                   4                                                         /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_4 Position */
#define GPIO_GROUP_INT1_PORT_ENA5_ENA_4_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_4_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_4 Mask */
#define GPIO_GROUP_INT1_PORT_ENA5_ENA_5_Pos                   5                                                         /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_5 Position */
#define GPIO_GROUP_INT1_PORT_ENA5_ENA_5_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_5_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_5 Mask */
#define GPIO_GROUP_INT1_PORT_ENA5_ENA_6_Pos                   6                                                         /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_6 Position */
#define GPIO_GROUP_INT1_PORT_ENA5_ENA_6_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_6_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_6 Mask */
#define GPIO_GROUP_INT1_PORT_ENA5_ENA_7_Pos                   7                                                         /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_7 Position */
#define GPIO_GROUP_INT1_PORT_ENA5_ENA_7_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_7_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_7 Mask */
#define GPIO_GROUP_INT1_PORT_ENA5_ENA_8_Pos                   8                                                         /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_8 Position */
#define GPIO_GROUP_INT1_PORT_ENA5_ENA_8_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_8_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_8 Mask */
#define GPIO_GROUP_INT1_PORT_ENA5_ENA_9_Pos                   9                                                         /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_9 Position */
#define GPIO_GROUP_INT1_PORT_ENA5_ENA_9_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_9_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_9 Mask */
#define GPIO_GROUP_INT1_PORT_ENA5_ENA_10_Pos                  10                                                        /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_10 Position */
#define GPIO_GROUP_INT1_PORT_ENA5_ENA_10_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_10_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_10 Mask */
#define GPIO_GROUP_INT1_PORT_ENA5_ENA_11_Pos                  11                                                        /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_11 Position */
#define GPIO_GROUP_INT1_PORT_ENA5_ENA_11_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_11_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_11 Mask */
#define GPIO_GROUP_INT1_PORT_ENA5_ENA_12_Pos                  12                                                        /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_12 Position */
#define GPIO_GROUP_INT1_PORT_ENA5_ENA_12_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_12_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_12 Mask */
#define GPIO_GROUP_INT1_PORT_ENA5_ENA_13_Pos                  13                                                        /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_13 Position */
#define GPIO_GROUP_INT1_PORT_ENA5_ENA_13_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_13_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_13 Mask */
#define GPIO_GROUP_INT1_PORT_ENA5_ENA_14_Pos                  14                                                        /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_14 Position */
#define GPIO_GROUP_INT1_PORT_ENA5_ENA_14_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_14_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_14 Mask */
#define GPIO_GROUP_INT1_PORT_ENA5_ENA_15_Pos                  15                                                        /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_15 Position */
#define GPIO_GROUP_INT1_PORT_ENA5_ENA_15_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_15_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_15 Mask */
#define GPIO_GROUP_INT1_PORT_ENA5_ENA_16_Pos                  16                                                        /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_16 Position */
#define GPIO_GROUP_INT1_PORT_ENA5_ENA_16_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_16_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_16 Mask */
#define GPIO_GROUP_INT1_PORT_ENA5_ENA_17_Pos                  17                                                        /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_17 Position */
#define GPIO_GROUP_INT1_PORT_ENA5_ENA_17_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_17_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_17 Mask */
#define GPIO_GROUP_INT1_PORT_ENA5_ENA_18_Pos                  18                                                        /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_18 Position */
#define GPIO_GROUP_INT1_PORT_ENA5_ENA_18_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_18_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_18 Mask */
#define GPIO_GROUP_INT1_PORT_ENA5_ENA_19_Pos                  19                                                        /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_19 Position */
#define GPIO_GROUP_INT1_PORT_ENA5_ENA_19_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_19_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_19 Mask */
#define GPIO_GROUP_INT1_PORT_ENA5_ENA_20_Pos                  20                                                        /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_20 Position */
#define GPIO_GROUP_INT1_PORT_ENA5_ENA_20_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_20_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_20 Mask */
#define GPIO_GROUP_INT1_PORT_ENA5_ENA_21_Pos                  21                                                        /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_21 Position */
#define GPIO_GROUP_INT1_PORT_ENA5_ENA_21_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_21_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_21 Mask */
#define GPIO_GROUP_INT1_PORT_ENA5_ENA_22_Pos                  22                                                        /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_22 Position */
#define GPIO_GROUP_INT1_PORT_ENA5_ENA_22_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_22_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_22 Mask */
#define GPIO_GROUP_INT1_PORT_ENA5_ENA_23_Pos                  23                                                        /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_23 Position */
#define GPIO_GROUP_INT1_PORT_ENA5_ENA_23_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_23_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_23 Mask */
#define GPIO_GROUP_INT1_PORT_ENA5_ENA_24_Pos                  24                                                        /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_24 Position */
#define GPIO_GROUP_INT1_PORT_ENA5_ENA_24_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_24_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_24 Mask */
#define GPIO_GROUP_INT1_PORT_ENA5_ENA_25_Pos                  25                                                        /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_25 Position */
#define GPIO_GROUP_INT1_PORT_ENA5_ENA_25_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_25_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_25 Mask */
#define GPIO_GROUP_INT1_PORT_ENA5_ENA_26_Pos                  26                                                        /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_26 Position */
#define GPIO_GROUP_INT1_PORT_ENA5_ENA_26_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_26_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_26 Mask */
#define GPIO_GROUP_INT1_PORT_ENA5_ENA_27_Pos                  27                                                        /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_27 Position */
#define GPIO_GROUP_INT1_PORT_ENA5_ENA_27_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_27_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_27 Mask */
#define GPIO_GROUP_INT1_PORT_ENA5_ENA_28_Pos                  28                                                        /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_28 Position */
#define GPIO_GROUP_INT1_PORT_ENA5_ENA_28_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_28_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_28 Mask */
#define GPIO_GROUP_INT1_PORT_ENA5_ENA_29_Pos                  29                                                        /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_29 Position */
#define GPIO_GROUP_INT1_PORT_ENA5_ENA_29_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_29_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_29 Mask */
#define GPIO_GROUP_INT1_PORT_ENA5_ENA_30_Pos                  30                                                        /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_30 Position */
#define GPIO_GROUP_INT1_PORT_ENA5_ENA_30_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_30_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_30 Mask */
#define GPIO_GROUP_INT1_PORT_ENA5_ENA_31_Pos                  31                                                        /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_31 Position */
#define GPIO_GROUP_INT1_PORT_ENA5_ENA_31_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_31_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_31 Mask */

// --------------------------------  GPIO_GROUP_INT1_PORT_ENA6  -----------------------------------
#define GPIO_GROUP_INT1_PORT_ENA6_ENA_0_Pos                   0                                                         /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_0 Position */
#define GPIO_GROUP_INT1_PORT_ENA6_ENA_0_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_0_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_0 Mask */
#define GPIO_GROUP_INT1_PORT_ENA6_ENA_1_Pos                   1                                                         /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_1 Position */
#define GPIO_GROUP_INT1_PORT_ENA6_ENA_1_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_1_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_1 Mask */
#define GPIO_GROUP_INT1_PORT_ENA6_ENA_2_Pos                   2                                                         /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_2 Position */
#define GPIO_GROUP_INT1_PORT_ENA6_ENA_2_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_2_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_2 Mask */
#define GPIO_GROUP_INT1_PORT_ENA6_ENA_3_Pos                   3                                                         /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_3 Position */
#define GPIO_GROUP_INT1_PORT_ENA6_ENA_3_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_3_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_3 Mask */
#define GPIO_GROUP_INT1_PORT_ENA6_ENA_4_Pos                   4                                                         /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_4 Position */
#define GPIO_GROUP_INT1_PORT_ENA6_ENA_4_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_4_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_4 Mask */
#define GPIO_GROUP_INT1_PORT_ENA6_ENA_5_Pos                   5                                                         /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_5 Position */
#define GPIO_GROUP_INT1_PORT_ENA6_ENA_5_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_5_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_5 Mask */
#define GPIO_GROUP_INT1_PORT_ENA6_ENA_6_Pos                   6                                                         /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_6 Position */
#define GPIO_GROUP_INT1_PORT_ENA6_ENA_6_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_6_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_6 Mask */
#define GPIO_GROUP_INT1_PORT_ENA6_ENA_7_Pos                   7                                                         /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_7 Position */
#define GPIO_GROUP_INT1_PORT_ENA6_ENA_7_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_7_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_7 Mask */
#define GPIO_GROUP_INT1_PORT_ENA6_ENA_8_Pos                   8                                                         /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_8 Position */
#define GPIO_GROUP_INT1_PORT_ENA6_ENA_8_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_8_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_8 Mask */
#define GPIO_GROUP_INT1_PORT_ENA6_ENA_9_Pos                   9                                                         /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_9 Position */
#define GPIO_GROUP_INT1_PORT_ENA6_ENA_9_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_9_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_9 Mask */
#define GPIO_GROUP_INT1_PORT_ENA6_ENA_10_Pos                  10                                                        /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_10 Position */
#define GPIO_GROUP_INT1_PORT_ENA6_ENA_10_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_10_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_10 Mask */
#define GPIO_GROUP_INT1_PORT_ENA6_ENA_11_Pos                  11                                                        /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_11 Position */
#define GPIO_GROUP_INT1_PORT_ENA6_ENA_11_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_11_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_11 Mask */
#define GPIO_GROUP_INT1_PORT_ENA6_ENA_12_Pos                  12                                                        /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_12 Position */
#define GPIO_GROUP_INT1_PORT_ENA6_ENA_12_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_12_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_12 Mask */
#define GPIO_GROUP_INT1_PORT_ENA6_ENA_13_Pos                  13                                                        /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_13 Position */
#define GPIO_GROUP_INT1_PORT_ENA6_ENA_13_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_13_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_13 Mask */
#define GPIO_GROUP_INT1_PORT_ENA6_ENA_14_Pos                  14                                                        /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_14 Position */
#define GPIO_GROUP_INT1_PORT_ENA6_ENA_14_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_14_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_14 Mask */
#define GPIO_GROUP_INT1_PORT_ENA6_ENA_15_Pos                  15                                                        /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_15 Position */
#define GPIO_GROUP_INT1_PORT_ENA6_ENA_15_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_15_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_15 Mask */
#define GPIO_GROUP_INT1_PORT_ENA6_ENA_16_Pos                  16                                                        /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_16 Position */
#define GPIO_GROUP_INT1_PORT_ENA6_ENA_16_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_16_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_16 Mask */
#define GPIO_GROUP_INT1_PORT_ENA6_ENA_17_Pos                  17                                                        /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_17 Position */
#define GPIO_GROUP_INT1_PORT_ENA6_ENA_17_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_17_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_17 Mask */
#define GPIO_GROUP_INT1_PORT_ENA6_ENA_18_Pos                  18                                                        /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_18 Position */
#define GPIO_GROUP_INT1_PORT_ENA6_ENA_18_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_18_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_18 Mask */
#define GPIO_GROUP_INT1_PORT_ENA6_ENA_19_Pos                  19                                                        /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_19 Position */
#define GPIO_GROUP_INT1_PORT_ENA6_ENA_19_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_19_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_19 Mask */
#define GPIO_GROUP_INT1_PORT_ENA6_ENA_20_Pos                  20                                                        /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_20 Position */
#define GPIO_GROUP_INT1_PORT_ENA6_ENA_20_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_20_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_20 Mask */
#define GPIO_GROUP_INT1_PORT_ENA6_ENA_21_Pos                  21                                                        /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_21 Position */
#define GPIO_GROUP_INT1_PORT_ENA6_ENA_21_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_21_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_21 Mask */
#define GPIO_GROUP_INT1_PORT_ENA6_ENA_22_Pos                  22                                                        /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_22 Position */
#define GPIO_GROUP_INT1_PORT_ENA6_ENA_22_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_22_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_22 Mask */
#define GPIO_GROUP_INT1_PORT_ENA6_ENA_23_Pos                  23                                                        /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_23 Position */
#define GPIO_GROUP_INT1_PORT_ENA6_ENA_23_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_23_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_23 Mask */
#define GPIO_GROUP_INT1_PORT_ENA6_ENA_24_Pos                  24                                                        /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_24 Position */
#define GPIO_GROUP_INT1_PORT_ENA6_ENA_24_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_24_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_24 Mask */
#define GPIO_GROUP_INT1_PORT_ENA6_ENA_25_Pos                  25                                                        /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_25 Position */
#define GPIO_GROUP_INT1_PORT_ENA6_ENA_25_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_25_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_25 Mask */
#define GPIO_GROUP_INT1_PORT_ENA6_ENA_26_Pos                  26                                                        /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_26 Position */
#define GPIO_GROUP_INT1_PORT_ENA6_ENA_26_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_26_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_26 Mask */
#define GPIO_GROUP_INT1_PORT_ENA6_ENA_27_Pos                  27                                                        /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_27 Position */
#define GPIO_GROUP_INT1_PORT_ENA6_ENA_27_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_27_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_27 Mask */
#define GPIO_GROUP_INT1_PORT_ENA6_ENA_28_Pos                  28                                                        /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_28 Position */
#define GPIO_GROUP_INT1_PORT_ENA6_ENA_28_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_28_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_28 Mask */
#define GPIO_GROUP_INT1_PORT_ENA6_ENA_29_Pos                  29                                                        /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_29 Position */
#define GPIO_GROUP_INT1_PORT_ENA6_ENA_29_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_29_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_29 Mask */
#define GPIO_GROUP_INT1_PORT_ENA6_ENA_30_Pos                  30                                                        /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_30 Position */
#define GPIO_GROUP_INT1_PORT_ENA6_ENA_30_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_30_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_30 Mask */
#define GPIO_GROUP_INT1_PORT_ENA6_ENA_31_Pos                  31                                                        /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_31 Position */
#define GPIO_GROUP_INT1_PORT_ENA6_ENA_31_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_31_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_31 Mask */

// --------------------------------  GPIO_GROUP_INT1_PORT_ENA7  -----------------------------------
#define GPIO_GROUP_INT1_PORT_ENA7_ENA_0_Pos                   0                                                         /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_0 Position */
#define GPIO_GROUP_INT1_PORT_ENA7_ENA_0_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_0_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_0 Mask */
#define GPIO_GROUP_INT1_PORT_ENA7_ENA_1_Pos                   1                                                         /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_1 Position */
#define GPIO_GROUP_INT1_PORT_ENA7_ENA_1_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_1_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_1 Mask */
#define GPIO_GROUP_INT1_PORT_ENA7_ENA_2_Pos                   2                                                         /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_2 Position */
#define GPIO_GROUP_INT1_PORT_ENA7_ENA_2_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_2_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_2 Mask */
#define GPIO_GROUP_INT1_PORT_ENA7_ENA_3_Pos                   3                                                         /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_3 Position */
#define GPIO_GROUP_INT1_PORT_ENA7_ENA_3_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_3_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_3 Mask */
#define GPIO_GROUP_INT1_PORT_ENA7_ENA_4_Pos                   4                                                         /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_4 Position */
#define GPIO_GROUP_INT1_PORT_ENA7_ENA_4_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_4_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_4 Mask */
#define GPIO_GROUP_INT1_PORT_ENA7_ENA_5_Pos                   5                                                         /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_5 Position */
#define GPIO_GROUP_INT1_PORT_ENA7_ENA_5_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_5_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_5 Mask */
#define GPIO_GROUP_INT1_PORT_ENA7_ENA_6_Pos                   6                                                         /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_6 Position */
#define GPIO_GROUP_INT1_PORT_ENA7_ENA_6_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_6_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_6 Mask */
#define GPIO_GROUP_INT1_PORT_ENA7_ENA_7_Pos                   7                                                         /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_7 Position */
#define GPIO_GROUP_INT1_PORT_ENA7_ENA_7_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_7_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_7 Mask */
#define GPIO_GROUP_INT1_PORT_ENA7_ENA_8_Pos                   8                                                         /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_8 Position */
#define GPIO_GROUP_INT1_PORT_ENA7_ENA_8_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_8_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_8 Mask */
#define GPIO_GROUP_INT1_PORT_ENA7_ENA_9_Pos                   9                                                         /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_9 Position */
#define GPIO_GROUP_INT1_PORT_ENA7_ENA_9_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_9_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_9 Mask */
#define GPIO_GROUP_INT1_PORT_ENA7_ENA_10_Pos                  10                                                        /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_10 Position */
#define GPIO_GROUP_INT1_PORT_ENA7_ENA_10_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_10_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_10 Mask */
#define GPIO_GROUP_INT1_PORT_ENA7_ENA_11_Pos                  11                                                        /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_11 Position */
#define GPIO_GROUP_INT1_PORT_ENA7_ENA_11_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_11_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_11 Mask */
#define GPIO_GROUP_INT1_PORT_ENA7_ENA_12_Pos                  12                                                        /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_12 Position */
#define GPIO_GROUP_INT1_PORT_ENA7_ENA_12_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_12_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_12 Mask */
#define GPIO_GROUP_INT1_PORT_ENA7_ENA_13_Pos                  13                                                        /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_13 Position */
#define GPIO_GROUP_INT1_PORT_ENA7_ENA_13_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_13_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_13 Mask */
#define GPIO_GROUP_INT1_PORT_ENA7_ENA_14_Pos                  14                                                        /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_14 Position */
#define GPIO_GROUP_INT1_PORT_ENA7_ENA_14_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_14_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_14 Mask */
#define GPIO_GROUP_INT1_PORT_ENA7_ENA_15_Pos                  15                                                        /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_15 Position */
#define GPIO_GROUP_INT1_PORT_ENA7_ENA_15_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_15_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_15 Mask */
#define GPIO_GROUP_INT1_PORT_ENA7_ENA_16_Pos                  16                                                        /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_16 Position */
#define GPIO_GROUP_INT1_PORT_ENA7_ENA_16_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_16_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_16 Mask */
#define GPIO_GROUP_INT1_PORT_ENA7_ENA_17_Pos                  17                                                        /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_17 Position */
#define GPIO_GROUP_INT1_PORT_ENA7_ENA_17_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_17_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_17 Mask */
#define GPIO_GROUP_INT1_PORT_ENA7_ENA_18_Pos                  18                                                        /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_18 Position */
#define GPIO_GROUP_INT1_PORT_ENA7_ENA_18_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_18_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_18 Mask */
#define GPIO_GROUP_INT1_PORT_ENA7_ENA_19_Pos                  19                                                        /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_19 Position */
#define GPIO_GROUP_INT1_PORT_ENA7_ENA_19_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_19_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_19 Mask */
#define GPIO_GROUP_INT1_PORT_ENA7_ENA_20_Pos                  20                                                        /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_20 Position */
#define GPIO_GROUP_INT1_PORT_ENA7_ENA_20_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_20_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_20 Mask */
#define GPIO_GROUP_INT1_PORT_ENA7_ENA_21_Pos                  21                                                        /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_21 Position */
#define GPIO_GROUP_INT1_PORT_ENA7_ENA_21_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_21_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_21 Mask */
#define GPIO_GROUP_INT1_PORT_ENA7_ENA_22_Pos                  22                                                        /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_22 Position */
#define GPIO_GROUP_INT1_PORT_ENA7_ENA_22_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_22_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_22 Mask */
#define GPIO_GROUP_INT1_PORT_ENA7_ENA_23_Pos                  23                                                        /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_23 Position */
#define GPIO_GROUP_INT1_PORT_ENA7_ENA_23_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_23_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_23 Mask */
#define GPIO_GROUP_INT1_PORT_ENA7_ENA_24_Pos                  24                                                        /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_24 Position */
#define GPIO_GROUP_INT1_PORT_ENA7_ENA_24_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_24_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_24 Mask */
#define GPIO_GROUP_INT1_PORT_ENA7_ENA_25_Pos                  25                                                        /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_25 Position */
#define GPIO_GROUP_INT1_PORT_ENA7_ENA_25_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_25_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_25 Mask */
#define GPIO_GROUP_INT1_PORT_ENA7_ENA_26_Pos                  26                                                        /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_26 Position */
#define GPIO_GROUP_INT1_PORT_ENA7_ENA_26_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_26_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_26 Mask */
#define GPIO_GROUP_INT1_PORT_ENA7_ENA_27_Pos                  27                                                        /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_27 Position */
#define GPIO_GROUP_INT1_PORT_ENA7_ENA_27_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_27_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_27 Mask */
#define GPIO_GROUP_INT1_PORT_ENA7_ENA_28_Pos                  28                                                        /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_28 Position */
#define GPIO_GROUP_INT1_PORT_ENA7_ENA_28_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_28_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_28 Mask */
#define GPIO_GROUP_INT1_PORT_ENA7_ENA_29_Pos                  29                                                        /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_29 Position */
#define GPIO_GROUP_INT1_PORT_ENA7_ENA_29_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_29_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_29 Mask */
#define GPIO_GROUP_INT1_PORT_ENA7_ENA_30_Pos                  30                                                        /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_30 Position */
#define GPIO_GROUP_INT1_PORT_ENA7_ENA_30_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_30_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_30 Mask */
#define GPIO_GROUP_INT1_PORT_ENA7_ENA_31_Pos                  31                                                        /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_31 Position */
#define GPIO_GROUP_INT1_PORT_ENA7_ENA_31_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_31_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_31 Mask */


// ------------------------------------------------------------------------------------------------
// -----                                 MCPWM Position & Mask                                -----
// ------------------------------------------------------------------------------------------------


// ----------------------------------------  MCPWM_CON  -------------------------------------------
#define MCPWM_CON_RUN0_Pos                                    0                                                         /*!< MCPWM CON: RUN0 Position            */
#define MCPWM_CON_RUN0_Msk                                    (0x01UL << MCPWM_CON_RUN0_Pos)                            /*!< MCPWM CON: RUN0 Mask                */
#define MCPWM_CON_CENTER0_Pos                                 1                                                         /*!< MCPWM CON: CENTER0 Position         */
#define MCPWM_CON_CENTER0_Msk                                 (0x01UL << MCPWM_CON_CENTER0_Pos)                         /*!< MCPWM CON: CENTER0 Mask             */
#define MCPWM_CON_POLA0_Pos                                   2                                                         /*!< MCPWM CON: POLA0 Position           */
#define MCPWM_CON_POLA0_Msk                                   (0x01UL << MCPWM_CON_POLA0_Pos)                           /*!< MCPWM CON: POLA0 Mask               */
#define MCPWM_CON_DTE0_Pos                                    3                                                         /*!< MCPWM CON: DTE0 Position            */
#define MCPWM_CON_DTE0_Msk                                    (0x01UL << MCPWM_CON_DTE0_Pos)                            /*!< MCPWM CON: DTE0 Mask                */
#define MCPWM_CON_DISUP0_Pos                                  4                                                         /*!< MCPWM CON: DISUP0 Position          */
#define MCPWM_CON_DISUP0_Msk                                  (0x01UL << MCPWM_CON_DISUP0_Pos)                          /*!< MCPWM CON: DISUP0 Mask              */
#define MCPWM_CON_RUN1_Pos                                    8                                                         /*!< MCPWM CON: RUN1 Position            */
#define MCPWM_CON_RUN1_Msk                                    (0x01UL << MCPWM_CON_RUN1_Pos)                            /*!< MCPWM CON: RUN1 Mask                */
#define MCPWM_CON_CENTER1_Pos                                 9                                                         /*!< MCPWM CON: CENTER1 Position         */
#define MCPWM_CON_CENTER1_Msk                                 (0x01UL << MCPWM_CON_CENTER1_Pos)                         /*!< MCPWM CON: CENTER1 Mask             */
#define MCPWM_CON_POLA1_Pos                                   10                                                        /*!< MCPWM CON: POLA1 Position           */
#define MCPWM_CON_POLA1_Msk                                   (0x01UL << MCPWM_CON_POLA1_Pos)                           /*!< MCPWM CON: POLA1 Mask               */
#define MCPWM_CON_DTE1_Pos                                    11                                                        /*!< MCPWM CON: DTE1 Position            */
#define MCPWM_CON_DTE1_Msk                                    (0x01UL << MCPWM_CON_DTE1_Pos)                            /*!< MCPWM CON: DTE1 Mask                */
#define MCPWM_CON_DISUP1_Pos                                  12                                                        /*!< MCPWM CON: DISUP1 Position          */
#define MCPWM_CON_DISUP1_Msk                                  (0x01UL << MCPWM_CON_DISUP1_Pos)                          /*!< MCPWM CON: DISUP1 Mask              */
#define MCPWM_CON_RUN2_Pos                                    16                                                        /*!< MCPWM CON: RUN2 Position            */
#define MCPWM_CON_RUN2_Msk                                    (0x01UL << MCPWM_CON_RUN2_Pos)                            /*!< MCPWM CON: RUN2 Mask                */
#define MCPWM_CON_CENTER2_Pos                                 17                                                        /*!< MCPWM CON: CENTER2 Position         */
#define MCPWM_CON_CENTER2_Msk                                 (0x01UL << MCPWM_CON_CENTER2_Pos)                         /*!< MCPWM CON: CENTER2 Mask             */
#define MCPWM_CON_POLA2_Pos                                   18                                                        /*!< MCPWM CON: POLA2 Position           */
#define MCPWM_CON_POLA2_Msk                                   (0x01UL << MCPWM_CON_POLA2_Pos)                           /*!< MCPWM CON: POLA2 Mask               */
#define MCPWM_CON_DTE2_Pos                                    19                                                        /*!< MCPWM CON: DTE2 Position            */
#define MCPWM_CON_DTE2_Msk                                    (0x01UL << MCPWM_CON_DTE2_Pos)                            /*!< MCPWM CON: DTE2 Mask                */
#define MCPWM_CON_DISUP2_Pos                                  20                                                        /*!< MCPWM CON: DISUP2 Position          */
#define MCPWM_CON_DISUP2_Msk                                  (0x01UL << MCPWM_CON_DISUP2_Pos)                          /*!< MCPWM CON: DISUP2 Mask              */
#define MCPWM_CON_INVBDC_Pos                                  29                                                        /*!< MCPWM CON: INVBDC Position          */
#define MCPWM_CON_INVBDC_Msk                                  (0x01UL << MCPWM_CON_INVBDC_Pos)                          /*!< MCPWM CON: INVBDC Mask              */
#define MCPWM_CON_ACMODE_Pos                                  30                                                        /*!< MCPWM CON: ACMODE Position          */
#define MCPWM_CON_ACMODE_Msk                                  (0x01UL << MCPWM_CON_ACMODE_Pos)                          /*!< MCPWM CON: ACMODE Mask              */
#define MCPWM_CON_DCMODE_Pos                                  31                                                        /*!< MCPWM CON: DCMODE Position          */
#define MCPWM_CON_DCMODE_Msk                                  (0x01UL << MCPWM_CON_DCMODE_Pos)                          /*!< MCPWM CON: DCMODE Mask              */

// --------------------------------------  MCPWM_CON_SET  -----------------------------------------
#define MCPWM_CON_SET_RUN0_SET_Pos                            0                                                         /*!< MCPWM CON_SET: RUN0_SET Position    */
#define MCPWM_CON_SET_RUN0_SET_Msk                            (0x01UL << MCPWM_CON_SET_RUN0_SET_Pos)                    /*!< MCPWM CON_SET: RUN0_SET Mask        */
#define MCPWM_CON_SET_CENTER0_SET_Pos                         1                                                         /*!< MCPWM CON_SET: CENTER0_SET Position */
#define MCPWM_CON_SET_CENTER0_SET_Msk                         (0x01UL << MCPWM_CON_SET_CENTER0_SET_Pos)                 /*!< MCPWM CON_SET: CENTER0_SET Mask     */
#define MCPWM_CON_SET_POLA0_SET_Pos                           2                                                         /*!< MCPWM CON_SET: POLA0_SET Position   */
#define MCPWM_CON_SET_POLA0_SET_Msk                           (0x01UL << MCPWM_CON_SET_POLA0_SET_Pos)                   /*!< MCPWM CON_SET: POLA0_SET Mask       */
#define MCPWM_CON_SET_DTE0_SET_Pos                            3                                                         /*!< MCPWM CON_SET: DTE0_SET Position    */
#define MCPWM_CON_SET_DTE0_SET_Msk                            (0x01UL << MCPWM_CON_SET_DTE0_SET_Pos)                    /*!< MCPWM CON_SET: DTE0_SET Mask        */
#define MCPWM_CON_SET_DISUP0_SET_Pos                          4                                                         /*!< MCPWM CON_SET: DISUP0_SET Position  */
#define MCPWM_CON_SET_DISUP0_SET_Msk                          (0x01UL << MCPWM_CON_SET_DISUP0_SET_Pos)                  /*!< MCPWM CON_SET: DISUP0_SET Mask      */
#define MCPWM_CON_SET_RUN1_SET_Pos                            8                                                         /*!< MCPWM CON_SET: RUN1_SET Position    */
#define MCPWM_CON_SET_RUN1_SET_Msk                            (0x01UL << MCPWM_CON_SET_RUN1_SET_Pos)                    /*!< MCPWM CON_SET: RUN1_SET Mask        */
#define MCPWM_CON_SET_CENTER1_SET_Pos                         9                                                         /*!< MCPWM CON_SET: CENTER1_SET Position */
#define MCPWM_CON_SET_CENTER1_SET_Msk                         (0x01UL << MCPWM_CON_SET_CENTER1_SET_Pos)                 /*!< MCPWM CON_SET: CENTER1_SET Mask     */
#define MCPWM_CON_SET_POLA1_SET_Pos                           10                                                        /*!< MCPWM CON_SET: POLA1_SET Position   */
#define MCPWM_CON_SET_POLA1_SET_Msk                           (0x01UL << MCPWM_CON_SET_POLA1_SET_Pos)                   /*!< MCPWM CON_SET: POLA1_SET Mask       */
#define MCPWM_CON_SET_DTE1_SET_Pos                            11                                                        /*!< MCPWM CON_SET: DTE1_SET Position    */
#define MCPWM_CON_SET_DTE1_SET_Msk                            (0x01UL << MCPWM_CON_SET_DTE1_SET_Pos)                    /*!< MCPWM CON_SET: DTE1_SET Mask        */
#define MCPWM_CON_SET_DISUP1_SET_Pos                          12                                                        /*!< MCPWM CON_SET: DISUP1_SET Position  */
#define MCPWM_CON_SET_DISUP1_SET_Msk                          (0x01UL << MCPWM_CON_SET_DISUP1_SET_Pos)                  /*!< MCPWM CON_SET: DISUP1_SET Mask      */
#define MCPWM_CON_SET_RUN2_SET_Pos                            16                                                        /*!< MCPWM CON_SET: RUN2_SET Position    */
#define MCPWM_CON_SET_RUN2_SET_Msk                            (0x01UL << MCPWM_CON_SET_RUN2_SET_Pos)                    /*!< MCPWM CON_SET: RUN2_SET Mask        */
#define MCPWM_CON_SET_CENTER2_SET_Pos                         17                                                        /*!< MCPWM CON_SET: CENTER2_SET Position */
#define MCPWM_CON_SET_CENTER2_SET_Msk                         (0x01UL << MCPWM_CON_SET_CENTER2_SET_Pos)                 /*!< MCPWM CON_SET: CENTER2_SET Mask     */
#define MCPWM_CON_SET_POLA2_SET_Pos                           18                                                        /*!< MCPWM CON_SET: POLA2_SET Position   */
#define MCPWM_CON_SET_POLA2_SET_Msk                           (0x01UL << MCPWM_CON_SET_POLA2_SET_Pos)                   /*!< MCPWM CON_SET: POLA2_SET Mask       */
#define MCPWM_CON_SET_DTE2_SET_Pos                            19                                                        /*!< MCPWM CON_SET: DTE2_SET Position    */
#define MCPWM_CON_SET_DTE2_SET_Msk                            (0x01UL << MCPWM_CON_SET_DTE2_SET_Pos)                    /*!< MCPWM CON_SET: DTE2_SET Mask        */
#define MCPWM_CON_SET_DISUP2_SET_Pos                          20                                                        /*!< MCPWM CON_SET: DISUP2_SET Position  */
#define MCPWM_CON_SET_DISUP2_SET_Msk                          (0x01UL << MCPWM_CON_SET_DISUP2_SET_Pos)                  /*!< MCPWM CON_SET: DISUP2_SET Mask      */
#define MCPWM_CON_SET_INVBDC_SET_Pos                          29                                                        /*!< MCPWM CON_SET: INVBDC_SET Position  */
#define MCPWM_CON_SET_INVBDC_SET_Msk                          (0x01UL << MCPWM_CON_SET_INVBDC_SET_Pos)                  /*!< MCPWM CON_SET: INVBDC_SET Mask      */
#define MCPWM_CON_SET_ACMODE_SET_Pos                          30                                                        /*!< MCPWM CON_SET: ACMODE_SET Position  */
#define MCPWM_CON_SET_ACMODE_SET_Msk                          (0x01UL << MCPWM_CON_SET_ACMODE_SET_Pos)                  /*!< MCPWM CON_SET: ACMODE_SET Mask      */
#define MCPWM_CON_SET_DCMODE_SET_Pos                          31                                                        /*!< MCPWM CON_SET: DCMODE_SET Position  */
#define MCPWM_CON_SET_DCMODE_SET_Msk                          (0x01UL << MCPWM_CON_SET_DCMODE_SET_Pos)                  /*!< MCPWM CON_SET: DCMODE_SET Mask      */

// --------------------------------------  MCPWM_CON_CLR  -----------------------------------------
#define MCPWM_CON_CLR_RUN0_CLR_Pos                            0                                                         /*!< MCPWM CON_CLR: RUN0_CLR Position    */
#define MCPWM_CON_CLR_RUN0_CLR_Msk                            (0x01UL << MCPWM_CON_CLR_RUN0_CLR_Pos)                    /*!< MCPWM CON_CLR: RUN0_CLR Mask        */
#define MCPWM_CON_CLR_CENTER0_CLR_Pos                         1                                                         /*!< MCPWM CON_CLR: CENTER0_CLR Position */
#define MCPWM_CON_CLR_CENTER0_CLR_Msk                         (0x01UL << MCPWM_CON_CLR_CENTER0_CLR_Pos)                 /*!< MCPWM CON_CLR: CENTER0_CLR Mask     */
#define MCPWM_CON_CLR_POLA0_CLR_Pos                           2                                                         /*!< MCPWM CON_CLR: POLA0_CLR Position   */
#define MCPWM_CON_CLR_POLA0_CLR_Msk                           (0x01UL << MCPWM_CON_CLR_POLA0_CLR_Pos)                   /*!< MCPWM CON_CLR: POLA0_CLR Mask       */
#define MCPWM_CON_CLR_DTE0_CLR_Pos                            3                                                         /*!< MCPWM CON_CLR: DTE0_CLR Position    */
#define MCPWM_CON_CLR_DTE0_CLR_Msk                            (0x01UL << MCPWM_CON_CLR_DTE0_CLR_Pos)                    /*!< MCPWM CON_CLR: DTE0_CLR Mask        */
#define MCPWM_CON_CLR_DISUP0_CLR_Pos                          4                                                         /*!< MCPWM CON_CLR: DISUP0_CLR Position  */
#define MCPWM_CON_CLR_DISUP0_CLR_Msk                          (0x01UL << MCPWM_CON_CLR_DISUP0_CLR_Pos)                  /*!< MCPWM CON_CLR: DISUP0_CLR Mask      */
#define MCPWM_CON_CLR_RUN1_CLR_Pos                            8                                                         /*!< MCPWM CON_CLR: RUN1_CLR Position    */
#define MCPWM_CON_CLR_RUN1_CLR_Msk                            (0x01UL << MCPWM_CON_CLR_RUN1_CLR_Pos)                    /*!< MCPWM CON_CLR: RUN1_CLR Mask        */
#define MCPWM_CON_CLR_CENTER1_CLR_Pos                         9                                                         /*!< MCPWM CON_CLR: CENTER1_CLR Position */
#define MCPWM_CON_CLR_CENTER1_CLR_Msk                         (0x01UL << MCPWM_CON_CLR_CENTER1_CLR_Pos)                 /*!< MCPWM CON_CLR: CENTER1_CLR Mask     */
#define MCPWM_CON_CLR_POLA1_CLR_Pos                           10                                                        /*!< MCPWM CON_CLR: POLA1_CLR Position   */
#define MCPWM_CON_CLR_POLA1_CLR_Msk                           (0x01UL << MCPWM_CON_CLR_POLA1_CLR_Pos)                   /*!< MCPWM CON_CLR: POLA1_CLR Mask       */
#define MCPWM_CON_CLR_DTE1_CLR_Pos                            11                                                        /*!< MCPWM CON_CLR: DTE1_CLR Position    */
#define MCPWM_CON_CLR_DTE1_CLR_Msk                            (0x01UL << MCPWM_CON_CLR_DTE1_CLR_Pos)                    /*!< MCPWM CON_CLR: DTE1_CLR Mask        */
#define MCPWM_CON_CLR_DISUP1_CLR_Pos                          12                                                        /*!< MCPWM CON_CLR: DISUP1_CLR Position  */
#define MCPWM_CON_CLR_DISUP1_CLR_Msk                          (0x01UL << MCPWM_CON_CLR_DISUP1_CLR_Pos)                  /*!< MCPWM CON_CLR: DISUP1_CLR Mask      */
#define MCPWM_CON_CLR_RUN2_CLR_Pos                            16                                                        /*!< MCPWM CON_CLR: RUN2_CLR Position    */
#define MCPWM_CON_CLR_RUN2_CLR_Msk                            (0x01UL << MCPWM_CON_CLR_RUN2_CLR_Pos)                    /*!< MCPWM CON_CLR: RUN2_CLR Mask        */
#define MCPWM_CON_CLR_CENTER2_CLR_Pos                         17                                                        /*!< MCPWM CON_CLR: CENTER2_CLR Position */
#define MCPWM_CON_CLR_CENTER2_CLR_Msk                         (0x01UL << MCPWM_CON_CLR_CENTER2_CLR_Pos)                 /*!< MCPWM CON_CLR: CENTER2_CLR Mask     */
#define MCPWM_CON_CLR_POLA2_CLR_Pos                           18                                                        /*!< MCPWM CON_CLR: POLA2_CLR Position   */
#define MCPWM_CON_CLR_POLA2_CLR_Msk                           (0x01UL << MCPWM_CON_CLR_POLA2_CLR_Pos)                   /*!< MCPWM CON_CLR: POLA2_CLR Mask       */
#define MCPWM_CON_CLR_DTE2_CLR_Pos                            19                                                        /*!< MCPWM CON_CLR: DTE2_CLR Position    */
#define MCPWM_CON_CLR_DTE2_CLR_Msk                            (0x01UL << MCPWM_CON_CLR_DTE2_CLR_Pos)                    /*!< MCPWM CON_CLR: DTE2_CLR Mask        */
#define MCPWM_CON_CLR_DISUP2_CLR_Pos                          20                                                        /*!< MCPWM CON_CLR: DISUP2_CLR Position  */
#define MCPWM_CON_CLR_DISUP2_CLR_Msk                          (0x01UL << MCPWM_CON_CLR_DISUP2_CLR_Pos)                  /*!< MCPWM CON_CLR: DISUP2_CLR Mask      */
#define MCPWM_CON_CLR_INVBDC_CLR_Pos                          29                                                        /*!< MCPWM CON_CLR: INVBDC_CLR Position  */
#define MCPWM_CON_CLR_INVBDC_CLR_Msk                          (0x01UL << MCPWM_CON_CLR_INVBDC_CLR_Pos)                  /*!< MCPWM CON_CLR: INVBDC_CLR Mask      */
#define MCPWM_CON_CLR_ACMOD_CLR_Pos                           30                                                        /*!< MCPWM CON_CLR: ACMOD_CLR Position   */
#define MCPWM_CON_CLR_ACMOD_CLR_Msk                           (0x01UL << MCPWM_CON_CLR_ACMOD_CLR_Pos)                   /*!< MCPWM CON_CLR: ACMOD_CLR Mask       */
#define MCPWM_CON_CLR_DCMODE_CLR_Pos                          31                                                        /*!< MCPWM CON_CLR: DCMODE_CLR Position  */
#define MCPWM_CON_CLR_DCMODE_CLR_Msk                          (0x01UL << MCPWM_CON_CLR_DCMODE_CLR_Pos)                  /*!< MCPWM CON_CLR: DCMODE_CLR Mask      */

// --------------------------------------  MCPWM_CAPCON  ------------------------------------------
#define MCPWM_CAPCON_CAP0MCI0_RE_Pos                          0                                                         /*!< MCPWM CAPCON: CAP0MCI0_RE Position  */
#define MCPWM_CAPCON_CAP0MCI0_RE_Msk                          (0x01UL << MCPWM_CAPCON_CAP0MCI0_RE_Pos)                  /*!< MCPWM CAPCON: CAP0MCI0_RE Mask      */
#define MCPWM_CAPCON_CAP0MCI0_FE_Pos                          1                                                         /*!< MCPWM CAPCON: CAP0MCI0_FE Position  */
#define MCPWM_CAPCON_CAP0MCI0_FE_Msk                          (0x01UL << MCPWM_CAPCON_CAP0MCI0_FE_Pos)                  /*!< MCPWM CAPCON: CAP0MCI0_FE Mask      */
#define MCPWM_CAPCON_CAP0MCI1_RE_Pos                          2                                                         /*!< MCPWM CAPCON: CAP0MCI1_RE Position  */
#define MCPWM_CAPCON_CAP0MCI1_RE_Msk                          (0x01UL << MCPWM_CAPCON_CAP0MCI1_RE_Pos)                  /*!< MCPWM CAPCON: CAP0MCI1_RE Mask      */
#define MCPWM_CAPCON_CAP0MCI1_FE_Pos                          3                                                         /*!< MCPWM CAPCON: CAP0MCI1_FE Position  */
#define MCPWM_CAPCON_CAP0MCI1_FE_Msk                          (0x01UL << MCPWM_CAPCON_CAP0MCI1_FE_Pos)                  /*!< MCPWM CAPCON: CAP0MCI1_FE Mask      */
#define MCPWM_CAPCON_CAP0MCI2_RE_Pos                          4                                                         /*!< MCPWM CAPCON: CAP0MCI2_RE Position  */
#define MCPWM_CAPCON_CAP0MCI2_RE_Msk                          (0x01UL << MCPWM_CAPCON_CAP0MCI2_RE_Pos)                  /*!< MCPWM CAPCON: CAP0MCI2_RE Mask      */
#define MCPWM_CAPCON_CAP0MCI2_FE_Pos                          5                                                         /*!< MCPWM CAPCON: CAP0MCI2_FE Position  */
#define MCPWM_CAPCON_CAP0MCI2_FE_Msk                          (0x01UL << MCPWM_CAPCON_CAP0MCI2_FE_Pos)                  /*!< MCPWM CAPCON: CAP0MCI2_FE Mask      */
#define MCPWM_CAPCON_CAP1MCI0_RE_Pos                          6                                                         /*!< MCPWM CAPCON: CAP1MCI0_RE Position  */
#define MCPWM_CAPCON_CAP1MCI0_RE_Msk                          (0x01UL << MCPWM_CAPCON_CAP1MCI0_RE_Pos)                  /*!< MCPWM CAPCON: CAP1MCI0_RE Mask      */
#define MCPWM_CAPCON_CAP1MCI0_FE_Pos                          7                                                         /*!< MCPWM CAPCON: CAP1MCI0_FE Position  */
#define MCPWM_CAPCON_CAP1MCI0_FE_Msk                          (0x01UL << MCPWM_CAPCON_CAP1MCI0_FE_Pos)                  /*!< MCPWM CAPCON: CAP1MCI0_FE Mask      */
#define MCPWM_CAPCON_CAP1MCI1_RE_Pos                          8                                                         /*!< MCPWM CAPCON: CAP1MCI1_RE Position  */
#define MCPWM_CAPCON_CAP1MCI1_RE_Msk                          (0x01UL << MCPWM_CAPCON_CAP1MCI1_RE_Pos)                  /*!< MCPWM CAPCON: CAP1MCI1_RE Mask      */
#define MCPWM_CAPCON_CAP1MCI1_FE_Pos                          9                                                         /*!< MCPWM CAPCON: CAP1MCI1_FE Position  */
#define MCPWM_CAPCON_CAP1MCI1_FE_Msk                          (0x01UL << MCPWM_CAPCON_CAP1MCI1_FE_Pos)                  /*!< MCPWM CAPCON: CAP1MCI1_FE Mask      */
#define MCPWM_CAPCON_CAP1MCI2_RE_Pos                          10                                                        /*!< MCPWM CAPCON: CAP1MCI2_RE Position  */
#define MCPWM_CAPCON_CAP1MCI2_RE_Msk                          (0x01UL << MCPWM_CAPCON_CAP1MCI2_RE_Pos)                  /*!< MCPWM CAPCON: CAP1MCI2_RE Mask      */
#define MCPWM_CAPCON_CAP1MCI2_FE_Pos                          11                                                        /*!< MCPWM CAPCON: CAP1MCI2_FE Position  */
#define MCPWM_CAPCON_CAP1MCI2_FE_Msk                          (0x01UL << MCPWM_CAPCON_CAP1MCI2_FE_Pos)                  /*!< MCPWM CAPCON: CAP1MCI2_FE Mask      */
#define MCPWM_CAPCON_CAP2MCI0_RE_Pos                          12                                                        /*!< MCPWM CAPCON: CAP2MCI0_RE Position  */
#define MCPWM_CAPCON_CAP2MCI0_RE_Msk                          (0x01UL << MCPWM_CAPCON_CAP2MCI0_RE_Pos)                  /*!< MCPWM CAPCON: CAP2MCI0_RE Mask      */
#define MCPWM_CAPCON_CAP2MCI0_FE_Pos                          13                                                        /*!< MCPWM CAPCON: CAP2MCI0_FE Position  */
#define MCPWM_CAPCON_CAP2MCI0_FE_Msk                          (0x01UL << MCPWM_CAPCON_CAP2MCI0_FE_Pos)                  /*!< MCPWM CAPCON: CAP2MCI0_FE Mask      */
#define MCPWM_CAPCON_CAP2MCI1_RE_Pos                          14                                                        /*!< MCPWM CAPCON: CAP2MCI1_RE Position  */
#define MCPWM_CAPCON_CAP2MCI1_RE_Msk                          (0x01UL << MCPWM_CAPCON_CAP2MCI1_RE_Pos)                  /*!< MCPWM CAPCON: CAP2MCI1_RE Mask      */
#define MCPWM_CAPCON_CAP2MCI1_FE_Pos                          15                                                        /*!< MCPWM CAPCON: CAP2MCI1_FE Position  */
#define MCPWM_CAPCON_CAP2MCI1_FE_Msk                          (0x01UL << MCPWM_CAPCON_CAP2MCI1_FE_Pos)                  /*!< MCPWM CAPCON: CAP2MCI1_FE Mask      */
#define MCPWM_CAPCON_CAP2MCI2_RE_Pos                          16                                                        /*!< MCPWM CAPCON: CAP2MCI2_RE Position  */
#define MCPWM_CAPCON_CAP2MCI2_RE_Msk                          (0x01UL << MCPWM_CAPCON_CAP2MCI2_RE_Pos)                  /*!< MCPWM CAPCON: CAP2MCI2_RE Mask      */
#define MCPWM_CAPCON_CAP2MCI2_FE_Pos                          17                                                        /*!< MCPWM CAPCON: CAP2MCI2_FE Position  */
#define MCPWM_CAPCON_CAP2MCI2_FE_Msk                          (0x01UL << MCPWM_CAPCON_CAP2MCI2_FE_Pos)                  /*!< MCPWM CAPCON: CAP2MCI2_FE Mask      */
#define MCPWM_CAPCON_RT0_Pos                                  18                                                        /*!< MCPWM CAPCON: RT0 Position          */
#define MCPWM_CAPCON_RT0_Msk                                  (0x01UL << MCPWM_CAPCON_RT0_Pos)                          /*!< MCPWM CAPCON: RT0 Mask              */
#define MCPWM_CAPCON_RT1_Pos                                  19                                                        /*!< MCPWM CAPCON: RT1 Position          */
#define MCPWM_CAPCON_RT1_Msk                                  (0x01UL << MCPWM_CAPCON_RT1_Pos)                          /*!< MCPWM CAPCON: RT1 Mask              */
#define MCPWM_CAPCON_RT2_Pos                                  20                                                        /*!< MCPWM CAPCON: RT2 Position          */
#define MCPWM_CAPCON_RT2_Msk                                  (0x01UL << MCPWM_CAPCON_RT2_Pos)                          /*!< MCPWM CAPCON: RT2 Mask              */
#define MCPWM_CAPCON_HNFCAP0_Pos                              21                                                        /*!< MCPWM CAPCON: HNFCAP0 Position      */
#define MCPWM_CAPCON_HNFCAP0_Msk                              (0x01UL << MCPWM_CAPCON_HNFCAP0_Pos)                      /*!< MCPWM CAPCON: HNFCAP0 Mask          */
#define MCPWM_CAPCON_HNFCAP1_Pos                              22                                                        /*!< MCPWM CAPCON: HNFCAP1 Position      */
#define MCPWM_CAPCON_HNFCAP1_Msk                              (0x01UL << MCPWM_CAPCON_HNFCAP1_Pos)                      /*!< MCPWM CAPCON: HNFCAP1 Mask          */
#define MCPWM_CAPCON_HNFCAP2_Pos                              23                                                        /*!< MCPWM CAPCON: HNFCAP2 Position      */
#define MCPWM_CAPCON_HNFCAP2_Msk                              (0x01UL << MCPWM_CAPCON_HNFCAP2_Pos)                      /*!< MCPWM CAPCON: HNFCAP2 Mask          */

// ------------------------------------  MCPWM_CAPCON_SET  ----------------------------------------
#define MCPWM_CAPCON_SET_CAP0MCI0_RE_SET_Pos                  0                                                         /*!< MCPWM CAPCON_SET: CAP0MCI0_RE_SET Position */
#define MCPWM_CAPCON_SET_CAP0MCI0_RE_SET_Msk                  (0x01UL << MCPWM_CAPCON_SET_CAP0MCI0_RE_SET_Pos)          /*!< MCPWM CAPCON_SET: CAP0MCI0_RE_SET Mask */
#define MCPWM_CAPCON_SET_CAP0MCI0_FE_SET_Pos                  1                                                         /*!< MCPWM CAPCON_SET: CAP0MCI0_FE_SET Position */
#define MCPWM_CAPCON_SET_CAP0MCI0_FE_SET_Msk                  (0x01UL << MCPWM_CAPCON_SET_CAP0MCI0_FE_SET_Pos)          /*!< MCPWM CAPCON_SET: CAP0MCI0_FE_SET Mask */
#define MCPWM_CAPCON_SET_CAP0MCI1_RE_SET_Pos                  2                                                         /*!< MCPWM CAPCON_SET: CAP0MCI1_RE_SET Position */
#define MCPWM_CAPCON_SET_CAP0MCI1_RE_SET_Msk                  (0x01UL << MCPWM_CAPCON_SET_CAP0MCI1_RE_SET_Pos)          /*!< MCPWM CAPCON_SET: CAP0MCI1_RE_SET Mask */
#define MCPWM_CAPCON_SET_CAP0MCI1_FE_SET_Pos                  3                                                         /*!< MCPWM CAPCON_SET: CAP0MCI1_FE_SET Position */
#define MCPWM_CAPCON_SET_CAP0MCI1_FE_SET_Msk                  (0x01UL << MCPWM_CAPCON_SET_CAP0MCI1_FE_SET_Pos)          /*!< MCPWM CAPCON_SET: CAP0MCI1_FE_SET Mask */
#define MCPWM_CAPCON_SET_CAP0MCI2_RE_SET_Pos                  4                                                         /*!< MCPWM CAPCON_SET: CAP0MCI2_RE_SET Position */
#define MCPWM_CAPCON_SET_CAP0MCI2_RE_SET_Msk                  (0x01UL << MCPWM_CAPCON_SET_CAP0MCI2_RE_SET_Pos)          /*!< MCPWM CAPCON_SET: CAP0MCI2_RE_SET Mask */
#define MCPWM_CAPCON_SET_CAP0MCI2_FE_SET_Pos                  5                                                         /*!< MCPWM CAPCON_SET: CAP0MCI2_FE_SET Position */
#define MCPWM_CAPCON_SET_CAP0MCI2_FE_SET_Msk                  (0x01UL << MCPWM_CAPCON_SET_CAP0MCI2_FE_SET_Pos)          /*!< MCPWM CAPCON_SET: CAP0MCI2_FE_SET Mask */
#define MCPWM_CAPCON_SET_CAP1MCI0_RE_SET_Pos                  6                                                         /*!< MCPWM CAPCON_SET: CAP1MCI0_RE_SET Position */
#define MCPWM_CAPCON_SET_CAP1MCI0_RE_SET_Msk                  (0x01UL << MCPWM_CAPCON_SET_CAP1MCI0_RE_SET_Pos)          /*!< MCPWM CAPCON_SET: CAP1MCI0_RE_SET Mask */
#define MCPWM_CAPCON_SET_CAP1MCI0_FE_SET_Pos                  7                                                         /*!< MCPWM CAPCON_SET: CAP1MCI0_FE_SET Position */
#define MCPWM_CAPCON_SET_CAP1MCI0_FE_SET_Msk                  (0x01UL << MCPWM_CAPCON_SET_CAP1MCI0_FE_SET_Pos)          /*!< MCPWM CAPCON_SET: CAP1MCI0_FE_SET Mask */
#define MCPWM_CAPCON_SET_CAP1MCI1_RE_SET_Pos                  8                                                         /*!< MCPWM CAPCON_SET: CAP1MCI1_RE_SET Position */
#define MCPWM_CAPCON_SET_CAP1MCI1_RE_SET_Msk                  (0x01UL << MCPWM_CAPCON_SET_CAP1MCI1_RE_SET_Pos)          /*!< MCPWM CAPCON_SET: CAP1MCI1_RE_SET Mask */
#define MCPWM_CAPCON_SET_CAP1MCI1_FE_SET_Pos                  9                                                         /*!< MCPWM CAPCON_SET: CAP1MCI1_FE_SET Position */
#define MCPWM_CAPCON_SET_CAP1MCI1_FE_SET_Msk                  (0x01UL << MCPWM_CAPCON_SET_CAP1MCI1_FE_SET_Pos)          /*!< MCPWM CAPCON_SET: CAP1MCI1_FE_SET Mask */
#define MCPWM_CAPCON_SET_CAP1MCI2_RE_SET_Pos                  10                                                        /*!< MCPWM CAPCON_SET: CAP1MCI2_RE_SET Position */
#define MCPWM_CAPCON_SET_CAP1MCI2_RE_SET_Msk                  (0x01UL << MCPWM_CAPCON_SET_CAP1MCI2_RE_SET_Pos)          /*!< MCPWM CAPCON_SET: CAP1MCI2_RE_SET Mask */
#define MCPWM_CAPCON_SET_CAP1MCI2_FE_SET_Pos                  11                                                        /*!< MCPWM CAPCON_SET: CAP1MCI2_FE_SET Position */
#define MCPWM_CAPCON_SET_CAP1MCI2_FE_SET_Msk                  (0x01UL << MCPWM_CAPCON_SET_CAP1MCI2_FE_SET_Pos)          /*!< MCPWM CAPCON_SET: CAP1MCI2_FE_SET Mask */
#define MCPWM_CAPCON_SET_CAP2MCI0_RE_SET_Pos                  12                                                        /*!< MCPWM CAPCON_SET: CAP2MCI0_RE_SET Position */
#define MCPWM_CAPCON_SET_CAP2MCI0_RE_SET_Msk                  (0x01UL << MCPWM_CAPCON_SET_CAP2MCI0_RE_SET_Pos)          /*!< MCPWM CAPCON_SET: CAP2MCI0_RE_SET Mask */
#define MCPWM_CAPCON_SET_CAP2MCI0_FE_SET_Pos                  13                                                        /*!< MCPWM CAPCON_SET: CAP2MCI0_FE_SET Position */
#define MCPWM_CAPCON_SET_CAP2MCI0_FE_SET_Msk                  (0x01UL << MCPWM_CAPCON_SET_CAP2MCI0_FE_SET_Pos)          /*!< MCPWM CAPCON_SET: CAP2MCI0_FE_SET Mask */
#define MCPWM_CAPCON_SET_CAP2MCI1_RE_SET_Pos                  14                                                        /*!< MCPWM CAPCON_SET: CAP2MCI1_RE_SET Position */
#define MCPWM_CAPCON_SET_CAP2MCI1_RE_SET_Msk                  (0x01UL << MCPWM_CAPCON_SET_CAP2MCI1_RE_SET_Pos)          /*!< MCPWM CAPCON_SET: CAP2MCI1_RE_SET Mask */
#define MCPWM_CAPCON_SET_CAP2MCI1_FE_SET_Pos                  15                                                        /*!< MCPWM CAPCON_SET: CAP2MCI1_FE_SET Position */
#define MCPWM_CAPCON_SET_CAP2MCI1_FE_SET_Msk                  (0x01UL << MCPWM_CAPCON_SET_CAP2MCI1_FE_SET_Pos)          /*!< MCPWM CAPCON_SET: CAP2MCI1_FE_SET Mask */
#define MCPWM_CAPCON_SET_CAP2MCI2_RE_SET_Pos                  16                                                        /*!< MCPWM CAPCON_SET: CAP2MCI2_RE_SET Position */
#define MCPWM_CAPCON_SET_CAP2MCI2_RE_SET_Msk                  (0x01UL << MCPWM_CAPCON_SET_CAP2MCI2_RE_SET_Pos)          /*!< MCPWM CAPCON_SET: CAP2MCI2_RE_SET Mask */
#define MCPWM_CAPCON_SET_CAP2MCI2_FE_SET_Pos                  17                                                        /*!< MCPWM CAPCON_SET: CAP2MCI2_FE_SET Position */
#define MCPWM_CAPCON_SET_CAP2MCI2_FE_SET_Msk                  (0x01UL << MCPWM_CAPCON_SET_CAP2MCI2_FE_SET_Pos)          /*!< MCPWM CAPCON_SET: CAP2MCI2_FE_SET Mask */
#define MCPWM_CAPCON_SET_RT0_SET_Pos                          18                                                        /*!< MCPWM CAPCON_SET: RT0_SET Position  */
#define MCPWM_CAPCON_SET_RT0_SET_Msk                          (0x01UL << MCPWM_CAPCON_SET_RT0_SET_Pos)                  /*!< MCPWM CAPCON_SET: RT0_SET Mask      */
#define MCPWM_CAPCON_SET_RT1_SET_Pos                          19                                                        /*!< MCPWM CAPCON_SET: RT1_SET Position  */
#define MCPWM_CAPCON_SET_RT1_SET_Msk                          (0x01UL << MCPWM_CAPCON_SET_RT1_SET_Pos)                  /*!< MCPWM CAPCON_SET: RT1_SET Mask      */
#define MCPWM_CAPCON_SET_RT2_SET_Pos                          20                                                        /*!< MCPWM CAPCON_SET: RT2_SET Position  */
#define MCPWM_CAPCON_SET_RT2_SET_Msk                          (0x01UL << MCPWM_CAPCON_SET_RT2_SET_Pos)                  /*!< MCPWM CAPCON_SET: RT2_SET Mask      */
#define MCPWM_CAPCON_SET_HNFCAP0_SET_Pos                      21                                                        /*!< MCPWM CAPCON_SET: HNFCAP0_SET Position */
#define MCPWM_CAPCON_SET_HNFCAP0_SET_Msk                      (0x01UL << MCPWM_CAPCON_SET_HNFCAP0_SET_Pos)              /*!< MCPWM CAPCON_SET: HNFCAP0_SET Mask  */
#define MCPWM_CAPCON_SET_HNFCAP1_SET_Pos                      22                                                        /*!< MCPWM CAPCON_SET: HNFCAP1_SET Position */
#define MCPWM_CAPCON_SET_HNFCAP1_SET_Msk                      (0x01UL << MCPWM_CAPCON_SET_HNFCAP1_SET_Pos)              /*!< MCPWM CAPCON_SET: HNFCAP1_SET Mask  */
#define MCPWM_CAPCON_SET_HNFCAP2_SET_Pos                      23                                                        /*!< MCPWM CAPCON_SET: HNFCAP2_SET Position */
#define MCPWM_CAPCON_SET_HNFCAP2_SET_Msk                      (0x01UL << MCPWM_CAPCON_SET_HNFCAP2_SET_Pos)              /*!< MCPWM CAPCON_SET: HNFCAP2_SET Mask  */

// ------------------------------------  MCPWM_CAPCON_CLR  ----------------------------------------
#define MCPWM_CAPCON_CLR_CAP0MCI0_RE_CLR_Pos                  0                                                         /*!< MCPWM CAPCON_CLR: CAP0MCI0_RE_CLR Position */
#define MCPWM_CAPCON_CLR_CAP0MCI0_RE_CLR_Msk                  (0x01UL << MCPWM_CAPCON_CLR_CAP0MCI0_RE_CLR_Pos)          /*!< MCPWM CAPCON_CLR: CAP0MCI0_RE_CLR Mask */
#define MCPWM_CAPCON_CLR_CAP0MCI0_FE_CLR_Pos                  1                                                         /*!< MCPWM CAPCON_CLR: CAP0MCI0_FE_CLR Position */
#define MCPWM_CAPCON_CLR_CAP0MCI0_FE_CLR_Msk                  (0x01UL << MCPWM_CAPCON_CLR_CAP0MCI0_FE_CLR_Pos)          /*!< MCPWM CAPCON_CLR: CAP0MCI0_FE_CLR Mask */
#define MCPWM_CAPCON_CLR_CAP0MCI1_RE_CLR_Pos                  2                                                         /*!< MCPWM CAPCON_CLR: CAP0MCI1_RE_CLR Position */
#define MCPWM_CAPCON_CLR_CAP0MCI1_RE_CLR_Msk                  (0x01UL << MCPWM_CAPCON_CLR_CAP0MCI1_RE_CLR_Pos)          /*!< MCPWM CAPCON_CLR: CAP0MCI1_RE_CLR Mask */
#define MCPWM_CAPCON_CLR_CAP0MCI1_FE_CLR_Pos                  3                                                         /*!< MCPWM CAPCON_CLR: CAP0MCI1_FE_CLR Position */
#define MCPWM_CAPCON_CLR_CAP0MCI1_FE_CLR_Msk                  (0x01UL << MCPWM_CAPCON_CLR_CAP0MCI1_FE_CLR_Pos)          /*!< MCPWM CAPCON_CLR: CAP0MCI1_FE_CLR Mask */
#define MCPWM_CAPCON_CLR_CAP0MCI2_RE_CLR_Pos                  4                                                         /*!< MCPWM CAPCON_CLR: CAP0MCI2_RE_CLR Position */
#define MCPWM_CAPCON_CLR_CAP0MCI2_RE_CLR_Msk                  (0x01UL << MCPWM_CAPCON_CLR_CAP0MCI2_RE_CLR_Pos)          /*!< MCPWM CAPCON_CLR: CAP0MCI2_RE_CLR Mask */
#define MCPWM_CAPCON_CLR_CAP0MCI2_FE_CLR_Pos                  5                                                         /*!< MCPWM CAPCON_CLR: CAP0MCI2_FE_CLR Position */
#define MCPWM_CAPCON_CLR_CAP0MCI2_FE_CLR_Msk                  (0x01UL << MCPWM_CAPCON_CLR_CAP0MCI2_FE_CLR_Pos)          /*!< MCPWM CAPCON_CLR: CAP0MCI2_FE_CLR Mask */
#define MCPWM_CAPCON_CLR_CAP1MCI0_RE_CLR_Pos                  6                                                         /*!< MCPWM CAPCON_CLR: CAP1MCI0_RE_CLR Position */
#define MCPWM_CAPCON_CLR_CAP1MCI0_RE_CLR_Msk                  (0x01UL << MCPWM_CAPCON_CLR_CAP1MCI0_RE_CLR_Pos)          /*!< MCPWM CAPCON_CLR: CAP1MCI0_RE_CLR Mask */
#define MCPWM_CAPCON_CLR_CAP1MCI0_FE_CLR_Pos                  7                                                         /*!< MCPWM CAPCON_CLR: CAP1MCI0_FE_CLR Position */
#define MCPWM_CAPCON_CLR_CAP1MCI0_FE_CLR_Msk                  (0x01UL << MCPWM_CAPCON_CLR_CAP1MCI0_FE_CLR_Pos)          /*!< MCPWM CAPCON_CLR: CAP1MCI0_FE_CLR Mask */
#define MCPWM_CAPCON_CLR_CAP1MCI1_RE_CLR_Pos                  8                                                         /*!< MCPWM CAPCON_CLR: CAP1MCI1_RE_CLR Position */
#define MCPWM_CAPCON_CLR_CAP1MCI1_RE_CLR_Msk                  (0x01UL << MCPWM_CAPCON_CLR_CAP1MCI1_RE_CLR_Pos)          /*!< MCPWM CAPCON_CLR: CAP1MCI1_RE_CLR Mask */
#define MCPWM_CAPCON_CLR_CAP1MCI1_FE_CLR_Pos                  9                                                         /*!< MCPWM CAPCON_CLR: CAP1MCI1_FE_CLR Position */
#define MCPWM_CAPCON_CLR_CAP1MCI1_FE_CLR_Msk                  (0x01UL << MCPWM_CAPCON_CLR_CAP1MCI1_FE_CLR_Pos)          /*!< MCPWM CAPCON_CLR: CAP1MCI1_FE_CLR Mask */
#define MCPWM_CAPCON_CLR_CAP1MCI2_RE_CLR_Pos                  10                                                        /*!< MCPWM CAPCON_CLR: CAP1MCI2_RE_CLR Position */
#define MCPWM_CAPCON_CLR_CAP1MCI2_RE_CLR_Msk                  (0x01UL << MCPWM_CAPCON_CLR_CAP1MCI2_RE_CLR_Pos)          /*!< MCPWM CAPCON_CLR: CAP1MCI2_RE_CLR Mask */
#define MCPWM_CAPCON_CLR_CAP1MCI2_FE_CLR_Pos                  11                                                        /*!< MCPWM CAPCON_CLR: CAP1MCI2_FE_CLR Position */
#define MCPWM_CAPCON_CLR_CAP1MCI2_FE_CLR_Msk                  (0x01UL << MCPWM_CAPCON_CLR_CAP1MCI2_FE_CLR_Pos)          /*!< MCPWM CAPCON_CLR: CAP1MCI2_FE_CLR Mask */
#define MCPWM_CAPCON_CLR_CAP2MCI0_RE_CLR_Pos                  12                                                        /*!< MCPWM CAPCON_CLR: CAP2MCI0_RE_CLR Position */
#define MCPWM_CAPCON_CLR_CAP2MCI0_RE_CLR_Msk                  (0x01UL << MCPWM_CAPCON_CLR_CAP2MCI0_RE_CLR_Pos)          /*!< MCPWM CAPCON_CLR: CAP2MCI0_RE_CLR Mask */
#define MCPWM_CAPCON_CLR_CAP2MCI0_FE_CLR_Pos                  13                                                        /*!< MCPWM CAPCON_CLR: CAP2MCI0_FE_CLR Position */
#define MCPWM_CAPCON_CLR_CAP2MCI0_FE_CLR_Msk                  (0x01UL << MCPWM_CAPCON_CLR_CAP2MCI0_FE_CLR_Pos)          /*!< MCPWM CAPCON_CLR: CAP2MCI0_FE_CLR Mask */
#define MCPWM_CAPCON_CLR_CAP2MCI1_RE_CLR_Pos                  14                                                        /*!< MCPWM CAPCON_CLR: CAP2MCI1_RE_CLR Position */
#define MCPWM_CAPCON_CLR_CAP2MCI1_RE_CLR_Msk                  (0x01UL << MCPWM_CAPCON_CLR_CAP2MCI1_RE_CLR_Pos)          /*!< MCPWM CAPCON_CLR: CAP2MCI1_RE_CLR Mask */
#define MCPWM_CAPCON_CLR_CAP2MCI1_FE_CLR_Pos                  15                                                        /*!< MCPWM CAPCON_CLR: CAP2MCI1_FE_CLR Position */
#define MCPWM_CAPCON_CLR_CAP2MCI1_FE_CLR_Msk                  (0x01UL << MCPWM_CAPCON_CLR_CAP2MCI1_FE_CLR_Pos)          /*!< MCPWM CAPCON_CLR: CAP2MCI1_FE_CLR Mask */
#define MCPWM_CAPCON_CLR_CAP2MCI2_RE_CLR_Pos                  16                                                        /*!< MCPWM CAPCON_CLR: CAP2MCI2_RE_CLR Position */
#define MCPWM_CAPCON_CLR_CAP2MCI2_RE_CLR_Msk                  (0x01UL << MCPWM_CAPCON_CLR_CAP2MCI2_RE_CLR_Pos)          /*!< MCPWM CAPCON_CLR: CAP2MCI2_RE_CLR Mask */
#define MCPWM_CAPCON_CLR_CAP2MCI2_FE_CLR_Pos                  17                                                        /*!< MCPWM CAPCON_CLR: CAP2MCI2_FE_CLR Position */
#define MCPWM_CAPCON_CLR_CAP2MCI2_FE_CLR_Msk                  (0x01UL << MCPWM_CAPCON_CLR_CAP2MCI2_FE_CLR_Pos)          /*!< MCPWM CAPCON_CLR: CAP2MCI2_FE_CLR Mask */
#define MCPWM_CAPCON_CLR_RT0_CLR_Pos                          18                                                        /*!< MCPWM CAPCON_CLR: RT0_CLR Position  */
#define MCPWM_CAPCON_CLR_RT0_CLR_Msk                          (0x01UL << MCPWM_CAPCON_CLR_RT0_CLR_Pos)                  /*!< MCPWM CAPCON_CLR: RT0_CLR Mask      */
#define MCPWM_CAPCON_CLR_RT1_CLR_Pos                          19                                                        /*!< MCPWM CAPCON_CLR: RT1_CLR Position  */
#define MCPWM_CAPCON_CLR_RT1_CLR_Msk                          (0x01UL << MCPWM_CAPCON_CLR_RT1_CLR_Pos)                  /*!< MCPWM CAPCON_CLR: RT1_CLR Mask      */
#define MCPWM_CAPCON_CLR_RT2_CLR_Pos                          20                                                        /*!< MCPWM CAPCON_CLR: RT2_CLR Position  */
#define MCPWM_CAPCON_CLR_RT2_CLR_Msk                          (0x01UL << MCPWM_CAPCON_CLR_RT2_CLR_Pos)                  /*!< MCPWM CAPCON_CLR: RT2_CLR Mask      */
#define MCPWM_CAPCON_CLR_HNFCAP0_CLR_Pos                      21                                                        /*!< MCPWM CAPCON_CLR: HNFCAP0_CLR Position */
#define MCPWM_CAPCON_CLR_HNFCAP0_CLR_Msk                      (0x01UL << MCPWM_CAPCON_CLR_HNFCAP0_CLR_Pos)              /*!< MCPWM CAPCON_CLR: HNFCAP0_CLR Mask  */
#define MCPWM_CAPCON_CLR_HNFCAP1_CLR_Pos                      22                                                        /*!< MCPWM CAPCON_CLR: HNFCAP1_CLR Position */
#define MCPWM_CAPCON_CLR_HNFCAP1_CLR_Msk                      (0x01UL << MCPWM_CAPCON_CLR_HNFCAP1_CLR_Pos)              /*!< MCPWM CAPCON_CLR: HNFCAP1_CLR Mask  */
#define MCPWM_CAPCON_CLR_HNFCAP2_CLR_Pos                      23                                                        /*!< MCPWM CAPCON_CLR: HNFCAP2_CLR Position */
#define MCPWM_CAPCON_CLR_HNFCAP2_CLR_Msk                      (0x01UL << MCPWM_CAPCON_CLR_HNFCAP2_CLR_Pos)              /*!< MCPWM CAPCON_CLR: HNFCAP2_CLR Mask  */

// ----------------------------------------  MCPWM_TC0  -------------------------------------------
#define MCPWM_TC0_MCTC_Pos                                    0                                                         /*!< MCPWM TC0: MCTC Position            */
#define MCPWM_TC0_MCTC_Msk                                    (0xffffffffUL << MCPWM_TC0_MCTC_Pos)                      /*!< MCPWM TC0: MCTC Mask                */

// ----------------------------------------  MCPWM_TC1  -------------------------------------------
#define MCPWM_TC1_MCTC_Pos                                    0                                                         /*!< MCPWM TC1: MCTC Position            */
#define MCPWM_TC1_MCTC_Msk                                    (0xffffffffUL << MCPWM_TC1_MCTC_Pos)                      /*!< MCPWM TC1: MCTC Mask                */

// ----------------------------------------  MCPWM_TC2  -------------------------------------------
#define MCPWM_TC2_MCTC_Pos                                    0                                                         /*!< MCPWM TC2: MCTC Position            */
#define MCPWM_TC2_MCTC_Msk                                    (0xffffffffUL << MCPWM_TC2_MCTC_Pos)                      /*!< MCPWM TC2: MCTC Mask                */

// ---------------------------------------  MCPWM_LIM0  -------------------------------------------
#define MCPWM_LIM0_MCLIM_Pos                                  0                                                         /*!< MCPWM LIM0: MCLIM Position          */
#define MCPWM_LIM0_MCLIM_Msk                                  (0xffffffffUL << MCPWM_LIM0_MCLIM_Pos)                    /*!< MCPWM LIM0: MCLIM Mask              */

// ---------------------------------------  MCPWM_LIM1  -------------------------------------------
#define MCPWM_LIM1_MCLIM_Pos                                  0                                                         /*!< MCPWM LIM1: MCLIM Position          */
#define MCPWM_LIM1_MCLIM_Msk                                  (0xffffffffUL << MCPWM_LIM1_MCLIM_Pos)                    /*!< MCPWM LIM1: MCLIM Mask              */

// ---------------------------------------  MCPWM_LIM2  -------------------------------------------
#define MCPWM_LIM2_MCLIM_Pos                                  0                                                         /*!< MCPWM LIM2: MCLIM Position          */
#define MCPWM_LIM2_MCLIM_Msk                                  (0xffffffffUL << MCPWM_LIM2_MCLIM_Pos)                    /*!< MCPWM LIM2: MCLIM Mask              */

// ---------------------------------------  MCPWM_MAT0  -------------------------------------------
#define MCPWM_MAT0_MCMAT_Pos                                  0                                                         /*!< MCPWM MAT0: MCMAT Position          */
#define MCPWM_MAT0_MCMAT_Msk                                  (0xffffffffUL << MCPWM_MAT0_MCMAT_Pos)                    /*!< MCPWM MAT0: MCMAT Mask              */

// ---------------------------------------  MCPWM_MAT1  -------------------------------------------
#define MCPWM_MAT1_MCMAT_Pos                                  0                                                         /*!< MCPWM MAT1: MCMAT Position          */
#define MCPWM_MAT1_MCMAT_Msk                                  (0xffffffffUL << MCPWM_MAT1_MCMAT_Pos)                    /*!< MCPWM MAT1: MCMAT Mask              */

// ---------------------------------------  MCPWM_MAT2  -------------------------------------------
#define MCPWM_MAT2_MCMAT_Pos                                  0                                                         /*!< MCPWM MAT2: MCMAT Position          */
#define MCPWM_MAT2_MCMAT_Msk                                  (0xffffffffUL << MCPWM_MAT2_MCMAT_Pos)                    /*!< MCPWM MAT2: MCMAT Mask              */

// ----------------------------------------  MCPWM_DT  --------------------------------------------
#define MCPWM_DT_DT0_Pos                                      0                                                         /*!< MCPWM DT: DT0 Position              */
#define MCPWM_DT_DT0_Msk                                      (0x000003ffUL << MCPWM_DT_DT0_Pos)                        /*!< MCPWM DT: DT0 Mask                  */
#define MCPWM_DT_DT1_Pos                                      10                                                        /*!< MCPWM DT: DT1 Position              */
#define MCPWM_DT_DT1_Msk                                      (0x000003ffUL << MCPWM_DT_DT1_Pos)                        /*!< MCPWM DT: DT1 Mask                  */
#define MCPWM_DT_DT2_Pos                                      20                                                        /*!< MCPWM DT: DT2 Position              */
#define MCPWM_DT_DT2_Msk                                      (0x000003ffUL << MCPWM_DT_DT2_Pos)                        /*!< MCPWM DT: DT2 Mask                  */

// ----------------------------------------  MCPWM_CCP  -------------------------------------------
#define MCPWM_CCP_CCPA0_Pos                                   0                                                         /*!< MCPWM CCP: CCPA0 Position           */
#define MCPWM_CCP_CCPA0_Msk                                   (0x01UL << MCPWM_CCP_CCPA0_Pos)                           /*!< MCPWM CCP: CCPA0 Mask               */
#define MCPWM_CCP_CCPB0_Pos                                   1                                                         /*!< MCPWM CCP: CCPB0 Position           */
#define MCPWM_CCP_CCPB0_Msk                                   (0x01UL << MCPWM_CCP_CCPB0_Pos)                           /*!< MCPWM CCP: CCPB0 Mask               */
#define MCPWM_CCP_CCPA1_Pos                                   2                                                         /*!< MCPWM CCP: CCPA1 Position           */
#define MCPWM_CCP_CCPA1_Msk                                   (0x01UL << MCPWM_CCP_CCPA1_Pos)                           /*!< MCPWM CCP: CCPA1 Mask               */
#define MCPWM_CCP_CCPB1_Pos                                   3                                                         /*!< MCPWM CCP: CCPB1 Position           */
#define MCPWM_CCP_CCPB1_Msk                                   (0x01UL << MCPWM_CCP_CCPB1_Pos)                           /*!< MCPWM CCP: CCPB1 Mask               */
#define MCPWM_CCP_CCPA2_Pos                                   4                                                         /*!< MCPWM CCP: CCPA2 Position           */
#define MCPWM_CCP_CCPA2_Msk                                   (0x01UL << MCPWM_CCP_CCPA2_Pos)                           /*!< MCPWM CCP: CCPA2 Mask               */
#define MCPWM_CCP_CCPB2_Pos                                   5                                                         /*!< MCPWM CCP: CCPB2 Position           */
#define MCPWM_CCP_CCPB2_Msk                                   (0x01UL << MCPWM_CCP_CCPB2_Pos)                           /*!< MCPWM CCP: CCPB2 Mask               */

// ---------------------------------------  MCPWM_CAP0  -------------------------------------------
#define MCPWM_CAP0_CAP_Pos                                    0                                                         /*!< MCPWM CAP0: CAP Position            */
#define MCPWM_CAP0_CAP_Msk                                    (0xffffffffUL << MCPWM_CAP0_CAP_Pos)                      /*!< MCPWM CAP0: CAP Mask                */

// ---------------------------------------  MCPWM_CAP1  -------------------------------------------
#define MCPWM_CAP1_CAP_Pos                                    0                                                         /*!< MCPWM CAP1: CAP Position            */
#define MCPWM_CAP1_CAP_Msk                                    (0xffffffffUL << MCPWM_CAP1_CAP_Pos)                      /*!< MCPWM CAP1: CAP Mask                */

// ---------------------------------------  MCPWM_CAP2  -------------------------------------------
#define MCPWM_CAP2_CAP_Pos                                    0                                                         /*!< MCPWM CAP2: CAP Position            */
#define MCPWM_CAP2_CAP_Msk                                    (0xffffffffUL << MCPWM_CAP2_CAP_Pos)                      /*!< MCPWM CAP2: CAP Mask                */

// ---------------------------------------  MCPWM_INTEN  ------------------------------------------
#define MCPWM_INTEN_ILIM0_Pos                                 0                                                         /*!< MCPWM INTEN: ILIM0 Position         */
#define MCPWM_INTEN_ILIM0_Msk                                 (0x01UL << MCPWM_INTEN_ILIM0_Pos)                         /*!< MCPWM INTEN: ILIM0 Mask             */
#define MCPWM_INTEN_IMAT0_Pos                                 1                                                         /*!< MCPWM INTEN: IMAT0 Position         */
#define MCPWM_INTEN_IMAT0_Msk                                 (0x01UL << MCPWM_INTEN_IMAT0_Pos)                         /*!< MCPWM INTEN: IMAT0 Mask             */
#define MCPWM_INTEN_ICAP0_Pos                                 2                                                         /*!< MCPWM INTEN: ICAP0 Position         */
#define MCPWM_INTEN_ICAP0_Msk                                 (0x01UL << MCPWM_INTEN_ICAP0_Pos)                         /*!< MCPWM INTEN: ICAP0 Mask             */
#define MCPWM_INTEN_ILIM1_Pos                                 4                                                         /*!< MCPWM INTEN: ILIM1 Position         */
#define MCPWM_INTEN_ILIM1_Msk                                 (0x01UL << MCPWM_INTEN_ILIM1_Pos)                         /*!< MCPWM INTEN: ILIM1 Mask             */
#define MCPWM_INTEN_IMAT1_Pos                                 5                                                         /*!< MCPWM INTEN: IMAT1 Position         */
#define MCPWM_INTEN_IMAT1_Msk                                 (0x01UL << MCPWM_INTEN_IMAT1_Pos)                         /*!< MCPWM INTEN: IMAT1 Mask             */
#define MCPWM_INTEN_ICAP1_Pos                                 6                                                         /*!< MCPWM INTEN: ICAP1 Position         */
#define MCPWM_INTEN_ICAP1_Msk                                 (0x01UL << MCPWM_INTEN_ICAP1_Pos)                         /*!< MCPWM INTEN: ICAP1 Mask             */
#define MCPWM_INTEN_ILIM2_Pos                                 8                                                         /*!< MCPWM INTEN: ILIM2 Position         */
#define MCPWM_INTEN_ILIM2_Msk                                 (0x01UL << MCPWM_INTEN_ILIM2_Pos)                         /*!< MCPWM INTEN: ILIM2 Mask             */
#define MCPWM_INTEN_IMAT2_Pos                                 9                                                         /*!< MCPWM INTEN: IMAT2 Position         */
#define MCPWM_INTEN_IMAT2_Msk                                 (0x01UL << MCPWM_INTEN_IMAT2_Pos)                         /*!< MCPWM INTEN: IMAT2 Mask             */
#define MCPWM_INTEN_ICAP2_Pos                                 10                                                        /*!< MCPWM INTEN: ICAP2 Position         */
#define MCPWM_INTEN_ICAP2_Msk                                 (0x01UL << MCPWM_INTEN_ICAP2_Pos)                         /*!< MCPWM INTEN: ICAP2 Mask             */
#define MCPWM_INTEN_ABORT_Pos                                 15                                                        /*!< MCPWM INTEN: ABORT Position         */
#define MCPWM_INTEN_ABORT_Msk                                 (0x01UL << MCPWM_INTEN_ABORT_Pos)                         /*!< MCPWM INTEN: ABORT Mask             */

// -------------------------------------  MCPWM_INTEN_SET  ----------------------------------------
#define MCPWM_INTEN_SET_ILIM0_SET_Pos                         0                                                         /*!< MCPWM INTEN_SET: ILIM0_SET Position */
#define MCPWM_INTEN_SET_ILIM0_SET_Msk                         (0x01UL << MCPWM_INTEN_SET_ILIM0_SET_Pos)                 /*!< MCPWM INTEN_SET: ILIM0_SET Mask     */
#define MCPWM_INTEN_SET_IMAT0_SET_Pos                         1                                                         /*!< MCPWM INTEN_SET: IMAT0_SET Position */
#define MCPWM_INTEN_SET_IMAT0_SET_Msk                         (0x01UL << MCPWM_INTEN_SET_IMAT0_SET_Pos)                 /*!< MCPWM INTEN_SET: IMAT0_SET Mask     */
#define MCPWM_INTEN_SET_ICAP0_SET_Pos                         2                                                         /*!< MCPWM INTEN_SET: ICAP0_SET Position */
#define MCPWM_INTEN_SET_ICAP0_SET_Msk                         (0x01UL << MCPWM_INTEN_SET_ICAP0_SET_Pos)                 /*!< MCPWM INTEN_SET: ICAP0_SET Mask     */
#define MCPWM_INTEN_SET_ILIM1_SET_Pos                         4                                                         /*!< MCPWM INTEN_SET: ILIM1_SET Position */
#define MCPWM_INTEN_SET_ILIM1_SET_Msk                         (0x01UL << MCPWM_INTEN_SET_ILIM1_SET_Pos)                 /*!< MCPWM INTEN_SET: ILIM1_SET Mask     */
#define MCPWM_INTEN_SET_IMAT1_SET_Pos                         5                                                         /*!< MCPWM INTEN_SET: IMAT1_SET Position */
#define MCPWM_INTEN_SET_IMAT1_SET_Msk                         (0x01UL << MCPWM_INTEN_SET_IMAT1_SET_Pos)                 /*!< MCPWM INTEN_SET: IMAT1_SET Mask     */
#define MCPWM_INTEN_SET_ICAP1_SET_Pos                         6                                                         /*!< MCPWM INTEN_SET: ICAP1_SET Position */
#define MCPWM_INTEN_SET_ICAP1_SET_Msk                         (0x01UL << MCPWM_INTEN_SET_ICAP1_SET_Pos)                 /*!< MCPWM INTEN_SET: ICAP1_SET Mask     */
#define MCPWM_INTEN_SET_ILIM2_SET_Pos                         9                                                         /*!< MCPWM INTEN_SET: ILIM2_SET Position */
#define MCPWM_INTEN_SET_ILIM2_SET_Msk                         (0x01UL << MCPWM_INTEN_SET_ILIM2_SET_Pos)                 /*!< MCPWM INTEN_SET: ILIM2_SET Mask     */
#define MCPWM_INTEN_SET_IMAT2_SET_Pos                         10                                                        /*!< MCPWM INTEN_SET: IMAT2_SET Position */
#define MCPWM_INTEN_SET_IMAT2_SET_Msk                         (0x01UL << MCPWM_INTEN_SET_IMAT2_SET_Pos)                 /*!< MCPWM INTEN_SET: IMAT2_SET Mask     */
#define MCPWM_INTEN_SET_ICAP2_SET_Pos                         11                                                        /*!< MCPWM INTEN_SET: ICAP2_SET Position */
#define MCPWM_INTEN_SET_ICAP2_SET_Msk                         (0x01UL << MCPWM_INTEN_SET_ICAP2_SET_Pos)                 /*!< MCPWM INTEN_SET: ICAP2_SET Mask     */
#define MCPWM_INTEN_SET_ABORT_SET_Pos                         15                                                        /*!< MCPWM INTEN_SET: ABORT_SET Position */
#define MCPWM_INTEN_SET_ABORT_SET_Msk                         (0x01UL << MCPWM_INTEN_SET_ABORT_SET_Pos)                 /*!< MCPWM INTEN_SET: ABORT_SET Mask     */

// -------------------------------------  MCPWM_INTEN_CLR  ----------------------------------------
#define MCPWM_INTEN_CLR_ILIM0_CLR_Pos                         0                                                         /*!< MCPWM INTEN_CLR: ILIM0_CLR Position */
#define MCPWM_INTEN_CLR_ILIM0_CLR_Msk                         (0x01UL << MCPWM_INTEN_CLR_ILIM0_CLR_Pos)                 /*!< MCPWM INTEN_CLR: ILIM0_CLR Mask     */
#define MCPWM_INTEN_CLR_IMAT0_CLR_Pos                         1                                                         /*!< MCPWM INTEN_CLR: IMAT0_CLR Position */
#define MCPWM_INTEN_CLR_IMAT0_CLR_Msk                         (0x01UL << MCPWM_INTEN_CLR_IMAT0_CLR_Pos)                 /*!< MCPWM INTEN_CLR: IMAT0_CLR Mask     */
#define MCPWM_INTEN_CLR_ICAP0_CLR_Pos                         2                                                         /*!< MCPWM INTEN_CLR: ICAP0_CLR Position */
#define MCPWM_INTEN_CLR_ICAP0_CLR_Msk                         (0x01UL << MCPWM_INTEN_CLR_ICAP0_CLR_Pos)                 /*!< MCPWM INTEN_CLR: ICAP0_CLR Mask     */
#define MCPWM_INTEN_CLR_ILIM1_CLR_Pos                         4                                                         /*!< MCPWM INTEN_CLR: ILIM1_CLR Position */
#define MCPWM_INTEN_CLR_ILIM1_CLR_Msk                         (0x01UL << MCPWM_INTEN_CLR_ILIM1_CLR_Pos)                 /*!< MCPWM INTEN_CLR: ILIM1_CLR Mask     */
#define MCPWM_INTEN_CLR_IMAT1_CLR_Pos                         5                                                         /*!< MCPWM INTEN_CLR: IMAT1_CLR Position */
#define MCPWM_INTEN_CLR_IMAT1_CLR_Msk                         (0x01UL << MCPWM_INTEN_CLR_IMAT1_CLR_Pos)                 /*!< MCPWM INTEN_CLR: IMAT1_CLR Mask     */
#define MCPWM_INTEN_CLR_ICAP1_CLR_Pos                         6                                                         /*!< MCPWM INTEN_CLR: ICAP1_CLR Position */
#define MCPWM_INTEN_CLR_ICAP1_CLR_Msk                         (0x01UL << MCPWM_INTEN_CLR_ICAP1_CLR_Pos)                 /*!< MCPWM INTEN_CLR: ICAP1_CLR Mask     */
#define MCPWM_INTEN_CLR_ILIM2_CLR_Pos                         8                                                         /*!< MCPWM INTEN_CLR: ILIM2_CLR Position */
#define MCPWM_INTEN_CLR_ILIM2_CLR_Msk                         (0x01UL << MCPWM_INTEN_CLR_ILIM2_CLR_Pos)                 /*!< MCPWM INTEN_CLR: ILIM2_CLR Mask     */
#define MCPWM_INTEN_CLR_IMAT2_CLR_Pos                         9                                                         /*!< MCPWM INTEN_CLR: IMAT2_CLR Position */
#define MCPWM_INTEN_CLR_IMAT2_CLR_Msk                         (0x01UL << MCPWM_INTEN_CLR_IMAT2_CLR_Pos)                 /*!< MCPWM INTEN_CLR: IMAT2_CLR Mask     */
#define MCPWM_INTEN_CLR_ICAP2_CLR_Pos                         10                                                        /*!< MCPWM INTEN_CLR: ICAP2_CLR Position */
#define MCPWM_INTEN_CLR_ICAP2_CLR_Msk                         (0x01UL << MCPWM_INTEN_CLR_ICAP2_CLR_Pos)                 /*!< MCPWM INTEN_CLR: ICAP2_CLR Mask     */
#define MCPWM_INTEN_CLR_ABORT_CLR_Pos                         15                                                        /*!< MCPWM INTEN_CLR: ABORT_CLR Position */
#define MCPWM_INTEN_CLR_ABORT_CLR_Msk                         (0x01UL << MCPWM_INTEN_CLR_ABORT_CLR_Pos)                 /*!< MCPWM INTEN_CLR: ABORT_CLR Mask     */

// --------------------------------------  MCPWM_CNTCON  ------------------------------------------
#define MCPWM_CNTCON_TC0MCI0_RE_Pos                           0                                                         /*!< MCPWM CNTCON: TC0MCI0_RE Position   */
#define MCPWM_CNTCON_TC0MCI0_RE_Msk                           (0x01UL << MCPWM_CNTCON_TC0MCI0_RE_Pos)                   /*!< MCPWM CNTCON: TC0MCI0_RE Mask       */
#define MCPWM_CNTCON_TC0MCI0_FE_Pos                           1                                                         /*!< MCPWM CNTCON: TC0MCI0_FE Position   */
#define MCPWM_CNTCON_TC0MCI0_FE_Msk                           (0x01UL << MCPWM_CNTCON_TC0MCI0_FE_Pos)                   /*!< MCPWM CNTCON: TC0MCI0_FE Mask       */
#define MCPWM_CNTCON_TC0MCI1_RE_Pos                           2                                                         /*!< MCPWM CNTCON: TC0MCI1_RE Position   */
#define MCPWM_CNTCON_TC0MCI1_RE_Msk                           (0x01UL << MCPWM_CNTCON_TC0MCI1_RE_Pos)                   /*!< MCPWM CNTCON: TC0MCI1_RE Mask       */
#define MCPWM_CNTCON_TC0MCI1_FE_Pos                           3                                                         /*!< MCPWM CNTCON: TC0MCI1_FE Position   */
#define MCPWM_CNTCON_TC0MCI1_FE_Msk                           (0x01UL << MCPWM_CNTCON_TC0MCI1_FE_Pos)                   /*!< MCPWM CNTCON: TC0MCI1_FE Mask       */
#define MCPWM_CNTCON_TC0MCI2_RE_Pos                           4                                                         /*!< MCPWM CNTCON: TC0MCI2_RE Position   */
#define MCPWM_CNTCON_TC0MCI2_RE_Msk                           (0x01UL << MCPWM_CNTCON_TC0MCI2_RE_Pos)                   /*!< MCPWM CNTCON: TC0MCI2_RE Mask       */
#define MCPWM_CNTCON_TC0MCI2_FE_Pos                           5                                                         /*!< MCPWM CNTCON: TC0MCI2_FE Position   */
#define MCPWM_CNTCON_TC0MCI2_FE_Msk                           (0x01UL << MCPWM_CNTCON_TC0MCI2_FE_Pos)                   /*!< MCPWM CNTCON: TC0MCI2_FE Mask       */
#define MCPWM_CNTCON_TC1MCI0_RE_Pos                           6                                                         /*!< MCPWM CNTCON: TC1MCI0_RE Position   */
#define MCPWM_CNTCON_TC1MCI0_RE_Msk                           (0x01UL << MCPWM_CNTCON_TC1MCI0_RE_Pos)                   /*!< MCPWM CNTCON: TC1MCI0_RE Mask       */
#define MCPWM_CNTCON_TC1MCI0_FE_Pos                           7                                                         /*!< MCPWM CNTCON: TC1MCI0_FE Position   */
#define MCPWM_CNTCON_TC1MCI0_FE_Msk                           (0x01UL << MCPWM_CNTCON_TC1MCI0_FE_Pos)                   /*!< MCPWM CNTCON: TC1MCI0_FE Mask       */
#define MCPWM_CNTCON_TC1MCI1_RE_Pos                           8                                                         /*!< MCPWM CNTCON: TC1MCI1_RE Position   */
#define MCPWM_CNTCON_TC1MCI1_RE_Msk                           (0x01UL << MCPWM_CNTCON_TC1MCI1_RE_Pos)                   /*!< MCPWM CNTCON: TC1MCI1_RE Mask       */
#define MCPWM_CNTCON_TC1MCI1_FE_Pos                           9                                                         /*!< MCPWM CNTCON: TC1MCI1_FE Position   */
#define MCPWM_CNTCON_TC1MCI1_FE_Msk                           (0x01UL << MCPWM_CNTCON_TC1MCI1_FE_Pos)                   /*!< MCPWM CNTCON: TC1MCI1_FE Mask       */
#define MCPWM_CNTCON_TC1MCI2_RE_Pos                           10                                                        /*!< MCPWM CNTCON: TC1MCI2_RE Position   */
#define MCPWM_CNTCON_TC1MCI2_RE_Msk                           (0x01UL << MCPWM_CNTCON_TC1MCI2_RE_Pos)                   /*!< MCPWM CNTCON: TC1MCI2_RE Mask       */
#define MCPWM_CNTCON_TC1MCI2_FE_Pos                           11                                                        /*!< MCPWM CNTCON: TC1MCI2_FE Position   */
#define MCPWM_CNTCON_TC1MCI2_FE_Msk                           (0x01UL << MCPWM_CNTCON_TC1MCI2_FE_Pos)                   /*!< MCPWM CNTCON: TC1MCI2_FE Mask       */
#define MCPWM_CNTCON_TC2MCI0_RE_Pos                           12                                                        /*!< MCPWM CNTCON: TC2MCI0_RE Position   */
#define MCPWM_CNTCON_TC2MCI0_RE_Msk                           (0x01UL << MCPWM_CNTCON_TC2MCI0_RE_Pos)                   /*!< MCPWM CNTCON: TC2MCI0_RE Mask       */
#define MCPWM_CNTCON_TC2MCI0_FE_Pos                           13                                                        /*!< MCPWM CNTCON: TC2MCI0_FE Position   */
#define MCPWM_CNTCON_TC2MCI0_FE_Msk                           (0x01UL << MCPWM_CNTCON_TC2MCI0_FE_Pos)                   /*!< MCPWM CNTCON: TC2MCI0_FE Mask       */
#define MCPWM_CNTCON_TC2MCI1_RE_Pos                           14                                                        /*!< MCPWM CNTCON: TC2MCI1_RE Position   */
#define MCPWM_CNTCON_TC2MCI1_RE_Msk                           (0x01UL << MCPWM_CNTCON_TC2MCI1_RE_Pos)                   /*!< MCPWM CNTCON: TC2MCI1_RE Mask       */
#define MCPWM_CNTCON_TC2MCI1_FE_Pos                           15                                                        /*!< MCPWM CNTCON: TC2MCI1_FE Position   */
#define MCPWM_CNTCON_TC2MCI1_FE_Msk                           (0x01UL << MCPWM_CNTCON_TC2MCI1_FE_Pos)                   /*!< MCPWM CNTCON: TC2MCI1_FE Mask       */
#define MCPWM_CNTCON_TC2MCI2_RE_Pos                           16                                                        /*!< MCPWM CNTCON: TC2MCI2_RE Position   */
#define MCPWM_CNTCON_TC2MCI2_RE_Msk                           (0x01UL << MCPWM_CNTCON_TC2MCI2_RE_Pos)                   /*!< MCPWM CNTCON: TC2MCI2_RE Mask       */
#define MCPWM_CNTCON_TC2MCI2_FE_Pos                           17                                                        /*!< MCPWM CNTCON: TC2MCI2_FE Position   */
#define MCPWM_CNTCON_TC2MCI2_FE_Msk                           (0x01UL << MCPWM_CNTCON_TC2MCI2_FE_Pos)                   /*!< MCPWM CNTCON: TC2MCI2_FE Mask       */
#define MCPWM_CNTCON_CNTR0_Pos                                29                                                        /*!< MCPWM CNTCON: CNTR0 Position        */
#define MCPWM_CNTCON_CNTR0_Msk                                (0x01UL << MCPWM_CNTCON_CNTR0_Pos)                        /*!< MCPWM CNTCON: CNTR0 Mask            */
#define MCPWM_CNTCON_CNTR1_Pos                                30                                                        /*!< MCPWM CNTCON: CNTR1 Position        */
#define MCPWM_CNTCON_CNTR1_Msk                                (0x01UL << MCPWM_CNTCON_CNTR1_Pos)                        /*!< MCPWM CNTCON: CNTR1 Mask            */
#define MCPWM_CNTCON_CNTR2_Pos                                31                                                        /*!< MCPWM CNTCON: CNTR2 Position        */
#define MCPWM_CNTCON_CNTR2_Msk                                (0x01UL << MCPWM_CNTCON_CNTR2_Pos)                        /*!< MCPWM CNTCON: CNTR2 Mask            */

// ------------------------------------  MCPWM_CNTCON_SET  ----------------------------------------
#define MCPWM_CNTCON_SET_TC0MCI0_RE_SET_Pos                   0                                                         /*!< MCPWM CNTCON_SET: TC0MCI0_RE_SET Position */
#define MCPWM_CNTCON_SET_TC0MCI0_RE_SET_Msk                   (0x01UL << MCPWM_CNTCON_SET_TC0MCI0_RE_SET_Pos)           /*!< MCPWM CNTCON_SET: TC0MCI0_RE_SET Mask */
#define MCPWM_CNTCON_SET_TC0MCI0_FE_SET_Pos                   1                                                         /*!< MCPWM CNTCON_SET: TC0MCI0_FE_SET Position */
#define MCPWM_CNTCON_SET_TC0MCI0_FE_SET_Msk                   (0x01UL << MCPWM_CNTCON_SET_TC0MCI0_FE_SET_Pos)           /*!< MCPWM CNTCON_SET: TC0MCI0_FE_SET Mask */
#define MCPWM_CNTCON_SET_TC0MCI1_RE_SET_Pos                   2                                                         /*!< MCPWM CNTCON_SET: TC0MCI1_RE_SET Position */
#define MCPWM_CNTCON_SET_TC0MCI1_RE_SET_Msk                   (0x01UL << MCPWM_CNTCON_SET_TC0MCI1_RE_SET_Pos)           /*!< MCPWM CNTCON_SET: TC0MCI1_RE_SET Mask */
#define MCPWM_CNTCON_SET_TC0MCI1_FE_SET_Pos                   3                                                         /*!< MCPWM CNTCON_SET: TC0MCI1_FE_SET Position */
#define MCPWM_CNTCON_SET_TC0MCI1_FE_SET_Msk                   (0x01UL << MCPWM_CNTCON_SET_TC0MCI1_FE_SET_Pos)           /*!< MCPWM CNTCON_SET: TC0MCI1_FE_SET Mask */
#define MCPWM_CNTCON_SET_TC0MCI2_RE_SET_Pos                   4                                                         /*!< MCPWM CNTCON_SET: TC0MCI2_RE_SET Position */
#define MCPWM_CNTCON_SET_TC0MCI2_RE_SET_Msk                   (0x01UL << MCPWM_CNTCON_SET_TC0MCI2_RE_SET_Pos)           /*!< MCPWM CNTCON_SET: TC0MCI2_RE_SET Mask */
#define MCPWM_CNTCON_SET_TC0MCI2_FE_SET_Pos                   5                                                         /*!< MCPWM CNTCON_SET: TC0MCI2_FE_SET Position */
#define MCPWM_CNTCON_SET_TC0MCI2_FE_SET_Msk                   (0x01UL << MCPWM_CNTCON_SET_TC0MCI2_FE_SET_Pos)           /*!< MCPWM CNTCON_SET: TC0MCI2_FE_SET Mask */
#define MCPWM_CNTCON_SET_TC1MCI0_RE_SET_Pos                   6                                                         /*!< MCPWM CNTCON_SET: TC1MCI0_RE_SET Position */
#define MCPWM_CNTCON_SET_TC1MCI0_RE_SET_Msk                   (0x01UL << MCPWM_CNTCON_SET_TC1MCI0_RE_SET_Pos)           /*!< MCPWM CNTCON_SET: TC1MCI0_RE_SET Mask */
#define MCPWM_CNTCON_SET_TC1MCI0_FE_SET_Pos                   7                                                         /*!< MCPWM CNTCON_SET: TC1MCI0_FE_SET Position */
#define MCPWM_CNTCON_SET_TC1MCI0_FE_SET_Msk                   (0x01UL << MCPWM_CNTCON_SET_TC1MCI0_FE_SET_Pos)           /*!< MCPWM CNTCON_SET: TC1MCI0_FE_SET Mask */
#define MCPWM_CNTCON_SET_TC1MCI1_RE_SET_Pos                   8                                                         /*!< MCPWM CNTCON_SET: TC1MCI1_RE_SET Position */
#define MCPWM_CNTCON_SET_TC1MCI1_RE_SET_Msk                   (0x01UL << MCPWM_CNTCON_SET_TC1MCI1_RE_SET_Pos)           /*!< MCPWM CNTCON_SET: TC1MCI1_RE_SET Mask */
#define MCPWM_CNTCON_SET_TC1MCI1_FE_SET_Pos                   9                                                         /*!< MCPWM CNTCON_SET: TC1MCI1_FE_SET Position */
#define MCPWM_CNTCON_SET_TC1MCI1_FE_SET_Msk                   (0x01UL << MCPWM_CNTCON_SET_TC1MCI1_FE_SET_Pos)           /*!< MCPWM CNTCON_SET: TC1MCI1_FE_SET Mask */
#define MCPWM_CNTCON_SET_TC1MCI2_RE_SET_Pos                   10                                                        /*!< MCPWM CNTCON_SET: TC1MCI2_RE_SET Position */
#define MCPWM_CNTCON_SET_TC1MCI2_RE_SET_Msk                   (0x01UL << MCPWM_CNTCON_SET_TC1MCI2_RE_SET_Pos)           /*!< MCPWM CNTCON_SET: TC1MCI2_RE_SET Mask */
#define MCPWM_CNTCON_SET_TC1MCI2_FE_SET_Pos                   11                                                        /*!< MCPWM CNTCON_SET: TC1MCI2_FE_SET Position */
#define MCPWM_CNTCON_SET_TC1MCI2_FE_SET_Msk                   (0x01UL << MCPWM_CNTCON_SET_TC1MCI2_FE_SET_Pos)           /*!< MCPWM CNTCON_SET: TC1MCI2_FE_SET Mask */
#define MCPWM_CNTCON_SET_TC2MCI0_RE_SET_Pos                   12                                                        /*!< MCPWM CNTCON_SET: TC2MCI0_RE_SET Position */
#define MCPWM_CNTCON_SET_TC2MCI0_RE_SET_Msk                   (0x01UL << MCPWM_CNTCON_SET_TC2MCI0_RE_SET_Pos)           /*!< MCPWM CNTCON_SET: TC2MCI0_RE_SET Mask */
#define MCPWM_CNTCON_SET_TC2MCI0_FE_SET_Pos                   13                                                        /*!< MCPWM CNTCON_SET: TC2MCI0_FE_SET Position */
#define MCPWM_CNTCON_SET_TC2MCI0_FE_SET_Msk                   (0x01UL << MCPWM_CNTCON_SET_TC2MCI0_FE_SET_Pos)           /*!< MCPWM CNTCON_SET: TC2MCI0_FE_SET Mask */
#define MCPWM_CNTCON_SET_TC2MCI1_RE_SET_Pos                   14                                                        /*!< MCPWM CNTCON_SET: TC2MCI1_RE_SET Position */
#define MCPWM_CNTCON_SET_TC2MCI1_RE_SET_Msk                   (0x01UL << MCPWM_CNTCON_SET_TC2MCI1_RE_SET_Pos)           /*!< MCPWM CNTCON_SET: TC2MCI1_RE_SET Mask */
#define MCPWM_CNTCON_SET_TC2MCI1_FE_SET_Pos                   15                                                        /*!< MCPWM CNTCON_SET: TC2MCI1_FE_SET Position */
#define MCPWM_CNTCON_SET_TC2MCI1_FE_SET_Msk                   (0x01UL << MCPWM_CNTCON_SET_TC2MCI1_FE_SET_Pos)           /*!< MCPWM CNTCON_SET: TC2MCI1_FE_SET Mask */
#define MCPWM_CNTCON_SET_TC2MCI2_RE_SET_Pos                   16                                                        /*!< MCPWM CNTCON_SET: TC2MCI2_RE_SET Position */
#define MCPWM_CNTCON_SET_TC2MCI2_RE_SET_Msk                   (0x01UL << MCPWM_CNTCON_SET_TC2MCI2_RE_SET_Pos)           /*!< MCPWM CNTCON_SET: TC2MCI2_RE_SET Mask */
#define MCPWM_CNTCON_SET_TC2MCI2_FE_SET_Pos                   17                                                        /*!< MCPWM CNTCON_SET: TC2MCI2_FE_SET Position */
#define MCPWM_CNTCON_SET_TC2MCI2_FE_SET_Msk                   (0x01UL << MCPWM_CNTCON_SET_TC2MCI2_FE_SET_Pos)           /*!< MCPWM CNTCON_SET: TC2MCI2_FE_SET Mask */
#define MCPWM_CNTCON_SET_CNTR0_SET_Pos                        29                                                        /*!< MCPWM CNTCON_SET: CNTR0_SET Position */
#define MCPWM_CNTCON_SET_CNTR0_SET_Msk                        (0x01UL << MCPWM_CNTCON_SET_CNTR0_SET_Pos)                /*!< MCPWM CNTCON_SET: CNTR0_SET Mask    */
#define MCPWM_CNTCON_SET_CNTR1_SET_Pos                        30                                                        /*!< MCPWM CNTCON_SET: CNTR1_SET Position */
#define MCPWM_CNTCON_SET_CNTR1_SET_Msk                        (0x01UL << MCPWM_CNTCON_SET_CNTR1_SET_Pos)                /*!< MCPWM CNTCON_SET: CNTR1_SET Mask    */
#define MCPWM_CNTCON_SET_CNTR2_SET_Pos                        31                                                        /*!< MCPWM CNTCON_SET: CNTR2_SET Position */
#define MCPWM_CNTCON_SET_CNTR2_SET_Msk                        (0x01UL << MCPWM_CNTCON_SET_CNTR2_SET_Pos)                /*!< MCPWM CNTCON_SET: CNTR2_SET Mask    */

// ------------------------------------  MCPWM_CNTCON_CLR  ----------------------------------------
#define MCPWM_CNTCON_CLR_TC0MCI0_RE_CLR_Pos                   0                                                         /*!< MCPWM CNTCON_CLR: TC0MCI0_RE_CLR Position */
#define MCPWM_CNTCON_CLR_TC0MCI0_RE_CLR_Msk                   (0x01UL << MCPWM_CNTCON_CLR_TC0MCI0_RE_CLR_Pos)           /*!< MCPWM CNTCON_CLR: TC0MCI0_RE_CLR Mask */
#define MCPWM_CNTCON_CLR_TC0MCI0_FE_CLR_Pos                   1                                                         /*!< MCPWM CNTCON_CLR: TC0MCI0_FE_CLR Position */
#define MCPWM_CNTCON_CLR_TC0MCI0_FE_CLR_Msk                   (0x01UL << MCPWM_CNTCON_CLR_TC0MCI0_FE_CLR_Pos)           /*!< MCPWM CNTCON_CLR: TC0MCI0_FE_CLR Mask */
#define MCPWM_CNTCON_CLR_TC0MCI1_RE_CLR_Pos                   2                                                         /*!< MCPWM CNTCON_CLR: TC0MCI1_RE_CLR Position */
#define MCPWM_CNTCON_CLR_TC0MCI1_RE_CLR_Msk                   (0x01UL << MCPWM_CNTCON_CLR_TC0MCI1_RE_CLR_Pos)           /*!< MCPWM CNTCON_CLR: TC0MCI1_RE_CLR Mask */
#define MCPWM_CNTCON_CLR_TC0MCI1_FE_CLR_Pos                   3                                                         /*!< MCPWM CNTCON_CLR: TC0MCI1_FE_CLR Position */
#define MCPWM_CNTCON_CLR_TC0MCI1_FE_CLR_Msk                   (0x01UL << MCPWM_CNTCON_CLR_TC0MCI1_FE_CLR_Pos)           /*!< MCPWM CNTCON_CLR: TC0MCI1_FE_CLR Mask */
#define MCPWM_CNTCON_CLR_TC0MCI2_RE_Pos                       4                                                         /*!< MCPWM CNTCON_CLR: TC0MCI2_RE Position */
#define MCPWM_CNTCON_CLR_TC0MCI2_RE_Msk                       (0x01UL << MCPWM_CNTCON_CLR_TC0MCI2_RE_Pos)               /*!< MCPWM CNTCON_CLR: TC0MCI2_RE Mask   */
#define MCPWM_CNTCON_CLR_TC0MCI2_FE_CLR_Pos                   5                                                         /*!< MCPWM CNTCON_CLR: TC0MCI2_FE_CLR Position */
#define MCPWM_CNTCON_CLR_TC0MCI2_FE_CLR_Msk                   (0x01UL << MCPWM_CNTCON_CLR_TC0MCI2_FE_CLR_Pos)           /*!< MCPWM CNTCON_CLR: TC0MCI2_FE_CLR Mask */
#define MCPWM_CNTCON_CLR_TC1MCI0_RE_CLR_Pos                   6                                                         /*!< MCPWM CNTCON_CLR: TC1MCI0_RE_CLR Position */
#define MCPWM_CNTCON_CLR_TC1MCI0_RE_CLR_Msk                   (0x01UL << MCPWM_CNTCON_CLR_TC1MCI0_RE_CLR_Pos)           /*!< MCPWM CNTCON_CLR: TC1MCI0_RE_CLR Mask */
#define MCPWM_CNTCON_CLR_TC1MCI0_FE_CLR_Pos                   7                                                         /*!< MCPWM CNTCON_CLR: TC1MCI0_FE_CLR Position */
#define MCPWM_CNTCON_CLR_TC1MCI0_FE_CLR_Msk                   (0x01UL << MCPWM_CNTCON_CLR_TC1MCI0_FE_CLR_Pos)           /*!< MCPWM CNTCON_CLR: TC1MCI0_FE_CLR Mask */
#define MCPWM_CNTCON_CLR_TC1MCI1_RE_CLR_Pos                   8                                                         /*!< MCPWM CNTCON_CLR: TC1MCI1_RE_CLR Position */
#define MCPWM_CNTCON_CLR_TC1MCI1_RE_CLR_Msk                   (0x01UL << MCPWM_CNTCON_CLR_TC1MCI1_RE_CLR_Pos)           /*!< MCPWM CNTCON_CLR: TC1MCI1_RE_CLR Mask */
#define MCPWM_CNTCON_CLR_TC1MCI1_FE_CLR_Pos                   9                                                         /*!< MCPWM CNTCON_CLR: TC1MCI1_FE_CLR Position */
#define MCPWM_CNTCON_CLR_TC1MCI1_FE_CLR_Msk                   (0x01UL << MCPWM_CNTCON_CLR_TC1MCI1_FE_CLR_Pos)           /*!< MCPWM CNTCON_CLR: TC1MCI1_FE_CLR Mask */
#define MCPWM_CNTCON_CLR_TC1MCI2_RE_CLR_Pos                   10                                                        /*!< MCPWM CNTCON_CLR: TC1MCI2_RE_CLR Position */
#define MCPWM_CNTCON_CLR_TC1MCI2_RE_CLR_Msk                   (0x01UL << MCPWM_CNTCON_CLR_TC1MCI2_RE_CLR_Pos)           /*!< MCPWM CNTCON_CLR: TC1MCI2_RE_CLR Mask */
#define MCPWM_CNTCON_CLR_TC1MCI2_FE_CLR_Pos                   11                                                        /*!< MCPWM CNTCON_CLR: TC1MCI2_FE_CLR Position */
#define MCPWM_CNTCON_CLR_TC1MCI2_FE_CLR_Msk                   (0x01UL << MCPWM_CNTCON_CLR_TC1MCI2_FE_CLR_Pos)           /*!< MCPWM CNTCON_CLR: TC1MCI2_FE_CLR Mask */
#define MCPWM_CNTCON_CLR_TC2MCI0_RE_CLR_Pos                   12                                                        /*!< MCPWM CNTCON_CLR: TC2MCI0_RE_CLR Position */
#define MCPWM_CNTCON_CLR_TC2MCI0_RE_CLR_Msk                   (0x01UL << MCPWM_CNTCON_CLR_TC2MCI0_RE_CLR_Pos)           /*!< MCPWM CNTCON_CLR: TC2MCI0_RE_CLR Mask */
#define MCPWM_CNTCON_CLR_TC2MCI0_FE_CLR_Pos                   13                                                        /*!< MCPWM CNTCON_CLR: TC2MCI0_FE_CLR Position */
#define MCPWM_CNTCON_CLR_TC2MCI0_FE_CLR_Msk                   (0x01UL << MCPWM_CNTCON_CLR_TC2MCI0_FE_CLR_Pos)           /*!< MCPWM CNTCON_CLR: TC2MCI0_FE_CLR Mask */
#define MCPWM_CNTCON_CLR_TC2MCI1_RE_CLR_Pos                   14                                                        /*!< MCPWM CNTCON_CLR: TC2MCI1_RE_CLR Position */
#define MCPWM_CNTCON_CLR_TC2MCI1_RE_CLR_Msk                   (0x01UL << MCPWM_CNTCON_CLR_TC2MCI1_RE_CLR_Pos)           /*!< MCPWM CNTCON_CLR: TC2MCI1_RE_CLR Mask */
#define MCPWM_CNTCON_CLR_TC2MCI1_FE_CLR_Pos                   15                                                        /*!< MCPWM CNTCON_CLR: TC2MCI1_FE_CLR Position */
#define MCPWM_CNTCON_CLR_TC2MCI1_FE_CLR_Msk                   (0x01UL << MCPWM_CNTCON_CLR_TC2MCI1_FE_CLR_Pos)           /*!< MCPWM CNTCON_CLR: TC2MCI1_FE_CLR Mask */
#define MCPWM_CNTCON_CLR_TC2MCI2_RE_CLR_Pos                   16                                                        /*!< MCPWM CNTCON_CLR: TC2MCI2_RE_CLR Position */
#define MCPWM_CNTCON_CLR_TC2MCI2_RE_CLR_Msk                   (0x01UL << MCPWM_CNTCON_CLR_TC2MCI2_RE_CLR_Pos)           /*!< MCPWM CNTCON_CLR: TC2MCI2_RE_CLR Mask */
#define MCPWM_CNTCON_CLR_TC2MCI2_FE_CLR_Pos                   17                                                        /*!< MCPWM CNTCON_CLR: TC2MCI2_FE_CLR Position */
#define MCPWM_CNTCON_CLR_TC2MCI2_FE_CLR_Msk                   (0x01UL << MCPWM_CNTCON_CLR_TC2MCI2_FE_CLR_Pos)           /*!< MCPWM CNTCON_CLR: TC2MCI2_FE_CLR Mask */
#define MCPWM_CNTCON_CLR_CNTR0_CLR_Pos                        29                                                        /*!< MCPWM CNTCON_CLR: CNTR0_CLR Position */
#define MCPWM_CNTCON_CLR_CNTR0_CLR_Msk                        (0x01UL << MCPWM_CNTCON_CLR_CNTR0_CLR_Pos)                /*!< MCPWM CNTCON_CLR: CNTR0_CLR Mask    */
#define MCPWM_CNTCON_CLR_CNTR1_CLR_Pos                        30                                                        /*!< MCPWM CNTCON_CLR: CNTR1_CLR Position */
#define MCPWM_CNTCON_CLR_CNTR1_CLR_Msk                        (0x01UL << MCPWM_CNTCON_CLR_CNTR1_CLR_Pos)                /*!< MCPWM CNTCON_CLR: CNTR1_CLR Mask    */
#define MCPWM_CNTCON_CLR_CNTR2_CLR_Pos                        31                                                        /*!< MCPWM CNTCON_CLR: CNTR2_CLR Position */
#define MCPWM_CNTCON_CLR_CNTR2_CLR_Msk                        (0x01UL << MCPWM_CNTCON_CLR_CNTR2_CLR_Pos)                /*!< MCPWM CNTCON_CLR: CNTR2_CLR Mask    */

// ---------------------------------------  MCPWM_INTF  -------------------------------------------
#define MCPWM_INTF_ILIM0_F_Pos                                0                                                         /*!< MCPWM INTF: ILIM0_F Position        */
#define MCPWM_INTF_ILIM0_F_Msk                                (0x01UL << MCPWM_INTF_ILIM0_F_Pos)                        /*!< MCPWM INTF: ILIM0_F Mask            */
#define MCPWM_INTF_IMAT0_F_Pos                                1                                                         /*!< MCPWM INTF: IMAT0_F Position        */
#define MCPWM_INTF_IMAT0_F_Msk                                (0x01UL << MCPWM_INTF_IMAT0_F_Pos)                        /*!< MCPWM INTF: IMAT0_F Mask            */
#define MCPWM_INTF_ICAP0_F_Pos                                2                                                         /*!< MCPWM INTF: ICAP0_F Position        */
#define MCPWM_INTF_ICAP0_F_Msk                                (0x01UL << MCPWM_INTF_ICAP0_F_Pos)                        /*!< MCPWM INTF: ICAP0_F Mask            */
#define MCPWM_INTF_ILIM1_F_Pos                                4                                                         /*!< MCPWM INTF: ILIM1_F Position        */
#define MCPWM_INTF_ILIM1_F_Msk                                (0x01UL << MCPWM_INTF_ILIM1_F_Pos)                        /*!< MCPWM INTF: ILIM1_F Mask            */
#define MCPWM_INTF_IMAT1_F_Pos                                5                                                         /*!< MCPWM INTF: IMAT1_F Position        */
#define MCPWM_INTF_IMAT1_F_Msk                                (0x01UL << MCPWM_INTF_IMAT1_F_Pos)                        /*!< MCPWM INTF: IMAT1_F Mask            */
#define MCPWM_INTF_ICAP1_F_Pos                                6                                                         /*!< MCPWM INTF: ICAP1_F Position        */
#define MCPWM_INTF_ICAP1_F_Msk                                (0x01UL << MCPWM_INTF_ICAP1_F_Pos)                        /*!< MCPWM INTF: ICAP1_F Mask            */
#define MCPWM_INTF_ILIM2_F_Pos                                8                                                         /*!< MCPWM INTF: ILIM2_F Position        */
#define MCPWM_INTF_ILIM2_F_Msk                                (0x01UL << MCPWM_INTF_ILIM2_F_Pos)                        /*!< MCPWM INTF: ILIM2_F Mask            */
#define MCPWM_INTF_IMAT2_F_Pos                                9                                                         /*!< MCPWM INTF: IMAT2_F Position        */
#define MCPWM_INTF_IMAT2_F_Msk                                (0x01UL << MCPWM_INTF_IMAT2_F_Pos)                        /*!< MCPWM INTF: IMAT2_F Mask            */
#define MCPWM_INTF_ICAP2_F_Pos                                10                                                        /*!< MCPWM INTF: ICAP2_F Position        */
#define MCPWM_INTF_ICAP2_F_Msk                                (0x01UL << MCPWM_INTF_ICAP2_F_Pos)                        /*!< MCPWM INTF: ICAP2_F Mask            */
#define MCPWM_INTF_ABORT_F_Pos                                15                                                        /*!< MCPWM INTF: ABORT_F Position        */
#define MCPWM_INTF_ABORT_F_Msk                                (0x01UL << MCPWM_INTF_ABORT_F_Pos)                        /*!< MCPWM INTF: ABORT_F Mask            */

// -------------------------------------  MCPWM_INTF_SET  -----------------------------------------
#define MCPWM_INTF_SET_ILIM0_F_SET_Pos                        0                                                         /*!< MCPWM INTF_SET: ILIM0_F_SET Position */
#define MCPWM_INTF_SET_ILIM0_F_SET_Msk                        (0x01UL << MCPWM_INTF_SET_ILIM0_F_SET_Pos)                /*!< MCPWM INTF_SET: ILIM0_F_SET Mask    */
#define MCPWM_INTF_SET_IMAT0_F_SET_Pos                        1                                                         /*!< MCPWM INTF_SET: IMAT0_F_SET Position */
#define MCPWM_INTF_SET_IMAT0_F_SET_Msk                        (0x01UL << MCPWM_INTF_SET_IMAT0_F_SET_Pos)                /*!< MCPWM INTF_SET: IMAT0_F_SET Mask    */
#define MCPWM_INTF_SET_ICAP0_F_SET_Pos                        2                                                         /*!< MCPWM INTF_SET: ICAP0_F_SET Position */
#define MCPWM_INTF_SET_ICAP0_F_SET_Msk                        (0x01UL << MCPWM_INTF_SET_ICAP0_F_SET_Pos)                /*!< MCPWM INTF_SET: ICAP0_F_SET Mask    */
#define MCPWM_INTF_SET_ILIM1_F_SET_Pos                        4                                                         /*!< MCPWM INTF_SET: ILIM1_F_SET Position */
#define MCPWM_INTF_SET_ILIM1_F_SET_Msk                        (0x01UL << MCPWM_INTF_SET_ILIM1_F_SET_Pos)                /*!< MCPWM INTF_SET: ILIM1_F_SET Mask    */
#define MCPWM_INTF_SET_IMAT1_F_SET_Pos                        5                                                         /*!< MCPWM INTF_SET: IMAT1_F_SET Position */
#define MCPWM_INTF_SET_IMAT1_F_SET_Msk                        (0x01UL << MCPWM_INTF_SET_IMAT1_F_SET_Pos)                /*!< MCPWM INTF_SET: IMAT1_F_SET Mask    */
#define MCPWM_INTF_SET_ICAP1_F_SET_Pos                        6                                                         /*!< MCPWM INTF_SET: ICAP1_F_SET Position */
#define MCPWM_INTF_SET_ICAP1_F_SET_Msk                        (0x01UL << MCPWM_INTF_SET_ICAP1_F_SET_Pos)                /*!< MCPWM INTF_SET: ICAP1_F_SET Mask    */
#define MCPWM_INTF_SET_ILIM2_F_SET_Pos                        8                                                         /*!< MCPWM INTF_SET: ILIM2_F_SET Position */
#define MCPWM_INTF_SET_ILIM2_F_SET_Msk                        (0x01UL << MCPWM_INTF_SET_ILIM2_F_SET_Pos)                /*!< MCPWM INTF_SET: ILIM2_F_SET Mask    */
#define MCPWM_INTF_SET_IMAT2_F_SET_Pos                        9                                                         /*!< MCPWM INTF_SET: IMAT2_F_SET Position */
#define MCPWM_INTF_SET_IMAT2_F_SET_Msk                        (0x01UL << MCPWM_INTF_SET_IMAT2_F_SET_Pos)                /*!< MCPWM INTF_SET: IMAT2_F_SET Mask    */
#define MCPWM_INTF_SET_ICAP2_F_SET_Pos                        10                                                        /*!< MCPWM INTF_SET: ICAP2_F_SET Position */
#define MCPWM_INTF_SET_ICAP2_F_SET_Msk                        (0x01UL << MCPWM_INTF_SET_ICAP2_F_SET_Pos)                /*!< MCPWM INTF_SET: ICAP2_F_SET Mask    */
#define MCPWM_INTF_SET_ABORT_F_SET_Pos                        15                                                        /*!< MCPWM INTF_SET: ABORT_F_SET Position */
#define MCPWM_INTF_SET_ABORT_F_SET_Msk                        (0x01UL << MCPWM_INTF_SET_ABORT_F_SET_Pos)                /*!< MCPWM INTF_SET: ABORT_F_SET Mask    */

// -------------------------------------  MCPWM_INTF_CLR  -----------------------------------------
#define MCPWM_INTF_CLR_ILIM0_F_CLR_Pos                        0                                                         /*!< MCPWM INTF_CLR: ILIM0_F_CLR Position */
#define MCPWM_INTF_CLR_ILIM0_F_CLR_Msk                        (0x01UL << MCPWM_INTF_CLR_ILIM0_F_CLR_Pos)                /*!< MCPWM INTF_CLR: ILIM0_F_CLR Mask    */
#define MCPWM_INTF_CLR_IMAT0_F_CLR_Pos                        1                                                         /*!< MCPWM INTF_CLR: IMAT0_F_CLR Position */
#define MCPWM_INTF_CLR_IMAT0_F_CLR_Msk                        (0x01UL << MCPWM_INTF_CLR_IMAT0_F_CLR_Pos)                /*!< MCPWM INTF_CLR: IMAT0_F_CLR Mask    */
#define MCPWM_INTF_CLR_ICAP0_F_CLR_Pos                        2                                                         /*!< MCPWM INTF_CLR: ICAP0_F_CLR Position */
#define MCPWM_INTF_CLR_ICAP0_F_CLR_Msk                        (0x01UL << MCPWM_INTF_CLR_ICAP0_F_CLR_Pos)                /*!< MCPWM INTF_CLR: ICAP0_F_CLR Mask    */
#define MCPWM_INTF_CLR_ILIM1_F_CLR_Pos                        4                                                         /*!< MCPWM INTF_CLR: ILIM1_F_CLR Position */
#define MCPWM_INTF_CLR_ILIM1_F_CLR_Msk                        (0x01UL << MCPWM_INTF_CLR_ILIM1_F_CLR_Pos)                /*!< MCPWM INTF_CLR: ILIM1_F_CLR Mask    */
#define MCPWM_INTF_CLR_IMAT1_F_CLR_Pos                        5                                                         /*!< MCPWM INTF_CLR: IMAT1_F_CLR Position */
#define MCPWM_INTF_CLR_IMAT1_F_CLR_Msk                        (0x01UL << MCPWM_INTF_CLR_IMAT1_F_CLR_Pos)                /*!< MCPWM INTF_CLR: IMAT1_F_CLR Mask    */
#define MCPWM_INTF_CLR_ICAP1_F_CLR_Pos                        6                                                         /*!< MCPWM INTF_CLR: ICAP1_F_CLR Position */
#define MCPWM_INTF_CLR_ICAP1_F_CLR_Msk                        (0x01UL << MCPWM_INTF_CLR_ICAP1_F_CLR_Pos)                /*!< MCPWM INTF_CLR: ICAP1_F_CLR Mask    */
#define MCPWM_INTF_CLR_ILIM2_F_CLR_Pos                        8                                                         /*!< MCPWM INTF_CLR: ILIM2_F_CLR Position */
#define MCPWM_INTF_CLR_ILIM2_F_CLR_Msk                        (0x01UL << MCPWM_INTF_CLR_ILIM2_F_CLR_Pos)                /*!< MCPWM INTF_CLR: ILIM2_F_CLR Mask    */
#define MCPWM_INTF_CLR_IMAT2_F_CLR_Pos                        9                                                         /*!< MCPWM INTF_CLR: IMAT2_F_CLR Position */
#define MCPWM_INTF_CLR_IMAT2_F_CLR_Msk                        (0x01UL << MCPWM_INTF_CLR_IMAT2_F_CLR_Pos)                /*!< MCPWM INTF_CLR: IMAT2_F_CLR Mask    */
#define MCPWM_INTF_CLR_ICAP2_F_CLR_Pos                        10                                                        /*!< MCPWM INTF_CLR: ICAP2_F_CLR Position */
#define MCPWM_INTF_CLR_ICAP2_F_CLR_Msk                        (0x01UL << MCPWM_INTF_CLR_ICAP2_F_CLR_Pos)                /*!< MCPWM INTF_CLR: ICAP2_F_CLR Mask    */
#define MCPWM_INTF_CLR_ABORT_F_CLR_Pos                        15                                                        /*!< MCPWM INTF_CLR: ABORT_F_CLR Position */
#define MCPWM_INTF_CLR_ABORT_F_CLR_Msk                        (0x01UL << MCPWM_INTF_CLR_ABORT_F_CLR_Pos)                /*!< MCPWM INTF_CLR: ABORT_F_CLR Mask    */

// --------------------------------------  MCPWM_CAP_CLR  -----------------------------------------
#define MCPWM_CAP_CLR_CAP_CLR0_Pos                            0                                                         /*!< MCPWM CAP_CLR: CAP_CLR0 Position    */
#define MCPWM_CAP_CLR_CAP_CLR0_Msk                            (0x01UL << MCPWM_CAP_CLR_CAP_CLR0_Pos)                    /*!< MCPWM CAP_CLR: CAP_CLR0 Mask        */
#define MCPWM_CAP_CLR_CAP_CLR1_Pos                            1                                                         /*!< MCPWM CAP_CLR: CAP_CLR1 Position    */
#define MCPWM_CAP_CLR_CAP_CLR1_Msk                            (0x01UL << MCPWM_CAP_CLR_CAP_CLR1_Pos)                    /*!< MCPWM CAP_CLR: CAP_CLR1 Mask        */
#define MCPWM_CAP_CLR_CAP_CLR2_Pos                            2                                                         /*!< MCPWM CAP_CLR: CAP_CLR2 Position    */
#define MCPWM_CAP_CLR_CAP_CLR2_Msk                            (0x01UL << MCPWM_CAP_CLR_CAP_CLR2_Pos)                    /*!< MCPWM CAP_CLR: CAP_CLR2 Mask        */


// ------------------------------------------------------------------------------------------------
// -----                                 I2C0 Position & Mask                                 -----
// ------------------------------------------------------------------------------------------------


// ---------------------------------------  I2C0_CONSET  ------------------------------------------
#define I2C0_CONSET_AA_Pos                                    2                                                         /*!< I2C0 CONSET: AA Position            */
#define I2C0_CONSET_AA_Msk                                    (0x01UL << I2C0_CONSET_AA_Pos)                            /*!< I2C0 CONSET: AA Mask                */
#define I2C0_CONSET_SI_Pos                                    3                                                         /*!< I2C0 CONSET: SI Position            */
#define I2C0_CONSET_SI_Msk                                    (0x01UL << I2C0_CONSET_SI_Pos)                            /*!< I2C0 CONSET: SI Mask                */
#define I2C0_CONSET_STO_Pos                                   4                                                         /*!< I2C0 CONSET: STO Position           */
#define I2C0_CONSET_STO_Msk                                   (0x01UL << I2C0_CONSET_STO_Pos)                           /*!< I2C0 CONSET: STO Mask               */
#define I2C0_CONSET_STA_Pos                                   5                                                         /*!< I2C0 CONSET: STA Position           */
#define I2C0_CONSET_STA_Msk                                   (0x01UL << I2C0_CONSET_STA_Pos)                           /*!< I2C0 CONSET: STA Mask               */
#define I2C0_CONSET_I2EN_Pos                                  6                                                         /*!< I2C0 CONSET: I2EN Position          */
#define I2C0_CONSET_I2EN_Msk                                  (0x01UL << I2C0_CONSET_I2EN_Pos)                          /*!< I2C0 CONSET: I2EN Mask              */

// ----------------------------------------  I2C0_STAT  -------------------------------------------
#define I2C0_STAT_Status_Pos                                  3                                                         /*!< I2C0 STAT: Status Position          */
#define I2C0_STAT_Status_Msk                                  (0x1fUL << I2C0_STAT_Status_Pos)                          /*!< I2C0 STAT: Status Mask              */

// ----------------------------------------  I2C0_DAT  --------------------------------------------
#define I2C0_DAT_Data_Pos                                     0                                                         /*!< I2C0 DAT: Data Position             */
#define I2C0_DAT_Data_Msk                                     (0x000000ffUL << I2C0_DAT_Data_Pos)                       /*!< I2C0 DAT: Data Mask                 */

// ----------------------------------------  I2C0_ADR0  -------------------------------------------
#define I2C0_ADR0_GC_Pos                                      0                                                         /*!< I2C0 ADR0: GC Position              */
#define I2C0_ADR0_GC_Msk                                      (0x01UL << I2C0_ADR0_GC_Pos)                              /*!< I2C0 ADR0: GC Mask                  */
#define I2C0_ADR0_Address_Pos                                 1                                                         /*!< I2C0 ADR0: Address Position         */
#define I2C0_ADR0_Address_Msk                                 (0x7fUL << I2C0_ADR0_Address_Pos)                         /*!< I2C0 ADR0: Address Mask             */

// ----------------------------------------  I2C0_SCLH  -------------------------------------------
#define I2C0_SCLH_SCLH_Pos                                    0                                                         /*!< I2C0 SCLH: SCLH Position            */
#define I2C0_SCLH_SCLH_Msk                                    (0x0000ffffUL << I2C0_SCLH_SCLH_Pos)                      /*!< I2C0 SCLH: SCLH Mask                */

// ----------------------------------------  I2C0_SCLL  -------------------------------------------
#define I2C0_SCLL_SCLL_Pos                                    0                                                         /*!< I2C0 SCLL: SCLL Position            */
#define I2C0_SCLL_SCLL_Msk                                    (0x0000ffffUL << I2C0_SCLL_SCLL_Pos)                      /*!< I2C0 SCLL: SCLL Mask                */

// ---------------------------------------  I2C0_CONCLR  ------------------------------------------
#define I2C0_CONCLR_AAC_Pos                                   2                                                         /*!< I2C0 CONCLR: AAC Position           */
#define I2C0_CONCLR_AAC_Msk                                   (0x01UL << I2C0_CONCLR_AAC_Pos)                           /*!< I2C0 CONCLR: AAC Mask               */
#define I2C0_CONCLR_SIC_Pos                                   3                                                         /*!< I2C0 CONCLR: SIC Position           */
#define I2C0_CONCLR_SIC_Msk                                   (0x01UL << I2C0_CONCLR_SIC_Pos)                           /*!< I2C0 CONCLR: SIC Mask               */
#define I2C0_CONCLR_STAC_Pos                                  5                                                         /*!< I2C0 CONCLR: STAC Position          */
#define I2C0_CONCLR_STAC_Msk                                  (0x01UL << I2C0_CONCLR_STAC_Pos)                          /*!< I2C0 CONCLR: STAC Mask              */
#define I2C0_CONCLR_I2ENC_Pos                                 6                                                         /*!< I2C0 CONCLR: I2ENC Position         */
#define I2C0_CONCLR_I2ENC_Msk                                 (0x01UL << I2C0_CONCLR_I2ENC_Pos)                         /*!< I2C0 CONCLR: I2ENC Mask             */

// ---------------------------------------  I2C0_MMCTRL  ------------------------------------------
#define I2C0_MMCTRL_MM_ENA_Pos                                0                                                         /*!< I2C0 MMCTRL: MM_ENA Position        */
#define I2C0_MMCTRL_MM_ENA_Msk                                (0x01UL << I2C0_MMCTRL_MM_ENA_Pos)                        /*!< I2C0 MMCTRL: MM_ENA Mask            */
#define I2C0_MMCTRL_ENA_SCL_Pos                               1                                                         /*!< I2C0 MMCTRL: ENA_SCL Position       */
#define I2C0_MMCTRL_ENA_SCL_Msk                               (0x01UL << I2C0_MMCTRL_ENA_SCL_Pos)                       /*!< I2C0 MMCTRL: ENA_SCL Mask           */
#define I2C0_MMCTRL_MATCH_ALL_Pos                             2                                                         /*!< I2C0 MMCTRL: MATCH_ALL Position     */
#define I2C0_MMCTRL_MATCH_ALL_Msk                             (0x01UL << I2C0_MMCTRL_MATCH_ALL_Pos)                     /*!< I2C0 MMCTRL: MATCH_ALL Mask         */

// ----------------------------------------  I2C0_ADR1  -------------------------------------------
#define I2C0_ADR1_GC_Pos                                      0                                                         /*!< I2C0 ADR1: GC Position              */
#define I2C0_ADR1_GC_Msk                                      (0x01UL << I2C0_ADR1_GC_Pos)                              /*!< I2C0 ADR1: GC Mask                  */
#define I2C0_ADR1_Address_Pos                                 1                                                         /*!< I2C0 ADR1: Address Position         */
#define I2C0_ADR1_Address_Msk                                 (0x7fUL << I2C0_ADR1_Address_Pos)                         /*!< I2C0 ADR1: Address Mask             */

// ----------------------------------------  I2C0_ADR2  -------------------------------------------
#define I2C0_ADR2_GC_Pos                                      0                                                         /*!< I2C0 ADR2: GC Position              */
#define I2C0_ADR2_GC_Msk                                      (0x01UL << I2C0_ADR2_GC_Pos)                              /*!< I2C0 ADR2: GC Mask                  */
#define I2C0_ADR2_Address_Pos                                 1                                                         /*!< I2C0 ADR2: Address Position         */
#define I2C0_ADR2_Address_Msk                                 (0x7fUL << I2C0_ADR2_Address_Pos)                         /*!< I2C0 ADR2: Address Mask             */

// ----------------------------------------  I2C0_ADR3  -------------------------------------------
#define I2C0_ADR3_GC_Pos                                      0                                                         /*!< I2C0 ADR3: GC Position              */
#define I2C0_ADR3_GC_Msk                                      (0x01UL << I2C0_ADR3_GC_Pos)                              /*!< I2C0 ADR3: GC Mask                  */
#define I2C0_ADR3_Address_Pos                                 1                                                         /*!< I2C0 ADR3: Address Position         */
#define I2C0_ADR3_Address_Msk                                 (0x7fUL << I2C0_ADR3_Address_Pos)                         /*!< I2C0 ADR3: Address Mask             */

// ------------------------------------  I2C0_DATA_BUFFER  ----------------------------------------
#define I2C0_DATA_BUFFER_Data_Pos                             0                                                         /*!< I2C0 DATA_BUFFER: Data Position     */
#define I2C0_DATA_BUFFER_Data_Msk                             (0x000000ffUL << I2C0_DATA_BUFFER_Data_Pos)               /*!< I2C0 DATA_BUFFER: Data Mask         */

// ---------------------------------------  I2C0_MASK0  -------------------------------------------
#define I2C0_MASK0_MASK_Pos                                   1                                                         /*!< I2C0 MASK0: MASK Position           */
#define I2C0_MASK0_MASK_Msk                                   (0x7fUL << I2C0_MASK0_MASK_Pos)                           /*!< I2C0 MASK0: MASK Mask               */

// ---------------------------------------  I2C0_MASK1  -------------------------------------------
#define I2C0_MASK1_MASK_Pos                                   1                                                         /*!< I2C0 MASK1: MASK Position           */
#define I2C0_MASK1_MASK_Msk                                   (0x7fUL << I2C0_MASK1_MASK_Pos)                           /*!< I2C0 MASK1: MASK Mask               */

// ---------------------------------------  I2C0_MASK2  -------------------------------------------
#define I2C0_MASK2_MASK_Pos                                   1                                                         /*!< I2C0 MASK2: MASK Position           */
#define I2C0_MASK2_MASK_Msk                                   (0x7fUL << I2C0_MASK2_MASK_Pos)                           /*!< I2C0 MASK2: MASK Mask               */

// ---------------------------------------  I2C0_MASK3  -------------------------------------------
#define I2C0_MASK3_MASK_Pos                                   1                                                         /*!< I2C0 MASK3: MASK Position           */
#define I2C0_MASK3_MASK_Msk                                   (0x7fUL << I2C0_MASK3_MASK_Pos)                           /*!< I2C0 MASK3: MASK Mask               */


// ------------------------------------------------------------------------------------------------
// -----                                 I2C1 Position & Mask                                 -----
// ------------------------------------------------------------------------------------------------


// ---------------------------------------  I2C1_CONSET  ------------------------------------------
#define I2C1_CONSET_AA_Pos                                    2                                                         /*!< I2C1 CONSET: AA Position            */
#define I2C1_CONSET_AA_Msk                                    (0x01UL << I2C1_CONSET_AA_Pos)                            /*!< I2C1 CONSET: AA Mask                */
#define I2C1_CONSET_SI_Pos                                    3                                                         /*!< I2C1 CONSET: SI Position            */
#define I2C1_CONSET_SI_Msk                                    (0x01UL << I2C1_CONSET_SI_Pos)                            /*!< I2C1 CONSET: SI Mask                */
#define I2C1_CONSET_STO_Pos                                   4                                                         /*!< I2C1 CONSET: STO Position           */
#define I2C1_CONSET_STO_Msk                                   (0x01UL << I2C1_CONSET_STO_Pos)                           /*!< I2C1 CONSET: STO Mask               */
#define I2C1_CONSET_STA_Pos                                   5                                                         /*!< I2C1 CONSET: STA Position           */
#define I2C1_CONSET_STA_Msk                                   (0x01UL << I2C1_CONSET_STA_Pos)                           /*!< I2C1 CONSET: STA Mask               */
#define I2C1_CONSET_I2EN_Pos                                  6                                                         /*!< I2C1 CONSET: I2EN Position          */
#define I2C1_CONSET_I2EN_Msk                                  (0x01UL << I2C1_CONSET_I2EN_Pos)                          /*!< I2C1 CONSET: I2EN Mask              */

// ----------------------------------------  I2C1_STAT  -------------------------------------------
#define I2C1_STAT_Status_Pos                                  3                                                         /*!< I2C1 STAT: Status Position          */
#define I2C1_STAT_Status_Msk                                  (0x1fUL << I2C1_STAT_Status_Pos)                          /*!< I2C1 STAT: Status Mask              */

// ----------------------------------------  I2C1_DAT  --------------------------------------------
#define I2C1_DAT_Data_Pos                                     0                                                         /*!< I2C1 DAT: Data Position             */
#define I2C1_DAT_Data_Msk                                     (0x000000ffUL << I2C1_DAT_Data_Pos)                       /*!< I2C1 DAT: Data Mask                 */

// ----------------------------------------  I2C1_ADR0  -------------------------------------------
#define I2C1_ADR0_GC_Pos                                      0                                                         /*!< I2C1 ADR0: GC Position              */
#define I2C1_ADR0_GC_Msk                                      (0x01UL << I2C1_ADR0_GC_Pos)                              /*!< I2C1 ADR0: GC Mask                  */
#define I2C1_ADR0_Address_Pos                                 1                                                         /*!< I2C1 ADR0: Address Position         */
#define I2C1_ADR0_Address_Msk                                 (0x7fUL << I2C1_ADR0_Address_Pos)                         /*!< I2C1 ADR0: Address Mask             */

// ----------------------------------------  I2C1_SCLH  -------------------------------------------
#define I2C1_SCLH_SCLH_Pos                                    0                                                         /*!< I2C1 SCLH: SCLH Position            */
#define I2C1_SCLH_SCLH_Msk                                    (0x0000ffffUL << I2C1_SCLH_SCLH_Pos)                      /*!< I2C1 SCLH: SCLH Mask                */

// ----------------------------------------  I2C1_SCLL  -------------------------------------------
#define I2C1_SCLL_SCLL_Pos                                    0                                                         /*!< I2C1 SCLL: SCLL Position            */
#define I2C1_SCLL_SCLL_Msk                                    (0x0000ffffUL << I2C1_SCLL_SCLL_Pos)                      /*!< I2C1 SCLL: SCLL Mask                */

// ---------------------------------------  I2C1_CONCLR  ------------------------------------------
#define I2C1_CONCLR_AAC_Pos                                   2                                                         /*!< I2C1 CONCLR: AAC Position           */
#define I2C1_CONCLR_AAC_Msk                                   (0x01UL << I2C1_CONCLR_AAC_Pos)                           /*!< I2C1 CONCLR: AAC Mask               */
#define I2C1_CONCLR_SIC_Pos                                   3                                                         /*!< I2C1 CONCLR: SIC Position           */
#define I2C1_CONCLR_SIC_Msk                                   (0x01UL << I2C1_CONCLR_SIC_Pos)                           /*!< I2C1 CONCLR: SIC Mask               */
#define I2C1_CONCLR_STAC_Pos                                  5                                                         /*!< I2C1 CONCLR: STAC Position          */
#define I2C1_CONCLR_STAC_Msk                                  (0x01UL << I2C1_CONCLR_STAC_Pos)                          /*!< I2C1 CONCLR: STAC Mask              */
#define I2C1_CONCLR_I2ENC_Pos                                 6                                                         /*!< I2C1 CONCLR: I2ENC Position         */
#define I2C1_CONCLR_I2ENC_Msk                                 (0x01UL << I2C1_CONCLR_I2ENC_Pos)                         /*!< I2C1 CONCLR: I2ENC Mask             */

// ---------------------------------------  I2C1_MMCTRL  ------------------------------------------
#define I2C1_MMCTRL_MM_ENA_Pos                                0                                                         /*!< I2C1 MMCTRL: MM_ENA Position        */
#define I2C1_MMCTRL_MM_ENA_Msk                                (0x01UL << I2C1_MMCTRL_MM_ENA_Pos)                        /*!< I2C1 MMCTRL: MM_ENA Mask            */
#define I2C1_MMCTRL_ENA_SCL_Pos                               1                                                         /*!< I2C1 MMCTRL: ENA_SCL Position       */
#define I2C1_MMCTRL_ENA_SCL_Msk                               (0x01UL << I2C1_MMCTRL_ENA_SCL_Pos)                       /*!< I2C1 MMCTRL: ENA_SCL Mask           */
#define I2C1_MMCTRL_MATCH_ALL_Pos                             2                                                         /*!< I2C1 MMCTRL: MATCH_ALL Position     */
#define I2C1_MMCTRL_MATCH_ALL_Msk                             (0x01UL << I2C1_MMCTRL_MATCH_ALL_Pos)                     /*!< I2C1 MMCTRL: MATCH_ALL Mask         */

// ----------------------------------------  I2C1_ADR1  -------------------------------------------
#define I2C1_ADR1_GC_Pos                                      0                                                         /*!< I2C1 ADR1: GC Position              */
#define I2C1_ADR1_GC_Msk                                      (0x01UL << I2C1_ADR1_GC_Pos)                              /*!< I2C1 ADR1: GC Mask                  */
#define I2C1_ADR1_Address_Pos                                 1                                                         /*!< I2C1 ADR1: Address Position         */
#define I2C1_ADR1_Address_Msk                                 (0x7fUL << I2C1_ADR1_Address_Pos)                         /*!< I2C1 ADR1: Address Mask             */

// ----------------------------------------  I2C1_ADR2  -------------------------------------------
#define I2C1_ADR2_GC_Pos                                      0                                                         /*!< I2C1 ADR2: GC Position              */
#define I2C1_ADR2_GC_Msk                                      (0x01UL << I2C1_ADR2_GC_Pos)                              /*!< I2C1 ADR2: GC Mask                  */
#define I2C1_ADR2_Address_Pos                                 1                                                         /*!< I2C1 ADR2: Address Position         */
#define I2C1_ADR2_Address_Msk                                 (0x7fUL << I2C1_ADR2_Address_Pos)                         /*!< I2C1 ADR2: Address Mask             */

// ----------------------------------------  I2C1_ADR3  -------------------------------------------
#define I2C1_ADR3_GC_Pos                                      0                                                         /*!< I2C1 ADR3: GC Position              */
#define I2C1_ADR3_GC_Msk                                      (0x01UL << I2C1_ADR3_GC_Pos)                              /*!< I2C1 ADR3: GC Mask                  */
#define I2C1_ADR3_Address_Pos                                 1                                                         /*!< I2C1 ADR3: Address Position         */
#define I2C1_ADR3_Address_Msk                                 (0x7fUL << I2C1_ADR3_Address_Pos)                         /*!< I2C1 ADR3: Address Mask             */

// ------------------------------------  I2C1_DATA_BUFFER  ----------------------------------------
#define I2C1_DATA_BUFFER_Data_Pos                             0                                                         /*!< I2C1 DATA_BUFFER: Data Position     */
#define I2C1_DATA_BUFFER_Data_Msk                             (0x000000ffUL << I2C1_DATA_BUFFER_Data_Pos)               /*!< I2C1 DATA_BUFFER: Data Mask         */

// ---------------------------------------  I2C1_MASK0  -------------------------------------------
#define I2C1_MASK0_MASK_Pos                                   1                                                         /*!< I2C1 MASK0: MASK Position           */
#define I2C1_MASK0_MASK_Msk                                   (0x7fUL << I2C1_MASK0_MASK_Pos)                           /*!< I2C1 MASK0: MASK Mask               */

// ---------------------------------------  I2C1_MASK1  -------------------------------------------
#define I2C1_MASK1_MASK_Pos                                   1                                                         /*!< I2C1 MASK1: MASK Position           */
#define I2C1_MASK1_MASK_Msk                                   (0x7fUL << I2C1_MASK1_MASK_Pos)                           /*!< I2C1 MASK1: MASK Mask               */

// ---------------------------------------  I2C1_MASK2  -------------------------------------------
#define I2C1_MASK2_MASK_Pos                                   1                                                         /*!< I2C1 MASK2: MASK Position           */
#define I2C1_MASK2_MASK_Msk                                   (0x7fUL << I2C1_MASK2_MASK_Pos)                           /*!< I2C1 MASK2: MASK Mask               */

// ---------------------------------------  I2C1_MASK3  -------------------------------------------
#define I2C1_MASK3_MASK_Pos                                   1                                                         /*!< I2C1 MASK3: MASK Position           */
#define I2C1_MASK3_MASK_Msk                                   (0x7fUL << I2C1_MASK3_MASK_Pos)                           /*!< I2C1 MASK3: MASK Mask               */


// ------------------------------------------------------------------------------------------------
// -----                                 I2S0 Position & Mask                                 -----
// ------------------------------------------------------------------------------------------------


// ----------------------------------------  I2S0_DAO  --------------------------------------------
#define I2S0_DAO_WORDWIDTH_Pos                                0                                                         /*!< I2S0 DAO: WORDWIDTH Position        */
#define I2S0_DAO_WORDWIDTH_Msk                                (0x03UL << I2S0_DAO_WORDWIDTH_Pos)                        /*!< I2S0 DAO: WORDWIDTH Mask            */
#define I2S0_DAO_MONO_Pos                                     2                                                         /*!< I2S0 DAO: MONO Position             */
#define I2S0_DAO_MONO_Msk                                     (0x01UL << I2S0_DAO_MONO_Pos)                             /*!< I2S0 DAO: MONO Mask                 */
#define I2S0_DAO_STOP_Pos                                     3                                                         /*!< I2S0 DAO: STOP Position             */
#define I2S0_DAO_STOP_Msk                                     (0x01UL << I2S0_DAO_STOP_Pos)                             /*!< I2S0 DAO: STOP Mask                 */
#define I2S0_DAO_RESET_Pos                                    4                                                         /*!< I2S0 DAO: RESET Position            */
#define I2S0_DAO_RESET_Msk                                    (0x01UL << I2S0_DAO_RESET_Pos)                            /*!< I2S0 DAO: RESET Mask                */
#define I2S0_DAO_WS_SEL_Pos                                   5                                                         /*!< I2S0 DAO: WS_SEL Position           */
#define I2S0_DAO_WS_SEL_Msk                                   (0x01UL << I2S0_DAO_WS_SEL_Pos)                           /*!< I2S0 DAO: WS_SEL Mask               */
#define I2S0_DAO_WS_HALFPERIOD_Pos                            6                                                         /*!< I2S0 DAO: WS_HALFPERIOD Position    */
#define I2S0_DAO_WS_HALFPERIOD_Msk                            (0x000001ffUL << I2S0_DAO_WS_HALFPERIOD_Pos)              /*!< I2S0 DAO: WS_HALFPERIOD Mask        */
#define I2S0_DAO_MUTE_Pos                                     15                                                        /*!< I2S0 DAO: MUTE Position             */
#define I2S0_DAO_MUTE_Msk                                     (0x01UL << I2S0_DAO_MUTE_Pos)                             /*!< I2S0 DAO: MUTE Mask                 */

// ----------------------------------------  I2S0_DAI  --------------------------------------------
#define I2S0_DAI_WORDWIDTH_Pos                                0                                                         /*!< I2S0 DAI: WORDWIDTH Position        */
#define I2S0_DAI_WORDWIDTH_Msk                                (0x03UL << I2S0_DAI_WORDWIDTH_Pos)                        /*!< I2S0 DAI: WORDWIDTH Mask            */
#define I2S0_DAI_MONO_Pos                                     2                                                         /*!< I2S0 DAI: MONO Position             */
#define I2S0_DAI_MONO_Msk                                     (0x01UL << I2S0_DAI_MONO_Pos)                             /*!< I2S0 DAI: MONO Mask                 */
#define I2S0_DAI_STOP_Pos                                     3                                                         /*!< I2S0 DAI: STOP Position             */
#define I2S0_DAI_STOP_Msk                                     (0x01UL << I2S0_DAI_STOP_Pos)                             /*!< I2S0 DAI: STOP Mask                 */
#define I2S0_DAI_RESET_Pos                                    4                                                         /*!< I2S0 DAI: RESET Position            */
#define I2S0_DAI_RESET_Msk                                    (0x01UL << I2S0_DAI_RESET_Pos)                            /*!< I2S0 DAI: RESET Mask                */
#define I2S0_DAI_WS_SEL_Pos                                   5                                                         /*!< I2S0 DAI: WS_SEL Position           */
#define I2S0_DAI_WS_SEL_Msk                                   (0x01UL << I2S0_DAI_WS_SEL_Pos)                           /*!< I2S0 DAI: WS_SEL Mask               */
#define I2S0_DAI_WS_HALFPERIOD_Pos                            6                                                         /*!< I2S0 DAI: WS_HALFPERIOD Position    */
#define I2S0_DAI_WS_HALFPERIOD_Msk                            (0x000001ffUL << I2S0_DAI_WS_HALFPERIOD_Pos)              /*!< I2S0 DAI: WS_HALFPERIOD Mask        */

// ---------------------------------------  I2S0_TXFIFO  ------------------------------------------
#define I2S0_TXFIFO_I2STXFIFO_Pos                             0                                                         /*!< I2S0 TXFIFO: I2STXFIFO Position     */
#define I2S0_TXFIFO_I2STXFIFO_Msk                             (0xffffffffUL << I2S0_TXFIFO_I2STXFIFO_Pos)               /*!< I2S0 TXFIFO: I2STXFIFO Mask         */

// ---------------------------------------  I2S0_RXFIFO  ------------------------------------------
#define I2S0_RXFIFO_I2SRXFIFO_Pos                             0                                                         /*!< I2S0 RXFIFO: I2SRXFIFO Position     */
#define I2S0_RXFIFO_I2SRXFIFO_Msk                             (0xffffffffUL << I2S0_RXFIFO_I2SRXFIFO_Pos)               /*!< I2S0 RXFIFO: I2SRXFIFO Mask         */

// ---------------------------------------  I2S0_STATE  -------------------------------------------
#define I2S0_STATE_IRQ_Pos                                    0                                                         /*!< I2S0 STATE: IRQ Position            */
#define I2S0_STATE_IRQ_Msk                                    (0x01UL << I2S0_STATE_IRQ_Pos)                            /*!< I2S0 STATE: IRQ Mask                */
#define I2S0_STATE_DMAREQ1_Pos                                1                                                         /*!< I2S0 STATE: DMAREQ1 Position        */
#define I2S0_STATE_DMAREQ1_Msk                                (0x01UL << I2S0_STATE_DMAREQ1_Pos)                        /*!< I2S0 STATE: DMAREQ1 Mask            */
#define I2S0_STATE_DMAREQ2_Pos                                2                                                         /*!< I2S0 STATE: DMAREQ2 Position        */
#define I2S0_STATE_DMAREQ2_Msk                                (0x01UL << I2S0_STATE_DMAREQ2_Pos)                        /*!< I2S0 STATE: DMAREQ2 Mask            */
#define I2S0_STATE_RX_LEVEL_Pos                               8                                                         /*!< I2S0 STATE: RX_LEVEL Position       */
#define I2S0_STATE_RX_LEVEL_Msk                               (0x0fUL << I2S0_STATE_RX_LEVEL_Pos)                       /*!< I2S0 STATE: RX_LEVEL Mask           */
#define I2S0_STATE_TX_LEVEL_Pos                               16                                                        /*!< I2S0 STATE: TX_LEVEL Position       */
#define I2S0_STATE_TX_LEVEL_Msk                               (0x0fUL << I2S0_STATE_TX_LEVEL_Pos)                       /*!< I2S0 STATE: TX_LEVEL Mask           */

// ----------------------------------------  I2S0_DMA1  -------------------------------------------
#define I2S0_DMA1_RX_DMA1_ENABLE_Pos                          0                                                         /*!< I2S0 DMA1: RX_DMA1_ENABLE Position  */
#define I2S0_DMA1_RX_DMA1_ENABLE_Msk                          (0x01UL << I2S0_DMA1_RX_DMA1_ENABLE_Pos)                  /*!< I2S0 DMA1: RX_DMA1_ENABLE Mask      */
#define I2S0_DMA1_TX_DMA1_ENABLE_Pos                          1                                                         /*!< I2S0 DMA1: TX_DMA1_ENABLE Position  */
#define I2S0_DMA1_TX_DMA1_ENABLE_Msk                          (0x01UL << I2S0_DMA1_TX_DMA1_ENABLE_Pos)                  /*!< I2S0 DMA1: TX_DMA1_ENABLE Mask      */
#define I2S0_DMA1_RX_DEPTH_DMA1_Pos                           8                                                         /*!< I2S0 DMA1: RX_DEPTH_DMA1 Position   */
#define I2S0_DMA1_RX_DEPTH_DMA1_Msk                           (0x0fUL << I2S0_DMA1_RX_DEPTH_DMA1_Pos)                   /*!< I2S0 DMA1: RX_DEPTH_DMA1 Mask       */
#define I2S0_DMA1_TX_DEPTH_DMA1_Pos                           16                                                        /*!< I2S0 DMA1: TX_DEPTH_DMA1 Position   */
#define I2S0_DMA1_TX_DEPTH_DMA1_Msk                           (0x0fUL << I2S0_DMA1_TX_DEPTH_DMA1_Pos)                   /*!< I2S0 DMA1: TX_DEPTH_DMA1 Mask       */

// ----------------------------------------  I2S0_DMA2  -------------------------------------------
#define I2S0_DMA2_RX_DMA2_ENABLE_Pos                          0                                                         /*!< I2S0 DMA2: RX_DMA2_ENABLE Position  */
#define I2S0_DMA2_RX_DMA2_ENABLE_Msk                          (0x01UL << I2S0_DMA2_RX_DMA2_ENABLE_Pos)                  /*!< I2S0 DMA2: RX_DMA2_ENABLE Mask      */
#define I2S0_DMA2_TX_DMA2_ENABLE_Pos                          1                                                         /*!< I2S0 DMA2: TX_DMA2_ENABLE Position  */
#define I2S0_DMA2_TX_DMA2_ENABLE_Msk                          (0x01UL << I2S0_DMA2_TX_DMA2_ENABLE_Pos)                  /*!< I2S0 DMA2: TX_DMA2_ENABLE Mask      */
#define I2S0_DMA2_RX_DEPTH_DMA2_Pos                           8                                                         /*!< I2S0 DMA2: RX_DEPTH_DMA2 Position   */
#define I2S0_DMA2_RX_DEPTH_DMA2_Msk                           (0x0fUL << I2S0_DMA2_RX_DEPTH_DMA2_Pos)                   /*!< I2S0 DMA2: RX_DEPTH_DMA2 Mask       */
#define I2S0_DMA2_TX_DEPTH_DMA2_Pos                           16                                                        /*!< I2S0 DMA2: TX_DEPTH_DMA2 Position   */
#define I2S0_DMA2_TX_DEPTH_DMA2_Msk                           (0x0fUL << I2S0_DMA2_TX_DEPTH_DMA2_Pos)                   /*!< I2S0 DMA2: TX_DEPTH_DMA2 Mask       */

// ----------------------------------------  I2S0_IRQ  --------------------------------------------
#define I2S0_IRQ_RX_IRQ_ENABLE_Pos                            0                                                         /*!< I2S0 IRQ: RX_IRQ_ENABLE Position    */
#define I2S0_IRQ_RX_IRQ_ENABLE_Msk                            (0x01UL << I2S0_IRQ_RX_IRQ_ENABLE_Pos)                    /*!< I2S0 IRQ: RX_IRQ_ENABLE Mask        */
#define I2S0_IRQ_TX_IRQ_ENABLE_Pos                            1                                                         /*!< I2S0 IRQ: TX_IRQ_ENABLE Position    */
#define I2S0_IRQ_TX_IRQ_ENABLE_Msk                            (0x01UL << I2S0_IRQ_TX_IRQ_ENABLE_Pos)                    /*!< I2S0 IRQ: TX_IRQ_ENABLE Mask        */
#define I2S0_IRQ_RX_DEPTH_IRQ_Pos                             8                                                         /*!< I2S0 IRQ: RX_DEPTH_IRQ Position     */
#define I2S0_IRQ_RX_DEPTH_IRQ_Msk                             (0x0fUL << I2S0_IRQ_RX_DEPTH_IRQ_Pos)                     /*!< I2S0 IRQ: RX_DEPTH_IRQ Mask         */
#define I2S0_IRQ_TX_DEPTH_IRQ_Pos                             16                                                        /*!< I2S0 IRQ: TX_DEPTH_IRQ Position     */
#define I2S0_IRQ_TX_DEPTH_IRQ_Msk                             (0x0fUL << I2S0_IRQ_TX_DEPTH_IRQ_Pos)                     /*!< I2S0 IRQ: TX_DEPTH_IRQ Mask         */

// ---------------------------------------  I2S0_TXRATE  ------------------------------------------
#define I2S0_TXRATE_Y_DIVIDER_Pos                             0                                                         /*!< I2S0 TXRATE: Y_DIVIDER Position     */
#define I2S0_TXRATE_Y_DIVIDER_Msk                             (0x000000ffUL << I2S0_TXRATE_Y_DIVIDER_Pos)               /*!< I2S0 TXRATE: Y_DIVIDER Mask         */
#define I2S0_TXRATE_X_DIVIDER_Pos                             8                                                         /*!< I2S0 TXRATE: X_DIVIDER Position     */
#define I2S0_TXRATE_X_DIVIDER_Msk                             (0x000000ffUL << I2S0_TXRATE_X_DIVIDER_Pos)               /*!< I2S0 TXRATE: X_DIVIDER Mask         */

// ---------------------------------------  I2S0_RXRATE  ------------------------------------------
#define I2S0_RXRATE_Y_DIVIDER_Pos                             0                                                         /*!< I2S0 RXRATE: Y_DIVIDER Position     */
#define I2S0_RXRATE_Y_DIVIDER_Msk                             (0x000000ffUL << I2S0_RXRATE_Y_DIVIDER_Pos)               /*!< I2S0 RXRATE: Y_DIVIDER Mask         */
#define I2S0_RXRATE_X_DIVIDER_Pos                             8                                                         /*!< I2S0 RXRATE: X_DIVIDER Position     */
#define I2S0_RXRATE_X_DIVIDER_Msk                             (0x000000ffUL << I2S0_RXRATE_X_DIVIDER_Pos)               /*!< I2S0 RXRATE: X_DIVIDER Mask         */

// -------------------------------------  I2S0_TXBITRATE  -----------------------------------------
#define I2S0_TXBITRATE_TX_BITRATE_Pos                         0                                                         /*!< I2S0 TXBITRATE: TX_BITRATE Position */
#define I2S0_TXBITRATE_TX_BITRATE_Msk                         (0x3fUL << I2S0_TXBITRATE_TX_BITRATE_Pos)                 /*!< I2S0 TXBITRATE: TX_BITRATE Mask     */

// -------------------------------------  I2S0_RXBITRATE  -----------------------------------------
#define I2S0_RXBITRATE_RX_BITRATE_Pos                         0                                                         /*!< I2S0 RXBITRATE: RX_BITRATE Position */
#define I2S0_RXBITRATE_RX_BITRATE_Msk                         (0x3fUL << I2S0_RXBITRATE_RX_BITRATE_Pos)                 /*!< I2S0 RXBITRATE: RX_BITRATE Mask     */

// ---------------------------------------  I2S0_TXMODE  ------------------------------------------
#define I2S0_TXMODE_TXCLKSEL_Pos                              0                                                         /*!< I2S0 TXMODE: TXCLKSEL Position      */
#define I2S0_TXMODE_TXCLKSEL_Msk                              (0x03UL << I2S0_TXMODE_TXCLKSEL_Pos)                      /*!< I2S0 TXMODE: TXCLKSEL Mask          */
#define I2S0_TXMODE_TX4PIN_Pos                                2                                                         /*!< I2S0 TXMODE: TX4PIN Position        */
#define I2S0_TXMODE_TX4PIN_Msk                                (0x01UL << I2S0_TXMODE_TX4PIN_Pos)                        /*!< I2S0 TXMODE: TX4PIN Mask            */
#define I2S0_TXMODE_TXMCENA_Pos                               3                                                         /*!< I2S0 TXMODE: TXMCENA Position       */
#define I2S0_TXMODE_TXMCENA_Msk                               (0x01UL << I2S0_TXMODE_TXMCENA_Pos)                       /*!< I2S0 TXMODE: TXMCENA Mask           */

// ---------------------------------------  I2S0_RXMODE  ------------------------------------------
#define I2S0_RXMODE_RXCLKSEL_Pos                              0                                                         /*!< I2S0 RXMODE: RXCLKSEL Position      */
#define I2S0_RXMODE_RXCLKSEL_Msk                              (0x03UL << I2S0_RXMODE_RXCLKSEL_Pos)                      /*!< I2S0 RXMODE: RXCLKSEL Mask          */
#define I2S0_RXMODE_RX4PIN_Pos                                2                                                         /*!< I2S0 RXMODE: RX4PIN Position        */
#define I2S0_RXMODE_RX4PIN_Msk                                (0x01UL << I2S0_RXMODE_RX4PIN_Pos)                        /*!< I2S0 RXMODE: RX4PIN Mask            */
#define I2S0_RXMODE_RXMCENA_Pos                               3                                                         /*!< I2S0 RXMODE: RXMCENA Position       */
#define I2S0_RXMODE_RXMCENA_Msk                               (0x01UL << I2S0_RXMODE_RXMCENA_Pos)                       /*!< I2S0 RXMODE: RXMCENA Mask           */


// ------------------------------------------------------------------------------------------------
// -----                                 I2S1 Position & Mask                                 -----
// ------------------------------------------------------------------------------------------------


// ----------------------------------------  I2S1_DAO  --------------------------------------------
#define I2S1_DAO_WORDWIDTH_Pos                                0                                                         /*!< I2S1 DAO: WORDWIDTH Position        */
#define I2S1_DAO_WORDWIDTH_Msk                                (0x03UL << I2S1_DAO_WORDWIDTH_Pos)                        /*!< I2S1 DAO: WORDWIDTH Mask            */
#define I2S1_DAO_MONO_Pos                                     2                                                         /*!< I2S1 DAO: MONO Position             */
#define I2S1_DAO_MONO_Msk                                     (0x01UL << I2S1_DAO_MONO_Pos)                             /*!< I2S1 DAO: MONO Mask                 */
#define I2S1_DAO_STOP_Pos                                     3                                                         /*!< I2S1 DAO: STOP Position             */
#define I2S1_DAO_STOP_Msk                                     (0x01UL << I2S1_DAO_STOP_Pos)                             /*!< I2S1 DAO: STOP Mask                 */
#define I2S1_DAO_RESET_Pos                                    4                                                         /*!< I2S1 DAO: RESET Position            */
#define I2S1_DAO_RESET_Msk                                    (0x01UL << I2S1_DAO_RESET_Pos)                            /*!< I2S1 DAO: RESET Mask                */
#define I2S1_DAO_WS_SEL_Pos                                   5                                                         /*!< I2S1 DAO: WS_SEL Position           */
#define I2S1_DAO_WS_SEL_Msk                                   (0x01UL << I2S1_DAO_WS_SEL_Pos)                           /*!< I2S1 DAO: WS_SEL Mask               */
#define I2S1_DAO_WS_HALFPERIOD_Pos                            6                                                         /*!< I2S1 DAO: WS_HALFPERIOD Position    */
#define I2S1_DAO_WS_HALFPERIOD_Msk                            (0x000001ffUL << I2S1_DAO_WS_HALFPERIOD_Pos)              /*!< I2S1 DAO: WS_HALFPERIOD Mask        */
#define I2S1_DAO_MUTE_Pos                                     15                                                        /*!< I2S1 DAO: MUTE Position             */
#define I2S1_DAO_MUTE_Msk                                     (0x01UL << I2S1_DAO_MUTE_Pos)                             /*!< I2S1 DAO: MUTE Mask                 */

// ----------------------------------------  I2S1_DAI  --------------------------------------------
#define I2S1_DAI_WORDWIDTH_Pos                                0                                                         /*!< I2S1 DAI: WORDWIDTH Position        */
#define I2S1_DAI_WORDWIDTH_Msk                                (0x03UL << I2S1_DAI_WORDWIDTH_Pos)                        /*!< I2S1 DAI: WORDWIDTH Mask            */
#define I2S1_DAI_MONO_Pos                                     2                                                         /*!< I2S1 DAI: MONO Position             */
#define I2S1_DAI_MONO_Msk                                     (0x01UL << I2S1_DAI_MONO_Pos)                             /*!< I2S1 DAI: MONO Mask                 */
#define I2S1_DAI_STOP_Pos                                     3                                                         /*!< I2S1 DAI: STOP Position             */
#define I2S1_DAI_STOP_Msk                                     (0x01UL << I2S1_DAI_STOP_Pos)                             /*!< I2S1 DAI: STOP Mask                 */
#define I2S1_DAI_RESET_Pos                                    4                                                         /*!< I2S1 DAI: RESET Position            */
#define I2S1_DAI_RESET_Msk                                    (0x01UL << I2S1_DAI_RESET_Pos)                            /*!< I2S1 DAI: RESET Mask                */
#define I2S1_DAI_WS_SEL_Pos                                   5                                                         /*!< I2S1 DAI: WS_SEL Position           */
#define I2S1_DAI_WS_SEL_Msk                                   (0x01UL << I2S1_DAI_WS_SEL_Pos)                           /*!< I2S1 DAI: WS_SEL Mask               */
#define I2S1_DAI_WS_HALFPERIOD_Pos                            6                                                         /*!< I2S1 DAI: WS_HALFPERIOD Position    */
#define I2S1_DAI_WS_HALFPERIOD_Msk                            (0x000001ffUL << I2S1_DAI_WS_HALFPERIOD_Pos)              /*!< I2S1 DAI: WS_HALFPERIOD Mask        */

// ---------------------------------------  I2S1_TXFIFO  ------------------------------------------
#define I2S1_TXFIFO_I2STXFIFO_Pos                             0                                                         /*!< I2S1 TXFIFO: I2STXFIFO Position     */
#define I2S1_TXFIFO_I2STXFIFO_Msk                             (0xffffffffUL << I2S1_TXFIFO_I2STXFIFO_Pos)               /*!< I2S1 TXFIFO: I2STXFIFO Mask         */

// ---------------------------------------  I2S1_RXFIFO  ------------------------------------------
#define I2S1_RXFIFO_I2SRXFIFO_Pos                             0                                                         /*!< I2S1 RXFIFO: I2SRXFIFO Position     */
#define I2S1_RXFIFO_I2SRXFIFO_Msk                             (0xffffffffUL << I2S1_RXFIFO_I2SRXFIFO_Pos)               /*!< I2S1 RXFIFO: I2SRXFIFO Mask         */

// ---------------------------------------  I2S1_STATE  -------------------------------------------
#define I2S1_STATE_IRQ_Pos                                    0                                                         /*!< I2S1 STATE: IRQ Position            */
#define I2S1_STATE_IRQ_Msk                                    (0x01UL << I2S1_STATE_IRQ_Pos)                            /*!< I2S1 STATE: IRQ Mask                */
#define I2S1_STATE_DMAREQ1_Pos                                1                                                         /*!< I2S1 STATE: DMAREQ1 Position        */
#define I2S1_STATE_DMAREQ1_Msk                                (0x01UL << I2S1_STATE_DMAREQ1_Pos)                        /*!< I2S1 STATE: DMAREQ1 Mask            */
#define I2S1_STATE_DMAREQ2_Pos                                2                                                         /*!< I2S1 STATE: DMAREQ2 Position        */
#define I2S1_STATE_DMAREQ2_Msk                                (0x01UL << I2S1_STATE_DMAREQ2_Pos)                        /*!< I2S1 STATE: DMAREQ2 Mask            */
#define I2S1_STATE_RX_LEVEL_Pos                               8                                                         /*!< I2S1 STATE: RX_LEVEL Position       */
#define I2S1_STATE_RX_LEVEL_Msk                               (0x0fUL << I2S1_STATE_RX_LEVEL_Pos)                       /*!< I2S1 STATE: RX_LEVEL Mask           */
#define I2S1_STATE_TX_LEVEL_Pos                               16                                                        /*!< I2S1 STATE: TX_LEVEL Position       */
#define I2S1_STATE_TX_LEVEL_Msk                               (0x0fUL << I2S1_STATE_TX_LEVEL_Pos)                       /*!< I2S1 STATE: TX_LEVEL Mask           */

// ----------------------------------------  I2S1_DMA1  -------------------------------------------
#define I2S1_DMA1_RX_DMA1_ENABLE_Pos                          0                                                         /*!< I2S1 DMA1: RX_DMA1_ENABLE Position  */
#define I2S1_DMA1_RX_DMA1_ENABLE_Msk                          (0x01UL << I2S1_DMA1_RX_DMA1_ENABLE_Pos)                  /*!< I2S1 DMA1: RX_DMA1_ENABLE Mask      */
#define I2S1_DMA1_TX_DMA1_ENABLE_Pos                          1                                                         /*!< I2S1 DMA1: TX_DMA1_ENABLE Position  */
#define I2S1_DMA1_TX_DMA1_ENABLE_Msk                          (0x01UL << I2S1_DMA1_TX_DMA1_ENABLE_Pos)                  /*!< I2S1 DMA1: TX_DMA1_ENABLE Mask      */
#define I2S1_DMA1_RX_DEPTH_DMA1_Pos                           8                                                         /*!< I2S1 DMA1: RX_DEPTH_DMA1 Position   */
#define I2S1_DMA1_RX_DEPTH_DMA1_Msk                           (0x0fUL << I2S1_DMA1_RX_DEPTH_DMA1_Pos)                   /*!< I2S1 DMA1: RX_DEPTH_DMA1 Mask       */
#define I2S1_DMA1_TX_DEPTH_DMA1_Pos                           16                                                        /*!< I2S1 DMA1: TX_DEPTH_DMA1 Position   */
#define I2S1_DMA1_TX_DEPTH_DMA1_Msk                           (0x0fUL << I2S1_DMA1_TX_DEPTH_DMA1_Pos)                   /*!< I2S1 DMA1: TX_DEPTH_DMA1 Mask       */

// ----------------------------------------  I2S1_DMA2  -------------------------------------------
#define I2S1_DMA2_RX_DMA2_ENABLE_Pos                          0                                                         /*!< I2S1 DMA2: RX_DMA2_ENABLE Position  */
#define I2S1_DMA2_RX_DMA2_ENABLE_Msk                          (0x01UL << I2S1_DMA2_RX_DMA2_ENABLE_Pos)                  /*!< I2S1 DMA2: RX_DMA2_ENABLE Mask      */
#define I2S1_DMA2_TX_DMA2_ENABLE_Pos                          1                                                         /*!< I2S1 DMA2: TX_DMA2_ENABLE Position  */
#define I2S1_DMA2_TX_DMA2_ENABLE_Msk                          (0x01UL << I2S1_DMA2_TX_DMA2_ENABLE_Pos)                  /*!< I2S1 DMA2: TX_DMA2_ENABLE Mask      */
#define I2S1_DMA2_RX_DEPTH_DMA2_Pos                           8                                                         /*!< I2S1 DMA2: RX_DEPTH_DMA2 Position   */
#define I2S1_DMA2_RX_DEPTH_DMA2_Msk                           (0x0fUL << I2S1_DMA2_RX_DEPTH_DMA2_Pos)                   /*!< I2S1 DMA2: RX_DEPTH_DMA2 Mask       */
#define I2S1_DMA2_TX_DEPTH_DMA2_Pos                           16                                                        /*!< I2S1 DMA2: TX_DEPTH_DMA2 Position   */
#define I2S1_DMA2_TX_DEPTH_DMA2_Msk                           (0x0fUL << I2S1_DMA2_TX_DEPTH_DMA2_Pos)                   /*!< I2S1 DMA2: TX_DEPTH_DMA2 Mask       */

// ----------------------------------------  I2S1_IRQ  --------------------------------------------
#define I2S1_IRQ_RX_IRQ_ENABLE_Pos                            0                                                         /*!< I2S1 IRQ: RX_IRQ_ENABLE Position    */
#define I2S1_IRQ_RX_IRQ_ENABLE_Msk                            (0x01UL << I2S1_IRQ_RX_IRQ_ENABLE_Pos)                    /*!< I2S1 IRQ: RX_IRQ_ENABLE Mask        */
#define I2S1_IRQ_TX_IRQ_ENABLE_Pos                            1                                                         /*!< I2S1 IRQ: TX_IRQ_ENABLE Position    */
#define I2S1_IRQ_TX_IRQ_ENABLE_Msk                            (0x01UL << I2S1_IRQ_TX_IRQ_ENABLE_Pos)                    /*!< I2S1 IRQ: TX_IRQ_ENABLE Mask        */
#define I2S1_IRQ_RX_DEPTH_IRQ_Pos                             8                                                         /*!< I2S1 IRQ: RX_DEPTH_IRQ Position     */
#define I2S1_IRQ_RX_DEPTH_IRQ_Msk                             (0x0fUL << I2S1_IRQ_RX_DEPTH_IRQ_Pos)                     /*!< I2S1 IRQ: RX_DEPTH_IRQ Mask         */
#define I2S1_IRQ_TX_DEPTH_IRQ_Pos                             16                                                        /*!< I2S1 IRQ: TX_DEPTH_IRQ Position     */
#define I2S1_IRQ_TX_DEPTH_IRQ_Msk                             (0x0fUL << I2S1_IRQ_TX_DEPTH_IRQ_Pos)                     /*!< I2S1 IRQ: TX_DEPTH_IRQ Mask         */

// ---------------------------------------  I2S1_TXRATE  ------------------------------------------
#define I2S1_TXRATE_Y_DIVIDER_Pos                             0                                                         /*!< I2S1 TXRATE: Y_DIVIDER Position     */
#define I2S1_TXRATE_Y_DIVIDER_Msk                             (0x000000ffUL << I2S1_TXRATE_Y_DIVIDER_Pos)               /*!< I2S1 TXRATE: Y_DIVIDER Mask         */
#define I2S1_TXRATE_X_DIVIDER_Pos                             8                                                         /*!< I2S1 TXRATE: X_DIVIDER Position     */
#define I2S1_TXRATE_X_DIVIDER_Msk                             (0x000000ffUL << I2S1_TXRATE_X_DIVIDER_Pos)               /*!< I2S1 TXRATE: X_DIVIDER Mask         */

// ---------------------------------------  I2S1_RXRATE  ------------------------------------------
#define I2S1_RXRATE_Y_DIVIDER_Pos                             0                                                         /*!< I2S1 RXRATE: Y_DIVIDER Position     */
#define I2S1_RXRATE_Y_DIVIDER_Msk                             (0x000000ffUL << I2S1_RXRATE_Y_DIVIDER_Pos)               /*!< I2S1 RXRATE: Y_DIVIDER Mask         */
#define I2S1_RXRATE_X_DIVIDER_Pos                             8                                                         /*!< I2S1 RXRATE: X_DIVIDER Position     */
#define I2S1_RXRATE_X_DIVIDER_Msk                             (0x000000ffUL << I2S1_RXRATE_X_DIVIDER_Pos)               /*!< I2S1 RXRATE: X_DIVIDER Mask         */

// -------------------------------------  I2S1_TXBITRATE  -----------------------------------------
#define I2S1_TXBITRATE_TX_BITRATE_Pos                         0                                                         /*!< I2S1 TXBITRATE: TX_BITRATE Position */
#define I2S1_TXBITRATE_TX_BITRATE_Msk                         (0x3fUL << I2S1_TXBITRATE_TX_BITRATE_Pos)                 /*!< I2S1 TXBITRATE: TX_BITRATE Mask     */

// -------------------------------------  I2S1_RXBITRATE  -----------------------------------------
#define I2S1_RXBITRATE_RX_BITRATE_Pos                         0                                                         /*!< I2S1 RXBITRATE: RX_BITRATE Position */
#define I2S1_RXBITRATE_RX_BITRATE_Msk                         (0x3fUL << I2S1_RXBITRATE_RX_BITRATE_Pos)                 /*!< I2S1 RXBITRATE: RX_BITRATE Mask     */

// ---------------------------------------  I2S1_TXMODE  ------------------------------------------
#define I2S1_TXMODE_TXCLKSEL_Pos                              0                                                         /*!< I2S1 TXMODE: TXCLKSEL Position      */
#define I2S1_TXMODE_TXCLKSEL_Msk                              (0x03UL << I2S1_TXMODE_TXCLKSEL_Pos)                      /*!< I2S1 TXMODE: TXCLKSEL Mask          */
#define I2S1_TXMODE_TX4PIN_Pos                                2                                                         /*!< I2S1 TXMODE: TX4PIN Position        */
#define I2S1_TXMODE_TX4PIN_Msk                                (0x01UL << I2S1_TXMODE_TX4PIN_Pos)                        /*!< I2S1 TXMODE: TX4PIN Mask            */
#define I2S1_TXMODE_TXMCENA_Pos                               3                                                         /*!< I2S1 TXMODE: TXMCENA Position       */
#define I2S1_TXMODE_TXMCENA_Msk                               (0x01UL << I2S1_TXMODE_TXMCENA_Pos)                       /*!< I2S1 TXMODE: TXMCENA Mask           */

// ---------------------------------------  I2S1_RXMODE  ------------------------------------------
#define I2S1_RXMODE_RXCLKSEL_Pos                              0                                                         /*!< I2S1 RXMODE: RXCLKSEL Position      */
#define I2S1_RXMODE_RXCLKSEL_Msk                              (0x03UL << I2S1_RXMODE_RXCLKSEL_Pos)                      /*!< I2S1 RXMODE: RXCLKSEL Mask          */
#define I2S1_RXMODE_RX4PIN_Pos                                2                                                         /*!< I2S1 RXMODE: RX4PIN Position        */
#define I2S1_RXMODE_RX4PIN_Msk                                (0x01UL << I2S1_RXMODE_RX4PIN_Pos)                        /*!< I2S1 RXMODE: RX4PIN Mask            */
#define I2S1_RXMODE_RXMCENA_Pos                               3                                                         /*!< I2S1 RXMODE: RXMCENA Position       */
#define I2S1_RXMODE_RXMCENA_Msk                               (0x01UL << I2S1_RXMODE_RXMCENA_Pos)                       /*!< I2S1 RXMODE: RXMCENA Mask           */


// ------------------------------------------------------------------------------------------------
// -----                                C_CAN1 Position & Mask                                -----
// ------------------------------------------------------------------------------------------------


// ---------------------------------------  C_CAN1_CNTL  ------------------------------------------
#define C_CAN1_CNTL_INIT_Pos                                  0                                                         /*!< C_CAN1 CNTL: INIT Position          */
#define C_CAN1_CNTL_INIT_Msk                                  (0x01UL << C_CAN1_CNTL_INIT_Pos)                          /*!< C_CAN1 CNTL: INIT Mask              */
#define C_CAN1_CNTL_IE_Pos                                    1                                                         /*!< C_CAN1 CNTL: IE Position            */
#define C_CAN1_CNTL_IE_Msk                                    (0x01UL << C_CAN1_CNTL_IE_Pos)                            /*!< C_CAN1 CNTL: IE Mask                */
#define C_CAN1_CNTL_SIE_Pos                                   2                                                         /*!< C_CAN1 CNTL: SIE Position           */
#define C_CAN1_CNTL_SIE_Msk                                   (0x01UL << C_CAN1_CNTL_SIE_Pos)                           /*!< C_CAN1 CNTL: SIE Mask               */
#define C_CAN1_CNTL_EIE_Pos                                   3                                                         /*!< C_CAN1 CNTL: EIE Position           */
#define C_CAN1_CNTL_EIE_Msk                                   (0x01UL << C_CAN1_CNTL_EIE_Pos)                           /*!< C_CAN1 CNTL: EIE Mask               */
#define C_CAN1_CNTL_DAR_Pos                                   5                                                         /*!< C_CAN1 CNTL: DAR Position           */
#define C_CAN1_CNTL_DAR_Msk                                   (0x01UL << C_CAN1_CNTL_DAR_Pos)                           /*!< C_CAN1 CNTL: DAR Mask               */
#define C_CAN1_CNTL_CCE_Pos                                   6                                                         /*!< C_CAN1 CNTL: CCE Position           */
#define C_CAN1_CNTL_CCE_Msk                                   (0x01UL << C_CAN1_CNTL_CCE_Pos)                           /*!< C_CAN1 CNTL: CCE Mask               */
#define C_CAN1_CNTL_TEST_Pos                                  7                                                         /*!< C_CAN1 CNTL: TEST Position          */
#define C_CAN1_CNTL_TEST_Msk                                  (0x01UL << C_CAN1_CNTL_TEST_Pos)                          /*!< C_CAN1 CNTL: TEST Mask              */

// ---------------------------------------  C_CAN1_STAT  ------------------------------------------
#define C_CAN1_STAT_LEC_Pos                                   0                                                         /*!< C_CAN1 STAT: LEC Position           */
#define C_CAN1_STAT_LEC_Msk                                   (0x07UL << C_CAN1_STAT_LEC_Pos)                           /*!< C_CAN1 STAT: LEC Mask               */
#define C_CAN1_STAT_TXOK_Pos                                  3                                                         /*!< C_CAN1 STAT: TXOK Position          */
#define C_CAN1_STAT_TXOK_Msk                                  (0x01UL << C_CAN1_STAT_TXOK_Pos)                          /*!< C_CAN1 STAT: TXOK Mask              */
#define C_CAN1_STAT_RXOK_Pos                                  4                                                         /*!< C_CAN1 STAT: RXOK Position          */
#define C_CAN1_STAT_RXOK_Msk                                  (0x01UL << C_CAN1_STAT_RXOK_Pos)                          /*!< C_CAN1 STAT: RXOK Mask              */
#define C_CAN1_STAT_EPASS_Pos                                 5                                                         /*!< C_CAN1 STAT: EPASS Position         */
#define C_CAN1_STAT_EPASS_Msk                                 (0x01UL << C_CAN1_STAT_EPASS_Pos)                         /*!< C_CAN1 STAT: EPASS Mask             */
#define C_CAN1_STAT_EWARN_Pos                                 6                                                         /*!< C_CAN1 STAT: EWARN Position         */
#define C_CAN1_STAT_EWARN_Msk                                 (0x01UL << C_CAN1_STAT_EWARN_Pos)                         /*!< C_CAN1 STAT: EWARN Mask             */
#define C_CAN1_STAT_BOFF_Pos                                  7                                                         /*!< C_CAN1 STAT: BOFF Position          */
#define C_CAN1_STAT_BOFF_Msk                                  (0x01UL << C_CAN1_STAT_BOFF_Pos)                          /*!< C_CAN1 STAT: BOFF Mask              */

// ----------------------------------------  C_CAN1_EC  -------------------------------------------
#define C_CAN1_EC_TEC_7_0_Pos                                 0                                                         /*!< C_CAN1 EC: TEC_7_0 Position         */
#define C_CAN1_EC_TEC_7_0_Msk                                 (0x000000ffUL << C_CAN1_EC_TEC_7_0_Pos)                   /*!< C_CAN1 EC: TEC_7_0 Mask             */
#define C_CAN1_EC_REC_6_0_Pos                                 8                                                         /*!< C_CAN1 EC: REC_6_0 Position         */
#define C_CAN1_EC_REC_6_0_Msk                                 (0x7fUL << C_CAN1_EC_REC_6_0_Pos)                         /*!< C_CAN1 EC: REC_6_0 Mask             */
#define C_CAN1_EC_RP_Pos                                      15                                                        /*!< C_CAN1 EC: RP Position              */
#define C_CAN1_EC_RP_Msk                                      (0x01UL << C_CAN1_EC_RP_Pos)                              /*!< C_CAN1 EC: RP Mask                  */

// ----------------------------------------  C_CAN1_BT  -------------------------------------------
#define C_CAN1_BT_BRP_Pos                                     0                                                         /*!< C_CAN1 BT: BRP Position             */
#define C_CAN1_BT_BRP_Msk                                     (0x3fUL << C_CAN1_BT_BRP_Pos)                             /*!< C_CAN1 BT: BRP Mask                 */
#define C_CAN1_BT_SJW_Pos                                     6                                                         /*!< C_CAN1 BT: SJW Position             */
#define C_CAN1_BT_SJW_Msk                                     (0x03UL << C_CAN1_BT_SJW_Pos)                             /*!< C_CAN1 BT: SJW Mask                 */
#define C_CAN1_BT_TSEG1_Pos                                   8                                                         /*!< C_CAN1 BT: TSEG1 Position           */
#define C_CAN1_BT_TSEG1_Msk                                   (0x0fUL << C_CAN1_BT_TSEG1_Pos)                           /*!< C_CAN1 BT: TSEG1 Mask               */
#define C_CAN1_BT_TSEG2_Pos                                   12                                                        /*!< C_CAN1 BT: TSEG2 Position           */
#define C_CAN1_BT_TSEG2_Msk                                   (0x07UL << C_CAN1_BT_TSEG2_Pos)                           /*!< C_CAN1 BT: TSEG2 Mask               */

// ---------------------------------------  C_CAN1_INT  -------------------------------------------
#define C_CAN1_INT_INTID15_0_Pos                              0                                                         /*!< C_CAN1 INT: INTID15_0 Position      */
#define C_CAN1_INT_INTID15_0_Msk                              (0x0000ffffUL << C_CAN1_INT_INTID15_0_Pos)                /*!< C_CAN1 INT: INTID15_0 Mask          */

// ---------------------------------------  C_CAN1_TEST  ------------------------------------------
#define C_CAN1_TEST_BASIC_Pos                                 2                                                         /*!< C_CAN1 TEST: BASIC Position         */
#define C_CAN1_TEST_BASIC_Msk                                 (0x01UL << C_CAN1_TEST_BASIC_Pos)                         /*!< C_CAN1 TEST: BASIC Mask             */
#define C_CAN1_TEST_SILENT_Pos                                3                                                         /*!< C_CAN1 TEST: SILENT Position        */
#define C_CAN1_TEST_SILENT_Msk                                (0x01UL << C_CAN1_TEST_SILENT_Pos)                        /*!< C_CAN1 TEST: SILENT Mask            */
#define C_CAN1_TEST_LBACK_Pos                                 4                                                         /*!< C_CAN1 TEST: LBACK Position         */
#define C_CAN1_TEST_LBACK_Msk                                 (0x01UL << C_CAN1_TEST_LBACK_Pos)                         /*!< C_CAN1 TEST: LBACK Mask             */
#define C_CAN1_TEST_TX1_0_Pos                                 5                                                         /*!< C_CAN1 TEST: TX1_0 Position         */
#define C_CAN1_TEST_TX1_0_Msk                                 (0x03UL << C_CAN1_TEST_TX1_0_Pos)                         /*!< C_CAN1 TEST: TX1_0 Mask             */
#define C_CAN1_TEST_RX_Pos                                    7                                                         /*!< C_CAN1 TEST: RX Position            */
#define C_CAN1_TEST_RX_Msk                                    (0x01UL << C_CAN1_TEST_RX_Pos)                            /*!< C_CAN1 TEST: RX Mask                */

// ---------------------------------------  C_CAN1_BRPE  ------------------------------------------
#define C_CAN1_BRPE_BRPE_Pos                                  0                                                         /*!< C_CAN1 BRPE: BRPE Position          */
#define C_CAN1_BRPE_BRPE_Msk                                  (0x0fUL << C_CAN1_BRPE_BRPE_Pos)                          /*!< C_CAN1 BRPE: BRPE Mask              */

// ------------------------------------  C_CAN1_IF1_CMDREQ  ---------------------------------------
#define C_CAN1_IF1_CMDREQ_MESSNUM_Pos                         0                                                         /*!< C_CAN1 IF1_CMDREQ: MESSNUM Position */
#define C_CAN1_IF1_CMDREQ_MESSNUM_Msk                         (0x3fUL << C_CAN1_IF1_CMDREQ_MESSNUM_Pos)                 /*!< C_CAN1 IF1_CMDREQ: MESSNUM Mask     */
#define C_CAN1_IF1_CMDREQ_BUSY_Pos                            15                                                        /*!< C_CAN1 IF1_CMDREQ: BUSY Position    */
#define C_CAN1_IF1_CMDREQ_BUSY_Msk                            (0x01UL << C_CAN1_IF1_CMDREQ_BUSY_Pos)                    /*!< C_CAN1 IF1_CMDREQ: BUSY Mask        */

// -----------------------------------  C_CAN1_IF1_CMDMSK_W  --------------------------------------
#define C_CAN1_IF1_CMDMSK_W_DATA_B_Pos                        0                                                         /*!< C_CAN1 IF1_CMDMSK_W: DATA_B Position */
#define C_CAN1_IF1_CMDMSK_W_DATA_B_Msk                        (0x01UL << C_CAN1_IF1_CMDMSK_W_DATA_B_Pos)                /*!< C_CAN1 IF1_CMDMSK_W: DATA_B Mask    */
#define C_CAN1_IF1_CMDMSK_W_DATA_A_Pos                        1                                                         /*!< C_CAN1 IF1_CMDMSK_W: DATA_A Position */
#define C_CAN1_IF1_CMDMSK_W_DATA_A_Msk                        (0x01UL << C_CAN1_IF1_CMDMSK_W_DATA_A_Pos)                /*!< C_CAN1 IF1_CMDMSK_W: DATA_A Mask    */
#define C_CAN1_IF1_CMDMSK_W_TXRQST_Pos                        2                                                         /*!< C_CAN1 IF1_CMDMSK_W: TXRQST Position */
#define C_CAN1_IF1_CMDMSK_W_TXRQST_Msk                        (0x01UL << C_CAN1_IF1_CMDMSK_W_TXRQST_Pos)                /*!< C_CAN1 IF1_CMDMSK_W: TXRQST Mask    */
#define C_CAN1_IF1_CMDMSK_W_CLRINTPND_Pos                     3                                                         /*!< C_CAN1 IF1_CMDMSK_W: CLRINTPND Position */
#define C_CAN1_IF1_CMDMSK_W_CLRINTPND_Msk                     (0x01UL << C_CAN1_IF1_CMDMSK_W_CLRINTPND_Pos)             /*!< C_CAN1 IF1_CMDMSK_W: CLRINTPND Mask */
#define C_CAN1_IF1_CMDMSK_W_CTRL_Pos                          4                                                         /*!< C_CAN1 IF1_CMDMSK_W: CTRL Position  */
#define C_CAN1_IF1_CMDMSK_W_CTRL_Msk                          (0x01UL << C_CAN1_IF1_CMDMSK_W_CTRL_Pos)                  /*!< C_CAN1 IF1_CMDMSK_W: CTRL Mask      */
#define C_CAN1_IF1_CMDMSK_W_ARB_Pos                           5                                                         /*!< C_CAN1 IF1_CMDMSK_W: ARB Position   */
#define C_CAN1_IF1_CMDMSK_W_ARB_Msk                           (0x01UL << C_CAN1_IF1_CMDMSK_W_ARB_Pos)                   /*!< C_CAN1 IF1_CMDMSK_W: ARB Mask       */
#define C_CAN1_IF1_CMDMSK_W_MASK_Pos                          6                                                         /*!< C_CAN1 IF1_CMDMSK_W: MASK Position  */
#define C_CAN1_IF1_CMDMSK_W_MASK_Msk                          (0x01UL << C_CAN1_IF1_CMDMSK_W_MASK_Pos)                  /*!< C_CAN1 IF1_CMDMSK_W: MASK Mask      */
#define C_CAN1_IF1_CMDMSK_W_WR_RD_Pos                         7                                                         /*!< C_CAN1 IF1_CMDMSK_W: WR_RD Position */
#define C_CAN1_IF1_CMDMSK_W_WR_RD_Msk                         (0x01UL << C_CAN1_IF1_CMDMSK_W_WR_RD_Pos)                 /*!< C_CAN1 IF1_CMDMSK_W: WR_RD Mask     */

// -----------------------------------  C_CAN1_IF1_CMDMSK_R  --------------------------------------
#define C_CAN1_IF1_CMDMSK_R_DATA_B_Pos                        0                                                         /*!< C_CAN1 IF1_CMDMSK_R: DATA_B Position */
#define C_CAN1_IF1_CMDMSK_R_DATA_B_Msk                        (0x01UL << C_CAN1_IF1_CMDMSK_R_DATA_B_Pos)                /*!< C_CAN1 IF1_CMDMSK_R: DATA_B Mask    */
#define C_CAN1_IF1_CMDMSK_R_DATA_A_Pos                        1                                                         /*!< C_CAN1 IF1_CMDMSK_R: DATA_A Position */
#define C_CAN1_IF1_CMDMSK_R_DATA_A_Msk                        (0x01UL << C_CAN1_IF1_CMDMSK_R_DATA_A_Pos)                /*!< C_CAN1 IF1_CMDMSK_R: DATA_A Mask    */
#define C_CAN1_IF1_CMDMSK_R_NEWDAT_Pos                        2                                                         /*!< C_CAN1 IF1_CMDMSK_R: NEWDAT Position */
#define C_CAN1_IF1_CMDMSK_R_NEWDAT_Msk                        (0x01UL << C_CAN1_IF1_CMDMSK_R_NEWDAT_Pos)                /*!< C_CAN1 IF1_CMDMSK_R: NEWDAT Mask    */
#define C_CAN1_IF1_CMDMSK_R_CLRINTPND_Pos                     3                                                         /*!< C_CAN1 IF1_CMDMSK_R: CLRINTPND Position */
#define C_CAN1_IF1_CMDMSK_R_CLRINTPND_Msk                     (0x01UL << C_CAN1_IF1_CMDMSK_R_CLRINTPND_Pos)             /*!< C_CAN1 IF1_CMDMSK_R: CLRINTPND Mask */
#define C_CAN1_IF1_CMDMSK_R_CTRL_Pos                          4                                                         /*!< C_CAN1 IF1_CMDMSK_R: CTRL Position  */
#define C_CAN1_IF1_CMDMSK_R_CTRL_Msk                          (0x01UL << C_CAN1_IF1_CMDMSK_R_CTRL_Pos)                  /*!< C_CAN1 IF1_CMDMSK_R: CTRL Mask      */
#define C_CAN1_IF1_CMDMSK_R_ARB_Pos                           5                                                         /*!< C_CAN1 IF1_CMDMSK_R: ARB Position   */
#define C_CAN1_IF1_CMDMSK_R_ARB_Msk                           (0x01UL << C_CAN1_IF1_CMDMSK_R_ARB_Pos)                   /*!< C_CAN1 IF1_CMDMSK_R: ARB Mask       */
#define C_CAN1_IF1_CMDMSK_R_MASK_Pos                          6                                                         /*!< C_CAN1 IF1_CMDMSK_R: MASK Position  */
#define C_CAN1_IF1_CMDMSK_R_MASK_Msk                          (0x01UL << C_CAN1_IF1_CMDMSK_R_MASK_Pos)                  /*!< C_CAN1 IF1_CMDMSK_R: MASK Mask      */
#define C_CAN1_IF1_CMDMSK_R_WR_RD_Pos                         7                                                         /*!< C_CAN1 IF1_CMDMSK_R: WR_RD Position */
#define C_CAN1_IF1_CMDMSK_R_WR_RD_Msk                         (0x01UL << C_CAN1_IF1_CMDMSK_R_WR_RD_Pos)                 /*!< C_CAN1 IF1_CMDMSK_R: WR_RD Mask     */

// -------------------------------------  C_CAN1_IF1_MSK1  ----------------------------------------
#define C_CAN1_IF1_MSK1_MSK15_0_Pos                           0                                                         /*!< C_CAN1 IF1_MSK1: MSK15_0 Position   */
#define C_CAN1_IF1_MSK1_MSK15_0_Msk                           (0x0000ffffUL << C_CAN1_IF1_MSK1_MSK15_0_Pos)             /*!< C_CAN1 IF1_MSK1: MSK15_0 Mask       */

// -------------------------------------  C_CAN1_IF1_MSK2  ----------------------------------------
#define C_CAN1_IF1_MSK2_MSK28_16_Pos                          0                                                         /*!< C_CAN1 IF1_MSK2: MSK28_16 Position  */
#define C_CAN1_IF1_MSK2_MSK28_16_Msk                          (0x00001fffUL << C_CAN1_IF1_MSK2_MSK28_16_Pos)            /*!< C_CAN1 IF1_MSK2: MSK28_16 Mask      */
#define C_CAN1_IF1_MSK2_MDIR_Pos                              14                                                        /*!< C_CAN1 IF1_MSK2: MDIR Position      */
#define C_CAN1_IF1_MSK2_MDIR_Msk                              (0x01UL << C_CAN1_IF1_MSK2_MDIR_Pos)                      /*!< C_CAN1 IF1_MSK2: MDIR Mask          */
#define C_CAN1_IF1_MSK2_MXTD_Pos                              15                                                        /*!< C_CAN1 IF1_MSK2: MXTD Position      */
#define C_CAN1_IF1_MSK2_MXTD_Msk                              (0x01UL << C_CAN1_IF1_MSK2_MXTD_Pos)                      /*!< C_CAN1 IF1_MSK2: MXTD Mask          */

// -------------------------------------  C_CAN1_IF1_ARB1  ----------------------------------------
#define C_CAN1_IF1_ARB1_ID15_0_Pos                            0                                                         /*!< C_CAN1 IF1_ARB1: ID15_0 Position    */
#define C_CAN1_IF1_ARB1_ID15_0_Msk                            (0x0000ffffUL << C_CAN1_IF1_ARB1_ID15_0_Pos)              /*!< C_CAN1 IF1_ARB1: ID15_0 Mask        */

// -------------------------------------  C_CAN1_IF1_ARB2  ----------------------------------------
#define C_CAN1_IF1_ARB2_ID28_16_Pos                           0                                                         /*!< C_CAN1 IF1_ARB2: ID28_16 Position   */
#define C_CAN1_IF1_ARB2_ID28_16_Msk                           (0x00001fffUL << C_CAN1_IF1_ARB2_ID28_16_Pos)             /*!< C_CAN1 IF1_ARB2: ID28_16 Mask       */
#define C_CAN1_IF1_ARB2_DIR_Pos                               13                                                        /*!< C_CAN1 IF1_ARB2: DIR Position       */
#define C_CAN1_IF1_ARB2_DIR_Msk                               (0x01UL << C_CAN1_IF1_ARB2_DIR_Pos)                       /*!< C_CAN1 IF1_ARB2: DIR Mask           */
#define C_CAN1_IF1_ARB2_XTD_Pos                               14                                                        /*!< C_CAN1 IF1_ARB2: XTD Position       */
#define C_CAN1_IF1_ARB2_XTD_Msk                               (0x01UL << C_CAN1_IF1_ARB2_XTD_Pos)                       /*!< C_CAN1 IF1_ARB2: XTD Mask           */
#define C_CAN1_IF1_ARB2_MSGVAL_Pos                            15                                                        /*!< C_CAN1 IF1_ARB2: MSGVAL Position    */
#define C_CAN1_IF1_ARB2_MSGVAL_Msk                            (0x01UL << C_CAN1_IF1_ARB2_MSGVAL_Pos)                    /*!< C_CAN1 IF1_ARB2: MSGVAL Mask        */

// ------------------------------------  C_CAN1_IF1_MCTRL  ----------------------------------------
#define C_CAN1_IF1_MCTRL_DLC3_0_Pos                           0                                                         /*!< C_CAN1 IF1_MCTRL: DLC3_0 Position   */
#define C_CAN1_IF1_MCTRL_DLC3_0_Msk                           (0x0fUL << C_CAN1_IF1_MCTRL_DLC3_0_Pos)                   /*!< C_CAN1 IF1_MCTRL: DLC3_0 Mask       */
#define C_CAN1_IF1_MCTRL_EOB_Pos                              7                                                         /*!< C_CAN1 IF1_MCTRL: EOB Position      */
#define C_CAN1_IF1_MCTRL_EOB_Msk                              (0x01UL << C_CAN1_IF1_MCTRL_EOB_Pos)                      /*!< C_CAN1 IF1_MCTRL: EOB Mask          */
#define C_CAN1_IF1_MCTRL_TXRQST_Pos                           8                                                         /*!< C_CAN1 IF1_MCTRL: TXRQST Position   */
#define C_CAN1_IF1_MCTRL_TXRQST_Msk                           (0x01UL << C_CAN1_IF1_MCTRL_TXRQST_Pos)                   /*!< C_CAN1 IF1_MCTRL: TXRQST Mask       */
#define C_CAN1_IF1_MCTRL_RMTEN_Pos                            9                                                         /*!< C_CAN1 IF1_MCTRL: RMTEN Position    */
#define C_CAN1_IF1_MCTRL_RMTEN_Msk                            (0x01UL << C_CAN1_IF1_MCTRL_RMTEN_Pos)                    /*!< C_CAN1 IF1_MCTRL: RMTEN Mask        */
#define C_CAN1_IF1_MCTRL_RXIE_Pos                             10                                                        /*!< C_CAN1 IF1_MCTRL: RXIE Position     */
#define C_CAN1_IF1_MCTRL_RXIE_Msk                             (0x01UL << C_CAN1_IF1_MCTRL_RXIE_Pos)                     /*!< C_CAN1 IF1_MCTRL: RXIE Mask         */
#define C_CAN1_IF1_MCTRL_TXIE_Pos                             11                                                        /*!< C_CAN1 IF1_MCTRL: TXIE Position     */
#define C_CAN1_IF1_MCTRL_TXIE_Msk                             (0x01UL << C_CAN1_IF1_MCTRL_TXIE_Pos)                     /*!< C_CAN1 IF1_MCTRL: TXIE Mask         */
#define C_CAN1_IF1_MCTRL_UMASK_Pos                            12                                                        /*!< C_CAN1 IF1_MCTRL: UMASK Position    */
#define C_CAN1_IF1_MCTRL_UMASK_Msk                            (0x01UL << C_CAN1_IF1_MCTRL_UMASK_Pos)                    /*!< C_CAN1 IF1_MCTRL: UMASK Mask        */
#define C_CAN1_IF1_MCTRL_INTPND_Pos                           13                                                        /*!< C_CAN1 IF1_MCTRL: INTPND Position   */
#define C_CAN1_IF1_MCTRL_INTPND_Msk                           (0x01UL << C_CAN1_IF1_MCTRL_INTPND_Pos)                   /*!< C_CAN1 IF1_MCTRL: INTPND Mask       */
#define C_CAN1_IF1_MCTRL_MSGLST_Pos                           14                                                        /*!< C_CAN1 IF1_MCTRL: MSGLST Position   */
#define C_CAN1_IF1_MCTRL_MSGLST_Msk                           (0x01UL << C_CAN1_IF1_MCTRL_MSGLST_Pos)                   /*!< C_CAN1 IF1_MCTRL: MSGLST Mask       */
#define C_CAN1_IF1_MCTRL_NEWDAT_Pos                           15                                                        /*!< C_CAN1 IF1_MCTRL: NEWDAT Position   */
#define C_CAN1_IF1_MCTRL_NEWDAT_Msk                           (0x01UL << C_CAN1_IF1_MCTRL_NEWDAT_Pos)                   /*!< C_CAN1 IF1_MCTRL: NEWDAT Mask       */

// -------------------------------------  C_CAN1_IF1_DA1  -----------------------------------------
#define C_CAN1_IF1_DA1_DATA0_Pos                              0                                                         /*!< C_CAN1 IF1_DA1: DATA0 Position      */
#define C_CAN1_IF1_DA1_DATA0_Msk                              (0x000000ffUL << C_CAN1_IF1_DA1_DATA0_Pos)                /*!< C_CAN1 IF1_DA1: DATA0 Mask          */
#define C_CAN1_IF1_DA1_DATA1_Pos                              8                                                         /*!< C_CAN1 IF1_DA1: DATA1 Position      */
#define C_CAN1_IF1_DA1_DATA1_Msk                              (0x000000ffUL << C_CAN1_IF1_DA1_DATA1_Pos)                /*!< C_CAN1 IF1_DA1: DATA1 Mask          */

// -------------------------------------  C_CAN1_IF1_DA2  -----------------------------------------
#define C_CAN1_IF1_DA2_DATA2_Pos                              0                                                         /*!< C_CAN1 IF1_DA2: DATA2 Position      */
#define C_CAN1_IF1_DA2_DATA2_Msk                              (0x000000ffUL << C_CAN1_IF1_DA2_DATA2_Pos)                /*!< C_CAN1 IF1_DA2: DATA2 Mask          */
#define C_CAN1_IF1_DA2_DATA3_Pos                              8                                                         /*!< C_CAN1 IF1_DA2: DATA3 Position      */
#define C_CAN1_IF1_DA2_DATA3_Msk                              (0x000000ffUL << C_CAN1_IF1_DA2_DATA3_Pos)                /*!< C_CAN1 IF1_DA2: DATA3 Mask          */

// -------------------------------------  C_CAN1_IF1_DB1  -----------------------------------------
#define C_CAN1_IF1_DB1_DATA4_Pos                              0                                                         /*!< C_CAN1 IF1_DB1: DATA4 Position      */
#define C_CAN1_IF1_DB1_DATA4_Msk                              (0x000000ffUL << C_CAN1_IF1_DB1_DATA4_Pos)                /*!< C_CAN1 IF1_DB1: DATA4 Mask          */
#define C_CAN1_IF1_DB1_DATA5_Pos                              8                                                         /*!< C_CAN1 IF1_DB1: DATA5 Position      */
#define C_CAN1_IF1_DB1_DATA5_Msk                              (0x000000ffUL << C_CAN1_IF1_DB1_DATA5_Pos)                /*!< C_CAN1 IF1_DB1: DATA5 Mask          */

// -------------------------------------  C_CAN1_IF1_DB2  -----------------------------------------
#define C_CAN1_IF1_DB2_DATA6_Pos                              0                                                         /*!< C_CAN1 IF1_DB2: DATA6 Position      */
#define C_CAN1_IF1_DB2_DATA6_Msk                              (0x000000ffUL << C_CAN1_IF1_DB2_DATA6_Pos)                /*!< C_CAN1 IF1_DB2: DATA6 Mask          */
#define C_CAN1_IF1_DB2_DATA7_Pos                              8                                                         /*!< C_CAN1 IF1_DB2: DATA7 Position      */
#define C_CAN1_IF1_DB2_DATA7_Msk                              (0x000000ffUL << C_CAN1_IF1_DB2_DATA7_Pos)                /*!< C_CAN1 IF1_DB2: DATA7 Mask          */

// ------------------------------------  C_CAN1_IF2_CMDREQ  ---------------------------------------
#define C_CAN1_IF2_CMDREQ_MESSNUM_Pos                         0                                                         /*!< C_CAN1 IF2_CMDREQ: MESSNUM Position */
#define C_CAN1_IF2_CMDREQ_MESSNUM_Msk                         (0x3fUL << C_CAN1_IF2_CMDREQ_MESSNUM_Pos)                 /*!< C_CAN1 IF2_CMDREQ: MESSNUM Mask     */
#define C_CAN1_IF2_CMDREQ_BUSY_Pos                            15                                                        /*!< C_CAN1 IF2_CMDREQ: BUSY Position    */
#define C_CAN1_IF2_CMDREQ_BUSY_Msk                            (0x01UL << C_CAN1_IF2_CMDREQ_BUSY_Pos)                    /*!< C_CAN1 IF2_CMDREQ: BUSY Mask        */

// -----------------------------------  C_CAN1_IF2_CMDMSK_W  --------------------------------------
#define C_CAN1_IF2_CMDMSK_W_DATA_B_Pos                        0                                                         /*!< C_CAN1 IF2_CMDMSK_W: DATA_B Position */
#define C_CAN1_IF2_CMDMSK_W_DATA_B_Msk                        (0x01UL << C_CAN1_IF2_CMDMSK_W_DATA_B_Pos)                /*!< C_CAN1 IF2_CMDMSK_W: DATA_B Mask    */
#define C_CAN1_IF2_CMDMSK_W_DATA_A_Pos                        1                                                         /*!< C_CAN1 IF2_CMDMSK_W: DATA_A Position */
#define C_CAN1_IF2_CMDMSK_W_DATA_A_Msk                        (0x01UL << C_CAN1_IF2_CMDMSK_W_DATA_A_Pos)                /*!< C_CAN1 IF2_CMDMSK_W: DATA_A Mask    */
#define C_CAN1_IF2_CMDMSK_W_TXRQST_Pos                        2                                                         /*!< C_CAN1 IF2_CMDMSK_W: TXRQST Position */
#define C_CAN1_IF2_CMDMSK_W_TXRQST_Msk                        (0x01UL << C_CAN1_IF2_CMDMSK_W_TXRQST_Pos)                /*!< C_CAN1 IF2_CMDMSK_W: TXRQST Mask    */
#define C_CAN1_IF2_CMDMSK_W_CLRINTPND_Pos                     3                                                         /*!< C_CAN1 IF2_CMDMSK_W: CLRINTPND Position */
#define C_CAN1_IF2_CMDMSK_W_CLRINTPND_Msk                     (0x01UL << C_CAN1_IF2_CMDMSK_W_CLRINTPND_Pos)             /*!< C_CAN1 IF2_CMDMSK_W: CLRINTPND Mask */
#define C_CAN1_IF2_CMDMSK_W_CTRL_Pos                          4                                                         /*!< C_CAN1 IF2_CMDMSK_W: CTRL Position  */
#define C_CAN1_IF2_CMDMSK_W_CTRL_Msk                          (0x01UL << C_CAN1_IF2_CMDMSK_W_CTRL_Pos)                  /*!< C_CAN1 IF2_CMDMSK_W: CTRL Mask      */
#define C_CAN1_IF2_CMDMSK_W_ARB_Pos                           5                                                         /*!< C_CAN1 IF2_CMDMSK_W: ARB Position   */
#define C_CAN1_IF2_CMDMSK_W_ARB_Msk                           (0x01UL << C_CAN1_IF2_CMDMSK_W_ARB_Pos)                   /*!< C_CAN1 IF2_CMDMSK_W: ARB Mask       */
#define C_CAN1_IF2_CMDMSK_W_MASK_Pos                          6                                                         /*!< C_CAN1 IF2_CMDMSK_W: MASK Position  */
#define C_CAN1_IF2_CMDMSK_W_MASK_Msk                          (0x01UL << C_CAN1_IF2_CMDMSK_W_MASK_Pos)                  /*!< C_CAN1 IF2_CMDMSK_W: MASK Mask      */
#define C_CAN1_IF2_CMDMSK_W_WR_RD_Pos                         7                                                         /*!< C_CAN1 IF2_CMDMSK_W: WR_RD Position */
#define C_CAN1_IF2_CMDMSK_W_WR_RD_Msk                         (0x01UL << C_CAN1_IF2_CMDMSK_W_WR_RD_Pos)                 /*!< C_CAN1 IF2_CMDMSK_W: WR_RD Mask     */

// -----------------------------------  C_CAN1_IF2_CMDMSK_R  --------------------------------------
#define C_CAN1_IF2_CMDMSK_R_DATA_B_Pos                        0                                                         /*!< C_CAN1 IF2_CMDMSK_R: DATA_B Position */
#define C_CAN1_IF2_CMDMSK_R_DATA_B_Msk                        (0x01UL << C_CAN1_IF2_CMDMSK_R_DATA_B_Pos)                /*!< C_CAN1 IF2_CMDMSK_R: DATA_B Mask    */
#define C_CAN1_IF2_CMDMSK_R_DATA_A_Pos                        1                                                         /*!< C_CAN1 IF2_CMDMSK_R: DATA_A Position */
#define C_CAN1_IF2_CMDMSK_R_DATA_A_Msk                        (0x01UL << C_CAN1_IF2_CMDMSK_R_DATA_A_Pos)                /*!< C_CAN1 IF2_CMDMSK_R: DATA_A Mask    */
#define C_CAN1_IF2_CMDMSK_R_NEWDAT_Pos                        2                                                         /*!< C_CAN1 IF2_CMDMSK_R: NEWDAT Position */
#define C_CAN1_IF2_CMDMSK_R_NEWDAT_Msk                        (0x01UL << C_CAN1_IF2_CMDMSK_R_NEWDAT_Pos)                /*!< C_CAN1 IF2_CMDMSK_R: NEWDAT Mask    */
#define C_CAN1_IF2_CMDMSK_R_CLRINTPND_Pos                     3                                                         /*!< C_CAN1 IF2_CMDMSK_R: CLRINTPND Position */
#define C_CAN1_IF2_CMDMSK_R_CLRINTPND_Msk                     (0x01UL << C_CAN1_IF2_CMDMSK_R_CLRINTPND_Pos)             /*!< C_CAN1 IF2_CMDMSK_R: CLRINTPND Mask */
#define C_CAN1_IF2_CMDMSK_R_CTRL_Pos                          4                                                         /*!< C_CAN1 IF2_CMDMSK_R: CTRL Position  */
#define C_CAN1_IF2_CMDMSK_R_CTRL_Msk                          (0x01UL << C_CAN1_IF2_CMDMSK_R_CTRL_Pos)                  /*!< C_CAN1 IF2_CMDMSK_R: CTRL Mask      */
#define C_CAN1_IF2_CMDMSK_R_ARB_Pos                           5                                                         /*!< C_CAN1 IF2_CMDMSK_R: ARB Position   */
#define C_CAN1_IF2_CMDMSK_R_ARB_Msk                           (0x01UL << C_CAN1_IF2_CMDMSK_R_ARB_Pos)                   /*!< C_CAN1 IF2_CMDMSK_R: ARB Mask       */
#define C_CAN1_IF2_CMDMSK_R_MASK_Pos                          6                                                         /*!< C_CAN1 IF2_CMDMSK_R: MASK Position  */
#define C_CAN1_IF2_CMDMSK_R_MASK_Msk                          (0x01UL << C_CAN1_IF2_CMDMSK_R_MASK_Pos)                  /*!< C_CAN1 IF2_CMDMSK_R: MASK Mask      */
#define C_CAN1_IF2_CMDMSK_R_WR_RD_Pos                         7                                                         /*!< C_CAN1 IF2_CMDMSK_R: WR_RD Position */
#define C_CAN1_IF2_CMDMSK_R_WR_RD_Msk                         (0x01UL << C_CAN1_IF2_CMDMSK_R_WR_RD_Pos)                 /*!< C_CAN1 IF2_CMDMSK_R: WR_RD Mask     */

// -------------------------------------  C_CAN1_IF2_MSK1  ----------------------------------------
#define C_CAN1_IF2_MSK1_MSK15_0_Pos                           0                                                         /*!< C_CAN1 IF2_MSK1: MSK15_0 Position   */
#define C_CAN1_IF2_MSK1_MSK15_0_Msk                           (0x0000ffffUL << C_CAN1_IF2_MSK1_MSK15_0_Pos)             /*!< C_CAN1 IF2_MSK1: MSK15_0 Mask       */

// -------------------------------------  C_CAN1_IF2_MSK2  ----------------------------------------
#define C_CAN1_IF2_MSK2_MSK28_16_Pos                          0                                                         /*!< C_CAN1 IF2_MSK2: MSK28_16 Position  */
#define C_CAN1_IF2_MSK2_MSK28_16_Msk                          (0x00001fffUL << C_CAN1_IF2_MSK2_MSK28_16_Pos)            /*!< C_CAN1 IF2_MSK2: MSK28_16 Mask      */
#define C_CAN1_IF2_MSK2_MDIR_Pos                              14                                                        /*!< C_CAN1 IF2_MSK2: MDIR Position      */
#define C_CAN1_IF2_MSK2_MDIR_Msk                              (0x01UL << C_CAN1_IF2_MSK2_MDIR_Pos)                      /*!< C_CAN1 IF2_MSK2: MDIR Mask          */
#define C_CAN1_IF2_MSK2_MXTD_Pos                              15                                                        /*!< C_CAN1 IF2_MSK2: MXTD Position      */
#define C_CAN1_IF2_MSK2_MXTD_Msk                              (0x01UL << C_CAN1_IF2_MSK2_MXTD_Pos)                      /*!< C_CAN1 IF2_MSK2: MXTD Mask          */

// -------------------------------------  C_CAN1_IF2_ARB1  ----------------------------------------
#define C_CAN1_IF2_ARB1_ID15_0_Pos                            0                                                         /*!< C_CAN1 IF2_ARB1: ID15_0 Position    */
#define C_CAN1_IF2_ARB1_ID15_0_Msk                            (0x0000ffffUL << C_CAN1_IF2_ARB1_ID15_0_Pos)              /*!< C_CAN1 IF2_ARB1: ID15_0 Mask        */

// -------------------------------------  C_CAN1_IF2_ARB2  ----------------------------------------
#define C_CAN1_IF2_ARB2_ID28_16_Pos                           0                                                         /*!< C_CAN1 IF2_ARB2: ID28_16 Position   */
#define C_CAN1_IF2_ARB2_ID28_16_Msk                           (0x00001fffUL << C_CAN1_IF2_ARB2_ID28_16_Pos)             /*!< C_CAN1 IF2_ARB2: ID28_16 Mask       */
#define C_CAN1_IF2_ARB2_DIR_Pos                               13                                                        /*!< C_CAN1 IF2_ARB2: DIR Position       */
#define C_CAN1_IF2_ARB2_DIR_Msk                               (0x01UL << C_CAN1_IF2_ARB2_DIR_Pos)                       /*!< C_CAN1 IF2_ARB2: DIR Mask           */
#define C_CAN1_IF2_ARB2_XTD_Pos                               14                                                        /*!< C_CAN1 IF2_ARB2: XTD Position       */
#define C_CAN1_IF2_ARB2_XTD_Msk                               (0x01UL << C_CAN1_IF2_ARB2_XTD_Pos)                       /*!< C_CAN1 IF2_ARB2: XTD Mask           */
#define C_CAN1_IF2_ARB2_MSGVAL_Pos                            15                                                        /*!< C_CAN1 IF2_ARB2: MSGVAL Position    */
#define C_CAN1_IF2_ARB2_MSGVAL_Msk                            (0x01UL << C_CAN1_IF2_ARB2_MSGVAL_Pos)                    /*!< C_CAN1 IF2_ARB2: MSGVAL Mask        */

// ------------------------------------  C_CAN1_IF2_MCTRL  ----------------------------------------
#define C_CAN1_IF2_MCTRL_DLC3_0_Pos                           0                                                         /*!< C_CAN1 IF2_MCTRL: DLC3_0 Position   */
#define C_CAN1_IF2_MCTRL_DLC3_0_Msk                           (0x0fUL << C_CAN1_IF2_MCTRL_DLC3_0_Pos)                   /*!< C_CAN1 IF2_MCTRL: DLC3_0 Mask       */
#define C_CAN1_IF2_MCTRL_EOB_Pos                              7                                                         /*!< C_CAN1 IF2_MCTRL: EOB Position      */
#define C_CAN1_IF2_MCTRL_EOB_Msk                              (0x01UL << C_CAN1_IF2_MCTRL_EOB_Pos)                      /*!< C_CAN1 IF2_MCTRL: EOB Mask          */
#define C_CAN1_IF2_MCTRL_TXRQST_Pos                           8                                                         /*!< C_CAN1 IF2_MCTRL: TXRQST Position   */
#define C_CAN1_IF2_MCTRL_TXRQST_Msk                           (0x01UL << C_CAN1_IF2_MCTRL_TXRQST_Pos)                   /*!< C_CAN1 IF2_MCTRL: TXRQST Mask       */
#define C_CAN1_IF2_MCTRL_RMTEN_Pos                            9                                                         /*!< C_CAN1 IF2_MCTRL: RMTEN Position    */
#define C_CAN1_IF2_MCTRL_RMTEN_Msk                            (0x01UL << C_CAN1_IF2_MCTRL_RMTEN_Pos)                    /*!< C_CAN1 IF2_MCTRL: RMTEN Mask        */
#define C_CAN1_IF2_MCTRL_RXIE_Pos                             10                                                        /*!< C_CAN1 IF2_MCTRL: RXIE Position     */
#define C_CAN1_IF2_MCTRL_RXIE_Msk                             (0x01UL << C_CAN1_IF2_MCTRL_RXIE_Pos)                     /*!< C_CAN1 IF2_MCTRL: RXIE Mask         */
#define C_CAN1_IF2_MCTRL_TXIE_Pos                             11                                                        /*!< C_CAN1 IF2_MCTRL: TXIE Position     */
#define C_CAN1_IF2_MCTRL_TXIE_Msk                             (0x01UL << C_CAN1_IF2_MCTRL_TXIE_Pos)                     /*!< C_CAN1 IF2_MCTRL: TXIE Mask         */
#define C_CAN1_IF2_MCTRL_UMASK_Pos                            12                                                        /*!< C_CAN1 IF2_MCTRL: UMASK Position    */
#define C_CAN1_IF2_MCTRL_UMASK_Msk                            (0x01UL << C_CAN1_IF2_MCTRL_UMASK_Pos)                    /*!< C_CAN1 IF2_MCTRL: UMASK Mask        */
#define C_CAN1_IF2_MCTRL_INTPND_Pos                           13                                                        /*!< C_CAN1 IF2_MCTRL: INTPND Position   */
#define C_CAN1_IF2_MCTRL_INTPND_Msk                           (0x01UL << C_CAN1_IF2_MCTRL_INTPND_Pos)                   /*!< C_CAN1 IF2_MCTRL: INTPND Mask       */
#define C_CAN1_IF2_MCTRL_MSGLST_Pos                           14                                                        /*!< C_CAN1 IF2_MCTRL: MSGLST Position   */
#define C_CAN1_IF2_MCTRL_MSGLST_Msk                           (0x01UL << C_CAN1_IF2_MCTRL_MSGLST_Pos)                   /*!< C_CAN1 IF2_MCTRL: MSGLST Mask       */
#define C_CAN1_IF2_MCTRL_NEWDAT_Pos                           15                                                        /*!< C_CAN1 IF2_MCTRL: NEWDAT Position   */
#define C_CAN1_IF2_MCTRL_NEWDAT_Msk                           (0x01UL << C_CAN1_IF2_MCTRL_NEWDAT_Pos)                   /*!< C_CAN1 IF2_MCTRL: NEWDAT Mask       */

// -------------------------------------  C_CAN1_IF2_DA1  -----------------------------------------
#define C_CAN1_IF2_DA1_DATA0_Pos                              0                                                         /*!< C_CAN1 IF2_DA1: DATA0 Position      */
#define C_CAN1_IF2_DA1_DATA0_Msk                              (0x000000ffUL << C_CAN1_IF2_DA1_DATA0_Pos)                /*!< C_CAN1 IF2_DA1: DATA0 Mask          */
#define C_CAN1_IF2_DA1_DATA1_Pos                              8                                                         /*!< C_CAN1 IF2_DA1: DATA1 Position      */
#define C_CAN1_IF2_DA1_DATA1_Msk                              (0x000000ffUL << C_CAN1_IF2_DA1_DATA1_Pos)                /*!< C_CAN1 IF2_DA1: DATA1 Mask          */

// -------------------------------------  C_CAN1_IF2_DA2  -----------------------------------------
#define C_CAN1_IF2_DA2_DATA2_Pos                              0                                                         /*!< C_CAN1 IF2_DA2: DATA2 Position      */
#define C_CAN1_IF2_DA2_DATA2_Msk                              (0x000000ffUL << C_CAN1_IF2_DA2_DATA2_Pos)                /*!< C_CAN1 IF2_DA2: DATA2 Mask          */
#define C_CAN1_IF2_DA2_DATA3_Pos                              8                                                         /*!< C_CAN1 IF2_DA2: DATA3 Position      */
#define C_CAN1_IF2_DA2_DATA3_Msk                              (0x000000ffUL << C_CAN1_IF2_DA2_DATA3_Pos)                /*!< C_CAN1 IF2_DA2: DATA3 Mask          */

// -------------------------------------  C_CAN1_IF2_DB1  -----------------------------------------
#define C_CAN1_IF2_DB1_DATA4_Pos                              0                                                         /*!< C_CAN1 IF2_DB1: DATA4 Position      */
#define C_CAN1_IF2_DB1_DATA4_Msk                              (0x000000ffUL << C_CAN1_IF2_DB1_DATA4_Pos)                /*!< C_CAN1 IF2_DB1: DATA4 Mask          */
#define C_CAN1_IF2_DB1_DATA5_Pos                              8                                                         /*!< C_CAN1 IF2_DB1: DATA5 Position      */
#define C_CAN1_IF2_DB1_DATA5_Msk                              (0x000000ffUL << C_CAN1_IF2_DB1_DATA5_Pos)                /*!< C_CAN1 IF2_DB1: DATA5 Mask          */

// -------------------------------------  C_CAN1_IF2_DB2  -----------------------------------------
#define C_CAN1_IF2_DB2_DATA6_Pos                              0                                                         /*!< C_CAN1 IF2_DB2: DATA6 Position      */
#define C_CAN1_IF2_DB2_DATA6_Msk                              (0x000000ffUL << C_CAN1_IF2_DB2_DATA6_Pos)                /*!< C_CAN1 IF2_DB2: DATA6 Mask          */
#define C_CAN1_IF2_DB2_DATA7_Pos                              8                                                         /*!< C_CAN1 IF2_DB2: DATA7 Position      */
#define C_CAN1_IF2_DB2_DATA7_Msk                              (0x000000ffUL << C_CAN1_IF2_DB2_DATA7_Pos)                /*!< C_CAN1 IF2_DB2: DATA7 Mask          */

// --------------------------------------  C_CAN1_TXREQ1  -----------------------------------------
#define C_CAN1_TXREQ1_TXRQST16_1_Pos                          0                                                         /*!< C_CAN1 TXREQ1: TXRQST16_1 Position  */
#define C_CAN1_TXREQ1_TXRQST16_1_Msk                          (0x0000ffffUL << C_CAN1_TXREQ1_TXRQST16_1_Pos)            /*!< C_CAN1 TXREQ1: TXRQST16_1 Mask      */

// --------------------------------------  C_CAN1_TXREQ2  -----------------------------------------
#define C_CAN1_TXREQ2_TXRQST32_17_Pos                         0                                                         /*!< C_CAN1 TXREQ2: TXRQST32_17 Position */
#define C_CAN1_TXREQ2_TXRQST32_17_Msk                         (0x0000ffffUL << C_CAN1_TXREQ2_TXRQST32_17_Pos)           /*!< C_CAN1 TXREQ2: TXRQST32_17 Mask     */

// ---------------------------------------  C_CAN1_ND1  -------------------------------------------
#define C_CAN1_ND1_NEWDAT16_1_Pos                             0                                                         /*!< C_CAN1 ND1: NEWDAT16_1 Position     */
#define C_CAN1_ND1_NEWDAT16_1_Msk                             (0x0000ffffUL << C_CAN1_ND1_NEWDAT16_1_Pos)               /*!< C_CAN1 ND1: NEWDAT16_1 Mask         */

// ---------------------------------------  C_CAN1_ND2  -------------------------------------------
#define C_CAN1_ND2_NEWDAT32_17_Pos                            0                                                         /*!< C_CAN1 ND2: NEWDAT32_17 Position    */
#define C_CAN1_ND2_NEWDAT32_17_Msk                            (0x0000ffffUL << C_CAN1_ND2_NEWDAT32_17_Pos)              /*!< C_CAN1 ND2: NEWDAT32_17 Mask        */

// ---------------------------------------  C_CAN1_IR1  -------------------------------------------
#define C_CAN1_IR1_INTPND16_1_Pos                             0                                                         /*!< C_CAN1 IR1: INTPND16_1 Position     */
#define C_CAN1_IR1_INTPND16_1_Msk                             (0x0000ffffUL << C_CAN1_IR1_INTPND16_1_Pos)               /*!< C_CAN1 IR1: INTPND16_1 Mask         */

// ---------------------------------------  C_CAN1_IR2  -------------------------------------------
#define C_CAN1_IR2_INTPND32_17_Pos                            0                                                         /*!< C_CAN1 IR2: INTPND32_17 Position    */
#define C_CAN1_IR2_INTPND32_17_Msk                            (0x0000ffffUL << C_CAN1_IR2_INTPND32_17_Pos)              /*!< C_CAN1 IR2: INTPND32_17 Mask        */

// --------------------------------------  C_CAN1_MSGV1  ------------------------------------------
#define C_CAN1_MSGV1_MSGVAL16_1_Pos                           0                                                         /*!< C_CAN1 MSGV1: MSGVAL16_1 Position   */
#define C_CAN1_MSGV1_MSGVAL16_1_Msk                           (0x0000ffffUL << C_CAN1_MSGV1_MSGVAL16_1_Pos)             /*!< C_CAN1 MSGV1: MSGVAL16_1 Mask       */

// --------------------------------------  C_CAN1_MSGV2  ------------------------------------------
#define C_CAN1_MSGV2_MSGVAL32_17_Pos                          0                                                         /*!< C_CAN1 MSGV2: MSGVAL32_17 Position  */
#define C_CAN1_MSGV2_MSGVAL32_17_Msk                          (0x0000ffffUL << C_CAN1_MSGV2_MSGVAL32_17_Pos)            /*!< C_CAN1 MSGV2: MSGVAL32_17 Mask      */

// --------------------------------------  C_CAN1_CLKDIV  -----------------------------------------
#define C_CAN1_CLKDIV_CLKDIVVAL_Pos                           0                                                         /*!< C_CAN1 CLKDIV: CLKDIVVAL Position   */
#define C_CAN1_CLKDIV_CLKDIVVAL_Msk                           (0x0fUL << C_CAN1_CLKDIV_CLKDIVVAL_Pos)                   /*!< C_CAN1 CLKDIV: CLKDIVVAL Mask       */


// ------------------------------------------------------------------------------------------------
// -----                                RITIMER Position & Mask                               -----
// ------------------------------------------------------------------------------------------------


// -------------------------------------  RITIMER_COMPVAL  ----------------------------------------
#define RITIMER_COMPVAL_RICOMP_Pos                            0                                                         /*!< RITIMER COMPVAL: RICOMP Position    */
#define RITIMER_COMPVAL_RICOMP_Msk                            (0xffffffffUL << RITIMER_COMPVAL_RICOMP_Pos)              /*!< RITIMER COMPVAL: RICOMP Mask        */

// --------------------------------------  RITIMER_MASK  ------------------------------------------
#define RITIMER_MASK_RIMASK_Pos                               0                                                         /*!< RITIMER MASK: RIMASK Position       */
#define RITIMER_MASK_RIMASK_Msk                               (0xffffffffUL << RITIMER_MASK_RIMASK_Pos)                 /*!< RITIMER MASK: RIMASK Mask           */

// --------------------------------------  RITIMER_CTRL  ------------------------------------------
#define RITIMER_CTRL_RITINT_Pos                               0                                                         /*!< RITIMER CTRL: RITINT Position       */
#define RITIMER_CTRL_RITINT_Msk                               (0x01UL << RITIMER_CTRL_RITINT_Pos)                       /*!< RITIMER CTRL: RITINT Mask           */
#define RITIMER_CTRL_RITENCLR_Pos                             1                                                         /*!< RITIMER CTRL: RITENCLR Position     */
#define RITIMER_CTRL_RITENCLR_Msk                             (0x01UL << RITIMER_CTRL_RITENCLR_Pos)                     /*!< RITIMER CTRL: RITENCLR Mask         */
#define RITIMER_CTRL_RITENBR_Pos                              2                                                         /*!< RITIMER CTRL: RITENBR Position      */
#define RITIMER_CTRL_RITENBR_Msk                              (0x01UL << RITIMER_CTRL_RITENBR_Pos)                      /*!< RITIMER CTRL: RITENBR Mask          */
#define RITIMER_CTRL_RITEN_Pos                                3                                                         /*!< RITIMER CTRL: RITEN Position        */
#define RITIMER_CTRL_RITEN_Msk                                (0x01UL << RITIMER_CTRL_RITEN_Pos)                        /*!< RITIMER CTRL: RITEN Mask            */

// -------------------------------------  RITIMER_COUNTER  ----------------------------------------
#define RITIMER_COUNTER_RICOUNTER_Pos                         0                                                         /*!< RITIMER COUNTER: RICOUNTER Position */
#define RITIMER_COUNTER_RICOUNTER_Msk                         (0xffffffffUL << RITIMER_COUNTER_RICOUNTER_Pos)           /*!< RITIMER COUNTER: RICOUNTER Mask     */


// ------------------------------------------------------------------------------------------------
// -----                                  QEI Position & Mask                                 -----
// ------------------------------------------------------------------------------------------------


// -----------------------------------------  QEI_CON  --------------------------------------------
#define QEI_CON_RESP_Pos                                      0                                                         /*!< QEI CON: RESP Position              */
#define QEI_CON_RESP_Msk                                      (0x01UL << QEI_CON_RESP_Pos)                              /*!< QEI CON: RESP Mask                  */
#define QEI_CON_RESPI_Pos                                     1                                                         /*!< QEI CON: RESPI Position             */
#define QEI_CON_RESPI_Msk                                     (0x01UL << QEI_CON_RESPI_Pos)                             /*!< QEI CON: RESPI Mask                 */
#define QEI_CON_RESV_Pos                                      2                                                         /*!< QEI CON: RESV Position              */
#define QEI_CON_RESV_Msk                                      (0x01UL << QEI_CON_RESV_Pos)                              /*!< QEI CON: RESV Mask                  */
#define QEI_CON_RESI_Pos                                      3                                                         /*!< QEI CON: RESI Position              */
#define QEI_CON_RESI_Msk                                      (0x01UL << QEI_CON_RESI_Pos)                              /*!< QEI CON: RESI Mask                  */

// ----------------------------------------  QEI_STAT  --------------------------------------------
#define QEI_STAT_DIR_Pos                                      0                                                         /*!< QEI STAT: DIR Position              */
#define QEI_STAT_DIR_Msk                                      (0x01UL << QEI_STAT_DIR_Pos)                              /*!< QEI STAT: DIR Mask                  */

// ----------------------------------------  QEI_CONF  --------------------------------------------
#define QEI_CONF_DIRINV_Pos                                   0                                                         /*!< QEI CONF: DIRINV Position           */
#define QEI_CONF_DIRINV_Msk                                   (0x01UL << QEI_CONF_DIRINV_Pos)                           /*!< QEI CONF: DIRINV Mask               */
#define QEI_CONF_SIGMODE_Pos                                  1                                                         /*!< QEI CONF: SIGMODE Position          */
#define QEI_CONF_SIGMODE_Msk                                  (0x01UL << QEI_CONF_SIGMODE_Pos)                          /*!< QEI CONF: SIGMODE Mask              */
#define QEI_CONF_CAPMODE_Pos                                  2                                                         /*!< QEI CONF: CAPMODE Position          */
#define QEI_CONF_CAPMODE_Msk                                  (0x01UL << QEI_CONF_CAPMODE_Pos)                          /*!< QEI CONF: CAPMODE Mask              */
#define QEI_CONF_INVINX_Pos                                   3                                                         /*!< QEI CONF: INVINX Position           */
#define QEI_CONF_INVINX_Msk                                   (0x01UL << QEI_CONF_INVINX_Pos)                           /*!< QEI CONF: INVINX Mask               */
#define QEI_CONF_CRESPI_Pos                                   4                                                         /*!< QEI CONF: CRESPI Position           */
#define QEI_CONF_CRESPI_Msk                                   (0x01UL << QEI_CONF_CRESPI_Pos)                           /*!< QEI CONF: CRESPI Mask               */
#define QEI_CONF_INXGATE_Pos                                  16                                                        /*!< QEI CONF: INXGATE Position          */
#define QEI_CONF_INXGATE_Msk                                  (0x0fUL << QEI_CONF_INXGATE_Pos)                          /*!< QEI CONF: INXGATE Mask              */

// -----------------------------------------  QEI_POS  --------------------------------------------
#define QEI_POS_POS_Pos                                       0                                                         /*!< QEI POS: POS Position               */
#define QEI_POS_POS_Msk                                       (0xffffffffUL << QEI_POS_POS_Pos)                         /*!< QEI POS: POS Mask                   */

// ---------------------------------------  QEI_MAXPOS  -------------------------------------------
#define QEI_MAXPOS_MAXPOS_Pos                                 0                                                         /*!< QEI MAXPOS: MAXPOS Position         */
#define QEI_MAXPOS_MAXPOS_Msk                                 (0xffffffffUL << QEI_MAXPOS_MAXPOS_Pos)                   /*!< QEI MAXPOS: MAXPOS Mask             */

// ---------------------------------------  QEI_CMPOS0  -------------------------------------------
#define QEI_CMPOS0_PCMP0_Pos                                  0                                                         /*!< QEI CMPOS0: PCMP0 Position          */
#define QEI_CMPOS0_PCMP0_Msk                                  (0xffffffffUL << QEI_CMPOS0_PCMP0_Pos)                    /*!< QEI CMPOS0: PCMP0 Mask              */

// ---------------------------------------  QEI_CMPOS1  -------------------------------------------
#define QEI_CMPOS1_PCMP1_Pos                                  0                                                         /*!< QEI CMPOS1: PCMP1 Position          */
#define QEI_CMPOS1_PCMP1_Msk                                  (0xffffffffUL << QEI_CMPOS1_PCMP1_Pos)                    /*!< QEI CMPOS1: PCMP1 Mask              */

// ---------------------------------------  QEI_CMPOS2  -------------------------------------------
#define QEI_CMPOS2_PCMP2_Pos                                  0                                                         /*!< QEI CMPOS2: PCMP2 Position          */
#define QEI_CMPOS2_PCMP2_Msk                                  (0xffffffffUL << QEI_CMPOS2_PCMP2_Pos)                    /*!< QEI CMPOS2: PCMP2 Mask              */

// ---------------------------------------  QEI_INXCNT  -------------------------------------------
#define QEI_INXCNT_ENCPOS_Pos                                 0                                                         /*!< QEI INXCNT: ENCPOS Position         */
#define QEI_INXCNT_ENCPOS_Msk                                 (0xffffffffUL << QEI_INXCNT_ENCPOS_Pos)                   /*!< QEI INXCNT: ENCPOS Mask             */

// ---------------------------------------  QEI_INXCMP0  ------------------------------------------
#define QEI_INXCMP0_ICMP0_Pos                                 0                                                         /*!< QEI INXCMP0: ICMP0 Position         */
#define QEI_INXCMP0_ICMP0_Msk                                 (0xffffffffUL << QEI_INXCMP0_ICMP0_Pos)                   /*!< QEI INXCMP0: ICMP0 Mask             */

// ----------------------------------------  QEI_LOAD  --------------------------------------------
#define QEI_LOAD_VELLOAD_Pos                                  0                                                         /*!< QEI LOAD: VELLOAD Position          */
#define QEI_LOAD_VELLOAD_Msk                                  (0xffffffffUL << QEI_LOAD_VELLOAD_Pos)                    /*!< QEI LOAD: VELLOAD Mask              */

// ----------------------------------------  QEI_TIME  --------------------------------------------
#define QEI_TIME_VELVAL_Pos                                   0                                                         /*!< QEI TIME: VELVAL Position           */
#define QEI_TIME_VELVAL_Msk                                   (0xffffffffUL << QEI_TIME_VELVAL_Pos)                     /*!< QEI TIME: VELVAL Mask               */

// -----------------------------------------  QEI_VEL  --------------------------------------------
#define QEI_VEL_VELPC_Pos                                     0                                                         /*!< QEI VEL: VELPC Position             */
#define QEI_VEL_VELPC_Msk                                     (0xffffffffUL << QEI_VEL_VELPC_Pos)                       /*!< QEI VEL: VELPC Mask                 */

// -----------------------------------------  QEI_CAP  --------------------------------------------
#define QEI_CAP_VELCAP_Pos                                    0                                                         /*!< QEI CAP: VELCAP Position            */
#define QEI_CAP_VELCAP_Msk                                    (0xffffffffUL << QEI_CAP_VELCAP_Pos)                      /*!< QEI CAP: VELCAP Mask                */

// ---------------------------------------  QEI_VELCOMP  ------------------------------------------
#define QEI_VELCOMP_VELCMP_Pos                                0                                                         /*!< QEI VELCOMP: VELCMP Position        */
#define QEI_VELCOMP_VELCMP_Msk                                (0xffffffffUL << QEI_VELCOMP_VELCMP_Pos)                  /*!< QEI VELCOMP: VELCMP Mask            */

// --------------------------------------  QEI_FILTERPHA  -----------------------------------------
#define QEI_FILTERPHA_FILTA_Pos                               0                                                         /*!< QEI FILTERPHA: FILTA Position       */
#define QEI_FILTERPHA_FILTA_Msk                               (0xffffffffUL << QEI_FILTERPHA_FILTA_Pos)                 /*!< QEI FILTERPHA: FILTA Mask           */

// --------------------------------------  QEI_FILTERPHB  -----------------------------------------
#define QEI_FILTERPHB_FILTB_Pos                               0                                                         /*!< QEI FILTERPHB: FILTB Position       */
#define QEI_FILTERPHB_FILTB_Msk                               (0xffffffffUL << QEI_FILTERPHB_FILTB_Pos)                 /*!< QEI FILTERPHB: FILTB Mask           */

// --------------------------------------  QEI_FILTERINX  -----------------------------------------
#define QEI_FILTERINX_FITLINX_Pos                             0                                                         /*!< QEI FILTERINX: FITLINX Position     */
#define QEI_FILTERINX_FITLINX_Msk                             (0xffffffffUL << QEI_FILTERINX_FITLINX_Pos)               /*!< QEI FILTERINX: FITLINX Mask         */

// ---------------------------------------  QEI_WINDOW  -------------------------------------------
#define QEI_WINDOW_WINDOW_Pos                                 0                                                         /*!< QEI WINDOW: WINDOW Position         */
#define QEI_WINDOW_WINDOW_Msk                                 (0xffffffffUL << QEI_WINDOW_WINDOW_Pos)                   /*!< QEI WINDOW: WINDOW Mask             */

// ---------------------------------------  QEI_INXCMP1  ------------------------------------------
#define QEI_INXCMP1_ICMP1_Pos                                 0                                                         /*!< QEI INXCMP1: ICMP1 Position         */
#define QEI_INXCMP1_ICMP1_Msk                                 (0xffffffffUL << QEI_INXCMP1_ICMP1_Pos)                   /*!< QEI INXCMP1: ICMP1 Mask             */

// ---------------------------------------  QEI_INXCMP2  ------------------------------------------
#define QEI_INXCMP2_ICMP2_Pos                                 0                                                         /*!< QEI INXCMP2: ICMP2 Position         */
#define QEI_INXCMP2_ICMP2_Msk                                 (0xffffffffUL << QEI_INXCMP2_ICMP2_Pos)                   /*!< QEI INXCMP2: ICMP2 Mask             */

// -----------------------------------------  QEI_IEC  --------------------------------------------
#define QEI_IEC_INX_EN_Pos                                    0                                                         /*!< QEI IEC: INX_EN Position            */
#define QEI_IEC_INX_EN_Msk                                    (0x01UL << QEI_IEC_INX_EN_Pos)                            /*!< QEI IEC: INX_EN Mask                */
#define QEI_IEC_TIM_EN_Pos                                    1                                                         /*!< QEI IEC: TIM_EN Position            */
#define QEI_IEC_TIM_EN_Msk                                    (0x01UL << QEI_IEC_TIM_EN_Pos)                            /*!< QEI IEC: TIM_EN Mask                */
#define QEI_IEC_VELC_EN_Pos                                   2                                                         /*!< QEI IEC: VELC_EN Position           */
#define QEI_IEC_VELC_EN_Msk                                   (0x01UL << QEI_IEC_VELC_EN_Pos)                           /*!< QEI IEC: VELC_EN Mask               */
#define QEI_IEC_DIR_EN_Pos                                    3                                                         /*!< QEI IEC: DIR_EN Position            */
#define QEI_IEC_DIR_EN_Msk                                    (0x01UL << QEI_IEC_DIR_EN_Pos)                            /*!< QEI IEC: DIR_EN Mask                */
#define QEI_IEC_ERR_EN_Pos                                    4                                                         /*!< QEI IEC: ERR_EN Position            */
#define QEI_IEC_ERR_EN_Msk                                    (0x01UL << QEI_IEC_ERR_EN_Pos)                            /*!< QEI IEC: ERR_EN Mask                */
#define QEI_IEC_ENCLK_EN_Pos                                  5                                                         /*!< QEI IEC: ENCLK_EN Position          */
#define QEI_IEC_ENCLK_EN_Msk                                  (0x01UL << QEI_IEC_ENCLK_EN_Pos)                          /*!< QEI IEC: ENCLK_EN Mask              */
#define QEI_IEC_POS0_Int_Pos                                  6                                                         /*!< QEI IEC: POS0_Int Position          */
#define QEI_IEC_POS0_Int_Msk                                  (0x01UL << QEI_IEC_POS0_Int_Pos)                          /*!< QEI IEC: POS0_Int Mask              */
#define QEI_IEC_POS1_Int_Pos                                  7                                                         /*!< QEI IEC: POS1_Int Position          */
#define QEI_IEC_POS1_Int_Msk                                  (0x01UL << QEI_IEC_POS1_Int_Pos)                          /*!< QEI IEC: POS1_Int Mask              */
#define QEI_IEC_POS2_Int_Pos                                  8                                                         /*!< QEI IEC: POS2_Int Position          */
#define QEI_IEC_POS2_Int_Msk                                  (0x01UL << QEI_IEC_POS2_Int_Pos)                          /*!< QEI IEC: POS2_Int Mask              */
#define QEI_IEC_REV_Int_Pos                                   9                                                         /*!< QEI IEC: REV_Int Position           */
#define QEI_IEC_REV_Int_Msk                                   (0x01UL << QEI_IEC_REV_Int_Pos)                           /*!< QEI IEC: REV_Int Mask               */
#define QEI_IEC_POS0REV_Int_Pos                               10                                                        /*!< QEI IEC: POS0REV_Int Position       */
#define QEI_IEC_POS0REV_Int_Msk                               (0x01UL << QEI_IEC_POS0REV_Int_Pos)                       /*!< QEI IEC: POS0REV_Int Mask           */
#define QEI_IEC_POS1REV_Int_Pos                               11                                                        /*!< QEI IEC: POS1REV_Int Position       */
#define QEI_IEC_POS1REV_Int_Msk                               (0x01UL << QEI_IEC_POS1REV_Int_Pos)                       /*!< QEI IEC: POS1REV_Int Mask           */
#define QEI_IEC_POS2REV_Int_Pos                               12                                                        /*!< QEI IEC: POS2REV_Int Position       */
#define QEI_IEC_POS2REV_Int_Msk                               (0x01UL << QEI_IEC_POS2REV_Int_Pos)                       /*!< QEI IEC: POS2REV_Int Mask           */
#define QEI_IEC_REV1_Int_Pos                                  13                                                        /*!< QEI IEC: REV1_Int Position          */
#define QEI_IEC_REV1_Int_Msk                                  (0x01UL << QEI_IEC_REV1_Int_Pos)                          /*!< QEI IEC: REV1_Int Mask              */
#define QEI_IEC_REV2_Int_Pos                                  14                                                        /*!< QEI IEC: REV2_Int Position          */
#define QEI_IEC_REV2_Int_Msk                                  (0x01UL << QEI_IEC_REV2_Int_Pos)                          /*!< QEI IEC: REV2_Int Mask              */
#define QEI_IEC_MAXPOS_Int_Pos                                15                                                        /*!< QEI IEC: MAXPOS_Int Position        */
#define QEI_IEC_MAXPOS_Int_Msk                                (0x01UL << QEI_IEC_MAXPOS_Int_Pos)                        /*!< QEI IEC: MAXPOS_Int Mask            */

// -----------------------------------------  QEI_IES  --------------------------------------------
#define QEI_IES_INX_EN_Pos                                    0                                                         /*!< QEI IES: INX_EN Position            */
#define QEI_IES_INX_EN_Msk                                    (0x01UL << QEI_IES_INX_EN_Pos)                            /*!< QEI IES: INX_EN Mask                */
#define QEI_IES_TIM_EN_Pos                                    1                                                         /*!< QEI IES: TIM_EN Position            */
#define QEI_IES_TIM_EN_Msk                                    (0x01UL << QEI_IES_TIM_EN_Pos)                            /*!< QEI IES: TIM_EN Mask                */
#define QEI_IES_VELC_EN_Pos                                   2                                                         /*!< QEI IES: VELC_EN Position           */
#define QEI_IES_VELC_EN_Msk                                   (0x01UL << QEI_IES_VELC_EN_Pos)                           /*!< QEI IES: VELC_EN Mask               */
#define QEI_IES_DIR_EN_Pos                                    3                                                         /*!< QEI IES: DIR_EN Position            */
#define QEI_IES_DIR_EN_Msk                                    (0x01UL << QEI_IES_DIR_EN_Pos)                            /*!< QEI IES: DIR_EN Mask                */
#define QEI_IES_ERR_EN_Pos                                    4                                                         /*!< QEI IES: ERR_EN Position            */
#define QEI_IES_ERR_EN_Msk                                    (0x01UL << QEI_IES_ERR_EN_Pos)                            /*!< QEI IES: ERR_EN Mask                */
#define QEI_IES_ENCLK_EN_Pos                                  5                                                         /*!< QEI IES: ENCLK_EN Position          */
#define QEI_IES_ENCLK_EN_Msk                                  (0x01UL << QEI_IES_ENCLK_EN_Pos)                          /*!< QEI IES: ENCLK_EN Mask              */
#define QEI_IES_POS0_Int_Pos                                  6                                                         /*!< QEI IES: POS0_Int Position          */
#define QEI_IES_POS0_Int_Msk                                  (0x01UL << QEI_IES_POS0_Int_Pos)                          /*!< QEI IES: POS0_Int Mask              */
#define QEI_IES_POS1_Int_Pos                                  7                                                         /*!< QEI IES: POS1_Int Position          */
#define QEI_IES_POS1_Int_Msk                                  (0x01UL << QEI_IES_POS1_Int_Pos)                          /*!< QEI IES: POS1_Int Mask              */
#define QEI_IES_POS2_Int_Pos                                  8                                                         /*!< QEI IES: POS2_Int Position          */
#define QEI_IES_POS2_Int_Msk                                  (0x01UL << QEI_IES_POS2_Int_Pos)                          /*!< QEI IES: POS2_Int Mask              */
#define QEI_IES_REV_Int_Pos                                   9                                                         /*!< QEI IES: REV_Int Position           */
#define QEI_IES_REV_Int_Msk                                   (0x01UL << QEI_IES_REV_Int_Pos)                           /*!< QEI IES: REV_Int Mask               */
#define QEI_IES_POS0REV_Int_Pos                               10                                                        /*!< QEI IES: POS0REV_Int Position       */
#define QEI_IES_POS0REV_Int_Msk                               (0x01UL << QEI_IES_POS0REV_Int_Pos)                       /*!< QEI IES: POS0REV_Int Mask           */
#define QEI_IES_POS1REV_Int_Pos                               11                                                        /*!< QEI IES: POS1REV_Int Position       */
#define QEI_IES_POS1REV_Int_Msk                               (0x01UL << QEI_IES_POS1REV_Int_Pos)                       /*!< QEI IES: POS1REV_Int Mask           */
#define QEI_IES_POS2REV_Int_Pos                               12                                                        /*!< QEI IES: POS2REV_Int Position       */
#define QEI_IES_POS2REV_Int_Msk                               (0x01UL << QEI_IES_POS2REV_Int_Pos)                       /*!< QEI IES: POS2REV_Int Mask           */
#define QEI_IES_REV1_Int_Pos                                  13                                                        /*!< QEI IES: REV1_Int Position          */
#define QEI_IES_REV1_Int_Msk                                  (0x01UL << QEI_IES_REV1_Int_Pos)                          /*!< QEI IES: REV1_Int Mask              */
#define QEI_IES_REV2_Int_Pos                                  14                                                        /*!< QEI IES: REV2_Int Position          */
#define QEI_IES_REV2_Int_Msk                                  (0x01UL << QEI_IES_REV2_Int_Pos)                          /*!< QEI IES: REV2_Int Mask              */
#define QEI_IES_MAXPOS_Int_Pos                                15                                                        /*!< QEI IES: MAXPOS_Int Position        */
#define QEI_IES_MAXPOS_Int_Msk                                (0x01UL << QEI_IES_MAXPOS_Int_Pos)                        /*!< QEI IES: MAXPOS_Int Mask            */

// ---------------------------------------  QEI_INTSTAT  ------------------------------------------
#define QEI_INTSTAT_INX_Int_Pos                               0                                                         /*!< QEI INTSTAT: INX_Int Position       */
#define QEI_INTSTAT_INX_Int_Msk                               (0x01UL << QEI_INTSTAT_INX_Int_Pos)                       /*!< QEI INTSTAT: INX_Int Mask           */
#define QEI_INTSTAT_TIM_Int_Pos                               1                                                         /*!< QEI INTSTAT: TIM_Int Position       */
#define QEI_INTSTAT_TIM_Int_Msk                               (0x01UL << QEI_INTSTAT_TIM_Int_Pos)                       /*!< QEI INTSTAT: TIM_Int Mask           */
#define QEI_INTSTAT_VELC_Int_Pos                              2                                                         /*!< QEI INTSTAT: VELC_Int Position      */
#define QEI_INTSTAT_VELC_Int_Msk                              (0x01UL << QEI_INTSTAT_VELC_Int_Pos)                      /*!< QEI INTSTAT: VELC_Int Mask          */
#define QEI_INTSTAT_DIR_Int_Pos                               3                                                         /*!< QEI INTSTAT: DIR_Int Position       */
#define QEI_INTSTAT_DIR_Int_Msk                               (0x01UL << QEI_INTSTAT_DIR_Int_Pos)                       /*!< QEI INTSTAT: DIR_Int Mask           */
#define QEI_INTSTAT_ERR_Int_Pos                               4                                                         /*!< QEI INTSTAT: ERR_Int Position       */
#define QEI_INTSTAT_ERR_Int_Msk                               (0x01UL << QEI_INTSTAT_ERR_Int_Pos)                       /*!< QEI INTSTAT: ERR_Int Mask           */
#define QEI_INTSTAT_ENCLK_Int_Pos                             5                                                         /*!< QEI INTSTAT: ENCLK_Int Position     */
#define QEI_INTSTAT_ENCLK_Int_Msk                             (0x01UL << QEI_INTSTAT_ENCLK_Int_Pos)                     /*!< QEI INTSTAT: ENCLK_Int Mask         */
#define QEI_INTSTAT_POS0_Int_Pos                              6                                                         /*!< QEI INTSTAT: POS0_Int Position      */
#define QEI_INTSTAT_POS0_Int_Msk                              (0x01UL << QEI_INTSTAT_POS0_Int_Pos)                      /*!< QEI INTSTAT: POS0_Int Mask          */
#define QEI_INTSTAT_POS1_Int_Pos                              7                                                         /*!< QEI INTSTAT: POS1_Int Position      */
#define QEI_INTSTAT_POS1_Int_Msk                              (0x01UL << QEI_INTSTAT_POS1_Int_Pos)                      /*!< QEI INTSTAT: POS1_Int Mask          */
#define QEI_INTSTAT_POS2_Int_Pos                              8                                                         /*!< QEI INTSTAT: POS2_Int Position      */
#define QEI_INTSTAT_POS2_Int_Msk                              (0x01UL << QEI_INTSTAT_POS2_Int_Pos)                      /*!< QEI INTSTAT: POS2_Int Mask          */
#define QEI_INTSTAT_REV_Int_Pos                               9                                                         /*!< QEI INTSTAT: REV_Int Position       */
#define QEI_INTSTAT_REV_Int_Msk                               (0x01UL << QEI_INTSTAT_REV_Int_Pos)                       /*!< QEI INTSTAT: REV_Int Mask           */
#define QEI_INTSTAT_POS0REV_Int_Pos                           10                                                        /*!< QEI INTSTAT: POS0REV_Int Position   */
#define QEI_INTSTAT_POS0REV_Int_Msk                           (0x01UL << QEI_INTSTAT_POS0REV_Int_Pos)                   /*!< QEI INTSTAT: POS0REV_Int Mask       */
#define QEI_INTSTAT_POS1REV_Int_Pos                           11                                                        /*!< QEI INTSTAT: POS1REV_Int Position   */
#define QEI_INTSTAT_POS1REV_Int_Msk                           (0x01UL << QEI_INTSTAT_POS1REV_Int_Pos)                   /*!< QEI INTSTAT: POS1REV_Int Mask       */
#define QEI_INTSTAT_POS2REV_Int_Pos                           12                                                        /*!< QEI INTSTAT: POS2REV_Int Position   */
#define QEI_INTSTAT_POS2REV_Int_Msk                           (0x01UL << QEI_INTSTAT_POS2REV_Int_Pos)                   /*!< QEI INTSTAT: POS2REV_Int Mask       */
#define QEI_INTSTAT_REV1_Int_Pos                              13                                                        /*!< QEI INTSTAT: REV1_Int Position      */
#define QEI_INTSTAT_REV1_Int_Msk                              (0x01UL << QEI_INTSTAT_REV1_Int_Pos)                      /*!< QEI INTSTAT: REV1_Int Mask          */
#define QEI_INTSTAT_REV2_Int_Pos                              14                                                        /*!< QEI INTSTAT: REV2_Int Position      */
#define QEI_INTSTAT_REV2_Int_Msk                              (0x01UL << QEI_INTSTAT_REV2_Int_Pos)                      /*!< QEI INTSTAT: REV2_Int Mask          */
#define QEI_INTSTAT_MAXPOS_Int_Pos                            15                                                        /*!< QEI INTSTAT: MAXPOS_Int Position    */
#define QEI_INTSTAT_MAXPOS_Int_Msk                            (0x01UL << QEI_INTSTAT_MAXPOS_Int_Pos)                    /*!< QEI INTSTAT: MAXPOS_Int Mask        */

// -----------------------------------------  QEI_IE  ---------------------------------------------
#define QEI_IE_INX_Int_Pos                                    0                                                         /*!< QEI IE: INX_Int Position            */
#define QEI_IE_INX_Int_Msk                                    (0x01UL << QEI_IE_INX_Int_Pos)                            /*!< QEI IE: INX_Int Mask                */
#define QEI_IE_TIM_Int_Pos                                    1                                                         /*!< QEI IE: TIM_Int Position            */
#define QEI_IE_TIM_Int_Msk                                    (0x01UL << QEI_IE_TIM_Int_Pos)                            /*!< QEI IE: TIM_Int Mask                */
#define QEI_IE_VELC_Int_Pos                                   2                                                         /*!< QEI IE: VELC_Int Position           */
#define QEI_IE_VELC_Int_Msk                                   (0x01UL << QEI_IE_VELC_Int_Pos)                           /*!< QEI IE: VELC_Int Mask               */
#define QEI_IE_DIR_Int_Pos                                    3                                                         /*!< QEI IE: DIR_Int Position            */
#define QEI_IE_DIR_Int_Msk                                    (0x01UL << QEI_IE_DIR_Int_Pos)                            /*!< QEI IE: DIR_Int Mask                */
#define QEI_IE_ERR_Int_Pos                                    4                                                         /*!< QEI IE: ERR_Int Position            */
#define QEI_IE_ERR_Int_Msk                                    (0x01UL << QEI_IE_ERR_Int_Pos)                            /*!< QEI IE: ERR_Int Mask                */
#define QEI_IE_ENCLK_Int_Pos                                  5                                                         /*!< QEI IE: ENCLK_Int Position          */
#define QEI_IE_ENCLK_Int_Msk                                  (0x01UL << QEI_IE_ENCLK_Int_Pos)                          /*!< QEI IE: ENCLK_Int Mask              */
#define QEI_IE_POS0_Int_Pos                                   6                                                         /*!< QEI IE: POS0_Int Position           */
#define QEI_IE_POS0_Int_Msk                                   (0x01UL << QEI_IE_POS0_Int_Pos)                           /*!< QEI IE: POS0_Int Mask               */
#define QEI_IE_POS1_Int_Pos                                   7                                                         /*!< QEI IE: POS1_Int Position           */
#define QEI_IE_POS1_Int_Msk                                   (0x01UL << QEI_IE_POS1_Int_Pos)                           /*!< QEI IE: POS1_Int Mask               */
#define QEI_IE_POS2_Int_Pos                                   8                                                         /*!< QEI IE: POS2_Int Position           */
#define QEI_IE_POS2_Int_Msk                                   (0x01UL << QEI_IE_POS2_Int_Pos)                           /*!< QEI IE: POS2_Int Mask               */
#define QEI_IE_REV_Int_Pos                                    9                                                         /*!< QEI IE: REV_Int Position            */
#define QEI_IE_REV_Int_Msk                                    (0x01UL << QEI_IE_REV_Int_Pos)                            /*!< QEI IE: REV_Int Mask                */
#define QEI_IE_POS0REV_Int_Pos                                10                                                        /*!< QEI IE: POS0REV_Int Position        */
#define QEI_IE_POS0REV_Int_Msk                                (0x01UL << QEI_IE_POS0REV_Int_Pos)                        /*!< QEI IE: POS0REV_Int Mask            */
#define QEI_IE_POS1REV_Int_Pos                                11                                                        /*!< QEI IE: POS1REV_Int Position        */
#define QEI_IE_POS1REV_Int_Msk                                (0x01UL << QEI_IE_POS1REV_Int_Pos)                        /*!< QEI IE: POS1REV_Int Mask            */
#define QEI_IE_POS2REV_Int_Pos                                12                                                        /*!< QEI IE: POS2REV_Int Position        */
#define QEI_IE_POS2REV_Int_Msk                                (0x01UL << QEI_IE_POS2REV_Int_Pos)                        /*!< QEI IE: POS2REV_Int Mask            */
#define QEI_IE_REV1_Int_Pos                                   13                                                        /*!< QEI IE: REV1_Int Position           */
#define QEI_IE_REV1_Int_Msk                                   (0x01UL << QEI_IE_REV1_Int_Pos)                           /*!< QEI IE: REV1_Int Mask               */
#define QEI_IE_REV2_Int_Pos                                   14                                                        /*!< QEI IE: REV2_Int Position           */
#define QEI_IE_REV2_Int_Msk                                   (0x01UL << QEI_IE_REV2_Int_Pos)                           /*!< QEI IE: REV2_Int Mask               */
#define QEI_IE_MAXPOS_Int_Pos                                 15                                                        /*!< QEI IE: MAXPOS_Int Position         */
#define QEI_IE_MAXPOS_Int_Msk                                 (0x01UL << QEI_IE_MAXPOS_Int_Pos)                         /*!< QEI IE: MAXPOS_Int Mask             */

// -----------------------------------------  QEI_CLR  --------------------------------------------
#define QEI_CLR_INX_Int_Pos                                   0                                                         /*!< QEI CLR: INX_Int Position           */
#define QEI_CLR_INX_Int_Msk                                   (0x01UL << QEI_CLR_INX_Int_Pos)                           /*!< QEI CLR: INX_Int Mask               */
#define QEI_CLR_TIM_Int_Pos                                   1                                                         /*!< QEI CLR: TIM_Int Position           */
#define QEI_CLR_TIM_Int_Msk                                   (0x01UL << QEI_CLR_TIM_Int_Pos)                           /*!< QEI CLR: TIM_Int Mask               */
#define QEI_CLR_VELC_Int_Pos                                  2                                                         /*!< QEI CLR: VELC_Int Position          */
#define QEI_CLR_VELC_Int_Msk                                  (0x01UL << QEI_CLR_VELC_Int_Pos)                          /*!< QEI CLR: VELC_Int Mask              */
#define QEI_CLR_DIR_Int_Pos                                   3                                                         /*!< QEI CLR: DIR_Int Position           */
#define QEI_CLR_DIR_Int_Msk                                   (0x01UL << QEI_CLR_DIR_Int_Pos)                           /*!< QEI CLR: DIR_Int Mask               */
#define QEI_CLR_ERR_Int_Pos                                   4                                                         /*!< QEI CLR: ERR_Int Position           */
#define QEI_CLR_ERR_Int_Msk                                   (0x01UL << QEI_CLR_ERR_Int_Pos)                           /*!< QEI CLR: ERR_Int Mask               */
#define QEI_CLR_ENCLK_Int_Pos                                 5                                                         /*!< QEI CLR: ENCLK_Int Position         */
#define QEI_CLR_ENCLK_Int_Msk                                 (0x01UL << QEI_CLR_ENCLK_Int_Pos)                         /*!< QEI CLR: ENCLK_Int Mask             */
#define QEI_CLR_POS0_Int_Pos                                  6                                                         /*!< QEI CLR: POS0_Int Position          */
#define QEI_CLR_POS0_Int_Msk                                  (0x01UL << QEI_CLR_POS0_Int_Pos)                          /*!< QEI CLR: POS0_Int Mask              */
#define QEI_CLR_POS1_Int_Pos                                  7                                                         /*!< QEI CLR: POS1_Int Position          */
#define QEI_CLR_POS1_Int_Msk                                  (0x01UL << QEI_CLR_POS1_Int_Pos)                          /*!< QEI CLR: POS1_Int Mask              */
#define QEI_CLR_POS2_Int_Pos                                  8                                                         /*!< QEI CLR: POS2_Int Position          */
#define QEI_CLR_POS2_Int_Msk                                  (0x01UL << QEI_CLR_POS2_Int_Pos)                          /*!< QEI CLR: POS2_Int Mask              */
#define QEI_CLR_REV_Int_Pos                                   9                                                         /*!< QEI CLR: REV_Int Position           */
#define QEI_CLR_REV_Int_Msk                                   (0x01UL << QEI_CLR_REV_Int_Pos)                           /*!< QEI CLR: REV_Int Mask               */
#define QEI_CLR_POS0REV_Int_Pos                               10                                                        /*!< QEI CLR: POS0REV_Int Position       */
#define QEI_CLR_POS0REV_Int_Msk                               (0x01UL << QEI_CLR_POS0REV_Int_Pos)                       /*!< QEI CLR: POS0REV_Int Mask           */
#define QEI_CLR_POS1REV_Int_Pos                               11                                                        /*!< QEI CLR: POS1REV_Int Position       */
#define QEI_CLR_POS1REV_Int_Msk                               (0x01UL << QEI_CLR_POS1REV_Int_Pos)                       /*!< QEI CLR: POS1REV_Int Mask           */
#define QEI_CLR_REV1_Int_Pos                                  13                                                        /*!< QEI CLR: REV1_Int Position          */
#define QEI_CLR_REV1_Int_Msk                                  (0x01UL << QEI_CLR_REV1_Int_Pos)                          /*!< QEI CLR: REV1_Int Mask              */
#define QEI_CLR_REV2_Int_Pos                                  14                                                        /*!< QEI CLR: REV2_Int Position          */
#define QEI_CLR_REV2_Int_Msk                                  (0x01UL << QEI_CLR_REV2_Int_Pos)                          /*!< QEI CLR: REV2_Int Mask              */
#define QEI_CLR_MAXPOS_Int_Pos                                15                                                        /*!< QEI CLR: MAXPOS_Int Position        */
#define QEI_CLR_MAXPOS_Int_Msk                                (0x01UL << QEI_CLR_MAXPOS_Int_Pos)                        /*!< QEI CLR: MAXPOS_Int Mask            */

// -----------------------------------------  QEI_SET  --------------------------------------------
#define QEI_SET_INX_Int_Pos                                   0                                                         /*!< QEI SET: INX_Int Position           */
#define QEI_SET_INX_Int_Msk                                   (0x01UL << QEI_SET_INX_Int_Pos)                           /*!< QEI SET: INX_Int Mask               */
#define QEI_SET_TIM_Int_Pos                                   1                                                         /*!< QEI SET: TIM_Int Position           */
#define QEI_SET_TIM_Int_Msk                                   (0x01UL << QEI_SET_TIM_Int_Pos)                           /*!< QEI SET: TIM_Int Mask               */
#define QEI_SET_VELC_Int_Pos                                  2                                                         /*!< QEI SET: VELC_Int Position          */
#define QEI_SET_VELC_Int_Msk                                  (0x01UL << QEI_SET_VELC_Int_Pos)                          /*!< QEI SET: VELC_Int Mask              */
#define QEI_SET_DIR_Int_Pos                                   3                                                         /*!< QEI SET: DIR_Int Position           */
#define QEI_SET_DIR_Int_Msk                                   (0x01UL << QEI_SET_DIR_Int_Pos)                           /*!< QEI SET: DIR_Int Mask               */
#define QEI_SET_ERR_Int_Pos                                   4                                                         /*!< QEI SET: ERR_Int Position           */
#define QEI_SET_ERR_Int_Msk                                   (0x01UL << QEI_SET_ERR_Int_Pos)                           /*!< QEI SET: ERR_Int Mask               */
#define QEI_SET_ENCLK_Int_Pos                                 5                                                         /*!< QEI SET: ENCLK_Int Position         */
#define QEI_SET_ENCLK_Int_Msk                                 (0x01UL << QEI_SET_ENCLK_Int_Pos)                         /*!< QEI SET: ENCLK_Int Mask             */
#define QEI_SET_POS0_Int_Pos                                  6                                                         /*!< QEI SET: POS0_Int Position          */
#define QEI_SET_POS0_Int_Msk                                  (0x01UL << QEI_SET_POS0_Int_Pos)                          /*!< QEI SET: POS0_Int Mask              */
#define QEI_SET_POS1_Int_Pos                                  7                                                         /*!< QEI SET: POS1_Int Position          */
#define QEI_SET_POS1_Int_Msk                                  (0x01UL << QEI_SET_POS1_Int_Pos)                          /*!< QEI SET: POS1_Int Mask              */
#define QEI_SET_POS2_Int_Pos                                  8                                                         /*!< QEI SET: POS2_Int Position          */
#define QEI_SET_POS2_Int_Msk                                  (0x01UL << QEI_SET_POS2_Int_Pos)                          /*!< QEI SET: POS2_Int Mask              */
#define QEI_SET_REV_Int_Pos                                   9                                                         /*!< QEI SET: REV_Int Position           */
#define QEI_SET_REV_Int_Msk                                   (0x01UL << QEI_SET_REV_Int_Pos)                           /*!< QEI SET: REV_Int Mask               */
#define QEI_SET_POS0REV_Int_Pos                               10                                                        /*!< QEI SET: POS0REV_Int Position       */
#define QEI_SET_POS0REV_Int_Msk                               (0x01UL << QEI_SET_POS0REV_Int_Pos)                       /*!< QEI SET: POS0REV_Int Mask           */
#define QEI_SET_POS1REV_Int_Pos                               11                                                        /*!< QEI SET: POS1REV_Int Position       */
#define QEI_SET_POS1REV_Int_Msk                               (0x01UL << QEI_SET_POS1REV_Int_Pos)                       /*!< QEI SET: POS1REV_Int Mask           */
#define QEI_SET_POS2REV_Int_Pos                               12                                                        /*!< QEI SET: POS2REV_Int Position       */
#define QEI_SET_POS2REV_Int_Msk                               (0x01UL << QEI_SET_POS2REV_Int_Pos)                       /*!< QEI SET: POS2REV_Int Mask           */
#define QEI_SET_REV1_Int_Pos                                  13                                                        /*!< QEI SET: REV1_Int Position          */
#define QEI_SET_REV1_Int_Msk                                  (0x01UL << QEI_SET_REV1_Int_Pos)                          /*!< QEI SET: REV1_Int Mask              */
#define QEI_SET_REV2_Int_Pos                                  14                                                        /*!< QEI SET: REV2_Int Position          */
#define QEI_SET_REV2_Int_Msk                                  (0x01UL << QEI_SET_REV2_Int_Pos)                          /*!< QEI SET: REV2_Int Mask              */
#define QEI_SET_MAXPOS_Int_Pos                                15                                                        /*!< QEI SET: MAXPOS_Int Position        */
#define QEI_SET_MAXPOS_Int_Msk                                (0x01UL << QEI_SET_MAXPOS_Int_Pos)                        /*!< QEI SET: MAXPOS_Int Mask            */


// ------------------------------------------------------------------------------------------------
// -----                                 GIMA Position & Mask                                 -----
// ------------------------------------------------------------------------------------------------


// -------------------------------------  GIMA_CAP0_0_IN  -----------------------------------------
#define GIMA_CAP0_0_IN_INV_Pos                                0                                                         /*!< GIMA CAP0_0_IN: INV Position        */
#define GIMA_CAP0_0_IN_INV_Msk                                (0x01UL << GIMA_CAP0_0_IN_INV_Pos)                        /*!< GIMA CAP0_0_IN: INV Mask            */
#define GIMA_CAP0_0_IN_EDGE_Pos                               1                                                         /*!< GIMA CAP0_0_IN: EDGE Position       */
#define GIMA_CAP0_0_IN_EDGE_Msk                               (0x01UL << GIMA_CAP0_0_IN_EDGE_Pos)                       /*!< GIMA CAP0_0_IN: EDGE Mask           */
#define GIMA_CAP0_0_IN_SYNCH_Pos                              2                                                         /*!< GIMA CAP0_0_IN: SYNCH Position      */
#define GIMA_CAP0_0_IN_SYNCH_Msk                              (0x01UL << GIMA_CAP0_0_IN_SYNCH_Pos)                      /*!< GIMA CAP0_0_IN: SYNCH Mask          */
#define GIMA_CAP0_0_IN_PULSE_Pos                              3                                                         /*!< GIMA CAP0_0_IN: PULSE Position      */
#define GIMA_CAP0_0_IN_PULSE_Msk                              (0x01UL << GIMA_CAP0_0_IN_PULSE_Pos)                      /*!< GIMA CAP0_0_IN: PULSE Mask          */
#define GIMA_CAP0_0_IN_SELECT_Pos                             4                                                         /*!< GIMA CAP0_0_IN: SELECT Position     */
#define GIMA_CAP0_0_IN_SELECT_Msk                             (0x0fUL << GIMA_CAP0_0_IN_SELECT_Pos)                     /*!< GIMA CAP0_0_IN: SELECT Mask         */

// -------------------------------------  GIMA_CAP0_1_IN  -----------------------------------------
#define GIMA_CAP0_1_IN_INV_Pos                                0                                                         /*!< GIMA CAP0_1_IN: INV Position        */
#define GIMA_CAP0_1_IN_INV_Msk                                (0x01UL << GIMA_CAP0_1_IN_INV_Pos)                        /*!< GIMA CAP0_1_IN: INV Mask            */
#define GIMA_CAP0_1_IN_EDGE_Pos                               1                                                         /*!< GIMA CAP0_1_IN: EDGE Position       */
#define GIMA_CAP0_1_IN_EDGE_Msk                               (0x01UL << GIMA_CAP0_1_IN_EDGE_Pos)                       /*!< GIMA CAP0_1_IN: EDGE Mask           */
#define GIMA_CAP0_1_IN_SYNCH_Pos                              2                                                         /*!< GIMA CAP0_1_IN: SYNCH Position      */
#define GIMA_CAP0_1_IN_SYNCH_Msk                              (0x01UL << GIMA_CAP0_1_IN_SYNCH_Pos)                      /*!< GIMA CAP0_1_IN: SYNCH Mask          */
#define GIMA_CAP0_1_IN_PULSE_Pos                              3                                                         /*!< GIMA CAP0_1_IN: PULSE Position      */
#define GIMA_CAP0_1_IN_PULSE_Msk                              (0x01UL << GIMA_CAP0_1_IN_PULSE_Pos)                      /*!< GIMA CAP0_1_IN: PULSE Mask          */
#define GIMA_CAP0_1_IN_SELECT_Pos                             4                                                         /*!< GIMA CAP0_1_IN: SELECT Position     */
#define GIMA_CAP0_1_IN_SELECT_Msk                             (0x0fUL << GIMA_CAP0_1_IN_SELECT_Pos)                     /*!< GIMA CAP0_1_IN: SELECT Mask         */

// -------------------------------------  GIMA_CAP0_2_IN  -----------------------------------------
#define GIMA_CAP0_2_IN_INV_Pos                                0                                                         /*!< GIMA CAP0_2_IN: INV Position        */
#define GIMA_CAP0_2_IN_INV_Msk                                (0x01UL << GIMA_CAP0_2_IN_INV_Pos)                        /*!< GIMA CAP0_2_IN: INV Mask            */
#define GIMA_CAP0_2_IN_EDGE_Pos                               1                                                         /*!< GIMA CAP0_2_IN: EDGE Position       */
#define GIMA_CAP0_2_IN_EDGE_Msk                               (0x01UL << GIMA_CAP0_2_IN_EDGE_Pos)                       /*!< GIMA CAP0_2_IN: EDGE Mask           */
#define GIMA_CAP0_2_IN_SYNCH_Pos                              2                                                         /*!< GIMA CAP0_2_IN: SYNCH Position      */
#define GIMA_CAP0_2_IN_SYNCH_Msk                              (0x01UL << GIMA_CAP0_2_IN_SYNCH_Pos)                      /*!< GIMA CAP0_2_IN: SYNCH Mask          */
#define GIMA_CAP0_2_IN_PULSE_Pos                              3                                                         /*!< GIMA CAP0_2_IN: PULSE Position      */
#define GIMA_CAP0_2_IN_PULSE_Msk                              (0x01UL << GIMA_CAP0_2_IN_PULSE_Pos)                      /*!< GIMA CAP0_2_IN: PULSE Mask          */
#define GIMA_CAP0_2_IN_SELECT_Pos                             4                                                         /*!< GIMA CAP0_2_IN: SELECT Position     */
#define GIMA_CAP0_2_IN_SELECT_Msk                             (0x0fUL << GIMA_CAP0_2_IN_SELECT_Pos)                     /*!< GIMA CAP0_2_IN: SELECT Mask         */

// -------------------------------------  GIMA_CAP0_3_IN  -----------------------------------------
#define GIMA_CAP0_3_IN_INV_Pos                                0                                                         /*!< GIMA CAP0_3_IN: INV Position        */
#define GIMA_CAP0_3_IN_INV_Msk                                (0x01UL << GIMA_CAP0_3_IN_INV_Pos)                        /*!< GIMA CAP0_3_IN: INV Mask            */
#define GIMA_CAP0_3_IN_EDGE_Pos                               1                                                         /*!< GIMA CAP0_3_IN: EDGE Position       */
#define GIMA_CAP0_3_IN_EDGE_Msk                               (0x01UL << GIMA_CAP0_3_IN_EDGE_Pos)                       /*!< GIMA CAP0_3_IN: EDGE Mask           */
#define GIMA_CAP0_3_IN_SYNCH_Pos                              2                                                         /*!< GIMA CAP0_3_IN: SYNCH Position      */
#define GIMA_CAP0_3_IN_SYNCH_Msk                              (0x01UL << GIMA_CAP0_3_IN_SYNCH_Pos)                      /*!< GIMA CAP0_3_IN: SYNCH Mask          */
#define GIMA_CAP0_3_IN_PULSE_Pos                              3                                                         /*!< GIMA CAP0_3_IN: PULSE Position      */
#define GIMA_CAP0_3_IN_PULSE_Msk                              (0x01UL << GIMA_CAP0_3_IN_PULSE_Pos)                      /*!< GIMA CAP0_3_IN: PULSE Mask          */
#define GIMA_CAP0_3_IN_SELECT_Pos                             4                                                         /*!< GIMA CAP0_3_IN: SELECT Position     */
#define GIMA_CAP0_3_IN_SELECT_Msk                             (0x0fUL << GIMA_CAP0_3_IN_SELECT_Pos)                     /*!< GIMA CAP0_3_IN: SELECT Mask         */

// -------------------------------------  GIMA_CAP1_0_IN  -----------------------------------------
#define GIMA_CAP1_0_IN_INV_Pos                                0                                                         /*!< GIMA CAP1_0_IN: INV Position        */
#define GIMA_CAP1_0_IN_INV_Msk                                (0x01UL << GIMA_CAP1_0_IN_INV_Pos)                        /*!< GIMA CAP1_0_IN: INV Mask            */
#define GIMA_CAP1_0_IN_EDGE_Pos                               1                                                         /*!< GIMA CAP1_0_IN: EDGE Position       */
#define GIMA_CAP1_0_IN_EDGE_Msk                               (0x01UL << GIMA_CAP1_0_IN_EDGE_Pos)                       /*!< GIMA CAP1_0_IN: EDGE Mask           */
#define GIMA_CAP1_0_IN_SYNCH_Pos                              2                                                         /*!< GIMA CAP1_0_IN: SYNCH Position      */
#define GIMA_CAP1_0_IN_SYNCH_Msk                              (0x01UL << GIMA_CAP1_0_IN_SYNCH_Pos)                      /*!< GIMA CAP1_0_IN: SYNCH Mask          */
#define GIMA_CAP1_0_IN_PULSE_Pos                              3                                                         /*!< GIMA CAP1_0_IN: PULSE Position      */
#define GIMA_CAP1_0_IN_PULSE_Msk                              (0x01UL << GIMA_CAP1_0_IN_PULSE_Pos)                      /*!< GIMA CAP1_0_IN: PULSE Mask          */
#define GIMA_CAP1_0_IN_SELECT_Pos                             4                                                         /*!< GIMA CAP1_0_IN: SELECT Position     */
#define GIMA_CAP1_0_IN_SELECT_Msk                             (0x0fUL << GIMA_CAP1_0_IN_SELECT_Pos)                     /*!< GIMA CAP1_0_IN: SELECT Mask         */

// -------------------------------------  GIMA_CAP1_1_IN  -----------------------------------------
#define GIMA_CAP1_1_IN_INV_Pos                                0                                                         /*!< GIMA CAP1_1_IN: INV Position        */
#define GIMA_CAP1_1_IN_INV_Msk                                (0x01UL << GIMA_CAP1_1_IN_INV_Pos)                        /*!< GIMA CAP1_1_IN: INV Mask            */
#define GIMA_CAP1_1_IN_EDGE_Pos                               1                                                         /*!< GIMA CAP1_1_IN: EDGE Position       */
#define GIMA_CAP1_1_IN_EDGE_Msk                               (0x01UL << GIMA_CAP1_1_IN_EDGE_Pos)                       /*!< GIMA CAP1_1_IN: EDGE Mask           */
#define GIMA_CAP1_1_IN_SYNCH_Pos                              2                                                         /*!< GIMA CAP1_1_IN: SYNCH Position      */
#define GIMA_CAP1_1_IN_SYNCH_Msk                              (0x01UL << GIMA_CAP1_1_IN_SYNCH_Pos)                      /*!< GIMA CAP1_1_IN: SYNCH Mask          */
#define GIMA_CAP1_1_IN_PULSE_Pos                              3                                                         /*!< GIMA CAP1_1_IN: PULSE Position      */
#define GIMA_CAP1_1_IN_PULSE_Msk                              (0x01UL << GIMA_CAP1_1_IN_PULSE_Pos)                      /*!< GIMA CAP1_1_IN: PULSE Mask          */
#define GIMA_CAP1_1_IN_SELECT_Pos                             4                                                         /*!< GIMA CAP1_1_IN: SELECT Position     */
#define GIMA_CAP1_1_IN_SELECT_Msk                             (0x0fUL << GIMA_CAP1_1_IN_SELECT_Pos)                     /*!< GIMA CAP1_1_IN: SELECT Mask         */

// -------------------------------------  GIMA_CAP1_2_IN  -----------------------------------------
#define GIMA_CAP1_2_IN_INV_Pos                                0                                                         /*!< GIMA CAP1_2_IN: INV Position        */
#define GIMA_CAP1_2_IN_INV_Msk                                (0x01UL << GIMA_CAP1_2_IN_INV_Pos)                        /*!< GIMA CAP1_2_IN: INV Mask            */
#define GIMA_CAP1_2_IN_EDGE_Pos                               1                                                         /*!< GIMA CAP1_2_IN: EDGE Position       */
#define GIMA_CAP1_2_IN_EDGE_Msk                               (0x01UL << GIMA_CAP1_2_IN_EDGE_Pos)                       /*!< GIMA CAP1_2_IN: EDGE Mask           */
#define GIMA_CAP1_2_IN_SYNCH_Pos                              2                                                         /*!< GIMA CAP1_2_IN: SYNCH Position      */
#define GIMA_CAP1_2_IN_SYNCH_Msk                              (0x01UL << GIMA_CAP1_2_IN_SYNCH_Pos)                      /*!< GIMA CAP1_2_IN: SYNCH Mask          */
#define GIMA_CAP1_2_IN_PULSE_Pos                              3                                                         /*!< GIMA CAP1_2_IN: PULSE Position      */
#define GIMA_CAP1_2_IN_PULSE_Msk                              (0x01UL << GIMA_CAP1_2_IN_PULSE_Pos)                      /*!< GIMA CAP1_2_IN: PULSE Mask          */
#define GIMA_CAP1_2_IN_SELECT_Pos                             4                                                         /*!< GIMA CAP1_2_IN: SELECT Position     */
#define GIMA_CAP1_2_IN_SELECT_Msk                             (0x0fUL << GIMA_CAP1_2_IN_SELECT_Pos)                     /*!< GIMA CAP1_2_IN: SELECT Mask         */

// -------------------------------------  GIMA_CAP1_3_IN  -----------------------------------------
#define GIMA_CAP1_3_IN_INV_Pos                                0                                                         /*!< GIMA CAP1_3_IN: INV Position        */
#define GIMA_CAP1_3_IN_INV_Msk                                (0x01UL << GIMA_CAP1_3_IN_INV_Pos)                        /*!< GIMA CAP1_3_IN: INV Mask            */
#define GIMA_CAP1_3_IN_EDGE_Pos                               1                                                         /*!< GIMA CAP1_3_IN: EDGE Position       */
#define GIMA_CAP1_3_IN_EDGE_Msk                               (0x01UL << GIMA_CAP1_3_IN_EDGE_Pos)                       /*!< GIMA CAP1_3_IN: EDGE Mask           */
#define GIMA_CAP1_3_IN_SYNCH_Pos                              2                                                         /*!< GIMA CAP1_3_IN: SYNCH Position      */
#define GIMA_CAP1_3_IN_SYNCH_Msk                              (0x01UL << GIMA_CAP1_3_IN_SYNCH_Pos)                      /*!< GIMA CAP1_3_IN: SYNCH Mask          */
#define GIMA_CAP1_3_IN_PULSE_Pos                              3                                                         /*!< GIMA CAP1_3_IN: PULSE Position      */
#define GIMA_CAP1_3_IN_PULSE_Msk                              (0x01UL << GIMA_CAP1_3_IN_PULSE_Pos)                      /*!< GIMA CAP1_3_IN: PULSE Mask          */
#define GIMA_CAP1_3_IN_SELECT_Pos                             4                                                         /*!< GIMA CAP1_3_IN: SELECT Position     */
#define GIMA_CAP1_3_IN_SELECT_Msk                             (0x0fUL << GIMA_CAP1_3_IN_SELECT_Pos)                     /*!< GIMA CAP1_3_IN: SELECT Mask         */

// -------------------------------------  GIMA_CAP2_0_IN  -----------------------------------------
#define GIMA_CAP2_0_IN_INV_Pos                                0                                                         /*!< GIMA CAP2_0_IN: INV Position        */
#define GIMA_CAP2_0_IN_INV_Msk                                (0x01UL << GIMA_CAP2_0_IN_INV_Pos)                        /*!< GIMA CAP2_0_IN: INV Mask            */
#define GIMA_CAP2_0_IN_EDGE_Pos                               1                                                         /*!< GIMA CAP2_0_IN: EDGE Position       */
#define GIMA_CAP2_0_IN_EDGE_Msk                               (0x01UL << GIMA_CAP2_0_IN_EDGE_Pos)                       /*!< GIMA CAP2_0_IN: EDGE Mask           */
#define GIMA_CAP2_0_IN_SYNCH_Pos                              2                                                         /*!< GIMA CAP2_0_IN: SYNCH Position      */
#define GIMA_CAP2_0_IN_SYNCH_Msk                              (0x01UL << GIMA_CAP2_0_IN_SYNCH_Pos)                      /*!< GIMA CAP2_0_IN: SYNCH Mask          */
#define GIMA_CAP2_0_IN_PULSE_Pos                              3                                                         /*!< GIMA CAP2_0_IN: PULSE Position      */
#define GIMA_CAP2_0_IN_PULSE_Msk                              (0x01UL << GIMA_CAP2_0_IN_PULSE_Pos)                      /*!< GIMA CAP2_0_IN: PULSE Mask          */
#define GIMA_CAP2_0_IN_SELECT_Pos                             4                                                         /*!< GIMA CAP2_0_IN: SELECT Position     */
#define GIMA_CAP2_0_IN_SELECT_Msk                             (0x0fUL << GIMA_CAP2_0_IN_SELECT_Pos)                     /*!< GIMA CAP2_0_IN: SELECT Mask         */

// -------------------------------------  GIMA_CAP2_1_IN  -----------------------------------------
#define GIMA_CAP2_1_IN_INV_Pos                                0                                                         /*!< GIMA CAP2_1_IN: INV Position        */
#define GIMA_CAP2_1_IN_INV_Msk                                (0x01UL << GIMA_CAP2_1_IN_INV_Pos)                        /*!< GIMA CAP2_1_IN: INV Mask            */
#define GIMA_CAP2_1_IN_EDGE_Pos                               1                                                         /*!< GIMA CAP2_1_IN: EDGE Position       */
#define GIMA_CAP2_1_IN_EDGE_Msk                               (0x01UL << GIMA_CAP2_1_IN_EDGE_Pos)                       /*!< GIMA CAP2_1_IN: EDGE Mask           */
#define GIMA_CAP2_1_IN_SYNCH_Pos                              2                                                         /*!< GIMA CAP2_1_IN: SYNCH Position      */
#define GIMA_CAP2_1_IN_SYNCH_Msk                              (0x01UL << GIMA_CAP2_1_IN_SYNCH_Pos)                      /*!< GIMA CAP2_1_IN: SYNCH Mask          */
#define GIMA_CAP2_1_IN_PULSE_Pos                              3                                                         /*!< GIMA CAP2_1_IN: PULSE Position      */
#define GIMA_CAP2_1_IN_PULSE_Msk                              (0x01UL << GIMA_CAP2_1_IN_PULSE_Pos)                      /*!< GIMA CAP2_1_IN: PULSE Mask          */
#define GIMA_CAP2_1_IN_SELECT_Pos                             4                                                         /*!< GIMA CAP2_1_IN: SELECT Position     */
#define GIMA_CAP2_1_IN_SELECT_Msk                             (0x0fUL << GIMA_CAP2_1_IN_SELECT_Pos)                     /*!< GIMA CAP2_1_IN: SELECT Mask         */

// -------------------------------------  GIMA_CAP2_2_IN  -----------------------------------------
#define GIMA_CAP2_2_IN_INV_Pos                                0                                                         /*!< GIMA CAP2_2_IN: INV Position        */
#define GIMA_CAP2_2_IN_INV_Msk                                (0x01UL << GIMA_CAP2_2_IN_INV_Pos)                        /*!< GIMA CAP2_2_IN: INV Mask            */
#define GIMA_CAP2_2_IN_EDGE_Pos                               1                                                         /*!< GIMA CAP2_2_IN: EDGE Position       */
#define GIMA_CAP2_2_IN_EDGE_Msk                               (0x01UL << GIMA_CAP2_2_IN_EDGE_Pos)                       /*!< GIMA CAP2_2_IN: EDGE Mask           */
#define GIMA_CAP2_2_IN_SYNCH_Pos                              2                                                         /*!< GIMA CAP2_2_IN: SYNCH Position      */
#define GIMA_CAP2_2_IN_SYNCH_Msk                              (0x01UL << GIMA_CAP2_2_IN_SYNCH_Pos)                      /*!< GIMA CAP2_2_IN: SYNCH Mask          */
#define GIMA_CAP2_2_IN_PULSE_Pos                              3                                                         /*!< GIMA CAP2_2_IN: PULSE Position      */
#define GIMA_CAP2_2_IN_PULSE_Msk                              (0x01UL << GIMA_CAP2_2_IN_PULSE_Pos)                      /*!< GIMA CAP2_2_IN: PULSE Mask          */
#define GIMA_CAP2_2_IN_SELECT_Pos                             4                                                         /*!< GIMA CAP2_2_IN: SELECT Position     */
#define GIMA_CAP2_2_IN_SELECT_Msk                             (0x0fUL << GIMA_CAP2_2_IN_SELECT_Pos)                     /*!< GIMA CAP2_2_IN: SELECT Mask         */

// -------------------------------------  GIMA_CAP2_3_IN  -----------------------------------------
#define GIMA_CAP2_3_IN_INV_Pos                                0                                                         /*!< GIMA CAP2_3_IN: INV Position        */
#define GIMA_CAP2_3_IN_INV_Msk                                (0x01UL << GIMA_CAP2_3_IN_INV_Pos)                        /*!< GIMA CAP2_3_IN: INV Mask            */
#define GIMA_CAP2_3_IN_EDGE_Pos                               1                                                         /*!< GIMA CAP2_3_IN: EDGE Position       */
#define GIMA_CAP2_3_IN_EDGE_Msk                               (0x01UL << GIMA_CAP2_3_IN_EDGE_Pos)                       /*!< GIMA CAP2_3_IN: EDGE Mask           */
#define GIMA_CAP2_3_IN_SYNCH_Pos                              2                                                         /*!< GIMA CAP2_3_IN: SYNCH Position      */
#define GIMA_CAP2_3_IN_SYNCH_Msk                              (0x01UL << GIMA_CAP2_3_IN_SYNCH_Pos)                      /*!< GIMA CAP2_3_IN: SYNCH Mask          */
#define GIMA_CAP2_3_IN_PULSE_Pos                              3                                                         /*!< GIMA CAP2_3_IN: PULSE Position      */
#define GIMA_CAP2_3_IN_PULSE_Msk                              (0x01UL << GIMA_CAP2_3_IN_PULSE_Pos)                      /*!< GIMA CAP2_3_IN: PULSE Mask          */
#define GIMA_CAP2_3_IN_SELECT_Pos                             4                                                         /*!< GIMA CAP2_3_IN: SELECT Position     */
#define GIMA_CAP2_3_IN_SELECT_Msk                             (0x0fUL << GIMA_CAP2_3_IN_SELECT_Pos)                     /*!< GIMA CAP2_3_IN: SELECT Mask         */

// -------------------------------------  GIMA_CAP3_0_IN  -----------------------------------------
#define GIMA_CAP3_0_IN_INV_Pos                                0                                                         /*!< GIMA CAP3_0_IN: INV Position        */
#define GIMA_CAP3_0_IN_INV_Msk                                (0x01UL << GIMA_CAP3_0_IN_INV_Pos)                        /*!< GIMA CAP3_0_IN: INV Mask            */
#define GIMA_CAP3_0_IN_EDGE_Pos                               1                                                         /*!< GIMA CAP3_0_IN: EDGE Position       */
#define GIMA_CAP3_0_IN_EDGE_Msk                               (0x01UL << GIMA_CAP3_0_IN_EDGE_Pos)                       /*!< GIMA CAP3_0_IN: EDGE Mask           */
#define GIMA_CAP3_0_IN_SYNCH_Pos                              2                                                         /*!< GIMA CAP3_0_IN: SYNCH Position      */
#define GIMA_CAP3_0_IN_SYNCH_Msk                              (0x01UL << GIMA_CAP3_0_IN_SYNCH_Pos)                      /*!< GIMA CAP3_0_IN: SYNCH Mask          */
#define GIMA_CAP3_0_IN_PULSE_Pos                              3                                                         /*!< GIMA CAP3_0_IN: PULSE Position      */
#define GIMA_CAP3_0_IN_PULSE_Msk                              (0x01UL << GIMA_CAP3_0_IN_PULSE_Pos)                      /*!< GIMA CAP3_0_IN: PULSE Mask          */
#define GIMA_CAP3_0_IN_SELECT_Pos                             4                                                         /*!< GIMA CAP3_0_IN: SELECT Position     */
#define GIMA_CAP3_0_IN_SELECT_Msk                             (0x0fUL << GIMA_CAP3_0_IN_SELECT_Pos)                     /*!< GIMA CAP3_0_IN: SELECT Mask         */

// -------------------------------------  GIMA_CAP3_1_IN  -----------------------------------------
#define GIMA_CAP3_1_IN_INV_Pos                                0                                                         /*!< GIMA CAP3_1_IN: INV Position        */
#define GIMA_CAP3_1_IN_INV_Msk                                (0x01UL << GIMA_CAP3_1_IN_INV_Pos)                        /*!< GIMA CAP3_1_IN: INV Mask            */
#define GIMA_CAP3_1_IN_EDGE_Pos                               1                                                         /*!< GIMA CAP3_1_IN: EDGE Position       */
#define GIMA_CAP3_1_IN_EDGE_Msk                               (0x01UL << GIMA_CAP3_1_IN_EDGE_Pos)                       /*!< GIMA CAP3_1_IN: EDGE Mask           */
#define GIMA_CAP3_1_IN_SYNCH_Pos                              2                                                         /*!< GIMA CAP3_1_IN: SYNCH Position      */
#define GIMA_CAP3_1_IN_SYNCH_Msk                              (0x01UL << GIMA_CAP3_1_IN_SYNCH_Pos)                      /*!< GIMA CAP3_1_IN: SYNCH Mask          */
#define GIMA_CAP3_1_IN_PULSE_Pos                              3                                                         /*!< GIMA CAP3_1_IN: PULSE Position      */
#define GIMA_CAP3_1_IN_PULSE_Msk                              (0x01UL << GIMA_CAP3_1_IN_PULSE_Pos)                      /*!< GIMA CAP3_1_IN: PULSE Mask          */
#define GIMA_CAP3_1_IN_SELECT_Pos                             4                                                         /*!< GIMA CAP3_1_IN: SELECT Position     */
#define GIMA_CAP3_1_IN_SELECT_Msk                             (0x0fUL << GIMA_CAP3_1_IN_SELECT_Pos)                     /*!< GIMA CAP3_1_IN: SELECT Mask         */

// -------------------------------------  GIMA_CAP3_2_IN  -----------------------------------------
#define GIMA_CAP3_2_IN_INV_Pos                                0                                                         /*!< GIMA CAP3_2_IN: INV Position        */
#define GIMA_CAP3_2_IN_INV_Msk                                (0x01UL << GIMA_CAP3_2_IN_INV_Pos)                        /*!< GIMA CAP3_2_IN: INV Mask            */
#define GIMA_CAP3_2_IN_EDGE_Pos                               1                                                         /*!< GIMA CAP3_2_IN: EDGE Position       */
#define GIMA_CAP3_2_IN_EDGE_Msk                               (0x01UL << GIMA_CAP3_2_IN_EDGE_Pos)                       /*!< GIMA CAP3_2_IN: EDGE Mask           */
#define GIMA_CAP3_2_IN_SYNCH_Pos                              2                                                         /*!< GIMA CAP3_2_IN: SYNCH Position      */
#define GIMA_CAP3_2_IN_SYNCH_Msk                              (0x01UL << GIMA_CAP3_2_IN_SYNCH_Pos)                      /*!< GIMA CAP3_2_IN: SYNCH Mask          */
#define GIMA_CAP3_2_IN_PULSE_Pos                              3                                                         /*!< GIMA CAP3_2_IN: PULSE Position      */
#define GIMA_CAP3_2_IN_PULSE_Msk                              (0x01UL << GIMA_CAP3_2_IN_PULSE_Pos)                      /*!< GIMA CAP3_2_IN: PULSE Mask          */
#define GIMA_CAP3_2_IN_SELECT_Pos                             4                                                         /*!< GIMA CAP3_2_IN: SELECT Position     */
#define GIMA_CAP3_2_IN_SELECT_Msk                             (0x0fUL << GIMA_CAP3_2_IN_SELECT_Pos)                     /*!< GIMA CAP3_2_IN: SELECT Mask         */

// -------------------------------------  GIMA_CAP3_3_IN  -----------------------------------------
#define GIMA_CAP3_3_IN_INV_Pos                                0                                                         /*!< GIMA CAP3_3_IN: INV Position        */
#define GIMA_CAP3_3_IN_INV_Msk                                (0x01UL << GIMA_CAP3_3_IN_INV_Pos)                        /*!< GIMA CAP3_3_IN: INV Mask            */
#define GIMA_CAP3_3_IN_EDGE_Pos                               1                                                         /*!< GIMA CAP3_3_IN: EDGE Position       */
#define GIMA_CAP3_3_IN_EDGE_Msk                               (0x01UL << GIMA_CAP3_3_IN_EDGE_Pos)                       /*!< GIMA CAP3_3_IN: EDGE Mask           */
#define GIMA_CAP3_3_IN_SYNCH_Pos                              2                                                         /*!< GIMA CAP3_3_IN: SYNCH Position      */
#define GIMA_CAP3_3_IN_SYNCH_Msk                              (0x01UL << GIMA_CAP3_3_IN_SYNCH_Pos)                      /*!< GIMA CAP3_3_IN: SYNCH Mask          */
#define GIMA_CAP3_3_IN_PULSE_Pos                              3                                                         /*!< GIMA CAP3_3_IN: PULSE Position      */
#define GIMA_CAP3_3_IN_PULSE_Msk                              (0x01UL << GIMA_CAP3_3_IN_PULSE_Pos)                      /*!< GIMA CAP3_3_IN: PULSE Mask          */
#define GIMA_CAP3_3_IN_SELECT_Pos                             4                                                         /*!< GIMA CAP3_3_IN: SELECT Position     */
#define GIMA_CAP3_3_IN_SELECT_Msk                             (0x0fUL << GIMA_CAP3_3_IN_SELECT_Pos)                     /*!< GIMA CAP3_3_IN: SELECT Mask         */

// -------------------------------------  GIMA_CTIN_0_IN  -----------------------------------------
#define GIMA_CTIN_0_IN_INV_Pos                                0                                                         /*!< GIMA CTIN_0_IN: INV Position        */
#define GIMA_CTIN_0_IN_INV_Msk                                (0x01UL << GIMA_CTIN_0_IN_INV_Pos)                        /*!< GIMA CTIN_0_IN: INV Mask            */
#define GIMA_CTIN_0_IN_EDGE_Pos                               1                                                         /*!< GIMA CTIN_0_IN: EDGE Position       */
#define GIMA_CTIN_0_IN_EDGE_Msk                               (0x01UL << GIMA_CTIN_0_IN_EDGE_Pos)                       /*!< GIMA CTIN_0_IN: EDGE Mask           */
#define GIMA_CTIN_0_IN_SYNCH_Pos                              2                                                         /*!< GIMA CTIN_0_IN: SYNCH Position      */
#define GIMA_CTIN_0_IN_SYNCH_Msk                              (0x01UL << GIMA_CTIN_0_IN_SYNCH_Pos)                      /*!< GIMA CTIN_0_IN: SYNCH Mask          */
#define GIMA_CTIN_0_IN_PULSE_Pos                              3                                                         /*!< GIMA CTIN_0_IN: PULSE Position      */
#define GIMA_CTIN_0_IN_PULSE_Msk                              (0x01UL << GIMA_CTIN_0_IN_PULSE_Pos)                      /*!< GIMA CTIN_0_IN: PULSE Mask          */
#define GIMA_CTIN_0_IN_SELECT_Pos                             4                                                         /*!< GIMA CTIN_0_IN: SELECT Position     */
#define GIMA_CTIN_0_IN_SELECT_Msk                             (0x0fUL << GIMA_CTIN_0_IN_SELECT_Pos)                     /*!< GIMA CTIN_0_IN: SELECT Mask         */

// -------------------------------------  GIMA_CTIN_1_IN  -----------------------------------------
#define GIMA_CTIN_1_IN_INV_Pos                                0                                                         /*!< GIMA CTIN_1_IN: INV Position        */
#define GIMA_CTIN_1_IN_INV_Msk                                (0x01UL << GIMA_CTIN_1_IN_INV_Pos)                        /*!< GIMA CTIN_1_IN: INV Mask            */
#define GIMA_CTIN_1_IN_EDGE_Pos                               1                                                         /*!< GIMA CTIN_1_IN: EDGE Position       */
#define GIMA_CTIN_1_IN_EDGE_Msk                               (0x01UL << GIMA_CTIN_1_IN_EDGE_Pos)                       /*!< GIMA CTIN_1_IN: EDGE Mask           */
#define GIMA_CTIN_1_IN_SYNCH_Pos                              2                                                         /*!< GIMA CTIN_1_IN: SYNCH Position      */
#define GIMA_CTIN_1_IN_SYNCH_Msk                              (0x01UL << GIMA_CTIN_1_IN_SYNCH_Pos)                      /*!< GIMA CTIN_1_IN: SYNCH Mask          */
#define GIMA_CTIN_1_IN_PULSE_Pos                              3                                                         /*!< GIMA CTIN_1_IN: PULSE Position      */
#define GIMA_CTIN_1_IN_PULSE_Msk                              (0x01UL << GIMA_CTIN_1_IN_PULSE_Pos)                      /*!< GIMA CTIN_1_IN: PULSE Mask          */
#define GIMA_CTIN_1_IN_SELECT_Pos                             4                                                         /*!< GIMA CTIN_1_IN: SELECT Position     */
#define GIMA_CTIN_1_IN_SELECT_Msk                             (0x0fUL << GIMA_CTIN_1_IN_SELECT_Pos)                     /*!< GIMA CTIN_1_IN: SELECT Mask         */

// -------------------------------------  GIMA_CTIN_2_IN  -----------------------------------------
#define GIMA_CTIN_2_IN_INV_Pos                                0                                                         /*!< GIMA CTIN_2_IN: INV Position        */
#define GIMA_CTIN_2_IN_INV_Msk                                (0x01UL << GIMA_CTIN_2_IN_INV_Pos)                        /*!< GIMA CTIN_2_IN: INV Mask            */
#define GIMA_CTIN_2_IN_EDGE_Pos                               1                                                         /*!< GIMA CTIN_2_IN: EDGE Position       */
#define GIMA_CTIN_2_IN_EDGE_Msk                               (0x01UL << GIMA_CTIN_2_IN_EDGE_Pos)                       /*!< GIMA CTIN_2_IN: EDGE Mask           */
#define GIMA_CTIN_2_IN_SYNCH_Pos                              2                                                         /*!< GIMA CTIN_2_IN: SYNCH Position      */
#define GIMA_CTIN_2_IN_SYNCH_Msk                              (0x01UL << GIMA_CTIN_2_IN_SYNCH_Pos)                      /*!< GIMA CTIN_2_IN: SYNCH Mask          */
#define GIMA_CTIN_2_IN_PULSE_Pos                              3                                                         /*!< GIMA CTIN_2_IN: PULSE Position      */
#define GIMA_CTIN_2_IN_PULSE_Msk                              (0x01UL << GIMA_CTIN_2_IN_PULSE_Pos)                      /*!< GIMA CTIN_2_IN: PULSE Mask          */
#define GIMA_CTIN_2_IN_SELECT_Pos                             4                                                         /*!< GIMA CTIN_2_IN: SELECT Position     */
#define GIMA_CTIN_2_IN_SELECT_Msk                             (0x0fUL << GIMA_CTIN_2_IN_SELECT_Pos)                     /*!< GIMA CTIN_2_IN: SELECT Mask         */

// -------------------------------------  GIMA_CTIN_3_IN  -----------------------------------------
#define GIMA_CTIN_3_IN_INV_Pos                                0                                                         /*!< GIMA CTIN_3_IN: INV Position        */
#define GIMA_CTIN_3_IN_INV_Msk                                (0x01UL << GIMA_CTIN_3_IN_INV_Pos)                        /*!< GIMA CTIN_3_IN: INV Mask            */
#define GIMA_CTIN_3_IN_EDGE_Pos                               1                                                         /*!< GIMA CTIN_3_IN: EDGE Position       */
#define GIMA_CTIN_3_IN_EDGE_Msk                               (0x01UL << GIMA_CTIN_3_IN_EDGE_Pos)                       /*!< GIMA CTIN_3_IN: EDGE Mask           */
#define GIMA_CTIN_3_IN_SYNCH_Pos                              2                                                         /*!< GIMA CTIN_3_IN: SYNCH Position      */
#define GIMA_CTIN_3_IN_SYNCH_Msk                              (0x01UL << GIMA_CTIN_3_IN_SYNCH_Pos)                      /*!< GIMA CTIN_3_IN: SYNCH Mask          */
#define GIMA_CTIN_3_IN_PULSE_Pos                              3                                                         /*!< GIMA CTIN_3_IN: PULSE Position      */
#define GIMA_CTIN_3_IN_PULSE_Msk                              (0x01UL << GIMA_CTIN_3_IN_PULSE_Pos)                      /*!< GIMA CTIN_3_IN: PULSE Mask          */
#define GIMA_CTIN_3_IN_SELECT_Pos                             4                                                         /*!< GIMA CTIN_3_IN: SELECT Position     */
#define GIMA_CTIN_3_IN_SELECT_Msk                             (0x0fUL << GIMA_CTIN_3_IN_SELECT_Pos)                     /*!< GIMA CTIN_3_IN: SELECT Mask         */

// -------------------------------------  GIMA_CTIN_4_IN  -----------------------------------------
#define GIMA_CTIN_4_IN_INV_Pos                                0                                                         /*!< GIMA CTIN_4_IN: INV Position        */
#define GIMA_CTIN_4_IN_INV_Msk                                (0x01UL << GIMA_CTIN_4_IN_INV_Pos)                        /*!< GIMA CTIN_4_IN: INV Mask            */
#define GIMA_CTIN_4_IN_EDGE_Pos                               1                                                         /*!< GIMA CTIN_4_IN: EDGE Position       */
#define GIMA_CTIN_4_IN_EDGE_Msk                               (0x01UL << GIMA_CTIN_4_IN_EDGE_Pos)                       /*!< GIMA CTIN_4_IN: EDGE Mask           */
#define GIMA_CTIN_4_IN_SYNCH_Pos                              2                                                         /*!< GIMA CTIN_4_IN: SYNCH Position      */
#define GIMA_CTIN_4_IN_SYNCH_Msk                              (0x01UL << GIMA_CTIN_4_IN_SYNCH_Pos)                      /*!< GIMA CTIN_4_IN: SYNCH Mask          */
#define GIMA_CTIN_4_IN_PULSE_Pos                              3                                                         /*!< GIMA CTIN_4_IN: PULSE Position      */
#define GIMA_CTIN_4_IN_PULSE_Msk                              (0x01UL << GIMA_CTIN_4_IN_PULSE_Pos)                      /*!< GIMA CTIN_4_IN: PULSE Mask          */
#define GIMA_CTIN_4_IN_SELECT_Pos                             4                                                         /*!< GIMA CTIN_4_IN: SELECT Position     */
#define GIMA_CTIN_4_IN_SELECT_Msk                             (0x0fUL << GIMA_CTIN_4_IN_SELECT_Pos)                     /*!< GIMA CTIN_4_IN: SELECT Mask         */

// -------------------------------------  GIMA_CTIN_5_IN  -----------------------------------------
#define GIMA_CTIN_5_IN_INV_Pos                                0                                                         /*!< GIMA CTIN_5_IN: INV Position        */
#define GIMA_CTIN_5_IN_INV_Msk                                (0x01UL << GIMA_CTIN_5_IN_INV_Pos)                        /*!< GIMA CTIN_5_IN: INV Mask            */
#define GIMA_CTIN_5_IN_EDGE_Pos                               1                                                         /*!< GIMA CTIN_5_IN: EDGE Position       */
#define GIMA_CTIN_5_IN_EDGE_Msk                               (0x01UL << GIMA_CTIN_5_IN_EDGE_Pos)                       /*!< GIMA CTIN_5_IN: EDGE Mask           */
#define GIMA_CTIN_5_IN_SYNCH_Pos                              2                                                         /*!< GIMA CTIN_5_IN: SYNCH Position      */
#define GIMA_CTIN_5_IN_SYNCH_Msk                              (0x01UL << GIMA_CTIN_5_IN_SYNCH_Pos)                      /*!< GIMA CTIN_5_IN: SYNCH Mask          */
#define GIMA_CTIN_5_IN_PULSE_Pos                              3                                                         /*!< GIMA CTIN_5_IN: PULSE Position      */
#define GIMA_CTIN_5_IN_PULSE_Msk                              (0x01UL << GIMA_CTIN_5_IN_PULSE_Pos)                      /*!< GIMA CTIN_5_IN: PULSE Mask          */
#define GIMA_CTIN_5_IN_SELECT_Pos                             4                                                         /*!< GIMA CTIN_5_IN: SELECT Position     */
#define GIMA_CTIN_5_IN_SELECT_Msk                             (0x0fUL << GIMA_CTIN_5_IN_SELECT_Pos)                     /*!< GIMA CTIN_5_IN: SELECT Mask         */

// -------------------------------------  GIMA_CTIN_6_IN  -----------------------------------------
#define GIMA_CTIN_6_IN_INV_Pos                                0                                                         /*!< GIMA CTIN_6_IN: INV Position        */
#define GIMA_CTIN_6_IN_INV_Msk                                (0x01UL << GIMA_CTIN_6_IN_INV_Pos)                        /*!< GIMA CTIN_6_IN: INV Mask            */
#define GIMA_CTIN_6_IN_EDGE_Pos                               1                                                         /*!< GIMA CTIN_6_IN: EDGE Position       */
#define GIMA_CTIN_6_IN_EDGE_Msk                               (0x01UL << GIMA_CTIN_6_IN_EDGE_Pos)                       /*!< GIMA CTIN_6_IN: EDGE Mask           */
#define GIMA_CTIN_6_IN_SYNCH_Pos                              2                                                         /*!< GIMA CTIN_6_IN: SYNCH Position      */
#define GIMA_CTIN_6_IN_SYNCH_Msk                              (0x01UL << GIMA_CTIN_6_IN_SYNCH_Pos)                      /*!< GIMA CTIN_6_IN: SYNCH Mask          */
#define GIMA_CTIN_6_IN_PULSE_Pos                              3                                                         /*!< GIMA CTIN_6_IN: PULSE Position      */
#define GIMA_CTIN_6_IN_PULSE_Msk                              (0x01UL << GIMA_CTIN_6_IN_PULSE_Pos)                      /*!< GIMA CTIN_6_IN: PULSE Mask          */
#define GIMA_CTIN_6_IN_SELECT_Pos                             4                                                         /*!< GIMA CTIN_6_IN: SELECT Position     */
#define GIMA_CTIN_6_IN_SELECT_Msk                             (0x0fUL << GIMA_CTIN_6_IN_SELECT_Pos)                     /*!< GIMA CTIN_6_IN: SELECT Mask         */

// -------------------------------------  GIMA_CTIN_7_IN  -----------------------------------------
#define GIMA_CTIN_7_IN_INV_Pos                                0                                                         /*!< GIMA CTIN_7_IN: INV Position        */
#define GIMA_CTIN_7_IN_INV_Msk                                (0x01UL << GIMA_CTIN_7_IN_INV_Pos)                        /*!< GIMA CTIN_7_IN: INV Mask            */
#define GIMA_CTIN_7_IN_EDGE_Pos                               1                                                         /*!< GIMA CTIN_7_IN: EDGE Position       */
#define GIMA_CTIN_7_IN_EDGE_Msk                               (0x01UL << GIMA_CTIN_7_IN_EDGE_Pos)                       /*!< GIMA CTIN_7_IN: EDGE Mask           */
#define GIMA_CTIN_7_IN_SYNCH_Pos                              2                                                         /*!< GIMA CTIN_7_IN: SYNCH Position      */
#define GIMA_CTIN_7_IN_SYNCH_Msk                              (0x01UL << GIMA_CTIN_7_IN_SYNCH_Pos)                      /*!< GIMA CTIN_7_IN: SYNCH Mask          */
#define GIMA_CTIN_7_IN_PULSE_Pos                              3                                                         /*!< GIMA CTIN_7_IN: PULSE Position      */
#define GIMA_CTIN_7_IN_PULSE_Msk                              (0x01UL << GIMA_CTIN_7_IN_PULSE_Pos)                      /*!< GIMA CTIN_7_IN: PULSE Mask          */
#define GIMA_CTIN_7_IN_SELECT_Pos                             4                                                         /*!< GIMA CTIN_7_IN: SELECT Position     */
#define GIMA_CTIN_7_IN_SELECT_Msk                             (0x0fUL << GIMA_CTIN_7_IN_SELECT_Pos)                     /*!< GIMA CTIN_7_IN: SELECT Mask         */

// ----------------------------------  GIMA_VADC_TRIGGER_IN  --------------------------------------
#define GIMA_VADC_TRIGGER_IN_INV_Pos                          0                                                         /*!< GIMA VADC_TRIGGER_IN: INV Position  */
#define GIMA_VADC_TRIGGER_IN_INV_Msk                          (0x01UL << GIMA_VADC_TRIGGER_IN_INV_Pos)                  /*!< GIMA VADC_TRIGGER_IN: INV Mask      */
#define GIMA_VADC_TRIGGER_IN_EDGE_Pos                         1                                                         /*!< GIMA VADC_TRIGGER_IN: EDGE Position */
#define GIMA_VADC_TRIGGER_IN_EDGE_Msk                         (0x01UL << GIMA_VADC_TRIGGER_IN_EDGE_Pos)                 /*!< GIMA VADC_TRIGGER_IN: EDGE Mask     */
#define GIMA_VADC_TRIGGER_IN_SYNCH_Pos                        2                                                         /*!< GIMA VADC_TRIGGER_IN: SYNCH Position */
#define GIMA_VADC_TRIGGER_IN_SYNCH_Msk                        (0x01UL << GIMA_VADC_TRIGGER_IN_SYNCH_Pos)                /*!< GIMA VADC_TRIGGER_IN: SYNCH Mask    */
#define GIMA_VADC_TRIGGER_IN_PULSE_Pos                        3                                                         /*!< GIMA VADC_TRIGGER_IN: PULSE Position */
#define GIMA_VADC_TRIGGER_IN_PULSE_Msk                        (0x01UL << GIMA_VADC_TRIGGER_IN_PULSE_Pos)                /*!< GIMA VADC_TRIGGER_IN: PULSE Mask    */
#define GIMA_VADC_TRIGGER_IN_SELECT_Pos                       4                                                         /*!< GIMA VADC_TRIGGER_IN: SELECT Position */
#define GIMA_VADC_TRIGGER_IN_SELECT_Msk                       (0x0fUL << GIMA_VADC_TRIGGER_IN_SELECT_Pos)               /*!< GIMA VADC_TRIGGER_IN: SELECT Mask   */

// ---------------------------------  GIMA_EVENTROUTER_13_IN  -------------------------------------
#define GIMA_EVENTROUTER_13_IN_INV_Pos                        0                                                         /*!< GIMA EVENTROUTER_13_IN: INV Position */
#define GIMA_EVENTROUTER_13_IN_INV_Msk                        (0x01UL << GIMA_EVENTROUTER_13_IN_INV_Pos)                /*!< GIMA EVENTROUTER_13_IN: INV Mask    */
#define GIMA_EVENTROUTER_13_IN_EDGE_Pos                       1                                                         /*!< GIMA EVENTROUTER_13_IN: EDGE Position */
#define GIMA_EVENTROUTER_13_IN_EDGE_Msk                       (0x01UL << GIMA_EVENTROUTER_13_IN_EDGE_Pos)               /*!< GIMA EVENTROUTER_13_IN: EDGE Mask   */
#define GIMA_EVENTROUTER_13_IN_SYNCH_Pos                      2                                                         /*!< GIMA EVENTROUTER_13_IN: SYNCH Position */
#define GIMA_EVENTROUTER_13_IN_SYNCH_Msk                      (0x01UL << GIMA_EVENTROUTER_13_IN_SYNCH_Pos)              /*!< GIMA EVENTROUTER_13_IN: SYNCH Mask  */
#define GIMA_EVENTROUTER_13_IN_PULSE_Pos                      3                                                         /*!< GIMA EVENTROUTER_13_IN: PULSE Position */
#define GIMA_EVENTROUTER_13_IN_PULSE_Msk                      (0x01UL << GIMA_EVENTROUTER_13_IN_PULSE_Pos)              /*!< GIMA EVENTROUTER_13_IN: PULSE Mask  */
#define GIMA_EVENTROUTER_13_IN_SELECT_Pos                     4                                                         /*!< GIMA EVENTROUTER_13_IN: SELECT Position */
#define GIMA_EVENTROUTER_13_IN_SELECT_Msk                     (0x0fUL << GIMA_EVENTROUTER_13_IN_SELECT_Pos)             /*!< GIMA EVENTROUTER_13_IN: SELECT Mask */

// ---------------------------------  GIMA_EVENTROUTER_14_IN  -------------------------------------
#define GIMA_EVENTROUTER_14_IN_INV_Pos                        0                                                         /*!< GIMA EVENTROUTER_14_IN: INV Position */
#define GIMA_EVENTROUTER_14_IN_INV_Msk                        (0x01UL << GIMA_EVENTROUTER_14_IN_INV_Pos)                /*!< GIMA EVENTROUTER_14_IN: INV Mask    */
#define GIMA_EVENTROUTER_14_IN_EDGE_Pos                       1                                                         /*!< GIMA EVENTROUTER_14_IN: EDGE Position */
#define GIMA_EVENTROUTER_14_IN_EDGE_Msk                       (0x01UL << GIMA_EVENTROUTER_14_IN_EDGE_Pos)               /*!< GIMA EVENTROUTER_14_IN: EDGE Mask   */
#define GIMA_EVENTROUTER_14_IN_SYNCH_Pos                      2                                                         /*!< GIMA EVENTROUTER_14_IN: SYNCH Position */
#define GIMA_EVENTROUTER_14_IN_SYNCH_Msk                      (0x01UL << GIMA_EVENTROUTER_14_IN_SYNCH_Pos)              /*!< GIMA EVENTROUTER_14_IN: SYNCH Mask  */
#define GIMA_EVENTROUTER_14_IN_PULSE_Pos                      3                                                         /*!< GIMA EVENTROUTER_14_IN: PULSE Position */
#define GIMA_EVENTROUTER_14_IN_PULSE_Msk                      (0x01UL << GIMA_EVENTROUTER_14_IN_PULSE_Pos)              /*!< GIMA EVENTROUTER_14_IN: PULSE Mask  */
#define GIMA_EVENTROUTER_14_IN_SELECT_Pos                     4                                                         /*!< GIMA EVENTROUTER_14_IN: SELECT Position */
#define GIMA_EVENTROUTER_14_IN_SELECT_Msk                     (0x0fUL << GIMA_EVENTROUTER_14_IN_SELECT_Pos)             /*!< GIMA EVENTROUTER_14_IN: SELECT Mask */

// ---------------------------------  GIMA_EVENTROUTER_16_IN  -------------------------------------
#define GIMA_EVENTROUTER_16_IN_INV_Pos                        0                                                         /*!< GIMA EVENTROUTER_16_IN: INV Position */
#define GIMA_EVENTROUTER_16_IN_INV_Msk                        (0x01UL << GIMA_EVENTROUTER_16_IN_INV_Pos)                /*!< GIMA EVENTROUTER_16_IN: INV Mask    */
#define GIMA_EVENTROUTER_16_IN_EDGE_Pos                       1                                                         /*!< GIMA EVENTROUTER_16_IN: EDGE Position */
#define GIMA_EVENTROUTER_16_IN_EDGE_Msk                       (0x01UL << GIMA_EVENTROUTER_16_IN_EDGE_Pos)               /*!< GIMA EVENTROUTER_16_IN: EDGE Mask   */
#define GIMA_EVENTROUTER_16_IN_SYNCH_Pos                      2                                                         /*!< GIMA EVENTROUTER_16_IN: SYNCH Position */
#define GIMA_EVENTROUTER_16_IN_SYNCH_Msk                      (0x01UL << GIMA_EVENTROUTER_16_IN_SYNCH_Pos)              /*!< GIMA EVENTROUTER_16_IN: SYNCH Mask  */
#define GIMA_EVENTROUTER_16_IN_PULSE_Pos                      3                                                         /*!< GIMA EVENTROUTER_16_IN: PULSE Position */
#define GIMA_EVENTROUTER_16_IN_PULSE_Msk                      (0x01UL << GIMA_EVENTROUTER_16_IN_PULSE_Pos)              /*!< GIMA EVENTROUTER_16_IN: PULSE Mask  */
#define GIMA_EVENTROUTER_16_IN_SELECT_Pos                     4                                                         /*!< GIMA EVENTROUTER_16_IN: SELECT Position */
#define GIMA_EVENTROUTER_16_IN_SELECT_Msk                     (0x0fUL << GIMA_EVENTROUTER_16_IN_SELECT_Pos)             /*!< GIMA EVENTROUTER_16_IN: SELECT Mask */

// ------------------------------------  GIMA_ADCSTART0_IN  ---------------------------------------
#define GIMA_ADCSTART0_IN_INV_Pos                             0                                                         /*!< GIMA ADCSTART0_IN: INV Position     */
#define GIMA_ADCSTART0_IN_INV_Msk                             (0x01UL << GIMA_ADCSTART0_IN_INV_Pos)                     /*!< GIMA ADCSTART0_IN: INV Mask         */
#define GIMA_ADCSTART0_IN_EDGE_Pos                            1                                                         /*!< GIMA ADCSTART0_IN: EDGE Position    */
#define GIMA_ADCSTART0_IN_EDGE_Msk                            (0x01UL << GIMA_ADCSTART0_IN_EDGE_Pos)                    /*!< GIMA ADCSTART0_IN: EDGE Mask        */
#define GIMA_ADCSTART0_IN_SYNCH_Pos                           2                                                         /*!< GIMA ADCSTART0_IN: SYNCH Position   */
#define GIMA_ADCSTART0_IN_SYNCH_Msk                           (0x01UL << GIMA_ADCSTART0_IN_SYNCH_Pos)                   /*!< GIMA ADCSTART0_IN: SYNCH Mask       */
#define GIMA_ADCSTART0_IN_PULSE_Pos                           3                                                         /*!< GIMA ADCSTART0_IN: PULSE Position   */
#define GIMA_ADCSTART0_IN_PULSE_Msk                           (0x01UL << GIMA_ADCSTART0_IN_PULSE_Pos)                   /*!< GIMA ADCSTART0_IN: PULSE Mask       */
#define GIMA_ADCSTART0_IN_SELECT_Pos                          4                                                         /*!< GIMA ADCSTART0_IN: SELECT Position  */
#define GIMA_ADCSTART0_IN_SELECT_Msk                          (0x0fUL << GIMA_ADCSTART0_IN_SELECT_Pos)                  /*!< GIMA ADCSTART0_IN: SELECT Mask      */

// ------------------------------------  GIMA_ADCSTART1_IN  ---------------------------------------
#define GIMA_ADCSTART1_IN_INV_Pos                             0                                                         /*!< GIMA ADCSTART1_IN: INV Position     */
#define GIMA_ADCSTART1_IN_INV_Msk                             (0x01UL << GIMA_ADCSTART1_IN_INV_Pos)                     /*!< GIMA ADCSTART1_IN: INV Mask         */
#define GIMA_ADCSTART1_IN_EDGE_Pos                            1                                                         /*!< GIMA ADCSTART1_IN: EDGE Position    */
#define GIMA_ADCSTART1_IN_EDGE_Msk                            (0x01UL << GIMA_ADCSTART1_IN_EDGE_Pos)                    /*!< GIMA ADCSTART1_IN: EDGE Mask        */
#define GIMA_ADCSTART1_IN_SYNCH_Pos                           2                                                         /*!< GIMA ADCSTART1_IN: SYNCH Position   */
#define GIMA_ADCSTART1_IN_SYNCH_Msk                           (0x01UL << GIMA_ADCSTART1_IN_SYNCH_Pos)                   /*!< GIMA ADCSTART1_IN: SYNCH Mask       */
#define GIMA_ADCSTART1_IN_PULSE_Pos                           3                                                         /*!< GIMA ADCSTART1_IN: PULSE Position   */
#define GIMA_ADCSTART1_IN_PULSE_Msk                           (0x01UL << GIMA_ADCSTART1_IN_PULSE_Pos)                   /*!< GIMA ADCSTART1_IN: PULSE Mask       */
#define GIMA_ADCSTART1_IN_SELECT_Pos                          4                                                         /*!< GIMA ADCSTART1_IN: SELECT Position  */
#define GIMA_ADCSTART1_IN_SELECT_Msk                          (0x0fUL << GIMA_ADCSTART1_IN_SELECT_Pos)                  /*!< GIMA ADCSTART1_IN: SELECT Mask      */


// ------------------------------------------------------------------------------------------------
// -----                                  DAC Position & Mask                                 -----
// ------------------------------------------------------------------------------------------------


// -----------------------------------------  DAC_CR  ---------------------------------------------
#define DAC_CR_VALUE_Pos                                      6                                                         /*!< DAC CR: VALUE Position              */
#define DAC_CR_VALUE_Msk                                      (0x000003ffUL << DAC_CR_VALUE_Pos)                        /*!< DAC CR: VALUE Mask                  */
#define DAC_CR_BIAS_Pos                                       16                                                        /*!< DAC CR: BIAS Position               */
#define DAC_CR_BIAS_Msk                                       (0x01UL << DAC_CR_BIAS_Pos)                               /*!< DAC CR: BIAS Mask                   */

// ----------------------------------------  DAC_CTRL  --------------------------------------------
#define DAC_CTRL_INT_DMA_REQ_Pos                              0                                                         /*!< DAC CTRL: INT_DMA_REQ Position      */
#define DAC_CTRL_INT_DMA_REQ_Msk                              (0x01UL << DAC_CTRL_INT_DMA_REQ_Pos)                      /*!< DAC CTRL: INT_DMA_REQ Mask          */
#define DAC_CTRL_DBLBUF_ENA_Pos                               1                                                         /*!< DAC CTRL: DBLBUF_ENA Position       */
#define DAC_CTRL_DBLBUF_ENA_Msk                               (0x01UL << DAC_CTRL_DBLBUF_ENA_Pos)                       /*!< DAC CTRL: DBLBUF_ENA Mask           */
#define DAC_CTRL_CNT_ENA_Pos                                  2                                                         /*!< DAC CTRL: CNT_ENA Position          */
#define DAC_CTRL_CNT_ENA_Msk                                  (0x01UL << DAC_CTRL_CNT_ENA_Pos)                          /*!< DAC CTRL: CNT_ENA Mask              */
#define DAC_CTRL_DMA_ENA_Pos                                  3                                                         /*!< DAC CTRL: DMA_ENA Position          */
#define DAC_CTRL_DMA_ENA_Msk                                  (0x01UL << DAC_CTRL_DMA_ENA_Pos)                          /*!< DAC CTRL: DMA_ENA Mask              */

// ---------------------------------------  DAC_CNTVAL  -------------------------------------------
#define DAC_CNTVAL_VALUE_Pos                                  0                                                         /*!< DAC CNTVAL: VALUE Position          */
#define DAC_CNTVAL_VALUE_Msk                                  (0x0000ffffUL << DAC_CNTVAL_VALUE_Pos)                    /*!< DAC CNTVAL: VALUE Mask              */


// ------------------------------------------------------------------------------------------------
// -----                                C_CAN0 Position & Mask                                -----
// ------------------------------------------------------------------------------------------------


// ---------------------------------------  C_CAN0_CNTL  ------------------------------------------
#define C_CAN0_CNTL_INIT_Pos                                  0                                                         /*!< C_CAN0 CNTL: INIT Position          */
#define C_CAN0_CNTL_INIT_Msk                                  (0x01UL << C_CAN0_CNTL_INIT_Pos)                          /*!< C_CAN0 CNTL: INIT Mask              */
#define C_CAN0_CNTL_IE_Pos                                    1                                                         /*!< C_CAN0 CNTL: IE Position            */
#define C_CAN0_CNTL_IE_Msk                                    (0x01UL << C_CAN0_CNTL_IE_Pos)                            /*!< C_CAN0 CNTL: IE Mask                */
#define C_CAN0_CNTL_SIE_Pos                                   2                                                         /*!< C_CAN0 CNTL: SIE Position           */
#define C_CAN0_CNTL_SIE_Msk                                   (0x01UL << C_CAN0_CNTL_SIE_Pos)                           /*!< C_CAN0 CNTL: SIE Mask               */
#define C_CAN0_CNTL_EIE_Pos                                   3                                                         /*!< C_CAN0 CNTL: EIE Position           */
#define C_CAN0_CNTL_EIE_Msk                                   (0x01UL << C_CAN0_CNTL_EIE_Pos)                           /*!< C_CAN0 CNTL: EIE Mask               */
#define C_CAN0_CNTL_DAR_Pos                                   5                                                         /*!< C_CAN0 CNTL: DAR Position           */
#define C_CAN0_CNTL_DAR_Msk                                   (0x01UL << C_CAN0_CNTL_DAR_Pos)                           /*!< C_CAN0 CNTL: DAR Mask               */
#define C_CAN0_CNTL_CCE_Pos                                   6                                                         /*!< C_CAN0 CNTL: CCE Position           */
#define C_CAN0_CNTL_CCE_Msk                                   (0x01UL << C_CAN0_CNTL_CCE_Pos)                           /*!< C_CAN0 CNTL: CCE Mask               */
#define C_CAN0_CNTL_TEST_Pos                                  7                                                         /*!< C_CAN0 CNTL: TEST Position          */
#define C_CAN0_CNTL_TEST_Msk                                  (0x01UL << C_CAN0_CNTL_TEST_Pos)                          /*!< C_CAN0 CNTL: TEST Mask              */

// ---------------------------------------  C_CAN0_STAT  ------------------------------------------
#define C_CAN0_STAT_LEC_Pos                                   0                                                         /*!< C_CAN0 STAT: LEC Position           */
#define C_CAN0_STAT_LEC_Msk                                   (0x07UL << C_CAN0_STAT_LEC_Pos)                           /*!< C_CAN0 STAT: LEC Mask               */
#define C_CAN0_STAT_TXOK_Pos                                  3                                                         /*!< C_CAN0 STAT: TXOK Position          */
#define C_CAN0_STAT_TXOK_Msk                                  (0x01UL << C_CAN0_STAT_TXOK_Pos)                          /*!< C_CAN0 STAT: TXOK Mask              */
#define C_CAN0_STAT_RXOK_Pos                                  4                                                         /*!< C_CAN0 STAT: RXOK Position          */
#define C_CAN0_STAT_RXOK_Msk                                  (0x01UL << C_CAN0_STAT_RXOK_Pos)                          /*!< C_CAN0 STAT: RXOK Mask              */
#define C_CAN0_STAT_EPASS_Pos                                 5                                                         /*!< C_CAN0 STAT: EPASS Position         */
#define C_CAN0_STAT_EPASS_Msk                                 (0x01UL << C_CAN0_STAT_EPASS_Pos)                         /*!< C_CAN0 STAT: EPASS Mask             */
#define C_CAN0_STAT_EWARN_Pos                                 6                                                         /*!< C_CAN0 STAT: EWARN Position         */
#define C_CAN0_STAT_EWARN_Msk                                 (0x01UL << C_CAN0_STAT_EWARN_Pos)                         /*!< C_CAN0 STAT: EWARN Mask             */
#define C_CAN0_STAT_BOFF_Pos                                  7                                                         /*!< C_CAN0 STAT: BOFF Position          */
#define C_CAN0_STAT_BOFF_Msk                                  (0x01UL << C_CAN0_STAT_BOFF_Pos)                          /*!< C_CAN0 STAT: BOFF Mask              */

// ----------------------------------------  C_CAN0_EC  -------------------------------------------
#define C_CAN0_EC_TEC_7_0_Pos                                 0                                                         /*!< C_CAN0 EC: TEC_7_0 Position         */
#define C_CAN0_EC_TEC_7_0_Msk                                 (0x000000ffUL << C_CAN0_EC_TEC_7_0_Pos)                   /*!< C_CAN0 EC: TEC_7_0 Mask             */
#define C_CAN0_EC_REC_6_0_Pos                                 8                                                         /*!< C_CAN0 EC: REC_6_0 Position         */
#define C_CAN0_EC_REC_6_0_Msk                                 (0x7fUL << C_CAN0_EC_REC_6_0_Pos)                         /*!< C_CAN0 EC: REC_6_0 Mask             */
#define C_CAN0_EC_RP_Pos                                      15                                                        /*!< C_CAN0 EC: RP Position              */
#define C_CAN0_EC_RP_Msk                                      (0x01UL << C_CAN0_EC_RP_Pos)                              /*!< C_CAN0 EC: RP Mask                  */

// ----------------------------------------  C_CAN0_BT  -------------------------------------------
#define C_CAN0_BT_BRP_Pos                                     0                                                         /*!< C_CAN0 BT: BRP Position             */
#define C_CAN0_BT_BRP_Msk                                     (0x3fUL << C_CAN0_BT_BRP_Pos)                             /*!< C_CAN0 BT: BRP Mask                 */
#define C_CAN0_BT_SJW_Pos                                     6                                                         /*!< C_CAN0 BT: SJW Position             */
#define C_CAN0_BT_SJW_Msk                                     (0x03UL << C_CAN0_BT_SJW_Pos)                             /*!< C_CAN0 BT: SJW Mask                 */
#define C_CAN0_BT_TSEG1_Pos                                   8                                                         /*!< C_CAN0 BT: TSEG1 Position           */
#define C_CAN0_BT_TSEG1_Msk                                   (0x0fUL << C_CAN0_BT_TSEG1_Pos)                           /*!< C_CAN0 BT: TSEG1 Mask               */
#define C_CAN0_BT_TSEG2_Pos                                   12                                                        /*!< C_CAN0 BT: TSEG2 Position           */
#define C_CAN0_BT_TSEG2_Msk                                   (0x07UL << C_CAN0_BT_TSEG2_Pos)                           /*!< C_CAN0 BT: TSEG2 Mask               */

// ---------------------------------------  C_CAN0_INT  -------------------------------------------
#define C_CAN0_INT_INTID15_0_Pos                              0                                                         /*!< C_CAN0 INT: INTID15_0 Position      */
#define C_CAN0_INT_INTID15_0_Msk                              (0x0000ffffUL << C_CAN0_INT_INTID15_0_Pos)                /*!< C_CAN0 INT: INTID15_0 Mask          */

// ---------------------------------------  C_CAN0_TEST  ------------------------------------------
#define C_CAN0_TEST_BASIC_Pos                                 2                                                         /*!< C_CAN0 TEST: BASIC Position         */
#define C_CAN0_TEST_BASIC_Msk                                 (0x01UL << C_CAN0_TEST_BASIC_Pos)                         /*!< C_CAN0 TEST: BASIC Mask             */
#define C_CAN0_TEST_SILENT_Pos                                3                                                         /*!< C_CAN0 TEST: SILENT Position        */
#define C_CAN0_TEST_SILENT_Msk                                (0x01UL << C_CAN0_TEST_SILENT_Pos)                        /*!< C_CAN0 TEST: SILENT Mask            */
#define C_CAN0_TEST_LBACK_Pos                                 4                                                         /*!< C_CAN0 TEST: LBACK Position         */
#define C_CAN0_TEST_LBACK_Msk                                 (0x01UL << C_CAN0_TEST_LBACK_Pos)                         /*!< C_CAN0 TEST: LBACK Mask             */
#define C_CAN0_TEST_TX1_0_Pos                                 5                                                         /*!< C_CAN0 TEST: TX1_0 Position         */
#define C_CAN0_TEST_TX1_0_Msk                                 (0x03UL << C_CAN0_TEST_TX1_0_Pos)                         /*!< C_CAN0 TEST: TX1_0 Mask             */
#define C_CAN0_TEST_RX_Pos                                    7                                                         /*!< C_CAN0 TEST: RX Position            */
#define C_CAN0_TEST_RX_Msk                                    (0x01UL << C_CAN0_TEST_RX_Pos)                            /*!< C_CAN0 TEST: RX Mask                */

// ---------------------------------------  C_CAN0_BRPE  ------------------------------------------
#define C_CAN0_BRPE_BRPE_Pos                                  0                                                         /*!< C_CAN0 BRPE: BRPE Position          */
#define C_CAN0_BRPE_BRPE_Msk                                  (0x0fUL << C_CAN0_BRPE_BRPE_Pos)                          /*!< C_CAN0 BRPE: BRPE Mask              */

// ------------------------------------  C_CAN0_IF1_CMDREQ  ---------------------------------------
#define C_CAN0_IF1_CMDREQ_MESSNUM_Pos                         0                                                         /*!< C_CAN0 IF1_CMDREQ: MESSNUM Position */
#define C_CAN0_IF1_CMDREQ_MESSNUM_Msk                         (0x3fUL << C_CAN0_IF1_CMDREQ_MESSNUM_Pos)                 /*!< C_CAN0 IF1_CMDREQ: MESSNUM Mask     */
#define C_CAN0_IF1_CMDREQ_BUSY_Pos                            15                                                        /*!< C_CAN0 IF1_CMDREQ: BUSY Position    */
#define C_CAN0_IF1_CMDREQ_BUSY_Msk                            (0x01UL << C_CAN0_IF1_CMDREQ_BUSY_Pos)                    /*!< C_CAN0 IF1_CMDREQ: BUSY Mask        */

// -----------------------------------  C_CAN0_IF1_CMDMSK_R  --------------------------------------
#define C_CAN0_IF1_CMDMSK_R_DATA_B_Pos                        0                                                         /*!< C_CAN0 IF1_CMDMSK_R: DATA_B Position */
#define C_CAN0_IF1_CMDMSK_R_DATA_B_Msk                        (0x01UL << C_CAN0_IF1_CMDMSK_R_DATA_B_Pos)                /*!< C_CAN0 IF1_CMDMSK_R: DATA_B Mask    */
#define C_CAN0_IF1_CMDMSK_R_DATA_A_Pos                        1                                                         /*!< C_CAN0 IF1_CMDMSK_R: DATA_A Position */
#define C_CAN0_IF1_CMDMSK_R_DATA_A_Msk                        (0x01UL << C_CAN0_IF1_CMDMSK_R_DATA_A_Pos)                /*!< C_CAN0 IF1_CMDMSK_R: DATA_A Mask    */
#define C_CAN0_IF1_CMDMSK_R_NEWDAT_Pos                        2                                                         /*!< C_CAN0 IF1_CMDMSK_R: NEWDAT Position */
#define C_CAN0_IF1_CMDMSK_R_NEWDAT_Msk                        (0x01UL << C_CAN0_IF1_CMDMSK_R_NEWDAT_Pos)                /*!< C_CAN0 IF1_CMDMSK_R: NEWDAT Mask    */
#define C_CAN0_IF1_CMDMSK_R_CLRINTPND_Pos                     3                                                         /*!< C_CAN0 IF1_CMDMSK_R: CLRINTPND Position */
#define C_CAN0_IF1_CMDMSK_R_CLRINTPND_Msk                     (0x01UL << C_CAN0_IF1_CMDMSK_R_CLRINTPND_Pos)             /*!< C_CAN0 IF1_CMDMSK_R: CLRINTPND Mask */
#define C_CAN0_IF1_CMDMSK_R_CTRL_Pos                          4                                                         /*!< C_CAN0 IF1_CMDMSK_R: CTRL Position  */
#define C_CAN0_IF1_CMDMSK_R_CTRL_Msk                          (0x01UL << C_CAN0_IF1_CMDMSK_R_CTRL_Pos)                  /*!< C_CAN0 IF1_CMDMSK_R: CTRL Mask      */
#define C_CAN0_IF1_CMDMSK_R_ARB_Pos                           5                                                         /*!< C_CAN0 IF1_CMDMSK_R: ARB Position   */
#define C_CAN0_IF1_CMDMSK_R_ARB_Msk                           (0x01UL << C_CAN0_IF1_CMDMSK_R_ARB_Pos)                   /*!< C_CAN0 IF1_CMDMSK_R: ARB Mask       */
#define C_CAN0_IF1_CMDMSK_R_MASK_Pos                          6                                                         /*!< C_CAN0 IF1_CMDMSK_R: MASK Position  */
#define C_CAN0_IF1_CMDMSK_R_MASK_Msk                          (0x01UL << C_CAN0_IF1_CMDMSK_R_MASK_Pos)                  /*!< C_CAN0 IF1_CMDMSK_R: MASK Mask      */
#define C_CAN0_IF1_CMDMSK_R_WR_RD_Pos                         7                                                         /*!< C_CAN0 IF1_CMDMSK_R: WR_RD Position */
#define C_CAN0_IF1_CMDMSK_R_WR_RD_Msk                         (0x01UL << C_CAN0_IF1_CMDMSK_R_WR_RD_Pos)                 /*!< C_CAN0 IF1_CMDMSK_R: WR_RD Mask     */

// -----------------------------------  C_CAN0_IF1_CMDMSK_W  --------------------------------------
#define C_CAN0_IF1_CMDMSK_W_DATA_B_Pos                        0                                                         /*!< C_CAN0 IF1_CMDMSK_W: DATA_B Position */
#define C_CAN0_IF1_CMDMSK_W_DATA_B_Msk                        (0x01UL << C_CAN0_IF1_CMDMSK_W_DATA_B_Pos)                /*!< C_CAN0 IF1_CMDMSK_W: DATA_B Mask    */
#define C_CAN0_IF1_CMDMSK_W_DATA_A_Pos                        1                                                         /*!< C_CAN0 IF1_CMDMSK_W: DATA_A Position */
#define C_CAN0_IF1_CMDMSK_W_DATA_A_Msk                        (0x01UL << C_CAN0_IF1_CMDMSK_W_DATA_A_Pos)                /*!< C_CAN0 IF1_CMDMSK_W: DATA_A Mask    */
#define C_CAN0_IF1_CMDMSK_W_TXRQST_Pos                        2                                                         /*!< C_CAN0 IF1_CMDMSK_W: TXRQST Position */
#define C_CAN0_IF1_CMDMSK_W_TXRQST_Msk                        (0x01UL << C_CAN0_IF1_CMDMSK_W_TXRQST_Pos)                /*!< C_CAN0 IF1_CMDMSK_W: TXRQST Mask    */
#define C_CAN0_IF1_CMDMSK_W_CLRINTPND_Pos                     3                                                         /*!< C_CAN0 IF1_CMDMSK_W: CLRINTPND Position */
#define C_CAN0_IF1_CMDMSK_W_CLRINTPND_Msk                     (0x01UL << C_CAN0_IF1_CMDMSK_W_CLRINTPND_Pos)             /*!< C_CAN0 IF1_CMDMSK_W: CLRINTPND Mask */
#define C_CAN0_IF1_CMDMSK_W_CTRL_Pos                          4                                                         /*!< C_CAN0 IF1_CMDMSK_W: CTRL Position  */
#define C_CAN0_IF1_CMDMSK_W_CTRL_Msk                          (0x01UL << C_CAN0_IF1_CMDMSK_W_CTRL_Pos)                  /*!< C_CAN0 IF1_CMDMSK_W: CTRL Mask      */
#define C_CAN0_IF1_CMDMSK_W_ARB_Pos                           5                                                         /*!< C_CAN0 IF1_CMDMSK_W: ARB Position   */
#define C_CAN0_IF1_CMDMSK_W_ARB_Msk                           (0x01UL << C_CAN0_IF1_CMDMSK_W_ARB_Pos)                   /*!< C_CAN0 IF1_CMDMSK_W: ARB Mask       */
#define C_CAN0_IF1_CMDMSK_W_MASK_Pos                          6                                                         /*!< C_CAN0 IF1_CMDMSK_W: MASK Position  */
#define C_CAN0_IF1_CMDMSK_W_MASK_Msk                          (0x01UL << C_CAN0_IF1_CMDMSK_W_MASK_Pos)                  /*!< C_CAN0 IF1_CMDMSK_W: MASK Mask      */
#define C_CAN0_IF1_CMDMSK_W_WR_RD_Pos                         7                                                         /*!< C_CAN0 IF1_CMDMSK_W: WR_RD Position */
#define C_CAN0_IF1_CMDMSK_W_WR_RD_Msk                         (0x01UL << C_CAN0_IF1_CMDMSK_W_WR_RD_Pos)                 /*!< C_CAN0 IF1_CMDMSK_W: WR_RD Mask     */

// -------------------------------------  C_CAN0_IF1_MSK1  ----------------------------------------
#define C_CAN0_IF1_MSK1_MSK15_0_Pos                           0                                                         /*!< C_CAN0 IF1_MSK1: MSK15_0 Position   */
#define C_CAN0_IF1_MSK1_MSK15_0_Msk                           (0x0000ffffUL << C_CAN0_IF1_MSK1_MSK15_0_Pos)             /*!< C_CAN0 IF1_MSK1: MSK15_0 Mask       */

// -------------------------------------  C_CAN0_IF1_MSK2  ----------------------------------------
#define C_CAN0_IF1_MSK2_MSK28_16_Pos                          0                                                         /*!< C_CAN0 IF1_MSK2: MSK28_16 Position  */
#define C_CAN0_IF1_MSK2_MSK28_16_Msk                          (0x00001fffUL << C_CAN0_IF1_MSK2_MSK28_16_Pos)            /*!< C_CAN0 IF1_MSK2: MSK28_16 Mask      */
#define C_CAN0_IF1_MSK2_MDIR_Pos                              14                                                        /*!< C_CAN0 IF1_MSK2: MDIR Position      */
#define C_CAN0_IF1_MSK2_MDIR_Msk                              (0x01UL << C_CAN0_IF1_MSK2_MDIR_Pos)                      /*!< C_CAN0 IF1_MSK2: MDIR Mask          */
#define C_CAN0_IF1_MSK2_MXTD_Pos                              15                                                        /*!< C_CAN0 IF1_MSK2: MXTD Position      */
#define C_CAN0_IF1_MSK2_MXTD_Msk                              (0x01UL << C_CAN0_IF1_MSK2_MXTD_Pos)                      /*!< C_CAN0 IF1_MSK2: MXTD Mask          */

// -------------------------------------  C_CAN0_IF1_ARB1  ----------------------------------------
#define C_CAN0_IF1_ARB1_ID15_0_Pos                            0                                                         /*!< C_CAN0 IF1_ARB1: ID15_0 Position    */
#define C_CAN0_IF1_ARB1_ID15_0_Msk                            (0x0000ffffUL << C_CAN0_IF1_ARB1_ID15_0_Pos)              /*!< C_CAN0 IF1_ARB1: ID15_0 Mask        */

// -------------------------------------  C_CAN0_IF1_ARB2  ----------------------------------------
#define C_CAN0_IF1_ARB2_ID28_16_Pos                           0                                                         /*!< C_CAN0 IF1_ARB2: ID28_16 Position   */
#define C_CAN0_IF1_ARB2_ID28_16_Msk                           (0x00001fffUL << C_CAN0_IF1_ARB2_ID28_16_Pos)             /*!< C_CAN0 IF1_ARB2: ID28_16 Mask       */
#define C_CAN0_IF1_ARB2_DIR_Pos                               13                                                        /*!< C_CAN0 IF1_ARB2: DIR Position       */
#define C_CAN0_IF1_ARB2_DIR_Msk                               (0x01UL << C_CAN0_IF1_ARB2_DIR_Pos)                       /*!< C_CAN0 IF1_ARB2: DIR Mask           */
#define C_CAN0_IF1_ARB2_XTD_Pos                               14                                                        /*!< C_CAN0 IF1_ARB2: XTD Position       */
#define C_CAN0_IF1_ARB2_XTD_Msk                               (0x01UL << C_CAN0_IF1_ARB2_XTD_Pos)                       /*!< C_CAN0 IF1_ARB2: XTD Mask           */
#define C_CAN0_IF1_ARB2_MSGVAL_Pos                            15                                                        /*!< C_CAN0 IF1_ARB2: MSGVAL Position    */
#define C_CAN0_IF1_ARB2_MSGVAL_Msk                            (0x01UL << C_CAN0_IF1_ARB2_MSGVAL_Pos)                    /*!< C_CAN0 IF1_ARB2: MSGVAL Mask        */

// ------------------------------------  C_CAN0_IF1_MCTRL  ----------------------------------------
#define C_CAN0_IF1_MCTRL_DLC3_0_Pos                           0                                                         /*!< C_CAN0 IF1_MCTRL: DLC3_0 Position   */
#define C_CAN0_IF1_MCTRL_DLC3_0_Msk                           (0x0fUL << C_CAN0_IF1_MCTRL_DLC3_0_Pos)                   /*!< C_CAN0 IF1_MCTRL: DLC3_0 Mask       */
#define C_CAN0_IF1_MCTRL_EOB_Pos                              7                                                         /*!< C_CAN0 IF1_MCTRL: EOB Position      */
#define C_CAN0_IF1_MCTRL_EOB_Msk                              (0x01UL << C_CAN0_IF1_MCTRL_EOB_Pos)                      /*!< C_CAN0 IF1_MCTRL: EOB Mask          */
#define C_CAN0_IF1_MCTRL_TXRQST_Pos                           8                                                         /*!< C_CAN0 IF1_MCTRL: TXRQST Position   */
#define C_CAN0_IF1_MCTRL_TXRQST_Msk                           (0x01UL << C_CAN0_IF1_MCTRL_TXRQST_Pos)                   /*!< C_CAN0 IF1_MCTRL: TXRQST Mask       */
#define C_CAN0_IF1_MCTRL_RMTEN_Pos                            9                                                         /*!< C_CAN0 IF1_MCTRL: RMTEN Position    */
#define C_CAN0_IF1_MCTRL_RMTEN_Msk                            (0x01UL << C_CAN0_IF1_MCTRL_RMTEN_Pos)                    /*!< C_CAN0 IF1_MCTRL: RMTEN Mask        */
#define C_CAN0_IF1_MCTRL_RXIE_Pos                             10                                                        /*!< C_CAN0 IF1_MCTRL: RXIE Position     */
#define C_CAN0_IF1_MCTRL_RXIE_Msk                             (0x01UL << C_CAN0_IF1_MCTRL_RXIE_Pos)                     /*!< C_CAN0 IF1_MCTRL: RXIE Mask         */
#define C_CAN0_IF1_MCTRL_TXIE_Pos                             11                                                        /*!< C_CAN0 IF1_MCTRL: TXIE Position     */
#define C_CAN0_IF1_MCTRL_TXIE_Msk                             (0x01UL << C_CAN0_IF1_MCTRL_TXIE_Pos)                     /*!< C_CAN0 IF1_MCTRL: TXIE Mask         */
#define C_CAN0_IF1_MCTRL_UMASK_Pos                            12                                                        /*!< C_CAN0 IF1_MCTRL: UMASK Position    */
#define C_CAN0_IF1_MCTRL_UMASK_Msk                            (0x01UL << C_CAN0_IF1_MCTRL_UMASK_Pos)                    /*!< C_CAN0 IF1_MCTRL: UMASK Mask        */
#define C_CAN0_IF1_MCTRL_INTPND_Pos                           13                                                        /*!< C_CAN0 IF1_MCTRL: INTPND Position   */
#define C_CAN0_IF1_MCTRL_INTPND_Msk                           (0x01UL << C_CAN0_IF1_MCTRL_INTPND_Pos)                   /*!< C_CAN0 IF1_MCTRL: INTPND Mask       */
#define C_CAN0_IF1_MCTRL_MSGLST_Pos                           14                                                        /*!< C_CAN0 IF1_MCTRL: MSGLST Position   */
#define C_CAN0_IF1_MCTRL_MSGLST_Msk                           (0x01UL << C_CAN0_IF1_MCTRL_MSGLST_Pos)                   /*!< C_CAN0 IF1_MCTRL: MSGLST Mask       */
#define C_CAN0_IF1_MCTRL_NEWDAT_Pos                           15                                                        /*!< C_CAN0 IF1_MCTRL: NEWDAT Position   */
#define C_CAN0_IF1_MCTRL_NEWDAT_Msk                           (0x01UL << C_CAN0_IF1_MCTRL_NEWDAT_Pos)                   /*!< C_CAN0 IF1_MCTRL: NEWDAT Mask       */

// -------------------------------------  C_CAN0_IF1_DA1  -----------------------------------------
#define C_CAN0_IF1_DA1_DATA0_Pos                              0                                                         /*!< C_CAN0 IF1_DA1: DATA0 Position      */
#define C_CAN0_IF1_DA1_DATA0_Msk                              (0x000000ffUL << C_CAN0_IF1_DA1_DATA0_Pos)                /*!< C_CAN0 IF1_DA1: DATA0 Mask          */
#define C_CAN0_IF1_DA1_DATA1_Pos                              8                                                         /*!< C_CAN0 IF1_DA1: DATA1 Position      */
#define C_CAN0_IF1_DA1_DATA1_Msk                              (0x000000ffUL << C_CAN0_IF1_DA1_DATA1_Pos)                /*!< C_CAN0 IF1_DA1: DATA1 Mask          */

// -------------------------------------  C_CAN0_IF1_DA2  -----------------------------------------
#define C_CAN0_IF1_DA2_DATA2_Pos                              0                                                         /*!< C_CAN0 IF1_DA2: DATA2 Position      */
#define C_CAN0_IF1_DA2_DATA2_Msk                              (0x000000ffUL << C_CAN0_IF1_DA2_DATA2_Pos)                /*!< C_CAN0 IF1_DA2: DATA2 Mask          */
#define C_CAN0_IF1_DA2_DATA3_Pos                              8                                                         /*!< C_CAN0 IF1_DA2: DATA3 Position      */
#define C_CAN0_IF1_DA2_DATA3_Msk                              (0x000000ffUL << C_CAN0_IF1_DA2_DATA3_Pos)                /*!< C_CAN0 IF1_DA2: DATA3 Mask          */

// -------------------------------------  C_CAN0_IF1_DB1  -----------------------------------------
#define C_CAN0_IF1_DB1_DATA4_Pos                              0                                                         /*!< C_CAN0 IF1_DB1: DATA4 Position      */
#define C_CAN0_IF1_DB1_DATA4_Msk                              (0x000000ffUL << C_CAN0_IF1_DB1_DATA4_Pos)                /*!< C_CAN0 IF1_DB1: DATA4 Mask          */
#define C_CAN0_IF1_DB1_DATA5_Pos                              8                                                         /*!< C_CAN0 IF1_DB1: DATA5 Position      */
#define C_CAN0_IF1_DB1_DATA5_Msk                              (0x000000ffUL << C_CAN0_IF1_DB1_DATA5_Pos)                /*!< C_CAN0 IF1_DB1: DATA5 Mask          */

// -------------------------------------  C_CAN0_IF1_DB2  -----------------------------------------
#define C_CAN0_IF1_DB2_DATA6_Pos                              0                                                         /*!< C_CAN0 IF1_DB2: DATA6 Position      */
#define C_CAN0_IF1_DB2_DATA6_Msk                              (0x000000ffUL << C_CAN0_IF1_DB2_DATA6_Pos)                /*!< C_CAN0 IF1_DB2: DATA6 Mask          */
#define C_CAN0_IF1_DB2_DATA7_Pos                              8                                                         /*!< C_CAN0 IF1_DB2: DATA7 Position      */
#define C_CAN0_IF1_DB2_DATA7_Msk                              (0x000000ffUL << C_CAN0_IF1_DB2_DATA7_Pos)                /*!< C_CAN0 IF1_DB2: DATA7 Mask          */

// ------------------------------------  C_CAN0_IF2_CMDREQ  ---------------------------------------
#define C_CAN0_IF2_CMDREQ_MESSNUM_Pos                         0                                                         /*!< C_CAN0 IF2_CMDREQ: MESSNUM Position */
#define C_CAN0_IF2_CMDREQ_MESSNUM_Msk                         (0x3fUL << C_CAN0_IF2_CMDREQ_MESSNUM_Pos)                 /*!< C_CAN0 IF2_CMDREQ: MESSNUM Mask     */
#define C_CAN0_IF2_CMDREQ_BUSY_Pos                            15                                                        /*!< C_CAN0 IF2_CMDREQ: BUSY Position    */
#define C_CAN0_IF2_CMDREQ_BUSY_Msk                            (0x01UL << C_CAN0_IF2_CMDREQ_BUSY_Pos)                    /*!< C_CAN0 IF2_CMDREQ: BUSY Mask        */

// -----------------------------------  C_CAN0_IF2_CMDMSK_R  --------------------------------------
#define C_CAN0_IF2_CMDMSK_R_DATA_B_Pos                        0                                                         /*!< C_CAN0 IF2_CMDMSK_R: DATA_B Position */
#define C_CAN0_IF2_CMDMSK_R_DATA_B_Msk                        (0x01UL << C_CAN0_IF2_CMDMSK_R_DATA_B_Pos)                /*!< C_CAN0 IF2_CMDMSK_R: DATA_B Mask    */
#define C_CAN0_IF2_CMDMSK_R_DATA_A_Pos                        1                                                         /*!< C_CAN0 IF2_CMDMSK_R: DATA_A Position */
#define C_CAN0_IF2_CMDMSK_R_DATA_A_Msk                        (0x01UL << C_CAN0_IF2_CMDMSK_R_DATA_A_Pos)                /*!< C_CAN0 IF2_CMDMSK_R: DATA_A Mask    */
#define C_CAN0_IF2_CMDMSK_R_NEWDAT_Pos                        2                                                         /*!< C_CAN0 IF2_CMDMSK_R: NEWDAT Position */
#define C_CAN0_IF2_CMDMSK_R_NEWDAT_Msk                        (0x01UL << C_CAN0_IF2_CMDMSK_R_NEWDAT_Pos)                /*!< C_CAN0 IF2_CMDMSK_R: NEWDAT Mask    */
#define C_CAN0_IF2_CMDMSK_R_CLRINTPND_Pos                     3                                                         /*!< C_CAN0 IF2_CMDMSK_R: CLRINTPND Position */
#define C_CAN0_IF2_CMDMSK_R_CLRINTPND_Msk                     (0x01UL << C_CAN0_IF2_CMDMSK_R_CLRINTPND_Pos)             /*!< C_CAN0 IF2_CMDMSK_R: CLRINTPND Mask */
#define C_CAN0_IF2_CMDMSK_R_CTRL_Pos                          4                                                         /*!< C_CAN0 IF2_CMDMSK_R: CTRL Position  */
#define C_CAN0_IF2_CMDMSK_R_CTRL_Msk                          (0x01UL << C_CAN0_IF2_CMDMSK_R_CTRL_Pos)                  /*!< C_CAN0 IF2_CMDMSK_R: CTRL Mask      */
#define C_CAN0_IF2_CMDMSK_R_ARB_Pos                           5                                                         /*!< C_CAN0 IF2_CMDMSK_R: ARB Position   */
#define C_CAN0_IF2_CMDMSK_R_ARB_Msk                           (0x01UL << C_CAN0_IF2_CMDMSK_R_ARB_Pos)                   /*!< C_CAN0 IF2_CMDMSK_R: ARB Mask       */
#define C_CAN0_IF2_CMDMSK_R_MASK_Pos                          6                                                         /*!< C_CAN0 IF2_CMDMSK_R: MASK Position  */
#define C_CAN0_IF2_CMDMSK_R_MASK_Msk                          (0x01UL << C_CAN0_IF2_CMDMSK_R_MASK_Pos)                  /*!< C_CAN0 IF2_CMDMSK_R: MASK Mask      */
#define C_CAN0_IF2_CMDMSK_R_WR_RD_Pos                         7                                                         /*!< C_CAN0 IF2_CMDMSK_R: WR_RD Position */
#define C_CAN0_IF2_CMDMSK_R_WR_RD_Msk                         (0x01UL << C_CAN0_IF2_CMDMSK_R_WR_RD_Pos)                 /*!< C_CAN0 IF2_CMDMSK_R: WR_RD Mask     */

// -----------------------------------  C_CAN0_IF2_CMDMSK_W  --------------------------------------
#define C_CAN0_IF2_CMDMSK_W_DATA_B_Pos                        0                                                         /*!< C_CAN0 IF2_CMDMSK_W: DATA_B Position */
#define C_CAN0_IF2_CMDMSK_W_DATA_B_Msk                        (0x01UL << C_CAN0_IF2_CMDMSK_W_DATA_B_Pos)                /*!< C_CAN0 IF2_CMDMSK_W: DATA_B Mask    */
#define C_CAN0_IF2_CMDMSK_W_DATA_A_Pos                        1                                                         /*!< C_CAN0 IF2_CMDMSK_W: DATA_A Position */
#define C_CAN0_IF2_CMDMSK_W_DATA_A_Msk                        (0x01UL << C_CAN0_IF2_CMDMSK_W_DATA_A_Pos)                /*!< C_CAN0 IF2_CMDMSK_W: DATA_A Mask    */
#define C_CAN0_IF2_CMDMSK_W_TXRQST_Pos                        2                                                         /*!< C_CAN0 IF2_CMDMSK_W: TXRQST Position */
#define C_CAN0_IF2_CMDMSK_W_TXRQST_Msk                        (0x01UL << C_CAN0_IF2_CMDMSK_W_TXRQST_Pos)                /*!< C_CAN0 IF2_CMDMSK_W: TXRQST Mask    */
#define C_CAN0_IF2_CMDMSK_W_CLRINTPND_Pos                     3                                                         /*!< C_CAN0 IF2_CMDMSK_W: CLRINTPND Position */
#define C_CAN0_IF2_CMDMSK_W_CLRINTPND_Msk                     (0x01UL << C_CAN0_IF2_CMDMSK_W_CLRINTPND_Pos)             /*!< C_CAN0 IF2_CMDMSK_W: CLRINTPND Mask */
#define C_CAN0_IF2_CMDMSK_W_CTRL_Pos                          4                                                         /*!< C_CAN0 IF2_CMDMSK_W: CTRL Position  */
#define C_CAN0_IF2_CMDMSK_W_CTRL_Msk                          (0x01UL << C_CAN0_IF2_CMDMSK_W_CTRL_Pos)                  /*!< C_CAN0 IF2_CMDMSK_W: CTRL Mask      */
#define C_CAN0_IF2_CMDMSK_W_ARB_Pos                           5                                                         /*!< C_CAN0 IF2_CMDMSK_W: ARB Position   */
#define C_CAN0_IF2_CMDMSK_W_ARB_Msk                           (0x01UL << C_CAN0_IF2_CMDMSK_W_ARB_Pos)                   /*!< C_CAN0 IF2_CMDMSK_W: ARB Mask       */
#define C_CAN0_IF2_CMDMSK_W_MASK_Pos                          6                                                         /*!< C_CAN0 IF2_CMDMSK_W: MASK Position  */
#define C_CAN0_IF2_CMDMSK_W_MASK_Msk                          (0x01UL << C_CAN0_IF2_CMDMSK_W_MASK_Pos)                  /*!< C_CAN0 IF2_CMDMSK_W: MASK Mask      */
#define C_CAN0_IF2_CMDMSK_W_WR_RD_Pos                         7                                                         /*!< C_CAN0 IF2_CMDMSK_W: WR_RD Position */
#define C_CAN0_IF2_CMDMSK_W_WR_RD_Msk                         (0x01UL << C_CAN0_IF2_CMDMSK_W_WR_RD_Pos)                 /*!< C_CAN0 IF2_CMDMSK_W: WR_RD Mask     */

// -------------------------------------  C_CAN0_IF2_MSK1  ----------------------------------------
#define C_CAN0_IF2_MSK1_MSK15_0_Pos                           0                                                         /*!< C_CAN0 IF2_MSK1: MSK15_0 Position   */
#define C_CAN0_IF2_MSK1_MSK15_0_Msk                           (0x0000ffffUL << C_CAN0_IF2_MSK1_MSK15_0_Pos)             /*!< C_CAN0 IF2_MSK1: MSK15_0 Mask       */

// -------------------------------------  C_CAN0_IF2_MSK2  ----------------------------------------
#define C_CAN0_IF2_MSK2_MSK28_16_Pos                          0                                                         /*!< C_CAN0 IF2_MSK2: MSK28_16 Position  */
#define C_CAN0_IF2_MSK2_MSK28_16_Msk                          (0x00001fffUL << C_CAN0_IF2_MSK2_MSK28_16_Pos)            /*!< C_CAN0 IF2_MSK2: MSK28_16 Mask      */
#define C_CAN0_IF2_MSK2_MDIR_Pos                              14                                                        /*!< C_CAN0 IF2_MSK2: MDIR Position      */
#define C_CAN0_IF2_MSK2_MDIR_Msk                              (0x01UL << C_CAN0_IF2_MSK2_MDIR_Pos)                      /*!< C_CAN0 IF2_MSK2: MDIR Mask          */
#define C_CAN0_IF2_MSK2_MXTD_Pos                              15                                                        /*!< C_CAN0 IF2_MSK2: MXTD Position      */
#define C_CAN0_IF2_MSK2_MXTD_Msk                              (0x01UL << C_CAN0_IF2_MSK2_MXTD_Pos)                      /*!< C_CAN0 IF2_MSK2: MXTD Mask          */

// -------------------------------------  C_CAN0_IF2_ARB1  ----------------------------------------
#define C_CAN0_IF2_ARB1_ID15_0_Pos                            0                                                         /*!< C_CAN0 IF2_ARB1: ID15_0 Position    */
#define C_CAN0_IF2_ARB1_ID15_0_Msk                            (0x0000ffffUL << C_CAN0_IF2_ARB1_ID15_0_Pos)              /*!< C_CAN0 IF2_ARB1: ID15_0 Mask        */

// -------------------------------------  C_CAN0_IF2_ARB2  ----------------------------------------
#define C_CAN0_IF2_ARB2_ID28_16_Pos                           0                                                         /*!< C_CAN0 IF2_ARB2: ID28_16 Position   */
#define C_CAN0_IF2_ARB2_ID28_16_Msk                           (0x00001fffUL << C_CAN0_IF2_ARB2_ID28_16_Pos)             /*!< C_CAN0 IF2_ARB2: ID28_16 Mask       */
#define C_CAN0_IF2_ARB2_DIR_Pos                               13                                                        /*!< C_CAN0 IF2_ARB2: DIR Position       */
#define C_CAN0_IF2_ARB2_DIR_Msk                               (0x01UL << C_CAN0_IF2_ARB2_DIR_Pos)                       /*!< C_CAN0 IF2_ARB2: DIR Mask           */
#define C_CAN0_IF2_ARB2_XTD_Pos                               14                                                        /*!< C_CAN0 IF2_ARB2: XTD Position       */
#define C_CAN0_IF2_ARB2_XTD_Msk                               (0x01UL << C_CAN0_IF2_ARB2_XTD_Pos)                       /*!< C_CAN0 IF2_ARB2: XTD Mask           */
#define C_CAN0_IF2_ARB2_MSGVAL_Pos                            15                                                        /*!< C_CAN0 IF2_ARB2: MSGVAL Position    */
#define C_CAN0_IF2_ARB2_MSGVAL_Msk                            (0x01UL << C_CAN0_IF2_ARB2_MSGVAL_Pos)                    /*!< C_CAN0 IF2_ARB2: MSGVAL Mask        */

// ------------------------------------  C_CAN0_IF2_MCTRL  ----------------------------------------
#define C_CAN0_IF2_MCTRL_DLC3_0_Pos                           0                                                         /*!< C_CAN0 IF2_MCTRL: DLC3_0 Position   */
#define C_CAN0_IF2_MCTRL_DLC3_0_Msk                           (0x0fUL << C_CAN0_IF2_MCTRL_DLC3_0_Pos)                   /*!< C_CAN0 IF2_MCTRL: DLC3_0 Mask       */
#define C_CAN0_IF2_MCTRL_EOB_Pos                              7                                                         /*!< C_CAN0 IF2_MCTRL: EOB Position      */
#define C_CAN0_IF2_MCTRL_EOB_Msk                              (0x01UL << C_CAN0_IF2_MCTRL_EOB_Pos)                      /*!< C_CAN0 IF2_MCTRL: EOB Mask          */
#define C_CAN0_IF2_MCTRL_TXRQST_Pos                           8                                                         /*!< C_CAN0 IF2_MCTRL: TXRQST Position   */
#define C_CAN0_IF2_MCTRL_TXRQST_Msk                           (0x01UL << C_CAN0_IF2_MCTRL_TXRQST_Pos)                   /*!< C_CAN0 IF2_MCTRL: TXRQST Mask       */
#define C_CAN0_IF2_MCTRL_RMTEN_Pos                            9                                                         /*!< C_CAN0 IF2_MCTRL: RMTEN Position    */
#define C_CAN0_IF2_MCTRL_RMTEN_Msk                            (0x01UL << C_CAN0_IF2_MCTRL_RMTEN_Pos)                    /*!< C_CAN0 IF2_MCTRL: RMTEN Mask        */
#define C_CAN0_IF2_MCTRL_RXIE_Pos                             10                                                        /*!< C_CAN0 IF2_MCTRL: RXIE Position     */
#define C_CAN0_IF2_MCTRL_RXIE_Msk                             (0x01UL << C_CAN0_IF2_MCTRL_RXIE_Pos)                     /*!< C_CAN0 IF2_MCTRL: RXIE Mask         */
#define C_CAN0_IF2_MCTRL_TXIE_Pos                             11                                                        /*!< C_CAN0 IF2_MCTRL: TXIE Position     */
#define C_CAN0_IF2_MCTRL_TXIE_Msk                             (0x01UL << C_CAN0_IF2_MCTRL_TXIE_Pos)                     /*!< C_CAN0 IF2_MCTRL: TXIE Mask         */
#define C_CAN0_IF2_MCTRL_UMASK_Pos                            12                                                        /*!< C_CAN0 IF2_MCTRL: UMASK Position    */
#define C_CAN0_IF2_MCTRL_UMASK_Msk                            (0x01UL << C_CAN0_IF2_MCTRL_UMASK_Pos)                    /*!< C_CAN0 IF2_MCTRL: UMASK Mask        */
#define C_CAN0_IF2_MCTRL_INTPND_Pos                           13                                                        /*!< C_CAN0 IF2_MCTRL: INTPND Position   */
#define C_CAN0_IF2_MCTRL_INTPND_Msk                           (0x01UL << C_CAN0_IF2_MCTRL_INTPND_Pos)                   /*!< C_CAN0 IF2_MCTRL: INTPND Mask       */
#define C_CAN0_IF2_MCTRL_MSGLST_Pos                           14                                                        /*!< C_CAN0 IF2_MCTRL: MSGLST Position   */
#define C_CAN0_IF2_MCTRL_MSGLST_Msk                           (0x01UL << C_CAN0_IF2_MCTRL_MSGLST_Pos)                   /*!< C_CAN0 IF2_MCTRL: MSGLST Mask       */
#define C_CAN0_IF2_MCTRL_NEWDAT_Pos                           15                                                        /*!< C_CAN0 IF2_MCTRL: NEWDAT Position   */
#define C_CAN0_IF2_MCTRL_NEWDAT_Msk                           (0x01UL << C_CAN0_IF2_MCTRL_NEWDAT_Pos)                   /*!< C_CAN0 IF2_MCTRL: NEWDAT Mask       */

// -------------------------------------  C_CAN0_IF2_DA1  -----------------------------------------
#define C_CAN0_IF2_DA1_DATA0_Pos                              0                                                         /*!< C_CAN0 IF2_DA1: DATA0 Position      */
#define C_CAN0_IF2_DA1_DATA0_Msk                              (0x000000ffUL << C_CAN0_IF2_DA1_DATA0_Pos)                /*!< C_CAN0 IF2_DA1: DATA0 Mask          */
#define C_CAN0_IF2_DA1_DATA1_Pos                              8                                                         /*!< C_CAN0 IF2_DA1: DATA1 Position      */
#define C_CAN0_IF2_DA1_DATA1_Msk                              (0x000000ffUL << C_CAN0_IF2_DA1_DATA1_Pos)                /*!< C_CAN0 IF2_DA1: DATA1 Mask          */

// -------------------------------------  C_CAN0_IF2_DA2  -----------------------------------------
#define C_CAN0_IF2_DA2_DATA2_Pos                              0                                                         /*!< C_CAN0 IF2_DA2: DATA2 Position      */
#define C_CAN0_IF2_DA2_DATA2_Msk                              (0x000000ffUL << C_CAN0_IF2_DA2_DATA2_Pos)                /*!< C_CAN0 IF2_DA2: DATA2 Mask          */
#define C_CAN0_IF2_DA2_DATA3_Pos                              8                                                         /*!< C_CAN0 IF2_DA2: DATA3 Position      */
#define C_CAN0_IF2_DA2_DATA3_Msk                              (0x000000ffUL << C_CAN0_IF2_DA2_DATA3_Pos)                /*!< C_CAN0 IF2_DA2: DATA3 Mask          */

// -------------------------------------  C_CAN0_IF2_DB1  -----------------------------------------
#define C_CAN0_IF2_DB1_DATA4_Pos                              0                                                         /*!< C_CAN0 IF2_DB1: DATA4 Position      */
#define C_CAN0_IF2_DB1_DATA4_Msk                              (0x000000ffUL << C_CAN0_IF2_DB1_DATA4_Pos)                /*!< C_CAN0 IF2_DB1: DATA4 Mask          */
#define C_CAN0_IF2_DB1_DATA5_Pos                              8                                                         /*!< C_CAN0 IF2_DB1: DATA5 Position      */
#define C_CAN0_IF2_DB1_DATA5_Msk                              (0x000000ffUL << C_CAN0_IF2_DB1_DATA5_Pos)                /*!< C_CAN0 IF2_DB1: DATA5 Mask          */

// -------------------------------------  C_CAN0_IF2_DB2  -----------------------------------------
#define C_CAN0_IF2_DB2_DATA6_Pos                              0                                                         /*!< C_CAN0 IF2_DB2: DATA6 Position      */
#define C_CAN0_IF2_DB2_DATA6_Msk                              (0x000000ffUL << C_CAN0_IF2_DB2_DATA6_Pos)                /*!< C_CAN0 IF2_DB2: DATA6 Mask          */
#define C_CAN0_IF2_DB2_DATA7_Pos                              8                                                         /*!< C_CAN0 IF2_DB2: DATA7 Position      */
#define C_CAN0_IF2_DB2_DATA7_Msk                              (0x000000ffUL << C_CAN0_IF2_DB2_DATA7_Pos)                /*!< C_CAN0 IF2_DB2: DATA7 Mask          */

// --------------------------------------  C_CAN0_TXREQ1  -----------------------------------------
#define C_CAN0_TXREQ1_TXRQST16_1_Pos                          0                                                         /*!< C_CAN0 TXREQ1: TXRQST16_1 Position  */
#define C_CAN0_TXREQ1_TXRQST16_1_Msk                          (0x0000ffffUL << C_CAN0_TXREQ1_TXRQST16_1_Pos)            /*!< C_CAN0 TXREQ1: TXRQST16_1 Mask      */

// --------------------------------------  C_CAN0_TXREQ2  -----------------------------------------
#define C_CAN0_TXREQ2_TXRQST32_17_Pos                         0                                                         /*!< C_CAN0 TXREQ2: TXRQST32_17 Position */
#define C_CAN0_TXREQ2_TXRQST32_17_Msk                         (0x0000ffffUL << C_CAN0_TXREQ2_TXRQST32_17_Pos)           /*!< C_CAN0 TXREQ2: TXRQST32_17 Mask     */

// ---------------------------------------  C_CAN0_ND1  -------------------------------------------
#define C_CAN0_ND1_NEWDAT16_1_Pos                             0                                                         /*!< C_CAN0 ND1: NEWDAT16_1 Position     */
#define C_CAN0_ND1_NEWDAT16_1_Msk                             (0x0000ffffUL << C_CAN0_ND1_NEWDAT16_1_Pos)               /*!< C_CAN0 ND1: NEWDAT16_1 Mask         */

// ---------------------------------------  C_CAN0_ND2  -------------------------------------------
#define C_CAN0_ND2_NEWDAT32_17_Pos                            0                                                         /*!< C_CAN0 ND2: NEWDAT32_17 Position    */
#define C_CAN0_ND2_NEWDAT32_17_Msk                            (0x0000ffffUL << C_CAN0_ND2_NEWDAT32_17_Pos)              /*!< C_CAN0 ND2: NEWDAT32_17 Mask        */

// ---------------------------------------  C_CAN0_IR1  -------------------------------------------
#define C_CAN0_IR1_INTPND16_1_Pos                             0                                                         /*!< C_CAN0 IR1: INTPND16_1 Position     */
#define C_CAN0_IR1_INTPND16_1_Msk                             (0x0000ffffUL << C_CAN0_IR1_INTPND16_1_Pos)               /*!< C_CAN0 IR1: INTPND16_1 Mask         */

// ---------------------------------------  C_CAN0_IR2  -------------------------------------------
#define C_CAN0_IR2_INTPND32_17_Pos                            0                                                         /*!< C_CAN0 IR2: INTPND32_17 Position    */
#define C_CAN0_IR2_INTPND32_17_Msk                            (0x0000ffffUL << C_CAN0_IR2_INTPND32_17_Pos)              /*!< C_CAN0 IR2: INTPND32_17 Mask        */

// --------------------------------------  C_CAN0_MSGV1  ------------------------------------------
#define C_CAN0_MSGV1_MSGVAL16_1_Pos                           0                                                         /*!< C_CAN0 MSGV1: MSGVAL16_1 Position   */
#define C_CAN0_MSGV1_MSGVAL16_1_Msk                           (0x0000ffffUL << C_CAN0_MSGV1_MSGVAL16_1_Pos)             /*!< C_CAN0 MSGV1: MSGVAL16_1 Mask       */

// --------------------------------------  C_CAN0_MSGV2  ------------------------------------------
#define C_CAN0_MSGV2_MSGVAL32_17_Pos                          0                                                         /*!< C_CAN0 MSGV2: MSGVAL32_17 Position  */
#define C_CAN0_MSGV2_MSGVAL32_17_Msk                          (0x0000ffffUL << C_CAN0_MSGV2_MSGVAL32_17_Pos)            /*!< C_CAN0 MSGV2: MSGVAL32_17 Mask      */

// --------------------------------------  C_CAN0_CLKDIV  -----------------------------------------
#define C_CAN0_CLKDIV_CLKDIVVAL_Pos                           0                                                         /*!< C_CAN0 CLKDIV: CLKDIVVAL Position   */
#define C_CAN0_CLKDIV_CLKDIVVAL_Msk                           (0x0fUL << C_CAN0_CLKDIV_CLKDIVVAL_Pos)                   /*!< C_CAN0 CLKDIV: CLKDIVVAL Mask       */


// ------------------------------------------------------------------------------------------------
// -----                                 ADC0 Position & Mask                                 -----
// ------------------------------------------------------------------------------------------------


// -----------------------------------------  ADC0_CR  --------------------------------------------
#define ADC0_CR_SEL_Pos                                       0                                                         /*!< ADC0 CR: SEL Position               */
#define ADC0_CR_SEL_Msk                                       (0x000000ffUL << ADC0_CR_SEL_Pos)                         /*!< ADC0 CR: SEL Mask                   */
#define ADC0_CR_CLKDIV_Pos                                    8                                                         /*!< ADC0 CR: CLKDIV Position            */
#define ADC0_CR_CLKDIV_Msk                                    (0x000000ffUL << ADC0_CR_CLKDIV_Pos)                      /*!< ADC0 CR: CLKDIV Mask                */
#define ADC0_CR_BURST_Pos                                     16                                                        /*!< ADC0 CR: BURST Position             */
#define ADC0_CR_BURST_Msk                                     (0x01UL << ADC0_CR_BURST_Pos)                             /*!< ADC0 CR: BURST Mask                 */
#define ADC0_CR_CLKS_Pos                                      17                                                        /*!< ADC0 CR: CLKS Position              */
#define ADC0_CR_CLKS_Msk                                      (0x07UL << ADC0_CR_CLKS_Pos)                              /*!< ADC0 CR: CLKS Mask                  */
#define ADC0_CR_PDN_Pos                                       21                                                        /*!< ADC0 CR: PDN Position               */
#define ADC0_CR_PDN_Msk                                       (0x01UL << ADC0_CR_PDN_Pos)                               /*!< ADC0 CR: PDN Mask                   */
#define ADC0_CR_START_Pos                                     24                                                        /*!< ADC0 CR: START Position             */
#define ADC0_CR_START_Msk                                     (0x07UL << ADC0_CR_START_Pos)                             /*!< ADC0 CR: START Mask                 */
#define ADC0_CR_EDGE_Pos                                      27                                                        /*!< ADC0 CR: EDGE Position              */
#define ADC0_CR_EDGE_Msk                                      (0x01UL << ADC0_CR_EDGE_Pos)                              /*!< ADC0 CR: EDGE Mask                  */

// ----------------------------------------  ADC0_GDR  --------------------------------------------
#define ADC0_GDR_V_VREF_Pos                                   6                                                         /*!< ADC0 GDR: V_VREF Position           */
#define ADC0_GDR_V_VREF_Msk                                   (0x000003ffUL << ADC0_GDR_V_VREF_Pos)                     /*!< ADC0 GDR: V_VREF Mask               */
#define ADC0_GDR_CHN_Pos                                      24                                                        /*!< ADC0 GDR: CHN Position              */
#define ADC0_GDR_CHN_Msk                                      (0x07UL << ADC0_GDR_CHN_Pos)                              /*!< ADC0 GDR: CHN Mask                  */
#define ADC0_GDR_OVERRUN_Pos                                  30                                                        /*!< ADC0 GDR: OVERRUN Position          */
#define ADC0_GDR_OVERRUN_Msk                                  (0x01UL << ADC0_GDR_OVERRUN_Pos)                          /*!< ADC0 GDR: OVERRUN Mask              */
#define ADC0_GDR_DONE_Pos                                     31                                                        /*!< ADC0 GDR: DONE Position             */
#define ADC0_GDR_DONE_Msk                                     (0x01UL << ADC0_GDR_DONE_Pos)                             /*!< ADC0 GDR: DONE Mask                 */

// ---------------------------------------  ADC0_INTEN  -------------------------------------------
#define ADC0_INTEN_ADINTEN_Pos                                0                                                         /*!< ADC0 INTEN: ADINTEN Position        */
#define ADC0_INTEN_ADINTEN_Msk                                (0x000000ffUL << ADC0_INTEN_ADINTEN_Pos)                  /*!< ADC0 INTEN: ADINTEN Mask            */
#define ADC0_INTEN_ADGINTEN_Pos                               8                                                         /*!< ADC0 INTEN: ADGINTEN Position       */
#define ADC0_INTEN_ADGINTEN_Msk                               (0x01UL << ADC0_INTEN_ADGINTEN_Pos)                       /*!< ADC0 INTEN: ADGINTEN Mask           */

// ----------------------------------------  ADC0_DR0  --------------------------------------------
#define ADC0_DR0_V_VREF_Pos                                   6                                                         /*!< ADC0 DR0: V_VREF Position           */
#define ADC0_DR0_V_VREF_Msk                                   (0x000003ffUL << ADC0_DR0_V_VREF_Pos)                     /*!< ADC0 DR0: V_VREF Mask               */
#define ADC0_DR0_OVERRUN_Pos                                  30                                                        /*!< ADC0 DR0: OVERRUN Position          */
#define ADC0_DR0_OVERRUN_Msk                                  (0x01UL << ADC0_DR0_OVERRUN_Pos)                          /*!< ADC0 DR0: OVERRUN Mask              */
#define ADC0_DR0_DONE_Pos                                     31                                                        /*!< ADC0 DR0: DONE Position             */
#define ADC0_DR0_DONE_Msk                                     (0x01UL << ADC0_DR0_DONE_Pos)                             /*!< ADC0 DR0: DONE Mask                 */

// ----------------------------------------  ADC0_DR1  --------------------------------------------
#define ADC0_DR1_V_VREF_Pos                                   6                                                         /*!< ADC0 DR1: V_VREF Position           */
#define ADC0_DR1_V_VREF_Msk                                   (0x000003ffUL << ADC0_DR1_V_VREF_Pos)                     /*!< ADC0 DR1: V_VREF Mask               */
#define ADC0_DR1_OVERRUN_Pos                                  30                                                        /*!< ADC0 DR1: OVERRUN Position          */
#define ADC0_DR1_OVERRUN_Msk                                  (0x01UL << ADC0_DR1_OVERRUN_Pos)                          /*!< ADC0 DR1: OVERRUN Mask              */
#define ADC0_DR1_DONE_Pos                                     31                                                        /*!< ADC0 DR1: DONE Position             */
#define ADC0_DR1_DONE_Msk                                     (0x01UL << ADC0_DR1_DONE_Pos)                             /*!< ADC0 DR1: DONE Mask                 */

// ----------------------------------------  ADC0_DR2  --------------------------------------------
#define ADC0_DR2_V_VREF_Pos                                   6                                                         /*!< ADC0 DR2: V_VREF Position           */
#define ADC0_DR2_V_VREF_Msk                                   (0x000003ffUL << ADC0_DR2_V_VREF_Pos)                     /*!< ADC0 DR2: V_VREF Mask               */
#define ADC0_DR2_OVERRUN_Pos                                  30                                                        /*!< ADC0 DR2: OVERRUN Position          */
#define ADC0_DR2_OVERRUN_Msk                                  (0x01UL << ADC0_DR2_OVERRUN_Pos)                          /*!< ADC0 DR2: OVERRUN Mask              */
#define ADC0_DR2_DONE_Pos                                     31                                                        /*!< ADC0 DR2: DONE Position             */
#define ADC0_DR2_DONE_Msk                                     (0x01UL << ADC0_DR2_DONE_Pos)                             /*!< ADC0 DR2: DONE Mask                 */

// ----------------------------------------  ADC0_DR3  --------------------------------------------
#define ADC0_DR3_V_VREF_Pos                                   6                                                         /*!< ADC0 DR3: V_VREF Position           */
#define ADC0_DR3_V_VREF_Msk                                   (0x000003ffUL << ADC0_DR3_V_VREF_Pos)                     /*!< ADC0 DR3: V_VREF Mask               */
#define ADC0_DR3_OVERRUN_Pos                                  30                                                        /*!< ADC0 DR3: OVERRUN Position          */
#define ADC0_DR3_OVERRUN_Msk                                  (0x01UL << ADC0_DR3_OVERRUN_Pos)                          /*!< ADC0 DR3: OVERRUN Mask              */
#define ADC0_DR3_DONE_Pos                                     31                                                        /*!< ADC0 DR3: DONE Position             */
#define ADC0_DR3_DONE_Msk                                     (0x01UL << ADC0_DR3_DONE_Pos)                             /*!< ADC0 DR3: DONE Mask                 */

// ----------------------------------------  ADC0_DR4  --------------------------------------------
#define ADC0_DR4_V_VREF_Pos                                   6                                                         /*!< ADC0 DR4: V_VREF Position           */
#define ADC0_DR4_V_VREF_Msk                                   (0x000003ffUL << ADC0_DR4_V_VREF_Pos)                     /*!< ADC0 DR4: V_VREF Mask               */
#define ADC0_DR4_OVERRUN_Pos                                  30                                                        /*!< ADC0 DR4: OVERRUN Position          */
#define ADC0_DR4_OVERRUN_Msk                                  (0x01UL << ADC0_DR4_OVERRUN_Pos)                          /*!< ADC0 DR4: OVERRUN Mask              */
#define ADC0_DR4_DONE_Pos                                     31                                                        /*!< ADC0 DR4: DONE Position             */
#define ADC0_DR4_DONE_Msk                                     (0x01UL << ADC0_DR4_DONE_Pos)                             /*!< ADC0 DR4: DONE Mask                 */

// ----------------------------------------  ADC0_DR5  --------------------------------------------
#define ADC0_DR5_V_VREF_Pos                                   6                                                         /*!< ADC0 DR5: V_VREF Position           */
#define ADC0_DR5_V_VREF_Msk                                   (0x000003ffUL << ADC0_DR5_V_VREF_Pos)                     /*!< ADC0 DR5: V_VREF Mask               */
#define ADC0_DR5_OVERRUN_Pos                                  30                                                        /*!< ADC0 DR5: OVERRUN Position          */
#define ADC0_DR5_OVERRUN_Msk                                  (0x01UL << ADC0_DR5_OVERRUN_Pos)                          /*!< ADC0 DR5: OVERRUN Mask              */
#define ADC0_DR5_DONE_Pos                                     31                                                        /*!< ADC0 DR5: DONE Position             */
#define ADC0_DR5_DONE_Msk                                     (0x01UL << ADC0_DR5_DONE_Pos)                             /*!< ADC0 DR5: DONE Mask                 */

// ----------------------------------------  ADC0_DR6  --------------------------------------------
#define ADC0_DR6_V_VREF_Pos                                   6                                                         /*!< ADC0 DR6: V_VREF Position           */
#define ADC0_DR6_V_VREF_Msk                                   (0x000003ffUL << ADC0_DR6_V_VREF_Pos)                     /*!< ADC0 DR6: V_VREF Mask               */
#define ADC0_DR6_OVERRUN_Pos                                  30                                                        /*!< ADC0 DR6: OVERRUN Position          */
#define ADC0_DR6_OVERRUN_Msk                                  (0x01UL << ADC0_DR6_OVERRUN_Pos)                          /*!< ADC0 DR6: OVERRUN Mask              */
#define ADC0_DR6_DONE_Pos                                     31                                                        /*!< ADC0 DR6: DONE Position             */
#define ADC0_DR6_DONE_Msk                                     (0x01UL << ADC0_DR6_DONE_Pos)                             /*!< ADC0 DR6: DONE Mask                 */

// ----------------------------------------  ADC0_DR7  --------------------------------------------
#define ADC0_DR7_V_VREF_Pos                                   6                                                         /*!< ADC0 DR7: V_VREF Position           */
#define ADC0_DR7_V_VREF_Msk                                   (0x000003ffUL << ADC0_DR7_V_VREF_Pos)                     /*!< ADC0 DR7: V_VREF Mask               */
#define ADC0_DR7_OVERRUN_Pos                                  30                                                        /*!< ADC0 DR7: OVERRUN Position          */
#define ADC0_DR7_OVERRUN_Msk                                  (0x01UL << ADC0_DR7_OVERRUN_Pos)                          /*!< ADC0 DR7: OVERRUN Mask              */
#define ADC0_DR7_DONE_Pos                                     31                                                        /*!< ADC0 DR7: DONE Position             */
#define ADC0_DR7_DONE_Msk                                     (0x01UL << ADC0_DR7_DONE_Pos)                             /*!< ADC0 DR7: DONE Mask                 */

// ----------------------------------------  ADC0_STAT  -------------------------------------------
#define ADC0_STAT_DONE_Pos                                    0                                                         /*!< ADC0 STAT: DONE Position            */
#define ADC0_STAT_DONE_Msk                                    (0x000000ffUL << ADC0_STAT_DONE_Pos)                      /*!< ADC0 STAT: DONE Mask                */
#define ADC0_STAT_OVERUN_Pos                                  8                                                         /*!< ADC0 STAT: OVERUN Position          */
#define ADC0_STAT_OVERUN_Msk                                  (0x000000ffUL << ADC0_STAT_OVERUN_Pos)                    /*!< ADC0 STAT: OVERUN Mask              */
#define ADC0_STAT_ADINT_Pos                                   16                                                        /*!< ADC0 STAT: ADINT Position           */
#define ADC0_STAT_ADINT_Msk                                   (0x01UL << ADC0_STAT_ADINT_Pos)                           /*!< ADC0 STAT: ADINT Mask               */


// ------------------------------------------------------------------------------------------------
// -----                                 ADC1 Position & Mask                                 -----
// ------------------------------------------------------------------------------------------------


// -----------------------------------------  ADC1_CR  --------------------------------------------
#define ADC1_CR_SEL_Pos                                       0                                                         /*!< ADC1 CR: SEL Position               */
#define ADC1_CR_SEL_Msk                                       (0x000000ffUL << ADC1_CR_SEL_Pos)                         /*!< ADC1 CR: SEL Mask                   */
#define ADC1_CR_CLKDIV_Pos                                    8                                                         /*!< ADC1 CR: CLKDIV Position            */
#define ADC1_CR_CLKDIV_Msk                                    (0x000000ffUL << ADC1_CR_CLKDIV_Pos)                      /*!< ADC1 CR: CLKDIV Mask                */
#define ADC1_CR_BURST_Pos                                     16                                                        /*!< ADC1 CR: BURST Position             */
#define ADC1_CR_BURST_Msk                                     (0x01UL << ADC1_CR_BURST_Pos)                             /*!< ADC1 CR: BURST Mask                 */
#define ADC1_CR_CLKS_Pos                                      17                                                        /*!< ADC1 CR: CLKS Position              */
#define ADC1_CR_CLKS_Msk                                      (0x07UL << ADC1_CR_CLKS_Pos)                              /*!< ADC1 CR: CLKS Mask                  */
#define ADC1_CR_PDN_Pos                                       21                                                        /*!< ADC1 CR: PDN Position               */
#define ADC1_CR_PDN_Msk                                       (0x01UL << ADC1_CR_PDN_Pos)                               /*!< ADC1 CR: PDN Mask                   */
#define ADC1_CR_START_Pos                                     24                                                        /*!< ADC1 CR: START Position             */
#define ADC1_CR_START_Msk                                     (0x07UL << ADC1_CR_START_Pos)                             /*!< ADC1 CR: START Mask                 */
#define ADC1_CR_EDGE_Pos                                      27                                                        /*!< ADC1 CR: EDGE Position              */
#define ADC1_CR_EDGE_Msk                                      (0x01UL << ADC1_CR_EDGE_Pos)                              /*!< ADC1 CR: EDGE Mask                  */

// ----------------------------------------  ADC1_GDR  --------------------------------------------
#define ADC1_GDR_V_VREF_Pos                                   6                                                         /*!< ADC1 GDR: V_VREF Position           */
#define ADC1_GDR_V_VREF_Msk                                   (0x000003ffUL << ADC1_GDR_V_VREF_Pos)                     /*!< ADC1 GDR: V_VREF Mask               */
#define ADC1_GDR_CHN_Pos                                      24                                                        /*!< ADC1 GDR: CHN Position              */
#define ADC1_GDR_CHN_Msk                                      (0x07UL << ADC1_GDR_CHN_Pos)                              /*!< ADC1 GDR: CHN Mask                  */
#define ADC1_GDR_OVERRUN_Pos                                  30                                                        /*!< ADC1 GDR: OVERRUN Position          */
#define ADC1_GDR_OVERRUN_Msk                                  (0x01UL << ADC1_GDR_OVERRUN_Pos)                          /*!< ADC1 GDR: OVERRUN Mask              */
#define ADC1_GDR_DONE_Pos                                     31                                                        /*!< ADC1 GDR: DONE Position             */
#define ADC1_GDR_DONE_Msk                                     (0x01UL << ADC1_GDR_DONE_Pos)                             /*!< ADC1 GDR: DONE Mask                 */

// ---------------------------------------  ADC1_INTEN  -------------------------------------------
#define ADC1_INTEN_ADINTEN_Pos                                0                                                         /*!< ADC1 INTEN: ADINTEN Position        */
#define ADC1_INTEN_ADINTEN_Msk                                (0x000000ffUL << ADC1_INTEN_ADINTEN_Pos)                  /*!< ADC1 INTEN: ADINTEN Mask            */
#define ADC1_INTEN_ADGINTEN_Pos                               8                                                         /*!< ADC1 INTEN: ADGINTEN Position       */
#define ADC1_INTEN_ADGINTEN_Msk                               (0x01UL << ADC1_INTEN_ADGINTEN_Pos)                       /*!< ADC1 INTEN: ADGINTEN Mask           */

// ----------------------------------------  ADC1_DR0  --------------------------------------------
#define ADC1_DR0_V_VREF_Pos                                   6                                                         /*!< ADC1 DR0: V_VREF Position           */
#define ADC1_DR0_V_VREF_Msk                                   (0x000003ffUL << ADC1_DR0_V_VREF_Pos)                     /*!< ADC1 DR0: V_VREF Mask               */
#define ADC1_DR0_OVERRUN_Pos                                  30                                                        /*!< ADC1 DR0: OVERRUN Position          */
#define ADC1_DR0_OVERRUN_Msk                                  (0x01UL << ADC1_DR0_OVERRUN_Pos)                          /*!< ADC1 DR0: OVERRUN Mask              */
#define ADC1_DR0_DONE_Pos                                     31                                                        /*!< ADC1 DR0: DONE Position             */
#define ADC1_DR0_DONE_Msk                                     (0x01UL << ADC1_DR0_DONE_Pos)                             /*!< ADC1 DR0: DONE Mask                 */

// ----------------------------------------  ADC1_DR1  --------------------------------------------
#define ADC1_DR1_V_VREF_Pos                                   6                                                         /*!< ADC1 DR1: V_VREF Position           */
#define ADC1_DR1_V_VREF_Msk                                   (0x000003ffUL << ADC1_DR1_V_VREF_Pos)                     /*!< ADC1 DR1: V_VREF Mask               */
#define ADC1_DR1_OVERRUN_Pos                                  30                                                        /*!< ADC1 DR1: OVERRUN Position          */
#define ADC1_DR1_OVERRUN_Msk                                  (0x01UL << ADC1_DR1_OVERRUN_Pos)                          /*!< ADC1 DR1: OVERRUN Mask              */
#define ADC1_DR1_DONE_Pos                                     31                                                        /*!< ADC1 DR1: DONE Position             */
#define ADC1_DR1_DONE_Msk                                     (0x01UL << ADC1_DR1_DONE_Pos)                             /*!< ADC1 DR1: DONE Mask                 */

// ----------------------------------------  ADC1_DR2  --------------------------------------------
#define ADC1_DR2_V_VREF_Pos                                   6                                                         /*!< ADC1 DR2: V_VREF Position           */
#define ADC1_DR2_V_VREF_Msk                                   (0x000003ffUL << ADC1_DR2_V_VREF_Pos)                     /*!< ADC1 DR2: V_VREF Mask               */
#define ADC1_DR2_OVERRUN_Pos                                  30                                                        /*!< ADC1 DR2: OVERRUN Position          */
#define ADC1_DR2_OVERRUN_Msk                                  (0x01UL << ADC1_DR2_OVERRUN_Pos)                          /*!< ADC1 DR2: OVERRUN Mask              */
#define ADC1_DR2_DONE_Pos                                     31                                                        /*!< ADC1 DR2: DONE Position             */
#define ADC1_DR2_DONE_Msk                                     (0x01UL << ADC1_DR2_DONE_Pos)                             /*!< ADC1 DR2: DONE Mask                 */

// ----------------------------------------  ADC1_DR3  --------------------------------------------
#define ADC1_DR3_V_VREF_Pos                                   6                                                         /*!< ADC1 DR3: V_VREF Position           */
#define ADC1_DR3_V_VREF_Msk                                   (0x000003ffUL << ADC1_DR3_V_VREF_Pos)                     /*!< ADC1 DR3: V_VREF Mask               */
#define ADC1_DR3_OVERRUN_Pos                                  30                                                        /*!< ADC1 DR3: OVERRUN Position          */
#define ADC1_DR3_OVERRUN_Msk                                  (0x01UL << ADC1_DR3_OVERRUN_Pos)                          /*!< ADC1 DR3: OVERRUN Mask              */
#define ADC1_DR3_DONE_Pos                                     31                                                        /*!< ADC1 DR3: DONE Position             */
#define ADC1_DR3_DONE_Msk                                     (0x01UL << ADC1_DR3_DONE_Pos)                             /*!< ADC1 DR3: DONE Mask                 */

// ----------------------------------------  ADC1_DR4  --------------------------------------------
#define ADC1_DR4_V_VREF_Pos                                   6                                                         /*!< ADC1 DR4: V_VREF Position           */
#define ADC1_DR4_V_VREF_Msk                                   (0x000003ffUL << ADC1_DR4_V_VREF_Pos)                     /*!< ADC1 DR4: V_VREF Mask               */
#define ADC1_DR4_OVERRUN_Pos                                  30                                                        /*!< ADC1 DR4: OVERRUN Position          */
#define ADC1_DR4_OVERRUN_Msk                                  (0x01UL << ADC1_DR4_OVERRUN_Pos)                          /*!< ADC1 DR4: OVERRUN Mask              */
#define ADC1_DR4_DONE_Pos                                     31                                                        /*!< ADC1 DR4: DONE Position             */
#define ADC1_DR4_DONE_Msk                                     (0x01UL << ADC1_DR4_DONE_Pos)                             /*!< ADC1 DR4: DONE Mask                 */

// ----------------------------------------  ADC1_DR5  --------------------------------------------
#define ADC1_DR5_V_VREF_Pos                                   6                                                         /*!< ADC1 DR5: V_VREF Position           */
#define ADC1_DR5_V_VREF_Msk                                   (0x000003ffUL << ADC1_DR5_V_VREF_Pos)                     /*!< ADC1 DR5: V_VREF Mask               */
#define ADC1_DR5_OVERRUN_Pos                                  30                                                        /*!< ADC1 DR5: OVERRUN Position          */
#define ADC1_DR5_OVERRUN_Msk                                  (0x01UL << ADC1_DR5_OVERRUN_Pos)                          /*!< ADC1 DR5: OVERRUN Mask              */
#define ADC1_DR5_DONE_Pos                                     31                                                        /*!< ADC1 DR5: DONE Position             */
#define ADC1_DR5_DONE_Msk                                     (0x01UL << ADC1_DR5_DONE_Pos)                             /*!< ADC1 DR5: DONE Mask                 */

// ----------------------------------------  ADC1_DR6  --------------------------------------------
#define ADC1_DR6_V_VREF_Pos                                   6                                                         /*!< ADC1 DR6: V_VREF Position           */
#define ADC1_DR6_V_VREF_Msk                                   (0x000003ffUL << ADC1_DR6_V_VREF_Pos)                     /*!< ADC1 DR6: V_VREF Mask               */
#define ADC1_DR6_OVERRUN_Pos                                  30                                                        /*!< ADC1 DR6: OVERRUN Position          */
#define ADC1_DR6_OVERRUN_Msk                                  (0x01UL << ADC1_DR6_OVERRUN_Pos)                          /*!< ADC1 DR6: OVERRUN Mask              */
#define ADC1_DR6_DONE_Pos                                     31                                                        /*!< ADC1 DR6: DONE Position             */
#define ADC1_DR6_DONE_Msk                                     (0x01UL << ADC1_DR6_DONE_Pos)                             /*!< ADC1 DR6: DONE Mask                 */

// ----------------------------------------  ADC1_DR7  --------------------------------------------
#define ADC1_DR7_V_VREF_Pos                                   6                                                         /*!< ADC1 DR7: V_VREF Position           */
#define ADC1_DR7_V_VREF_Msk                                   (0x000003ffUL << ADC1_DR7_V_VREF_Pos)                     /*!< ADC1 DR7: V_VREF Mask               */
#define ADC1_DR7_OVERRUN_Pos                                  30                                                        /*!< ADC1 DR7: OVERRUN Position          */
#define ADC1_DR7_OVERRUN_Msk                                  (0x01UL << ADC1_DR7_OVERRUN_Pos)                          /*!< ADC1 DR7: OVERRUN Mask              */
#define ADC1_DR7_DONE_Pos                                     31                                                        /*!< ADC1 DR7: DONE Position             */
#define ADC1_DR7_DONE_Msk                                     (0x01UL << ADC1_DR7_DONE_Pos)                             /*!< ADC1 DR7: DONE Mask                 */

// ----------------------------------------  ADC1_STAT  -------------------------------------------
#define ADC1_STAT_DONE_Pos                                    0                                                         /*!< ADC1 STAT: DONE Position            */
#define ADC1_STAT_DONE_Msk                                    (0x000000ffUL << ADC1_STAT_DONE_Pos)                      /*!< ADC1 STAT: DONE Mask                */
#define ADC1_STAT_OVERUN_Pos                                  8                                                         /*!< ADC1 STAT: OVERUN Position          */
#define ADC1_STAT_OVERUN_Msk                                  (0x000000ffUL << ADC1_STAT_OVERUN_Pos)                    /*!< ADC1 STAT: OVERUN Mask              */
#define ADC1_STAT_ADINT_Pos                                   16                                                        /*!< ADC1 STAT: ADINT Position           */
#define ADC1_STAT_ADINT_Msk                                   (0x01UL << ADC1_STAT_ADINT_Pos)                           /*!< ADC1 STAT: ADINT Mask               */


// ------------------------------------------------------------------------------------------------
// -----                               GPIO_PORT Position & Mask                              -----
// ------------------------------------------------------------------------------------------------


// --------------------------------------  GPIO_PORT_B0  ------------------------------------------
#define GPIO_PORT_B0_PBYTE_Pos                                0                                                         /*!< GPIO_PORT B0: PBYTE Position        */
#define GPIO_PORT_B0_PBYTE_Msk                                (0x01UL << GPIO_PORT_B0_PBYTE_Pos)                        /*!< GPIO_PORT B0: PBYTE Mask            */

// --------------------------------------  GPIO_PORT_B1  ------------------------------------------
#define GPIO_PORT_B1_PBYTE_Pos                                0                                                         /*!< GPIO_PORT B1: PBYTE Position        */
#define GPIO_PORT_B1_PBYTE_Msk                                (0x01UL << GPIO_PORT_B1_PBYTE_Pos)                        /*!< GPIO_PORT B1: PBYTE Mask            */

// --------------------------------------  GPIO_PORT_B2  ------------------------------------------
#define GPIO_PORT_B2_PBYTE_Pos                                0                                                         /*!< GPIO_PORT B2: PBYTE Position        */
#define GPIO_PORT_B2_PBYTE_Msk                                (0x01UL << GPIO_PORT_B2_PBYTE_Pos)                        /*!< GPIO_PORT B2: PBYTE Mask            */

// --------------------------------------  GPIO_PORT_B3  ------------------------------------------
#define GPIO_PORT_B3_PBYTE_Pos                                0                                                         /*!< GPIO_PORT B3: PBYTE Position        */
#define GPIO_PORT_B3_PBYTE_Msk                                (0x01UL << GPIO_PORT_B3_PBYTE_Pos)                        /*!< GPIO_PORT B3: PBYTE Mask            */

// --------------------------------------  GPIO_PORT_B4  ------------------------------------------
#define GPIO_PORT_B4_PBYTE_Pos                                0                                                         /*!< GPIO_PORT B4: PBYTE Position        */
#define GPIO_PORT_B4_PBYTE_Msk                                (0x01UL << GPIO_PORT_B4_PBYTE_Pos)                        /*!< GPIO_PORT B4: PBYTE Mask            */

// --------------------------------------  GPIO_PORT_B5  ------------------------------------------
#define GPIO_PORT_B5_PBYTE_Pos                                0                                                         /*!< GPIO_PORT B5: PBYTE Position        */
#define GPIO_PORT_B5_PBYTE_Msk                                (0x01UL << GPIO_PORT_B5_PBYTE_Pos)                        /*!< GPIO_PORT B5: PBYTE Mask            */

// --------------------------------------  GPIO_PORT_B6  ------------------------------------------
#define GPIO_PORT_B6_PBYTE_Pos                                0                                                         /*!< GPIO_PORT B6: PBYTE Position        */
#define GPIO_PORT_B6_PBYTE_Msk                                (0x01UL << GPIO_PORT_B6_PBYTE_Pos)                        /*!< GPIO_PORT B6: PBYTE Mask            */

// --------------------------------------  GPIO_PORT_B7  ------------------------------------------
#define GPIO_PORT_B7_PBYTE_Pos                                0                                                         /*!< GPIO_PORT B7: PBYTE Position        */
#define GPIO_PORT_B7_PBYTE_Msk                                (0x01UL << GPIO_PORT_B7_PBYTE_Pos)                        /*!< GPIO_PORT B7: PBYTE Mask            */

// --------------------------------------  GPIO_PORT_B8  ------------------------------------------
#define GPIO_PORT_B8_PBYTE_Pos                                0                                                         /*!< GPIO_PORT B8: PBYTE Position        */
#define GPIO_PORT_B8_PBYTE_Msk                                (0x01UL << GPIO_PORT_B8_PBYTE_Pos)                        /*!< GPIO_PORT B8: PBYTE Mask            */

// --------------------------------------  GPIO_PORT_B9  ------------------------------------------
#define GPIO_PORT_B9_PBYTE_Pos                                0                                                         /*!< GPIO_PORT B9: PBYTE Position        */
#define GPIO_PORT_B9_PBYTE_Msk                                (0x01UL << GPIO_PORT_B9_PBYTE_Pos)                        /*!< GPIO_PORT B9: PBYTE Mask            */

// --------------------------------------  GPIO_PORT_B10  -----------------------------------------
#define GPIO_PORT_B10_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B10: PBYTE Position       */
#define GPIO_PORT_B10_PBYTE_Msk                               (0x01UL << GPIO_PORT_B10_PBYTE_Pos)                       /*!< GPIO_PORT B10: PBYTE Mask           */

// --------------------------------------  GPIO_PORT_B11  -----------------------------------------
#define GPIO_PORT_B11_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B11: PBYTE Position       */
#define GPIO_PORT_B11_PBYTE_Msk                               (0x01UL << GPIO_PORT_B11_PBYTE_Pos)                       /*!< GPIO_PORT B11: PBYTE Mask           */

// --------------------------------------  GPIO_PORT_B12  -----------------------------------------
#define GPIO_PORT_B12_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B12: PBYTE Position       */
#define GPIO_PORT_B12_PBYTE_Msk                               (0x01UL << GPIO_PORT_B12_PBYTE_Pos)                       /*!< GPIO_PORT B12: PBYTE Mask           */

// --------------------------------------  GPIO_PORT_B13  -----------------------------------------
#define GPIO_PORT_B13_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B13: PBYTE Position       */
#define GPIO_PORT_B13_PBYTE_Msk                               (0x01UL << GPIO_PORT_B13_PBYTE_Pos)                       /*!< GPIO_PORT B13: PBYTE Mask           */

// --------------------------------------  GPIO_PORT_B14  -----------------------------------------
#define GPIO_PORT_B14_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B14: PBYTE Position       */
#define GPIO_PORT_B14_PBYTE_Msk                               (0x01UL << GPIO_PORT_B14_PBYTE_Pos)                       /*!< GPIO_PORT B14: PBYTE Mask           */

// --------------------------------------  GPIO_PORT_B15  -----------------------------------------
#define GPIO_PORT_B15_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B15: PBYTE Position       */
#define GPIO_PORT_B15_PBYTE_Msk                               (0x01UL << GPIO_PORT_B15_PBYTE_Pos)                       /*!< GPIO_PORT B15: PBYTE Mask           */

// --------------------------------------  GPIO_PORT_B16  -----------------------------------------
#define GPIO_PORT_B16_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B16: PBYTE Position       */
#define GPIO_PORT_B16_PBYTE_Msk                               (0x01UL << GPIO_PORT_B16_PBYTE_Pos)                       /*!< GPIO_PORT B16: PBYTE Mask           */

// --------------------------------------  GPIO_PORT_B17  -----------------------------------------
#define GPIO_PORT_B17_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B17: PBYTE Position       */
#define GPIO_PORT_B17_PBYTE_Msk                               (0x01UL << GPIO_PORT_B17_PBYTE_Pos)                       /*!< GPIO_PORT B17: PBYTE Mask           */

// --------------------------------------  GPIO_PORT_B18  -----------------------------------------
#define GPIO_PORT_B18_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B18: PBYTE Position       */
#define GPIO_PORT_B18_PBYTE_Msk                               (0x01UL << GPIO_PORT_B18_PBYTE_Pos)                       /*!< GPIO_PORT B18: PBYTE Mask           */

// --------------------------------------  GPIO_PORT_B19  -----------------------------------------
#define GPIO_PORT_B19_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B19: PBYTE Position       */
#define GPIO_PORT_B19_PBYTE_Msk                               (0x01UL << GPIO_PORT_B19_PBYTE_Pos)                       /*!< GPIO_PORT B19: PBYTE Mask           */

// --------------------------------------  GPIO_PORT_B20  -----------------------------------------
#define GPIO_PORT_B20_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B20: PBYTE Position       */
#define GPIO_PORT_B20_PBYTE_Msk                               (0x01UL << GPIO_PORT_B20_PBYTE_Pos)                       /*!< GPIO_PORT B20: PBYTE Mask           */

// --------------------------------------  GPIO_PORT_B21  -----------------------------------------
#define GPIO_PORT_B21_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B21: PBYTE Position       */
#define GPIO_PORT_B21_PBYTE_Msk                               (0x01UL << GPIO_PORT_B21_PBYTE_Pos)                       /*!< GPIO_PORT B21: PBYTE Mask           */

// --------------------------------------  GPIO_PORT_B22  -----------------------------------------
#define GPIO_PORT_B22_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B22: PBYTE Position       */
#define GPIO_PORT_B22_PBYTE_Msk                               (0x01UL << GPIO_PORT_B22_PBYTE_Pos)                       /*!< GPIO_PORT B22: PBYTE Mask           */

// --------------------------------------  GPIO_PORT_B23  -----------------------------------------
#define GPIO_PORT_B23_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B23: PBYTE Position       */
#define GPIO_PORT_B23_PBYTE_Msk                               (0x01UL << GPIO_PORT_B23_PBYTE_Pos)                       /*!< GPIO_PORT B23: PBYTE Mask           */

// --------------------------------------  GPIO_PORT_B24  -----------------------------------------
#define GPIO_PORT_B24_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B24: PBYTE Position       */
#define GPIO_PORT_B24_PBYTE_Msk                               (0x01UL << GPIO_PORT_B24_PBYTE_Pos)                       /*!< GPIO_PORT B24: PBYTE Mask           */

// --------------------------------------  GPIO_PORT_B25  -----------------------------------------
#define GPIO_PORT_B25_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B25: PBYTE Position       */
#define GPIO_PORT_B25_PBYTE_Msk                               (0x01UL << GPIO_PORT_B25_PBYTE_Pos)                       /*!< GPIO_PORT B25: PBYTE Mask           */

// --------------------------------------  GPIO_PORT_B26  -----------------------------------------
#define GPIO_PORT_B26_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B26: PBYTE Position       */
#define GPIO_PORT_B26_PBYTE_Msk                               (0x01UL << GPIO_PORT_B26_PBYTE_Pos)                       /*!< GPIO_PORT B26: PBYTE Mask           */

// --------------------------------------  GPIO_PORT_B27  -----------------------------------------
#define GPIO_PORT_B27_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B27: PBYTE Position       */
#define GPIO_PORT_B27_PBYTE_Msk                               (0x01UL << GPIO_PORT_B27_PBYTE_Pos)                       /*!< GPIO_PORT B27: PBYTE Mask           */

// --------------------------------------  GPIO_PORT_B28  -----------------------------------------
#define GPIO_PORT_B28_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B28: PBYTE Position       */
#define GPIO_PORT_B28_PBYTE_Msk                               (0x01UL << GPIO_PORT_B28_PBYTE_Pos)                       /*!< GPIO_PORT B28: PBYTE Mask           */

// --------------------------------------  GPIO_PORT_B29  -----------------------------------------
#define GPIO_PORT_B29_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B29: PBYTE Position       */
#define GPIO_PORT_B29_PBYTE_Msk                               (0x01UL << GPIO_PORT_B29_PBYTE_Pos)                       /*!< GPIO_PORT B29: PBYTE Mask           */

// --------------------------------------  GPIO_PORT_B30  -----------------------------------------
#define GPIO_PORT_B30_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B30: PBYTE Position       */
#define GPIO_PORT_B30_PBYTE_Msk                               (0x01UL << GPIO_PORT_B30_PBYTE_Pos)                       /*!< GPIO_PORT B30: PBYTE Mask           */

// --------------------------------------  GPIO_PORT_B31  -----------------------------------------
#define GPIO_PORT_B31_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B31: PBYTE Position       */
#define GPIO_PORT_B31_PBYTE_Msk                               (0x01UL << GPIO_PORT_B31_PBYTE_Pos)                       /*!< GPIO_PORT B31: PBYTE Mask           */

// --------------------------------------  GPIO_PORT_B32  -----------------------------------------
#define GPIO_PORT_B32_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B32: PBYTE Position       */
#define GPIO_PORT_B32_PBYTE_Msk                               (0x01UL << GPIO_PORT_B32_PBYTE_Pos)                       /*!< GPIO_PORT B32: PBYTE Mask           */

// --------------------------------------  GPIO_PORT_B33  -----------------------------------------
#define GPIO_PORT_B33_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B33: PBYTE Position       */
#define GPIO_PORT_B33_PBYTE_Msk                               (0x01UL << GPIO_PORT_B33_PBYTE_Pos)                       /*!< GPIO_PORT B33: PBYTE Mask           */

// --------------------------------------  GPIO_PORT_B34  -----------------------------------------
#define GPIO_PORT_B34_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B34: PBYTE Position       */
#define GPIO_PORT_B34_PBYTE_Msk                               (0x01UL << GPIO_PORT_B34_PBYTE_Pos)                       /*!< GPIO_PORT B34: PBYTE Mask           */

// --------------------------------------  GPIO_PORT_B35  -----------------------------------------
#define GPIO_PORT_B35_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B35: PBYTE Position       */
#define GPIO_PORT_B35_PBYTE_Msk                               (0x01UL << GPIO_PORT_B35_PBYTE_Pos)                       /*!< GPIO_PORT B35: PBYTE Mask           */

// --------------------------------------  GPIO_PORT_B36  -----------------------------------------
#define GPIO_PORT_B36_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B36: PBYTE Position       */
#define GPIO_PORT_B36_PBYTE_Msk                               (0x01UL << GPIO_PORT_B36_PBYTE_Pos)                       /*!< GPIO_PORT B36: PBYTE Mask           */

// --------------------------------------  GPIO_PORT_B37  -----------------------------------------
#define GPIO_PORT_B37_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B37: PBYTE Position       */
#define GPIO_PORT_B37_PBYTE_Msk                               (0x01UL << GPIO_PORT_B37_PBYTE_Pos)                       /*!< GPIO_PORT B37: PBYTE Mask           */

// --------------------------------------  GPIO_PORT_B38  -----------------------------------------
#define GPIO_PORT_B38_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B38: PBYTE Position       */
#define GPIO_PORT_B38_PBYTE_Msk                               (0x01UL << GPIO_PORT_B38_PBYTE_Pos)                       /*!< GPIO_PORT B38: PBYTE Mask           */

// --------------------------------------  GPIO_PORT_B39  -----------------------------------------
#define GPIO_PORT_B39_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B39: PBYTE Position       */
#define GPIO_PORT_B39_PBYTE_Msk                               (0x01UL << GPIO_PORT_B39_PBYTE_Pos)                       /*!< GPIO_PORT B39: PBYTE Mask           */

// --------------------------------------  GPIO_PORT_B40  -----------------------------------------
#define GPIO_PORT_B40_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B40: PBYTE Position       */
#define GPIO_PORT_B40_PBYTE_Msk                               (0x01UL << GPIO_PORT_B40_PBYTE_Pos)                       /*!< GPIO_PORT B40: PBYTE Mask           */

// --------------------------------------  GPIO_PORT_B41  -----------------------------------------
#define GPIO_PORT_B41_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B41: PBYTE Position       */
#define GPIO_PORT_B41_PBYTE_Msk                               (0x01UL << GPIO_PORT_B41_PBYTE_Pos)                       /*!< GPIO_PORT B41: PBYTE Mask           */

// --------------------------------------  GPIO_PORT_B42  -----------------------------------------
#define GPIO_PORT_B42_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B42: PBYTE Position       */
#define GPIO_PORT_B42_PBYTE_Msk                               (0x01UL << GPIO_PORT_B42_PBYTE_Pos)                       /*!< GPIO_PORT B42: PBYTE Mask           */

// --------------------------------------  GPIO_PORT_B43  -----------------------------------------
#define GPIO_PORT_B43_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B43: PBYTE Position       */
#define GPIO_PORT_B43_PBYTE_Msk                               (0x01UL << GPIO_PORT_B43_PBYTE_Pos)                       /*!< GPIO_PORT B43: PBYTE Mask           */

// --------------------------------------  GPIO_PORT_B44  -----------------------------------------
#define GPIO_PORT_B44_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B44: PBYTE Position       */
#define GPIO_PORT_B44_PBYTE_Msk                               (0x01UL << GPIO_PORT_B44_PBYTE_Pos)                       /*!< GPIO_PORT B44: PBYTE Mask           */

// --------------------------------------  GPIO_PORT_B45  -----------------------------------------
#define GPIO_PORT_B45_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B45: PBYTE Position       */
#define GPIO_PORT_B45_PBYTE_Msk                               (0x01UL << GPIO_PORT_B45_PBYTE_Pos)                       /*!< GPIO_PORT B45: PBYTE Mask           */

// --------------------------------------  GPIO_PORT_B46  -----------------------------------------
#define GPIO_PORT_B46_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B46: PBYTE Position       */
#define GPIO_PORT_B46_PBYTE_Msk                               (0x01UL << GPIO_PORT_B46_PBYTE_Pos)                       /*!< GPIO_PORT B46: PBYTE Mask           */

// --------------------------------------  GPIO_PORT_B47  -----------------------------------------
#define GPIO_PORT_B47_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B47: PBYTE Position       */
#define GPIO_PORT_B47_PBYTE_Msk                               (0x01UL << GPIO_PORT_B47_PBYTE_Pos)                       /*!< GPIO_PORT B47: PBYTE Mask           */

// --------------------------------------  GPIO_PORT_B48  -----------------------------------------
#define GPIO_PORT_B48_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B48: PBYTE Position       */
#define GPIO_PORT_B48_PBYTE_Msk                               (0x01UL << GPIO_PORT_B48_PBYTE_Pos)                       /*!< GPIO_PORT B48: PBYTE Mask           */

// --------------------------------------  GPIO_PORT_B49  -----------------------------------------
#define GPIO_PORT_B49_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B49: PBYTE Position       */
#define GPIO_PORT_B49_PBYTE_Msk                               (0x01UL << GPIO_PORT_B49_PBYTE_Pos)                       /*!< GPIO_PORT B49: PBYTE Mask           */

// --------------------------------------  GPIO_PORT_B50  -----------------------------------------
#define GPIO_PORT_B50_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B50: PBYTE Position       */
#define GPIO_PORT_B50_PBYTE_Msk                               (0x01UL << GPIO_PORT_B50_PBYTE_Pos)                       /*!< GPIO_PORT B50: PBYTE Mask           */

// --------------------------------------  GPIO_PORT_B51  -----------------------------------------
#define GPIO_PORT_B51_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B51: PBYTE Position       */
#define GPIO_PORT_B51_PBYTE_Msk                               (0x01UL << GPIO_PORT_B51_PBYTE_Pos)                       /*!< GPIO_PORT B51: PBYTE Mask           */

// --------------------------------------  GPIO_PORT_B52  -----------------------------------------
#define GPIO_PORT_B52_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B52: PBYTE Position       */
#define GPIO_PORT_B52_PBYTE_Msk                               (0x01UL << GPIO_PORT_B52_PBYTE_Pos)                       /*!< GPIO_PORT B52: PBYTE Mask           */

// --------------------------------------  GPIO_PORT_B53  -----------------------------------------
#define GPIO_PORT_B53_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B53: PBYTE Position       */
#define GPIO_PORT_B53_PBYTE_Msk                               (0x01UL << GPIO_PORT_B53_PBYTE_Pos)                       /*!< GPIO_PORT B53: PBYTE Mask           */

// --------------------------------------  GPIO_PORT_B54  -----------------------------------------
#define GPIO_PORT_B54_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B54: PBYTE Position       */
#define GPIO_PORT_B54_PBYTE_Msk                               (0x01UL << GPIO_PORT_B54_PBYTE_Pos)                       /*!< GPIO_PORT B54: PBYTE Mask           */

// --------------------------------------  GPIO_PORT_B55  -----------------------------------------
#define GPIO_PORT_B55_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B55: PBYTE Position       */
#define GPIO_PORT_B55_PBYTE_Msk                               (0x01UL << GPIO_PORT_B55_PBYTE_Pos)                       /*!< GPIO_PORT B55: PBYTE Mask           */

// --------------------------------------  GPIO_PORT_B56  -----------------------------------------
#define GPIO_PORT_B56_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B56: PBYTE Position       */
#define GPIO_PORT_B56_PBYTE_Msk                               (0x01UL << GPIO_PORT_B56_PBYTE_Pos)                       /*!< GPIO_PORT B56: PBYTE Mask           */

// --------------------------------------  GPIO_PORT_B57  -----------------------------------------
#define GPIO_PORT_B57_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B57: PBYTE Position       */
#define GPIO_PORT_B57_PBYTE_Msk                               (0x01UL << GPIO_PORT_B57_PBYTE_Pos)                       /*!< GPIO_PORT B57: PBYTE Mask           */

// --------------------------------------  GPIO_PORT_B58  -----------------------------------------
#define GPIO_PORT_B58_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B58: PBYTE Position       */
#define GPIO_PORT_B58_PBYTE_Msk                               (0x01UL << GPIO_PORT_B58_PBYTE_Pos)                       /*!< GPIO_PORT B58: PBYTE Mask           */

// --------------------------------------  GPIO_PORT_B59  -----------------------------------------
#define GPIO_PORT_B59_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B59: PBYTE Position       */
#define GPIO_PORT_B59_PBYTE_Msk                               (0x01UL << GPIO_PORT_B59_PBYTE_Pos)                       /*!< GPIO_PORT B59: PBYTE Mask           */

// --------------------------------------  GPIO_PORT_B60  -----------------------------------------
#define GPIO_PORT_B60_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B60: PBYTE Position       */
#define GPIO_PORT_B60_PBYTE_Msk                               (0x01UL << GPIO_PORT_B60_PBYTE_Pos)                       /*!< GPIO_PORT B60: PBYTE Mask           */

// --------------------------------------  GPIO_PORT_B61  -----------------------------------------
#define GPIO_PORT_B61_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B61: PBYTE Position       */
#define GPIO_PORT_B61_PBYTE_Msk                               (0x01UL << GPIO_PORT_B61_PBYTE_Pos)                       /*!< GPIO_PORT B61: PBYTE Mask           */

// --------------------------------------  GPIO_PORT_B62  -----------------------------------------
#define GPIO_PORT_B62_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B62: PBYTE Position       */
#define GPIO_PORT_B62_PBYTE_Msk                               (0x01UL << GPIO_PORT_B62_PBYTE_Pos)                       /*!< GPIO_PORT B62: PBYTE Mask           */

// --------------------------------------  GPIO_PORT_B63  -----------------------------------------
#define GPIO_PORT_B63_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B63: PBYTE Position       */
#define GPIO_PORT_B63_PBYTE_Msk                               (0x01UL << GPIO_PORT_B63_PBYTE_Pos)                       /*!< GPIO_PORT B63: PBYTE Mask           */

// --------------------------------------  GPIO_PORT_B64  -----------------------------------------
#define GPIO_PORT_B64_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B64: PBYTE Position       */
#define GPIO_PORT_B64_PBYTE_Msk                               (0x01UL << GPIO_PORT_B64_PBYTE_Pos)                       /*!< GPIO_PORT B64: PBYTE Mask           */

// --------------------------------------  GPIO_PORT_B65  -----------------------------------------
#define GPIO_PORT_B65_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B65: PBYTE Position       */
#define GPIO_PORT_B65_PBYTE_Msk                               (0x01UL << GPIO_PORT_B65_PBYTE_Pos)                       /*!< GPIO_PORT B65: PBYTE Mask           */

// --------------------------------------  GPIO_PORT_B66  -----------------------------------------
#define GPIO_PORT_B66_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B66: PBYTE Position       */
#define GPIO_PORT_B66_PBYTE_Msk                               (0x01UL << GPIO_PORT_B66_PBYTE_Pos)                       /*!< GPIO_PORT B66: PBYTE Mask           */

// --------------------------------------  GPIO_PORT_B67  -----------------------------------------
#define GPIO_PORT_B67_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B67: PBYTE Position       */
#define GPIO_PORT_B67_PBYTE_Msk                               (0x01UL << GPIO_PORT_B67_PBYTE_Pos)                       /*!< GPIO_PORT B67: PBYTE Mask           */

// --------------------------------------  GPIO_PORT_B68  -----------------------------------------
#define GPIO_PORT_B68_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B68: PBYTE Position       */
#define GPIO_PORT_B68_PBYTE_Msk                               (0x01UL << GPIO_PORT_B68_PBYTE_Pos)                       /*!< GPIO_PORT B68: PBYTE Mask           */

// --------------------------------------  GPIO_PORT_B69  -----------------------------------------
#define GPIO_PORT_B69_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B69: PBYTE Position       */
#define GPIO_PORT_B69_PBYTE_Msk                               (0x01UL << GPIO_PORT_B69_PBYTE_Pos)                       /*!< GPIO_PORT B69: PBYTE Mask           */

// --------------------------------------  GPIO_PORT_B70  -----------------------------------------
#define GPIO_PORT_B70_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B70: PBYTE Position       */
#define GPIO_PORT_B70_PBYTE_Msk                               (0x01UL << GPIO_PORT_B70_PBYTE_Pos)                       /*!< GPIO_PORT B70: PBYTE Mask           */

// --------------------------------------  GPIO_PORT_B71  -----------------------------------------
#define GPIO_PORT_B71_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B71: PBYTE Position       */
#define GPIO_PORT_B71_PBYTE_Msk                               (0x01UL << GPIO_PORT_B71_PBYTE_Pos)                       /*!< GPIO_PORT B71: PBYTE Mask           */

// --------------------------------------  GPIO_PORT_B72  -----------------------------------------
#define GPIO_PORT_B72_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B72: PBYTE Position       */
#define GPIO_PORT_B72_PBYTE_Msk                               (0x01UL << GPIO_PORT_B72_PBYTE_Pos)                       /*!< GPIO_PORT B72: PBYTE Mask           */

// --------------------------------------  GPIO_PORT_B73  -----------------------------------------
#define GPIO_PORT_B73_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B73: PBYTE Position       */
#define GPIO_PORT_B73_PBYTE_Msk                               (0x01UL << GPIO_PORT_B73_PBYTE_Pos)                       /*!< GPIO_PORT B73: PBYTE Mask           */

// --------------------------------------  GPIO_PORT_B74  -----------------------------------------
#define GPIO_PORT_B74_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B74: PBYTE Position       */
#define GPIO_PORT_B74_PBYTE_Msk                               (0x01UL << GPIO_PORT_B74_PBYTE_Pos)                       /*!< GPIO_PORT B74: PBYTE Mask           */

// --------------------------------------  GPIO_PORT_B75  -----------------------------------------
#define GPIO_PORT_B75_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B75: PBYTE Position       */
#define GPIO_PORT_B75_PBYTE_Msk                               (0x01UL << GPIO_PORT_B75_PBYTE_Pos)                       /*!< GPIO_PORT B75: PBYTE Mask           */

// --------------------------------------  GPIO_PORT_B76  -----------------------------------------
#define GPIO_PORT_B76_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B76: PBYTE Position       */
#define GPIO_PORT_B76_PBYTE_Msk                               (0x01UL << GPIO_PORT_B76_PBYTE_Pos)                       /*!< GPIO_PORT B76: PBYTE Mask           */

// --------------------------------------  GPIO_PORT_B77  -----------------------------------------
#define GPIO_PORT_B77_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B77: PBYTE Position       */
#define GPIO_PORT_B77_PBYTE_Msk                               (0x01UL << GPIO_PORT_B77_PBYTE_Pos)                       /*!< GPIO_PORT B77: PBYTE Mask           */

// --------------------------------------  GPIO_PORT_B78  -----------------------------------------
#define GPIO_PORT_B78_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B78: PBYTE Position       */
#define GPIO_PORT_B78_PBYTE_Msk                               (0x01UL << GPIO_PORT_B78_PBYTE_Pos)                       /*!< GPIO_PORT B78: PBYTE Mask           */

// --------------------------------------  GPIO_PORT_B79  -----------------------------------------
#define GPIO_PORT_B79_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B79: PBYTE Position       */
#define GPIO_PORT_B79_PBYTE_Msk                               (0x01UL << GPIO_PORT_B79_PBYTE_Pos)                       /*!< GPIO_PORT B79: PBYTE Mask           */

// --------------------------------------  GPIO_PORT_B80  -----------------------------------------
#define GPIO_PORT_B80_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B80: PBYTE Position       */
#define GPIO_PORT_B80_PBYTE_Msk                               (0x01UL << GPIO_PORT_B80_PBYTE_Pos)                       /*!< GPIO_PORT B80: PBYTE Mask           */

// --------------------------------------  GPIO_PORT_B81  -----------------------------------------
#define GPIO_PORT_B81_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B81: PBYTE Position       */
#define GPIO_PORT_B81_PBYTE_Msk                               (0x01UL << GPIO_PORT_B81_PBYTE_Pos)                       /*!< GPIO_PORT B81: PBYTE Mask           */

// --------------------------------------  GPIO_PORT_B82  -----------------------------------------
#define GPIO_PORT_B82_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B82: PBYTE Position       */
#define GPIO_PORT_B82_PBYTE_Msk                               (0x01UL << GPIO_PORT_B82_PBYTE_Pos)                       /*!< GPIO_PORT B82: PBYTE Mask           */

// --------------------------------------  GPIO_PORT_B83  -----------------------------------------
#define GPIO_PORT_B83_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B83: PBYTE Position       */
#define GPIO_PORT_B83_PBYTE_Msk                               (0x01UL << GPIO_PORT_B83_PBYTE_Pos)                       /*!< GPIO_PORT B83: PBYTE Mask           */

// --------------------------------------  GPIO_PORT_B84  -----------------------------------------
#define GPIO_PORT_B84_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B84: PBYTE Position       */
#define GPIO_PORT_B84_PBYTE_Msk                               (0x01UL << GPIO_PORT_B84_PBYTE_Pos)                       /*!< GPIO_PORT B84: PBYTE Mask           */

// --------------------------------------  GPIO_PORT_B85  -----------------------------------------
#define GPIO_PORT_B85_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B85: PBYTE Position       */
#define GPIO_PORT_B85_PBYTE_Msk                               (0x01UL << GPIO_PORT_B85_PBYTE_Pos)                       /*!< GPIO_PORT B85: PBYTE Mask           */

// --------------------------------------  GPIO_PORT_B86  -----------------------------------------
#define GPIO_PORT_B86_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B86: PBYTE Position       */
#define GPIO_PORT_B86_PBYTE_Msk                               (0x01UL << GPIO_PORT_B86_PBYTE_Pos)                       /*!< GPIO_PORT B86: PBYTE Mask           */

// --------------------------------------  GPIO_PORT_B87  -----------------------------------------
#define GPIO_PORT_B87_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B87: PBYTE Position       */
#define GPIO_PORT_B87_PBYTE_Msk                               (0x01UL << GPIO_PORT_B87_PBYTE_Pos)                       /*!< GPIO_PORT B87: PBYTE Mask           */

// --------------------------------------  GPIO_PORT_B88  -----------------------------------------
#define GPIO_PORT_B88_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B88: PBYTE Position       */
#define GPIO_PORT_B88_PBYTE_Msk                               (0x01UL << GPIO_PORT_B88_PBYTE_Pos)                       /*!< GPIO_PORT B88: PBYTE Mask           */

// --------------------------------------  GPIO_PORT_B89  -----------------------------------------
#define GPIO_PORT_B89_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B89: PBYTE Position       */
#define GPIO_PORT_B89_PBYTE_Msk                               (0x01UL << GPIO_PORT_B89_PBYTE_Pos)                       /*!< GPIO_PORT B89: PBYTE Mask           */

// --------------------------------------  GPIO_PORT_B90  -----------------------------------------
#define GPIO_PORT_B90_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B90: PBYTE Position       */
#define GPIO_PORT_B90_PBYTE_Msk                               (0x01UL << GPIO_PORT_B90_PBYTE_Pos)                       /*!< GPIO_PORT B90: PBYTE Mask           */

// --------------------------------------  GPIO_PORT_B91  -----------------------------------------
#define GPIO_PORT_B91_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B91: PBYTE Position       */
#define GPIO_PORT_B91_PBYTE_Msk                               (0x01UL << GPIO_PORT_B91_PBYTE_Pos)                       /*!< GPIO_PORT B91: PBYTE Mask           */

// --------------------------------------  GPIO_PORT_B92  -----------------------------------------
#define GPIO_PORT_B92_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B92: PBYTE Position       */
#define GPIO_PORT_B92_PBYTE_Msk                               (0x01UL << GPIO_PORT_B92_PBYTE_Pos)                       /*!< GPIO_PORT B92: PBYTE Mask           */

// --------------------------------------  GPIO_PORT_B93  -----------------------------------------
#define GPIO_PORT_B93_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B93: PBYTE Position       */
#define GPIO_PORT_B93_PBYTE_Msk                               (0x01UL << GPIO_PORT_B93_PBYTE_Pos)                       /*!< GPIO_PORT B93: PBYTE Mask           */

// --------------------------------------  GPIO_PORT_B94  -----------------------------------------
#define GPIO_PORT_B94_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B94: PBYTE Position       */
#define GPIO_PORT_B94_PBYTE_Msk                               (0x01UL << GPIO_PORT_B94_PBYTE_Pos)                       /*!< GPIO_PORT B94: PBYTE Mask           */

// --------------------------------------  GPIO_PORT_B95  -----------------------------------------
#define GPIO_PORT_B95_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B95: PBYTE Position       */
#define GPIO_PORT_B95_PBYTE_Msk                               (0x01UL << GPIO_PORT_B95_PBYTE_Pos)                       /*!< GPIO_PORT B95: PBYTE Mask           */

// --------------------------------------  GPIO_PORT_B96  -----------------------------------------
#define GPIO_PORT_B96_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B96: PBYTE Position       */
#define GPIO_PORT_B96_PBYTE_Msk                               (0x01UL << GPIO_PORT_B96_PBYTE_Pos)                       /*!< GPIO_PORT B96: PBYTE Mask           */

// --------------------------------------  GPIO_PORT_B97  -----------------------------------------
#define GPIO_PORT_B97_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B97: PBYTE Position       */
#define GPIO_PORT_B97_PBYTE_Msk                               (0x01UL << GPIO_PORT_B97_PBYTE_Pos)                       /*!< GPIO_PORT B97: PBYTE Mask           */

// --------------------------------------  GPIO_PORT_B98  -----------------------------------------
#define GPIO_PORT_B98_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B98: PBYTE Position       */
#define GPIO_PORT_B98_PBYTE_Msk                               (0x01UL << GPIO_PORT_B98_PBYTE_Pos)                       /*!< GPIO_PORT B98: PBYTE Mask           */

// --------------------------------------  GPIO_PORT_B99  -----------------------------------------
#define GPIO_PORT_B99_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B99: PBYTE Position       */
#define GPIO_PORT_B99_PBYTE_Msk                               (0x01UL << GPIO_PORT_B99_PBYTE_Pos)                       /*!< GPIO_PORT B99: PBYTE Mask           */

// -------------------------------------  GPIO_PORT_B100  -----------------------------------------
#define GPIO_PORT_B100_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B100: PBYTE Position      */
#define GPIO_PORT_B100_PBYTE_Msk                              (0x01UL << GPIO_PORT_B100_PBYTE_Pos)                      /*!< GPIO_PORT B100: PBYTE Mask          */

// -------------------------------------  GPIO_PORT_B101  -----------------------------------------
#define GPIO_PORT_B101_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B101: PBYTE Position      */
#define GPIO_PORT_B101_PBYTE_Msk                              (0x01UL << GPIO_PORT_B101_PBYTE_Pos)                      /*!< GPIO_PORT B101: PBYTE Mask          */

// -------------------------------------  GPIO_PORT_B102  -----------------------------------------
#define GPIO_PORT_B102_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B102: PBYTE Position      */
#define GPIO_PORT_B102_PBYTE_Msk                              (0x01UL << GPIO_PORT_B102_PBYTE_Pos)                      /*!< GPIO_PORT B102: PBYTE Mask          */

// -------------------------------------  GPIO_PORT_B103  -----------------------------------------
#define GPIO_PORT_B103_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B103: PBYTE Position      */
#define GPIO_PORT_B103_PBYTE_Msk                              (0x01UL << GPIO_PORT_B103_PBYTE_Pos)                      /*!< GPIO_PORT B103: PBYTE Mask          */

// -------------------------------------  GPIO_PORT_B104  -----------------------------------------
#define GPIO_PORT_B104_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B104: PBYTE Position      */
#define GPIO_PORT_B104_PBYTE_Msk                              (0x01UL << GPIO_PORT_B104_PBYTE_Pos)                      /*!< GPIO_PORT B104: PBYTE Mask          */

// -------------------------------------  GPIO_PORT_B105  -----------------------------------------
#define GPIO_PORT_B105_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B105: PBYTE Position      */
#define GPIO_PORT_B105_PBYTE_Msk                              (0x01UL << GPIO_PORT_B105_PBYTE_Pos)                      /*!< GPIO_PORT B105: PBYTE Mask          */

// -------------------------------------  GPIO_PORT_B106  -----------------------------------------
#define GPIO_PORT_B106_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B106: PBYTE Position      */
#define GPIO_PORT_B106_PBYTE_Msk                              (0x01UL << GPIO_PORT_B106_PBYTE_Pos)                      /*!< GPIO_PORT B106: PBYTE Mask          */

// -------------------------------------  GPIO_PORT_B107  -----------------------------------------
#define GPIO_PORT_B107_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B107: PBYTE Position      */
#define GPIO_PORT_B107_PBYTE_Msk                              (0x01UL << GPIO_PORT_B107_PBYTE_Pos)                      /*!< GPIO_PORT B107: PBYTE Mask          */

// -------------------------------------  GPIO_PORT_B108  -----------------------------------------
#define GPIO_PORT_B108_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B108: PBYTE Position      */
#define GPIO_PORT_B108_PBYTE_Msk                              (0x01UL << GPIO_PORT_B108_PBYTE_Pos)                      /*!< GPIO_PORT B108: PBYTE Mask          */

// -------------------------------------  GPIO_PORT_B109  -----------------------------------------
#define GPIO_PORT_B109_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B109: PBYTE Position      */
#define GPIO_PORT_B109_PBYTE_Msk                              (0x01UL << GPIO_PORT_B109_PBYTE_Pos)                      /*!< GPIO_PORT B109: PBYTE Mask          */

// -------------------------------------  GPIO_PORT_B110  -----------------------------------------
#define GPIO_PORT_B110_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B110: PBYTE Position      */
#define GPIO_PORT_B110_PBYTE_Msk                              (0x01UL << GPIO_PORT_B110_PBYTE_Pos)                      /*!< GPIO_PORT B110: PBYTE Mask          */

// -------------------------------------  GPIO_PORT_B111  -----------------------------------------
#define GPIO_PORT_B111_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B111: PBYTE Position      */
#define GPIO_PORT_B111_PBYTE_Msk                              (0x01UL << GPIO_PORT_B111_PBYTE_Pos)                      /*!< GPIO_PORT B111: PBYTE Mask          */

// -------------------------------------  GPIO_PORT_B112  -----------------------------------------
#define GPIO_PORT_B112_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B112: PBYTE Position      */
#define GPIO_PORT_B112_PBYTE_Msk                              (0x01UL << GPIO_PORT_B112_PBYTE_Pos)                      /*!< GPIO_PORT B112: PBYTE Mask          */

// -------------------------------------  GPIO_PORT_B113  -----------------------------------------
#define GPIO_PORT_B113_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B113: PBYTE Position      */
#define GPIO_PORT_B113_PBYTE_Msk                              (0x01UL << GPIO_PORT_B113_PBYTE_Pos)                      /*!< GPIO_PORT B113: PBYTE Mask          */

// -------------------------------------  GPIO_PORT_B114  -----------------------------------------
#define GPIO_PORT_B114_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B114: PBYTE Position      */
#define GPIO_PORT_B114_PBYTE_Msk                              (0x01UL << GPIO_PORT_B114_PBYTE_Pos)                      /*!< GPIO_PORT B114: PBYTE Mask          */

// -------------------------------------  GPIO_PORT_B115  -----------------------------------------
#define GPIO_PORT_B115_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B115: PBYTE Position      */
#define GPIO_PORT_B115_PBYTE_Msk                              (0x01UL << GPIO_PORT_B115_PBYTE_Pos)                      /*!< GPIO_PORT B115: PBYTE Mask          */

// -------------------------------------  GPIO_PORT_B116  -----------------------------------------
#define GPIO_PORT_B116_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B116: PBYTE Position      */
#define GPIO_PORT_B116_PBYTE_Msk                              (0x01UL << GPIO_PORT_B116_PBYTE_Pos)                      /*!< GPIO_PORT B116: PBYTE Mask          */

// -------------------------------------  GPIO_PORT_B117  -----------------------------------------
#define GPIO_PORT_B117_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B117: PBYTE Position      */
#define GPIO_PORT_B117_PBYTE_Msk                              (0x01UL << GPIO_PORT_B117_PBYTE_Pos)                      /*!< GPIO_PORT B117: PBYTE Mask          */

// -------------------------------------  GPIO_PORT_B118  -----------------------------------------
#define GPIO_PORT_B118_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B118: PBYTE Position      */
#define GPIO_PORT_B118_PBYTE_Msk                              (0x01UL << GPIO_PORT_B118_PBYTE_Pos)                      /*!< GPIO_PORT B118: PBYTE Mask          */

// -------------------------------------  GPIO_PORT_B119  -----------------------------------------
#define GPIO_PORT_B119_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B119: PBYTE Position      */
#define GPIO_PORT_B119_PBYTE_Msk                              (0x01UL << GPIO_PORT_B119_PBYTE_Pos)                      /*!< GPIO_PORT B119: PBYTE Mask          */

// -------------------------------------  GPIO_PORT_B120  -----------------------------------------
#define GPIO_PORT_B120_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B120: PBYTE Position      */
#define GPIO_PORT_B120_PBYTE_Msk                              (0x01UL << GPIO_PORT_B120_PBYTE_Pos)                      /*!< GPIO_PORT B120: PBYTE Mask          */

// -------------------------------------  GPIO_PORT_B121  -----------------------------------------
#define GPIO_PORT_B121_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B121: PBYTE Position      */
#define GPIO_PORT_B121_PBYTE_Msk                              (0x01UL << GPIO_PORT_B121_PBYTE_Pos)                      /*!< GPIO_PORT B121: PBYTE Mask          */

// -------------------------------------  GPIO_PORT_B122  -----------------------------------------
#define GPIO_PORT_B122_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B122: PBYTE Position      */
#define GPIO_PORT_B122_PBYTE_Msk                              (0x01UL << GPIO_PORT_B122_PBYTE_Pos)                      /*!< GPIO_PORT B122: PBYTE Mask          */

// -------------------------------------  GPIO_PORT_B123  -----------------------------------------
#define GPIO_PORT_B123_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B123: PBYTE Position      */
#define GPIO_PORT_B123_PBYTE_Msk                              (0x01UL << GPIO_PORT_B123_PBYTE_Pos)                      /*!< GPIO_PORT B123: PBYTE Mask          */

// -------------------------------------  GPIO_PORT_B124  -----------------------------------------
#define GPIO_PORT_B124_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B124: PBYTE Position      */
#define GPIO_PORT_B124_PBYTE_Msk                              (0x01UL << GPIO_PORT_B124_PBYTE_Pos)                      /*!< GPIO_PORT B124: PBYTE Mask          */

// -------------------------------------  GPIO_PORT_B125  -----------------------------------------
#define GPIO_PORT_B125_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B125: PBYTE Position      */
#define GPIO_PORT_B125_PBYTE_Msk                              (0x01UL << GPIO_PORT_B125_PBYTE_Pos)                      /*!< GPIO_PORT B125: PBYTE Mask          */

// -------------------------------------  GPIO_PORT_B126  -----------------------------------------
#define GPIO_PORT_B126_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B126: PBYTE Position      */
#define GPIO_PORT_B126_PBYTE_Msk                              (0x01UL << GPIO_PORT_B126_PBYTE_Pos)                      /*!< GPIO_PORT B126: PBYTE Mask          */

// -------------------------------------  GPIO_PORT_B127  -----------------------------------------
#define GPIO_PORT_B127_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B127: PBYTE Position      */
#define GPIO_PORT_B127_PBYTE_Msk                              (0x01UL << GPIO_PORT_B127_PBYTE_Pos)                      /*!< GPIO_PORT B127: PBYTE Mask          */

// -------------------------------------  GPIO_PORT_B128  -----------------------------------------
#define GPIO_PORT_B128_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B128: PBYTE Position      */
#define GPIO_PORT_B128_PBYTE_Msk                              (0x01UL << GPIO_PORT_B128_PBYTE_Pos)                      /*!< GPIO_PORT B128: PBYTE Mask          */

// -------------------------------------  GPIO_PORT_B129  -----------------------------------------
#define GPIO_PORT_B129_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B129: PBYTE Position      */
#define GPIO_PORT_B129_PBYTE_Msk                              (0x01UL << GPIO_PORT_B129_PBYTE_Pos)                      /*!< GPIO_PORT B129: PBYTE Mask          */

// -------------------------------------  GPIO_PORT_B130  -----------------------------------------
#define GPIO_PORT_B130_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B130: PBYTE Position      */
#define GPIO_PORT_B130_PBYTE_Msk                              (0x01UL << GPIO_PORT_B130_PBYTE_Pos)                      /*!< GPIO_PORT B130: PBYTE Mask          */

// -------------------------------------  GPIO_PORT_B131  -----------------------------------------
#define GPIO_PORT_B131_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B131: PBYTE Position      */
#define GPIO_PORT_B131_PBYTE_Msk                              (0x01UL << GPIO_PORT_B131_PBYTE_Pos)                      /*!< GPIO_PORT B131: PBYTE Mask          */

// -------------------------------------  GPIO_PORT_B132  -----------------------------------------
#define GPIO_PORT_B132_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B132: PBYTE Position      */
#define GPIO_PORT_B132_PBYTE_Msk                              (0x01UL << GPIO_PORT_B132_PBYTE_Pos)                      /*!< GPIO_PORT B132: PBYTE Mask          */

// -------------------------------------  GPIO_PORT_B133  -----------------------------------------
#define GPIO_PORT_B133_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B133: PBYTE Position      */
#define GPIO_PORT_B133_PBYTE_Msk                              (0x01UL << GPIO_PORT_B133_PBYTE_Pos)                      /*!< GPIO_PORT B133: PBYTE Mask          */

// -------------------------------------  GPIO_PORT_B134  -----------------------------------------
#define GPIO_PORT_B134_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B134: PBYTE Position      */
#define GPIO_PORT_B134_PBYTE_Msk                              (0x01UL << GPIO_PORT_B134_PBYTE_Pos)                      /*!< GPIO_PORT B134: PBYTE Mask          */

// -------------------------------------  GPIO_PORT_B135  -----------------------------------------
#define GPIO_PORT_B135_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B135: PBYTE Position      */
#define GPIO_PORT_B135_PBYTE_Msk                              (0x01UL << GPIO_PORT_B135_PBYTE_Pos)                      /*!< GPIO_PORT B135: PBYTE Mask          */

// -------------------------------------  GPIO_PORT_B136  -----------------------------------------
#define GPIO_PORT_B136_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B136: PBYTE Position      */
#define GPIO_PORT_B136_PBYTE_Msk                              (0x01UL << GPIO_PORT_B136_PBYTE_Pos)                      /*!< GPIO_PORT B136: PBYTE Mask          */

// -------------------------------------  GPIO_PORT_B137  -----------------------------------------
#define GPIO_PORT_B137_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B137: PBYTE Position      */
#define GPIO_PORT_B137_PBYTE_Msk                              (0x01UL << GPIO_PORT_B137_PBYTE_Pos)                      /*!< GPIO_PORT B137: PBYTE Mask          */

// -------------------------------------  GPIO_PORT_B138  -----------------------------------------
#define GPIO_PORT_B138_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B138: PBYTE Position      */
#define GPIO_PORT_B138_PBYTE_Msk                              (0x01UL << GPIO_PORT_B138_PBYTE_Pos)                      /*!< GPIO_PORT B138: PBYTE Mask          */

// -------------------------------------  GPIO_PORT_B139  -----------------------------------------
#define GPIO_PORT_B139_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B139: PBYTE Position      */
#define GPIO_PORT_B139_PBYTE_Msk                              (0x01UL << GPIO_PORT_B139_PBYTE_Pos)                      /*!< GPIO_PORT B139: PBYTE Mask          */

// -------------------------------------  GPIO_PORT_B140  -----------------------------------------
#define GPIO_PORT_B140_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B140: PBYTE Position      */
#define GPIO_PORT_B140_PBYTE_Msk                              (0x01UL << GPIO_PORT_B140_PBYTE_Pos)                      /*!< GPIO_PORT B140: PBYTE Mask          */

// -------------------------------------  GPIO_PORT_B141  -----------------------------------------
#define GPIO_PORT_B141_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B141: PBYTE Position      */
#define GPIO_PORT_B141_PBYTE_Msk                              (0x01UL << GPIO_PORT_B141_PBYTE_Pos)                      /*!< GPIO_PORT B141: PBYTE Mask          */

// -------------------------------------  GPIO_PORT_B142  -----------------------------------------
#define GPIO_PORT_B142_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B142: PBYTE Position      */
#define GPIO_PORT_B142_PBYTE_Msk                              (0x01UL << GPIO_PORT_B142_PBYTE_Pos)                      /*!< GPIO_PORT B142: PBYTE Mask          */

// -------------------------------------  GPIO_PORT_B143  -----------------------------------------
#define GPIO_PORT_B143_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B143: PBYTE Position      */
#define GPIO_PORT_B143_PBYTE_Msk                              (0x01UL << GPIO_PORT_B143_PBYTE_Pos)                      /*!< GPIO_PORT B143: PBYTE Mask          */

// -------------------------------------  GPIO_PORT_B144  -----------------------------------------
#define GPIO_PORT_B144_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B144: PBYTE Position      */
#define GPIO_PORT_B144_PBYTE_Msk                              (0x01UL << GPIO_PORT_B144_PBYTE_Pos)                      /*!< GPIO_PORT B144: PBYTE Mask          */

// -------------------------------------  GPIO_PORT_B145  -----------------------------------------
#define GPIO_PORT_B145_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B145: PBYTE Position      */
#define GPIO_PORT_B145_PBYTE_Msk                              (0x01UL << GPIO_PORT_B145_PBYTE_Pos)                      /*!< GPIO_PORT B145: PBYTE Mask          */

// -------------------------------------  GPIO_PORT_B146  -----------------------------------------
#define GPIO_PORT_B146_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B146: PBYTE Position      */
#define GPIO_PORT_B146_PBYTE_Msk                              (0x01UL << GPIO_PORT_B146_PBYTE_Pos)                      /*!< GPIO_PORT B146: PBYTE Mask          */

// -------------------------------------  GPIO_PORT_B147  -----------------------------------------
#define GPIO_PORT_B147_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B147: PBYTE Position      */
#define GPIO_PORT_B147_PBYTE_Msk                              (0x01UL << GPIO_PORT_B147_PBYTE_Pos)                      /*!< GPIO_PORT B147: PBYTE Mask          */

// -------------------------------------  GPIO_PORT_B148  -----------------------------------------
#define GPIO_PORT_B148_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B148: PBYTE Position      */
#define GPIO_PORT_B148_PBYTE_Msk                              (0x01UL << GPIO_PORT_B148_PBYTE_Pos)                      /*!< GPIO_PORT B148: PBYTE Mask          */

// -------------------------------------  GPIO_PORT_B149  -----------------------------------------
#define GPIO_PORT_B149_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B149: PBYTE Position      */
#define GPIO_PORT_B149_PBYTE_Msk                              (0x01UL << GPIO_PORT_B149_PBYTE_Pos)                      /*!< GPIO_PORT B149: PBYTE Mask          */

// -------------------------------------  GPIO_PORT_B150  -----------------------------------------
#define GPIO_PORT_B150_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B150: PBYTE Position      */
#define GPIO_PORT_B150_PBYTE_Msk                              (0x01UL << GPIO_PORT_B150_PBYTE_Pos)                      /*!< GPIO_PORT B150: PBYTE Mask          */

// -------------------------------------  GPIO_PORT_B151  -----------------------------------------
#define GPIO_PORT_B151_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B151: PBYTE Position      */
#define GPIO_PORT_B151_PBYTE_Msk                              (0x01UL << GPIO_PORT_B151_PBYTE_Pos)                      /*!< GPIO_PORT B151: PBYTE Mask          */

// -------------------------------------  GPIO_PORT_B152  -----------------------------------------
#define GPIO_PORT_B152_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B152: PBYTE Position      */
#define GPIO_PORT_B152_PBYTE_Msk                              (0x01UL << GPIO_PORT_B152_PBYTE_Pos)                      /*!< GPIO_PORT B152: PBYTE Mask          */

// -------------------------------------  GPIO_PORT_B153  -----------------------------------------
#define GPIO_PORT_B153_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B153: PBYTE Position      */
#define GPIO_PORT_B153_PBYTE_Msk                              (0x01UL << GPIO_PORT_B153_PBYTE_Pos)                      /*!< GPIO_PORT B153: PBYTE Mask          */

// -------------------------------------  GPIO_PORT_B154  -----------------------------------------
#define GPIO_PORT_B154_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B154: PBYTE Position      */
#define GPIO_PORT_B154_PBYTE_Msk                              (0x01UL << GPIO_PORT_B154_PBYTE_Pos)                      /*!< GPIO_PORT B154: PBYTE Mask          */

// -------------------------------------  GPIO_PORT_B155  -----------------------------------------
#define GPIO_PORT_B155_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B155: PBYTE Position      */
#define GPIO_PORT_B155_PBYTE_Msk                              (0x01UL << GPIO_PORT_B155_PBYTE_Pos)                      /*!< GPIO_PORT B155: PBYTE Mask          */

// -------------------------------------  GPIO_PORT_B156  -----------------------------------------
#define GPIO_PORT_B156_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B156: PBYTE Position      */
#define GPIO_PORT_B156_PBYTE_Msk                              (0x01UL << GPIO_PORT_B156_PBYTE_Pos)                      /*!< GPIO_PORT B156: PBYTE Mask          */

// -------------------------------------  GPIO_PORT_B157  -----------------------------------------
#define GPIO_PORT_B157_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B157: PBYTE Position      */
#define GPIO_PORT_B157_PBYTE_Msk                              (0x01UL << GPIO_PORT_B157_PBYTE_Pos)                      /*!< GPIO_PORT B157: PBYTE Mask          */

// -------------------------------------  GPIO_PORT_B158  -----------------------------------------
#define GPIO_PORT_B158_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B158: PBYTE Position      */
#define GPIO_PORT_B158_PBYTE_Msk                              (0x01UL << GPIO_PORT_B158_PBYTE_Pos)                      /*!< GPIO_PORT B158: PBYTE Mask          */

// -------------------------------------  GPIO_PORT_B159  -----------------------------------------
#define GPIO_PORT_B159_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B159: PBYTE Position      */
#define GPIO_PORT_B159_PBYTE_Msk                              (0x01UL << GPIO_PORT_B159_PBYTE_Pos)                      /*!< GPIO_PORT B159: PBYTE Mask          */

// -------------------------------------  GPIO_PORT_B160  -----------------------------------------
#define GPIO_PORT_B160_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B160: PBYTE Position      */
#define GPIO_PORT_B160_PBYTE_Msk                              (0x01UL << GPIO_PORT_B160_PBYTE_Pos)                      /*!< GPIO_PORT B160: PBYTE Mask          */

// -------------------------------------  GPIO_PORT_B161  -----------------------------------------
#define GPIO_PORT_B161_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B161: PBYTE Position      */
#define GPIO_PORT_B161_PBYTE_Msk                              (0x01UL << GPIO_PORT_B161_PBYTE_Pos)                      /*!< GPIO_PORT B161: PBYTE Mask          */

// -------------------------------------  GPIO_PORT_B162  -----------------------------------------
#define GPIO_PORT_B162_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B162: PBYTE Position      */
#define GPIO_PORT_B162_PBYTE_Msk                              (0x01UL << GPIO_PORT_B162_PBYTE_Pos)                      /*!< GPIO_PORT B162: PBYTE Mask          */

// -------------------------------------  GPIO_PORT_B163  -----------------------------------------
#define GPIO_PORT_B163_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B163: PBYTE Position      */
#define GPIO_PORT_B163_PBYTE_Msk                              (0x01UL << GPIO_PORT_B163_PBYTE_Pos)                      /*!< GPIO_PORT B163: PBYTE Mask          */

// -------------------------------------  GPIO_PORT_B164  -----------------------------------------
#define GPIO_PORT_B164_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B164: PBYTE Position      */
#define GPIO_PORT_B164_PBYTE_Msk                              (0x01UL << GPIO_PORT_B164_PBYTE_Pos)                      /*!< GPIO_PORT B164: PBYTE Mask          */

// -------------------------------------  GPIO_PORT_B165  -----------------------------------------
#define GPIO_PORT_B165_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B165: PBYTE Position      */
#define GPIO_PORT_B165_PBYTE_Msk                              (0x01UL << GPIO_PORT_B165_PBYTE_Pos)                      /*!< GPIO_PORT B165: PBYTE Mask          */

// -------------------------------------  GPIO_PORT_B166  -----------------------------------------
#define GPIO_PORT_B166_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B166: PBYTE Position      */
#define GPIO_PORT_B166_PBYTE_Msk                              (0x01UL << GPIO_PORT_B166_PBYTE_Pos)                      /*!< GPIO_PORT B166: PBYTE Mask          */

// -------------------------------------  GPIO_PORT_B167  -----------------------------------------
#define GPIO_PORT_B167_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B167: PBYTE Position      */
#define GPIO_PORT_B167_PBYTE_Msk                              (0x01UL << GPIO_PORT_B167_PBYTE_Pos)                      /*!< GPIO_PORT B167: PBYTE Mask          */

// -------------------------------------  GPIO_PORT_B168  -----------------------------------------
#define GPIO_PORT_B168_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B168: PBYTE Position      */
#define GPIO_PORT_B168_PBYTE_Msk                              (0x01UL << GPIO_PORT_B168_PBYTE_Pos)                      /*!< GPIO_PORT B168: PBYTE Mask          */

// -------------------------------------  GPIO_PORT_B169  -----------------------------------------
#define GPIO_PORT_B169_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B169: PBYTE Position      */
#define GPIO_PORT_B169_PBYTE_Msk                              (0x01UL << GPIO_PORT_B169_PBYTE_Pos)                      /*!< GPIO_PORT B169: PBYTE Mask          */

// -------------------------------------  GPIO_PORT_B170  -----------------------------------------
#define GPIO_PORT_B170_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B170: PBYTE Position      */
#define GPIO_PORT_B170_PBYTE_Msk                              (0x01UL << GPIO_PORT_B170_PBYTE_Pos)                      /*!< GPIO_PORT B170: PBYTE Mask          */

// -------------------------------------  GPIO_PORT_B171  -----------------------------------------
#define GPIO_PORT_B171_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B171: PBYTE Position      */
#define GPIO_PORT_B171_PBYTE_Msk                              (0x01UL << GPIO_PORT_B171_PBYTE_Pos)                      /*!< GPIO_PORT B171: PBYTE Mask          */

// -------------------------------------  GPIO_PORT_B172  -----------------------------------------
#define GPIO_PORT_B172_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B172: PBYTE Position      */
#define GPIO_PORT_B172_PBYTE_Msk                              (0x01UL << GPIO_PORT_B172_PBYTE_Pos)                      /*!< GPIO_PORT B172: PBYTE Mask          */

// -------------------------------------  GPIO_PORT_B173  -----------------------------------------
#define GPIO_PORT_B173_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B173: PBYTE Position      */
#define GPIO_PORT_B173_PBYTE_Msk                              (0x01UL << GPIO_PORT_B173_PBYTE_Pos)                      /*!< GPIO_PORT B173: PBYTE Mask          */

// -------------------------------------  GPIO_PORT_B174  -----------------------------------------
#define GPIO_PORT_B174_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B174: PBYTE Position      */
#define GPIO_PORT_B174_PBYTE_Msk                              (0x01UL << GPIO_PORT_B174_PBYTE_Pos)                      /*!< GPIO_PORT B174: PBYTE Mask          */

// -------------------------------------  GPIO_PORT_B175  -----------------------------------------
#define GPIO_PORT_B175_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B175: PBYTE Position      */
#define GPIO_PORT_B175_PBYTE_Msk                              (0x01UL << GPIO_PORT_B175_PBYTE_Pos)                      /*!< GPIO_PORT B175: PBYTE Mask          */

// -------------------------------------  GPIO_PORT_B176  -----------------------------------------
#define GPIO_PORT_B176_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B176: PBYTE Position      */
#define GPIO_PORT_B176_PBYTE_Msk                              (0x01UL << GPIO_PORT_B176_PBYTE_Pos)                      /*!< GPIO_PORT B176: PBYTE Mask          */

// -------------------------------------  GPIO_PORT_B177  -----------------------------------------
#define GPIO_PORT_B177_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B177: PBYTE Position      */
#define GPIO_PORT_B177_PBYTE_Msk                              (0x01UL << GPIO_PORT_B177_PBYTE_Pos)                      /*!< GPIO_PORT B177: PBYTE Mask          */

// -------------------------------------  GPIO_PORT_B178  -----------------------------------------
#define GPIO_PORT_B178_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B178: PBYTE Position      */
#define GPIO_PORT_B178_PBYTE_Msk                              (0x01UL << GPIO_PORT_B178_PBYTE_Pos)                      /*!< GPIO_PORT B178: PBYTE Mask          */

// -------------------------------------  GPIO_PORT_B179  -----------------------------------------
#define GPIO_PORT_B179_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B179: PBYTE Position      */
#define GPIO_PORT_B179_PBYTE_Msk                              (0x01UL << GPIO_PORT_B179_PBYTE_Pos)                      /*!< GPIO_PORT B179: PBYTE Mask          */

// -------------------------------------  GPIO_PORT_B180  -----------------------------------------
#define GPIO_PORT_B180_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B180: PBYTE Position      */
#define GPIO_PORT_B180_PBYTE_Msk                              (0x01UL << GPIO_PORT_B180_PBYTE_Pos)                      /*!< GPIO_PORT B180: PBYTE Mask          */

// -------------------------------------  GPIO_PORT_B181  -----------------------------------------
#define GPIO_PORT_B181_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B181: PBYTE Position      */
#define GPIO_PORT_B181_PBYTE_Msk                              (0x01UL << GPIO_PORT_B181_PBYTE_Pos)                      /*!< GPIO_PORT B181: PBYTE Mask          */

// -------------------------------------  GPIO_PORT_B182  -----------------------------------------
#define GPIO_PORT_B182_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B182: PBYTE Position      */
#define GPIO_PORT_B182_PBYTE_Msk                              (0x01UL << GPIO_PORT_B182_PBYTE_Pos)                      /*!< GPIO_PORT B182: PBYTE Mask          */

// -------------------------------------  GPIO_PORT_B183  -----------------------------------------
#define GPIO_PORT_B183_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B183: PBYTE Position      */
#define GPIO_PORT_B183_PBYTE_Msk                              (0x01UL << GPIO_PORT_B183_PBYTE_Pos)                      /*!< GPIO_PORT B183: PBYTE Mask          */

// -------------------------------------  GPIO_PORT_B184  -----------------------------------------
#define GPIO_PORT_B184_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B184: PBYTE Position      */
#define GPIO_PORT_B184_PBYTE_Msk                              (0x01UL << GPIO_PORT_B184_PBYTE_Pos)                      /*!< GPIO_PORT B184: PBYTE Mask          */

// -------------------------------------  GPIO_PORT_B185  -----------------------------------------
#define GPIO_PORT_B185_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B185: PBYTE Position      */
#define GPIO_PORT_B185_PBYTE_Msk                              (0x01UL << GPIO_PORT_B185_PBYTE_Pos)                      /*!< GPIO_PORT B185: PBYTE Mask          */

// -------------------------------------  GPIO_PORT_B186  -----------------------------------------
#define GPIO_PORT_B186_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B186: PBYTE Position      */
#define GPIO_PORT_B186_PBYTE_Msk                              (0x01UL << GPIO_PORT_B186_PBYTE_Pos)                      /*!< GPIO_PORT B186: PBYTE Mask          */

// -------------------------------------  GPIO_PORT_B187  -----------------------------------------
#define GPIO_PORT_B187_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B187: PBYTE Position      */
#define GPIO_PORT_B187_PBYTE_Msk                              (0x01UL << GPIO_PORT_B187_PBYTE_Pos)                      /*!< GPIO_PORT B187: PBYTE Mask          */

// -------------------------------------  GPIO_PORT_B188  -----------------------------------------
#define GPIO_PORT_B188_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B188: PBYTE Position      */
#define GPIO_PORT_B188_PBYTE_Msk                              (0x01UL << GPIO_PORT_B188_PBYTE_Pos)                      /*!< GPIO_PORT B188: PBYTE Mask          */

// -------------------------------------  GPIO_PORT_B189  -----------------------------------------
#define GPIO_PORT_B189_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B189: PBYTE Position      */
#define GPIO_PORT_B189_PBYTE_Msk                              (0x01UL << GPIO_PORT_B189_PBYTE_Pos)                      /*!< GPIO_PORT B189: PBYTE Mask          */

// -------------------------------------  GPIO_PORT_B190  -----------------------------------------
#define GPIO_PORT_B190_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B190: PBYTE Position      */
#define GPIO_PORT_B190_PBYTE_Msk                              (0x01UL << GPIO_PORT_B190_PBYTE_Pos)                      /*!< GPIO_PORT B190: PBYTE Mask          */

// -------------------------------------  GPIO_PORT_B191  -----------------------------------------
#define GPIO_PORT_B191_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B191: PBYTE Position      */
#define GPIO_PORT_B191_PBYTE_Msk                              (0x01UL << GPIO_PORT_B191_PBYTE_Pos)                      /*!< GPIO_PORT B191: PBYTE Mask          */

// -------------------------------------  GPIO_PORT_B192  -----------------------------------------
#define GPIO_PORT_B192_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B192: PBYTE Position      */
#define GPIO_PORT_B192_PBYTE_Msk                              (0x01UL << GPIO_PORT_B192_PBYTE_Pos)                      /*!< GPIO_PORT B192: PBYTE Mask          */

// -------------------------------------  GPIO_PORT_B193  -----------------------------------------
#define GPIO_PORT_B193_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B193: PBYTE Position      */
#define GPIO_PORT_B193_PBYTE_Msk                              (0x01UL << GPIO_PORT_B193_PBYTE_Pos)                      /*!< GPIO_PORT B193: PBYTE Mask          */

// -------------------------------------  GPIO_PORT_B194  -----------------------------------------
#define GPIO_PORT_B194_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B194: PBYTE Position      */
#define GPIO_PORT_B194_PBYTE_Msk                              (0x01UL << GPIO_PORT_B194_PBYTE_Pos)                      /*!< GPIO_PORT B194: PBYTE Mask          */

// -------------------------------------  GPIO_PORT_B195  -----------------------------------------
#define GPIO_PORT_B195_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B195: PBYTE Position      */
#define GPIO_PORT_B195_PBYTE_Msk                              (0x01UL << GPIO_PORT_B195_PBYTE_Pos)                      /*!< GPIO_PORT B195: PBYTE Mask          */

// -------------------------------------  GPIO_PORT_B196  -----------------------------------------
#define GPIO_PORT_B196_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B196: PBYTE Position      */
#define GPIO_PORT_B196_PBYTE_Msk                              (0x01UL << GPIO_PORT_B196_PBYTE_Pos)                      /*!< GPIO_PORT B196: PBYTE Mask          */

// -------------------------------------  GPIO_PORT_B197  -----------------------------------------
#define GPIO_PORT_B197_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B197: PBYTE Position      */
#define GPIO_PORT_B197_PBYTE_Msk                              (0x01UL << GPIO_PORT_B197_PBYTE_Pos)                      /*!< GPIO_PORT B197: PBYTE Mask          */

// -------------------------------------  GPIO_PORT_B198  -----------------------------------------
#define GPIO_PORT_B198_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B198: PBYTE Position      */
#define GPIO_PORT_B198_PBYTE_Msk                              (0x01UL << GPIO_PORT_B198_PBYTE_Pos)                      /*!< GPIO_PORT B198: PBYTE Mask          */

// -------------------------------------  GPIO_PORT_B199  -----------------------------------------
#define GPIO_PORT_B199_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B199: PBYTE Position      */
#define GPIO_PORT_B199_PBYTE_Msk                              (0x01UL << GPIO_PORT_B199_PBYTE_Pos)                      /*!< GPIO_PORT B199: PBYTE Mask          */

// -------------------------------------  GPIO_PORT_B200  -----------------------------------------
#define GPIO_PORT_B200_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B200: PBYTE Position      */
#define GPIO_PORT_B200_PBYTE_Msk                              (0x01UL << GPIO_PORT_B200_PBYTE_Pos)                      /*!< GPIO_PORT B200: PBYTE Mask          */

// -------------------------------------  GPIO_PORT_B201  -----------------------------------------
#define GPIO_PORT_B201_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B201: PBYTE Position      */
#define GPIO_PORT_B201_PBYTE_Msk                              (0x01UL << GPIO_PORT_B201_PBYTE_Pos)                      /*!< GPIO_PORT B201: PBYTE Mask          */

// -------------------------------------  GPIO_PORT_B202  -----------------------------------------
#define GPIO_PORT_B202_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B202: PBYTE Position      */
#define GPIO_PORT_B202_PBYTE_Msk                              (0x01UL << GPIO_PORT_B202_PBYTE_Pos)                      /*!< GPIO_PORT B202: PBYTE Mask          */

// -------------------------------------  GPIO_PORT_B203  -----------------------------------------
#define GPIO_PORT_B203_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B203: PBYTE Position      */
#define GPIO_PORT_B203_PBYTE_Msk                              (0x01UL << GPIO_PORT_B203_PBYTE_Pos)                      /*!< GPIO_PORT B203: PBYTE Mask          */

// -------------------------------------  GPIO_PORT_B204  -----------------------------------------
#define GPIO_PORT_B204_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B204: PBYTE Position      */
#define GPIO_PORT_B204_PBYTE_Msk                              (0x01UL << GPIO_PORT_B204_PBYTE_Pos)                      /*!< GPIO_PORT B204: PBYTE Mask          */

// -------------------------------------  GPIO_PORT_B205  -----------------------------------------
#define GPIO_PORT_B205_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B205: PBYTE Position      */
#define GPIO_PORT_B205_PBYTE_Msk                              (0x01UL << GPIO_PORT_B205_PBYTE_Pos)                      /*!< GPIO_PORT B205: PBYTE Mask          */

// -------------------------------------  GPIO_PORT_B206  -----------------------------------------
#define GPIO_PORT_B206_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B206: PBYTE Position      */
#define GPIO_PORT_B206_PBYTE_Msk                              (0x01UL << GPIO_PORT_B206_PBYTE_Pos)                      /*!< GPIO_PORT B206: PBYTE Mask          */

// -------------------------------------  GPIO_PORT_B207  -----------------------------------------
#define GPIO_PORT_B207_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B207: PBYTE Position      */
#define GPIO_PORT_B207_PBYTE_Msk                              (0x01UL << GPIO_PORT_B207_PBYTE_Pos)                      /*!< GPIO_PORT B207: PBYTE Mask          */

// -------------------------------------  GPIO_PORT_B208  -----------------------------------------
#define GPIO_PORT_B208_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B208: PBYTE Position      */
#define GPIO_PORT_B208_PBYTE_Msk                              (0x01UL << GPIO_PORT_B208_PBYTE_Pos)                      /*!< GPIO_PORT B208: PBYTE Mask          */

// -------------------------------------  GPIO_PORT_B209  -----------------------------------------
#define GPIO_PORT_B209_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B209: PBYTE Position      */
#define GPIO_PORT_B209_PBYTE_Msk                              (0x01UL << GPIO_PORT_B209_PBYTE_Pos)                      /*!< GPIO_PORT B209: PBYTE Mask          */

// -------------------------------------  GPIO_PORT_B210  -----------------------------------------
#define GPIO_PORT_B210_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B210: PBYTE Position      */
#define GPIO_PORT_B210_PBYTE_Msk                              (0x01UL << GPIO_PORT_B210_PBYTE_Pos)                      /*!< GPIO_PORT B210: PBYTE Mask          */

// -------------------------------------  GPIO_PORT_B211  -----------------------------------------
#define GPIO_PORT_B211_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B211: PBYTE Position      */
#define GPIO_PORT_B211_PBYTE_Msk                              (0x01UL << GPIO_PORT_B211_PBYTE_Pos)                      /*!< GPIO_PORT B211: PBYTE Mask          */

// -------------------------------------  GPIO_PORT_B212  -----------------------------------------
#define GPIO_PORT_B212_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B212: PBYTE Position      */
#define GPIO_PORT_B212_PBYTE_Msk                              (0x01UL << GPIO_PORT_B212_PBYTE_Pos)                      /*!< GPIO_PORT B212: PBYTE Mask          */

// -------------------------------------  GPIO_PORT_B213  -----------------------------------------
#define GPIO_PORT_B213_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B213: PBYTE Position      */
#define GPIO_PORT_B213_PBYTE_Msk                              (0x01UL << GPIO_PORT_B213_PBYTE_Pos)                      /*!< GPIO_PORT B213: PBYTE Mask          */

// -------------------------------------  GPIO_PORT_B214  -----------------------------------------
#define GPIO_PORT_B214_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B214: PBYTE Position      */
#define GPIO_PORT_B214_PBYTE_Msk                              (0x01UL << GPIO_PORT_B214_PBYTE_Pos)                      /*!< GPIO_PORT B214: PBYTE Mask          */

// -------------------------------------  GPIO_PORT_B215  -----------------------------------------
#define GPIO_PORT_B215_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B215: PBYTE Position      */
#define GPIO_PORT_B215_PBYTE_Msk                              (0x01UL << GPIO_PORT_B215_PBYTE_Pos)                      /*!< GPIO_PORT B215: PBYTE Mask          */

// -------------------------------------  GPIO_PORT_B216  -----------------------------------------
#define GPIO_PORT_B216_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B216: PBYTE Position      */
#define GPIO_PORT_B216_PBYTE_Msk                              (0x01UL << GPIO_PORT_B216_PBYTE_Pos)                      /*!< GPIO_PORT B216: PBYTE Mask          */

// -------------------------------------  GPIO_PORT_B217  -----------------------------------------
#define GPIO_PORT_B217_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B217: PBYTE Position      */
#define GPIO_PORT_B217_PBYTE_Msk                              (0x01UL << GPIO_PORT_B217_PBYTE_Pos)                      /*!< GPIO_PORT B217: PBYTE Mask          */

// -------------------------------------  GPIO_PORT_B218  -----------------------------------------
#define GPIO_PORT_B218_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B218: PBYTE Position      */
#define GPIO_PORT_B218_PBYTE_Msk                              (0x01UL << GPIO_PORT_B218_PBYTE_Pos)                      /*!< GPIO_PORT B218: PBYTE Mask          */

// -------------------------------------  GPIO_PORT_B219  -----------------------------------------
#define GPIO_PORT_B219_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B219: PBYTE Position      */
#define GPIO_PORT_B219_PBYTE_Msk                              (0x01UL << GPIO_PORT_B219_PBYTE_Pos)                      /*!< GPIO_PORT B219: PBYTE Mask          */

// -------------------------------------  GPIO_PORT_B220  -----------------------------------------
#define GPIO_PORT_B220_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B220: PBYTE Position      */
#define GPIO_PORT_B220_PBYTE_Msk                              (0x01UL << GPIO_PORT_B220_PBYTE_Pos)                      /*!< GPIO_PORT B220: PBYTE Mask          */

// -------------------------------------  GPIO_PORT_B221  -----------------------------------------
#define GPIO_PORT_B221_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B221: PBYTE Position      */
#define GPIO_PORT_B221_PBYTE_Msk                              (0x01UL << GPIO_PORT_B221_PBYTE_Pos)                      /*!< GPIO_PORT B221: PBYTE Mask          */

// -------------------------------------  GPIO_PORT_B222  -----------------------------------------
#define GPIO_PORT_B222_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B222: PBYTE Position      */
#define GPIO_PORT_B222_PBYTE_Msk                              (0x01UL << GPIO_PORT_B222_PBYTE_Pos)                      /*!< GPIO_PORT B222: PBYTE Mask          */

// -------------------------------------  GPIO_PORT_B223  -----------------------------------------
#define GPIO_PORT_B223_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B223: PBYTE Position      */
#define GPIO_PORT_B223_PBYTE_Msk                              (0x01UL << GPIO_PORT_B223_PBYTE_Pos)                      /*!< GPIO_PORT B223: PBYTE Mask          */

// -------------------------------------  GPIO_PORT_B224  -----------------------------------------
#define GPIO_PORT_B224_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B224: PBYTE Position      */
#define GPIO_PORT_B224_PBYTE_Msk                              (0x01UL << GPIO_PORT_B224_PBYTE_Pos)                      /*!< GPIO_PORT B224: PBYTE Mask          */

// -------------------------------------  GPIO_PORT_B225  -----------------------------------------
#define GPIO_PORT_B225_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B225: PBYTE Position      */
#define GPIO_PORT_B225_PBYTE_Msk                              (0x01UL << GPIO_PORT_B225_PBYTE_Pos)                      /*!< GPIO_PORT B225: PBYTE Mask          */

// -------------------------------------  GPIO_PORT_B226  -----------------------------------------
#define GPIO_PORT_B226_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B226: PBYTE Position      */
#define GPIO_PORT_B226_PBYTE_Msk                              (0x01UL << GPIO_PORT_B226_PBYTE_Pos)                      /*!< GPIO_PORT B226: PBYTE Mask          */

// -------------------------------------  GPIO_PORT_B227  -----------------------------------------
#define GPIO_PORT_B227_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B227: PBYTE Position      */
#define GPIO_PORT_B227_PBYTE_Msk                              (0x01UL << GPIO_PORT_B227_PBYTE_Pos)                      /*!< GPIO_PORT B227: PBYTE Mask          */

// -------------------------------------  GPIO_PORT_B228  -----------------------------------------
#define GPIO_PORT_B228_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B228: PBYTE Position      */
#define GPIO_PORT_B228_PBYTE_Msk                              (0x01UL << GPIO_PORT_B228_PBYTE_Pos)                      /*!< GPIO_PORT B228: PBYTE Mask          */

// -------------------------------------  GPIO_PORT_B229  -----------------------------------------
#define GPIO_PORT_B229_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B229: PBYTE Position      */
#define GPIO_PORT_B229_PBYTE_Msk                              (0x01UL << GPIO_PORT_B229_PBYTE_Pos)                      /*!< GPIO_PORT B229: PBYTE Mask          */

// -------------------------------------  GPIO_PORT_B230  -----------------------------------------
#define GPIO_PORT_B230_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B230: PBYTE Position      */
#define GPIO_PORT_B230_PBYTE_Msk                              (0x01UL << GPIO_PORT_B230_PBYTE_Pos)                      /*!< GPIO_PORT B230: PBYTE Mask          */

// -------------------------------------  GPIO_PORT_B231  -----------------------------------------
#define GPIO_PORT_B231_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B231: PBYTE Position      */
#define GPIO_PORT_B231_PBYTE_Msk                              (0x01UL << GPIO_PORT_B231_PBYTE_Pos)                      /*!< GPIO_PORT B231: PBYTE Mask          */

// -------------------------------------  GPIO_PORT_B232  -----------------------------------------
#define GPIO_PORT_B232_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B232: PBYTE Position      */
#define GPIO_PORT_B232_PBYTE_Msk                              (0x01UL << GPIO_PORT_B232_PBYTE_Pos)                      /*!< GPIO_PORT B232: PBYTE Mask          */

// -------------------------------------  GPIO_PORT_B233  -----------------------------------------
#define GPIO_PORT_B233_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B233: PBYTE Position      */
#define GPIO_PORT_B233_PBYTE_Msk                              (0x01UL << GPIO_PORT_B233_PBYTE_Pos)                      /*!< GPIO_PORT B233: PBYTE Mask          */

// -------------------------------------  GPIO_PORT_B234  -----------------------------------------
#define GPIO_PORT_B234_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B234: PBYTE Position      */
#define GPIO_PORT_B234_PBYTE_Msk                              (0x01UL << GPIO_PORT_B234_PBYTE_Pos)                      /*!< GPIO_PORT B234: PBYTE Mask          */

// -------------------------------------  GPIO_PORT_B235  -----------------------------------------
#define GPIO_PORT_B235_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B235: PBYTE Position      */
#define GPIO_PORT_B235_PBYTE_Msk                              (0x01UL << GPIO_PORT_B235_PBYTE_Pos)                      /*!< GPIO_PORT B235: PBYTE Mask          */

// -------------------------------------  GPIO_PORT_B236  -----------------------------------------
#define GPIO_PORT_B236_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B236: PBYTE Position      */
#define GPIO_PORT_B236_PBYTE_Msk                              (0x01UL << GPIO_PORT_B236_PBYTE_Pos)                      /*!< GPIO_PORT B236: PBYTE Mask          */

// -------------------------------------  GPIO_PORT_B237  -----------------------------------------
#define GPIO_PORT_B237_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B237: PBYTE Position      */
#define GPIO_PORT_B237_PBYTE_Msk                              (0x01UL << GPIO_PORT_B237_PBYTE_Pos)                      /*!< GPIO_PORT B237: PBYTE Mask          */

// -------------------------------------  GPIO_PORT_B238  -----------------------------------------
#define GPIO_PORT_B238_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B238: PBYTE Position      */
#define GPIO_PORT_B238_PBYTE_Msk                              (0x01UL << GPIO_PORT_B238_PBYTE_Pos)                      /*!< GPIO_PORT B238: PBYTE Mask          */

// -------------------------------------  GPIO_PORT_B239  -----------------------------------------
#define GPIO_PORT_B239_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B239: PBYTE Position      */
#define GPIO_PORT_B239_PBYTE_Msk                              (0x01UL << GPIO_PORT_B239_PBYTE_Pos)                      /*!< GPIO_PORT B239: PBYTE Mask          */

// -------------------------------------  GPIO_PORT_B240  -----------------------------------------
#define GPIO_PORT_B240_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B240: PBYTE Position      */
#define GPIO_PORT_B240_PBYTE_Msk                              (0x01UL << GPIO_PORT_B240_PBYTE_Pos)                      /*!< GPIO_PORT B240: PBYTE Mask          */

// -------------------------------------  GPIO_PORT_B241  -----------------------------------------
#define GPIO_PORT_B241_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B241: PBYTE Position      */
#define GPIO_PORT_B241_PBYTE_Msk                              (0x01UL << GPIO_PORT_B241_PBYTE_Pos)                      /*!< GPIO_PORT B241: PBYTE Mask          */

// -------------------------------------  GPIO_PORT_B242  -----------------------------------------
#define GPIO_PORT_B242_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B242: PBYTE Position      */
#define GPIO_PORT_B242_PBYTE_Msk                              (0x01UL << GPIO_PORT_B242_PBYTE_Pos)                      /*!< GPIO_PORT B242: PBYTE Mask          */

// -------------------------------------  GPIO_PORT_B243  -----------------------------------------
#define GPIO_PORT_B243_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B243: PBYTE Position      */
#define GPIO_PORT_B243_PBYTE_Msk                              (0x01UL << GPIO_PORT_B243_PBYTE_Pos)                      /*!< GPIO_PORT B243: PBYTE Mask          */

// -------------------------------------  GPIO_PORT_B244  -----------------------------------------
#define GPIO_PORT_B244_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B244: PBYTE Position      */
#define GPIO_PORT_B244_PBYTE_Msk                              (0x01UL << GPIO_PORT_B244_PBYTE_Pos)                      /*!< GPIO_PORT B244: PBYTE Mask          */

// -------------------------------------  GPIO_PORT_B245  -----------------------------------------
#define GPIO_PORT_B245_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B245: PBYTE Position      */
#define GPIO_PORT_B245_PBYTE_Msk                              (0x01UL << GPIO_PORT_B245_PBYTE_Pos)                      /*!< GPIO_PORT B245: PBYTE Mask          */

// -------------------------------------  GPIO_PORT_B246  -----------------------------------------
#define GPIO_PORT_B246_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B246: PBYTE Position      */
#define GPIO_PORT_B246_PBYTE_Msk                              (0x01UL << GPIO_PORT_B246_PBYTE_Pos)                      /*!< GPIO_PORT B246: PBYTE Mask          */

// -------------------------------------  GPIO_PORT_B247  -----------------------------------------
#define GPIO_PORT_B247_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B247: PBYTE Position      */
#define GPIO_PORT_B247_PBYTE_Msk                              (0x01UL << GPIO_PORT_B247_PBYTE_Pos)                      /*!< GPIO_PORT B247: PBYTE Mask          */

// -------------------------------------  GPIO_PORT_B248  -----------------------------------------
#define GPIO_PORT_B248_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B248: PBYTE Position      */
#define GPIO_PORT_B248_PBYTE_Msk                              (0x01UL << GPIO_PORT_B248_PBYTE_Pos)                      /*!< GPIO_PORT B248: PBYTE Mask          */

// -------------------------------------  GPIO_PORT_B249  -----------------------------------------
#define GPIO_PORT_B249_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B249: PBYTE Position      */
#define GPIO_PORT_B249_PBYTE_Msk                              (0x01UL << GPIO_PORT_B249_PBYTE_Pos)                      /*!< GPIO_PORT B249: PBYTE Mask          */

// -------------------------------------  GPIO_PORT_B250  -----------------------------------------
#define GPIO_PORT_B250_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B250: PBYTE Position      */
#define GPIO_PORT_B250_PBYTE_Msk                              (0x01UL << GPIO_PORT_B250_PBYTE_Pos)                      /*!< GPIO_PORT B250: PBYTE Mask          */

// -------------------------------------  GPIO_PORT_B251  -----------------------------------------
#define GPIO_PORT_B251_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B251: PBYTE Position      */
#define GPIO_PORT_B251_PBYTE_Msk                              (0x01UL << GPIO_PORT_B251_PBYTE_Pos)                      /*!< GPIO_PORT B251: PBYTE Mask          */

// -------------------------------------  GPIO_PORT_B252  -----------------------------------------
#define GPIO_PORT_B252_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B252: PBYTE Position      */
#define GPIO_PORT_B252_PBYTE_Msk                              (0x01UL << GPIO_PORT_B252_PBYTE_Pos)                      /*!< GPIO_PORT B252: PBYTE Mask          */

// -------------------------------------  GPIO_PORT_B253  -----------------------------------------
#define GPIO_PORT_B253_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B253: PBYTE Position      */
#define GPIO_PORT_B253_PBYTE_Msk                              (0x01UL << GPIO_PORT_B253_PBYTE_Pos)                      /*!< GPIO_PORT B253: PBYTE Mask          */

// -------------------------------------  GPIO_PORT_B254  -----------------------------------------
#define GPIO_PORT_B254_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B254: PBYTE Position      */
#define GPIO_PORT_B254_PBYTE_Msk                              (0x01UL << GPIO_PORT_B254_PBYTE_Pos)                      /*!< GPIO_PORT B254: PBYTE Mask          */

// -------------------------------------  GPIO_PORT_B255  -----------------------------------------
#define GPIO_PORT_B255_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B255: PBYTE Position      */
#define GPIO_PORT_B255_PBYTE_Msk                              (0x01UL << GPIO_PORT_B255_PBYTE_Pos)                      /*!< GPIO_PORT B255: PBYTE Mask          */

// --------------------------------------  GPIO_PORT_W0  ------------------------------------------
#define GPIO_PORT_W0_PWORD_Pos                                0                                                         /*!< GPIO_PORT W0: PWORD Position        */
#define GPIO_PORT_W0_PWORD_Msk                                (0xffffffffUL << GPIO_PORT_W0_PWORD_Pos)                  /*!< GPIO_PORT W0: PWORD Mask            */

// --------------------------------------  GPIO_PORT_W1  ------------------------------------------
#define GPIO_PORT_W1_PWORD_Pos                                0                                                         /*!< GPIO_PORT W1: PWORD Position        */
#define GPIO_PORT_W1_PWORD_Msk                                (0xffffffffUL << GPIO_PORT_W1_PWORD_Pos)                  /*!< GPIO_PORT W1: PWORD Mask            */

// --------------------------------------  GPIO_PORT_W2  ------------------------------------------
#define GPIO_PORT_W2_PWORD_Pos                                0                                                         /*!< GPIO_PORT W2: PWORD Position        */
#define GPIO_PORT_W2_PWORD_Msk                                (0xffffffffUL << GPIO_PORT_W2_PWORD_Pos)                  /*!< GPIO_PORT W2: PWORD Mask            */

// --------------------------------------  GPIO_PORT_W3  ------------------------------------------
#define GPIO_PORT_W3_PWORD_Pos                                0                                                         /*!< GPIO_PORT W3: PWORD Position        */
#define GPIO_PORT_W3_PWORD_Msk                                (0xffffffffUL << GPIO_PORT_W3_PWORD_Pos)                  /*!< GPIO_PORT W3: PWORD Mask            */

// --------------------------------------  GPIO_PORT_W4  ------------------------------------------
#define GPIO_PORT_W4_PWORD_Pos                                0                                                         /*!< GPIO_PORT W4: PWORD Position        */
#define GPIO_PORT_W4_PWORD_Msk                                (0xffffffffUL << GPIO_PORT_W4_PWORD_Pos)                  /*!< GPIO_PORT W4: PWORD Mask            */

// --------------------------------------  GPIO_PORT_W5  ------------------------------------------
#define GPIO_PORT_W5_PWORD_Pos                                0                                                         /*!< GPIO_PORT W5: PWORD Position        */
#define GPIO_PORT_W5_PWORD_Msk                                (0xffffffffUL << GPIO_PORT_W5_PWORD_Pos)                  /*!< GPIO_PORT W5: PWORD Mask            */

// --------------------------------------  GPIO_PORT_W6  ------------------------------------------
#define GPIO_PORT_W6_PWORD_Pos                                0                                                         /*!< GPIO_PORT W6: PWORD Position        */
#define GPIO_PORT_W6_PWORD_Msk                                (0xffffffffUL << GPIO_PORT_W6_PWORD_Pos)                  /*!< GPIO_PORT W6: PWORD Mask            */

// --------------------------------------  GPIO_PORT_W7  ------------------------------------------
#define GPIO_PORT_W7_PWORD_Pos                                0                                                         /*!< GPIO_PORT W7: PWORD Position        */
#define GPIO_PORT_W7_PWORD_Msk                                (0xffffffffUL << GPIO_PORT_W7_PWORD_Pos)                  /*!< GPIO_PORT W7: PWORD Mask            */

// --------------------------------------  GPIO_PORT_W8  ------------------------------------------
#define GPIO_PORT_W8_PWORD_Pos                                0                                                         /*!< GPIO_PORT W8: PWORD Position        */
#define GPIO_PORT_W8_PWORD_Msk                                (0xffffffffUL << GPIO_PORT_W8_PWORD_Pos)                  /*!< GPIO_PORT W8: PWORD Mask            */

// --------------------------------------  GPIO_PORT_W9  ------------------------------------------
#define GPIO_PORT_W9_PWORD_Pos                                0                                                         /*!< GPIO_PORT W9: PWORD Position        */
#define GPIO_PORT_W9_PWORD_Msk                                (0xffffffffUL << GPIO_PORT_W9_PWORD_Pos)                  /*!< GPIO_PORT W9: PWORD Mask            */

// --------------------------------------  GPIO_PORT_W10  -----------------------------------------
#define GPIO_PORT_W10_PWORD_Pos                               0                                                         /*!< GPIO_PORT W10: PWORD Position       */
#define GPIO_PORT_W10_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W10_PWORD_Pos)                 /*!< GPIO_PORT W10: PWORD Mask           */

// --------------------------------------  GPIO_PORT_W11  -----------------------------------------
#define GPIO_PORT_W11_PWORD_Pos                               0                                                         /*!< GPIO_PORT W11: PWORD Position       */
#define GPIO_PORT_W11_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W11_PWORD_Pos)                 /*!< GPIO_PORT W11: PWORD Mask           */

// --------------------------------------  GPIO_PORT_W12  -----------------------------------------
#define GPIO_PORT_W12_PWORD_Pos                               0                                                         /*!< GPIO_PORT W12: PWORD Position       */
#define GPIO_PORT_W12_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W12_PWORD_Pos)                 /*!< GPIO_PORT W12: PWORD Mask           */

// --------------------------------------  GPIO_PORT_W13  -----------------------------------------
#define GPIO_PORT_W13_PWORD_Pos                               0                                                         /*!< GPIO_PORT W13: PWORD Position       */
#define GPIO_PORT_W13_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W13_PWORD_Pos)                 /*!< GPIO_PORT W13: PWORD Mask           */

// --------------------------------------  GPIO_PORT_W14  -----------------------------------------
#define GPIO_PORT_W14_PWORD_Pos                               0                                                         /*!< GPIO_PORT W14: PWORD Position       */
#define GPIO_PORT_W14_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W14_PWORD_Pos)                 /*!< GPIO_PORT W14: PWORD Mask           */

// --------------------------------------  GPIO_PORT_W15  -----------------------------------------
#define GPIO_PORT_W15_PWORD_Pos                               0                                                         /*!< GPIO_PORT W15: PWORD Position       */
#define GPIO_PORT_W15_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W15_PWORD_Pos)                 /*!< GPIO_PORT W15: PWORD Mask           */

// --------------------------------------  GPIO_PORT_W16  -----------------------------------------
#define GPIO_PORT_W16_PWORD_Pos                               0                                                         /*!< GPIO_PORT W16: PWORD Position       */
#define GPIO_PORT_W16_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W16_PWORD_Pos)                 /*!< GPIO_PORT W16: PWORD Mask           */

// --------------------------------------  GPIO_PORT_W17  -----------------------------------------
#define GPIO_PORT_W17_PWORD_Pos                               0                                                         /*!< GPIO_PORT W17: PWORD Position       */
#define GPIO_PORT_W17_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W17_PWORD_Pos)                 /*!< GPIO_PORT W17: PWORD Mask           */

// --------------------------------------  GPIO_PORT_W18  -----------------------------------------
#define GPIO_PORT_W18_PWORD_Pos                               0                                                         /*!< GPIO_PORT W18: PWORD Position       */
#define GPIO_PORT_W18_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W18_PWORD_Pos)                 /*!< GPIO_PORT W18: PWORD Mask           */

// --------------------------------------  GPIO_PORT_W19  -----------------------------------------
#define GPIO_PORT_W19_PWORD_Pos                               0                                                         /*!< GPIO_PORT W19: PWORD Position       */
#define GPIO_PORT_W19_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W19_PWORD_Pos)                 /*!< GPIO_PORT W19: PWORD Mask           */

// --------------------------------------  GPIO_PORT_W20  -----------------------------------------
#define GPIO_PORT_W20_PWORD_Pos                               0                                                         /*!< GPIO_PORT W20: PWORD Position       */
#define GPIO_PORT_W20_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W20_PWORD_Pos)                 /*!< GPIO_PORT W20: PWORD Mask           */

// --------------------------------------  GPIO_PORT_W21  -----------------------------------------
#define GPIO_PORT_W21_PWORD_Pos                               0                                                         /*!< GPIO_PORT W21: PWORD Position       */
#define GPIO_PORT_W21_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W21_PWORD_Pos)                 /*!< GPIO_PORT W21: PWORD Mask           */

// --------------------------------------  GPIO_PORT_W22  -----------------------------------------
#define GPIO_PORT_W22_PWORD_Pos                               0                                                         /*!< GPIO_PORT W22: PWORD Position       */
#define GPIO_PORT_W22_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W22_PWORD_Pos)                 /*!< GPIO_PORT W22: PWORD Mask           */

// --------------------------------------  GPIO_PORT_W23  -----------------------------------------
#define GPIO_PORT_W23_PWORD_Pos                               0                                                         /*!< GPIO_PORT W23: PWORD Position       */
#define GPIO_PORT_W23_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W23_PWORD_Pos)                 /*!< GPIO_PORT W23: PWORD Mask           */

// --------------------------------------  GPIO_PORT_W24  -----------------------------------------
#define GPIO_PORT_W24_PWORD_Pos                               0                                                         /*!< GPIO_PORT W24: PWORD Position       */
#define GPIO_PORT_W24_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W24_PWORD_Pos)                 /*!< GPIO_PORT W24: PWORD Mask           */

// --------------------------------------  GPIO_PORT_W25  -----------------------------------------
#define GPIO_PORT_W25_PWORD_Pos                               0                                                         /*!< GPIO_PORT W25: PWORD Position       */
#define GPIO_PORT_W25_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W25_PWORD_Pos)                 /*!< GPIO_PORT W25: PWORD Mask           */

// --------------------------------------  GPIO_PORT_W26  -----------------------------------------
#define GPIO_PORT_W26_PWORD_Pos                               0                                                         /*!< GPIO_PORT W26: PWORD Position       */
#define GPIO_PORT_W26_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W26_PWORD_Pos)                 /*!< GPIO_PORT W26: PWORD Mask           */

// --------------------------------------  GPIO_PORT_W27  -----------------------------------------
#define GPIO_PORT_W27_PWORD_Pos                               0                                                         /*!< GPIO_PORT W27: PWORD Position       */
#define GPIO_PORT_W27_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W27_PWORD_Pos)                 /*!< GPIO_PORT W27: PWORD Mask           */

// --------------------------------------  GPIO_PORT_W28  -----------------------------------------
#define GPIO_PORT_W28_PWORD_Pos                               0                                                         /*!< GPIO_PORT W28: PWORD Position       */
#define GPIO_PORT_W28_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W28_PWORD_Pos)                 /*!< GPIO_PORT W28: PWORD Mask           */

// --------------------------------------  GPIO_PORT_W29  -----------------------------------------
#define GPIO_PORT_W29_PWORD_Pos                               0                                                         /*!< GPIO_PORT W29: PWORD Position       */
#define GPIO_PORT_W29_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W29_PWORD_Pos)                 /*!< GPIO_PORT W29: PWORD Mask           */

// --------------------------------------  GPIO_PORT_W30  -----------------------------------------
#define GPIO_PORT_W30_PWORD_Pos                               0                                                         /*!< GPIO_PORT W30: PWORD Position       */
#define GPIO_PORT_W30_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W30_PWORD_Pos)                 /*!< GPIO_PORT W30: PWORD Mask           */

// --------------------------------------  GPIO_PORT_W31  -----------------------------------------
#define GPIO_PORT_W31_PWORD_Pos                               0                                                         /*!< GPIO_PORT W31: PWORD Position       */
#define GPIO_PORT_W31_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W31_PWORD_Pos)                 /*!< GPIO_PORT W31: PWORD Mask           */

// --------------------------------------  GPIO_PORT_W32  -----------------------------------------
#define GPIO_PORT_W32_PWORD_Pos                               0                                                         /*!< GPIO_PORT W32: PWORD Position       */
#define GPIO_PORT_W32_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W32_PWORD_Pos)                 /*!< GPIO_PORT W32: PWORD Mask           */

// --------------------------------------  GPIO_PORT_W33  -----------------------------------------
#define GPIO_PORT_W33_PWORD_Pos                               0                                                         /*!< GPIO_PORT W33: PWORD Position       */
#define GPIO_PORT_W33_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W33_PWORD_Pos)                 /*!< GPIO_PORT W33: PWORD Mask           */

// --------------------------------------  GPIO_PORT_W34  -----------------------------------------
#define GPIO_PORT_W34_PWORD_Pos                               0                                                         /*!< GPIO_PORT W34: PWORD Position       */
#define GPIO_PORT_W34_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W34_PWORD_Pos)                 /*!< GPIO_PORT W34: PWORD Mask           */

// --------------------------------------  GPIO_PORT_W35  -----------------------------------------
#define GPIO_PORT_W35_PWORD_Pos                               0                                                         /*!< GPIO_PORT W35: PWORD Position       */
#define GPIO_PORT_W35_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W35_PWORD_Pos)                 /*!< GPIO_PORT W35: PWORD Mask           */

// --------------------------------------  GPIO_PORT_W36  -----------------------------------------
#define GPIO_PORT_W36_PWORD_Pos                               0                                                         /*!< GPIO_PORT W36: PWORD Position       */
#define GPIO_PORT_W36_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W36_PWORD_Pos)                 /*!< GPIO_PORT W36: PWORD Mask           */

// --------------------------------------  GPIO_PORT_W37  -----------------------------------------
#define GPIO_PORT_W37_PWORD_Pos                               0                                                         /*!< GPIO_PORT W37: PWORD Position       */
#define GPIO_PORT_W37_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W37_PWORD_Pos)                 /*!< GPIO_PORT W37: PWORD Mask           */

// --------------------------------------  GPIO_PORT_W38  -----------------------------------------
#define GPIO_PORT_W38_PWORD_Pos                               0                                                         /*!< GPIO_PORT W38: PWORD Position       */
#define GPIO_PORT_W38_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W38_PWORD_Pos)                 /*!< GPIO_PORT W38: PWORD Mask           */

// --------------------------------------  GPIO_PORT_W39  -----------------------------------------
#define GPIO_PORT_W39_PWORD_Pos                               0                                                         /*!< GPIO_PORT W39: PWORD Position       */
#define GPIO_PORT_W39_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W39_PWORD_Pos)                 /*!< GPIO_PORT W39: PWORD Mask           */

// --------------------------------------  GPIO_PORT_W40  -----------------------------------------
#define GPIO_PORT_W40_PWORD_Pos                               0                                                         /*!< GPIO_PORT W40: PWORD Position       */
#define GPIO_PORT_W40_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W40_PWORD_Pos)                 /*!< GPIO_PORT W40: PWORD Mask           */

// --------------------------------------  GPIO_PORT_W41  -----------------------------------------
#define GPIO_PORT_W41_PWORD_Pos                               0                                                         /*!< GPIO_PORT W41: PWORD Position       */
#define GPIO_PORT_W41_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W41_PWORD_Pos)                 /*!< GPIO_PORT W41: PWORD Mask           */

// --------------------------------------  GPIO_PORT_W42  -----------------------------------------
#define GPIO_PORT_W42_PWORD_Pos                               0                                                         /*!< GPIO_PORT W42: PWORD Position       */
#define GPIO_PORT_W42_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W42_PWORD_Pos)                 /*!< GPIO_PORT W42: PWORD Mask           */

// --------------------------------------  GPIO_PORT_W43  -----------------------------------------
#define GPIO_PORT_W43_PWORD_Pos                               0                                                         /*!< GPIO_PORT W43: PWORD Position       */
#define GPIO_PORT_W43_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W43_PWORD_Pos)                 /*!< GPIO_PORT W43: PWORD Mask           */

// --------------------------------------  GPIO_PORT_W44  -----------------------------------------
#define GPIO_PORT_W44_PWORD_Pos                               0                                                         /*!< GPIO_PORT W44: PWORD Position       */
#define GPIO_PORT_W44_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W44_PWORD_Pos)                 /*!< GPIO_PORT W44: PWORD Mask           */

// --------------------------------------  GPIO_PORT_W45  -----------------------------------------
#define GPIO_PORT_W45_PWORD_Pos                               0                                                         /*!< GPIO_PORT W45: PWORD Position       */
#define GPIO_PORT_W45_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W45_PWORD_Pos)                 /*!< GPIO_PORT W45: PWORD Mask           */

// --------------------------------------  GPIO_PORT_W46  -----------------------------------------
#define GPIO_PORT_W46_PWORD_Pos                               0                                                         /*!< GPIO_PORT W46: PWORD Position       */
#define GPIO_PORT_W46_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W46_PWORD_Pos)                 /*!< GPIO_PORT W46: PWORD Mask           */

// --------------------------------------  GPIO_PORT_W47  -----------------------------------------
#define GPIO_PORT_W47_PWORD_Pos                               0                                                         /*!< GPIO_PORT W47: PWORD Position       */
#define GPIO_PORT_W47_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W47_PWORD_Pos)                 /*!< GPIO_PORT W47: PWORD Mask           */

// --------------------------------------  GPIO_PORT_W48  -----------------------------------------
#define GPIO_PORT_W48_PWORD_Pos                               0                                                         /*!< GPIO_PORT W48: PWORD Position       */
#define GPIO_PORT_W48_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W48_PWORD_Pos)                 /*!< GPIO_PORT W48: PWORD Mask           */

// --------------------------------------  GPIO_PORT_W49  -----------------------------------------
#define GPIO_PORT_W49_PWORD_Pos                               0                                                         /*!< GPIO_PORT W49: PWORD Position       */
#define GPIO_PORT_W49_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W49_PWORD_Pos)                 /*!< GPIO_PORT W49: PWORD Mask           */

// --------------------------------------  GPIO_PORT_W50  -----------------------------------------
#define GPIO_PORT_W50_PWORD_Pos                               0                                                         /*!< GPIO_PORT W50: PWORD Position       */
#define GPIO_PORT_W50_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W50_PWORD_Pos)                 /*!< GPIO_PORT W50: PWORD Mask           */

// --------------------------------------  GPIO_PORT_W51  -----------------------------------------
#define GPIO_PORT_W51_PWORD_Pos                               0                                                         /*!< GPIO_PORT W51: PWORD Position       */
#define GPIO_PORT_W51_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W51_PWORD_Pos)                 /*!< GPIO_PORT W51: PWORD Mask           */

// --------------------------------------  GPIO_PORT_W52  -----------------------------------------
#define GPIO_PORT_W52_PWORD_Pos                               0                                                         /*!< GPIO_PORT W52: PWORD Position       */
#define GPIO_PORT_W52_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W52_PWORD_Pos)                 /*!< GPIO_PORT W52: PWORD Mask           */

// --------------------------------------  GPIO_PORT_W53  -----------------------------------------
#define GPIO_PORT_W53_PWORD_Pos                               0                                                         /*!< GPIO_PORT W53: PWORD Position       */
#define GPIO_PORT_W53_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W53_PWORD_Pos)                 /*!< GPIO_PORT W53: PWORD Mask           */

// --------------------------------------  GPIO_PORT_W54  -----------------------------------------
#define GPIO_PORT_W54_PWORD_Pos                               0                                                         /*!< GPIO_PORT W54: PWORD Position       */
#define GPIO_PORT_W54_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W54_PWORD_Pos)                 /*!< GPIO_PORT W54: PWORD Mask           */

// --------------------------------------  GPIO_PORT_W55  -----------------------------------------
#define GPIO_PORT_W55_PWORD_Pos                               0                                                         /*!< GPIO_PORT W55: PWORD Position       */
#define GPIO_PORT_W55_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W55_PWORD_Pos)                 /*!< GPIO_PORT W55: PWORD Mask           */

// --------------------------------------  GPIO_PORT_W56  -----------------------------------------
#define GPIO_PORT_W56_PWORD_Pos                               0                                                         /*!< GPIO_PORT W56: PWORD Position       */
#define GPIO_PORT_W56_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W56_PWORD_Pos)                 /*!< GPIO_PORT W56: PWORD Mask           */

// --------------------------------------  GPIO_PORT_W57  -----------------------------------------
#define GPIO_PORT_W57_PWORD_Pos                               0                                                         /*!< GPIO_PORT W57: PWORD Position       */
#define GPIO_PORT_W57_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W57_PWORD_Pos)                 /*!< GPIO_PORT W57: PWORD Mask           */

// --------------------------------------  GPIO_PORT_W58  -----------------------------------------
#define GPIO_PORT_W58_PWORD_Pos                               0                                                         /*!< GPIO_PORT W58: PWORD Position       */
#define GPIO_PORT_W58_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W58_PWORD_Pos)                 /*!< GPIO_PORT W58: PWORD Mask           */

// --------------------------------------  GPIO_PORT_W59  -----------------------------------------
#define GPIO_PORT_W59_PWORD_Pos                               0                                                         /*!< GPIO_PORT W59: PWORD Position       */
#define GPIO_PORT_W59_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W59_PWORD_Pos)                 /*!< GPIO_PORT W59: PWORD Mask           */

// --------------------------------------  GPIO_PORT_W60  -----------------------------------------
#define GPIO_PORT_W60_PWORD_Pos                               0                                                         /*!< GPIO_PORT W60: PWORD Position       */
#define GPIO_PORT_W60_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W60_PWORD_Pos)                 /*!< GPIO_PORT W60: PWORD Mask           */

// --------------------------------------  GPIO_PORT_W61  -----------------------------------------
#define GPIO_PORT_W61_PWORD_Pos                               0                                                         /*!< GPIO_PORT W61: PWORD Position       */
#define GPIO_PORT_W61_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W61_PWORD_Pos)                 /*!< GPIO_PORT W61: PWORD Mask           */

// --------------------------------------  GPIO_PORT_W62  -----------------------------------------
#define GPIO_PORT_W62_PWORD_Pos                               0                                                         /*!< GPIO_PORT W62: PWORD Position       */
#define GPIO_PORT_W62_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W62_PWORD_Pos)                 /*!< GPIO_PORT W62: PWORD Mask           */

// --------------------------------------  GPIO_PORT_W63  -----------------------------------------
#define GPIO_PORT_W63_PWORD_Pos                               0                                                         /*!< GPIO_PORT W63: PWORD Position       */
#define GPIO_PORT_W63_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W63_PWORD_Pos)                 /*!< GPIO_PORT W63: PWORD Mask           */

// --------------------------------------  GPIO_PORT_W64  -----------------------------------------
#define GPIO_PORT_W64_PWORD_Pos                               0                                                         /*!< GPIO_PORT W64: PWORD Position       */
#define GPIO_PORT_W64_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W64_PWORD_Pos)                 /*!< GPIO_PORT W64: PWORD Mask           */

// --------------------------------------  GPIO_PORT_W65  -----------------------------------------
#define GPIO_PORT_W65_PWORD_Pos                               0                                                         /*!< GPIO_PORT W65: PWORD Position       */
#define GPIO_PORT_W65_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W65_PWORD_Pos)                 /*!< GPIO_PORT W65: PWORD Mask           */

// --------------------------------------  GPIO_PORT_W66  -----------------------------------------
#define GPIO_PORT_W66_PWORD_Pos                               0                                                         /*!< GPIO_PORT W66: PWORD Position       */
#define GPIO_PORT_W66_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W66_PWORD_Pos)                 /*!< GPIO_PORT W66: PWORD Mask           */

// --------------------------------------  GPIO_PORT_W67  -----------------------------------------
#define GPIO_PORT_W67_PWORD_Pos                               0                                                         /*!< GPIO_PORT W67: PWORD Position       */
#define GPIO_PORT_W67_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W67_PWORD_Pos)                 /*!< GPIO_PORT W67: PWORD Mask           */

// --------------------------------------  GPIO_PORT_W68  -----------------------------------------
#define GPIO_PORT_W68_PWORD_Pos                               0                                                         /*!< GPIO_PORT W68: PWORD Position       */
#define GPIO_PORT_W68_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W68_PWORD_Pos)                 /*!< GPIO_PORT W68: PWORD Mask           */

// --------------------------------------  GPIO_PORT_W69  -----------------------------------------
#define GPIO_PORT_W69_PWORD_Pos                               0                                                         /*!< GPIO_PORT W69: PWORD Position       */
#define GPIO_PORT_W69_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W69_PWORD_Pos)                 /*!< GPIO_PORT W69: PWORD Mask           */

// --------------------------------------  GPIO_PORT_W70  -----------------------------------------
#define GPIO_PORT_W70_PWORD_Pos                               0                                                         /*!< GPIO_PORT W70: PWORD Position       */
#define GPIO_PORT_W70_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W70_PWORD_Pos)                 /*!< GPIO_PORT W70: PWORD Mask           */

// --------------------------------------  GPIO_PORT_W71  -----------------------------------------
#define GPIO_PORT_W71_PWORD_Pos                               0                                                         /*!< GPIO_PORT W71: PWORD Position       */
#define GPIO_PORT_W71_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W71_PWORD_Pos)                 /*!< GPIO_PORT W71: PWORD Mask           */

// --------------------------------------  GPIO_PORT_W72  -----------------------------------------
#define GPIO_PORT_W72_PWORD_Pos                               0                                                         /*!< GPIO_PORT W72: PWORD Position       */
#define GPIO_PORT_W72_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W72_PWORD_Pos)                 /*!< GPIO_PORT W72: PWORD Mask           */

// --------------------------------------  GPIO_PORT_W73  -----------------------------------------
#define GPIO_PORT_W73_PWORD_Pos                               0                                                         /*!< GPIO_PORT W73: PWORD Position       */
#define GPIO_PORT_W73_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W73_PWORD_Pos)                 /*!< GPIO_PORT W73: PWORD Mask           */

// --------------------------------------  GPIO_PORT_W74  -----------------------------------------
#define GPIO_PORT_W74_PWORD_Pos                               0                                                         /*!< GPIO_PORT W74: PWORD Position       */
#define GPIO_PORT_W74_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W74_PWORD_Pos)                 /*!< GPIO_PORT W74: PWORD Mask           */

// --------------------------------------  GPIO_PORT_W75  -----------------------------------------
#define GPIO_PORT_W75_PWORD_Pos                               0                                                         /*!< GPIO_PORT W75: PWORD Position       */
#define GPIO_PORT_W75_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W75_PWORD_Pos)                 /*!< GPIO_PORT W75: PWORD Mask           */

// --------------------------------------  GPIO_PORT_W76  -----------------------------------------
#define GPIO_PORT_W76_PWORD_Pos                               0                                                         /*!< GPIO_PORT W76: PWORD Position       */
#define GPIO_PORT_W76_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W76_PWORD_Pos)                 /*!< GPIO_PORT W76: PWORD Mask           */

// --------------------------------------  GPIO_PORT_W77  -----------------------------------------
#define GPIO_PORT_W77_PWORD_Pos                               0                                                         /*!< GPIO_PORT W77: PWORD Position       */
#define GPIO_PORT_W77_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W77_PWORD_Pos)                 /*!< GPIO_PORT W77: PWORD Mask           */

// --------------------------------------  GPIO_PORT_W78  -----------------------------------------
#define GPIO_PORT_W78_PWORD_Pos                               0                                                         /*!< GPIO_PORT W78: PWORD Position       */
#define GPIO_PORT_W78_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W78_PWORD_Pos)                 /*!< GPIO_PORT W78: PWORD Mask           */

// --------------------------------------  GPIO_PORT_W79  -----------------------------------------
#define GPIO_PORT_W79_PWORD_Pos                               0                                                         /*!< GPIO_PORT W79: PWORD Position       */
#define GPIO_PORT_W79_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W79_PWORD_Pos)                 /*!< GPIO_PORT W79: PWORD Mask           */

// --------------------------------------  GPIO_PORT_W80  -----------------------------------------
#define GPIO_PORT_W80_PWORD_Pos                               0                                                         /*!< GPIO_PORT W80: PWORD Position       */
#define GPIO_PORT_W80_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W80_PWORD_Pos)                 /*!< GPIO_PORT W80: PWORD Mask           */

// --------------------------------------  GPIO_PORT_W81  -----------------------------------------
#define GPIO_PORT_W81_PWORD_Pos                               0                                                         /*!< GPIO_PORT W81: PWORD Position       */
#define GPIO_PORT_W81_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W81_PWORD_Pos)                 /*!< GPIO_PORT W81: PWORD Mask           */

// --------------------------------------  GPIO_PORT_W82  -----------------------------------------
#define GPIO_PORT_W82_PWORD_Pos                               0                                                         /*!< GPIO_PORT W82: PWORD Position       */
#define GPIO_PORT_W82_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W82_PWORD_Pos)                 /*!< GPIO_PORT W82: PWORD Mask           */

// --------------------------------------  GPIO_PORT_W83  -----------------------------------------
#define GPIO_PORT_W83_PWORD_Pos                               0                                                         /*!< GPIO_PORT W83: PWORD Position       */
#define GPIO_PORT_W83_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W83_PWORD_Pos)                 /*!< GPIO_PORT W83: PWORD Mask           */

// --------------------------------------  GPIO_PORT_W84  -----------------------------------------
#define GPIO_PORT_W84_PWORD_Pos                               0                                                         /*!< GPIO_PORT W84: PWORD Position       */
#define GPIO_PORT_W84_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W84_PWORD_Pos)                 /*!< GPIO_PORT W84: PWORD Mask           */

// --------------------------------------  GPIO_PORT_W85  -----------------------------------------
#define GPIO_PORT_W85_PWORD_Pos                               0                                                         /*!< GPIO_PORT W85: PWORD Position       */
#define GPIO_PORT_W85_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W85_PWORD_Pos)                 /*!< GPIO_PORT W85: PWORD Mask           */

// --------------------------------------  GPIO_PORT_W86  -----------------------------------------
#define GPIO_PORT_W86_PWORD_Pos                               0                                                         /*!< GPIO_PORT W86: PWORD Position       */
#define GPIO_PORT_W86_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W86_PWORD_Pos)                 /*!< GPIO_PORT W86: PWORD Mask           */

// --------------------------------------  GPIO_PORT_W87  -----------------------------------------
#define GPIO_PORT_W87_PWORD_Pos                               0                                                         /*!< GPIO_PORT W87: PWORD Position       */
#define GPIO_PORT_W87_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W87_PWORD_Pos)                 /*!< GPIO_PORT W87: PWORD Mask           */

// --------------------------------------  GPIO_PORT_W88  -----------------------------------------
#define GPIO_PORT_W88_PWORD_Pos                               0                                                         /*!< GPIO_PORT W88: PWORD Position       */
#define GPIO_PORT_W88_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W88_PWORD_Pos)                 /*!< GPIO_PORT W88: PWORD Mask           */

// --------------------------------------  GPIO_PORT_W89  -----------------------------------------
#define GPIO_PORT_W89_PWORD_Pos                               0                                                         /*!< GPIO_PORT W89: PWORD Position       */
#define GPIO_PORT_W89_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W89_PWORD_Pos)                 /*!< GPIO_PORT W89: PWORD Mask           */

// --------------------------------------  GPIO_PORT_W90  -----------------------------------------
#define GPIO_PORT_W90_PWORD_Pos                               0                                                         /*!< GPIO_PORT W90: PWORD Position       */
#define GPIO_PORT_W90_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W90_PWORD_Pos)                 /*!< GPIO_PORT W90: PWORD Mask           */

// --------------------------------------  GPIO_PORT_W91  -----------------------------------------
#define GPIO_PORT_W91_PWORD_Pos                               0                                                         /*!< GPIO_PORT W91: PWORD Position       */
#define GPIO_PORT_W91_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W91_PWORD_Pos)                 /*!< GPIO_PORT W91: PWORD Mask           */

// --------------------------------------  GPIO_PORT_W92  -----------------------------------------
#define GPIO_PORT_W92_PWORD_Pos                               0                                                         /*!< GPIO_PORT W92: PWORD Position       */
#define GPIO_PORT_W92_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W92_PWORD_Pos)                 /*!< GPIO_PORT W92: PWORD Mask           */

// --------------------------------------  GPIO_PORT_W93  -----------------------------------------
#define GPIO_PORT_W93_PWORD_Pos                               0                                                         /*!< GPIO_PORT W93: PWORD Position       */
#define GPIO_PORT_W93_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W93_PWORD_Pos)                 /*!< GPIO_PORT W93: PWORD Mask           */

// --------------------------------------  GPIO_PORT_W94  -----------------------------------------
#define GPIO_PORT_W94_PWORD_Pos                               0                                                         /*!< GPIO_PORT W94: PWORD Position       */
#define GPIO_PORT_W94_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W94_PWORD_Pos)                 /*!< GPIO_PORT W94: PWORD Mask           */

// --------------------------------------  GPIO_PORT_W95  -----------------------------------------
#define GPIO_PORT_W95_PWORD_Pos                               0                                                         /*!< GPIO_PORT W95: PWORD Position       */
#define GPIO_PORT_W95_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W95_PWORD_Pos)                 /*!< GPIO_PORT W95: PWORD Mask           */

// --------------------------------------  GPIO_PORT_W96  -----------------------------------------
#define GPIO_PORT_W96_PWORD_Pos                               0                                                         /*!< GPIO_PORT W96: PWORD Position       */
#define GPIO_PORT_W96_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W96_PWORD_Pos)                 /*!< GPIO_PORT W96: PWORD Mask           */

// --------------------------------------  GPIO_PORT_W97  -----------------------------------------
#define GPIO_PORT_W97_PWORD_Pos                               0                                                         /*!< GPIO_PORT W97: PWORD Position       */
#define GPIO_PORT_W97_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W97_PWORD_Pos)                 /*!< GPIO_PORT W97: PWORD Mask           */

// --------------------------------------  GPIO_PORT_W98  -----------------------------------------
#define GPIO_PORT_W98_PWORD_Pos                               0                                                         /*!< GPIO_PORT W98: PWORD Position       */
#define GPIO_PORT_W98_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W98_PWORD_Pos)                 /*!< GPIO_PORT W98: PWORD Mask           */

// --------------------------------------  GPIO_PORT_W99  -----------------------------------------
#define GPIO_PORT_W99_PWORD_Pos                               0                                                         /*!< GPIO_PORT W99: PWORD Position       */
#define GPIO_PORT_W99_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W99_PWORD_Pos)                 /*!< GPIO_PORT W99: PWORD Mask           */

// -------------------------------------  GPIO_PORT_W100  -----------------------------------------
#define GPIO_PORT_W100_PWORD_Pos                              0                                                         /*!< GPIO_PORT W100: PWORD Position      */
#define GPIO_PORT_W100_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W100_PWORD_Pos)                /*!< GPIO_PORT W100: PWORD Mask          */

// -------------------------------------  GPIO_PORT_W101  -----------------------------------------
#define GPIO_PORT_W101_PWORD_Pos                              0                                                         /*!< GPIO_PORT W101: PWORD Position      */
#define GPIO_PORT_W101_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W101_PWORD_Pos)                /*!< GPIO_PORT W101: PWORD Mask          */

// -------------------------------------  GPIO_PORT_W102  -----------------------------------------
#define GPIO_PORT_W102_PWORD_Pos                              0                                                         /*!< GPIO_PORT W102: PWORD Position      */
#define GPIO_PORT_W102_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W102_PWORD_Pos)                /*!< GPIO_PORT W102: PWORD Mask          */

// -------------------------------------  GPIO_PORT_W103  -----------------------------------------
#define GPIO_PORT_W103_PWORD_Pos                              0                                                         /*!< GPIO_PORT W103: PWORD Position      */
#define GPIO_PORT_W103_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W103_PWORD_Pos)                /*!< GPIO_PORT W103: PWORD Mask          */

// -------------------------------------  GPIO_PORT_W104  -----------------------------------------
#define GPIO_PORT_W104_PWORD_Pos                              0                                                         /*!< GPIO_PORT W104: PWORD Position      */
#define GPIO_PORT_W104_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W104_PWORD_Pos)                /*!< GPIO_PORT W104: PWORD Mask          */

// -------------------------------------  GPIO_PORT_W105  -----------------------------------------
#define GPIO_PORT_W105_PWORD_Pos                              0                                                         /*!< GPIO_PORT W105: PWORD Position      */
#define GPIO_PORT_W105_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W105_PWORD_Pos)                /*!< GPIO_PORT W105: PWORD Mask          */

// -------------------------------------  GPIO_PORT_W106  -----------------------------------------
#define GPIO_PORT_W106_PWORD_Pos                              0                                                         /*!< GPIO_PORT W106: PWORD Position      */
#define GPIO_PORT_W106_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W106_PWORD_Pos)                /*!< GPIO_PORT W106: PWORD Mask          */

// -------------------------------------  GPIO_PORT_W107  -----------------------------------------
#define GPIO_PORT_W107_PWORD_Pos                              0                                                         /*!< GPIO_PORT W107: PWORD Position      */
#define GPIO_PORT_W107_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W107_PWORD_Pos)                /*!< GPIO_PORT W107: PWORD Mask          */

// -------------------------------------  GPIO_PORT_W108  -----------------------------------------
#define GPIO_PORT_W108_PWORD_Pos                              0                                                         /*!< GPIO_PORT W108: PWORD Position      */
#define GPIO_PORT_W108_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W108_PWORD_Pos)                /*!< GPIO_PORT W108: PWORD Mask          */

// -------------------------------------  GPIO_PORT_W109  -----------------------------------------
#define GPIO_PORT_W109_PWORD_Pos                              0                                                         /*!< GPIO_PORT W109: PWORD Position      */
#define GPIO_PORT_W109_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W109_PWORD_Pos)                /*!< GPIO_PORT W109: PWORD Mask          */

// -------------------------------------  GPIO_PORT_W110  -----------------------------------------
#define GPIO_PORT_W110_PWORD_Pos                              0                                                         /*!< GPIO_PORT W110: PWORD Position      */
#define GPIO_PORT_W110_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W110_PWORD_Pos)                /*!< GPIO_PORT W110: PWORD Mask          */

// -------------------------------------  GPIO_PORT_W111  -----------------------------------------
#define GPIO_PORT_W111_PWORD_Pos                              0                                                         /*!< GPIO_PORT W111: PWORD Position      */
#define GPIO_PORT_W111_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W111_PWORD_Pos)                /*!< GPIO_PORT W111: PWORD Mask          */

// -------------------------------------  GPIO_PORT_W112  -----------------------------------------
#define GPIO_PORT_W112_PWORD_Pos                              0                                                         /*!< GPIO_PORT W112: PWORD Position      */
#define GPIO_PORT_W112_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W112_PWORD_Pos)                /*!< GPIO_PORT W112: PWORD Mask          */

// -------------------------------------  GPIO_PORT_W113  -----------------------------------------
#define GPIO_PORT_W113_PWORD_Pos                              0                                                         /*!< GPIO_PORT W113: PWORD Position      */
#define GPIO_PORT_W113_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W113_PWORD_Pos)                /*!< GPIO_PORT W113: PWORD Mask          */

// -------------------------------------  GPIO_PORT_W114  -----------------------------------------
#define GPIO_PORT_W114_PWORD_Pos                              0                                                         /*!< GPIO_PORT W114: PWORD Position      */
#define GPIO_PORT_W114_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W114_PWORD_Pos)                /*!< GPIO_PORT W114: PWORD Mask          */

// -------------------------------------  GPIO_PORT_W115  -----------------------------------------
#define GPIO_PORT_W115_PWORD_Pos                              0                                                         /*!< GPIO_PORT W115: PWORD Position      */
#define GPIO_PORT_W115_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W115_PWORD_Pos)                /*!< GPIO_PORT W115: PWORD Mask          */

// -------------------------------------  GPIO_PORT_W116  -----------------------------------------
#define GPIO_PORT_W116_PWORD_Pos                              0                                                         /*!< GPIO_PORT W116: PWORD Position      */
#define GPIO_PORT_W116_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W116_PWORD_Pos)                /*!< GPIO_PORT W116: PWORD Mask          */

// -------------------------------------  GPIO_PORT_W117  -----------------------------------------
#define GPIO_PORT_W117_PWORD_Pos                              0                                                         /*!< GPIO_PORT W117: PWORD Position      */
#define GPIO_PORT_W117_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W117_PWORD_Pos)                /*!< GPIO_PORT W117: PWORD Mask          */

// -------------------------------------  GPIO_PORT_W118  -----------------------------------------
#define GPIO_PORT_W118_PWORD_Pos                              0                                                         /*!< GPIO_PORT W118: PWORD Position      */
#define GPIO_PORT_W118_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W118_PWORD_Pos)                /*!< GPIO_PORT W118: PWORD Mask          */

// -------------------------------------  GPIO_PORT_W119  -----------------------------------------
#define GPIO_PORT_W119_PWORD_Pos                              0                                                         /*!< GPIO_PORT W119: PWORD Position      */
#define GPIO_PORT_W119_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W119_PWORD_Pos)                /*!< GPIO_PORT W119: PWORD Mask          */

// -------------------------------------  GPIO_PORT_W120  -----------------------------------------
#define GPIO_PORT_W120_PWORD_Pos                              0                                                         /*!< GPIO_PORT W120: PWORD Position      */
#define GPIO_PORT_W120_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W120_PWORD_Pos)                /*!< GPIO_PORT W120: PWORD Mask          */

// -------------------------------------  GPIO_PORT_W121  -----------------------------------------
#define GPIO_PORT_W121_PWORD_Pos                              0                                                         /*!< GPIO_PORT W121: PWORD Position      */
#define GPIO_PORT_W121_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W121_PWORD_Pos)                /*!< GPIO_PORT W121: PWORD Mask          */

// -------------------------------------  GPIO_PORT_W122  -----------------------------------------
#define GPIO_PORT_W122_PWORD_Pos                              0                                                         /*!< GPIO_PORT W122: PWORD Position      */
#define GPIO_PORT_W122_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W122_PWORD_Pos)                /*!< GPIO_PORT W122: PWORD Mask          */

// -------------------------------------  GPIO_PORT_W123  -----------------------------------------
#define GPIO_PORT_W123_PWORD_Pos                              0                                                         /*!< GPIO_PORT W123: PWORD Position      */
#define GPIO_PORT_W123_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W123_PWORD_Pos)                /*!< GPIO_PORT W123: PWORD Mask          */

// -------------------------------------  GPIO_PORT_W124  -----------------------------------------
#define GPIO_PORT_W124_PWORD_Pos                              0                                                         /*!< GPIO_PORT W124: PWORD Position      */
#define GPIO_PORT_W124_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W124_PWORD_Pos)                /*!< GPIO_PORT W124: PWORD Mask          */

// -------------------------------------  GPIO_PORT_W125  -----------------------------------------
#define GPIO_PORT_W125_PWORD_Pos                              0                                                         /*!< GPIO_PORT W125: PWORD Position      */
#define GPIO_PORT_W125_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W125_PWORD_Pos)                /*!< GPIO_PORT W125: PWORD Mask          */

// -------------------------------------  GPIO_PORT_W126  -----------------------------------------
#define GPIO_PORT_W126_PWORD_Pos                              0                                                         /*!< GPIO_PORT W126: PWORD Position      */
#define GPIO_PORT_W126_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W126_PWORD_Pos)                /*!< GPIO_PORT W126: PWORD Mask          */

// -------------------------------------  GPIO_PORT_W127  -----------------------------------------
#define GPIO_PORT_W127_PWORD_Pos                              0                                                         /*!< GPIO_PORT W127: PWORD Position      */
#define GPIO_PORT_W127_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W127_PWORD_Pos)                /*!< GPIO_PORT W127: PWORD Mask          */

// -------------------------------------  GPIO_PORT_W128  -----------------------------------------
#define GPIO_PORT_W128_PWORD_Pos                              0                                                         /*!< GPIO_PORT W128: PWORD Position      */
#define GPIO_PORT_W128_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W128_PWORD_Pos)                /*!< GPIO_PORT W128: PWORD Mask          */

// -------------------------------------  GPIO_PORT_W129  -----------------------------------------
#define GPIO_PORT_W129_PWORD_Pos                              0                                                         /*!< GPIO_PORT W129: PWORD Position      */
#define GPIO_PORT_W129_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W129_PWORD_Pos)                /*!< GPIO_PORT W129: PWORD Mask          */

// -------------------------------------  GPIO_PORT_W130  -----------------------------------------
#define GPIO_PORT_W130_PWORD_Pos                              0                                                         /*!< GPIO_PORT W130: PWORD Position      */
#define GPIO_PORT_W130_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W130_PWORD_Pos)                /*!< GPIO_PORT W130: PWORD Mask          */

// -------------------------------------  GPIO_PORT_W131  -----------------------------------------
#define GPIO_PORT_W131_PWORD_Pos                              0                                                         /*!< GPIO_PORT W131: PWORD Position      */
#define GPIO_PORT_W131_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W131_PWORD_Pos)                /*!< GPIO_PORT W131: PWORD Mask          */

// -------------------------------------  GPIO_PORT_W132  -----------------------------------------
#define GPIO_PORT_W132_PWORD_Pos                              0                                                         /*!< GPIO_PORT W132: PWORD Position      */
#define GPIO_PORT_W132_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W132_PWORD_Pos)                /*!< GPIO_PORT W132: PWORD Mask          */

// -------------------------------------  GPIO_PORT_W133  -----------------------------------------
#define GPIO_PORT_W133_PWORD_Pos                              0                                                         /*!< GPIO_PORT W133: PWORD Position      */
#define GPIO_PORT_W133_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W133_PWORD_Pos)                /*!< GPIO_PORT W133: PWORD Mask          */

// -------------------------------------  GPIO_PORT_W134  -----------------------------------------
#define GPIO_PORT_W134_PWORD_Pos                              0                                                         /*!< GPIO_PORT W134: PWORD Position      */
#define GPIO_PORT_W134_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W134_PWORD_Pos)                /*!< GPIO_PORT W134: PWORD Mask          */

// -------------------------------------  GPIO_PORT_W135  -----------------------------------------
#define GPIO_PORT_W135_PWORD_Pos                              0                                                         /*!< GPIO_PORT W135: PWORD Position      */
#define GPIO_PORT_W135_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W135_PWORD_Pos)                /*!< GPIO_PORT W135: PWORD Mask          */

// -------------------------------------  GPIO_PORT_W136  -----------------------------------------
#define GPIO_PORT_W136_PWORD_Pos                              0                                                         /*!< GPIO_PORT W136: PWORD Position      */
#define GPIO_PORT_W136_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W136_PWORD_Pos)                /*!< GPIO_PORT W136: PWORD Mask          */

// -------------------------------------  GPIO_PORT_W137  -----------------------------------------
#define GPIO_PORT_W137_PWORD_Pos                              0                                                         /*!< GPIO_PORT W137: PWORD Position      */
#define GPIO_PORT_W137_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W137_PWORD_Pos)                /*!< GPIO_PORT W137: PWORD Mask          */

// -------------------------------------  GPIO_PORT_W138  -----------------------------------------
#define GPIO_PORT_W138_PWORD_Pos                              0                                                         /*!< GPIO_PORT W138: PWORD Position      */
#define GPIO_PORT_W138_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W138_PWORD_Pos)                /*!< GPIO_PORT W138: PWORD Mask          */

// -------------------------------------  GPIO_PORT_W139  -----------------------------------------
#define GPIO_PORT_W139_PWORD_Pos                              0                                                         /*!< GPIO_PORT W139: PWORD Position      */
#define GPIO_PORT_W139_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W139_PWORD_Pos)                /*!< GPIO_PORT W139: PWORD Mask          */

// -------------------------------------  GPIO_PORT_W140  -----------------------------------------
#define GPIO_PORT_W140_PWORD_Pos                              0                                                         /*!< GPIO_PORT W140: PWORD Position      */
#define GPIO_PORT_W140_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W140_PWORD_Pos)                /*!< GPIO_PORT W140: PWORD Mask          */

// -------------------------------------  GPIO_PORT_W141  -----------------------------------------
#define GPIO_PORT_W141_PWORD_Pos                              0                                                         /*!< GPIO_PORT W141: PWORD Position      */
#define GPIO_PORT_W141_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W141_PWORD_Pos)                /*!< GPIO_PORT W141: PWORD Mask          */

// -------------------------------------  GPIO_PORT_W142  -----------------------------------------
#define GPIO_PORT_W142_PWORD_Pos                              0                                                         /*!< GPIO_PORT W142: PWORD Position      */
#define GPIO_PORT_W142_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W142_PWORD_Pos)                /*!< GPIO_PORT W142: PWORD Mask          */

// -------------------------------------  GPIO_PORT_W143  -----------------------------------------
#define GPIO_PORT_W143_PWORD_Pos                              0                                                         /*!< GPIO_PORT W143: PWORD Position      */
#define GPIO_PORT_W143_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W143_PWORD_Pos)                /*!< GPIO_PORT W143: PWORD Mask          */

// -------------------------------------  GPIO_PORT_W144  -----------------------------------------
#define GPIO_PORT_W144_PWORD_Pos                              0                                                         /*!< GPIO_PORT W144: PWORD Position      */
#define GPIO_PORT_W144_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W144_PWORD_Pos)                /*!< GPIO_PORT W144: PWORD Mask          */

// -------------------------------------  GPIO_PORT_W145  -----------------------------------------
#define GPIO_PORT_W145_PWORD_Pos                              0                                                         /*!< GPIO_PORT W145: PWORD Position      */
#define GPIO_PORT_W145_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W145_PWORD_Pos)                /*!< GPIO_PORT W145: PWORD Mask          */

// -------------------------------------  GPIO_PORT_W146  -----------------------------------------
#define GPIO_PORT_W146_PWORD_Pos                              0                                                         /*!< GPIO_PORT W146: PWORD Position      */
#define GPIO_PORT_W146_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W146_PWORD_Pos)                /*!< GPIO_PORT W146: PWORD Mask          */

// -------------------------------------  GPIO_PORT_W147  -----------------------------------------
#define GPIO_PORT_W147_PWORD_Pos                              0                                                         /*!< GPIO_PORT W147: PWORD Position      */
#define GPIO_PORT_W147_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W147_PWORD_Pos)                /*!< GPIO_PORT W147: PWORD Mask          */

// -------------------------------------  GPIO_PORT_W148  -----------------------------------------
#define GPIO_PORT_W148_PWORD_Pos                              0                                                         /*!< GPIO_PORT W148: PWORD Position      */
#define GPIO_PORT_W148_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W148_PWORD_Pos)                /*!< GPIO_PORT W148: PWORD Mask          */

// -------------------------------------  GPIO_PORT_W149  -----------------------------------------
#define GPIO_PORT_W149_PWORD_Pos                              0                                                         /*!< GPIO_PORT W149: PWORD Position      */
#define GPIO_PORT_W149_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W149_PWORD_Pos)                /*!< GPIO_PORT W149: PWORD Mask          */

// -------------------------------------  GPIO_PORT_W150  -----------------------------------------
#define GPIO_PORT_W150_PWORD_Pos                              0                                                         /*!< GPIO_PORT W150: PWORD Position      */
#define GPIO_PORT_W150_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W150_PWORD_Pos)                /*!< GPIO_PORT W150: PWORD Mask          */

// -------------------------------------  GPIO_PORT_W151  -----------------------------------------
#define GPIO_PORT_W151_PWORD_Pos                              0                                                         /*!< GPIO_PORT W151: PWORD Position      */
#define GPIO_PORT_W151_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W151_PWORD_Pos)                /*!< GPIO_PORT W151: PWORD Mask          */

// -------------------------------------  GPIO_PORT_W152  -----------------------------------------
#define GPIO_PORT_W152_PWORD_Pos                              0                                                         /*!< GPIO_PORT W152: PWORD Position      */
#define GPIO_PORT_W152_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W152_PWORD_Pos)                /*!< GPIO_PORT W152: PWORD Mask          */

// -------------------------------------  GPIO_PORT_W153  -----------------------------------------
#define GPIO_PORT_W153_PWORD_Pos                              0                                                         /*!< GPIO_PORT W153: PWORD Position      */
#define GPIO_PORT_W153_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W153_PWORD_Pos)                /*!< GPIO_PORT W153: PWORD Mask          */

// -------------------------------------  GPIO_PORT_W154  -----------------------------------------
#define GPIO_PORT_W154_PWORD_Pos                              0                                                         /*!< GPIO_PORT W154: PWORD Position      */
#define GPIO_PORT_W154_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W154_PWORD_Pos)                /*!< GPIO_PORT W154: PWORD Mask          */

// -------------------------------------  GPIO_PORT_W155  -----------------------------------------
#define GPIO_PORT_W155_PWORD_Pos                              0                                                         /*!< GPIO_PORT W155: PWORD Position      */
#define GPIO_PORT_W155_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W155_PWORD_Pos)                /*!< GPIO_PORT W155: PWORD Mask          */

// -------------------------------------  GPIO_PORT_W156  -----------------------------------------
#define GPIO_PORT_W156_PWORD_Pos                              0                                                         /*!< GPIO_PORT W156: PWORD Position      */
#define GPIO_PORT_W156_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W156_PWORD_Pos)                /*!< GPIO_PORT W156: PWORD Mask          */

// -------------------------------------  GPIO_PORT_W157  -----------------------------------------
#define GPIO_PORT_W157_PWORD_Pos                              0                                                         /*!< GPIO_PORT W157: PWORD Position      */
#define GPIO_PORT_W157_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W157_PWORD_Pos)                /*!< GPIO_PORT W157: PWORD Mask          */

// -------------------------------------  GPIO_PORT_W158  -----------------------------------------
#define GPIO_PORT_W158_PWORD_Pos                              0                                                         /*!< GPIO_PORT W158: PWORD Position      */
#define GPIO_PORT_W158_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W158_PWORD_Pos)                /*!< GPIO_PORT W158: PWORD Mask          */

// -------------------------------------  GPIO_PORT_W159  -----------------------------------------
#define GPIO_PORT_W159_PWORD_Pos                              0                                                         /*!< GPIO_PORT W159: PWORD Position      */
#define GPIO_PORT_W159_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W159_PWORD_Pos)                /*!< GPIO_PORT W159: PWORD Mask          */

// -------------------------------------  GPIO_PORT_W160  -----------------------------------------
#define GPIO_PORT_W160_PWORD_Pos                              0                                                         /*!< GPIO_PORT W160: PWORD Position      */
#define GPIO_PORT_W160_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W160_PWORD_Pos)                /*!< GPIO_PORT W160: PWORD Mask          */

// -------------------------------------  GPIO_PORT_W161  -----------------------------------------
#define GPIO_PORT_W161_PWORD_Pos                              0                                                         /*!< GPIO_PORT W161: PWORD Position      */
#define GPIO_PORT_W161_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W161_PWORD_Pos)                /*!< GPIO_PORT W161: PWORD Mask          */

// -------------------------------------  GPIO_PORT_W162  -----------------------------------------
#define GPIO_PORT_W162_PWORD_Pos                              0                                                         /*!< GPIO_PORT W162: PWORD Position      */
#define GPIO_PORT_W162_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W162_PWORD_Pos)                /*!< GPIO_PORT W162: PWORD Mask          */

// -------------------------------------  GPIO_PORT_W163  -----------------------------------------
#define GPIO_PORT_W163_PWORD_Pos                              0                                                         /*!< GPIO_PORT W163: PWORD Position      */
#define GPIO_PORT_W163_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W163_PWORD_Pos)                /*!< GPIO_PORT W163: PWORD Mask          */

// -------------------------------------  GPIO_PORT_W164  -----------------------------------------
#define GPIO_PORT_W164_PWORD_Pos                              0                                                         /*!< GPIO_PORT W164: PWORD Position      */
#define GPIO_PORT_W164_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W164_PWORD_Pos)                /*!< GPIO_PORT W164: PWORD Mask          */

// -------------------------------------  GPIO_PORT_W165  -----------------------------------------
#define GPIO_PORT_W165_PWORD_Pos                              0                                                         /*!< GPIO_PORT W165: PWORD Position      */
#define GPIO_PORT_W165_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W165_PWORD_Pos)                /*!< GPIO_PORT W165: PWORD Mask          */

// -------------------------------------  GPIO_PORT_W166  -----------------------------------------
#define GPIO_PORT_W166_PWORD_Pos                              0                                                         /*!< GPIO_PORT W166: PWORD Position      */
#define GPIO_PORT_W166_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W166_PWORD_Pos)                /*!< GPIO_PORT W166: PWORD Mask          */

// -------------------------------------  GPIO_PORT_W167  -----------------------------------------
#define GPIO_PORT_W167_PWORD_Pos                              0                                                         /*!< GPIO_PORT W167: PWORD Position      */
#define GPIO_PORT_W167_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W167_PWORD_Pos)                /*!< GPIO_PORT W167: PWORD Mask          */

// -------------------------------------  GPIO_PORT_W168  -----------------------------------------
#define GPIO_PORT_W168_PWORD_Pos                              0                                                         /*!< GPIO_PORT W168: PWORD Position      */
#define GPIO_PORT_W168_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W168_PWORD_Pos)                /*!< GPIO_PORT W168: PWORD Mask          */

// -------------------------------------  GPIO_PORT_W169  -----------------------------------------
#define GPIO_PORT_W169_PWORD_Pos                              0                                                         /*!< GPIO_PORT W169: PWORD Position      */
#define GPIO_PORT_W169_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W169_PWORD_Pos)                /*!< GPIO_PORT W169: PWORD Mask          */

// -------------------------------------  GPIO_PORT_W170  -----------------------------------------
#define GPIO_PORT_W170_PWORD_Pos                              0                                                         /*!< GPIO_PORT W170: PWORD Position      */
#define GPIO_PORT_W170_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W170_PWORD_Pos)                /*!< GPIO_PORT W170: PWORD Mask          */

// -------------------------------------  GPIO_PORT_W171  -----------------------------------------
#define GPIO_PORT_W171_PWORD_Pos                              0                                                         /*!< GPIO_PORT W171: PWORD Position      */
#define GPIO_PORT_W171_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W171_PWORD_Pos)                /*!< GPIO_PORT W171: PWORD Mask          */

// -------------------------------------  GPIO_PORT_W172  -----------------------------------------
#define GPIO_PORT_W172_PWORD_Pos                              0                                                         /*!< GPIO_PORT W172: PWORD Position      */
#define GPIO_PORT_W172_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W172_PWORD_Pos)                /*!< GPIO_PORT W172: PWORD Mask          */

// -------------------------------------  GPIO_PORT_W173  -----------------------------------------
#define GPIO_PORT_W173_PWORD_Pos                              0                                                         /*!< GPIO_PORT W173: PWORD Position      */
#define GPIO_PORT_W173_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W173_PWORD_Pos)                /*!< GPIO_PORT W173: PWORD Mask          */

// -------------------------------------  GPIO_PORT_W174  -----------------------------------------
#define GPIO_PORT_W174_PWORD_Pos                              0                                                         /*!< GPIO_PORT W174: PWORD Position      */
#define GPIO_PORT_W174_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W174_PWORD_Pos)                /*!< GPIO_PORT W174: PWORD Mask          */

// -------------------------------------  GPIO_PORT_W175  -----------------------------------------
#define GPIO_PORT_W175_PWORD_Pos                              0                                                         /*!< GPIO_PORT W175: PWORD Position      */
#define GPIO_PORT_W175_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W175_PWORD_Pos)                /*!< GPIO_PORT W175: PWORD Mask          */

// -------------------------------------  GPIO_PORT_W176  -----------------------------------------
#define GPIO_PORT_W176_PWORD_Pos                              0                                                         /*!< GPIO_PORT W176: PWORD Position      */
#define GPIO_PORT_W176_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W176_PWORD_Pos)                /*!< GPIO_PORT W176: PWORD Mask          */

// -------------------------------------  GPIO_PORT_W177  -----------------------------------------
#define GPIO_PORT_W177_PWORD_Pos                              0                                                         /*!< GPIO_PORT W177: PWORD Position      */
#define GPIO_PORT_W177_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W177_PWORD_Pos)                /*!< GPIO_PORT W177: PWORD Mask          */

// -------------------------------------  GPIO_PORT_W178  -----------------------------------------
#define GPIO_PORT_W178_PWORD_Pos                              0                                                         /*!< GPIO_PORT W178: PWORD Position      */
#define GPIO_PORT_W178_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W178_PWORD_Pos)                /*!< GPIO_PORT W178: PWORD Mask          */

// -------------------------------------  GPIO_PORT_W179  -----------------------------------------
#define GPIO_PORT_W179_PWORD_Pos                              0                                                         /*!< GPIO_PORT W179: PWORD Position      */
#define GPIO_PORT_W179_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W179_PWORD_Pos)                /*!< GPIO_PORT W179: PWORD Mask          */

// -------------------------------------  GPIO_PORT_W180  -----------------------------------------
#define GPIO_PORT_W180_PWORD_Pos                              0                                                         /*!< GPIO_PORT W180: PWORD Position      */
#define GPIO_PORT_W180_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W180_PWORD_Pos)                /*!< GPIO_PORT W180: PWORD Mask          */

// -------------------------------------  GPIO_PORT_W181  -----------------------------------------
#define GPIO_PORT_W181_PWORD_Pos                              0                                                         /*!< GPIO_PORT W181: PWORD Position      */
#define GPIO_PORT_W181_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W181_PWORD_Pos)                /*!< GPIO_PORT W181: PWORD Mask          */

// -------------------------------------  GPIO_PORT_W182  -----------------------------------------
#define GPIO_PORT_W182_PWORD_Pos                              0                                                         /*!< GPIO_PORT W182: PWORD Position      */
#define GPIO_PORT_W182_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W182_PWORD_Pos)                /*!< GPIO_PORT W182: PWORD Mask          */

// -------------------------------------  GPIO_PORT_W183  -----------------------------------------
#define GPIO_PORT_W183_PWORD_Pos                              0                                                         /*!< GPIO_PORT W183: PWORD Position      */
#define GPIO_PORT_W183_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W183_PWORD_Pos)                /*!< GPIO_PORT W183: PWORD Mask          */

// -------------------------------------  GPIO_PORT_W184  -----------------------------------------
#define GPIO_PORT_W184_PWORD_Pos                              0                                                         /*!< GPIO_PORT W184: PWORD Position      */
#define GPIO_PORT_W184_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W184_PWORD_Pos)                /*!< GPIO_PORT W184: PWORD Mask          */

// -------------------------------------  GPIO_PORT_W185  -----------------------------------------
#define GPIO_PORT_W185_PWORD_Pos                              0                                                         /*!< GPIO_PORT W185: PWORD Position      */
#define GPIO_PORT_W185_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W185_PWORD_Pos)                /*!< GPIO_PORT W185: PWORD Mask          */

// -------------------------------------  GPIO_PORT_W186  -----------------------------------------
#define GPIO_PORT_W186_PWORD_Pos                              0                                                         /*!< GPIO_PORT W186: PWORD Position      */
#define GPIO_PORT_W186_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W186_PWORD_Pos)                /*!< GPIO_PORT W186: PWORD Mask          */

// -------------------------------------  GPIO_PORT_W187  -----------------------------------------
#define GPIO_PORT_W187_PWORD_Pos                              0                                                         /*!< GPIO_PORT W187: PWORD Position      */
#define GPIO_PORT_W187_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W187_PWORD_Pos)                /*!< GPIO_PORT W187: PWORD Mask          */

// -------------------------------------  GPIO_PORT_W188  -----------------------------------------
#define GPIO_PORT_W188_PWORD_Pos                              0                                                         /*!< GPIO_PORT W188: PWORD Position      */
#define GPIO_PORT_W188_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W188_PWORD_Pos)                /*!< GPIO_PORT W188: PWORD Mask          */

// -------------------------------------  GPIO_PORT_W189  -----------------------------------------
#define GPIO_PORT_W189_PWORD_Pos                              0                                                         /*!< GPIO_PORT W189: PWORD Position      */
#define GPIO_PORT_W189_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W189_PWORD_Pos)                /*!< GPIO_PORT W189: PWORD Mask          */

// -------------------------------------  GPIO_PORT_W190  -----------------------------------------
#define GPIO_PORT_W190_PWORD_Pos                              0                                                         /*!< GPIO_PORT W190: PWORD Position      */
#define GPIO_PORT_W190_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W190_PWORD_Pos)                /*!< GPIO_PORT W190: PWORD Mask          */

// -------------------------------------  GPIO_PORT_W191  -----------------------------------------
#define GPIO_PORT_W191_PWORD_Pos                              0                                                         /*!< GPIO_PORT W191: PWORD Position      */
#define GPIO_PORT_W191_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W191_PWORD_Pos)                /*!< GPIO_PORT W191: PWORD Mask          */

// -------------------------------------  GPIO_PORT_W192  -----------------------------------------
#define GPIO_PORT_W192_PWORD_Pos                              0                                                         /*!< GPIO_PORT W192: PWORD Position      */
#define GPIO_PORT_W192_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W192_PWORD_Pos)                /*!< GPIO_PORT W192: PWORD Mask          */

// -------------------------------------  GPIO_PORT_W193  -----------------------------------------
#define GPIO_PORT_W193_PWORD_Pos                              0                                                         /*!< GPIO_PORT W193: PWORD Position      */
#define GPIO_PORT_W193_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W193_PWORD_Pos)                /*!< GPIO_PORT W193: PWORD Mask          */

// -------------------------------------  GPIO_PORT_W194  -----------------------------------------
#define GPIO_PORT_W194_PWORD_Pos                              0                                                         /*!< GPIO_PORT W194: PWORD Position      */
#define GPIO_PORT_W194_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W194_PWORD_Pos)                /*!< GPIO_PORT W194: PWORD Mask          */

// -------------------------------------  GPIO_PORT_W195  -----------------------------------------
#define GPIO_PORT_W195_PWORD_Pos                              0                                                         /*!< GPIO_PORT W195: PWORD Position      */
#define GPIO_PORT_W195_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W195_PWORD_Pos)                /*!< GPIO_PORT W195: PWORD Mask          */

// -------------------------------------  GPIO_PORT_W196  -----------------------------------------
#define GPIO_PORT_W196_PWORD_Pos                              0                                                         /*!< GPIO_PORT W196: PWORD Position      */
#define GPIO_PORT_W196_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W196_PWORD_Pos)                /*!< GPIO_PORT W196: PWORD Mask          */

// -------------------------------------  GPIO_PORT_W197  -----------------------------------------
#define GPIO_PORT_W197_PWORD_Pos                              0                                                         /*!< GPIO_PORT W197: PWORD Position      */
#define GPIO_PORT_W197_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W197_PWORD_Pos)                /*!< GPIO_PORT W197: PWORD Mask          */

// -------------------------------------  GPIO_PORT_W198  -----------------------------------------
#define GPIO_PORT_W198_PWORD_Pos                              0                                                         /*!< GPIO_PORT W198: PWORD Position      */
#define GPIO_PORT_W198_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W198_PWORD_Pos)                /*!< GPIO_PORT W198: PWORD Mask          */

// -------------------------------------  GPIO_PORT_W199  -----------------------------------------
#define GPIO_PORT_W199_PWORD_Pos                              0                                                         /*!< GPIO_PORT W199: PWORD Position      */
#define GPIO_PORT_W199_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W199_PWORD_Pos)                /*!< GPIO_PORT W199: PWORD Mask          */

// -------------------------------------  GPIO_PORT_W200  -----------------------------------------
#define GPIO_PORT_W200_PWORD_Pos                              0                                                         /*!< GPIO_PORT W200: PWORD Position      */
#define GPIO_PORT_W200_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W200_PWORD_Pos)                /*!< GPIO_PORT W200: PWORD Mask          */

// -------------------------------------  GPIO_PORT_W201  -----------------------------------------
#define GPIO_PORT_W201_PWORD_Pos                              0                                                         /*!< GPIO_PORT W201: PWORD Position      */
#define GPIO_PORT_W201_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W201_PWORD_Pos)                /*!< GPIO_PORT W201: PWORD Mask          */

// -------------------------------------  GPIO_PORT_W202  -----------------------------------------
#define GPIO_PORT_W202_PWORD_Pos                              0                                                         /*!< GPIO_PORT W202: PWORD Position      */
#define GPIO_PORT_W202_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W202_PWORD_Pos)                /*!< GPIO_PORT W202: PWORD Mask          */

// -------------------------------------  GPIO_PORT_W203  -----------------------------------------
#define GPIO_PORT_W203_PWORD_Pos                              0                                                         /*!< GPIO_PORT W203: PWORD Position      */
#define GPIO_PORT_W203_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W203_PWORD_Pos)                /*!< GPIO_PORT W203: PWORD Mask          */

// -------------------------------------  GPIO_PORT_W204  -----------------------------------------
#define GPIO_PORT_W204_PWORD_Pos                              0                                                         /*!< GPIO_PORT W204: PWORD Position      */
#define GPIO_PORT_W204_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W204_PWORD_Pos)                /*!< GPIO_PORT W204: PWORD Mask          */

// -------------------------------------  GPIO_PORT_W205  -----------------------------------------
#define GPIO_PORT_W205_PWORD_Pos                              0                                                         /*!< GPIO_PORT W205: PWORD Position      */
#define GPIO_PORT_W205_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W205_PWORD_Pos)                /*!< GPIO_PORT W205: PWORD Mask          */

// -------------------------------------  GPIO_PORT_W206  -----------------------------------------
#define GPIO_PORT_W206_PWORD_Pos                              0                                                         /*!< GPIO_PORT W206: PWORD Position      */
#define GPIO_PORT_W206_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W206_PWORD_Pos)                /*!< GPIO_PORT W206: PWORD Mask          */

// -------------------------------------  GPIO_PORT_W207  -----------------------------------------
#define GPIO_PORT_W207_PWORD_Pos                              0                                                         /*!< GPIO_PORT W207: PWORD Position      */
#define GPIO_PORT_W207_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W207_PWORD_Pos)                /*!< GPIO_PORT W207: PWORD Mask          */

// -------------------------------------  GPIO_PORT_W208  -----------------------------------------
#define GPIO_PORT_W208_PWORD_Pos                              0                                                         /*!< GPIO_PORT W208: PWORD Position      */
#define GPIO_PORT_W208_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W208_PWORD_Pos)                /*!< GPIO_PORT W208: PWORD Mask          */

// -------------------------------------  GPIO_PORT_W209  -----------------------------------------
#define GPIO_PORT_W209_PWORD_Pos                              0                                                         /*!< GPIO_PORT W209: PWORD Position      */
#define GPIO_PORT_W209_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W209_PWORD_Pos)                /*!< GPIO_PORT W209: PWORD Mask          */

// -------------------------------------  GPIO_PORT_W210  -----------------------------------------
#define GPIO_PORT_W210_PWORD_Pos                              0                                                         /*!< GPIO_PORT W210: PWORD Position      */
#define GPIO_PORT_W210_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W210_PWORD_Pos)                /*!< GPIO_PORT W210: PWORD Mask          */

// -------------------------------------  GPIO_PORT_W211  -----------------------------------------
#define GPIO_PORT_W211_PWORD_Pos                              0                                                         /*!< GPIO_PORT W211: PWORD Position      */
#define GPIO_PORT_W211_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W211_PWORD_Pos)                /*!< GPIO_PORT W211: PWORD Mask          */

// -------------------------------------  GPIO_PORT_W212  -----------------------------------------
#define GPIO_PORT_W212_PWORD_Pos                              0                                                         /*!< GPIO_PORT W212: PWORD Position      */
#define GPIO_PORT_W212_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W212_PWORD_Pos)                /*!< GPIO_PORT W212: PWORD Mask          */

// -------------------------------------  GPIO_PORT_W213  -----------------------------------------
#define GPIO_PORT_W213_PWORD_Pos                              0                                                         /*!< GPIO_PORT W213: PWORD Position      */
#define GPIO_PORT_W213_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W213_PWORD_Pos)                /*!< GPIO_PORT W213: PWORD Mask          */

// -------------------------------------  GPIO_PORT_W214  -----------------------------------------
#define GPIO_PORT_W214_PWORD_Pos                              0                                                         /*!< GPIO_PORT W214: PWORD Position      */
#define GPIO_PORT_W214_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W214_PWORD_Pos)                /*!< GPIO_PORT W214: PWORD Mask          */

// -------------------------------------  GPIO_PORT_W215  -----------------------------------------
#define GPIO_PORT_W215_PWORD_Pos                              0                                                         /*!< GPIO_PORT W215: PWORD Position      */
#define GPIO_PORT_W215_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W215_PWORD_Pos)                /*!< GPIO_PORT W215: PWORD Mask          */

// -------------------------------------  GPIO_PORT_W216  -----------------------------------------
#define GPIO_PORT_W216_PWORD_Pos                              0                                                         /*!< GPIO_PORT W216: PWORD Position      */
#define GPIO_PORT_W216_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W216_PWORD_Pos)                /*!< GPIO_PORT W216: PWORD Mask          */

// -------------------------------------  GPIO_PORT_W217  -----------------------------------------
#define GPIO_PORT_W217_PWORD_Pos                              0                                                         /*!< GPIO_PORT W217: PWORD Position      */
#define GPIO_PORT_W217_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W217_PWORD_Pos)                /*!< GPIO_PORT W217: PWORD Mask          */

// -------------------------------------  GPIO_PORT_W218  -----------------------------------------
#define GPIO_PORT_W218_PWORD_Pos                              0                                                         /*!< GPIO_PORT W218: PWORD Position      */
#define GPIO_PORT_W218_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W218_PWORD_Pos)                /*!< GPIO_PORT W218: PWORD Mask          */

// -------------------------------------  GPIO_PORT_W219  -----------------------------------------
#define GPIO_PORT_W219_PWORD_Pos                              0                                                         /*!< GPIO_PORT W219: PWORD Position      */
#define GPIO_PORT_W219_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W219_PWORD_Pos)                /*!< GPIO_PORT W219: PWORD Mask          */

// -------------------------------------  GPIO_PORT_W220  -----------------------------------------
#define GPIO_PORT_W220_PWORD_Pos                              0                                                         /*!< GPIO_PORT W220: PWORD Position      */
#define GPIO_PORT_W220_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W220_PWORD_Pos)                /*!< GPIO_PORT W220: PWORD Mask          */

// -------------------------------------  GPIO_PORT_W221  -----------------------------------------
#define GPIO_PORT_W221_PWORD_Pos                              0                                                         /*!< GPIO_PORT W221: PWORD Position      */
#define GPIO_PORT_W221_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W221_PWORD_Pos)                /*!< GPIO_PORT W221: PWORD Mask          */

// -------------------------------------  GPIO_PORT_W222  -----------------------------------------
#define GPIO_PORT_W222_PWORD_Pos                              0                                                         /*!< GPIO_PORT W222: PWORD Position      */
#define GPIO_PORT_W222_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W222_PWORD_Pos)                /*!< GPIO_PORT W222: PWORD Mask          */

// -------------------------------------  GPIO_PORT_W223  -----------------------------------------
#define GPIO_PORT_W223_PWORD_Pos                              0                                                         /*!< GPIO_PORT W223: PWORD Position      */
#define GPIO_PORT_W223_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W223_PWORD_Pos)                /*!< GPIO_PORT W223: PWORD Mask          */

// -------------------------------------  GPIO_PORT_W224  -----------------------------------------
#define GPIO_PORT_W224_PWORD_Pos                              0                                                         /*!< GPIO_PORT W224: PWORD Position      */
#define GPIO_PORT_W224_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W224_PWORD_Pos)                /*!< GPIO_PORT W224: PWORD Mask          */

// -------------------------------------  GPIO_PORT_W225  -----------------------------------------
#define GPIO_PORT_W225_PWORD_Pos                              0                                                         /*!< GPIO_PORT W225: PWORD Position      */
#define GPIO_PORT_W225_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W225_PWORD_Pos)                /*!< GPIO_PORT W225: PWORD Mask          */

// -------------------------------------  GPIO_PORT_W226  -----------------------------------------
#define GPIO_PORT_W226_PWORD_Pos                              0                                                         /*!< GPIO_PORT W226: PWORD Position      */
#define GPIO_PORT_W226_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W226_PWORD_Pos)                /*!< GPIO_PORT W226: PWORD Mask          */

// -------------------------------------  GPIO_PORT_W227  -----------------------------------------
#define GPIO_PORT_W227_PWORD_Pos                              0                                                         /*!< GPIO_PORT W227: PWORD Position      */
#define GPIO_PORT_W227_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W227_PWORD_Pos)                /*!< GPIO_PORT W227: PWORD Mask          */

// -------------------------------------  GPIO_PORT_W228  -----------------------------------------
#define GPIO_PORT_W228_PWORD_Pos                              0                                                         /*!< GPIO_PORT W228: PWORD Position      */
#define GPIO_PORT_W228_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W228_PWORD_Pos)                /*!< GPIO_PORT W228: PWORD Mask          */

// -------------------------------------  GPIO_PORT_W229  -----------------------------------------
#define GPIO_PORT_W229_PWORD_Pos                              0                                                         /*!< GPIO_PORT W229: PWORD Position      */
#define GPIO_PORT_W229_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W229_PWORD_Pos)                /*!< GPIO_PORT W229: PWORD Mask          */

// -------------------------------------  GPIO_PORT_W230  -----------------------------------------
#define GPIO_PORT_W230_PWORD_Pos                              0                                                         /*!< GPIO_PORT W230: PWORD Position      */
#define GPIO_PORT_W230_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W230_PWORD_Pos)                /*!< GPIO_PORT W230: PWORD Mask          */

// -------------------------------------  GPIO_PORT_W231  -----------------------------------------
#define GPIO_PORT_W231_PWORD_Pos                              0                                                         /*!< GPIO_PORT W231: PWORD Position      */
#define GPIO_PORT_W231_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W231_PWORD_Pos)                /*!< GPIO_PORT W231: PWORD Mask          */

// -------------------------------------  GPIO_PORT_W232  -----------------------------------------
#define GPIO_PORT_W232_PWORD_Pos                              0                                                         /*!< GPIO_PORT W232: PWORD Position      */
#define GPIO_PORT_W232_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W232_PWORD_Pos)                /*!< GPIO_PORT W232: PWORD Mask          */

// -------------------------------------  GPIO_PORT_W233  -----------------------------------------
#define GPIO_PORT_W233_PWORD_Pos                              0                                                         /*!< GPIO_PORT W233: PWORD Position      */
#define GPIO_PORT_W233_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W233_PWORD_Pos)                /*!< GPIO_PORT W233: PWORD Mask          */

// -------------------------------------  GPIO_PORT_W234  -----------------------------------------
#define GPIO_PORT_W234_PWORD_Pos                              0                                                         /*!< GPIO_PORT W234: PWORD Position      */
#define GPIO_PORT_W234_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W234_PWORD_Pos)                /*!< GPIO_PORT W234: PWORD Mask          */

// -------------------------------------  GPIO_PORT_W235  -----------------------------------------
#define GPIO_PORT_W235_PWORD_Pos                              0                                                         /*!< GPIO_PORT W235: PWORD Position      */
#define GPIO_PORT_W235_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W235_PWORD_Pos)                /*!< GPIO_PORT W235: PWORD Mask          */

// -------------------------------------  GPIO_PORT_W236  -----------------------------------------
#define GPIO_PORT_W236_PWORD_Pos                              0                                                         /*!< GPIO_PORT W236: PWORD Position      */
#define GPIO_PORT_W236_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W236_PWORD_Pos)                /*!< GPIO_PORT W236: PWORD Mask          */

// -------------------------------------  GPIO_PORT_W237  -----------------------------------------
#define GPIO_PORT_W237_PWORD_Pos                              0                                                         /*!< GPIO_PORT W237: PWORD Position      */
#define GPIO_PORT_W237_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W237_PWORD_Pos)                /*!< GPIO_PORT W237: PWORD Mask          */

// -------------------------------------  GPIO_PORT_W238  -----------------------------------------
#define GPIO_PORT_W238_PWORD_Pos                              0                                                         /*!< GPIO_PORT W238: PWORD Position      */
#define GPIO_PORT_W238_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W238_PWORD_Pos)                /*!< GPIO_PORT W238: PWORD Mask          */

// -------------------------------------  GPIO_PORT_W239  -----------------------------------------
#define GPIO_PORT_W239_PWORD_Pos                              0                                                         /*!< GPIO_PORT W239: PWORD Position      */
#define GPIO_PORT_W239_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W239_PWORD_Pos)                /*!< GPIO_PORT W239: PWORD Mask          */

// -------------------------------------  GPIO_PORT_W240  -----------------------------------------
#define GPIO_PORT_W240_PWORD_Pos                              0                                                         /*!< GPIO_PORT W240: PWORD Position      */
#define GPIO_PORT_W240_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W240_PWORD_Pos)                /*!< GPIO_PORT W240: PWORD Mask          */

// -------------------------------------  GPIO_PORT_W241  -----------------------------------------
#define GPIO_PORT_W241_PWORD_Pos                              0                                                         /*!< GPIO_PORT W241: PWORD Position      */
#define GPIO_PORT_W241_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W241_PWORD_Pos)                /*!< GPIO_PORT W241: PWORD Mask          */

// -------------------------------------  GPIO_PORT_W242  -----------------------------------------
#define GPIO_PORT_W242_PWORD_Pos                              0                                                         /*!< GPIO_PORT W242: PWORD Position      */
#define GPIO_PORT_W242_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W242_PWORD_Pos)                /*!< GPIO_PORT W242: PWORD Mask          */

// -------------------------------------  GPIO_PORT_W243  -----------------------------------------
#define GPIO_PORT_W243_PWORD_Pos                              0                                                         /*!< GPIO_PORT W243: PWORD Position      */
#define GPIO_PORT_W243_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W243_PWORD_Pos)                /*!< GPIO_PORT W243: PWORD Mask          */

// -------------------------------------  GPIO_PORT_W244  -----------------------------------------
#define GPIO_PORT_W244_PWORD_Pos                              0                                                         /*!< GPIO_PORT W244: PWORD Position      */
#define GPIO_PORT_W244_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W244_PWORD_Pos)                /*!< GPIO_PORT W244: PWORD Mask          */

// -------------------------------------  GPIO_PORT_W245  -----------------------------------------
#define GPIO_PORT_W245_PWORD_Pos                              0                                                         /*!< GPIO_PORT W245: PWORD Position      */
#define GPIO_PORT_W245_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W245_PWORD_Pos)                /*!< GPIO_PORT W245: PWORD Mask          */

// -------------------------------------  GPIO_PORT_W246  -----------------------------------------
#define GPIO_PORT_W246_PWORD_Pos                              0                                                         /*!< GPIO_PORT W246: PWORD Position      */
#define GPIO_PORT_W246_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W246_PWORD_Pos)                /*!< GPIO_PORT W246: PWORD Mask          */

// -------------------------------------  GPIO_PORT_W247  -----------------------------------------
#define GPIO_PORT_W247_PWORD_Pos                              0                                                         /*!< GPIO_PORT W247: PWORD Position      */
#define GPIO_PORT_W247_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W247_PWORD_Pos)                /*!< GPIO_PORT W247: PWORD Mask          */

// -------------------------------------  GPIO_PORT_W248  -----------------------------------------
#define GPIO_PORT_W248_PWORD_Pos                              0                                                         /*!< GPIO_PORT W248: PWORD Position      */
#define GPIO_PORT_W248_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W248_PWORD_Pos)                /*!< GPIO_PORT W248: PWORD Mask          */

// -------------------------------------  GPIO_PORT_W249  -----------------------------------------
#define GPIO_PORT_W249_PWORD_Pos                              0                                                         /*!< GPIO_PORT W249: PWORD Position      */
#define GPIO_PORT_W249_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W249_PWORD_Pos)                /*!< GPIO_PORT W249: PWORD Mask          */

// -------------------------------------  GPIO_PORT_W250  -----------------------------------------
#define GPIO_PORT_W250_PWORD_Pos                              0                                                         /*!< GPIO_PORT W250: PWORD Position      */
#define GPIO_PORT_W250_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W250_PWORD_Pos)                /*!< GPIO_PORT W250: PWORD Mask          */

// -------------------------------------  GPIO_PORT_W251  -----------------------------------------
#define GPIO_PORT_W251_PWORD_Pos                              0                                                         /*!< GPIO_PORT W251: PWORD Position      */
#define GPIO_PORT_W251_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W251_PWORD_Pos)                /*!< GPIO_PORT W251: PWORD Mask          */

// -------------------------------------  GPIO_PORT_W252  -----------------------------------------
#define GPIO_PORT_W252_PWORD_Pos                              0                                                         /*!< GPIO_PORT W252: PWORD Position      */
#define GPIO_PORT_W252_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W252_PWORD_Pos)                /*!< GPIO_PORT W252: PWORD Mask          */

// -------------------------------------  GPIO_PORT_W253  -----------------------------------------
#define GPIO_PORT_W253_PWORD_Pos                              0                                                         /*!< GPIO_PORT W253: PWORD Position      */
#define GPIO_PORT_W253_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W253_PWORD_Pos)                /*!< GPIO_PORT W253: PWORD Mask          */

// -------------------------------------  GPIO_PORT_W254  -----------------------------------------
#define GPIO_PORT_W254_PWORD_Pos                              0                                                         /*!< GPIO_PORT W254: PWORD Position      */
#define GPIO_PORT_W254_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W254_PWORD_Pos)                /*!< GPIO_PORT W254: PWORD Mask          */

// -------------------------------------  GPIO_PORT_W255  -----------------------------------------
#define GPIO_PORT_W255_PWORD_Pos                              0                                                         /*!< GPIO_PORT W255: PWORD Position      */
#define GPIO_PORT_W255_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W255_PWORD_Pos)                /*!< GPIO_PORT W255: PWORD Mask          */

// -------------------------------------  GPIO_PORT_DIR0  -----------------------------------------
#define GPIO_PORT_DIR0_DIRP0_Pos                              0                                                         /*!< GPIO_PORT DIR0: DIRP0 Position      */
#define GPIO_PORT_DIR0_DIRP0_Msk                              (0x01UL << GPIO_PORT_DIR0_DIRP0_Pos)                      /*!< GPIO_PORT DIR0: DIRP0 Mask          */
#define GPIO_PORT_DIR0_DIRP1_Pos                              1                                                         /*!< GPIO_PORT DIR0: DIRP1 Position      */
#define GPIO_PORT_DIR0_DIRP1_Msk                              (0x01UL << GPIO_PORT_DIR0_DIRP1_Pos)                      /*!< GPIO_PORT DIR0: DIRP1 Mask          */
#define GPIO_PORT_DIR0_DIRP2_Pos                              2                                                         /*!< GPIO_PORT DIR0: DIRP2 Position      */
#define GPIO_PORT_DIR0_DIRP2_Msk                              (0x01UL << GPIO_PORT_DIR0_DIRP2_Pos)                      /*!< GPIO_PORT DIR0: DIRP2 Mask          */
#define GPIO_PORT_DIR0_DIRP3_Pos                              3                                                         /*!< GPIO_PORT DIR0: DIRP3 Position      */
#define GPIO_PORT_DIR0_DIRP3_Msk                              (0x01UL << GPIO_PORT_DIR0_DIRP3_Pos)                      /*!< GPIO_PORT DIR0: DIRP3 Mask          */
#define GPIO_PORT_DIR0_DIRP4_Pos                              4                                                         /*!< GPIO_PORT DIR0: DIRP4 Position      */
#define GPIO_PORT_DIR0_DIRP4_Msk                              (0x01UL << GPIO_PORT_DIR0_DIRP4_Pos)                      /*!< GPIO_PORT DIR0: DIRP4 Mask          */
#define GPIO_PORT_DIR0_DIRP5_Pos                              5                                                         /*!< GPIO_PORT DIR0: DIRP5 Position      */
#define GPIO_PORT_DIR0_DIRP5_Msk                              (0x01UL << GPIO_PORT_DIR0_DIRP5_Pos)                      /*!< GPIO_PORT DIR0: DIRP5 Mask          */
#define GPIO_PORT_DIR0_DIRP6_Pos                              6                                                         /*!< GPIO_PORT DIR0: DIRP6 Position      */
#define GPIO_PORT_DIR0_DIRP6_Msk                              (0x01UL << GPIO_PORT_DIR0_DIRP6_Pos)                      /*!< GPIO_PORT DIR0: DIRP6 Mask          */
#define GPIO_PORT_DIR0_DIRP7_Pos                              7                                                         /*!< GPIO_PORT DIR0: DIRP7 Position      */
#define GPIO_PORT_DIR0_DIRP7_Msk                              (0x01UL << GPIO_PORT_DIR0_DIRP7_Pos)                      /*!< GPIO_PORT DIR0: DIRP7 Mask          */
#define GPIO_PORT_DIR0_DIRP8_Pos                              8                                                         /*!< GPIO_PORT DIR0: DIRP8 Position      */
#define GPIO_PORT_DIR0_DIRP8_Msk                              (0x01UL << GPIO_PORT_DIR0_DIRP8_Pos)                      /*!< GPIO_PORT DIR0: DIRP8 Mask          */
#define GPIO_PORT_DIR0_DIRP9_Pos                              9                                                         /*!< GPIO_PORT DIR0: DIRP9 Position      */
#define GPIO_PORT_DIR0_DIRP9_Msk                              (0x01UL << GPIO_PORT_DIR0_DIRP9_Pos)                      /*!< GPIO_PORT DIR0: DIRP9 Mask          */
#define GPIO_PORT_DIR0_DIRP10_Pos                             10                                                        /*!< GPIO_PORT DIR0: DIRP10 Position     */
#define GPIO_PORT_DIR0_DIRP10_Msk                             (0x01UL << GPIO_PORT_DIR0_DIRP10_Pos)                     /*!< GPIO_PORT DIR0: DIRP10 Mask         */
#define GPIO_PORT_DIR0_DIRP11_Pos                             11                                                        /*!< GPIO_PORT DIR0: DIRP11 Position     */
#define GPIO_PORT_DIR0_DIRP11_Msk                             (0x01UL << GPIO_PORT_DIR0_DIRP11_Pos)                     /*!< GPIO_PORT DIR0: DIRP11 Mask         */
#define GPIO_PORT_DIR0_DIRP12_Pos                             12                                                        /*!< GPIO_PORT DIR0: DIRP12 Position     */
#define GPIO_PORT_DIR0_DIRP12_Msk                             (0x01UL << GPIO_PORT_DIR0_DIRP12_Pos)                     /*!< GPIO_PORT DIR0: DIRP12 Mask         */
#define GPIO_PORT_DIR0_DIRP13_Pos                             13                                                        /*!< GPIO_PORT DIR0: DIRP13 Position     */
#define GPIO_PORT_DIR0_DIRP13_Msk                             (0x01UL << GPIO_PORT_DIR0_DIRP13_Pos)                     /*!< GPIO_PORT DIR0: DIRP13 Mask         */
#define GPIO_PORT_DIR0_DIRP14_Pos                             14                                                        /*!< GPIO_PORT DIR0: DIRP14 Position     */
#define GPIO_PORT_DIR0_DIRP14_Msk                             (0x01UL << GPIO_PORT_DIR0_DIRP14_Pos)                     /*!< GPIO_PORT DIR0: DIRP14 Mask         */
#define GPIO_PORT_DIR0_DIRP15_Pos                             15                                                        /*!< GPIO_PORT DIR0: DIRP15 Position     */
#define GPIO_PORT_DIR0_DIRP15_Msk                             (0x01UL << GPIO_PORT_DIR0_DIRP15_Pos)                     /*!< GPIO_PORT DIR0: DIRP15 Mask         */
#define GPIO_PORT_DIR0_DIRP16_Pos                             16                                                        /*!< GPIO_PORT DIR0: DIRP16 Position     */
#define GPIO_PORT_DIR0_DIRP16_Msk                             (0x01UL << GPIO_PORT_DIR0_DIRP16_Pos)                     /*!< GPIO_PORT DIR0: DIRP16 Mask         */
#define GPIO_PORT_DIR0_DIRP17_Pos                             17                                                        /*!< GPIO_PORT DIR0: DIRP17 Position     */
#define GPIO_PORT_DIR0_DIRP17_Msk                             (0x01UL << GPIO_PORT_DIR0_DIRP17_Pos)                     /*!< GPIO_PORT DIR0: DIRP17 Mask         */
#define GPIO_PORT_DIR0_DIRP18_Pos                             18                                                        /*!< GPIO_PORT DIR0: DIRP18 Position     */
#define GPIO_PORT_DIR0_DIRP18_Msk                             (0x01UL << GPIO_PORT_DIR0_DIRP18_Pos)                     /*!< GPIO_PORT DIR0: DIRP18 Mask         */
#define GPIO_PORT_DIR0_DIRP19_Pos                             19                                                        /*!< GPIO_PORT DIR0: DIRP19 Position     */
#define GPIO_PORT_DIR0_DIRP19_Msk                             (0x01UL << GPIO_PORT_DIR0_DIRP19_Pos)                     /*!< GPIO_PORT DIR0: DIRP19 Mask         */
#define GPIO_PORT_DIR0_DIRP20_Pos                             20                                                        /*!< GPIO_PORT DIR0: DIRP20 Position     */
#define GPIO_PORT_DIR0_DIRP20_Msk                             (0x01UL << GPIO_PORT_DIR0_DIRP20_Pos)                     /*!< GPIO_PORT DIR0: DIRP20 Mask         */
#define GPIO_PORT_DIR0_DIRP21_Pos                             21                                                        /*!< GPIO_PORT DIR0: DIRP21 Position     */
#define GPIO_PORT_DIR0_DIRP21_Msk                             (0x01UL << GPIO_PORT_DIR0_DIRP21_Pos)                     /*!< GPIO_PORT DIR0: DIRP21 Mask         */
#define GPIO_PORT_DIR0_DIRP22_Pos                             22                                                        /*!< GPIO_PORT DIR0: DIRP22 Position     */
#define GPIO_PORT_DIR0_DIRP22_Msk                             (0x01UL << GPIO_PORT_DIR0_DIRP22_Pos)                     /*!< GPIO_PORT DIR0: DIRP22 Mask         */
#define GPIO_PORT_DIR0_DIRP23_Pos                             23                                                        /*!< GPIO_PORT DIR0: DIRP23 Position     */
#define GPIO_PORT_DIR0_DIRP23_Msk                             (0x01UL << GPIO_PORT_DIR0_DIRP23_Pos)                     /*!< GPIO_PORT DIR0: DIRP23 Mask         */
#define GPIO_PORT_DIR0_DIRP24_Pos                             24                                                        /*!< GPIO_PORT DIR0: DIRP24 Position     */
#define GPIO_PORT_DIR0_DIRP24_Msk                             (0x01UL << GPIO_PORT_DIR0_DIRP24_Pos)                     /*!< GPIO_PORT DIR0: DIRP24 Mask         */
#define GPIO_PORT_DIR0_DIRP25_Pos                             25                                                        /*!< GPIO_PORT DIR0: DIRP25 Position     */
#define GPIO_PORT_DIR0_DIRP25_Msk                             (0x01UL << GPIO_PORT_DIR0_DIRP25_Pos)                     /*!< GPIO_PORT DIR0: DIRP25 Mask         */
#define GPIO_PORT_DIR0_DIRP26_Pos                             26                                                        /*!< GPIO_PORT DIR0: DIRP26 Position     */
#define GPIO_PORT_DIR0_DIRP26_Msk                             (0x01UL << GPIO_PORT_DIR0_DIRP26_Pos)                     /*!< GPIO_PORT DIR0: DIRP26 Mask         */
#define GPIO_PORT_DIR0_DIRP27_Pos                             27                                                        /*!< GPIO_PORT DIR0: DIRP27 Position     */
#define GPIO_PORT_DIR0_DIRP27_Msk                             (0x01UL << GPIO_PORT_DIR0_DIRP27_Pos)                     /*!< GPIO_PORT DIR0: DIRP27 Mask         */
#define GPIO_PORT_DIR0_DIRP28_Pos                             28                                                        /*!< GPIO_PORT DIR0: DIRP28 Position     */
#define GPIO_PORT_DIR0_DIRP28_Msk                             (0x01UL << GPIO_PORT_DIR0_DIRP28_Pos)                     /*!< GPIO_PORT DIR0: DIRP28 Mask         */
#define GPIO_PORT_DIR0_DIRP29_Pos                             29                                                        /*!< GPIO_PORT DIR0: DIRP29 Position     */
#define GPIO_PORT_DIR0_DIRP29_Msk                             (0x01UL << GPIO_PORT_DIR0_DIRP29_Pos)                     /*!< GPIO_PORT DIR0: DIRP29 Mask         */
#define GPIO_PORT_DIR0_DIRP30_Pos                             30                                                        /*!< GPIO_PORT DIR0: DIRP30 Position     */
#define GPIO_PORT_DIR0_DIRP30_Msk                             (0x01UL << GPIO_PORT_DIR0_DIRP30_Pos)                     /*!< GPIO_PORT DIR0: DIRP30 Mask         */
#define GPIO_PORT_DIR0_DIRP31_Pos                             31                                                        /*!< GPIO_PORT DIR0: DIRP31 Position     */
#define GPIO_PORT_DIR0_DIRP31_Msk                             (0x01UL << GPIO_PORT_DIR0_DIRP31_Pos)                     /*!< GPIO_PORT DIR0: DIRP31 Mask         */

// -------------------------------------  GPIO_PORT_DIR1  -----------------------------------------
#define GPIO_PORT_DIR1_DIRP0_Pos                              0                                                         /*!< GPIO_PORT DIR1: DIRP0 Position      */
#define GPIO_PORT_DIR1_DIRP0_Msk                              (0x01UL << GPIO_PORT_DIR1_DIRP0_Pos)                      /*!< GPIO_PORT DIR1: DIRP0 Mask          */
#define GPIO_PORT_DIR1_DIRP1_Pos                              1                                                         /*!< GPIO_PORT DIR1: DIRP1 Position      */
#define GPIO_PORT_DIR1_DIRP1_Msk                              (0x01UL << GPIO_PORT_DIR1_DIRP1_Pos)                      /*!< GPIO_PORT DIR1: DIRP1 Mask          */
#define GPIO_PORT_DIR1_DIRP2_Pos                              2                                                         /*!< GPIO_PORT DIR1: DIRP2 Position      */
#define GPIO_PORT_DIR1_DIRP2_Msk                              (0x01UL << GPIO_PORT_DIR1_DIRP2_Pos)                      /*!< GPIO_PORT DIR1: DIRP2 Mask          */
#define GPIO_PORT_DIR1_DIRP3_Pos                              3                                                         /*!< GPIO_PORT DIR1: DIRP3 Position      */
#define GPIO_PORT_DIR1_DIRP3_Msk                              (0x01UL << GPIO_PORT_DIR1_DIRP3_Pos)                      /*!< GPIO_PORT DIR1: DIRP3 Mask          */
#define GPIO_PORT_DIR1_DIRP4_Pos                              4                                                         /*!< GPIO_PORT DIR1: DIRP4 Position      */
#define GPIO_PORT_DIR1_DIRP4_Msk                              (0x01UL << GPIO_PORT_DIR1_DIRP4_Pos)                      /*!< GPIO_PORT DIR1: DIRP4 Mask          */
#define GPIO_PORT_DIR1_DIRP5_Pos                              5                                                         /*!< GPIO_PORT DIR1: DIRP5 Position      */
#define GPIO_PORT_DIR1_DIRP5_Msk                              (0x01UL << GPIO_PORT_DIR1_DIRP5_Pos)                      /*!< GPIO_PORT DIR1: DIRP5 Mask          */
#define GPIO_PORT_DIR1_DIRP6_Pos                              6                                                         /*!< GPIO_PORT DIR1: DIRP6 Position      */
#define GPIO_PORT_DIR1_DIRP6_Msk                              (0x01UL << GPIO_PORT_DIR1_DIRP6_Pos)                      /*!< GPIO_PORT DIR1: DIRP6 Mask          */
#define GPIO_PORT_DIR1_DIRP7_Pos                              7                                                         /*!< GPIO_PORT DIR1: DIRP7 Position      */
#define GPIO_PORT_DIR1_DIRP7_Msk                              (0x01UL << GPIO_PORT_DIR1_DIRP7_Pos)                      /*!< GPIO_PORT DIR1: DIRP7 Mask          */
#define GPIO_PORT_DIR1_DIRP8_Pos                              8                                                         /*!< GPIO_PORT DIR1: DIRP8 Position      */
#define GPIO_PORT_DIR1_DIRP8_Msk                              (0x01UL << GPIO_PORT_DIR1_DIRP8_Pos)                      /*!< GPIO_PORT DIR1: DIRP8 Mask          */
#define GPIO_PORT_DIR1_DIRP9_Pos                              9                                                         /*!< GPIO_PORT DIR1: DIRP9 Position      */
#define GPIO_PORT_DIR1_DIRP9_Msk                              (0x01UL << GPIO_PORT_DIR1_DIRP9_Pos)                      /*!< GPIO_PORT DIR1: DIRP9 Mask          */
#define GPIO_PORT_DIR1_DIRP10_Pos                             10                                                        /*!< GPIO_PORT DIR1: DIRP10 Position     */
#define GPIO_PORT_DIR1_DIRP10_Msk                             (0x01UL << GPIO_PORT_DIR1_DIRP10_Pos)                     /*!< GPIO_PORT DIR1: DIRP10 Mask         */
#define GPIO_PORT_DIR1_DIRP11_Pos                             11                                                        /*!< GPIO_PORT DIR1: DIRP11 Position     */
#define GPIO_PORT_DIR1_DIRP11_Msk                             (0x01UL << GPIO_PORT_DIR1_DIRP11_Pos)                     /*!< GPIO_PORT DIR1: DIRP11 Mask         */
#define GPIO_PORT_DIR1_DIRP12_Pos                             12                                                        /*!< GPIO_PORT DIR1: DIRP12 Position     */
#define GPIO_PORT_DIR1_DIRP12_Msk                             (0x01UL << GPIO_PORT_DIR1_DIRP12_Pos)                     /*!< GPIO_PORT DIR1: DIRP12 Mask         */
#define GPIO_PORT_DIR1_DIRP13_Pos                             13                                                        /*!< GPIO_PORT DIR1: DIRP13 Position     */
#define GPIO_PORT_DIR1_DIRP13_Msk                             (0x01UL << GPIO_PORT_DIR1_DIRP13_Pos)                     /*!< GPIO_PORT DIR1: DIRP13 Mask         */
#define GPIO_PORT_DIR1_DIRP14_Pos                             14                                                        /*!< GPIO_PORT DIR1: DIRP14 Position     */
#define GPIO_PORT_DIR1_DIRP14_Msk                             (0x01UL << GPIO_PORT_DIR1_DIRP14_Pos)                     /*!< GPIO_PORT DIR1: DIRP14 Mask         */
#define GPIO_PORT_DIR1_DIRP15_Pos                             15                                                        /*!< GPIO_PORT DIR1: DIRP15 Position     */
#define GPIO_PORT_DIR1_DIRP15_Msk                             (0x01UL << GPIO_PORT_DIR1_DIRP15_Pos)                     /*!< GPIO_PORT DIR1: DIRP15 Mask         */
#define GPIO_PORT_DIR1_DIRP16_Pos                             16                                                        /*!< GPIO_PORT DIR1: DIRP16 Position     */
#define GPIO_PORT_DIR1_DIRP16_Msk                             (0x01UL << GPIO_PORT_DIR1_DIRP16_Pos)                     /*!< GPIO_PORT DIR1: DIRP16 Mask         */
#define GPIO_PORT_DIR1_DIRP17_Pos                             17                                                        /*!< GPIO_PORT DIR1: DIRP17 Position     */
#define GPIO_PORT_DIR1_DIRP17_Msk                             (0x01UL << GPIO_PORT_DIR1_DIRP17_Pos)                     /*!< GPIO_PORT DIR1: DIRP17 Mask         */
#define GPIO_PORT_DIR1_DIRP18_Pos                             18                                                        /*!< GPIO_PORT DIR1: DIRP18 Position     */
#define GPIO_PORT_DIR1_DIRP18_Msk                             (0x01UL << GPIO_PORT_DIR1_DIRP18_Pos)                     /*!< GPIO_PORT DIR1: DIRP18 Mask         */
#define GPIO_PORT_DIR1_DIRP19_Pos                             19                                                        /*!< GPIO_PORT DIR1: DIRP19 Position     */
#define GPIO_PORT_DIR1_DIRP19_Msk                             (0x01UL << GPIO_PORT_DIR1_DIRP19_Pos)                     /*!< GPIO_PORT DIR1: DIRP19 Mask         */
#define GPIO_PORT_DIR1_DIRP20_Pos                             20                                                        /*!< GPIO_PORT DIR1: DIRP20 Position     */
#define GPIO_PORT_DIR1_DIRP20_Msk                             (0x01UL << GPIO_PORT_DIR1_DIRP20_Pos)                     /*!< GPIO_PORT DIR1: DIRP20 Mask         */
#define GPIO_PORT_DIR1_DIRP21_Pos                             21                                                        /*!< GPIO_PORT DIR1: DIRP21 Position     */
#define GPIO_PORT_DIR1_DIRP21_Msk                             (0x01UL << GPIO_PORT_DIR1_DIRP21_Pos)                     /*!< GPIO_PORT DIR1: DIRP21 Mask         */
#define GPIO_PORT_DIR1_DIRP22_Pos                             22                                                        /*!< GPIO_PORT DIR1: DIRP22 Position     */
#define GPIO_PORT_DIR1_DIRP22_Msk                             (0x01UL << GPIO_PORT_DIR1_DIRP22_Pos)                     /*!< GPIO_PORT DIR1: DIRP22 Mask         */
#define GPIO_PORT_DIR1_DIRP23_Pos                             23                                                        /*!< GPIO_PORT DIR1: DIRP23 Position     */
#define GPIO_PORT_DIR1_DIRP23_Msk                             (0x01UL << GPIO_PORT_DIR1_DIRP23_Pos)                     /*!< GPIO_PORT DIR1: DIRP23 Mask         */
#define GPIO_PORT_DIR1_DIRP24_Pos                             24                                                        /*!< GPIO_PORT DIR1: DIRP24 Position     */
#define GPIO_PORT_DIR1_DIRP24_Msk                             (0x01UL << GPIO_PORT_DIR1_DIRP24_Pos)                     /*!< GPIO_PORT DIR1: DIRP24 Mask         */
#define GPIO_PORT_DIR1_DIRP25_Pos                             25                                                        /*!< GPIO_PORT DIR1: DIRP25 Position     */
#define GPIO_PORT_DIR1_DIRP25_Msk                             (0x01UL << GPIO_PORT_DIR1_DIRP25_Pos)                     /*!< GPIO_PORT DIR1: DIRP25 Mask         */
#define GPIO_PORT_DIR1_DIRP26_Pos                             26                                                        /*!< GPIO_PORT DIR1: DIRP26 Position     */
#define GPIO_PORT_DIR1_DIRP26_Msk                             (0x01UL << GPIO_PORT_DIR1_DIRP26_Pos)                     /*!< GPIO_PORT DIR1: DIRP26 Mask         */
#define GPIO_PORT_DIR1_DIRP27_Pos                             27                                                        /*!< GPIO_PORT DIR1: DIRP27 Position     */
#define GPIO_PORT_DIR1_DIRP27_Msk                             (0x01UL << GPIO_PORT_DIR1_DIRP27_Pos)                     /*!< GPIO_PORT DIR1: DIRP27 Mask         */
#define GPIO_PORT_DIR1_DIRP28_Pos                             28                                                        /*!< GPIO_PORT DIR1: DIRP28 Position     */
#define GPIO_PORT_DIR1_DIRP28_Msk                             (0x01UL << GPIO_PORT_DIR1_DIRP28_Pos)                     /*!< GPIO_PORT DIR1: DIRP28 Mask         */
#define GPIO_PORT_DIR1_DIRP29_Pos                             29                                                        /*!< GPIO_PORT DIR1: DIRP29 Position     */
#define GPIO_PORT_DIR1_DIRP29_Msk                             (0x01UL << GPIO_PORT_DIR1_DIRP29_Pos)                     /*!< GPIO_PORT DIR1: DIRP29 Mask         */
#define GPIO_PORT_DIR1_DIRP30_Pos                             30                                                        /*!< GPIO_PORT DIR1: DIRP30 Position     */
#define GPIO_PORT_DIR1_DIRP30_Msk                             (0x01UL << GPIO_PORT_DIR1_DIRP30_Pos)                     /*!< GPIO_PORT DIR1: DIRP30 Mask         */
#define GPIO_PORT_DIR1_DIRP31_Pos                             31                                                        /*!< GPIO_PORT DIR1: DIRP31 Position     */
#define GPIO_PORT_DIR1_DIRP31_Msk                             (0x01UL << GPIO_PORT_DIR1_DIRP31_Pos)                     /*!< GPIO_PORT DIR1: DIRP31 Mask         */

// -------------------------------------  GPIO_PORT_DIR2  -----------------------------------------
#define GPIO_PORT_DIR2_DIRP0_Pos                              0                                                         /*!< GPIO_PORT DIR2: DIRP0 Position      */
#define GPIO_PORT_DIR2_DIRP0_Msk                              (0x01UL << GPIO_PORT_DIR2_DIRP0_Pos)                      /*!< GPIO_PORT DIR2: DIRP0 Mask          */
#define GPIO_PORT_DIR2_DIRP1_Pos                              1                                                         /*!< GPIO_PORT DIR2: DIRP1 Position      */
#define GPIO_PORT_DIR2_DIRP1_Msk                              (0x01UL << GPIO_PORT_DIR2_DIRP1_Pos)                      /*!< GPIO_PORT DIR2: DIRP1 Mask          */
#define GPIO_PORT_DIR2_DIRP2_Pos                              2                                                         /*!< GPIO_PORT DIR2: DIRP2 Position      */
#define GPIO_PORT_DIR2_DIRP2_Msk                              (0x01UL << GPIO_PORT_DIR2_DIRP2_Pos)                      /*!< GPIO_PORT DIR2: DIRP2 Mask          */
#define GPIO_PORT_DIR2_DIRP3_Pos                              3                                                         /*!< GPIO_PORT DIR2: DIRP3 Position      */
#define GPIO_PORT_DIR2_DIRP3_Msk                              (0x01UL << GPIO_PORT_DIR2_DIRP3_Pos)                      /*!< GPIO_PORT DIR2: DIRP3 Mask          */
#define GPIO_PORT_DIR2_DIRP4_Pos                              4                                                         /*!< GPIO_PORT DIR2: DIRP4 Position      */
#define GPIO_PORT_DIR2_DIRP4_Msk                              (0x01UL << GPIO_PORT_DIR2_DIRP4_Pos)                      /*!< GPIO_PORT DIR2: DIRP4 Mask          */
#define GPIO_PORT_DIR2_DIRP5_Pos                              5                                                         /*!< GPIO_PORT DIR2: DIRP5 Position      */
#define GPIO_PORT_DIR2_DIRP5_Msk                              (0x01UL << GPIO_PORT_DIR2_DIRP5_Pos)                      /*!< GPIO_PORT DIR2: DIRP5 Mask          */
#define GPIO_PORT_DIR2_DIRP6_Pos                              6                                                         /*!< GPIO_PORT DIR2: DIRP6 Position      */
#define GPIO_PORT_DIR2_DIRP6_Msk                              (0x01UL << GPIO_PORT_DIR2_DIRP6_Pos)                      /*!< GPIO_PORT DIR2: DIRP6 Mask          */
#define GPIO_PORT_DIR2_DIRP7_Pos                              7                                                         /*!< GPIO_PORT DIR2: DIRP7 Position      */
#define GPIO_PORT_DIR2_DIRP7_Msk                              (0x01UL << GPIO_PORT_DIR2_DIRP7_Pos)                      /*!< GPIO_PORT DIR2: DIRP7 Mask          */
#define GPIO_PORT_DIR2_DIRP8_Pos                              8                                                         /*!< GPIO_PORT DIR2: DIRP8 Position      */
#define GPIO_PORT_DIR2_DIRP8_Msk                              (0x01UL << GPIO_PORT_DIR2_DIRP8_Pos)                      /*!< GPIO_PORT DIR2: DIRP8 Mask          */
#define GPIO_PORT_DIR2_DIRP9_Pos                              9                                                         /*!< GPIO_PORT DIR2: DIRP9 Position      */
#define GPIO_PORT_DIR2_DIRP9_Msk                              (0x01UL << GPIO_PORT_DIR2_DIRP9_Pos)                      /*!< GPIO_PORT DIR2: DIRP9 Mask          */
#define GPIO_PORT_DIR2_DIRP10_Pos                             10                                                        /*!< GPIO_PORT DIR2: DIRP10 Position     */
#define GPIO_PORT_DIR2_DIRP10_Msk                             (0x01UL << GPIO_PORT_DIR2_DIRP10_Pos)                     /*!< GPIO_PORT DIR2: DIRP10 Mask         */
#define GPIO_PORT_DIR2_DIRP11_Pos                             11                                                        /*!< GPIO_PORT DIR2: DIRP11 Position     */
#define GPIO_PORT_DIR2_DIRP11_Msk                             (0x01UL << GPIO_PORT_DIR2_DIRP11_Pos)                     /*!< GPIO_PORT DIR2: DIRP11 Mask         */
#define GPIO_PORT_DIR2_DIRP12_Pos                             12                                                        /*!< GPIO_PORT DIR2: DIRP12 Position     */
#define GPIO_PORT_DIR2_DIRP12_Msk                             (0x01UL << GPIO_PORT_DIR2_DIRP12_Pos)                     /*!< GPIO_PORT DIR2: DIRP12 Mask         */
#define GPIO_PORT_DIR2_DIRP13_Pos                             13                                                        /*!< GPIO_PORT DIR2: DIRP13 Position     */
#define GPIO_PORT_DIR2_DIRP13_Msk                             (0x01UL << GPIO_PORT_DIR2_DIRP13_Pos)                     /*!< GPIO_PORT DIR2: DIRP13 Mask         */
#define GPIO_PORT_DIR2_DIRP14_Pos                             14                                                        /*!< GPIO_PORT DIR2: DIRP14 Position     */
#define GPIO_PORT_DIR2_DIRP14_Msk                             (0x01UL << GPIO_PORT_DIR2_DIRP14_Pos)                     /*!< GPIO_PORT DIR2: DIRP14 Mask         */
#define GPIO_PORT_DIR2_DIRP15_Pos                             15                                                        /*!< GPIO_PORT DIR2: DIRP15 Position     */
#define GPIO_PORT_DIR2_DIRP15_Msk                             (0x01UL << GPIO_PORT_DIR2_DIRP15_Pos)                     /*!< GPIO_PORT DIR2: DIRP15 Mask         */
#define GPIO_PORT_DIR2_DIRP16_Pos                             16                                                        /*!< GPIO_PORT DIR2: DIRP16 Position     */
#define GPIO_PORT_DIR2_DIRP16_Msk                             (0x01UL << GPIO_PORT_DIR2_DIRP16_Pos)                     /*!< GPIO_PORT DIR2: DIRP16 Mask         */
#define GPIO_PORT_DIR2_DIRP17_Pos                             17                                                        /*!< GPIO_PORT DIR2: DIRP17 Position     */
#define GPIO_PORT_DIR2_DIRP17_Msk                             (0x01UL << GPIO_PORT_DIR2_DIRP17_Pos)                     /*!< GPIO_PORT DIR2: DIRP17 Mask         */
#define GPIO_PORT_DIR2_DIRP18_Pos                             18                                                        /*!< GPIO_PORT DIR2: DIRP18 Position     */
#define GPIO_PORT_DIR2_DIRP18_Msk                             (0x01UL << GPIO_PORT_DIR2_DIRP18_Pos)                     /*!< GPIO_PORT DIR2: DIRP18 Mask         */
#define GPIO_PORT_DIR2_DIRP19_Pos                             19                                                        /*!< GPIO_PORT DIR2: DIRP19 Position     */
#define GPIO_PORT_DIR2_DIRP19_Msk                             (0x01UL << GPIO_PORT_DIR2_DIRP19_Pos)                     /*!< GPIO_PORT DIR2: DIRP19 Mask         */
#define GPIO_PORT_DIR2_DIRP20_Pos                             20                                                        /*!< GPIO_PORT DIR2: DIRP20 Position     */
#define GPIO_PORT_DIR2_DIRP20_Msk                             (0x01UL << GPIO_PORT_DIR2_DIRP20_Pos)                     /*!< GPIO_PORT DIR2: DIRP20 Mask         */
#define GPIO_PORT_DIR2_DIRP21_Pos                             21                                                        /*!< GPIO_PORT DIR2: DIRP21 Position     */
#define GPIO_PORT_DIR2_DIRP21_Msk                             (0x01UL << GPIO_PORT_DIR2_DIRP21_Pos)                     /*!< GPIO_PORT DIR2: DIRP21 Mask         */
#define GPIO_PORT_DIR2_DIRP22_Pos                             22                                                        /*!< GPIO_PORT DIR2: DIRP22 Position     */
#define GPIO_PORT_DIR2_DIRP22_Msk                             (0x01UL << GPIO_PORT_DIR2_DIRP22_Pos)                     /*!< GPIO_PORT DIR2: DIRP22 Mask         */
#define GPIO_PORT_DIR2_DIRP23_Pos                             23                                                        /*!< GPIO_PORT DIR2: DIRP23 Position     */
#define GPIO_PORT_DIR2_DIRP23_Msk                             (0x01UL << GPIO_PORT_DIR2_DIRP23_Pos)                     /*!< GPIO_PORT DIR2: DIRP23 Mask         */
#define GPIO_PORT_DIR2_DIRP24_Pos                             24                                                        /*!< GPIO_PORT DIR2: DIRP24 Position     */
#define GPIO_PORT_DIR2_DIRP24_Msk                             (0x01UL << GPIO_PORT_DIR2_DIRP24_Pos)                     /*!< GPIO_PORT DIR2: DIRP24 Mask         */
#define GPIO_PORT_DIR2_DIRP25_Pos                             25                                                        /*!< GPIO_PORT DIR2: DIRP25 Position     */
#define GPIO_PORT_DIR2_DIRP25_Msk                             (0x01UL << GPIO_PORT_DIR2_DIRP25_Pos)                     /*!< GPIO_PORT DIR2: DIRP25 Mask         */
#define GPIO_PORT_DIR2_DIRP26_Pos                             26                                                        /*!< GPIO_PORT DIR2: DIRP26 Position     */
#define GPIO_PORT_DIR2_DIRP26_Msk                             (0x01UL << GPIO_PORT_DIR2_DIRP26_Pos)                     /*!< GPIO_PORT DIR2: DIRP26 Mask         */
#define GPIO_PORT_DIR2_DIRP27_Pos                             27                                                        /*!< GPIO_PORT DIR2: DIRP27 Position     */
#define GPIO_PORT_DIR2_DIRP27_Msk                             (0x01UL << GPIO_PORT_DIR2_DIRP27_Pos)                     /*!< GPIO_PORT DIR2: DIRP27 Mask         */
#define GPIO_PORT_DIR2_DIRP28_Pos                             28                                                        /*!< GPIO_PORT DIR2: DIRP28 Position     */
#define GPIO_PORT_DIR2_DIRP28_Msk                             (0x01UL << GPIO_PORT_DIR2_DIRP28_Pos)                     /*!< GPIO_PORT DIR2: DIRP28 Mask         */
#define GPIO_PORT_DIR2_DIRP29_Pos                             29                                                        /*!< GPIO_PORT DIR2: DIRP29 Position     */
#define GPIO_PORT_DIR2_DIRP29_Msk                             (0x01UL << GPIO_PORT_DIR2_DIRP29_Pos)                     /*!< GPIO_PORT DIR2: DIRP29 Mask         */
#define GPIO_PORT_DIR2_DIRP30_Pos                             30                                                        /*!< GPIO_PORT DIR2: DIRP30 Position     */
#define GPIO_PORT_DIR2_DIRP30_Msk                             (0x01UL << GPIO_PORT_DIR2_DIRP30_Pos)                     /*!< GPIO_PORT DIR2: DIRP30 Mask         */
#define GPIO_PORT_DIR2_DIRP31_Pos                             31                                                        /*!< GPIO_PORT DIR2: DIRP31 Position     */
#define GPIO_PORT_DIR2_DIRP31_Msk                             (0x01UL << GPIO_PORT_DIR2_DIRP31_Pos)                     /*!< GPIO_PORT DIR2: DIRP31 Mask         */

// -------------------------------------  GPIO_PORT_DIR3  -----------------------------------------
#define GPIO_PORT_DIR3_DIRP0_Pos                              0                                                         /*!< GPIO_PORT DIR3: DIRP0 Position      */
#define GPIO_PORT_DIR3_DIRP0_Msk                              (0x01UL << GPIO_PORT_DIR3_DIRP0_Pos)                      /*!< GPIO_PORT DIR3: DIRP0 Mask          */
#define GPIO_PORT_DIR3_DIRP1_Pos                              1                                                         /*!< GPIO_PORT DIR3: DIRP1 Position      */
#define GPIO_PORT_DIR3_DIRP1_Msk                              (0x01UL << GPIO_PORT_DIR3_DIRP1_Pos)                      /*!< GPIO_PORT DIR3: DIRP1 Mask          */
#define GPIO_PORT_DIR3_DIRP2_Pos                              2                                                         /*!< GPIO_PORT DIR3: DIRP2 Position      */
#define GPIO_PORT_DIR3_DIRP2_Msk                              (0x01UL << GPIO_PORT_DIR3_DIRP2_Pos)                      /*!< GPIO_PORT DIR3: DIRP2 Mask          */
#define GPIO_PORT_DIR3_DIRP3_Pos                              3                                                         /*!< GPIO_PORT DIR3: DIRP3 Position      */
#define GPIO_PORT_DIR3_DIRP3_Msk                              (0x01UL << GPIO_PORT_DIR3_DIRP3_Pos)                      /*!< GPIO_PORT DIR3: DIRP3 Mask          */
#define GPIO_PORT_DIR3_DIRP4_Pos                              4                                                         /*!< GPIO_PORT DIR3: DIRP4 Position      */
#define GPIO_PORT_DIR3_DIRP4_Msk                              (0x01UL << GPIO_PORT_DIR3_DIRP4_Pos)                      /*!< GPIO_PORT DIR3: DIRP4 Mask          */
#define GPIO_PORT_DIR3_DIRP5_Pos                              5                                                         /*!< GPIO_PORT DIR3: DIRP5 Position      */
#define GPIO_PORT_DIR3_DIRP5_Msk                              (0x01UL << GPIO_PORT_DIR3_DIRP5_Pos)                      /*!< GPIO_PORT DIR3: DIRP5 Mask          */
#define GPIO_PORT_DIR3_DIRP6_Pos                              6                                                         /*!< GPIO_PORT DIR3: DIRP6 Position      */
#define GPIO_PORT_DIR3_DIRP6_Msk                              (0x01UL << GPIO_PORT_DIR3_DIRP6_Pos)                      /*!< GPIO_PORT DIR3: DIRP6 Mask          */
#define GPIO_PORT_DIR3_DIRP7_Pos                              7                                                         /*!< GPIO_PORT DIR3: DIRP7 Position      */
#define GPIO_PORT_DIR3_DIRP7_Msk                              (0x01UL << GPIO_PORT_DIR3_DIRP7_Pos)                      /*!< GPIO_PORT DIR3: DIRP7 Mask          */
#define GPIO_PORT_DIR3_DIRP8_Pos                              8                                                         /*!< GPIO_PORT DIR3: DIRP8 Position      */
#define GPIO_PORT_DIR3_DIRP8_Msk                              (0x01UL << GPIO_PORT_DIR3_DIRP8_Pos)                      /*!< GPIO_PORT DIR3: DIRP8 Mask          */
#define GPIO_PORT_DIR3_DIRP9_Pos                              9                                                         /*!< GPIO_PORT DIR3: DIRP9 Position      */
#define GPIO_PORT_DIR3_DIRP9_Msk                              (0x01UL << GPIO_PORT_DIR3_DIRP9_Pos)                      /*!< GPIO_PORT DIR3: DIRP9 Mask          */
#define GPIO_PORT_DIR3_DIRP10_Pos                             10                                                        /*!< GPIO_PORT DIR3: DIRP10 Position     */
#define GPIO_PORT_DIR3_DIRP10_Msk                             (0x01UL << GPIO_PORT_DIR3_DIRP10_Pos)                     /*!< GPIO_PORT DIR3: DIRP10 Mask         */
#define GPIO_PORT_DIR3_DIRP11_Pos                             11                                                        /*!< GPIO_PORT DIR3: DIRP11 Position     */
#define GPIO_PORT_DIR3_DIRP11_Msk                             (0x01UL << GPIO_PORT_DIR3_DIRP11_Pos)                     /*!< GPIO_PORT DIR3: DIRP11 Mask         */
#define GPIO_PORT_DIR3_DIRP12_Pos                             12                                                        /*!< GPIO_PORT DIR3: DIRP12 Position     */
#define GPIO_PORT_DIR3_DIRP12_Msk                             (0x01UL << GPIO_PORT_DIR3_DIRP12_Pos)                     /*!< GPIO_PORT DIR3: DIRP12 Mask         */
#define GPIO_PORT_DIR3_DIRP13_Pos                             13                                                        /*!< GPIO_PORT DIR3: DIRP13 Position     */
#define GPIO_PORT_DIR3_DIRP13_Msk                             (0x01UL << GPIO_PORT_DIR3_DIRP13_Pos)                     /*!< GPIO_PORT DIR3: DIRP13 Mask         */
#define GPIO_PORT_DIR3_DIRP14_Pos                             14                                                        /*!< GPIO_PORT DIR3: DIRP14 Position     */
#define GPIO_PORT_DIR3_DIRP14_Msk                             (0x01UL << GPIO_PORT_DIR3_DIRP14_Pos)                     /*!< GPIO_PORT DIR3: DIRP14 Mask         */
#define GPIO_PORT_DIR3_DIRP15_Pos                             15                                                        /*!< GPIO_PORT DIR3: DIRP15 Position     */
#define GPIO_PORT_DIR3_DIRP15_Msk                             (0x01UL << GPIO_PORT_DIR3_DIRP15_Pos)                     /*!< GPIO_PORT DIR3: DIRP15 Mask         */
#define GPIO_PORT_DIR3_DIRP16_Pos                             16                                                        /*!< GPIO_PORT DIR3: DIRP16 Position     */
#define GPIO_PORT_DIR3_DIRP16_Msk                             (0x01UL << GPIO_PORT_DIR3_DIRP16_Pos)                     /*!< GPIO_PORT DIR3: DIRP16 Mask         */
#define GPIO_PORT_DIR3_DIRP17_Pos                             17                                                        /*!< GPIO_PORT DIR3: DIRP17 Position     */
#define GPIO_PORT_DIR3_DIRP17_Msk                             (0x01UL << GPIO_PORT_DIR3_DIRP17_Pos)                     /*!< GPIO_PORT DIR3: DIRP17 Mask         */
#define GPIO_PORT_DIR3_DIRP18_Pos                             18                                                        /*!< GPIO_PORT DIR3: DIRP18 Position     */
#define GPIO_PORT_DIR3_DIRP18_Msk                             (0x01UL << GPIO_PORT_DIR3_DIRP18_Pos)                     /*!< GPIO_PORT DIR3: DIRP18 Mask         */
#define GPIO_PORT_DIR3_DIRP19_Pos                             19                                                        /*!< GPIO_PORT DIR3: DIRP19 Position     */
#define GPIO_PORT_DIR3_DIRP19_Msk                             (0x01UL << GPIO_PORT_DIR3_DIRP19_Pos)                     /*!< GPIO_PORT DIR3: DIRP19 Mask         */
#define GPIO_PORT_DIR3_DIRP20_Pos                             20                                                        /*!< GPIO_PORT DIR3: DIRP20 Position     */
#define GPIO_PORT_DIR3_DIRP20_Msk                             (0x01UL << GPIO_PORT_DIR3_DIRP20_Pos)                     /*!< GPIO_PORT DIR3: DIRP20 Mask         */
#define GPIO_PORT_DIR3_DIRP21_Pos                             21                                                        /*!< GPIO_PORT DIR3: DIRP21 Position     */
#define GPIO_PORT_DIR3_DIRP21_Msk                             (0x01UL << GPIO_PORT_DIR3_DIRP21_Pos)                     /*!< GPIO_PORT DIR3: DIRP21 Mask         */
#define GPIO_PORT_DIR3_DIRP22_Pos                             22                                                        /*!< GPIO_PORT DIR3: DIRP22 Position     */
#define GPIO_PORT_DIR3_DIRP22_Msk                             (0x01UL << GPIO_PORT_DIR3_DIRP22_Pos)                     /*!< GPIO_PORT DIR3: DIRP22 Mask         */
#define GPIO_PORT_DIR3_DIRP23_Pos                             23                                                        /*!< GPIO_PORT DIR3: DIRP23 Position     */
#define GPIO_PORT_DIR3_DIRP23_Msk                             (0x01UL << GPIO_PORT_DIR3_DIRP23_Pos)                     /*!< GPIO_PORT DIR3: DIRP23 Mask         */
#define GPIO_PORT_DIR3_DIRP24_Pos                             24                                                        /*!< GPIO_PORT DIR3: DIRP24 Position     */
#define GPIO_PORT_DIR3_DIRP24_Msk                             (0x01UL << GPIO_PORT_DIR3_DIRP24_Pos)                     /*!< GPIO_PORT DIR3: DIRP24 Mask         */
#define GPIO_PORT_DIR3_DIRP25_Pos                             25                                                        /*!< GPIO_PORT DIR3: DIRP25 Position     */
#define GPIO_PORT_DIR3_DIRP25_Msk                             (0x01UL << GPIO_PORT_DIR3_DIRP25_Pos)                     /*!< GPIO_PORT DIR3: DIRP25 Mask         */
#define GPIO_PORT_DIR3_DIRP26_Pos                             26                                                        /*!< GPIO_PORT DIR3: DIRP26 Position     */
#define GPIO_PORT_DIR3_DIRP26_Msk                             (0x01UL << GPIO_PORT_DIR3_DIRP26_Pos)                     /*!< GPIO_PORT DIR3: DIRP26 Mask         */
#define GPIO_PORT_DIR3_DIRP27_Pos                             27                                                        /*!< GPIO_PORT DIR3: DIRP27 Position     */
#define GPIO_PORT_DIR3_DIRP27_Msk                             (0x01UL << GPIO_PORT_DIR3_DIRP27_Pos)                     /*!< GPIO_PORT DIR3: DIRP27 Mask         */
#define GPIO_PORT_DIR3_DIRP28_Pos                             28                                                        /*!< GPIO_PORT DIR3: DIRP28 Position     */
#define GPIO_PORT_DIR3_DIRP28_Msk                             (0x01UL << GPIO_PORT_DIR3_DIRP28_Pos)                     /*!< GPIO_PORT DIR3: DIRP28 Mask         */
#define GPIO_PORT_DIR3_DIRP29_Pos                             29                                                        /*!< GPIO_PORT DIR3: DIRP29 Position     */
#define GPIO_PORT_DIR3_DIRP29_Msk                             (0x01UL << GPIO_PORT_DIR3_DIRP29_Pos)                     /*!< GPIO_PORT DIR3: DIRP29 Mask         */
#define GPIO_PORT_DIR3_DIRP30_Pos                             30                                                        /*!< GPIO_PORT DIR3: DIRP30 Position     */
#define GPIO_PORT_DIR3_DIRP30_Msk                             (0x01UL << GPIO_PORT_DIR3_DIRP30_Pos)                     /*!< GPIO_PORT DIR3: DIRP30 Mask         */
#define GPIO_PORT_DIR3_DIRP31_Pos                             31                                                        /*!< GPIO_PORT DIR3: DIRP31 Position     */
#define GPIO_PORT_DIR3_DIRP31_Msk                             (0x01UL << GPIO_PORT_DIR3_DIRP31_Pos)                     /*!< GPIO_PORT DIR3: DIRP31 Mask         */

// -------------------------------------  GPIO_PORT_DIR4  -----------------------------------------
#define GPIO_PORT_DIR4_DIRP0_Pos                              0                                                         /*!< GPIO_PORT DIR4: DIRP0 Position      */
#define GPIO_PORT_DIR4_DIRP0_Msk                              (0x01UL << GPIO_PORT_DIR4_DIRP0_Pos)                      /*!< GPIO_PORT DIR4: DIRP0 Mask          */
#define GPIO_PORT_DIR4_DIRP1_Pos                              1                                                         /*!< GPIO_PORT DIR4: DIRP1 Position      */
#define GPIO_PORT_DIR4_DIRP1_Msk                              (0x01UL << GPIO_PORT_DIR4_DIRP1_Pos)                      /*!< GPIO_PORT DIR4: DIRP1 Mask          */
#define GPIO_PORT_DIR4_DIRP2_Pos                              2                                                         /*!< GPIO_PORT DIR4: DIRP2 Position      */
#define GPIO_PORT_DIR4_DIRP2_Msk                              (0x01UL << GPIO_PORT_DIR4_DIRP2_Pos)                      /*!< GPIO_PORT DIR4: DIRP2 Mask          */
#define GPIO_PORT_DIR4_DIRP3_Pos                              3                                                         /*!< GPIO_PORT DIR4: DIRP3 Position      */
#define GPIO_PORT_DIR4_DIRP3_Msk                              (0x01UL << GPIO_PORT_DIR4_DIRP3_Pos)                      /*!< GPIO_PORT DIR4: DIRP3 Mask          */
#define GPIO_PORT_DIR4_DIRP4_Pos                              4                                                         /*!< GPIO_PORT DIR4: DIRP4 Position      */
#define GPIO_PORT_DIR4_DIRP4_Msk                              (0x01UL << GPIO_PORT_DIR4_DIRP4_Pos)                      /*!< GPIO_PORT DIR4: DIRP4 Mask          */
#define GPIO_PORT_DIR4_DIRP5_Pos                              5                                                         /*!< GPIO_PORT DIR4: DIRP5 Position      */
#define GPIO_PORT_DIR4_DIRP5_Msk                              (0x01UL << GPIO_PORT_DIR4_DIRP5_Pos)                      /*!< GPIO_PORT DIR4: DIRP5 Mask          */
#define GPIO_PORT_DIR4_DIRP6_Pos                              6                                                         /*!< GPIO_PORT DIR4: DIRP6 Position      */
#define GPIO_PORT_DIR4_DIRP6_Msk                              (0x01UL << GPIO_PORT_DIR4_DIRP6_Pos)                      /*!< GPIO_PORT DIR4: DIRP6 Mask          */
#define GPIO_PORT_DIR4_DIRP7_Pos                              7                                                         /*!< GPIO_PORT DIR4: DIRP7 Position      */
#define GPIO_PORT_DIR4_DIRP7_Msk                              (0x01UL << GPIO_PORT_DIR4_DIRP7_Pos)                      /*!< GPIO_PORT DIR4: DIRP7 Mask          */
#define GPIO_PORT_DIR4_DIRP8_Pos                              8                                                         /*!< GPIO_PORT DIR4: DIRP8 Position      */
#define GPIO_PORT_DIR4_DIRP8_Msk                              (0x01UL << GPIO_PORT_DIR4_DIRP8_Pos)                      /*!< GPIO_PORT DIR4: DIRP8 Mask          */
#define GPIO_PORT_DIR4_DIRP9_Pos                              9                                                         /*!< GPIO_PORT DIR4: DIRP9 Position      */
#define GPIO_PORT_DIR4_DIRP9_Msk                              (0x01UL << GPIO_PORT_DIR4_DIRP9_Pos)                      /*!< GPIO_PORT DIR4: DIRP9 Mask          */
#define GPIO_PORT_DIR4_DIRP10_Pos                             10                                                        /*!< GPIO_PORT DIR4: DIRP10 Position     */
#define GPIO_PORT_DIR4_DIRP10_Msk                             (0x01UL << GPIO_PORT_DIR4_DIRP10_Pos)                     /*!< GPIO_PORT DIR4: DIRP10 Mask         */
#define GPIO_PORT_DIR4_DIRP11_Pos                             11                                                        /*!< GPIO_PORT DIR4: DIRP11 Position     */
#define GPIO_PORT_DIR4_DIRP11_Msk                             (0x01UL << GPIO_PORT_DIR4_DIRP11_Pos)                     /*!< GPIO_PORT DIR4: DIRP11 Mask         */
#define GPIO_PORT_DIR4_DIRP12_Pos                             12                                                        /*!< GPIO_PORT DIR4: DIRP12 Position     */
#define GPIO_PORT_DIR4_DIRP12_Msk                             (0x01UL << GPIO_PORT_DIR4_DIRP12_Pos)                     /*!< GPIO_PORT DIR4: DIRP12 Mask         */
#define GPIO_PORT_DIR4_DIRP13_Pos                             13                                                        /*!< GPIO_PORT DIR4: DIRP13 Position     */
#define GPIO_PORT_DIR4_DIRP13_Msk                             (0x01UL << GPIO_PORT_DIR4_DIRP13_Pos)                     /*!< GPIO_PORT DIR4: DIRP13 Mask         */
#define GPIO_PORT_DIR4_DIRP14_Pos                             14                                                        /*!< GPIO_PORT DIR4: DIRP14 Position     */
#define GPIO_PORT_DIR4_DIRP14_Msk                             (0x01UL << GPIO_PORT_DIR4_DIRP14_Pos)                     /*!< GPIO_PORT DIR4: DIRP14 Mask         */
#define GPIO_PORT_DIR4_DIRP15_Pos                             15                                                        /*!< GPIO_PORT DIR4: DIRP15 Position     */
#define GPIO_PORT_DIR4_DIRP15_Msk                             (0x01UL << GPIO_PORT_DIR4_DIRP15_Pos)                     /*!< GPIO_PORT DIR4: DIRP15 Mask         */
#define GPIO_PORT_DIR4_DIRP16_Pos                             16                                                        /*!< GPIO_PORT DIR4: DIRP16 Position     */
#define GPIO_PORT_DIR4_DIRP16_Msk                             (0x01UL << GPIO_PORT_DIR4_DIRP16_Pos)                     /*!< GPIO_PORT DIR4: DIRP16 Mask         */
#define GPIO_PORT_DIR4_DIRP17_Pos                             17                                                        /*!< GPIO_PORT DIR4: DIRP17 Position     */
#define GPIO_PORT_DIR4_DIRP17_Msk                             (0x01UL << GPIO_PORT_DIR4_DIRP17_Pos)                     /*!< GPIO_PORT DIR4: DIRP17 Mask         */
#define GPIO_PORT_DIR4_DIRP18_Pos                             18                                                        /*!< GPIO_PORT DIR4: DIRP18 Position     */
#define GPIO_PORT_DIR4_DIRP18_Msk                             (0x01UL << GPIO_PORT_DIR4_DIRP18_Pos)                     /*!< GPIO_PORT DIR4: DIRP18 Mask         */
#define GPIO_PORT_DIR4_DIRP19_Pos                             19                                                        /*!< GPIO_PORT DIR4: DIRP19 Position     */
#define GPIO_PORT_DIR4_DIRP19_Msk                             (0x01UL << GPIO_PORT_DIR4_DIRP19_Pos)                     /*!< GPIO_PORT DIR4: DIRP19 Mask         */
#define GPIO_PORT_DIR4_DIRP20_Pos                             20                                                        /*!< GPIO_PORT DIR4: DIRP20 Position     */
#define GPIO_PORT_DIR4_DIRP20_Msk                             (0x01UL << GPIO_PORT_DIR4_DIRP20_Pos)                     /*!< GPIO_PORT DIR4: DIRP20 Mask         */
#define GPIO_PORT_DIR4_DIRP21_Pos                             21                                                        /*!< GPIO_PORT DIR4: DIRP21 Position     */
#define GPIO_PORT_DIR4_DIRP21_Msk                             (0x01UL << GPIO_PORT_DIR4_DIRP21_Pos)                     /*!< GPIO_PORT DIR4: DIRP21 Mask         */
#define GPIO_PORT_DIR4_DIRP22_Pos                             22                                                        /*!< GPIO_PORT DIR4: DIRP22 Position     */
#define GPIO_PORT_DIR4_DIRP22_Msk                             (0x01UL << GPIO_PORT_DIR4_DIRP22_Pos)                     /*!< GPIO_PORT DIR4: DIRP22 Mask         */
#define GPIO_PORT_DIR4_DIRP23_Pos                             23                                                        /*!< GPIO_PORT DIR4: DIRP23 Position     */
#define GPIO_PORT_DIR4_DIRP23_Msk                             (0x01UL << GPIO_PORT_DIR4_DIRP23_Pos)                     /*!< GPIO_PORT DIR4: DIRP23 Mask         */
#define GPIO_PORT_DIR4_DIRP24_Pos                             24                                                        /*!< GPIO_PORT DIR4: DIRP24 Position     */
#define GPIO_PORT_DIR4_DIRP24_Msk                             (0x01UL << GPIO_PORT_DIR4_DIRP24_Pos)                     /*!< GPIO_PORT DIR4: DIRP24 Mask         */
#define GPIO_PORT_DIR4_DIRP25_Pos                             25                                                        /*!< GPIO_PORT DIR4: DIRP25 Position     */
#define GPIO_PORT_DIR4_DIRP25_Msk                             (0x01UL << GPIO_PORT_DIR4_DIRP25_Pos)                     /*!< GPIO_PORT DIR4: DIRP25 Mask         */
#define GPIO_PORT_DIR4_DIRP26_Pos                             26                                                        /*!< GPIO_PORT DIR4: DIRP26 Position     */
#define GPIO_PORT_DIR4_DIRP26_Msk                             (0x01UL << GPIO_PORT_DIR4_DIRP26_Pos)                     /*!< GPIO_PORT DIR4: DIRP26 Mask         */
#define GPIO_PORT_DIR4_DIRP27_Pos                             27                                                        /*!< GPIO_PORT DIR4: DIRP27 Position     */
#define GPIO_PORT_DIR4_DIRP27_Msk                             (0x01UL << GPIO_PORT_DIR4_DIRP27_Pos)                     /*!< GPIO_PORT DIR4: DIRP27 Mask         */
#define GPIO_PORT_DIR4_DIRP28_Pos                             28                                                        /*!< GPIO_PORT DIR4: DIRP28 Position     */
#define GPIO_PORT_DIR4_DIRP28_Msk                             (0x01UL << GPIO_PORT_DIR4_DIRP28_Pos)                     /*!< GPIO_PORT DIR4: DIRP28 Mask         */
#define GPIO_PORT_DIR4_DIRP29_Pos                             29                                                        /*!< GPIO_PORT DIR4: DIRP29 Position     */
#define GPIO_PORT_DIR4_DIRP29_Msk                             (0x01UL << GPIO_PORT_DIR4_DIRP29_Pos)                     /*!< GPIO_PORT DIR4: DIRP29 Mask         */
#define GPIO_PORT_DIR4_DIRP30_Pos                             30                                                        /*!< GPIO_PORT DIR4: DIRP30 Position     */
#define GPIO_PORT_DIR4_DIRP30_Msk                             (0x01UL << GPIO_PORT_DIR4_DIRP30_Pos)                     /*!< GPIO_PORT DIR4: DIRP30 Mask         */
#define GPIO_PORT_DIR4_DIRP31_Pos                             31                                                        /*!< GPIO_PORT DIR4: DIRP31 Position     */
#define GPIO_PORT_DIR4_DIRP31_Msk                             (0x01UL << GPIO_PORT_DIR4_DIRP31_Pos)                     /*!< GPIO_PORT DIR4: DIRP31 Mask         */

// -------------------------------------  GPIO_PORT_DIR5  -----------------------------------------
#define GPIO_PORT_DIR5_DIRP0_Pos                              0                                                         /*!< GPIO_PORT DIR5: DIRP0 Position      */
#define GPIO_PORT_DIR5_DIRP0_Msk                              (0x01UL << GPIO_PORT_DIR5_DIRP0_Pos)                      /*!< GPIO_PORT DIR5: DIRP0 Mask          */
#define GPIO_PORT_DIR5_DIRP1_Pos                              1                                                         /*!< GPIO_PORT DIR5: DIRP1 Position      */
#define GPIO_PORT_DIR5_DIRP1_Msk                              (0x01UL << GPIO_PORT_DIR5_DIRP1_Pos)                      /*!< GPIO_PORT DIR5: DIRP1 Mask          */
#define GPIO_PORT_DIR5_DIRP2_Pos                              2                                                         /*!< GPIO_PORT DIR5: DIRP2 Position      */
#define GPIO_PORT_DIR5_DIRP2_Msk                              (0x01UL << GPIO_PORT_DIR5_DIRP2_Pos)                      /*!< GPIO_PORT DIR5: DIRP2 Mask          */
#define GPIO_PORT_DIR5_DIRP3_Pos                              3                                                         /*!< GPIO_PORT DIR5: DIRP3 Position      */
#define GPIO_PORT_DIR5_DIRP3_Msk                              (0x01UL << GPIO_PORT_DIR5_DIRP3_Pos)                      /*!< GPIO_PORT DIR5: DIRP3 Mask          */
#define GPIO_PORT_DIR5_DIRP4_Pos                              4                                                         /*!< GPIO_PORT DIR5: DIRP4 Position      */
#define GPIO_PORT_DIR5_DIRP4_Msk                              (0x01UL << GPIO_PORT_DIR5_DIRP4_Pos)                      /*!< GPIO_PORT DIR5: DIRP4 Mask          */
#define GPIO_PORT_DIR5_DIRP5_Pos                              5                                                         /*!< GPIO_PORT DIR5: DIRP5 Position      */
#define GPIO_PORT_DIR5_DIRP5_Msk                              (0x01UL << GPIO_PORT_DIR5_DIRP5_Pos)                      /*!< GPIO_PORT DIR5: DIRP5 Mask          */
#define GPIO_PORT_DIR5_DIRP6_Pos                              6                                                         /*!< GPIO_PORT DIR5: DIRP6 Position      */
#define GPIO_PORT_DIR5_DIRP6_Msk                              (0x01UL << GPIO_PORT_DIR5_DIRP6_Pos)                      /*!< GPIO_PORT DIR5: DIRP6 Mask          */
#define GPIO_PORT_DIR5_DIRP7_Pos                              7                                                         /*!< GPIO_PORT DIR5: DIRP7 Position      */
#define GPIO_PORT_DIR5_DIRP7_Msk                              (0x01UL << GPIO_PORT_DIR5_DIRP7_Pos)                      /*!< GPIO_PORT DIR5: DIRP7 Mask          */
#define GPIO_PORT_DIR5_DIRP8_Pos                              8                                                         /*!< GPIO_PORT DIR5: DIRP8 Position      */
#define GPIO_PORT_DIR5_DIRP8_Msk                              (0x01UL << GPIO_PORT_DIR5_DIRP8_Pos)                      /*!< GPIO_PORT DIR5: DIRP8 Mask          */
#define GPIO_PORT_DIR5_DIRP9_Pos                              9                                                         /*!< GPIO_PORT DIR5: DIRP9 Position      */
#define GPIO_PORT_DIR5_DIRP9_Msk                              (0x01UL << GPIO_PORT_DIR5_DIRP9_Pos)                      /*!< GPIO_PORT DIR5: DIRP9 Mask          */
#define GPIO_PORT_DIR5_DIRP10_Pos                             10                                                        /*!< GPIO_PORT DIR5: DIRP10 Position     */
#define GPIO_PORT_DIR5_DIRP10_Msk                             (0x01UL << GPIO_PORT_DIR5_DIRP10_Pos)                     /*!< GPIO_PORT DIR5: DIRP10 Mask         */
#define GPIO_PORT_DIR5_DIRP11_Pos                             11                                                        /*!< GPIO_PORT DIR5: DIRP11 Position     */
#define GPIO_PORT_DIR5_DIRP11_Msk                             (0x01UL << GPIO_PORT_DIR5_DIRP11_Pos)                     /*!< GPIO_PORT DIR5: DIRP11 Mask         */
#define GPIO_PORT_DIR5_DIRP12_Pos                             12                                                        /*!< GPIO_PORT DIR5: DIRP12 Position     */
#define GPIO_PORT_DIR5_DIRP12_Msk                             (0x01UL << GPIO_PORT_DIR5_DIRP12_Pos)                     /*!< GPIO_PORT DIR5: DIRP12 Mask         */
#define GPIO_PORT_DIR5_DIRP13_Pos                             13                                                        /*!< GPIO_PORT DIR5: DIRP13 Position     */
#define GPIO_PORT_DIR5_DIRP13_Msk                             (0x01UL << GPIO_PORT_DIR5_DIRP13_Pos)                     /*!< GPIO_PORT DIR5: DIRP13 Mask         */
#define GPIO_PORT_DIR5_DIRP14_Pos                             14                                                        /*!< GPIO_PORT DIR5: DIRP14 Position     */
#define GPIO_PORT_DIR5_DIRP14_Msk                             (0x01UL << GPIO_PORT_DIR5_DIRP14_Pos)                     /*!< GPIO_PORT DIR5: DIRP14 Mask         */
#define GPIO_PORT_DIR5_DIRP15_Pos                             15                                                        /*!< GPIO_PORT DIR5: DIRP15 Position     */
#define GPIO_PORT_DIR5_DIRP15_Msk                             (0x01UL << GPIO_PORT_DIR5_DIRP15_Pos)                     /*!< GPIO_PORT DIR5: DIRP15 Mask         */
#define GPIO_PORT_DIR5_DIRP16_Pos                             16                                                        /*!< GPIO_PORT DIR5: DIRP16 Position     */
#define GPIO_PORT_DIR5_DIRP16_Msk                             (0x01UL << GPIO_PORT_DIR5_DIRP16_Pos)                     /*!< GPIO_PORT DIR5: DIRP16 Mask         */
#define GPIO_PORT_DIR5_DIRP17_Pos                             17                                                        /*!< GPIO_PORT DIR5: DIRP17 Position     */
#define GPIO_PORT_DIR5_DIRP17_Msk                             (0x01UL << GPIO_PORT_DIR5_DIRP17_Pos)                     /*!< GPIO_PORT DIR5: DIRP17 Mask         */
#define GPIO_PORT_DIR5_DIRP18_Pos                             18                                                        /*!< GPIO_PORT DIR5: DIRP18 Position     */
#define GPIO_PORT_DIR5_DIRP18_Msk                             (0x01UL << GPIO_PORT_DIR5_DIRP18_Pos)                     /*!< GPIO_PORT DIR5: DIRP18 Mask         */
#define GPIO_PORT_DIR5_DIRP19_Pos                             19                                                        /*!< GPIO_PORT DIR5: DIRP19 Position     */
#define GPIO_PORT_DIR5_DIRP19_Msk                             (0x01UL << GPIO_PORT_DIR5_DIRP19_Pos)                     /*!< GPIO_PORT DIR5: DIRP19 Mask         */
#define GPIO_PORT_DIR5_DIRP20_Pos                             20                                                        /*!< GPIO_PORT DIR5: DIRP20 Position     */
#define GPIO_PORT_DIR5_DIRP20_Msk                             (0x01UL << GPIO_PORT_DIR5_DIRP20_Pos)                     /*!< GPIO_PORT DIR5: DIRP20 Mask         */
#define GPIO_PORT_DIR5_DIRP21_Pos                             21                                                        /*!< GPIO_PORT DIR5: DIRP21 Position     */
#define GPIO_PORT_DIR5_DIRP21_Msk                             (0x01UL << GPIO_PORT_DIR5_DIRP21_Pos)                     /*!< GPIO_PORT DIR5: DIRP21 Mask         */
#define GPIO_PORT_DIR5_DIRP22_Pos                             22                                                        /*!< GPIO_PORT DIR5: DIRP22 Position     */
#define GPIO_PORT_DIR5_DIRP22_Msk                             (0x01UL << GPIO_PORT_DIR5_DIRP22_Pos)                     /*!< GPIO_PORT DIR5: DIRP22 Mask         */
#define GPIO_PORT_DIR5_DIRP23_Pos                             23                                                        /*!< GPIO_PORT DIR5: DIRP23 Position     */
#define GPIO_PORT_DIR5_DIRP23_Msk                             (0x01UL << GPIO_PORT_DIR5_DIRP23_Pos)                     /*!< GPIO_PORT DIR5: DIRP23 Mask         */
#define GPIO_PORT_DIR5_DIRP24_Pos                             24                                                        /*!< GPIO_PORT DIR5: DIRP24 Position     */
#define GPIO_PORT_DIR5_DIRP24_Msk                             (0x01UL << GPIO_PORT_DIR5_DIRP24_Pos)                     /*!< GPIO_PORT DIR5: DIRP24 Mask         */
#define GPIO_PORT_DIR5_DIRP25_Pos                             25                                                        /*!< GPIO_PORT DIR5: DIRP25 Position     */
#define GPIO_PORT_DIR5_DIRP25_Msk                             (0x01UL << GPIO_PORT_DIR5_DIRP25_Pos)                     /*!< GPIO_PORT DIR5: DIRP25 Mask         */
#define GPIO_PORT_DIR5_DIRP26_Pos                             26                                                        /*!< GPIO_PORT DIR5: DIRP26 Position     */
#define GPIO_PORT_DIR5_DIRP26_Msk                             (0x01UL << GPIO_PORT_DIR5_DIRP26_Pos)                     /*!< GPIO_PORT DIR5: DIRP26 Mask         */
#define GPIO_PORT_DIR5_DIRP27_Pos                             27                                                        /*!< GPIO_PORT DIR5: DIRP27 Position     */
#define GPIO_PORT_DIR5_DIRP27_Msk                             (0x01UL << GPIO_PORT_DIR5_DIRP27_Pos)                     /*!< GPIO_PORT DIR5: DIRP27 Mask         */
#define GPIO_PORT_DIR5_DIRP28_Pos                             28                                                        /*!< GPIO_PORT DIR5: DIRP28 Position     */
#define GPIO_PORT_DIR5_DIRP28_Msk                             (0x01UL << GPIO_PORT_DIR5_DIRP28_Pos)                     /*!< GPIO_PORT DIR5: DIRP28 Mask         */
#define GPIO_PORT_DIR5_DIRP29_Pos                             29                                                        /*!< GPIO_PORT DIR5: DIRP29 Position     */
#define GPIO_PORT_DIR5_DIRP29_Msk                             (0x01UL << GPIO_PORT_DIR5_DIRP29_Pos)                     /*!< GPIO_PORT DIR5: DIRP29 Mask         */
#define GPIO_PORT_DIR5_DIRP30_Pos                             30                                                        /*!< GPIO_PORT DIR5: DIRP30 Position     */
#define GPIO_PORT_DIR5_DIRP30_Msk                             (0x01UL << GPIO_PORT_DIR5_DIRP30_Pos)                     /*!< GPIO_PORT DIR5: DIRP30 Mask         */
#define GPIO_PORT_DIR5_DIRP31_Pos                             31                                                        /*!< GPIO_PORT DIR5: DIRP31 Position     */
#define GPIO_PORT_DIR5_DIRP31_Msk                             (0x01UL << GPIO_PORT_DIR5_DIRP31_Pos)                     /*!< GPIO_PORT DIR5: DIRP31 Mask         */

// -------------------------------------  GPIO_PORT_DIR6  -----------------------------------------
#define GPIO_PORT_DIR6_DIRP0_Pos                              0                                                         /*!< GPIO_PORT DIR6: DIRP0 Position      */
#define GPIO_PORT_DIR6_DIRP0_Msk                              (0x01UL << GPIO_PORT_DIR6_DIRP0_Pos)                      /*!< GPIO_PORT DIR6: DIRP0 Mask          */
#define GPIO_PORT_DIR6_DIRP1_Pos                              1                                                         /*!< GPIO_PORT DIR6: DIRP1 Position      */
#define GPIO_PORT_DIR6_DIRP1_Msk                              (0x01UL << GPIO_PORT_DIR6_DIRP1_Pos)                      /*!< GPIO_PORT DIR6: DIRP1 Mask          */
#define GPIO_PORT_DIR6_DIRP2_Pos                              2                                                         /*!< GPIO_PORT DIR6: DIRP2 Position      */
#define GPIO_PORT_DIR6_DIRP2_Msk                              (0x01UL << GPIO_PORT_DIR6_DIRP2_Pos)                      /*!< GPIO_PORT DIR6: DIRP2 Mask          */
#define GPIO_PORT_DIR6_DIRP3_Pos                              3                                                         /*!< GPIO_PORT DIR6: DIRP3 Position      */
#define GPIO_PORT_DIR6_DIRP3_Msk                              (0x01UL << GPIO_PORT_DIR6_DIRP3_Pos)                      /*!< GPIO_PORT DIR6: DIRP3 Mask          */
#define GPIO_PORT_DIR6_DIRP4_Pos                              4                                                         /*!< GPIO_PORT DIR6: DIRP4 Position      */
#define GPIO_PORT_DIR6_DIRP4_Msk                              (0x01UL << GPIO_PORT_DIR6_DIRP4_Pos)                      /*!< GPIO_PORT DIR6: DIRP4 Mask          */
#define GPIO_PORT_DIR6_DIRP5_Pos                              5                                                         /*!< GPIO_PORT DIR6: DIRP5 Position      */
#define GPIO_PORT_DIR6_DIRP5_Msk                              (0x01UL << GPIO_PORT_DIR6_DIRP5_Pos)                      /*!< GPIO_PORT DIR6: DIRP5 Mask          */
#define GPIO_PORT_DIR6_DIRP6_Pos                              6                                                         /*!< GPIO_PORT DIR6: DIRP6 Position      */
#define GPIO_PORT_DIR6_DIRP6_Msk                              (0x01UL << GPIO_PORT_DIR6_DIRP6_Pos)                      /*!< GPIO_PORT DIR6: DIRP6 Mask          */
#define GPIO_PORT_DIR6_DIRP7_Pos                              7                                                         /*!< GPIO_PORT DIR6: DIRP7 Position      */
#define GPIO_PORT_DIR6_DIRP7_Msk                              (0x01UL << GPIO_PORT_DIR6_DIRP7_Pos)                      /*!< GPIO_PORT DIR6: DIRP7 Mask          */
#define GPIO_PORT_DIR6_DIRP8_Pos                              8                                                         /*!< GPIO_PORT DIR6: DIRP8 Position      */
#define GPIO_PORT_DIR6_DIRP8_Msk                              (0x01UL << GPIO_PORT_DIR6_DIRP8_Pos)                      /*!< GPIO_PORT DIR6: DIRP8 Mask          */
#define GPIO_PORT_DIR6_DIRP9_Pos                              9                                                         /*!< GPIO_PORT DIR6: DIRP9 Position      */
#define GPIO_PORT_DIR6_DIRP9_Msk                              (0x01UL << GPIO_PORT_DIR6_DIRP9_Pos)                      /*!< GPIO_PORT DIR6: DIRP9 Mask          */
#define GPIO_PORT_DIR6_DIRP10_Pos                             10                                                        /*!< GPIO_PORT DIR6: DIRP10 Position     */
#define GPIO_PORT_DIR6_DIRP10_Msk                             (0x01UL << GPIO_PORT_DIR6_DIRP10_Pos)                     /*!< GPIO_PORT DIR6: DIRP10 Mask         */
#define GPIO_PORT_DIR6_DIRP11_Pos                             11                                                        /*!< GPIO_PORT DIR6: DIRP11 Position     */
#define GPIO_PORT_DIR6_DIRP11_Msk                             (0x01UL << GPIO_PORT_DIR6_DIRP11_Pos)                     /*!< GPIO_PORT DIR6: DIRP11 Mask         */
#define GPIO_PORT_DIR6_DIRP12_Pos                             12                                                        /*!< GPIO_PORT DIR6: DIRP12 Position     */
#define GPIO_PORT_DIR6_DIRP12_Msk                             (0x01UL << GPIO_PORT_DIR6_DIRP12_Pos)                     /*!< GPIO_PORT DIR6: DIRP12 Mask         */
#define GPIO_PORT_DIR6_DIRP13_Pos                             13                                                        /*!< GPIO_PORT DIR6: DIRP13 Position     */
#define GPIO_PORT_DIR6_DIRP13_Msk                             (0x01UL << GPIO_PORT_DIR6_DIRP13_Pos)                     /*!< GPIO_PORT DIR6: DIRP13 Mask         */
#define GPIO_PORT_DIR6_DIRP14_Pos                             14                                                        /*!< GPIO_PORT DIR6: DIRP14 Position     */
#define GPIO_PORT_DIR6_DIRP14_Msk                             (0x01UL << GPIO_PORT_DIR6_DIRP14_Pos)                     /*!< GPIO_PORT DIR6: DIRP14 Mask         */
#define GPIO_PORT_DIR6_DIRP15_Pos                             15                                                        /*!< GPIO_PORT DIR6: DIRP15 Position     */
#define GPIO_PORT_DIR6_DIRP15_Msk                             (0x01UL << GPIO_PORT_DIR6_DIRP15_Pos)                     /*!< GPIO_PORT DIR6: DIRP15 Mask         */
#define GPIO_PORT_DIR6_DIRP16_Pos                             16                                                        /*!< GPIO_PORT DIR6: DIRP16 Position     */
#define GPIO_PORT_DIR6_DIRP16_Msk                             (0x01UL << GPIO_PORT_DIR6_DIRP16_Pos)                     /*!< GPIO_PORT DIR6: DIRP16 Mask         */
#define GPIO_PORT_DIR6_DIRP17_Pos                             17                                                        /*!< GPIO_PORT DIR6: DIRP17 Position     */
#define GPIO_PORT_DIR6_DIRP17_Msk                             (0x01UL << GPIO_PORT_DIR6_DIRP17_Pos)                     /*!< GPIO_PORT DIR6: DIRP17 Mask         */
#define GPIO_PORT_DIR6_DIRP18_Pos                             18                                                        /*!< GPIO_PORT DIR6: DIRP18 Position     */
#define GPIO_PORT_DIR6_DIRP18_Msk                             (0x01UL << GPIO_PORT_DIR6_DIRP18_Pos)                     /*!< GPIO_PORT DIR6: DIRP18 Mask         */
#define GPIO_PORT_DIR6_DIRP19_Pos                             19                                                        /*!< GPIO_PORT DIR6: DIRP19 Position     */
#define GPIO_PORT_DIR6_DIRP19_Msk                             (0x01UL << GPIO_PORT_DIR6_DIRP19_Pos)                     /*!< GPIO_PORT DIR6: DIRP19 Mask         */
#define GPIO_PORT_DIR6_DIRP20_Pos                             20                                                        /*!< GPIO_PORT DIR6: DIRP20 Position     */
#define GPIO_PORT_DIR6_DIRP20_Msk                             (0x01UL << GPIO_PORT_DIR6_DIRP20_Pos)                     /*!< GPIO_PORT DIR6: DIRP20 Mask         */
#define GPIO_PORT_DIR6_DIRP21_Pos                             21                                                        /*!< GPIO_PORT DIR6: DIRP21 Position     */
#define GPIO_PORT_DIR6_DIRP21_Msk                             (0x01UL << GPIO_PORT_DIR6_DIRP21_Pos)                     /*!< GPIO_PORT DIR6: DIRP21 Mask         */
#define GPIO_PORT_DIR6_DIRP22_Pos                             22                                                        /*!< GPIO_PORT DIR6: DIRP22 Position     */
#define GPIO_PORT_DIR6_DIRP22_Msk                             (0x01UL << GPIO_PORT_DIR6_DIRP22_Pos)                     /*!< GPIO_PORT DIR6: DIRP22 Mask         */
#define GPIO_PORT_DIR6_DIRP23_Pos                             23                                                        /*!< GPIO_PORT DIR6: DIRP23 Position     */
#define GPIO_PORT_DIR6_DIRP23_Msk                             (0x01UL << GPIO_PORT_DIR6_DIRP23_Pos)                     /*!< GPIO_PORT DIR6: DIRP23 Mask         */
#define GPIO_PORT_DIR6_DIRP24_Pos                             24                                                        /*!< GPIO_PORT DIR6: DIRP24 Position     */
#define GPIO_PORT_DIR6_DIRP24_Msk                             (0x01UL << GPIO_PORT_DIR6_DIRP24_Pos)                     /*!< GPIO_PORT DIR6: DIRP24 Mask         */
#define GPIO_PORT_DIR6_DIRP25_Pos                             25                                                        /*!< GPIO_PORT DIR6: DIRP25 Position     */
#define GPIO_PORT_DIR6_DIRP25_Msk                             (0x01UL << GPIO_PORT_DIR6_DIRP25_Pos)                     /*!< GPIO_PORT DIR6: DIRP25 Mask         */
#define GPIO_PORT_DIR6_DIRP26_Pos                             26                                                        /*!< GPIO_PORT DIR6: DIRP26 Position     */
#define GPIO_PORT_DIR6_DIRP26_Msk                             (0x01UL << GPIO_PORT_DIR6_DIRP26_Pos)                     /*!< GPIO_PORT DIR6: DIRP26 Mask         */
#define GPIO_PORT_DIR6_DIRP27_Pos                             27                                                        /*!< GPIO_PORT DIR6: DIRP27 Position     */
#define GPIO_PORT_DIR6_DIRP27_Msk                             (0x01UL << GPIO_PORT_DIR6_DIRP27_Pos)                     /*!< GPIO_PORT DIR6: DIRP27 Mask         */
#define GPIO_PORT_DIR6_DIRP28_Pos                             28                                                        /*!< GPIO_PORT DIR6: DIRP28 Position     */
#define GPIO_PORT_DIR6_DIRP28_Msk                             (0x01UL << GPIO_PORT_DIR6_DIRP28_Pos)                     /*!< GPIO_PORT DIR6: DIRP28 Mask         */
#define GPIO_PORT_DIR6_DIRP29_Pos                             29                                                        /*!< GPIO_PORT DIR6: DIRP29 Position     */
#define GPIO_PORT_DIR6_DIRP29_Msk                             (0x01UL << GPIO_PORT_DIR6_DIRP29_Pos)                     /*!< GPIO_PORT DIR6: DIRP29 Mask         */
#define GPIO_PORT_DIR6_DIRP30_Pos                             30                                                        /*!< GPIO_PORT DIR6: DIRP30 Position     */
#define GPIO_PORT_DIR6_DIRP30_Msk                             (0x01UL << GPIO_PORT_DIR6_DIRP30_Pos)                     /*!< GPIO_PORT DIR6: DIRP30 Mask         */
#define GPIO_PORT_DIR6_DIRP31_Pos                             31                                                        /*!< GPIO_PORT DIR6: DIRP31 Position     */
#define GPIO_PORT_DIR6_DIRP31_Msk                             (0x01UL << GPIO_PORT_DIR6_DIRP31_Pos)                     /*!< GPIO_PORT DIR6: DIRP31 Mask         */

// -------------------------------------  GPIO_PORT_DIR7  -----------------------------------------
#define GPIO_PORT_DIR7_DIRP0_Pos                              0                                                         /*!< GPIO_PORT DIR7: DIRP0 Position      */
#define GPIO_PORT_DIR7_DIRP0_Msk                              (0x01UL << GPIO_PORT_DIR7_DIRP0_Pos)                      /*!< GPIO_PORT DIR7: DIRP0 Mask          */
#define GPIO_PORT_DIR7_DIRP1_Pos                              1                                                         /*!< GPIO_PORT DIR7: DIRP1 Position      */
#define GPIO_PORT_DIR7_DIRP1_Msk                              (0x01UL << GPIO_PORT_DIR7_DIRP1_Pos)                      /*!< GPIO_PORT DIR7: DIRP1 Mask          */
#define GPIO_PORT_DIR7_DIRP2_Pos                              2                                                         /*!< GPIO_PORT DIR7: DIRP2 Position      */
#define GPIO_PORT_DIR7_DIRP2_Msk                              (0x01UL << GPIO_PORT_DIR7_DIRP2_Pos)                      /*!< GPIO_PORT DIR7: DIRP2 Mask          */
#define GPIO_PORT_DIR7_DIRP3_Pos                              3                                                         /*!< GPIO_PORT DIR7: DIRP3 Position      */
#define GPIO_PORT_DIR7_DIRP3_Msk                              (0x01UL << GPIO_PORT_DIR7_DIRP3_Pos)                      /*!< GPIO_PORT DIR7: DIRP3 Mask          */
#define GPIO_PORT_DIR7_DIRP4_Pos                              4                                                         /*!< GPIO_PORT DIR7: DIRP4 Position      */
#define GPIO_PORT_DIR7_DIRP4_Msk                              (0x01UL << GPIO_PORT_DIR7_DIRP4_Pos)                      /*!< GPIO_PORT DIR7: DIRP4 Mask          */
#define GPIO_PORT_DIR7_DIRP5_Pos                              5                                                         /*!< GPIO_PORT DIR7: DIRP5 Position      */
#define GPIO_PORT_DIR7_DIRP5_Msk                              (0x01UL << GPIO_PORT_DIR7_DIRP5_Pos)                      /*!< GPIO_PORT DIR7: DIRP5 Mask          */
#define GPIO_PORT_DIR7_DIRP6_Pos                              6                                                         /*!< GPIO_PORT DIR7: DIRP6 Position      */
#define GPIO_PORT_DIR7_DIRP6_Msk                              (0x01UL << GPIO_PORT_DIR7_DIRP6_Pos)                      /*!< GPIO_PORT DIR7: DIRP6 Mask          */
#define GPIO_PORT_DIR7_DIRP7_Pos                              7                                                         /*!< GPIO_PORT DIR7: DIRP7 Position      */
#define GPIO_PORT_DIR7_DIRP7_Msk                              (0x01UL << GPIO_PORT_DIR7_DIRP7_Pos)                      /*!< GPIO_PORT DIR7: DIRP7 Mask          */
#define GPIO_PORT_DIR7_DIRP8_Pos                              8                                                         /*!< GPIO_PORT DIR7: DIRP8 Position      */
#define GPIO_PORT_DIR7_DIRP8_Msk                              (0x01UL << GPIO_PORT_DIR7_DIRP8_Pos)                      /*!< GPIO_PORT DIR7: DIRP8 Mask          */
#define GPIO_PORT_DIR7_DIRP9_Pos                              9                                                         /*!< GPIO_PORT DIR7: DIRP9 Position      */
#define GPIO_PORT_DIR7_DIRP9_Msk                              (0x01UL << GPIO_PORT_DIR7_DIRP9_Pos)                      /*!< GPIO_PORT DIR7: DIRP9 Mask          */
#define GPIO_PORT_DIR7_DIRP10_Pos                             10                                                        /*!< GPIO_PORT DIR7: DIRP10 Position     */
#define GPIO_PORT_DIR7_DIRP10_Msk                             (0x01UL << GPIO_PORT_DIR7_DIRP10_Pos)                     /*!< GPIO_PORT DIR7: DIRP10 Mask         */
#define GPIO_PORT_DIR7_DIRP11_Pos                             11                                                        /*!< GPIO_PORT DIR7: DIRP11 Position     */
#define GPIO_PORT_DIR7_DIRP11_Msk                             (0x01UL << GPIO_PORT_DIR7_DIRP11_Pos)                     /*!< GPIO_PORT DIR7: DIRP11 Mask         */
#define GPIO_PORT_DIR7_DIRP12_Pos                             12                                                        /*!< GPIO_PORT DIR7: DIRP12 Position     */
#define GPIO_PORT_DIR7_DIRP12_Msk                             (0x01UL << GPIO_PORT_DIR7_DIRP12_Pos)                     /*!< GPIO_PORT DIR7: DIRP12 Mask         */
#define GPIO_PORT_DIR7_DIRP13_Pos                             13                                                        /*!< GPIO_PORT DIR7: DIRP13 Position     */
#define GPIO_PORT_DIR7_DIRP13_Msk                             (0x01UL << GPIO_PORT_DIR7_DIRP13_Pos)                     /*!< GPIO_PORT DIR7: DIRP13 Mask         */
#define GPIO_PORT_DIR7_DIRP14_Pos                             14                                                        /*!< GPIO_PORT DIR7: DIRP14 Position     */
#define GPIO_PORT_DIR7_DIRP14_Msk                             (0x01UL << GPIO_PORT_DIR7_DIRP14_Pos)                     /*!< GPIO_PORT DIR7: DIRP14 Mask         */
#define GPIO_PORT_DIR7_DIRP15_Pos                             15                                                        /*!< GPIO_PORT DIR7: DIRP15 Position     */
#define GPIO_PORT_DIR7_DIRP15_Msk                             (0x01UL << GPIO_PORT_DIR7_DIRP15_Pos)                     /*!< GPIO_PORT DIR7: DIRP15 Mask         */
#define GPIO_PORT_DIR7_DIRP16_Pos                             16                                                        /*!< GPIO_PORT DIR7: DIRP16 Position     */
#define GPIO_PORT_DIR7_DIRP16_Msk                             (0x01UL << GPIO_PORT_DIR7_DIRP16_Pos)                     /*!< GPIO_PORT DIR7: DIRP16 Mask         */
#define GPIO_PORT_DIR7_DIRP17_Pos                             17                                                        /*!< GPIO_PORT DIR7: DIRP17 Position     */
#define GPIO_PORT_DIR7_DIRP17_Msk                             (0x01UL << GPIO_PORT_DIR7_DIRP17_Pos)                     /*!< GPIO_PORT DIR7: DIRP17 Mask         */
#define GPIO_PORT_DIR7_DIRP18_Pos                             18                                                        /*!< GPIO_PORT DIR7: DIRP18 Position     */
#define GPIO_PORT_DIR7_DIRP18_Msk                             (0x01UL << GPIO_PORT_DIR7_DIRP18_Pos)                     /*!< GPIO_PORT DIR7: DIRP18 Mask         */
#define GPIO_PORT_DIR7_DIRP19_Pos                             19                                                        /*!< GPIO_PORT DIR7: DIRP19 Position     */
#define GPIO_PORT_DIR7_DIRP19_Msk                             (0x01UL << GPIO_PORT_DIR7_DIRP19_Pos)                     /*!< GPIO_PORT DIR7: DIRP19 Mask         */
#define GPIO_PORT_DIR7_DIRP20_Pos                             20                                                        /*!< GPIO_PORT DIR7: DIRP20 Position     */
#define GPIO_PORT_DIR7_DIRP20_Msk                             (0x01UL << GPIO_PORT_DIR7_DIRP20_Pos)                     /*!< GPIO_PORT DIR7: DIRP20 Mask         */
#define GPIO_PORT_DIR7_DIRP21_Pos                             21                                                        /*!< GPIO_PORT DIR7: DIRP21 Position     */
#define GPIO_PORT_DIR7_DIRP21_Msk                             (0x01UL << GPIO_PORT_DIR7_DIRP21_Pos)                     /*!< GPIO_PORT DIR7: DIRP21 Mask         */
#define GPIO_PORT_DIR7_DIRP22_Pos                             22                                                        /*!< GPIO_PORT DIR7: DIRP22 Position     */
#define GPIO_PORT_DIR7_DIRP22_Msk                             (0x01UL << GPIO_PORT_DIR7_DIRP22_Pos)                     /*!< GPIO_PORT DIR7: DIRP22 Mask         */
#define GPIO_PORT_DIR7_DIRP23_Pos                             23                                                        /*!< GPIO_PORT DIR7: DIRP23 Position     */
#define GPIO_PORT_DIR7_DIRP23_Msk                             (0x01UL << GPIO_PORT_DIR7_DIRP23_Pos)                     /*!< GPIO_PORT DIR7: DIRP23 Mask         */
#define GPIO_PORT_DIR7_DIRP24_Pos                             24                                                        /*!< GPIO_PORT DIR7: DIRP24 Position     */
#define GPIO_PORT_DIR7_DIRP24_Msk                             (0x01UL << GPIO_PORT_DIR7_DIRP24_Pos)                     /*!< GPIO_PORT DIR7: DIRP24 Mask         */
#define GPIO_PORT_DIR7_DIRP25_Pos                             25                                                        /*!< GPIO_PORT DIR7: DIRP25 Position     */
#define GPIO_PORT_DIR7_DIRP25_Msk                             (0x01UL << GPIO_PORT_DIR7_DIRP25_Pos)                     /*!< GPIO_PORT DIR7: DIRP25 Mask         */
#define GPIO_PORT_DIR7_DIRP26_Pos                             26                                                        /*!< GPIO_PORT DIR7: DIRP26 Position     */
#define GPIO_PORT_DIR7_DIRP26_Msk                             (0x01UL << GPIO_PORT_DIR7_DIRP26_Pos)                     /*!< GPIO_PORT DIR7: DIRP26 Mask         */
#define GPIO_PORT_DIR7_DIRP27_Pos                             27                                                        /*!< GPIO_PORT DIR7: DIRP27 Position     */
#define GPIO_PORT_DIR7_DIRP27_Msk                             (0x01UL << GPIO_PORT_DIR7_DIRP27_Pos)                     /*!< GPIO_PORT DIR7: DIRP27 Mask         */
#define GPIO_PORT_DIR7_DIRP28_Pos                             28                                                        /*!< GPIO_PORT DIR7: DIRP28 Position     */
#define GPIO_PORT_DIR7_DIRP28_Msk                             (0x01UL << GPIO_PORT_DIR7_DIRP28_Pos)                     /*!< GPIO_PORT DIR7: DIRP28 Mask         */
#define GPIO_PORT_DIR7_DIRP29_Pos                             29                                                        /*!< GPIO_PORT DIR7: DIRP29 Position     */
#define GPIO_PORT_DIR7_DIRP29_Msk                             (0x01UL << GPIO_PORT_DIR7_DIRP29_Pos)                     /*!< GPIO_PORT DIR7: DIRP29 Mask         */
#define GPIO_PORT_DIR7_DIRP30_Pos                             30                                                        /*!< GPIO_PORT DIR7: DIRP30 Position     */
#define GPIO_PORT_DIR7_DIRP30_Msk                             (0x01UL << GPIO_PORT_DIR7_DIRP30_Pos)                     /*!< GPIO_PORT DIR7: DIRP30 Mask         */
#define GPIO_PORT_DIR7_DIRP31_Pos                             31                                                        /*!< GPIO_PORT DIR7: DIRP31 Position     */
#define GPIO_PORT_DIR7_DIRP31_Msk                             (0x01UL << GPIO_PORT_DIR7_DIRP31_Pos)                     /*!< GPIO_PORT DIR7: DIRP31 Mask         */

// -------------------------------------  GPIO_PORT_MASK0  ----------------------------------------
#define GPIO_PORT_MASK0_MASKP0_Pos                            0                                                         /*!< GPIO_PORT MASK0: MASKP0 Position    */
#define GPIO_PORT_MASK0_MASKP0_Msk                            (0x01UL << GPIO_PORT_MASK0_MASKP0_Pos)                    /*!< GPIO_PORT MASK0: MASKP0 Mask        */
#define GPIO_PORT_MASK0_MASKP1_Pos                            1                                                         /*!< GPIO_PORT MASK0: MASKP1 Position    */
#define GPIO_PORT_MASK0_MASKP1_Msk                            (0x01UL << GPIO_PORT_MASK0_MASKP1_Pos)                    /*!< GPIO_PORT MASK0: MASKP1 Mask        */
#define GPIO_PORT_MASK0_MASKP2_Pos                            2                                                         /*!< GPIO_PORT MASK0: MASKP2 Position    */
#define GPIO_PORT_MASK0_MASKP2_Msk                            (0x01UL << GPIO_PORT_MASK0_MASKP2_Pos)                    /*!< GPIO_PORT MASK0: MASKP2 Mask        */
#define GPIO_PORT_MASK0_MASKP3_Pos                            3                                                         /*!< GPIO_PORT MASK0: MASKP3 Position    */
#define GPIO_PORT_MASK0_MASKP3_Msk                            (0x01UL << GPIO_PORT_MASK0_MASKP3_Pos)                    /*!< GPIO_PORT MASK0: MASKP3 Mask        */
#define GPIO_PORT_MASK0_MASKP4_Pos                            4                                                         /*!< GPIO_PORT MASK0: MASKP4 Position    */
#define GPIO_PORT_MASK0_MASKP4_Msk                            (0x01UL << GPIO_PORT_MASK0_MASKP4_Pos)                    /*!< GPIO_PORT MASK0: MASKP4 Mask        */
#define GPIO_PORT_MASK0_MASKP5_Pos                            5                                                         /*!< GPIO_PORT MASK0: MASKP5 Position    */
#define GPIO_PORT_MASK0_MASKP5_Msk                            (0x01UL << GPIO_PORT_MASK0_MASKP5_Pos)                    /*!< GPIO_PORT MASK0: MASKP5 Mask        */
#define GPIO_PORT_MASK0_MASKP6_Pos                            6                                                         /*!< GPIO_PORT MASK0: MASKP6 Position    */
#define GPIO_PORT_MASK0_MASKP6_Msk                            (0x01UL << GPIO_PORT_MASK0_MASKP6_Pos)                    /*!< GPIO_PORT MASK0: MASKP6 Mask        */
#define GPIO_PORT_MASK0_MASKP7_Pos                            7                                                         /*!< GPIO_PORT MASK0: MASKP7 Position    */
#define GPIO_PORT_MASK0_MASKP7_Msk                            (0x01UL << GPIO_PORT_MASK0_MASKP7_Pos)                    /*!< GPIO_PORT MASK0: MASKP7 Mask        */
#define GPIO_PORT_MASK0_MASKP8_Pos                            8                                                         /*!< GPIO_PORT MASK0: MASKP8 Position    */
#define GPIO_PORT_MASK0_MASKP8_Msk                            (0x01UL << GPIO_PORT_MASK0_MASKP8_Pos)                    /*!< GPIO_PORT MASK0: MASKP8 Mask        */
#define GPIO_PORT_MASK0_MASKP9_Pos                            9                                                         /*!< GPIO_PORT MASK0: MASKP9 Position    */
#define GPIO_PORT_MASK0_MASKP9_Msk                            (0x01UL << GPIO_PORT_MASK0_MASKP9_Pos)                    /*!< GPIO_PORT MASK0: MASKP9 Mask        */
#define GPIO_PORT_MASK0_MASKP10_Pos                           10                                                        /*!< GPIO_PORT MASK0: MASKP10 Position   */
#define GPIO_PORT_MASK0_MASKP10_Msk                           (0x01UL << GPIO_PORT_MASK0_MASKP10_Pos)                   /*!< GPIO_PORT MASK0: MASKP10 Mask       */
#define GPIO_PORT_MASK0_MASKP11_Pos                           11                                                        /*!< GPIO_PORT MASK0: MASKP11 Position   */
#define GPIO_PORT_MASK0_MASKP11_Msk                           (0x01UL << GPIO_PORT_MASK0_MASKP11_Pos)                   /*!< GPIO_PORT MASK0: MASKP11 Mask       */
#define GPIO_PORT_MASK0_MASKP12_Pos                           12                                                        /*!< GPIO_PORT MASK0: MASKP12 Position   */
#define GPIO_PORT_MASK0_MASKP12_Msk                           (0x01UL << GPIO_PORT_MASK0_MASKP12_Pos)                   /*!< GPIO_PORT MASK0: MASKP12 Mask       */
#define GPIO_PORT_MASK0_MASKP13_Pos                           13                                                        /*!< GPIO_PORT MASK0: MASKP13 Position   */
#define GPIO_PORT_MASK0_MASKP13_Msk                           (0x01UL << GPIO_PORT_MASK0_MASKP13_Pos)                   /*!< GPIO_PORT MASK0: MASKP13 Mask       */
#define GPIO_PORT_MASK0_MASKP14_Pos                           14                                                        /*!< GPIO_PORT MASK0: MASKP14 Position   */
#define GPIO_PORT_MASK0_MASKP14_Msk                           (0x01UL << GPIO_PORT_MASK0_MASKP14_Pos)                   /*!< GPIO_PORT MASK0: MASKP14 Mask       */
#define GPIO_PORT_MASK0_MASKP15_Pos                           15                                                        /*!< GPIO_PORT MASK0: MASKP15 Position   */
#define GPIO_PORT_MASK0_MASKP15_Msk                           (0x01UL << GPIO_PORT_MASK0_MASKP15_Pos)                   /*!< GPIO_PORT MASK0: MASKP15 Mask       */
#define GPIO_PORT_MASK0_MASKP16_Pos                           16                                                        /*!< GPIO_PORT MASK0: MASKP16 Position   */
#define GPIO_PORT_MASK0_MASKP16_Msk                           (0x01UL << GPIO_PORT_MASK0_MASKP16_Pos)                   /*!< GPIO_PORT MASK0: MASKP16 Mask       */
#define GPIO_PORT_MASK0_MASKP17_Pos                           17                                                        /*!< GPIO_PORT MASK0: MASKP17 Position   */
#define GPIO_PORT_MASK0_MASKP17_Msk                           (0x01UL << GPIO_PORT_MASK0_MASKP17_Pos)                   /*!< GPIO_PORT MASK0: MASKP17 Mask       */
#define GPIO_PORT_MASK0_MASKP18_Pos                           18                                                        /*!< GPIO_PORT MASK0: MASKP18 Position   */
#define GPIO_PORT_MASK0_MASKP18_Msk                           (0x01UL << GPIO_PORT_MASK0_MASKP18_Pos)                   /*!< GPIO_PORT MASK0: MASKP18 Mask       */
#define GPIO_PORT_MASK0_MASKP19_Pos                           19                                                        /*!< GPIO_PORT MASK0: MASKP19 Position   */
#define GPIO_PORT_MASK0_MASKP19_Msk                           (0x01UL << GPIO_PORT_MASK0_MASKP19_Pos)                   /*!< GPIO_PORT MASK0: MASKP19 Mask       */
#define GPIO_PORT_MASK0_MASKP20_Pos                           20                                                        /*!< GPIO_PORT MASK0: MASKP20 Position   */
#define GPIO_PORT_MASK0_MASKP20_Msk                           (0x01UL << GPIO_PORT_MASK0_MASKP20_Pos)                   /*!< GPIO_PORT MASK0: MASKP20 Mask       */
#define GPIO_PORT_MASK0_MASKP21_Pos                           21                                                        /*!< GPIO_PORT MASK0: MASKP21 Position   */
#define GPIO_PORT_MASK0_MASKP21_Msk                           (0x01UL << GPIO_PORT_MASK0_MASKP21_Pos)                   /*!< GPIO_PORT MASK0: MASKP21 Mask       */
#define GPIO_PORT_MASK0_MASKP22_Pos                           22                                                        /*!< GPIO_PORT MASK0: MASKP22 Position   */
#define GPIO_PORT_MASK0_MASKP22_Msk                           (0x01UL << GPIO_PORT_MASK0_MASKP22_Pos)                   /*!< GPIO_PORT MASK0: MASKP22 Mask       */
#define GPIO_PORT_MASK0_MASKP23_Pos                           23                                                        /*!< GPIO_PORT MASK0: MASKP23 Position   */
#define GPIO_PORT_MASK0_MASKP23_Msk                           (0x01UL << GPIO_PORT_MASK0_MASKP23_Pos)                   /*!< GPIO_PORT MASK0: MASKP23 Mask       */
#define GPIO_PORT_MASK0_MASKP24_Pos                           24                                                        /*!< GPIO_PORT MASK0: MASKP24 Position   */
#define GPIO_PORT_MASK0_MASKP24_Msk                           (0x01UL << GPIO_PORT_MASK0_MASKP24_Pos)                   /*!< GPIO_PORT MASK0: MASKP24 Mask       */
#define GPIO_PORT_MASK0_MASKP25_Pos                           25                                                        /*!< GPIO_PORT MASK0: MASKP25 Position   */
#define GPIO_PORT_MASK0_MASKP25_Msk                           (0x01UL << GPIO_PORT_MASK0_MASKP25_Pos)                   /*!< GPIO_PORT MASK0: MASKP25 Mask       */
#define GPIO_PORT_MASK0_MASKP26_Pos                           26                                                        /*!< GPIO_PORT MASK0: MASKP26 Position   */
#define GPIO_PORT_MASK0_MASKP26_Msk                           (0x01UL << GPIO_PORT_MASK0_MASKP26_Pos)                   /*!< GPIO_PORT MASK0: MASKP26 Mask       */
#define GPIO_PORT_MASK0_MASKP27_Pos                           27                                                        /*!< GPIO_PORT MASK0: MASKP27 Position   */
#define GPIO_PORT_MASK0_MASKP27_Msk                           (0x01UL << GPIO_PORT_MASK0_MASKP27_Pos)                   /*!< GPIO_PORT MASK0: MASKP27 Mask       */
#define GPIO_PORT_MASK0_MASKP28_Pos                           28                                                        /*!< GPIO_PORT MASK0: MASKP28 Position   */
#define GPIO_PORT_MASK0_MASKP28_Msk                           (0x01UL << GPIO_PORT_MASK0_MASKP28_Pos)                   /*!< GPIO_PORT MASK0: MASKP28 Mask       */
#define GPIO_PORT_MASK0_MASKP29_Pos                           29                                                        /*!< GPIO_PORT MASK0: MASKP29 Position   */
#define GPIO_PORT_MASK0_MASKP29_Msk                           (0x01UL << GPIO_PORT_MASK0_MASKP29_Pos)                   /*!< GPIO_PORT MASK0: MASKP29 Mask       */
#define GPIO_PORT_MASK0_MASKP30_Pos                           30                                                        /*!< GPIO_PORT MASK0: MASKP30 Position   */
#define GPIO_PORT_MASK0_MASKP30_Msk                           (0x01UL << GPIO_PORT_MASK0_MASKP30_Pos)                   /*!< GPIO_PORT MASK0: MASKP30 Mask       */
#define GPIO_PORT_MASK0_MASKP31_Pos                           31                                                        /*!< GPIO_PORT MASK0: MASKP31 Position   */
#define GPIO_PORT_MASK0_MASKP31_Msk                           (0x01UL << GPIO_PORT_MASK0_MASKP31_Pos)                   /*!< GPIO_PORT MASK0: MASKP31 Mask       */

// -------------------------------------  GPIO_PORT_MASK1  ----------------------------------------
#define GPIO_PORT_MASK1_MASKP0_Pos                            0                                                         /*!< GPIO_PORT MASK1: MASKP0 Position    */
#define GPIO_PORT_MASK1_MASKP0_Msk                            (0x01UL << GPIO_PORT_MASK1_MASKP0_Pos)                    /*!< GPIO_PORT MASK1: MASKP0 Mask        */
#define GPIO_PORT_MASK1_MASKP1_Pos                            1                                                         /*!< GPIO_PORT MASK1: MASKP1 Position    */
#define GPIO_PORT_MASK1_MASKP1_Msk                            (0x01UL << GPIO_PORT_MASK1_MASKP1_Pos)                    /*!< GPIO_PORT MASK1: MASKP1 Mask        */
#define GPIO_PORT_MASK1_MASKP2_Pos                            2                                                         /*!< GPIO_PORT MASK1: MASKP2 Position    */
#define GPIO_PORT_MASK1_MASKP2_Msk                            (0x01UL << GPIO_PORT_MASK1_MASKP2_Pos)                    /*!< GPIO_PORT MASK1: MASKP2 Mask        */
#define GPIO_PORT_MASK1_MASKP3_Pos                            3                                                         /*!< GPIO_PORT MASK1: MASKP3 Position    */
#define GPIO_PORT_MASK1_MASKP3_Msk                            (0x01UL << GPIO_PORT_MASK1_MASKP3_Pos)                    /*!< GPIO_PORT MASK1: MASKP3 Mask        */
#define GPIO_PORT_MASK1_MASKP4_Pos                            4                                                         /*!< GPIO_PORT MASK1: MASKP4 Position    */
#define GPIO_PORT_MASK1_MASKP4_Msk                            (0x01UL << GPIO_PORT_MASK1_MASKP4_Pos)                    /*!< GPIO_PORT MASK1: MASKP4 Mask        */
#define GPIO_PORT_MASK1_MASKP5_Pos                            5                                                         /*!< GPIO_PORT MASK1: MASKP5 Position    */
#define GPIO_PORT_MASK1_MASKP5_Msk                            (0x01UL << GPIO_PORT_MASK1_MASKP5_Pos)                    /*!< GPIO_PORT MASK1: MASKP5 Mask        */
#define GPIO_PORT_MASK1_MASKP6_Pos                            6                                                         /*!< GPIO_PORT MASK1: MASKP6 Position    */
#define GPIO_PORT_MASK1_MASKP6_Msk                            (0x01UL << GPIO_PORT_MASK1_MASKP6_Pos)                    /*!< GPIO_PORT MASK1: MASKP6 Mask        */
#define GPIO_PORT_MASK1_MASKP7_Pos                            7                                                         /*!< GPIO_PORT MASK1: MASKP7 Position    */
#define GPIO_PORT_MASK1_MASKP7_Msk                            (0x01UL << GPIO_PORT_MASK1_MASKP7_Pos)                    /*!< GPIO_PORT MASK1: MASKP7 Mask        */
#define GPIO_PORT_MASK1_MASKP8_Pos                            8                                                         /*!< GPIO_PORT MASK1: MASKP8 Position    */
#define GPIO_PORT_MASK1_MASKP8_Msk                            (0x01UL << GPIO_PORT_MASK1_MASKP8_Pos)                    /*!< GPIO_PORT MASK1: MASKP8 Mask        */
#define GPIO_PORT_MASK1_MASKP9_Pos                            9                                                         /*!< GPIO_PORT MASK1: MASKP9 Position    */
#define GPIO_PORT_MASK1_MASKP9_Msk                            (0x01UL << GPIO_PORT_MASK1_MASKP9_Pos)                    /*!< GPIO_PORT MASK1: MASKP9 Mask        */
#define GPIO_PORT_MASK1_MASKP10_Pos                           10                                                        /*!< GPIO_PORT MASK1: MASKP10 Position   */
#define GPIO_PORT_MASK1_MASKP10_Msk                           (0x01UL << GPIO_PORT_MASK1_MASKP10_Pos)                   /*!< GPIO_PORT MASK1: MASKP10 Mask       */
#define GPIO_PORT_MASK1_MASKP11_Pos                           11                                                        /*!< GPIO_PORT MASK1: MASKP11 Position   */
#define GPIO_PORT_MASK1_MASKP11_Msk                           (0x01UL << GPIO_PORT_MASK1_MASKP11_Pos)                   /*!< GPIO_PORT MASK1: MASKP11 Mask       */
#define GPIO_PORT_MASK1_MASKP12_Pos                           12                                                        /*!< GPIO_PORT MASK1: MASKP12 Position   */
#define GPIO_PORT_MASK1_MASKP12_Msk                           (0x01UL << GPIO_PORT_MASK1_MASKP12_Pos)                   /*!< GPIO_PORT MASK1: MASKP12 Mask       */
#define GPIO_PORT_MASK1_MASKP13_Pos                           13                                                        /*!< GPIO_PORT MASK1: MASKP13 Position   */
#define GPIO_PORT_MASK1_MASKP13_Msk                           (0x01UL << GPIO_PORT_MASK1_MASKP13_Pos)                   /*!< GPIO_PORT MASK1: MASKP13 Mask       */
#define GPIO_PORT_MASK1_MASKP14_Pos                           14                                                        /*!< GPIO_PORT MASK1: MASKP14 Position   */
#define GPIO_PORT_MASK1_MASKP14_Msk                           (0x01UL << GPIO_PORT_MASK1_MASKP14_Pos)                   /*!< GPIO_PORT MASK1: MASKP14 Mask       */
#define GPIO_PORT_MASK1_MASKP15_Pos                           15                                                        /*!< GPIO_PORT MASK1: MASKP15 Position   */
#define GPIO_PORT_MASK1_MASKP15_Msk                           (0x01UL << GPIO_PORT_MASK1_MASKP15_Pos)                   /*!< GPIO_PORT MASK1: MASKP15 Mask       */
#define GPIO_PORT_MASK1_MASKP16_Pos                           16                                                        /*!< GPIO_PORT MASK1: MASKP16 Position   */
#define GPIO_PORT_MASK1_MASKP16_Msk                           (0x01UL << GPIO_PORT_MASK1_MASKP16_Pos)                   /*!< GPIO_PORT MASK1: MASKP16 Mask       */
#define GPIO_PORT_MASK1_MASKP17_Pos                           17                                                        /*!< GPIO_PORT MASK1: MASKP17 Position   */
#define GPIO_PORT_MASK1_MASKP17_Msk                           (0x01UL << GPIO_PORT_MASK1_MASKP17_Pos)                   /*!< GPIO_PORT MASK1: MASKP17 Mask       */
#define GPIO_PORT_MASK1_MASKP18_Pos                           18                                                        /*!< GPIO_PORT MASK1: MASKP18 Position   */
#define GPIO_PORT_MASK1_MASKP18_Msk                           (0x01UL << GPIO_PORT_MASK1_MASKP18_Pos)                   /*!< GPIO_PORT MASK1: MASKP18 Mask       */
#define GPIO_PORT_MASK1_MASKP19_Pos                           19                                                        /*!< GPIO_PORT MASK1: MASKP19 Position   */
#define GPIO_PORT_MASK1_MASKP19_Msk                           (0x01UL << GPIO_PORT_MASK1_MASKP19_Pos)                   /*!< GPIO_PORT MASK1: MASKP19 Mask       */
#define GPIO_PORT_MASK1_MASKP20_Pos                           20                                                        /*!< GPIO_PORT MASK1: MASKP20 Position   */
#define GPIO_PORT_MASK1_MASKP20_Msk                           (0x01UL << GPIO_PORT_MASK1_MASKP20_Pos)                   /*!< GPIO_PORT MASK1: MASKP20 Mask       */
#define GPIO_PORT_MASK1_MASKP21_Pos                           21                                                        /*!< GPIO_PORT MASK1: MASKP21 Position   */
#define GPIO_PORT_MASK1_MASKP21_Msk                           (0x01UL << GPIO_PORT_MASK1_MASKP21_Pos)                   /*!< GPIO_PORT MASK1: MASKP21 Mask       */
#define GPIO_PORT_MASK1_MASKP22_Pos                           22                                                        /*!< GPIO_PORT MASK1: MASKP22 Position   */
#define GPIO_PORT_MASK1_MASKP22_Msk                           (0x01UL << GPIO_PORT_MASK1_MASKP22_Pos)                   /*!< GPIO_PORT MASK1: MASKP22 Mask       */
#define GPIO_PORT_MASK1_MASKP23_Pos                           23                                                        /*!< GPIO_PORT MASK1: MASKP23 Position   */
#define GPIO_PORT_MASK1_MASKP23_Msk                           (0x01UL << GPIO_PORT_MASK1_MASKP23_Pos)                   /*!< GPIO_PORT MASK1: MASKP23 Mask       */
#define GPIO_PORT_MASK1_MASKP24_Pos                           24                                                        /*!< GPIO_PORT MASK1: MASKP24 Position   */
#define GPIO_PORT_MASK1_MASKP24_Msk                           (0x01UL << GPIO_PORT_MASK1_MASKP24_Pos)                   /*!< GPIO_PORT MASK1: MASKP24 Mask       */
#define GPIO_PORT_MASK1_MASKP25_Pos                           25                                                        /*!< GPIO_PORT MASK1: MASKP25 Position   */
#define GPIO_PORT_MASK1_MASKP25_Msk                           (0x01UL << GPIO_PORT_MASK1_MASKP25_Pos)                   /*!< GPIO_PORT MASK1: MASKP25 Mask       */
#define GPIO_PORT_MASK1_MASKP26_Pos                           26                                                        /*!< GPIO_PORT MASK1: MASKP26 Position   */
#define GPIO_PORT_MASK1_MASKP26_Msk                           (0x01UL << GPIO_PORT_MASK1_MASKP26_Pos)                   /*!< GPIO_PORT MASK1: MASKP26 Mask       */
#define GPIO_PORT_MASK1_MASKP27_Pos                           27                                                        /*!< GPIO_PORT MASK1: MASKP27 Position   */
#define GPIO_PORT_MASK1_MASKP27_Msk                           (0x01UL << GPIO_PORT_MASK1_MASKP27_Pos)                   /*!< GPIO_PORT MASK1: MASKP27 Mask       */
#define GPIO_PORT_MASK1_MASKP28_Pos                           28                                                        /*!< GPIO_PORT MASK1: MASKP28 Position   */
#define GPIO_PORT_MASK1_MASKP28_Msk                           (0x01UL << GPIO_PORT_MASK1_MASKP28_Pos)                   /*!< GPIO_PORT MASK1: MASKP28 Mask       */
#define GPIO_PORT_MASK1_MASKP29_Pos                           29                                                        /*!< GPIO_PORT MASK1: MASKP29 Position   */
#define GPIO_PORT_MASK1_MASKP29_Msk                           (0x01UL << GPIO_PORT_MASK1_MASKP29_Pos)                   /*!< GPIO_PORT MASK1: MASKP29 Mask       */
#define GPIO_PORT_MASK1_MASKP30_Pos                           30                                                        /*!< GPIO_PORT MASK1: MASKP30 Position   */
#define GPIO_PORT_MASK1_MASKP30_Msk                           (0x01UL << GPIO_PORT_MASK1_MASKP30_Pos)                   /*!< GPIO_PORT MASK1: MASKP30 Mask       */
#define GPIO_PORT_MASK1_MASKP31_Pos                           31                                                        /*!< GPIO_PORT MASK1: MASKP31 Position   */
#define GPIO_PORT_MASK1_MASKP31_Msk                           (0x01UL << GPIO_PORT_MASK1_MASKP31_Pos)                   /*!< GPIO_PORT MASK1: MASKP31 Mask       */

// -------------------------------------  GPIO_PORT_MASK2  ----------------------------------------
#define GPIO_PORT_MASK2_MASKP0_Pos                            0                                                         /*!< GPIO_PORT MASK2: MASKP0 Position    */
#define GPIO_PORT_MASK2_MASKP0_Msk                            (0x01UL << GPIO_PORT_MASK2_MASKP0_Pos)                    /*!< GPIO_PORT MASK2: MASKP0 Mask        */
#define GPIO_PORT_MASK2_MASKP1_Pos                            1                                                         /*!< GPIO_PORT MASK2: MASKP1 Position    */
#define GPIO_PORT_MASK2_MASKP1_Msk                            (0x01UL << GPIO_PORT_MASK2_MASKP1_Pos)                    /*!< GPIO_PORT MASK2: MASKP1 Mask        */
#define GPIO_PORT_MASK2_MASKP2_Pos                            2                                                         /*!< GPIO_PORT MASK2: MASKP2 Position    */
#define GPIO_PORT_MASK2_MASKP2_Msk                            (0x01UL << GPIO_PORT_MASK2_MASKP2_Pos)                    /*!< GPIO_PORT MASK2: MASKP2 Mask        */
#define GPIO_PORT_MASK2_MASKP3_Pos                            3                                                         /*!< GPIO_PORT MASK2: MASKP3 Position    */
#define GPIO_PORT_MASK2_MASKP3_Msk                            (0x01UL << GPIO_PORT_MASK2_MASKP3_Pos)                    /*!< GPIO_PORT MASK2: MASKP3 Mask        */
#define GPIO_PORT_MASK2_MASKP4_Pos                            4                                                         /*!< GPIO_PORT MASK2: MASKP4 Position    */
#define GPIO_PORT_MASK2_MASKP4_Msk                            (0x01UL << GPIO_PORT_MASK2_MASKP4_Pos)                    /*!< GPIO_PORT MASK2: MASKP4 Mask        */
#define GPIO_PORT_MASK2_MASKP5_Pos                            5                                                         /*!< GPIO_PORT MASK2: MASKP5 Position    */
#define GPIO_PORT_MASK2_MASKP5_Msk                            (0x01UL << GPIO_PORT_MASK2_MASKP5_Pos)                    /*!< GPIO_PORT MASK2: MASKP5 Mask        */
#define GPIO_PORT_MASK2_MASKP6_Pos                            6                                                         /*!< GPIO_PORT MASK2: MASKP6 Position    */
#define GPIO_PORT_MASK2_MASKP6_Msk                            (0x01UL << GPIO_PORT_MASK2_MASKP6_Pos)                    /*!< GPIO_PORT MASK2: MASKP6 Mask        */
#define GPIO_PORT_MASK2_MASKP7_Pos                            7                                                         /*!< GPIO_PORT MASK2: MASKP7 Position    */
#define GPIO_PORT_MASK2_MASKP7_Msk                            (0x01UL << GPIO_PORT_MASK2_MASKP7_Pos)                    /*!< GPIO_PORT MASK2: MASKP7 Mask        */
#define GPIO_PORT_MASK2_MASKP8_Pos                            8                                                         /*!< GPIO_PORT MASK2: MASKP8 Position    */
#define GPIO_PORT_MASK2_MASKP8_Msk                            (0x01UL << GPIO_PORT_MASK2_MASKP8_Pos)                    /*!< GPIO_PORT MASK2: MASKP8 Mask        */
#define GPIO_PORT_MASK2_MASKP9_Pos                            9                                                         /*!< GPIO_PORT MASK2: MASKP9 Position    */
#define GPIO_PORT_MASK2_MASKP9_Msk                            (0x01UL << GPIO_PORT_MASK2_MASKP9_Pos)                    /*!< GPIO_PORT MASK2: MASKP9 Mask        */
#define GPIO_PORT_MASK2_MASKP10_Pos                           10                                                        /*!< GPIO_PORT MASK2: MASKP10 Position   */
#define GPIO_PORT_MASK2_MASKP10_Msk                           (0x01UL << GPIO_PORT_MASK2_MASKP10_Pos)                   /*!< GPIO_PORT MASK2: MASKP10 Mask       */
#define GPIO_PORT_MASK2_MASKP11_Pos                           11                                                        /*!< GPIO_PORT MASK2: MASKP11 Position   */
#define GPIO_PORT_MASK2_MASKP11_Msk                           (0x01UL << GPIO_PORT_MASK2_MASKP11_Pos)                   /*!< GPIO_PORT MASK2: MASKP11 Mask       */
#define GPIO_PORT_MASK2_MASKP12_Pos                           12                                                        /*!< GPIO_PORT MASK2: MASKP12 Position   */
#define GPIO_PORT_MASK2_MASKP12_Msk                           (0x01UL << GPIO_PORT_MASK2_MASKP12_Pos)                   /*!< GPIO_PORT MASK2: MASKP12 Mask       */
#define GPIO_PORT_MASK2_MASKP13_Pos                           13                                                        /*!< GPIO_PORT MASK2: MASKP13 Position   */
#define GPIO_PORT_MASK2_MASKP13_Msk                           (0x01UL << GPIO_PORT_MASK2_MASKP13_Pos)                   /*!< GPIO_PORT MASK2: MASKP13 Mask       */
#define GPIO_PORT_MASK2_MASKP14_Pos                           14                                                        /*!< GPIO_PORT MASK2: MASKP14 Position   */
#define GPIO_PORT_MASK2_MASKP14_Msk                           (0x01UL << GPIO_PORT_MASK2_MASKP14_Pos)                   /*!< GPIO_PORT MASK2: MASKP14 Mask       */
#define GPIO_PORT_MASK2_MASKP15_Pos                           15                                                        /*!< GPIO_PORT MASK2: MASKP15 Position   */
#define GPIO_PORT_MASK2_MASKP15_Msk                           (0x01UL << GPIO_PORT_MASK2_MASKP15_Pos)                   /*!< GPIO_PORT MASK2: MASKP15 Mask       */
#define GPIO_PORT_MASK2_MASKP16_Pos                           16                                                        /*!< GPIO_PORT MASK2: MASKP16 Position   */
#define GPIO_PORT_MASK2_MASKP16_Msk                           (0x01UL << GPIO_PORT_MASK2_MASKP16_Pos)                   /*!< GPIO_PORT MASK2: MASKP16 Mask       */
#define GPIO_PORT_MASK2_MASKP17_Pos                           17                                                        /*!< GPIO_PORT MASK2: MASKP17 Position   */
#define GPIO_PORT_MASK2_MASKP17_Msk                           (0x01UL << GPIO_PORT_MASK2_MASKP17_Pos)                   /*!< GPIO_PORT MASK2: MASKP17 Mask       */
#define GPIO_PORT_MASK2_MASKP18_Pos                           18                                                        /*!< GPIO_PORT MASK2: MASKP18 Position   */
#define GPIO_PORT_MASK2_MASKP18_Msk                           (0x01UL << GPIO_PORT_MASK2_MASKP18_Pos)                   /*!< GPIO_PORT MASK2: MASKP18 Mask       */
#define GPIO_PORT_MASK2_MASKP19_Pos                           19                                                        /*!< GPIO_PORT MASK2: MASKP19 Position   */
#define GPIO_PORT_MASK2_MASKP19_Msk                           (0x01UL << GPIO_PORT_MASK2_MASKP19_Pos)                   /*!< GPIO_PORT MASK2: MASKP19 Mask       */
#define GPIO_PORT_MASK2_MASKP20_Pos                           20                                                        /*!< GPIO_PORT MASK2: MASKP20 Position   */
#define GPIO_PORT_MASK2_MASKP20_Msk                           (0x01UL << GPIO_PORT_MASK2_MASKP20_Pos)                   /*!< GPIO_PORT MASK2: MASKP20 Mask       */
#define GPIO_PORT_MASK2_MASKP21_Pos                           21                                                        /*!< GPIO_PORT MASK2: MASKP21 Position   */
#define GPIO_PORT_MASK2_MASKP21_Msk                           (0x01UL << GPIO_PORT_MASK2_MASKP21_Pos)                   /*!< GPIO_PORT MASK2: MASKP21 Mask       */
#define GPIO_PORT_MASK2_MASKP22_Pos                           22                                                        /*!< GPIO_PORT MASK2: MASKP22 Position   */
#define GPIO_PORT_MASK2_MASKP22_Msk                           (0x01UL << GPIO_PORT_MASK2_MASKP22_Pos)                   /*!< GPIO_PORT MASK2: MASKP22 Mask       */
#define GPIO_PORT_MASK2_MASKP23_Pos                           23                                                        /*!< GPIO_PORT MASK2: MASKP23 Position   */
#define GPIO_PORT_MASK2_MASKP23_Msk                           (0x01UL << GPIO_PORT_MASK2_MASKP23_Pos)                   /*!< GPIO_PORT MASK2: MASKP23 Mask       */
#define GPIO_PORT_MASK2_MASKP24_Pos                           24                                                        /*!< GPIO_PORT MASK2: MASKP24 Position   */
#define GPIO_PORT_MASK2_MASKP24_Msk                           (0x01UL << GPIO_PORT_MASK2_MASKP24_Pos)                   /*!< GPIO_PORT MASK2: MASKP24 Mask       */
#define GPIO_PORT_MASK2_MASKP25_Pos                           25                                                        /*!< GPIO_PORT MASK2: MASKP25 Position   */
#define GPIO_PORT_MASK2_MASKP25_Msk                           (0x01UL << GPIO_PORT_MASK2_MASKP25_Pos)                   /*!< GPIO_PORT MASK2: MASKP25 Mask       */
#define GPIO_PORT_MASK2_MASKP26_Pos                           26                                                        /*!< GPIO_PORT MASK2: MASKP26 Position   */
#define GPIO_PORT_MASK2_MASKP26_Msk                           (0x01UL << GPIO_PORT_MASK2_MASKP26_Pos)                   /*!< GPIO_PORT MASK2: MASKP26 Mask       */
#define GPIO_PORT_MASK2_MASKP27_Pos                           27                                                        /*!< GPIO_PORT MASK2: MASKP27 Position   */
#define GPIO_PORT_MASK2_MASKP27_Msk                           (0x01UL << GPIO_PORT_MASK2_MASKP27_Pos)                   /*!< GPIO_PORT MASK2: MASKP27 Mask       */
#define GPIO_PORT_MASK2_MASKP28_Pos                           28                                                        /*!< GPIO_PORT MASK2: MASKP28 Position   */
#define GPIO_PORT_MASK2_MASKP28_Msk                           (0x01UL << GPIO_PORT_MASK2_MASKP28_Pos)                   /*!< GPIO_PORT MASK2: MASKP28 Mask       */
#define GPIO_PORT_MASK2_MASKP29_Pos                           29                                                        /*!< GPIO_PORT MASK2: MASKP29 Position   */
#define GPIO_PORT_MASK2_MASKP29_Msk                           (0x01UL << GPIO_PORT_MASK2_MASKP29_Pos)                   /*!< GPIO_PORT MASK2: MASKP29 Mask       */
#define GPIO_PORT_MASK2_MASKP30_Pos                           30                                                        /*!< GPIO_PORT MASK2: MASKP30 Position   */
#define GPIO_PORT_MASK2_MASKP30_Msk                           (0x01UL << GPIO_PORT_MASK2_MASKP30_Pos)                   /*!< GPIO_PORT MASK2: MASKP30 Mask       */
#define GPIO_PORT_MASK2_MASKP31_Pos                           31                                                        /*!< GPIO_PORT MASK2: MASKP31 Position   */
#define GPIO_PORT_MASK2_MASKP31_Msk                           (0x01UL << GPIO_PORT_MASK2_MASKP31_Pos)                   /*!< GPIO_PORT MASK2: MASKP31 Mask       */

// -------------------------------------  GPIO_PORT_MASK3  ----------------------------------------
#define GPIO_PORT_MASK3_MASKP0_Pos                            0                                                         /*!< GPIO_PORT MASK3: MASKP0 Position    */
#define GPIO_PORT_MASK3_MASKP0_Msk                            (0x01UL << GPIO_PORT_MASK3_MASKP0_Pos)                    /*!< GPIO_PORT MASK3: MASKP0 Mask        */
#define GPIO_PORT_MASK3_MASKP1_Pos                            1                                                         /*!< GPIO_PORT MASK3: MASKP1 Position    */
#define GPIO_PORT_MASK3_MASKP1_Msk                            (0x01UL << GPIO_PORT_MASK3_MASKP1_Pos)                    /*!< GPIO_PORT MASK3: MASKP1 Mask        */
#define GPIO_PORT_MASK3_MASKP2_Pos                            2                                                         /*!< GPIO_PORT MASK3: MASKP2 Position    */
#define GPIO_PORT_MASK3_MASKP2_Msk                            (0x01UL << GPIO_PORT_MASK3_MASKP2_Pos)                    /*!< GPIO_PORT MASK3: MASKP2 Mask        */
#define GPIO_PORT_MASK3_MASKP3_Pos                            3                                                         /*!< GPIO_PORT MASK3: MASKP3 Position    */
#define GPIO_PORT_MASK3_MASKP3_Msk                            (0x01UL << GPIO_PORT_MASK3_MASKP3_Pos)                    /*!< GPIO_PORT MASK3: MASKP3 Mask        */
#define GPIO_PORT_MASK3_MASKP4_Pos                            4                                                         /*!< GPIO_PORT MASK3: MASKP4 Position    */
#define GPIO_PORT_MASK3_MASKP4_Msk                            (0x01UL << GPIO_PORT_MASK3_MASKP4_Pos)                    /*!< GPIO_PORT MASK3: MASKP4 Mask        */
#define GPIO_PORT_MASK3_MASKP5_Pos                            5                                                         /*!< GPIO_PORT MASK3: MASKP5 Position    */
#define GPIO_PORT_MASK3_MASKP5_Msk                            (0x01UL << GPIO_PORT_MASK3_MASKP5_Pos)                    /*!< GPIO_PORT MASK3: MASKP5 Mask        */
#define GPIO_PORT_MASK3_MASKP6_Pos                            6                                                         /*!< GPIO_PORT MASK3: MASKP6 Position    */
#define GPIO_PORT_MASK3_MASKP6_Msk                            (0x01UL << GPIO_PORT_MASK3_MASKP6_Pos)                    /*!< GPIO_PORT MASK3: MASKP6 Mask        */
#define GPIO_PORT_MASK3_MASKP7_Pos                            7                                                         /*!< GPIO_PORT MASK3: MASKP7 Position    */
#define GPIO_PORT_MASK3_MASKP7_Msk                            (0x01UL << GPIO_PORT_MASK3_MASKP7_Pos)                    /*!< GPIO_PORT MASK3: MASKP7 Mask        */
#define GPIO_PORT_MASK3_MASKP8_Pos                            8                                                         /*!< GPIO_PORT MASK3: MASKP8 Position    */
#define GPIO_PORT_MASK3_MASKP8_Msk                            (0x01UL << GPIO_PORT_MASK3_MASKP8_Pos)                    /*!< GPIO_PORT MASK3: MASKP8 Mask        */
#define GPIO_PORT_MASK3_MASKP9_Pos                            9                                                         /*!< GPIO_PORT MASK3: MASKP9 Position    */
#define GPIO_PORT_MASK3_MASKP9_Msk                            (0x01UL << GPIO_PORT_MASK3_MASKP9_Pos)                    /*!< GPIO_PORT MASK3: MASKP9 Mask        */
#define GPIO_PORT_MASK3_MASKP10_Pos                           10                                                        /*!< GPIO_PORT MASK3: MASKP10 Position   */
#define GPIO_PORT_MASK3_MASKP10_Msk                           (0x01UL << GPIO_PORT_MASK3_MASKP10_Pos)                   /*!< GPIO_PORT MASK3: MASKP10 Mask       */
#define GPIO_PORT_MASK3_MASKP11_Pos                           11                                                        /*!< GPIO_PORT MASK3: MASKP11 Position   */
#define GPIO_PORT_MASK3_MASKP11_Msk                           (0x01UL << GPIO_PORT_MASK3_MASKP11_Pos)                   /*!< GPIO_PORT MASK3: MASKP11 Mask       */
#define GPIO_PORT_MASK3_MASKP12_Pos                           12                                                        /*!< GPIO_PORT MASK3: MASKP12 Position   */
#define GPIO_PORT_MASK3_MASKP12_Msk                           (0x01UL << GPIO_PORT_MASK3_MASKP12_Pos)                   /*!< GPIO_PORT MASK3: MASKP12 Mask       */
#define GPIO_PORT_MASK3_MASKP13_Pos                           13                                                        /*!< GPIO_PORT MASK3: MASKP13 Position   */
#define GPIO_PORT_MASK3_MASKP13_Msk                           (0x01UL << GPIO_PORT_MASK3_MASKP13_Pos)                   /*!< GPIO_PORT MASK3: MASKP13 Mask       */
#define GPIO_PORT_MASK3_MASKP14_Pos                           14                                                        /*!< GPIO_PORT MASK3: MASKP14 Position   */
#define GPIO_PORT_MASK3_MASKP14_Msk                           (0x01UL << GPIO_PORT_MASK3_MASKP14_Pos)                   /*!< GPIO_PORT MASK3: MASKP14 Mask       */
#define GPIO_PORT_MASK3_MASKP15_Pos                           15                                                        /*!< GPIO_PORT MASK3: MASKP15 Position   */
#define GPIO_PORT_MASK3_MASKP15_Msk                           (0x01UL << GPIO_PORT_MASK3_MASKP15_Pos)                   /*!< GPIO_PORT MASK3: MASKP15 Mask       */
#define GPIO_PORT_MASK3_MASKP16_Pos                           16                                                        /*!< GPIO_PORT MASK3: MASKP16 Position   */
#define GPIO_PORT_MASK3_MASKP16_Msk                           (0x01UL << GPIO_PORT_MASK3_MASKP16_Pos)                   /*!< GPIO_PORT MASK3: MASKP16 Mask       */
#define GPIO_PORT_MASK3_MASKP17_Pos                           17                                                        /*!< GPIO_PORT MASK3: MASKP17 Position   */
#define GPIO_PORT_MASK3_MASKP17_Msk                           (0x01UL << GPIO_PORT_MASK3_MASKP17_Pos)                   /*!< GPIO_PORT MASK3: MASKP17 Mask       */
#define GPIO_PORT_MASK3_MASKP18_Pos                           18                                                        /*!< GPIO_PORT MASK3: MASKP18 Position   */
#define GPIO_PORT_MASK3_MASKP18_Msk                           (0x01UL << GPIO_PORT_MASK3_MASKP18_Pos)                   /*!< GPIO_PORT MASK3: MASKP18 Mask       */
#define GPIO_PORT_MASK3_MASKP19_Pos                           19                                                        /*!< GPIO_PORT MASK3: MASKP19 Position   */
#define GPIO_PORT_MASK3_MASKP19_Msk                           (0x01UL << GPIO_PORT_MASK3_MASKP19_Pos)                   /*!< GPIO_PORT MASK3: MASKP19 Mask       */
#define GPIO_PORT_MASK3_MASKP20_Pos                           20                                                        /*!< GPIO_PORT MASK3: MASKP20 Position   */
#define GPIO_PORT_MASK3_MASKP20_Msk                           (0x01UL << GPIO_PORT_MASK3_MASKP20_Pos)                   /*!< GPIO_PORT MASK3: MASKP20 Mask       */
#define GPIO_PORT_MASK3_MASKP21_Pos                           21                                                        /*!< GPIO_PORT MASK3: MASKP21 Position   */
#define GPIO_PORT_MASK3_MASKP21_Msk                           (0x01UL << GPIO_PORT_MASK3_MASKP21_Pos)                   /*!< GPIO_PORT MASK3: MASKP21 Mask       */
#define GPIO_PORT_MASK3_MASKP22_Pos                           22                                                        /*!< GPIO_PORT MASK3: MASKP22 Position   */
#define GPIO_PORT_MASK3_MASKP22_Msk                           (0x01UL << GPIO_PORT_MASK3_MASKP22_Pos)                   /*!< GPIO_PORT MASK3: MASKP22 Mask       */
#define GPIO_PORT_MASK3_MASKP23_Pos                           23                                                        /*!< GPIO_PORT MASK3: MASKP23 Position   */
#define GPIO_PORT_MASK3_MASKP23_Msk                           (0x01UL << GPIO_PORT_MASK3_MASKP23_Pos)                   /*!< GPIO_PORT MASK3: MASKP23 Mask       */
#define GPIO_PORT_MASK3_MASKP24_Pos                           24                                                        /*!< GPIO_PORT MASK3: MASKP24 Position   */
#define GPIO_PORT_MASK3_MASKP24_Msk                           (0x01UL << GPIO_PORT_MASK3_MASKP24_Pos)                   /*!< GPIO_PORT MASK3: MASKP24 Mask       */
#define GPIO_PORT_MASK3_MASKP25_Pos                           25                                                        /*!< GPIO_PORT MASK3: MASKP25 Position   */
#define GPIO_PORT_MASK3_MASKP25_Msk                           (0x01UL << GPIO_PORT_MASK3_MASKP25_Pos)                   /*!< GPIO_PORT MASK3: MASKP25 Mask       */
#define GPIO_PORT_MASK3_MASKP26_Pos                           26                                                        /*!< GPIO_PORT MASK3: MASKP26 Position   */
#define GPIO_PORT_MASK3_MASKP26_Msk                           (0x01UL << GPIO_PORT_MASK3_MASKP26_Pos)                   /*!< GPIO_PORT MASK3: MASKP26 Mask       */
#define GPIO_PORT_MASK3_MASKP27_Pos                           27                                                        /*!< GPIO_PORT MASK3: MASKP27 Position   */
#define GPIO_PORT_MASK3_MASKP27_Msk                           (0x01UL << GPIO_PORT_MASK3_MASKP27_Pos)                   /*!< GPIO_PORT MASK3: MASKP27 Mask       */
#define GPIO_PORT_MASK3_MASKP28_Pos                           28                                                        /*!< GPIO_PORT MASK3: MASKP28 Position   */
#define GPIO_PORT_MASK3_MASKP28_Msk                           (0x01UL << GPIO_PORT_MASK3_MASKP28_Pos)                   /*!< GPIO_PORT MASK3: MASKP28 Mask       */
#define GPIO_PORT_MASK3_MASKP29_Pos                           29                                                        /*!< GPIO_PORT MASK3: MASKP29 Position   */
#define GPIO_PORT_MASK3_MASKP29_Msk                           (0x01UL << GPIO_PORT_MASK3_MASKP29_Pos)                   /*!< GPIO_PORT MASK3: MASKP29 Mask       */
#define GPIO_PORT_MASK3_MASKP30_Pos                           30                                                        /*!< GPIO_PORT MASK3: MASKP30 Position   */
#define GPIO_PORT_MASK3_MASKP30_Msk                           (0x01UL << GPIO_PORT_MASK3_MASKP30_Pos)                   /*!< GPIO_PORT MASK3: MASKP30 Mask       */
#define GPIO_PORT_MASK3_MASKP31_Pos                           31                                                        /*!< GPIO_PORT MASK3: MASKP31 Position   */
#define GPIO_PORT_MASK3_MASKP31_Msk                           (0x01UL << GPIO_PORT_MASK3_MASKP31_Pos)                   /*!< GPIO_PORT MASK3: MASKP31 Mask       */

// -------------------------------------  GPIO_PORT_MASK4  ----------------------------------------
#define GPIO_PORT_MASK4_MASKP0_Pos                            0                                                         /*!< GPIO_PORT MASK4: MASKP0 Position    */
#define GPIO_PORT_MASK4_MASKP0_Msk                            (0x01UL << GPIO_PORT_MASK4_MASKP0_Pos)                    /*!< GPIO_PORT MASK4: MASKP0 Mask        */
#define GPIO_PORT_MASK4_MASKP1_Pos                            1                                                         /*!< GPIO_PORT MASK4: MASKP1 Position    */
#define GPIO_PORT_MASK4_MASKP1_Msk                            (0x01UL << GPIO_PORT_MASK4_MASKP1_Pos)                    /*!< GPIO_PORT MASK4: MASKP1 Mask        */
#define GPIO_PORT_MASK4_MASKP2_Pos                            2                                                         /*!< GPIO_PORT MASK4: MASKP2 Position    */
#define GPIO_PORT_MASK4_MASKP2_Msk                            (0x01UL << GPIO_PORT_MASK4_MASKP2_Pos)                    /*!< GPIO_PORT MASK4: MASKP2 Mask        */
#define GPIO_PORT_MASK4_MASKP3_Pos                            3                                                         /*!< GPIO_PORT MASK4: MASKP3 Position    */
#define GPIO_PORT_MASK4_MASKP3_Msk                            (0x01UL << GPIO_PORT_MASK4_MASKP3_Pos)                    /*!< GPIO_PORT MASK4: MASKP3 Mask        */
#define GPIO_PORT_MASK4_MASKP4_Pos                            4                                                         /*!< GPIO_PORT MASK4: MASKP4 Position    */
#define GPIO_PORT_MASK4_MASKP4_Msk                            (0x01UL << GPIO_PORT_MASK4_MASKP4_Pos)                    /*!< GPIO_PORT MASK4: MASKP4 Mask        */
#define GPIO_PORT_MASK4_MASKP5_Pos                            5                                                         /*!< GPIO_PORT MASK4: MASKP5 Position    */
#define GPIO_PORT_MASK4_MASKP5_Msk                            (0x01UL << GPIO_PORT_MASK4_MASKP5_Pos)                    /*!< GPIO_PORT MASK4: MASKP5 Mask        */
#define GPIO_PORT_MASK4_MASKP6_Pos                            6                                                         /*!< GPIO_PORT MASK4: MASKP6 Position    */
#define GPIO_PORT_MASK4_MASKP6_Msk                            (0x01UL << GPIO_PORT_MASK4_MASKP6_Pos)                    /*!< GPIO_PORT MASK4: MASKP6 Mask        */
#define GPIO_PORT_MASK4_MASKP7_Pos                            7                                                         /*!< GPIO_PORT MASK4: MASKP7 Position    */
#define GPIO_PORT_MASK4_MASKP7_Msk                            (0x01UL << GPIO_PORT_MASK4_MASKP7_Pos)                    /*!< GPIO_PORT MASK4: MASKP7 Mask        */
#define GPIO_PORT_MASK4_MASKP8_Pos                            8                                                         /*!< GPIO_PORT MASK4: MASKP8 Position    */
#define GPIO_PORT_MASK4_MASKP8_Msk                            (0x01UL << GPIO_PORT_MASK4_MASKP8_Pos)                    /*!< GPIO_PORT MASK4: MASKP8 Mask        */
#define GPIO_PORT_MASK4_MASKP9_Pos                            9                                                         /*!< GPIO_PORT MASK4: MASKP9 Position    */
#define GPIO_PORT_MASK4_MASKP9_Msk                            (0x01UL << GPIO_PORT_MASK4_MASKP9_Pos)                    /*!< GPIO_PORT MASK4: MASKP9 Mask        */
#define GPIO_PORT_MASK4_MASKP10_Pos                           10                                                        /*!< GPIO_PORT MASK4: MASKP10 Position   */
#define GPIO_PORT_MASK4_MASKP10_Msk                           (0x01UL << GPIO_PORT_MASK4_MASKP10_Pos)                   /*!< GPIO_PORT MASK4: MASKP10 Mask       */
#define GPIO_PORT_MASK4_MASKP11_Pos                           11                                                        /*!< GPIO_PORT MASK4: MASKP11 Position   */
#define GPIO_PORT_MASK4_MASKP11_Msk                           (0x01UL << GPIO_PORT_MASK4_MASKP11_Pos)                   /*!< GPIO_PORT MASK4: MASKP11 Mask       */
#define GPIO_PORT_MASK4_MASKP12_Pos                           12                                                        /*!< GPIO_PORT MASK4: MASKP12 Position   */
#define GPIO_PORT_MASK4_MASKP12_Msk                           (0x01UL << GPIO_PORT_MASK4_MASKP12_Pos)                   /*!< GPIO_PORT MASK4: MASKP12 Mask       */
#define GPIO_PORT_MASK4_MASKP13_Pos                           13                                                        /*!< GPIO_PORT MASK4: MASKP13 Position   */
#define GPIO_PORT_MASK4_MASKP13_Msk                           (0x01UL << GPIO_PORT_MASK4_MASKP13_Pos)                   /*!< GPIO_PORT MASK4: MASKP13 Mask       */
#define GPIO_PORT_MASK4_MASKP14_Pos                           14                                                        /*!< GPIO_PORT MASK4: MASKP14 Position   */
#define GPIO_PORT_MASK4_MASKP14_Msk                           (0x01UL << GPIO_PORT_MASK4_MASKP14_Pos)                   /*!< GPIO_PORT MASK4: MASKP14 Mask       */
#define GPIO_PORT_MASK4_MASKP15_Pos                           15                                                        /*!< GPIO_PORT MASK4: MASKP15 Position   */
#define GPIO_PORT_MASK4_MASKP15_Msk                           (0x01UL << GPIO_PORT_MASK4_MASKP15_Pos)                   /*!< GPIO_PORT MASK4: MASKP15 Mask       */
#define GPIO_PORT_MASK4_MASKP16_Pos                           16                                                        /*!< GPIO_PORT MASK4: MASKP16 Position   */
#define GPIO_PORT_MASK4_MASKP16_Msk                           (0x01UL << GPIO_PORT_MASK4_MASKP16_Pos)                   /*!< GPIO_PORT MASK4: MASKP16 Mask       */
#define GPIO_PORT_MASK4_MASKP17_Pos                           17                                                        /*!< GPIO_PORT MASK4: MASKP17 Position   */
#define GPIO_PORT_MASK4_MASKP17_Msk                           (0x01UL << GPIO_PORT_MASK4_MASKP17_Pos)                   /*!< GPIO_PORT MASK4: MASKP17 Mask       */
#define GPIO_PORT_MASK4_MASKP18_Pos                           18                                                        /*!< GPIO_PORT MASK4: MASKP18 Position   */
#define GPIO_PORT_MASK4_MASKP18_Msk                           (0x01UL << GPIO_PORT_MASK4_MASKP18_Pos)                   /*!< GPIO_PORT MASK4: MASKP18 Mask       */
#define GPIO_PORT_MASK4_MASKP19_Pos                           19                                                        /*!< GPIO_PORT MASK4: MASKP19 Position   */
#define GPIO_PORT_MASK4_MASKP19_Msk                           (0x01UL << GPIO_PORT_MASK4_MASKP19_Pos)                   /*!< GPIO_PORT MASK4: MASKP19 Mask       */
#define GPIO_PORT_MASK4_MASKP20_Pos                           20                                                        /*!< GPIO_PORT MASK4: MASKP20 Position   */
#define GPIO_PORT_MASK4_MASKP20_Msk                           (0x01UL << GPIO_PORT_MASK4_MASKP20_Pos)                   /*!< GPIO_PORT MASK4: MASKP20 Mask       */
#define GPIO_PORT_MASK4_MASKP21_Pos                           21                                                        /*!< GPIO_PORT MASK4: MASKP21 Position   */
#define GPIO_PORT_MASK4_MASKP21_Msk                           (0x01UL << GPIO_PORT_MASK4_MASKP21_Pos)                   /*!< GPIO_PORT MASK4: MASKP21 Mask       */
#define GPIO_PORT_MASK4_MASKP22_Pos                           22                                                        /*!< GPIO_PORT MASK4: MASKP22 Position   */
#define GPIO_PORT_MASK4_MASKP22_Msk                           (0x01UL << GPIO_PORT_MASK4_MASKP22_Pos)                   /*!< GPIO_PORT MASK4: MASKP22 Mask       */
#define GPIO_PORT_MASK4_MASKP23_Pos                           23                                                        /*!< GPIO_PORT MASK4: MASKP23 Position   */
#define GPIO_PORT_MASK4_MASKP23_Msk                           (0x01UL << GPIO_PORT_MASK4_MASKP23_Pos)                   /*!< GPIO_PORT MASK4: MASKP23 Mask       */
#define GPIO_PORT_MASK4_MASKP24_Pos                           24                                                        /*!< GPIO_PORT MASK4: MASKP24 Position   */
#define GPIO_PORT_MASK4_MASKP24_Msk                           (0x01UL << GPIO_PORT_MASK4_MASKP24_Pos)                   /*!< GPIO_PORT MASK4: MASKP24 Mask       */
#define GPIO_PORT_MASK4_MASKP25_Pos                           25                                                        /*!< GPIO_PORT MASK4: MASKP25 Position   */
#define GPIO_PORT_MASK4_MASKP25_Msk                           (0x01UL << GPIO_PORT_MASK4_MASKP25_Pos)                   /*!< GPIO_PORT MASK4: MASKP25 Mask       */
#define GPIO_PORT_MASK4_MASKP26_Pos                           26                                                        /*!< GPIO_PORT MASK4: MASKP26 Position   */
#define GPIO_PORT_MASK4_MASKP26_Msk                           (0x01UL << GPIO_PORT_MASK4_MASKP26_Pos)                   /*!< GPIO_PORT MASK4: MASKP26 Mask       */
#define GPIO_PORT_MASK4_MASKP27_Pos                           27                                                        /*!< GPIO_PORT MASK4: MASKP27 Position   */
#define GPIO_PORT_MASK4_MASKP27_Msk                           (0x01UL << GPIO_PORT_MASK4_MASKP27_Pos)                   /*!< GPIO_PORT MASK4: MASKP27 Mask       */
#define GPIO_PORT_MASK4_MASKP28_Pos                           28                                                        /*!< GPIO_PORT MASK4: MASKP28 Position   */
#define GPIO_PORT_MASK4_MASKP28_Msk                           (0x01UL << GPIO_PORT_MASK4_MASKP28_Pos)                   /*!< GPIO_PORT MASK4: MASKP28 Mask       */
#define GPIO_PORT_MASK4_MASKP29_Pos                           29                                                        /*!< GPIO_PORT MASK4: MASKP29 Position   */
#define GPIO_PORT_MASK4_MASKP29_Msk                           (0x01UL << GPIO_PORT_MASK4_MASKP29_Pos)                   /*!< GPIO_PORT MASK4: MASKP29 Mask       */
#define GPIO_PORT_MASK4_MASKP30_Pos                           30                                                        /*!< GPIO_PORT MASK4: MASKP30 Position   */
#define GPIO_PORT_MASK4_MASKP30_Msk                           (0x01UL << GPIO_PORT_MASK4_MASKP30_Pos)                   /*!< GPIO_PORT MASK4: MASKP30 Mask       */
#define GPIO_PORT_MASK4_MASKP31_Pos                           31                                                        /*!< GPIO_PORT MASK4: MASKP31 Position   */
#define GPIO_PORT_MASK4_MASKP31_Msk                           (0x01UL << GPIO_PORT_MASK4_MASKP31_Pos)                   /*!< GPIO_PORT MASK4: MASKP31 Mask       */

// -------------------------------------  GPIO_PORT_MASK5  ----------------------------------------
#define GPIO_PORT_MASK5_MASKP0_Pos                            0                                                         /*!< GPIO_PORT MASK5: MASKP0 Position    */
#define GPIO_PORT_MASK5_MASKP0_Msk                            (0x01UL << GPIO_PORT_MASK5_MASKP0_Pos)                    /*!< GPIO_PORT MASK5: MASKP0 Mask        */
#define GPIO_PORT_MASK5_MASKP1_Pos                            1                                                         /*!< GPIO_PORT MASK5: MASKP1 Position    */
#define GPIO_PORT_MASK5_MASKP1_Msk                            (0x01UL << GPIO_PORT_MASK5_MASKP1_Pos)                    /*!< GPIO_PORT MASK5: MASKP1 Mask        */
#define GPIO_PORT_MASK5_MASKP2_Pos                            2                                                         /*!< GPIO_PORT MASK5: MASKP2 Position    */
#define GPIO_PORT_MASK5_MASKP2_Msk                            (0x01UL << GPIO_PORT_MASK5_MASKP2_Pos)                    /*!< GPIO_PORT MASK5: MASKP2 Mask        */
#define GPIO_PORT_MASK5_MASKP3_Pos                            3                                                         /*!< GPIO_PORT MASK5: MASKP3 Position    */
#define GPIO_PORT_MASK5_MASKP3_Msk                            (0x01UL << GPIO_PORT_MASK5_MASKP3_Pos)                    /*!< GPIO_PORT MASK5: MASKP3 Mask        */
#define GPIO_PORT_MASK5_MASKP4_Pos                            4                                                         /*!< GPIO_PORT MASK5: MASKP4 Position    */
#define GPIO_PORT_MASK5_MASKP4_Msk                            (0x01UL << GPIO_PORT_MASK5_MASKP4_Pos)                    /*!< GPIO_PORT MASK5: MASKP4 Mask        */
#define GPIO_PORT_MASK5_MASKP5_Pos                            5                                                         /*!< GPIO_PORT MASK5: MASKP5 Position    */
#define GPIO_PORT_MASK5_MASKP5_Msk                            (0x01UL << GPIO_PORT_MASK5_MASKP5_Pos)                    /*!< GPIO_PORT MASK5: MASKP5 Mask        */
#define GPIO_PORT_MASK5_MASKP6_Pos                            6                                                         /*!< GPIO_PORT MASK5: MASKP6 Position    */
#define GPIO_PORT_MASK5_MASKP6_Msk                            (0x01UL << GPIO_PORT_MASK5_MASKP6_Pos)                    /*!< GPIO_PORT MASK5: MASKP6 Mask        */
#define GPIO_PORT_MASK5_MASKP7_Pos                            7                                                         /*!< GPIO_PORT MASK5: MASKP7 Position    */
#define GPIO_PORT_MASK5_MASKP7_Msk                            (0x01UL << GPIO_PORT_MASK5_MASKP7_Pos)                    /*!< GPIO_PORT MASK5: MASKP7 Mask        */
#define GPIO_PORT_MASK5_MASKP8_Pos                            8                                                         /*!< GPIO_PORT MASK5: MASKP8 Position    */
#define GPIO_PORT_MASK5_MASKP8_Msk                            (0x01UL << GPIO_PORT_MASK5_MASKP8_Pos)                    /*!< GPIO_PORT MASK5: MASKP8 Mask        */
#define GPIO_PORT_MASK5_MASKP9_Pos                            9                                                         /*!< GPIO_PORT MASK5: MASKP9 Position    */
#define GPIO_PORT_MASK5_MASKP9_Msk                            (0x01UL << GPIO_PORT_MASK5_MASKP9_Pos)                    /*!< GPIO_PORT MASK5: MASKP9 Mask        */
#define GPIO_PORT_MASK5_MASKP10_Pos                           10                                                        /*!< GPIO_PORT MASK5: MASKP10 Position   */
#define GPIO_PORT_MASK5_MASKP10_Msk                           (0x01UL << GPIO_PORT_MASK5_MASKP10_Pos)                   /*!< GPIO_PORT MASK5: MASKP10 Mask       */
#define GPIO_PORT_MASK5_MASKP11_Pos                           11                                                        /*!< GPIO_PORT MASK5: MASKP11 Position   */
#define GPIO_PORT_MASK5_MASKP11_Msk                           (0x01UL << GPIO_PORT_MASK5_MASKP11_Pos)                   /*!< GPIO_PORT MASK5: MASKP11 Mask       */
#define GPIO_PORT_MASK5_MASKP12_Pos                           12                                                        /*!< GPIO_PORT MASK5: MASKP12 Position   */
#define GPIO_PORT_MASK5_MASKP12_Msk                           (0x01UL << GPIO_PORT_MASK5_MASKP12_Pos)                   /*!< GPIO_PORT MASK5: MASKP12 Mask       */
#define GPIO_PORT_MASK5_MASKP13_Pos                           13                                                        /*!< GPIO_PORT MASK5: MASKP13 Position   */
#define GPIO_PORT_MASK5_MASKP13_Msk                           (0x01UL << GPIO_PORT_MASK5_MASKP13_Pos)                   /*!< GPIO_PORT MASK5: MASKP13 Mask       */
#define GPIO_PORT_MASK5_MASKP14_Pos                           14                                                        /*!< GPIO_PORT MASK5: MASKP14 Position   */
#define GPIO_PORT_MASK5_MASKP14_Msk                           (0x01UL << GPIO_PORT_MASK5_MASKP14_Pos)                   /*!< GPIO_PORT MASK5: MASKP14 Mask       */
#define GPIO_PORT_MASK5_MASKP15_Pos                           15                                                        /*!< GPIO_PORT MASK5: MASKP15 Position   */
#define GPIO_PORT_MASK5_MASKP15_Msk                           (0x01UL << GPIO_PORT_MASK5_MASKP15_Pos)                   /*!< GPIO_PORT MASK5: MASKP15 Mask       */
#define GPIO_PORT_MASK5_MASKP16_Pos                           16                                                        /*!< GPIO_PORT MASK5: MASKP16 Position   */
#define GPIO_PORT_MASK5_MASKP16_Msk                           (0x01UL << GPIO_PORT_MASK5_MASKP16_Pos)                   /*!< GPIO_PORT MASK5: MASKP16 Mask       */
#define GPIO_PORT_MASK5_MASKP17_Pos                           17                                                        /*!< GPIO_PORT MASK5: MASKP17 Position   */
#define GPIO_PORT_MASK5_MASKP17_Msk                           (0x01UL << GPIO_PORT_MASK5_MASKP17_Pos)                   /*!< GPIO_PORT MASK5: MASKP17 Mask       */
#define GPIO_PORT_MASK5_MASKP18_Pos                           18                                                        /*!< GPIO_PORT MASK5: MASKP18 Position   */
#define GPIO_PORT_MASK5_MASKP18_Msk                           (0x01UL << GPIO_PORT_MASK5_MASKP18_Pos)                   /*!< GPIO_PORT MASK5: MASKP18 Mask       */
#define GPIO_PORT_MASK5_MASKP19_Pos                           19                                                        /*!< GPIO_PORT MASK5: MASKP19 Position   */
#define GPIO_PORT_MASK5_MASKP19_Msk                           (0x01UL << GPIO_PORT_MASK5_MASKP19_Pos)                   /*!< GPIO_PORT MASK5: MASKP19 Mask       */
#define GPIO_PORT_MASK5_MASKP20_Pos                           20                                                        /*!< GPIO_PORT MASK5: MASKP20 Position   */
#define GPIO_PORT_MASK5_MASKP20_Msk                           (0x01UL << GPIO_PORT_MASK5_MASKP20_Pos)                   /*!< GPIO_PORT MASK5: MASKP20 Mask       */
#define GPIO_PORT_MASK5_MASKP21_Pos                           21                                                        /*!< GPIO_PORT MASK5: MASKP21 Position   */
#define GPIO_PORT_MASK5_MASKP21_Msk                           (0x01UL << GPIO_PORT_MASK5_MASKP21_Pos)                   /*!< GPIO_PORT MASK5: MASKP21 Mask       */
#define GPIO_PORT_MASK5_MASKP22_Pos                           22                                                        /*!< GPIO_PORT MASK5: MASKP22 Position   */
#define GPIO_PORT_MASK5_MASKP22_Msk                           (0x01UL << GPIO_PORT_MASK5_MASKP22_Pos)                   /*!< GPIO_PORT MASK5: MASKP22 Mask       */
#define GPIO_PORT_MASK5_MASKP23_Pos                           23                                                        /*!< GPIO_PORT MASK5: MASKP23 Position   */
#define GPIO_PORT_MASK5_MASKP23_Msk                           (0x01UL << GPIO_PORT_MASK5_MASKP23_Pos)                   /*!< GPIO_PORT MASK5: MASKP23 Mask       */
#define GPIO_PORT_MASK5_MASKP24_Pos                           24                                                        /*!< GPIO_PORT MASK5: MASKP24 Position   */
#define GPIO_PORT_MASK5_MASKP24_Msk                           (0x01UL << GPIO_PORT_MASK5_MASKP24_Pos)                   /*!< GPIO_PORT MASK5: MASKP24 Mask       */
#define GPIO_PORT_MASK5_MASKP25_Pos                           25                                                        /*!< GPIO_PORT MASK5: MASKP25 Position   */
#define GPIO_PORT_MASK5_MASKP25_Msk                           (0x01UL << GPIO_PORT_MASK5_MASKP25_Pos)                   /*!< GPIO_PORT MASK5: MASKP25 Mask       */
#define GPIO_PORT_MASK5_MASKP26_Pos                           26                                                        /*!< GPIO_PORT MASK5: MASKP26 Position   */
#define GPIO_PORT_MASK5_MASKP26_Msk                           (0x01UL << GPIO_PORT_MASK5_MASKP26_Pos)                   /*!< GPIO_PORT MASK5: MASKP26 Mask       */
#define GPIO_PORT_MASK5_MASKP27_Pos                           27                                                        /*!< GPIO_PORT MASK5: MASKP27 Position   */
#define GPIO_PORT_MASK5_MASKP27_Msk                           (0x01UL << GPIO_PORT_MASK5_MASKP27_Pos)                   /*!< GPIO_PORT MASK5: MASKP27 Mask       */
#define GPIO_PORT_MASK5_MASKP28_Pos                           28                                                        /*!< GPIO_PORT MASK5: MASKP28 Position   */
#define GPIO_PORT_MASK5_MASKP28_Msk                           (0x01UL << GPIO_PORT_MASK5_MASKP28_Pos)                   /*!< GPIO_PORT MASK5: MASKP28 Mask       */
#define GPIO_PORT_MASK5_MASKP29_Pos                           29                                                        /*!< GPIO_PORT MASK5: MASKP29 Position   */
#define GPIO_PORT_MASK5_MASKP29_Msk                           (0x01UL << GPIO_PORT_MASK5_MASKP29_Pos)                   /*!< GPIO_PORT MASK5: MASKP29 Mask       */
#define GPIO_PORT_MASK5_MASKP30_Pos                           30                                                        /*!< GPIO_PORT MASK5: MASKP30 Position   */
#define GPIO_PORT_MASK5_MASKP30_Msk                           (0x01UL << GPIO_PORT_MASK5_MASKP30_Pos)                   /*!< GPIO_PORT MASK5: MASKP30 Mask       */
#define GPIO_PORT_MASK5_MASKP31_Pos                           31                                                        /*!< GPIO_PORT MASK5: MASKP31 Position   */
#define GPIO_PORT_MASK5_MASKP31_Msk                           (0x01UL << GPIO_PORT_MASK5_MASKP31_Pos)                   /*!< GPIO_PORT MASK5: MASKP31 Mask       */

// -------------------------------------  GPIO_PORT_MASK6  ----------------------------------------
#define GPIO_PORT_MASK6_MASKP0_Pos                            0                                                         /*!< GPIO_PORT MASK6: MASKP0 Position    */
#define GPIO_PORT_MASK6_MASKP0_Msk                            (0x01UL << GPIO_PORT_MASK6_MASKP0_Pos)                    /*!< GPIO_PORT MASK6: MASKP0 Mask        */
#define GPIO_PORT_MASK6_MASKP1_Pos                            1                                                         /*!< GPIO_PORT MASK6: MASKP1 Position    */
#define GPIO_PORT_MASK6_MASKP1_Msk                            (0x01UL << GPIO_PORT_MASK6_MASKP1_Pos)                    /*!< GPIO_PORT MASK6: MASKP1 Mask        */
#define GPIO_PORT_MASK6_MASKP2_Pos                            2                                                         /*!< GPIO_PORT MASK6: MASKP2 Position    */
#define GPIO_PORT_MASK6_MASKP2_Msk                            (0x01UL << GPIO_PORT_MASK6_MASKP2_Pos)                    /*!< GPIO_PORT MASK6: MASKP2 Mask        */
#define GPIO_PORT_MASK6_MASKP3_Pos                            3                                                         /*!< GPIO_PORT MASK6: MASKP3 Position    */
#define GPIO_PORT_MASK6_MASKP3_Msk                            (0x01UL << GPIO_PORT_MASK6_MASKP3_Pos)                    /*!< GPIO_PORT MASK6: MASKP3 Mask        */
#define GPIO_PORT_MASK6_MASKP4_Pos                            4                                                         /*!< GPIO_PORT MASK6: MASKP4 Position    */
#define GPIO_PORT_MASK6_MASKP4_Msk                            (0x01UL << GPIO_PORT_MASK6_MASKP4_Pos)                    /*!< GPIO_PORT MASK6: MASKP4 Mask        */
#define GPIO_PORT_MASK6_MASKP5_Pos                            5                                                         /*!< GPIO_PORT MASK6: MASKP5 Position    */
#define GPIO_PORT_MASK6_MASKP5_Msk                            (0x01UL << GPIO_PORT_MASK6_MASKP5_Pos)                    /*!< GPIO_PORT MASK6: MASKP5 Mask        */
#define GPIO_PORT_MASK6_MASKP6_Pos                            6                                                         /*!< GPIO_PORT MASK6: MASKP6 Position    */
#define GPIO_PORT_MASK6_MASKP6_Msk                            (0x01UL << GPIO_PORT_MASK6_MASKP6_Pos)                    /*!< GPIO_PORT MASK6: MASKP6 Mask        */
#define GPIO_PORT_MASK6_MASKP7_Pos                            7                                                         /*!< GPIO_PORT MASK6: MASKP7 Position    */
#define GPIO_PORT_MASK6_MASKP7_Msk                            (0x01UL << GPIO_PORT_MASK6_MASKP7_Pos)                    /*!< GPIO_PORT MASK6: MASKP7 Mask        */
#define GPIO_PORT_MASK6_MASKP8_Pos                            8                                                         /*!< GPIO_PORT MASK6: MASKP8 Position    */
#define GPIO_PORT_MASK6_MASKP8_Msk                            (0x01UL << GPIO_PORT_MASK6_MASKP8_Pos)                    /*!< GPIO_PORT MASK6: MASKP8 Mask        */
#define GPIO_PORT_MASK6_MASKP9_Pos                            9                                                         /*!< GPIO_PORT MASK6: MASKP9 Position    */
#define GPIO_PORT_MASK6_MASKP9_Msk                            (0x01UL << GPIO_PORT_MASK6_MASKP9_Pos)                    /*!< GPIO_PORT MASK6: MASKP9 Mask        */
#define GPIO_PORT_MASK6_MASKP10_Pos                           10                                                        /*!< GPIO_PORT MASK6: MASKP10 Position   */
#define GPIO_PORT_MASK6_MASKP10_Msk                           (0x01UL << GPIO_PORT_MASK6_MASKP10_Pos)                   /*!< GPIO_PORT MASK6: MASKP10 Mask       */
#define GPIO_PORT_MASK6_MASKP11_Pos                           11                                                        /*!< GPIO_PORT MASK6: MASKP11 Position   */
#define GPIO_PORT_MASK6_MASKP11_Msk                           (0x01UL << GPIO_PORT_MASK6_MASKP11_Pos)                   /*!< GPIO_PORT MASK6: MASKP11 Mask       */
#define GPIO_PORT_MASK6_MASKP12_Pos                           12                                                        /*!< GPIO_PORT MASK6: MASKP12 Position   */
#define GPIO_PORT_MASK6_MASKP12_Msk                           (0x01UL << GPIO_PORT_MASK6_MASKP12_Pos)                   /*!< GPIO_PORT MASK6: MASKP12 Mask       */
#define GPIO_PORT_MASK6_MASKP13_Pos                           13                                                        /*!< GPIO_PORT MASK6: MASKP13 Position   */
#define GPIO_PORT_MASK6_MASKP13_Msk                           (0x01UL << GPIO_PORT_MASK6_MASKP13_Pos)                   /*!< GPIO_PORT MASK6: MASKP13 Mask       */
#define GPIO_PORT_MASK6_MASKP14_Pos                           14                                                        /*!< GPIO_PORT MASK6: MASKP14 Position   */
#define GPIO_PORT_MASK6_MASKP14_Msk                           (0x01UL << GPIO_PORT_MASK6_MASKP14_Pos)                   /*!< GPIO_PORT MASK6: MASKP14 Mask       */
#define GPIO_PORT_MASK6_MASKP15_Pos                           15                                                        /*!< GPIO_PORT MASK6: MASKP15 Position   */
#define GPIO_PORT_MASK6_MASKP15_Msk                           (0x01UL << GPIO_PORT_MASK6_MASKP15_Pos)                   /*!< GPIO_PORT MASK6: MASKP15 Mask       */
#define GPIO_PORT_MASK6_MASKP16_Pos                           16                                                        /*!< GPIO_PORT MASK6: MASKP16 Position   */
#define GPIO_PORT_MASK6_MASKP16_Msk                           (0x01UL << GPIO_PORT_MASK6_MASKP16_Pos)                   /*!< GPIO_PORT MASK6: MASKP16 Mask       */
#define GPIO_PORT_MASK6_MASKP17_Pos                           17                                                        /*!< GPIO_PORT MASK6: MASKP17 Position   */
#define GPIO_PORT_MASK6_MASKP17_Msk                           (0x01UL << GPIO_PORT_MASK6_MASKP17_Pos)                   /*!< GPIO_PORT MASK6: MASKP17 Mask       */
#define GPIO_PORT_MASK6_MASKP18_Pos                           18                                                        /*!< GPIO_PORT MASK6: MASKP18 Position   */
#define GPIO_PORT_MASK6_MASKP18_Msk                           (0x01UL << GPIO_PORT_MASK6_MASKP18_Pos)                   /*!< GPIO_PORT MASK6: MASKP18 Mask       */
#define GPIO_PORT_MASK6_MASKP19_Pos                           19                                                        /*!< GPIO_PORT MASK6: MASKP19 Position   */
#define GPIO_PORT_MASK6_MASKP19_Msk                           (0x01UL << GPIO_PORT_MASK6_MASKP19_Pos)                   /*!< GPIO_PORT MASK6: MASKP19 Mask       */
#define GPIO_PORT_MASK6_MASKP20_Pos                           20                                                        /*!< GPIO_PORT MASK6: MASKP20 Position   */
#define GPIO_PORT_MASK6_MASKP20_Msk                           (0x01UL << GPIO_PORT_MASK6_MASKP20_Pos)                   /*!< GPIO_PORT MASK6: MASKP20 Mask       */
#define GPIO_PORT_MASK6_MASKP21_Pos                           21                                                        /*!< GPIO_PORT MASK6: MASKP21 Position   */
#define GPIO_PORT_MASK6_MASKP21_Msk                           (0x01UL << GPIO_PORT_MASK6_MASKP21_Pos)                   /*!< GPIO_PORT MASK6: MASKP21 Mask       */
#define GPIO_PORT_MASK6_MASKP22_Pos                           22                                                        /*!< GPIO_PORT MASK6: MASKP22 Position   */
#define GPIO_PORT_MASK6_MASKP22_Msk                           (0x01UL << GPIO_PORT_MASK6_MASKP22_Pos)                   /*!< GPIO_PORT MASK6: MASKP22 Mask       */
#define GPIO_PORT_MASK6_MASKP23_Pos                           23                                                        /*!< GPIO_PORT MASK6: MASKP23 Position   */
#define GPIO_PORT_MASK6_MASKP23_Msk                           (0x01UL << GPIO_PORT_MASK6_MASKP23_Pos)                   /*!< GPIO_PORT MASK6: MASKP23 Mask       */
#define GPIO_PORT_MASK6_MASKP24_Pos                           24                                                        /*!< GPIO_PORT MASK6: MASKP24 Position   */
#define GPIO_PORT_MASK6_MASKP24_Msk                           (0x01UL << GPIO_PORT_MASK6_MASKP24_Pos)                   /*!< GPIO_PORT MASK6: MASKP24 Mask       */
#define GPIO_PORT_MASK6_MASKP25_Pos                           25                                                        /*!< GPIO_PORT MASK6: MASKP25 Position   */
#define GPIO_PORT_MASK6_MASKP25_Msk                           (0x01UL << GPIO_PORT_MASK6_MASKP25_Pos)                   /*!< GPIO_PORT MASK6: MASKP25 Mask       */
#define GPIO_PORT_MASK6_MASKP26_Pos                           26                                                        /*!< GPIO_PORT MASK6: MASKP26 Position   */
#define GPIO_PORT_MASK6_MASKP26_Msk                           (0x01UL << GPIO_PORT_MASK6_MASKP26_Pos)                   /*!< GPIO_PORT MASK6: MASKP26 Mask       */
#define GPIO_PORT_MASK6_MASKP27_Pos                           27                                                        /*!< GPIO_PORT MASK6: MASKP27 Position   */
#define GPIO_PORT_MASK6_MASKP27_Msk                           (0x01UL << GPIO_PORT_MASK6_MASKP27_Pos)                   /*!< GPIO_PORT MASK6: MASKP27 Mask       */
#define GPIO_PORT_MASK6_MASKP28_Pos                           28                                                        /*!< GPIO_PORT MASK6: MASKP28 Position   */
#define GPIO_PORT_MASK6_MASKP28_Msk                           (0x01UL << GPIO_PORT_MASK6_MASKP28_Pos)                   /*!< GPIO_PORT MASK6: MASKP28 Mask       */
#define GPIO_PORT_MASK6_MASKP29_Pos                           29                                                        /*!< GPIO_PORT MASK6: MASKP29 Position   */
#define GPIO_PORT_MASK6_MASKP29_Msk                           (0x01UL << GPIO_PORT_MASK6_MASKP29_Pos)                   /*!< GPIO_PORT MASK6: MASKP29 Mask       */
#define GPIO_PORT_MASK6_MASKP30_Pos                           30                                                        /*!< GPIO_PORT MASK6: MASKP30 Position   */
#define GPIO_PORT_MASK6_MASKP30_Msk                           (0x01UL << GPIO_PORT_MASK6_MASKP30_Pos)                   /*!< GPIO_PORT MASK6: MASKP30 Mask       */
#define GPIO_PORT_MASK6_MASKP31_Pos                           31                                                        /*!< GPIO_PORT MASK6: MASKP31 Position   */
#define GPIO_PORT_MASK6_MASKP31_Msk                           (0x01UL << GPIO_PORT_MASK6_MASKP31_Pos)                   /*!< GPIO_PORT MASK6: MASKP31 Mask       */

// -------------------------------------  GPIO_PORT_MASK7  ----------------------------------------
#define GPIO_PORT_MASK7_MASKP0_Pos                            0                                                         /*!< GPIO_PORT MASK7: MASKP0 Position    */
#define GPIO_PORT_MASK7_MASKP0_Msk                            (0x01UL << GPIO_PORT_MASK7_MASKP0_Pos)                    /*!< GPIO_PORT MASK7: MASKP0 Mask        */
#define GPIO_PORT_MASK7_MASKP1_Pos                            1                                                         /*!< GPIO_PORT MASK7: MASKP1 Position    */
#define GPIO_PORT_MASK7_MASKP1_Msk                            (0x01UL << GPIO_PORT_MASK7_MASKP1_Pos)                    /*!< GPIO_PORT MASK7: MASKP1 Mask        */
#define GPIO_PORT_MASK7_MASKP2_Pos                            2                                                         /*!< GPIO_PORT MASK7: MASKP2 Position    */
#define GPIO_PORT_MASK7_MASKP2_Msk                            (0x01UL << GPIO_PORT_MASK7_MASKP2_Pos)                    /*!< GPIO_PORT MASK7: MASKP2 Mask        */
#define GPIO_PORT_MASK7_MASKP3_Pos                            3                                                         /*!< GPIO_PORT MASK7: MASKP3 Position    */
#define GPIO_PORT_MASK7_MASKP3_Msk                            (0x01UL << GPIO_PORT_MASK7_MASKP3_Pos)                    /*!< GPIO_PORT MASK7: MASKP3 Mask        */
#define GPIO_PORT_MASK7_MASKP4_Pos                            4                                                         /*!< GPIO_PORT MASK7: MASKP4 Position    */
#define GPIO_PORT_MASK7_MASKP4_Msk                            (0x01UL << GPIO_PORT_MASK7_MASKP4_Pos)                    /*!< GPIO_PORT MASK7: MASKP4 Mask        */
#define GPIO_PORT_MASK7_MASKP5_Pos                            5                                                         /*!< GPIO_PORT MASK7: MASKP5 Position    */
#define GPIO_PORT_MASK7_MASKP5_Msk                            (0x01UL << GPIO_PORT_MASK7_MASKP5_Pos)                    /*!< GPIO_PORT MASK7: MASKP5 Mask        */
#define GPIO_PORT_MASK7_MASKP6_Pos                            6                                                         /*!< GPIO_PORT MASK7: MASKP6 Position    */
#define GPIO_PORT_MASK7_MASKP6_Msk                            (0x01UL << GPIO_PORT_MASK7_MASKP6_Pos)                    /*!< GPIO_PORT MASK7: MASKP6 Mask        */
#define GPIO_PORT_MASK7_MASKP7_Pos                            7                                                         /*!< GPIO_PORT MASK7: MASKP7 Position    */
#define GPIO_PORT_MASK7_MASKP7_Msk                            (0x01UL << GPIO_PORT_MASK7_MASKP7_Pos)                    /*!< GPIO_PORT MASK7: MASKP7 Mask        */
#define GPIO_PORT_MASK7_MASKP8_Pos                            8                                                         /*!< GPIO_PORT MASK7: MASKP8 Position    */
#define GPIO_PORT_MASK7_MASKP8_Msk                            (0x01UL << GPIO_PORT_MASK7_MASKP8_Pos)                    /*!< GPIO_PORT MASK7: MASKP8 Mask        */
#define GPIO_PORT_MASK7_MASKP9_Pos                            9                                                         /*!< GPIO_PORT MASK7: MASKP9 Position    */
#define GPIO_PORT_MASK7_MASKP9_Msk                            (0x01UL << GPIO_PORT_MASK7_MASKP9_Pos)                    /*!< GPIO_PORT MASK7: MASKP9 Mask        */
#define GPIO_PORT_MASK7_MASKP10_Pos                           10                                                        /*!< GPIO_PORT MASK7: MASKP10 Position   */
#define GPIO_PORT_MASK7_MASKP10_Msk                           (0x01UL << GPIO_PORT_MASK7_MASKP10_Pos)                   /*!< GPIO_PORT MASK7: MASKP10 Mask       */
#define GPIO_PORT_MASK7_MASKP11_Pos                           11                                                        /*!< GPIO_PORT MASK7: MASKP11 Position   */
#define GPIO_PORT_MASK7_MASKP11_Msk                           (0x01UL << GPIO_PORT_MASK7_MASKP11_Pos)                   /*!< GPIO_PORT MASK7: MASKP11 Mask       */
#define GPIO_PORT_MASK7_MASKP12_Pos                           12                                                        /*!< GPIO_PORT MASK7: MASKP12 Position   */
#define GPIO_PORT_MASK7_MASKP12_Msk                           (0x01UL << GPIO_PORT_MASK7_MASKP12_Pos)                   /*!< GPIO_PORT MASK7: MASKP12 Mask       */
#define GPIO_PORT_MASK7_MASKP13_Pos                           13                                                        /*!< GPIO_PORT MASK7: MASKP13 Position   */
#define GPIO_PORT_MASK7_MASKP13_Msk                           (0x01UL << GPIO_PORT_MASK7_MASKP13_Pos)                   /*!< GPIO_PORT MASK7: MASKP13 Mask       */
#define GPIO_PORT_MASK7_MASKP14_Pos                           14                                                        /*!< GPIO_PORT MASK7: MASKP14 Position   */
#define GPIO_PORT_MASK7_MASKP14_Msk                           (0x01UL << GPIO_PORT_MASK7_MASKP14_Pos)                   /*!< GPIO_PORT MASK7: MASKP14 Mask       */
#define GPIO_PORT_MASK7_MASKP15_Pos                           15                                                        /*!< GPIO_PORT MASK7: MASKP15 Position   */
#define GPIO_PORT_MASK7_MASKP15_Msk                           (0x01UL << GPIO_PORT_MASK7_MASKP15_Pos)                   /*!< GPIO_PORT MASK7: MASKP15 Mask       */
#define GPIO_PORT_MASK7_MASKP16_Pos                           16                                                        /*!< GPIO_PORT MASK7: MASKP16 Position   */
#define GPIO_PORT_MASK7_MASKP16_Msk                           (0x01UL << GPIO_PORT_MASK7_MASKP16_Pos)                   /*!< GPIO_PORT MASK7: MASKP16 Mask       */
#define GPIO_PORT_MASK7_MASKP17_Pos                           17                                                        /*!< GPIO_PORT MASK7: MASKP17 Position   */
#define GPIO_PORT_MASK7_MASKP17_Msk                           (0x01UL << GPIO_PORT_MASK7_MASKP17_Pos)                   /*!< GPIO_PORT MASK7: MASKP17 Mask       */
#define GPIO_PORT_MASK7_MASKP18_Pos                           18                                                        /*!< GPIO_PORT MASK7: MASKP18 Position   */
#define GPIO_PORT_MASK7_MASKP18_Msk                           (0x01UL << GPIO_PORT_MASK7_MASKP18_Pos)                   /*!< GPIO_PORT MASK7: MASKP18 Mask       */
#define GPIO_PORT_MASK7_MASKP19_Pos                           19                                                        /*!< GPIO_PORT MASK7: MASKP19 Position   */
#define GPIO_PORT_MASK7_MASKP19_Msk                           (0x01UL << GPIO_PORT_MASK7_MASKP19_Pos)                   /*!< GPIO_PORT MASK7: MASKP19 Mask       */
#define GPIO_PORT_MASK7_MASKP20_Pos                           20                                                        /*!< GPIO_PORT MASK7: MASKP20 Position   */
#define GPIO_PORT_MASK7_MASKP20_Msk                           (0x01UL << GPIO_PORT_MASK7_MASKP20_Pos)                   /*!< GPIO_PORT MASK7: MASKP20 Mask       */
#define GPIO_PORT_MASK7_MASKP21_Pos                           21                                                        /*!< GPIO_PORT MASK7: MASKP21 Position   */
#define GPIO_PORT_MASK7_MASKP21_Msk                           (0x01UL << GPIO_PORT_MASK7_MASKP21_Pos)                   /*!< GPIO_PORT MASK7: MASKP21 Mask       */
#define GPIO_PORT_MASK7_MASKP22_Pos                           22                                                        /*!< GPIO_PORT MASK7: MASKP22 Position   */
#define GPIO_PORT_MASK7_MASKP22_Msk                           (0x01UL << GPIO_PORT_MASK7_MASKP22_Pos)                   /*!< GPIO_PORT MASK7: MASKP22 Mask       */
#define GPIO_PORT_MASK7_MASKP23_Pos                           23                                                        /*!< GPIO_PORT MASK7: MASKP23 Position   */
#define GPIO_PORT_MASK7_MASKP23_Msk                           (0x01UL << GPIO_PORT_MASK7_MASKP23_Pos)                   /*!< GPIO_PORT MASK7: MASKP23 Mask       */
#define GPIO_PORT_MASK7_MASKP24_Pos                           24                                                        /*!< GPIO_PORT MASK7: MASKP24 Position   */
#define GPIO_PORT_MASK7_MASKP24_Msk                           (0x01UL << GPIO_PORT_MASK7_MASKP24_Pos)                   /*!< GPIO_PORT MASK7: MASKP24 Mask       */
#define GPIO_PORT_MASK7_MASKP25_Pos                           25                                                        /*!< GPIO_PORT MASK7: MASKP25 Position   */
#define GPIO_PORT_MASK7_MASKP25_Msk                           (0x01UL << GPIO_PORT_MASK7_MASKP25_Pos)                   /*!< GPIO_PORT MASK7: MASKP25 Mask       */
#define GPIO_PORT_MASK7_MASKP26_Pos                           26                                                        /*!< GPIO_PORT MASK7: MASKP26 Position   */
#define GPIO_PORT_MASK7_MASKP26_Msk                           (0x01UL << GPIO_PORT_MASK7_MASKP26_Pos)                   /*!< GPIO_PORT MASK7: MASKP26 Mask       */
#define GPIO_PORT_MASK7_MASKP27_Pos                           27                                                        /*!< GPIO_PORT MASK7: MASKP27 Position   */
#define GPIO_PORT_MASK7_MASKP27_Msk                           (0x01UL << GPIO_PORT_MASK7_MASKP27_Pos)                   /*!< GPIO_PORT MASK7: MASKP27 Mask       */
#define GPIO_PORT_MASK7_MASKP28_Pos                           28                                                        /*!< GPIO_PORT MASK7: MASKP28 Position   */
#define GPIO_PORT_MASK7_MASKP28_Msk                           (0x01UL << GPIO_PORT_MASK7_MASKP28_Pos)                   /*!< GPIO_PORT MASK7: MASKP28 Mask       */
#define GPIO_PORT_MASK7_MASKP29_Pos                           29                                                        /*!< GPIO_PORT MASK7: MASKP29 Position   */
#define GPIO_PORT_MASK7_MASKP29_Msk                           (0x01UL << GPIO_PORT_MASK7_MASKP29_Pos)                   /*!< GPIO_PORT MASK7: MASKP29 Mask       */
#define GPIO_PORT_MASK7_MASKP30_Pos                           30                                                        /*!< GPIO_PORT MASK7: MASKP30 Position   */
#define GPIO_PORT_MASK7_MASKP30_Msk                           (0x01UL << GPIO_PORT_MASK7_MASKP30_Pos)                   /*!< GPIO_PORT MASK7: MASKP30 Mask       */
#define GPIO_PORT_MASK7_MASKP31_Pos                           31                                                        /*!< GPIO_PORT MASK7: MASKP31 Position   */
#define GPIO_PORT_MASK7_MASKP31_Msk                           (0x01UL << GPIO_PORT_MASK7_MASKP31_Pos)                   /*!< GPIO_PORT MASK7: MASKP31 Mask       */

// -------------------------------------  GPIO_PORT_PIN0  -----------------------------------------
#define GPIO_PORT_PIN0_PORT0_Pos                              0                                                         /*!< GPIO_PORT PIN0: PORT0 Position      */
#define GPIO_PORT_PIN0_PORT0_Msk                              (0x01UL << GPIO_PORT_PIN0_PORT0_Pos)                      /*!< GPIO_PORT PIN0: PORT0 Mask          */
#define GPIO_PORT_PIN0_PORT1_Pos                              1                                                         /*!< GPIO_PORT PIN0: PORT1 Position      */
#define GPIO_PORT_PIN0_PORT1_Msk                              (0x01UL << GPIO_PORT_PIN0_PORT1_Pos)                      /*!< GPIO_PORT PIN0: PORT1 Mask          */
#define GPIO_PORT_PIN0_PORT2_Pos                              2                                                         /*!< GPIO_PORT PIN0: PORT2 Position      */
#define GPIO_PORT_PIN0_PORT2_Msk                              (0x01UL << GPIO_PORT_PIN0_PORT2_Pos)                      /*!< GPIO_PORT PIN0: PORT2 Mask          */
#define GPIO_PORT_PIN0_PORT3_Pos                              3                                                         /*!< GPIO_PORT PIN0: PORT3 Position      */
#define GPIO_PORT_PIN0_PORT3_Msk                              (0x01UL << GPIO_PORT_PIN0_PORT3_Pos)                      /*!< GPIO_PORT PIN0: PORT3 Mask          */
#define GPIO_PORT_PIN0_PORT4_Pos                              4                                                         /*!< GPIO_PORT PIN0: PORT4 Position      */
#define GPIO_PORT_PIN0_PORT4_Msk                              (0x01UL << GPIO_PORT_PIN0_PORT4_Pos)                      /*!< GPIO_PORT PIN0: PORT4 Mask          */
#define GPIO_PORT_PIN0_PORT5_Pos                              5                                                         /*!< GPIO_PORT PIN0: PORT5 Position      */
#define GPIO_PORT_PIN0_PORT5_Msk                              (0x01UL << GPIO_PORT_PIN0_PORT5_Pos)                      /*!< GPIO_PORT PIN0: PORT5 Mask          */
#define GPIO_PORT_PIN0_PORT6_Pos                              6                                                         /*!< GPIO_PORT PIN0: PORT6 Position      */
#define GPIO_PORT_PIN0_PORT6_Msk                              (0x01UL << GPIO_PORT_PIN0_PORT6_Pos)                      /*!< GPIO_PORT PIN0: PORT6 Mask          */
#define GPIO_PORT_PIN0_PORT7_Pos                              7                                                         /*!< GPIO_PORT PIN0: PORT7 Position      */
#define GPIO_PORT_PIN0_PORT7_Msk                              (0x01UL << GPIO_PORT_PIN0_PORT7_Pos)                      /*!< GPIO_PORT PIN0: PORT7 Mask          */
#define GPIO_PORT_PIN0_PORT8_Pos                              8                                                         /*!< GPIO_PORT PIN0: PORT8 Position      */
#define GPIO_PORT_PIN0_PORT8_Msk                              (0x01UL << GPIO_PORT_PIN0_PORT8_Pos)                      /*!< GPIO_PORT PIN0: PORT8 Mask          */
#define GPIO_PORT_PIN0_PORT9_Pos                              9                                                         /*!< GPIO_PORT PIN0: PORT9 Position      */
#define GPIO_PORT_PIN0_PORT9_Msk                              (0x01UL << GPIO_PORT_PIN0_PORT9_Pos)                      /*!< GPIO_PORT PIN0: PORT9 Mask          */
#define GPIO_PORT_PIN0_PORT10_Pos                             10                                                        /*!< GPIO_PORT PIN0: PORT10 Position     */
#define GPIO_PORT_PIN0_PORT10_Msk                             (0x01UL << GPIO_PORT_PIN0_PORT10_Pos)                     /*!< GPIO_PORT PIN0: PORT10 Mask         */
#define GPIO_PORT_PIN0_PORT11_Pos                             11                                                        /*!< GPIO_PORT PIN0: PORT11 Position     */
#define GPIO_PORT_PIN0_PORT11_Msk                             (0x01UL << GPIO_PORT_PIN0_PORT11_Pos)                     /*!< GPIO_PORT PIN0: PORT11 Mask         */
#define GPIO_PORT_PIN0_PORT12_Pos                             12                                                        /*!< GPIO_PORT PIN0: PORT12 Position     */
#define GPIO_PORT_PIN0_PORT12_Msk                             (0x01UL << GPIO_PORT_PIN0_PORT12_Pos)                     /*!< GPIO_PORT PIN0: PORT12 Mask         */
#define GPIO_PORT_PIN0_PORT13_Pos                             13                                                        /*!< GPIO_PORT PIN0: PORT13 Position     */
#define GPIO_PORT_PIN0_PORT13_Msk                             (0x01UL << GPIO_PORT_PIN0_PORT13_Pos)                     /*!< GPIO_PORT PIN0: PORT13 Mask         */
#define GPIO_PORT_PIN0_PORT14_Pos                             14                                                        /*!< GPIO_PORT PIN0: PORT14 Position     */
#define GPIO_PORT_PIN0_PORT14_Msk                             (0x01UL << GPIO_PORT_PIN0_PORT14_Pos)                     /*!< GPIO_PORT PIN0: PORT14 Mask         */
#define GPIO_PORT_PIN0_PORT15_Pos                             15                                                        /*!< GPIO_PORT PIN0: PORT15 Position     */
#define GPIO_PORT_PIN0_PORT15_Msk                             (0x01UL << GPIO_PORT_PIN0_PORT15_Pos)                     /*!< GPIO_PORT PIN0: PORT15 Mask         */
#define GPIO_PORT_PIN0_PORT16_Pos                             16                                                        /*!< GPIO_PORT PIN0: PORT16 Position     */
#define GPIO_PORT_PIN0_PORT16_Msk                             (0x01UL << GPIO_PORT_PIN0_PORT16_Pos)                     /*!< GPIO_PORT PIN0: PORT16 Mask         */
#define GPIO_PORT_PIN0_PORT17_Pos                             17                                                        /*!< GPIO_PORT PIN0: PORT17 Position     */
#define GPIO_PORT_PIN0_PORT17_Msk                             (0x01UL << GPIO_PORT_PIN0_PORT17_Pos)                     /*!< GPIO_PORT PIN0: PORT17 Mask         */
#define GPIO_PORT_PIN0_PORT18_Pos                             18                                                        /*!< GPIO_PORT PIN0: PORT18 Position     */
#define GPIO_PORT_PIN0_PORT18_Msk                             (0x01UL << GPIO_PORT_PIN0_PORT18_Pos)                     /*!< GPIO_PORT PIN0: PORT18 Mask         */
#define GPIO_PORT_PIN0_PORT19_Pos                             19                                                        /*!< GPIO_PORT PIN0: PORT19 Position     */
#define GPIO_PORT_PIN0_PORT19_Msk                             (0x01UL << GPIO_PORT_PIN0_PORT19_Pos)                     /*!< GPIO_PORT PIN0: PORT19 Mask         */
#define GPIO_PORT_PIN0_PORT20_Pos                             20                                                        /*!< GPIO_PORT PIN0: PORT20 Position     */
#define GPIO_PORT_PIN0_PORT20_Msk                             (0x01UL << GPIO_PORT_PIN0_PORT20_Pos)                     /*!< GPIO_PORT PIN0: PORT20 Mask         */
#define GPIO_PORT_PIN0_PORT21_Pos                             21                                                        /*!< GPIO_PORT PIN0: PORT21 Position     */
#define GPIO_PORT_PIN0_PORT21_Msk                             (0x01UL << GPIO_PORT_PIN0_PORT21_Pos)                     /*!< GPIO_PORT PIN0: PORT21 Mask         */
#define GPIO_PORT_PIN0_PORT22_Pos                             22                                                        /*!< GPIO_PORT PIN0: PORT22 Position     */
#define GPIO_PORT_PIN0_PORT22_Msk                             (0x01UL << GPIO_PORT_PIN0_PORT22_Pos)                     /*!< GPIO_PORT PIN0: PORT22 Mask         */
#define GPIO_PORT_PIN0_PORT23_Pos                             23                                                        /*!< GPIO_PORT PIN0: PORT23 Position     */
#define GPIO_PORT_PIN0_PORT23_Msk                             (0x01UL << GPIO_PORT_PIN0_PORT23_Pos)                     /*!< GPIO_PORT PIN0: PORT23 Mask         */
#define GPIO_PORT_PIN0_PORT24_Pos                             24                                                        /*!< GPIO_PORT PIN0: PORT24 Position     */
#define GPIO_PORT_PIN0_PORT24_Msk                             (0x01UL << GPIO_PORT_PIN0_PORT24_Pos)                     /*!< GPIO_PORT PIN0: PORT24 Mask         */
#define GPIO_PORT_PIN0_PORT25_Pos                             25                                                        /*!< GPIO_PORT PIN0: PORT25 Position     */
#define GPIO_PORT_PIN0_PORT25_Msk                             (0x01UL << GPIO_PORT_PIN0_PORT25_Pos)                     /*!< GPIO_PORT PIN0: PORT25 Mask         */
#define GPIO_PORT_PIN0_PORT26_Pos                             26                                                        /*!< GPIO_PORT PIN0: PORT26 Position     */
#define GPIO_PORT_PIN0_PORT26_Msk                             (0x01UL << GPIO_PORT_PIN0_PORT26_Pos)                     /*!< GPIO_PORT PIN0: PORT26 Mask         */
#define GPIO_PORT_PIN0_PORT27_Pos                             27                                                        /*!< GPIO_PORT PIN0: PORT27 Position     */
#define GPIO_PORT_PIN0_PORT27_Msk                             (0x01UL << GPIO_PORT_PIN0_PORT27_Pos)                     /*!< GPIO_PORT PIN0: PORT27 Mask         */
#define GPIO_PORT_PIN0_PORT28_Pos                             28                                                        /*!< GPIO_PORT PIN0: PORT28 Position     */
#define GPIO_PORT_PIN0_PORT28_Msk                             (0x01UL << GPIO_PORT_PIN0_PORT28_Pos)                     /*!< GPIO_PORT PIN0: PORT28 Mask         */
#define GPIO_PORT_PIN0_PORT29_Pos                             29                                                        /*!< GPIO_PORT PIN0: PORT29 Position     */
#define GPIO_PORT_PIN0_PORT29_Msk                             (0x01UL << GPIO_PORT_PIN0_PORT29_Pos)                     /*!< GPIO_PORT PIN0: PORT29 Mask         */
#define GPIO_PORT_PIN0_PORT30_Pos                             30                                                        /*!< GPIO_PORT PIN0: PORT30 Position     */
#define GPIO_PORT_PIN0_PORT30_Msk                             (0x01UL << GPIO_PORT_PIN0_PORT30_Pos)                     /*!< GPIO_PORT PIN0: PORT30 Mask         */
#define GPIO_PORT_PIN0_PORT31_Pos                             31                                                        /*!< GPIO_PORT PIN0: PORT31 Position     */
#define GPIO_PORT_PIN0_PORT31_Msk                             (0x01UL << GPIO_PORT_PIN0_PORT31_Pos)                     /*!< GPIO_PORT PIN0: PORT31 Mask         */

// -------------------------------------  GPIO_PORT_PIN1  -----------------------------------------
#define GPIO_PORT_PIN1_PORT0_Pos                              0                                                         /*!< GPIO_PORT PIN1: PORT0 Position      */
#define GPIO_PORT_PIN1_PORT0_Msk                              (0x01UL << GPIO_PORT_PIN1_PORT0_Pos)                      /*!< GPIO_PORT PIN1: PORT0 Mask          */
#define GPIO_PORT_PIN1_PORT1_Pos                              1                                                         /*!< GPIO_PORT PIN1: PORT1 Position      */
#define GPIO_PORT_PIN1_PORT1_Msk                              (0x01UL << GPIO_PORT_PIN1_PORT1_Pos)                      /*!< GPIO_PORT PIN1: PORT1 Mask          */
#define GPIO_PORT_PIN1_PORT2_Pos                              2                                                         /*!< GPIO_PORT PIN1: PORT2 Position      */
#define GPIO_PORT_PIN1_PORT2_Msk                              (0x01UL << GPIO_PORT_PIN1_PORT2_Pos)                      /*!< GPIO_PORT PIN1: PORT2 Mask          */
#define GPIO_PORT_PIN1_PORT3_Pos                              3                                                         /*!< GPIO_PORT PIN1: PORT3 Position      */
#define GPIO_PORT_PIN1_PORT3_Msk                              (0x01UL << GPIO_PORT_PIN1_PORT3_Pos)                      /*!< GPIO_PORT PIN1: PORT3 Mask          */
#define GPIO_PORT_PIN1_PORT4_Pos                              4                                                         /*!< GPIO_PORT PIN1: PORT4 Position      */
#define GPIO_PORT_PIN1_PORT4_Msk                              (0x01UL << GPIO_PORT_PIN1_PORT4_Pos)                      /*!< GPIO_PORT PIN1: PORT4 Mask          */
#define GPIO_PORT_PIN1_PORT5_Pos                              5                                                         /*!< GPIO_PORT PIN1: PORT5 Position      */
#define GPIO_PORT_PIN1_PORT5_Msk                              (0x01UL << GPIO_PORT_PIN1_PORT5_Pos)                      /*!< GPIO_PORT PIN1: PORT5 Mask          */
#define GPIO_PORT_PIN1_PORT6_Pos                              6                                                         /*!< GPIO_PORT PIN1: PORT6 Position      */
#define GPIO_PORT_PIN1_PORT6_Msk                              (0x01UL << GPIO_PORT_PIN1_PORT6_Pos)                      /*!< GPIO_PORT PIN1: PORT6 Mask          */
#define GPIO_PORT_PIN1_PORT7_Pos                              7                                                         /*!< GPIO_PORT PIN1: PORT7 Position      */
#define GPIO_PORT_PIN1_PORT7_Msk                              (0x01UL << GPIO_PORT_PIN1_PORT7_Pos)                      /*!< GPIO_PORT PIN1: PORT7 Mask          */
#define GPIO_PORT_PIN1_PORT8_Pos                              8                                                         /*!< GPIO_PORT PIN1: PORT8 Position      */
#define GPIO_PORT_PIN1_PORT8_Msk                              (0x01UL << GPIO_PORT_PIN1_PORT8_Pos)                      /*!< GPIO_PORT PIN1: PORT8 Mask          */
#define GPIO_PORT_PIN1_PORT9_Pos                              9                                                         /*!< GPIO_PORT PIN1: PORT9 Position      */
#define GPIO_PORT_PIN1_PORT9_Msk                              (0x01UL << GPIO_PORT_PIN1_PORT9_Pos)                      /*!< GPIO_PORT PIN1: PORT9 Mask          */
#define GPIO_PORT_PIN1_PORT10_Pos                             10                                                        /*!< GPIO_PORT PIN1: PORT10 Position     */
#define GPIO_PORT_PIN1_PORT10_Msk                             (0x01UL << GPIO_PORT_PIN1_PORT10_Pos)                     /*!< GPIO_PORT PIN1: PORT10 Mask         */
#define GPIO_PORT_PIN1_PORT11_Pos                             11                                                        /*!< GPIO_PORT PIN1: PORT11 Position     */
#define GPIO_PORT_PIN1_PORT11_Msk                             (0x01UL << GPIO_PORT_PIN1_PORT11_Pos)                     /*!< GPIO_PORT PIN1: PORT11 Mask         */
#define GPIO_PORT_PIN1_PORT12_Pos                             12                                                        /*!< GPIO_PORT PIN1: PORT12 Position     */
#define GPIO_PORT_PIN1_PORT12_Msk                             (0x01UL << GPIO_PORT_PIN1_PORT12_Pos)                     /*!< GPIO_PORT PIN1: PORT12 Mask         */
#define GPIO_PORT_PIN1_PORT13_Pos                             13                                                        /*!< GPIO_PORT PIN1: PORT13 Position     */
#define GPIO_PORT_PIN1_PORT13_Msk                             (0x01UL << GPIO_PORT_PIN1_PORT13_Pos)                     /*!< GPIO_PORT PIN1: PORT13 Mask         */
#define GPIO_PORT_PIN1_PORT14_Pos                             14                                                        /*!< GPIO_PORT PIN1: PORT14 Position     */
#define GPIO_PORT_PIN1_PORT14_Msk                             (0x01UL << GPIO_PORT_PIN1_PORT14_Pos)                     /*!< GPIO_PORT PIN1: PORT14 Mask         */
#define GPIO_PORT_PIN1_PORT15_Pos                             15                                                        /*!< GPIO_PORT PIN1: PORT15 Position     */
#define GPIO_PORT_PIN1_PORT15_Msk                             (0x01UL << GPIO_PORT_PIN1_PORT15_Pos)                     /*!< GPIO_PORT PIN1: PORT15 Mask         */
#define GPIO_PORT_PIN1_PORT16_Pos                             16                                                        /*!< GPIO_PORT PIN1: PORT16 Position     */
#define GPIO_PORT_PIN1_PORT16_Msk                             (0x01UL << GPIO_PORT_PIN1_PORT16_Pos)                     /*!< GPIO_PORT PIN1: PORT16 Mask         */
#define GPIO_PORT_PIN1_PORT17_Pos                             17                                                        /*!< GPIO_PORT PIN1: PORT17 Position     */
#define GPIO_PORT_PIN1_PORT17_Msk                             (0x01UL << GPIO_PORT_PIN1_PORT17_Pos)                     /*!< GPIO_PORT PIN1: PORT17 Mask         */
#define GPIO_PORT_PIN1_PORT18_Pos                             18                                                        /*!< GPIO_PORT PIN1: PORT18 Position     */
#define GPIO_PORT_PIN1_PORT18_Msk                             (0x01UL << GPIO_PORT_PIN1_PORT18_Pos)                     /*!< GPIO_PORT PIN1: PORT18 Mask         */
#define GPIO_PORT_PIN1_PORT19_Pos                             19                                                        /*!< GPIO_PORT PIN1: PORT19 Position     */
#define GPIO_PORT_PIN1_PORT19_Msk                             (0x01UL << GPIO_PORT_PIN1_PORT19_Pos)                     /*!< GPIO_PORT PIN1: PORT19 Mask         */
#define GPIO_PORT_PIN1_PORT20_Pos                             20                                                        /*!< GPIO_PORT PIN1: PORT20 Position     */
#define GPIO_PORT_PIN1_PORT20_Msk                             (0x01UL << GPIO_PORT_PIN1_PORT20_Pos)                     /*!< GPIO_PORT PIN1: PORT20 Mask         */
#define GPIO_PORT_PIN1_PORT21_Pos                             21                                                        /*!< GPIO_PORT PIN1: PORT21 Position     */
#define GPIO_PORT_PIN1_PORT21_Msk                             (0x01UL << GPIO_PORT_PIN1_PORT21_Pos)                     /*!< GPIO_PORT PIN1: PORT21 Mask         */
#define GPIO_PORT_PIN1_PORT22_Pos                             22                                                        /*!< GPIO_PORT PIN1: PORT22 Position     */
#define GPIO_PORT_PIN1_PORT22_Msk                             (0x01UL << GPIO_PORT_PIN1_PORT22_Pos)                     /*!< GPIO_PORT PIN1: PORT22 Mask         */
#define GPIO_PORT_PIN1_PORT23_Pos                             23                                                        /*!< GPIO_PORT PIN1: PORT23 Position     */
#define GPIO_PORT_PIN1_PORT23_Msk                             (0x01UL << GPIO_PORT_PIN1_PORT23_Pos)                     /*!< GPIO_PORT PIN1: PORT23 Mask         */
#define GPIO_PORT_PIN1_PORT24_Pos                             24                                                        /*!< GPIO_PORT PIN1: PORT24 Position     */
#define GPIO_PORT_PIN1_PORT24_Msk                             (0x01UL << GPIO_PORT_PIN1_PORT24_Pos)                     /*!< GPIO_PORT PIN1: PORT24 Mask         */
#define GPIO_PORT_PIN1_PORT25_Pos                             25                                                        /*!< GPIO_PORT PIN1: PORT25 Position     */
#define GPIO_PORT_PIN1_PORT25_Msk                             (0x01UL << GPIO_PORT_PIN1_PORT25_Pos)                     /*!< GPIO_PORT PIN1: PORT25 Mask         */
#define GPIO_PORT_PIN1_PORT26_Pos                             26                                                        /*!< GPIO_PORT PIN1: PORT26 Position     */
#define GPIO_PORT_PIN1_PORT26_Msk                             (0x01UL << GPIO_PORT_PIN1_PORT26_Pos)                     /*!< GPIO_PORT PIN1: PORT26 Mask         */
#define GPIO_PORT_PIN1_PORT27_Pos                             27                                                        /*!< GPIO_PORT PIN1: PORT27 Position     */
#define GPIO_PORT_PIN1_PORT27_Msk                             (0x01UL << GPIO_PORT_PIN1_PORT27_Pos)                     /*!< GPIO_PORT PIN1: PORT27 Mask         */
#define GPIO_PORT_PIN1_PORT28_Pos                             28                                                        /*!< GPIO_PORT PIN1: PORT28 Position     */
#define GPIO_PORT_PIN1_PORT28_Msk                             (0x01UL << GPIO_PORT_PIN1_PORT28_Pos)                     /*!< GPIO_PORT PIN1: PORT28 Mask         */
#define GPIO_PORT_PIN1_PORT29_Pos                             29                                                        /*!< GPIO_PORT PIN1: PORT29 Position     */
#define GPIO_PORT_PIN1_PORT29_Msk                             (0x01UL << GPIO_PORT_PIN1_PORT29_Pos)                     /*!< GPIO_PORT PIN1: PORT29 Mask         */
#define GPIO_PORT_PIN1_PORT30_Pos                             30                                                        /*!< GPIO_PORT PIN1: PORT30 Position     */
#define GPIO_PORT_PIN1_PORT30_Msk                             (0x01UL << GPIO_PORT_PIN1_PORT30_Pos)                     /*!< GPIO_PORT PIN1: PORT30 Mask         */
#define GPIO_PORT_PIN1_PORT31_Pos                             31                                                        /*!< GPIO_PORT PIN1: PORT31 Position     */
#define GPIO_PORT_PIN1_PORT31_Msk                             (0x01UL << GPIO_PORT_PIN1_PORT31_Pos)                     /*!< GPIO_PORT PIN1: PORT31 Mask         */

// -------------------------------------  GPIO_PORT_PIN2  -----------------------------------------
#define GPIO_PORT_PIN2_PORT0_Pos                              0                                                         /*!< GPIO_PORT PIN2: PORT0 Position      */
#define GPIO_PORT_PIN2_PORT0_Msk                              (0x01UL << GPIO_PORT_PIN2_PORT0_Pos)                      /*!< GPIO_PORT PIN2: PORT0 Mask          */
#define GPIO_PORT_PIN2_PORT1_Pos                              1                                                         /*!< GPIO_PORT PIN2: PORT1 Position      */
#define GPIO_PORT_PIN2_PORT1_Msk                              (0x01UL << GPIO_PORT_PIN2_PORT1_Pos)                      /*!< GPIO_PORT PIN2: PORT1 Mask          */
#define GPIO_PORT_PIN2_PORT2_Pos                              2                                                         /*!< GPIO_PORT PIN2: PORT2 Position      */
#define GPIO_PORT_PIN2_PORT2_Msk                              (0x01UL << GPIO_PORT_PIN2_PORT2_Pos)                      /*!< GPIO_PORT PIN2: PORT2 Mask          */
#define GPIO_PORT_PIN2_PORT3_Pos                              3                                                         /*!< GPIO_PORT PIN2: PORT3 Position      */
#define GPIO_PORT_PIN2_PORT3_Msk                              (0x01UL << GPIO_PORT_PIN2_PORT3_Pos)                      /*!< GPIO_PORT PIN2: PORT3 Mask          */
#define GPIO_PORT_PIN2_PORT4_Pos                              4                                                         /*!< GPIO_PORT PIN2: PORT4 Position      */
#define GPIO_PORT_PIN2_PORT4_Msk                              (0x01UL << GPIO_PORT_PIN2_PORT4_Pos)                      /*!< GPIO_PORT PIN2: PORT4 Mask          */
#define GPIO_PORT_PIN2_PORT5_Pos                              5                                                         /*!< GPIO_PORT PIN2: PORT5 Position      */
#define GPIO_PORT_PIN2_PORT5_Msk                              (0x01UL << GPIO_PORT_PIN2_PORT5_Pos)                      /*!< GPIO_PORT PIN2: PORT5 Mask          */
#define GPIO_PORT_PIN2_PORT6_Pos                              6                                                         /*!< GPIO_PORT PIN2: PORT6 Position      */
#define GPIO_PORT_PIN2_PORT6_Msk                              (0x01UL << GPIO_PORT_PIN2_PORT6_Pos)                      /*!< GPIO_PORT PIN2: PORT6 Mask          */
#define GPIO_PORT_PIN2_PORT7_Pos                              7                                                         /*!< GPIO_PORT PIN2: PORT7 Position      */
#define GPIO_PORT_PIN2_PORT7_Msk                              (0x01UL << GPIO_PORT_PIN2_PORT7_Pos)                      /*!< GPIO_PORT PIN2: PORT7 Mask          */
#define GPIO_PORT_PIN2_PORT8_Pos                              8                                                         /*!< GPIO_PORT PIN2: PORT8 Position      */
#define GPIO_PORT_PIN2_PORT8_Msk                              (0x01UL << GPIO_PORT_PIN2_PORT8_Pos)                      /*!< GPIO_PORT PIN2: PORT8 Mask          */
#define GPIO_PORT_PIN2_PORT9_Pos                              9                                                         /*!< GPIO_PORT PIN2: PORT9 Position      */
#define GPIO_PORT_PIN2_PORT9_Msk                              (0x01UL << GPIO_PORT_PIN2_PORT9_Pos)                      /*!< GPIO_PORT PIN2: PORT9 Mask          */
#define GPIO_PORT_PIN2_PORT10_Pos                             10                                                        /*!< GPIO_PORT PIN2: PORT10 Position     */
#define GPIO_PORT_PIN2_PORT10_Msk                             (0x01UL << GPIO_PORT_PIN2_PORT10_Pos)                     /*!< GPIO_PORT PIN2: PORT10 Mask         */
#define GPIO_PORT_PIN2_PORT11_Pos                             11                                                        /*!< GPIO_PORT PIN2: PORT11 Position     */
#define GPIO_PORT_PIN2_PORT11_Msk                             (0x01UL << GPIO_PORT_PIN2_PORT11_Pos)                     /*!< GPIO_PORT PIN2: PORT11 Mask         */
#define GPIO_PORT_PIN2_PORT12_Pos                             12                                                        /*!< GPIO_PORT PIN2: PORT12 Position     */
#define GPIO_PORT_PIN2_PORT12_Msk                             (0x01UL << GPIO_PORT_PIN2_PORT12_Pos)                     /*!< GPIO_PORT PIN2: PORT12 Mask         */
#define GPIO_PORT_PIN2_PORT13_Pos                             13                                                        /*!< GPIO_PORT PIN2: PORT13 Position     */
#define GPIO_PORT_PIN2_PORT13_Msk                             (0x01UL << GPIO_PORT_PIN2_PORT13_Pos)                     /*!< GPIO_PORT PIN2: PORT13 Mask         */
#define GPIO_PORT_PIN2_PORT14_Pos                             14                                                        /*!< GPIO_PORT PIN2: PORT14 Position     */
#define GPIO_PORT_PIN2_PORT14_Msk                             (0x01UL << GPIO_PORT_PIN2_PORT14_Pos)                     /*!< GPIO_PORT PIN2: PORT14 Mask         */
#define GPIO_PORT_PIN2_PORT15_Pos                             15                                                        /*!< GPIO_PORT PIN2: PORT15 Position     */
#define GPIO_PORT_PIN2_PORT15_Msk                             (0x01UL << GPIO_PORT_PIN2_PORT15_Pos)                     /*!< GPIO_PORT PIN2: PORT15 Mask         */
#define GPIO_PORT_PIN2_PORT16_Pos                             16                                                        /*!< GPIO_PORT PIN2: PORT16 Position     */
#define GPIO_PORT_PIN2_PORT16_Msk                             (0x01UL << GPIO_PORT_PIN2_PORT16_Pos)                     /*!< GPIO_PORT PIN2: PORT16 Mask         */
#define GPIO_PORT_PIN2_PORT17_Pos                             17                                                        /*!< GPIO_PORT PIN2: PORT17 Position     */
#define GPIO_PORT_PIN2_PORT17_Msk                             (0x01UL << GPIO_PORT_PIN2_PORT17_Pos)                     /*!< GPIO_PORT PIN2: PORT17 Mask         */
#define GPIO_PORT_PIN2_PORT18_Pos                             18                                                        /*!< GPIO_PORT PIN2: PORT18 Position     */
#define GPIO_PORT_PIN2_PORT18_Msk                             (0x01UL << GPIO_PORT_PIN2_PORT18_Pos)                     /*!< GPIO_PORT PIN2: PORT18 Mask         */
#define GPIO_PORT_PIN2_PORT19_Pos                             19                                                        /*!< GPIO_PORT PIN2: PORT19 Position     */
#define GPIO_PORT_PIN2_PORT19_Msk                             (0x01UL << GPIO_PORT_PIN2_PORT19_Pos)                     /*!< GPIO_PORT PIN2: PORT19 Mask         */
#define GPIO_PORT_PIN2_PORT20_Pos                             20                                                        /*!< GPIO_PORT PIN2: PORT20 Position     */
#define GPIO_PORT_PIN2_PORT20_Msk                             (0x01UL << GPIO_PORT_PIN2_PORT20_Pos)                     /*!< GPIO_PORT PIN2: PORT20 Mask         */
#define GPIO_PORT_PIN2_PORT21_Pos                             21                                                        /*!< GPIO_PORT PIN2: PORT21 Position     */
#define GPIO_PORT_PIN2_PORT21_Msk                             (0x01UL << GPIO_PORT_PIN2_PORT21_Pos)                     /*!< GPIO_PORT PIN2: PORT21 Mask         */
#define GPIO_PORT_PIN2_PORT22_Pos                             22                                                        /*!< GPIO_PORT PIN2: PORT22 Position     */
#define GPIO_PORT_PIN2_PORT22_Msk                             (0x01UL << GPIO_PORT_PIN2_PORT22_Pos)                     /*!< GPIO_PORT PIN2: PORT22 Mask         */
#define GPIO_PORT_PIN2_PORT23_Pos                             23                                                        /*!< GPIO_PORT PIN2: PORT23 Position     */
#define GPIO_PORT_PIN2_PORT23_Msk                             (0x01UL << GPIO_PORT_PIN2_PORT23_Pos)                     /*!< GPIO_PORT PIN2: PORT23 Mask         */
#define GPIO_PORT_PIN2_PORT24_Pos                             24                                                        /*!< GPIO_PORT PIN2: PORT24 Position     */
#define GPIO_PORT_PIN2_PORT24_Msk                             (0x01UL << GPIO_PORT_PIN2_PORT24_Pos)                     /*!< GPIO_PORT PIN2: PORT24 Mask         */
#define GPIO_PORT_PIN2_PORT25_Pos                             25                                                        /*!< GPIO_PORT PIN2: PORT25 Position     */
#define GPIO_PORT_PIN2_PORT25_Msk                             (0x01UL << GPIO_PORT_PIN2_PORT25_Pos)                     /*!< GPIO_PORT PIN2: PORT25 Mask         */
#define GPIO_PORT_PIN2_PORT26_Pos                             26                                                        /*!< GPIO_PORT PIN2: PORT26 Position     */
#define GPIO_PORT_PIN2_PORT26_Msk                             (0x01UL << GPIO_PORT_PIN2_PORT26_Pos)                     /*!< GPIO_PORT PIN2: PORT26 Mask         */
#define GPIO_PORT_PIN2_PORT27_Pos                             27                                                        /*!< GPIO_PORT PIN2: PORT27 Position     */
#define GPIO_PORT_PIN2_PORT27_Msk                             (0x01UL << GPIO_PORT_PIN2_PORT27_Pos)                     /*!< GPIO_PORT PIN2: PORT27 Mask         */
#define GPIO_PORT_PIN2_PORT28_Pos                             28                                                        /*!< GPIO_PORT PIN2: PORT28 Position     */
#define GPIO_PORT_PIN2_PORT28_Msk                             (0x01UL << GPIO_PORT_PIN2_PORT28_Pos)                     /*!< GPIO_PORT PIN2: PORT28 Mask         */
#define GPIO_PORT_PIN2_PORT29_Pos                             29                                                        /*!< GPIO_PORT PIN2: PORT29 Position     */
#define GPIO_PORT_PIN2_PORT29_Msk                             (0x01UL << GPIO_PORT_PIN2_PORT29_Pos)                     /*!< GPIO_PORT PIN2: PORT29 Mask         */
#define GPIO_PORT_PIN2_PORT30_Pos                             30                                                        /*!< GPIO_PORT PIN2: PORT30 Position     */
#define GPIO_PORT_PIN2_PORT30_Msk                             (0x01UL << GPIO_PORT_PIN2_PORT30_Pos)                     /*!< GPIO_PORT PIN2: PORT30 Mask         */
#define GPIO_PORT_PIN2_PORT31_Pos                             31                                                        /*!< GPIO_PORT PIN2: PORT31 Position     */
#define GPIO_PORT_PIN2_PORT31_Msk                             (0x01UL << GPIO_PORT_PIN2_PORT31_Pos)                     /*!< GPIO_PORT PIN2: PORT31 Mask         */

// -------------------------------------  GPIO_PORT_PIN3  -----------------------------------------
#define GPIO_PORT_PIN3_PORT0_Pos                              0                                                         /*!< GPIO_PORT PIN3: PORT0 Position      */
#define GPIO_PORT_PIN3_PORT0_Msk                              (0x01UL << GPIO_PORT_PIN3_PORT0_Pos)                      /*!< GPIO_PORT PIN3: PORT0 Mask          */
#define GPIO_PORT_PIN3_PORT1_Pos                              1                                                         /*!< GPIO_PORT PIN3: PORT1 Position      */
#define GPIO_PORT_PIN3_PORT1_Msk                              (0x01UL << GPIO_PORT_PIN3_PORT1_Pos)                      /*!< GPIO_PORT PIN3: PORT1 Mask          */
#define GPIO_PORT_PIN3_PORT2_Pos                              2                                                         /*!< GPIO_PORT PIN3: PORT2 Position      */
#define GPIO_PORT_PIN3_PORT2_Msk                              (0x01UL << GPIO_PORT_PIN3_PORT2_Pos)                      /*!< GPIO_PORT PIN3: PORT2 Mask          */
#define GPIO_PORT_PIN3_PORT3_Pos                              3                                                         /*!< GPIO_PORT PIN3: PORT3 Position      */
#define GPIO_PORT_PIN3_PORT3_Msk                              (0x01UL << GPIO_PORT_PIN3_PORT3_Pos)                      /*!< GPIO_PORT PIN3: PORT3 Mask          */
#define GPIO_PORT_PIN3_PORT4_Pos                              4                                                         /*!< GPIO_PORT PIN3: PORT4 Position      */
#define GPIO_PORT_PIN3_PORT4_Msk                              (0x01UL << GPIO_PORT_PIN3_PORT4_Pos)                      /*!< GPIO_PORT PIN3: PORT4 Mask          */
#define GPIO_PORT_PIN3_PORT5_Pos                              5                                                         /*!< GPIO_PORT PIN3: PORT5 Position      */
#define GPIO_PORT_PIN3_PORT5_Msk                              (0x01UL << GPIO_PORT_PIN3_PORT5_Pos)                      /*!< GPIO_PORT PIN3: PORT5 Mask          */
#define GPIO_PORT_PIN3_PORT6_Pos                              6                                                         /*!< GPIO_PORT PIN3: PORT6 Position      */
#define GPIO_PORT_PIN3_PORT6_Msk                              (0x01UL << GPIO_PORT_PIN3_PORT6_Pos)                      /*!< GPIO_PORT PIN3: PORT6 Mask          */
#define GPIO_PORT_PIN3_PORT7_Pos                              7                                                         /*!< GPIO_PORT PIN3: PORT7 Position      */
#define GPIO_PORT_PIN3_PORT7_Msk                              (0x01UL << GPIO_PORT_PIN3_PORT7_Pos)                      /*!< GPIO_PORT PIN3: PORT7 Mask          */
#define GPIO_PORT_PIN3_PORT8_Pos                              8                                                         /*!< GPIO_PORT PIN3: PORT8 Position      */
#define GPIO_PORT_PIN3_PORT8_Msk                              (0x01UL << GPIO_PORT_PIN3_PORT8_Pos)                      /*!< GPIO_PORT PIN3: PORT8 Mask          */
#define GPIO_PORT_PIN3_PORT9_Pos                              9                                                         /*!< GPIO_PORT PIN3: PORT9 Position      */
#define GPIO_PORT_PIN3_PORT9_Msk                              (0x01UL << GPIO_PORT_PIN3_PORT9_Pos)                      /*!< GPIO_PORT PIN3: PORT9 Mask          */
#define GPIO_PORT_PIN3_PORT10_Pos                             10                                                        /*!< GPIO_PORT PIN3: PORT10 Position     */
#define GPIO_PORT_PIN3_PORT10_Msk                             (0x01UL << GPIO_PORT_PIN3_PORT10_Pos)                     /*!< GPIO_PORT PIN3: PORT10 Mask         */
#define GPIO_PORT_PIN3_PORT11_Pos                             11                                                        /*!< GPIO_PORT PIN3: PORT11 Position     */
#define GPIO_PORT_PIN3_PORT11_Msk                             (0x01UL << GPIO_PORT_PIN3_PORT11_Pos)                     /*!< GPIO_PORT PIN3: PORT11 Mask         */
#define GPIO_PORT_PIN3_PORT12_Pos                             12                                                        /*!< GPIO_PORT PIN3: PORT12 Position     */
#define GPIO_PORT_PIN3_PORT12_Msk                             (0x01UL << GPIO_PORT_PIN3_PORT12_Pos)                     /*!< GPIO_PORT PIN3: PORT12 Mask         */
#define GPIO_PORT_PIN3_PORT13_Pos                             13                                                        /*!< GPIO_PORT PIN3: PORT13 Position     */
#define GPIO_PORT_PIN3_PORT13_Msk                             (0x01UL << GPIO_PORT_PIN3_PORT13_Pos)                     /*!< GPIO_PORT PIN3: PORT13 Mask         */
#define GPIO_PORT_PIN3_PORT14_Pos                             14                                                        /*!< GPIO_PORT PIN3: PORT14 Position     */
#define GPIO_PORT_PIN3_PORT14_Msk                             (0x01UL << GPIO_PORT_PIN3_PORT14_Pos)                     /*!< GPIO_PORT PIN3: PORT14 Mask         */
#define GPIO_PORT_PIN3_PORT15_Pos                             15                                                        /*!< GPIO_PORT PIN3: PORT15 Position     */
#define GPIO_PORT_PIN3_PORT15_Msk                             (0x01UL << GPIO_PORT_PIN3_PORT15_Pos)                     /*!< GPIO_PORT PIN3: PORT15 Mask         */
#define GPIO_PORT_PIN3_PORT16_Pos                             16                                                        /*!< GPIO_PORT PIN3: PORT16 Position     */
#define GPIO_PORT_PIN3_PORT16_Msk                             (0x01UL << GPIO_PORT_PIN3_PORT16_Pos)                     /*!< GPIO_PORT PIN3: PORT16 Mask         */
#define GPIO_PORT_PIN3_PORT17_Pos                             17                                                        /*!< GPIO_PORT PIN3: PORT17 Position     */
#define GPIO_PORT_PIN3_PORT17_Msk                             (0x01UL << GPIO_PORT_PIN3_PORT17_Pos)                     /*!< GPIO_PORT PIN3: PORT17 Mask         */
#define GPIO_PORT_PIN3_PORT18_Pos                             18                                                        /*!< GPIO_PORT PIN3: PORT18 Position     */
#define GPIO_PORT_PIN3_PORT18_Msk                             (0x01UL << GPIO_PORT_PIN3_PORT18_Pos)                     /*!< GPIO_PORT PIN3: PORT18 Mask         */
#define GPIO_PORT_PIN3_PORT19_Pos                             19                                                        /*!< GPIO_PORT PIN3: PORT19 Position     */
#define GPIO_PORT_PIN3_PORT19_Msk                             (0x01UL << GPIO_PORT_PIN3_PORT19_Pos)                     /*!< GPIO_PORT PIN3: PORT19 Mask         */
#define GPIO_PORT_PIN3_PORT20_Pos                             20                                                        /*!< GPIO_PORT PIN3: PORT20 Position     */
#define GPIO_PORT_PIN3_PORT20_Msk                             (0x01UL << GPIO_PORT_PIN3_PORT20_Pos)                     /*!< GPIO_PORT PIN3: PORT20 Mask         */
#define GPIO_PORT_PIN3_PORT21_Pos                             21                                                        /*!< GPIO_PORT PIN3: PORT21 Position     */
#define GPIO_PORT_PIN3_PORT21_Msk                             (0x01UL << GPIO_PORT_PIN3_PORT21_Pos)                     /*!< GPIO_PORT PIN3: PORT21 Mask         */
#define GPIO_PORT_PIN3_PORT22_Pos                             22                                                        /*!< GPIO_PORT PIN3: PORT22 Position     */
#define GPIO_PORT_PIN3_PORT22_Msk                             (0x01UL << GPIO_PORT_PIN3_PORT22_Pos)                     /*!< GPIO_PORT PIN3: PORT22 Mask         */
#define GPIO_PORT_PIN3_PORT23_Pos                             23                                                        /*!< GPIO_PORT PIN3: PORT23 Position     */
#define GPIO_PORT_PIN3_PORT23_Msk                             (0x01UL << GPIO_PORT_PIN3_PORT23_Pos)                     /*!< GPIO_PORT PIN3: PORT23 Mask         */
#define GPIO_PORT_PIN3_PORT24_Pos                             24                                                        /*!< GPIO_PORT PIN3: PORT24 Position     */
#define GPIO_PORT_PIN3_PORT24_Msk                             (0x01UL << GPIO_PORT_PIN3_PORT24_Pos)                     /*!< GPIO_PORT PIN3: PORT24 Mask         */
#define GPIO_PORT_PIN3_PORT25_Pos                             25                                                        /*!< GPIO_PORT PIN3: PORT25 Position     */
#define GPIO_PORT_PIN3_PORT25_Msk                             (0x01UL << GPIO_PORT_PIN3_PORT25_Pos)                     /*!< GPIO_PORT PIN3: PORT25 Mask         */
#define GPIO_PORT_PIN3_PORT26_Pos                             26                                                        /*!< GPIO_PORT PIN3: PORT26 Position     */
#define GPIO_PORT_PIN3_PORT26_Msk                             (0x01UL << GPIO_PORT_PIN3_PORT26_Pos)                     /*!< GPIO_PORT PIN3: PORT26 Mask         */
#define GPIO_PORT_PIN3_PORT27_Pos                             27                                                        /*!< GPIO_PORT PIN3: PORT27 Position     */
#define GPIO_PORT_PIN3_PORT27_Msk                             (0x01UL << GPIO_PORT_PIN3_PORT27_Pos)                     /*!< GPIO_PORT PIN3: PORT27 Mask         */
#define GPIO_PORT_PIN3_PORT28_Pos                             28                                                        /*!< GPIO_PORT PIN3: PORT28 Position     */
#define GPIO_PORT_PIN3_PORT28_Msk                             (0x01UL << GPIO_PORT_PIN3_PORT28_Pos)                     /*!< GPIO_PORT PIN3: PORT28 Mask         */
#define GPIO_PORT_PIN3_PORT29_Pos                             29                                                        /*!< GPIO_PORT PIN3: PORT29 Position     */
#define GPIO_PORT_PIN3_PORT29_Msk                             (0x01UL << GPIO_PORT_PIN3_PORT29_Pos)                     /*!< GPIO_PORT PIN3: PORT29 Mask         */
#define GPIO_PORT_PIN3_PORT30_Pos                             30                                                        /*!< GPIO_PORT PIN3: PORT30 Position     */
#define GPIO_PORT_PIN3_PORT30_Msk                             (0x01UL << GPIO_PORT_PIN3_PORT30_Pos)                     /*!< GPIO_PORT PIN3: PORT30 Mask         */
#define GPIO_PORT_PIN3_PORT31_Pos                             31                                                        /*!< GPIO_PORT PIN3: PORT31 Position     */
#define GPIO_PORT_PIN3_PORT31_Msk                             (0x01UL << GPIO_PORT_PIN3_PORT31_Pos)                     /*!< GPIO_PORT PIN3: PORT31 Mask         */

// -------------------------------------  GPIO_PORT_PIN4  -----------------------------------------
#define GPIO_PORT_PIN4_PORT0_Pos                              0                                                         /*!< GPIO_PORT PIN4: PORT0 Position      */
#define GPIO_PORT_PIN4_PORT0_Msk                              (0x01UL << GPIO_PORT_PIN4_PORT0_Pos)                      /*!< GPIO_PORT PIN4: PORT0 Mask          */
#define GPIO_PORT_PIN4_PORT1_Pos                              1                                                         /*!< GPIO_PORT PIN4: PORT1 Position      */
#define GPIO_PORT_PIN4_PORT1_Msk                              (0x01UL << GPIO_PORT_PIN4_PORT1_Pos)                      /*!< GPIO_PORT PIN4: PORT1 Mask          */
#define GPIO_PORT_PIN4_PORT2_Pos                              2                                                         /*!< GPIO_PORT PIN4: PORT2 Position      */
#define GPIO_PORT_PIN4_PORT2_Msk                              (0x01UL << GPIO_PORT_PIN4_PORT2_Pos)                      /*!< GPIO_PORT PIN4: PORT2 Mask          */
#define GPIO_PORT_PIN4_PORT3_Pos                              3                                                         /*!< GPIO_PORT PIN4: PORT3 Position      */
#define GPIO_PORT_PIN4_PORT3_Msk                              (0x01UL << GPIO_PORT_PIN4_PORT3_Pos)                      /*!< GPIO_PORT PIN4: PORT3 Mask          */
#define GPIO_PORT_PIN4_PORT4_Pos                              4                                                         /*!< GPIO_PORT PIN4: PORT4 Position      */
#define GPIO_PORT_PIN4_PORT4_Msk                              (0x01UL << GPIO_PORT_PIN4_PORT4_Pos)                      /*!< GPIO_PORT PIN4: PORT4 Mask          */
#define GPIO_PORT_PIN4_PORT5_Pos                              5                                                         /*!< GPIO_PORT PIN4: PORT5 Position      */
#define GPIO_PORT_PIN4_PORT5_Msk                              (0x01UL << GPIO_PORT_PIN4_PORT5_Pos)                      /*!< GPIO_PORT PIN4: PORT5 Mask          */
#define GPIO_PORT_PIN4_PORT6_Pos                              6                                                         /*!< GPIO_PORT PIN4: PORT6 Position      */
#define GPIO_PORT_PIN4_PORT6_Msk                              (0x01UL << GPIO_PORT_PIN4_PORT6_Pos)                      /*!< GPIO_PORT PIN4: PORT6 Mask          */
#define GPIO_PORT_PIN4_PORT7_Pos                              7                                                         /*!< GPIO_PORT PIN4: PORT7 Position      */
#define GPIO_PORT_PIN4_PORT7_Msk                              (0x01UL << GPIO_PORT_PIN4_PORT7_Pos)                      /*!< GPIO_PORT PIN4: PORT7 Mask          */
#define GPIO_PORT_PIN4_PORT8_Pos                              8                                                         /*!< GPIO_PORT PIN4: PORT8 Position      */
#define GPIO_PORT_PIN4_PORT8_Msk                              (0x01UL << GPIO_PORT_PIN4_PORT8_Pos)                      /*!< GPIO_PORT PIN4: PORT8 Mask          */
#define GPIO_PORT_PIN4_PORT9_Pos                              9                                                         /*!< GPIO_PORT PIN4: PORT9 Position      */
#define GPIO_PORT_PIN4_PORT9_Msk                              (0x01UL << GPIO_PORT_PIN4_PORT9_Pos)                      /*!< GPIO_PORT PIN4: PORT9 Mask          */
#define GPIO_PORT_PIN4_PORT10_Pos                             10                                                        /*!< GPIO_PORT PIN4: PORT10 Position     */
#define GPIO_PORT_PIN4_PORT10_Msk                             (0x01UL << GPIO_PORT_PIN4_PORT10_Pos)                     /*!< GPIO_PORT PIN4: PORT10 Mask         */
#define GPIO_PORT_PIN4_PORT11_Pos                             11                                                        /*!< GPIO_PORT PIN4: PORT11 Position     */
#define GPIO_PORT_PIN4_PORT11_Msk                             (0x01UL << GPIO_PORT_PIN4_PORT11_Pos)                     /*!< GPIO_PORT PIN4: PORT11 Mask         */
#define GPIO_PORT_PIN4_PORT12_Pos                             12                                                        /*!< GPIO_PORT PIN4: PORT12 Position     */
#define GPIO_PORT_PIN4_PORT12_Msk                             (0x01UL << GPIO_PORT_PIN4_PORT12_Pos)                     /*!< GPIO_PORT PIN4: PORT12 Mask         */
#define GPIO_PORT_PIN4_PORT13_Pos                             13                                                        /*!< GPIO_PORT PIN4: PORT13 Position     */
#define GPIO_PORT_PIN4_PORT13_Msk                             (0x01UL << GPIO_PORT_PIN4_PORT13_Pos)                     /*!< GPIO_PORT PIN4: PORT13 Mask         */
#define GPIO_PORT_PIN4_PORT14_Pos                             14                                                        /*!< GPIO_PORT PIN4: PORT14 Position     */
#define GPIO_PORT_PIN4_PORT14_Msk                             (0x01UL << GPIO_PORT_PIN4_PORT14_Pos)                     /*!< GPIO_PORT PIN4: PORT14 Mask         */
#define GPIO_PORT_PIN4_PORT15_Pos                             15                                                        /*!< GPIO_PORT PIN4: PORT15 Position     */
#define GPIO_PORT_PIN4_PORT15_Msk                             (0x01UL << GPIO_PORT_PIN4_PORT15_Pos)                     /*!< GPIO_PORT PIN4: PORT15 Mask         */
#define GPIO_PORT_PIN4_PORT16_Pos                             16                                                        /*!< GPIO_PORT PIN4: PORT16 Position     */
#define GPIO_PORT_PIN4_PORT16_Msk                             (0x01UL << GPIO_PORT_PIN4_PORT16_Pos)                     /*!< GPIO_PORT PIN4: PORT16 Mask         */
#define GPIO_PORT_PIN4_PORT17_Pos                             17                                                        /*!< GPIO_PORT PIN4: PORT17 Position     */
#define GPIO_PORT_PIN4_PORT17_Msk                             (0x01UL << GPIO_PORT_PIN4_PORT17_Pos)                     /*!< GPIO_PORT PIN4: PORT17 Mask         */
#define GPIO_PORT_PIN4_PORT18_Pos                             18                                                        /*!< GPIO_PORT PIN4: PORT18 Position     */
#define GPIO_PORT_PIN4_PORT18_Msk                             (0x01UL << GPIO_PORT_PIN4_PORT18_Pos)                     /*!< GPIO_PORT PIN4: PORT18 Mask         */
#define GPIO_PORT_PIN4_PORT19_Pos                             19                                                        /*!< GPIO_PORT PIN4: PORT19 Position     */
#define GPIO_PORT_PIN4_PORT19_Msk                             (0x01UL << GPIO_PORT_PIN4_PORT19_Pos)                     /*!< GPIO_PORT PIN4: PORT19 Mask         */
#define GPIO_PORT_PIN4_PORT20_Pos                             20                                                        /*!< GPIO_PORT PIN4: PORT20 Position     */
#define GPIO_PORT_PIN4_PORT20_Msk                             (0x01UL << GPIO_PORT_PIN4_PORT20_Pos)                     /*!< GPIO_PORT PIN4: PORT20 Mask         */
#define GPIO_PORT_PIN4_PORT21_Pos                             21                                                        /*!< GPIO_PORT PIN4: PORT21 Position     */
#define GPIO_PORT_PIN4_PORT21_Msk                             (0x01UL << GPIO_PORT_PIN4_PORT21_Pos)                     /*!< GPIO_PORT PIN4: PORT21 Mask         */
#define GPIO_PORT_PIN4_PORT22_Pos                             22                                                        /*!< GPIO_PORT PIN4: PORT22 Position     */
#define GPIO_PORT_PIN4_PORT22_Msk                             (0x01UL << GPIO_PORT_PIN4_PORT22_Pos)                     /*!< GPIO_PORT PIN4: PORT22 Mask         */
#define GPIO_PORT_PIN4_PORT23_Pos                             23                                                        /*!< GPIO_PORT PIN4: PORT23 Position     */
#define GPIO_PORT_PIN4_PORT23_Msk                             (0x01UL << GPIO_PORT_PIN4_PORT23_Pos)                     /*!< GPIO_PORT PIN4: PORT23 Mask         */
#define GPIO_PORT_PIN4_PORT24_Pos                             24                                                        /*!< GPIO_PORT PIN4: PORT24 Position     */
#define GPIO_PORT_PIN4_PORT24_Msk                             (0x01UL << GPIO_PORT_PIN4_PORT24_Pos)                     /*!< GPIO_PORT PIN4: PORT24 Mask         */
#define GPIO_PORT_PIN4_PORT25_Pos                             25                                                        /*!< GPIO_PORT PIN4: PORT25 Position     */
#define GPIO_PORT_PIN4_PORT25_Msk                             (0x01UL << GPIO_PORT_PIN4_PORT25_Pos)                     /*!< GPIO_PORT PIN4: PORT25 Mask         */
#define GPIO_PORT_PIN4_PORT26_Pos                             26                                                        /*!< GPIO_PORT PIN4: PORT26 Position     */
#define GPIO_PORT_PIN4_PORT26_Msk                             (0x01UL << GPIO_PORT_PIN4_PORT26_Pos)                     /*!< GPIO_PORT PIN4: PORT26 Mask         */
#define GPIO_PORT_PIN4_PORT27_Pos                             27                                                        /*!< GPIO_PORT PIN4: PORT27 Position     */
#define GPIO_PORT_PIN4_PORT27_Msk                             (0x01UL << GPIO_PORT_PIN4_PORT27_Pos)                     /*!< GPIO_PORT PIN4: PORT27 Mask         */
#define GPIO_PORT_PIN4_PORT28_Pos                             28                                                        /*!< GPIO_PORT PIN4: PORT28 Position     */
#define GPIO_PORT_PIN4_PORT28_Msk                             (0x01UL << GPIO_PORT_PIN4_PORT28_Pos)                     /*!< GPIO_PORT PIN4: PORT28 Mask         */
#define GPIO_PORT_PIN4_PORT29_Pos                             29                                                        /*!< GPIO_PORT PIN4: PORT29 Position     */
#define GPIO_PORT_PIN4_PORT29_Msk                             (0x01UL << GPIO_PORT_PIN4_PORT29_Pos)                     /*!< GPIO_PORT PIN4: PORT29 Mask         */
#define GPIO_PORT_PIN4_PORT30_Pos                             30                                                        /*!< GPIO_PORT PIN4: PORT30 Position     */
#define GPIO_PORT_PIN4_PORT30_Msk                             (0x01UL << GPIO_PORT_PIN4_PORT30_Pos)                     /*!< GPIO_PORT PIN4: PORT30 Mask         */
#define GPIO_PORT_PIN4_PORT31_Pos                             31                                                        /*!< GPIO_PORT PIN4: PORT31 Position     */
#define GPIO_PORT_PIN4_PORT31_Msk                             (0x01UL << GPIO_PORT_PIN4_PORT31_Pos)                     /*!< GPIO_PORT PIN4: PORT31 Mask         */

// -------------------------------------  GPIO_PORT_PIN5  -----------------------------------------
#define GPIO_PORT_PIN5_PORT0_Pos                              0                                                         /*!< GPIO_PORT PIN5: PORT0 Position      */
#define GPIO_PORT_PIN5_PORT0_Msk                              (0x01UL << GPIO_PORT_PIN5_PORT0_Pos)                      /*!< GPIO_PORT PIN5: PORT0 Mask          */
#define GPIO_PORT_PIN5_PORT1_Pos                              1                                                         /*!< GPIO_PORT PIN5: PORT1 Position      */
#define GPIO_PORT_PIN5_PORT1_Msk                              (0x01UL << GPIO_PORT_PIN5_PORT1_Pos)                      /*!< GPIO_PORT PIN5: PORT1 Mask          */
#define GPIO_PORT_PIN5_PORT2_Pos                              2                                                         /*!< GPIO_PORT PIN5: PORT2 Position      */
#define GPIO_PORT_PIN5_PORT2_Msk                              (0x01UL << GPIO_PORT_PIN5_PORT2_Pos)                      /*!< GPIO_PORT PIN5: PORT2 Mask          */
#define GPIO_PORT_PIN5_PORT3_Pos                              3                                                         /*!< GPIO_PORT PIN5: PORT3 Position      */
#define GPIO_PORT_PIN5_PORT3_Msk                              (0x01UL << GPIO_PORT_PIN5_PORT3_Pos)                      /*!< GPIO_PORT PIN5: PORT3 Mask          */
#define GPIO_PORT_PIN5_PORT4_Pos                              4                                                         /*!< GPIO_PORT PIN5: PORT4 Position      */
#define GPIO_PORT_PIN5_PORT4_Msk                              (0x01UL << GPIO_PORT_PIN5_PORT4_Pos)                      /*!< GPIO_PORT PIN5: PORT4 Mask          */
#define GPIO_PORT_PIN5_PORT5_Pos                              5                                                         /*!< GPIO_PORT PIN5: PORT5 Position      */
#define GPIO_PORT_PIN5_PORT5_Msk                              (0x01UL << GPIO_PORT_PIN5_PORT5_Pos)                      /*!< GPIO_PORT PIN5: PORT5 Mask          */
#define GPIO_PORT_PIN5_PORT6_Pos                              6                                                         /*!< GPIO_PORT PIN5: PORT6 Position      */
#define GPIO_PORT_PIN5_PORT6_Msk                              (0x01UL << GPIO_PORT_PIN5_PORT6_Pos)                      /*!< GPIO_PORT PIN5: PORT6 Mask          */
#define GPIO_PORT_PIN5_PORT7_Pos                              7                                                         /*!< GPIO_PORT PIN5: PORT7 Position      */
#define GPIO_PORT_PIN5_PORT7_Msk                              (0x01UL << GPIO_PORT_PIN5_PORT7_Pos)                      /*!< GPIO_PORT PIN5: PORT7 Mask          */
#define GPIO_PORT_PIN5_PORT8_Pos                              8                                                         /*!< GPIO_PORT PIN5: PORT8 Position      */
#define GPIO_PORT_PIN5_PORT8_Msk                              (0x01UL << GPIO_PORT_PIN5_PORT8_Pos)                      /*!< GPIO_PORT PIN5: PORT8 Mask          */
#define GPIO_PORT_PIN5_PORT9_Pos                              9                                                         /*!< GPIO_PORT PIN5: PORT9 Position      */
#define GPIO_PORT_PIN5_PORT9_Msk                              (0x01UL << GPIO_PORT_PIN5_PORT9_Pos)                      /*!< GPIO_PORT PIN5: PORT9 Mask          */
#define GPIO_PORT_PIN5_PORT10_Pos                             10                                                        /*!< GPIO_PORT PIN5: PORT10 Position     */
#define GPIO_PORT_PIN5_PORT10_Msk                             (0x01UL << GPIO_PORT_PIN5_PORT10_Pos)                     /*!< GPIO_PORT PIN5: PORT10 Mask         */
#define GPIO_PORT_PIN5_PORT11_Pos                             11                                                        /*!< GPIO_PORT PIN5: PORT11 Position     */
#define GPIO_PORT_PIN5_PORT11_Msk                             (0x01UL << GPIO_PORT_PIN5_PORT11_Pos)                     /*!< GPIO_PORT PIN5: PORT11 Mask         */
#define GPIO_PORT_PIN5_PORT12_Pos                             12                                                        /*!< GPIO_PORT PIN5: PORT12 Position     */
#define GPIO_PORT_PIN5_PORT12_Msk                             (0x01UL << GPIO_PORT_PIN5_PORT12_Pos)                     /*!< GPIO_PORT PIN5: PORT12 Mask         */
#define GPIO_PORT_PIN5_PORT13_Pos                             13                                                        /*!< GPIO_PORT PIN5: PORT13 Position     */
#define GPIO_PORT_PIN5_PORT13_Msk                             (0x01UL << GPIO_PORT_PIN5_PORT13_Pos)                     /*!< GPIO_PORT PIN5: PORT13 Mask         */
#define GPIO_PORT_PIN5_PORT14_Pos                             14                                                        /*!< GPIO_PORT PIN5: PORT14 Position     */
#define GPIO_PORT_PIN5_PORT14_Msk                             (0x01UL << GPIO_PORT_PIN5_PORT14_Pos)                     /*!< GPIO_PORT PIN5: PORT14 Mask         */
#define GPIO_PORT_PIN5_PORT15_Pos                             15                                                        /*!< GPIO_PORT PIN5: PORT15 Position     */
#define GPIO_PORT_PIN5_PORT15_Msk                             (0x01UL << GPIO_PORT_PIN5_PORT15_Pos)                     /*!< GPIO_PORT PIN5: PORT15 Mask         */
#define GPIO_PORT_PIN5_PORT16_Pos                             16                                                        /*!< GPIO_PORT PIN5: PORT16 Position     */
#define GPIO_PORT_PIN5_PORT16_Msk                             (0x01UL << GPIO_PORT_PIN5_PORT16_Pos)                     /*!< GPIO_PORT PIN5: PORT16 Mask         */
#define GPIO_PORT_PIN5_PORT17_Pos                             17                                                        /*!< GPIO_PORT PIN5: PORT17 Position     */
#define GPIO_PORT_PIN5_PORT17_Msk                             (0x01UL << GPIO_PORT_PIN5_PORT17_Pos)                     /*!< GPIO_PORT PIN5: PORT17 Mask         */
#define GPIO_PORT_PIN5_PORT18_Pos                             18                                                        /*!< GPIO_PORT PIN5: PORT18 Position     */
#define GPIO_PORT_PIN5_PORT18_Msk                             (0x01UL << GPIO_PORT_PIN5_PORT18_Pos)                     /*!< GPIO_PORT PIN5: PORT18 Mask         */
#define GPIO_PORT_PIN5_PORT19_Pos                             19                                                        /*!< GPIO_PORT PIN5: PORT19 Position     */
#define GPIO_PORT_PIN5_PORT19_Msk                             (0x01UL << GPIO_PORT_PIN5_PORT19_Pos)                     /*!< GPIO_PORT PIN5: PORT19 Mask         */
#define GPIO_PORT_PIN5_PORT20_Pos                             20                                                        /*!< GPIO_PORT PIN5: PORT20 Position     */
#define GPIO_PORT_PIN5_PORT20_Msk                             (0x01UL << GPIO_PORT_PIN5_PORT20_Pos)                     /*!< GPIO_PORT PIN5: PORT20 Mask         */
#define GPIO_PORT_PIN5_PORT21_Pos                             21                                                        /*!< GPIO_PORT PIN5: PORT21 Position     */
#define GPIO_PORT_PIN5_PORT21_Msk                             (0x01UL << GPIO_PORT_PIN5_PORT21_Pos)                     /*!< GPIO_PORT PIN5: PORT21 Mask         */
#define GPIO_PORT_PIN5_PORT22_Pos                             22                                                        /*!< GPIO_PORT PIN5: PORT22 Position     */
#define GPIO_PORT_PIN5_PORT22_Msk                             (0x01UL << GPIO_PORT_PIN5_PORT22_Pos)                     /*!< GPIO_PORT PIN5: PORT22 Mask         */
#define GPIO_PORT_PIN5_PORT23_Pos                             23                                                        /*!< GPIO_PORT PIN5: PORT23 Position     */
#define GPIO_PORT_PIN5_PORT23_Msk                             (0x01UL << GPIO_PORT_PIN5_PORT23_Pos)                     /*!< GPIO_PORT PIN5: PORT23 Mask         */
#define GPIO_PORT_PIN5_PORT24_Pos                             24                                                        /*!< GPIO_PORT PIN5: PORT24 Position     */
#define GPIO_PORT_PIN5_PORT24_Msk                             (0x01UL << GPIO_PORT_PIN5_PORT24_Pos)                     /*!< GPIO_PORT PIN5: PORT24 Mask         */
#define GPIO_PORT_PIN5_PORT25_Pos                             25                                                        /*!< GPIO_PORT PIN5: PORT25 Position     */
#define GPIO_PORT_PIN5_PORT25_Msk                             (0x01UL << GPIO_PORT_PIN5_PORT25_Pos)                     /*!< GPIO_PORT PIN5: PORT25 Mask         */
#define GPIO_PORT_PIN5_PORT26_Pos                             26                                                        /*!< GPIO_PORT PIN5: PORT26 Position     */
#define GPIO_PORT_PIN5_PORT26_Msk                             (0x01UL << GPIO_PORT_PIN5_PORT26_Pos)                     /*!< GPIO_PORT PIN5: PORT26 Mask         */
#define GPIO_PORT_PIN5_PORT27_Pos                             27                                                        /*!< GPIO_PORT PIN5: PORT27 Position     */
#define GPIO_PORT_PIN5_PORT27_Msk                             (0x01UL << GPIO_PORT_PIN5_PORT27_Pos)                     /*!< GPIO_PORT PIN5: PORT27 Mask         */
#define GPIO_PORT_PIN5_PORT28_Pos                             28                                                        /*!< GPIO_PORT PIN5: PORT28 Position     */
#define GPIO_PORT_PIN5_PORT28_Msk                             (0x01UL << GPIO_PORT_PIN5_PORT28_Pos)                     /*!< GPIO_PORT PIN5: PORT28 Mask         */
#define GPIO_PORT_PIN5_PORT29_Pos                             29                                                        /*!< GPIO_PORT PIN5: PORT29 Position     */
#define GPIO_PORT_PIN5_PORT29_Msk                             (0x01UL << GPIO_PORT_PIN5_PORT29_Pos)                     /*!< GPIO_PORT PIN5: PORT29 Mask         */
#define GPIO_PORT_PIN5_PORT30_Pos                             30                                                        /*!< GPIO_PORT PIN5: PORT30 Position     */
#define GPIO_PORT_PIN5_PORT30_Msk                             (0x01UL << GPIO_PORT_PIN5_PORT30_Pos)                     /*!< GPIO_PORT PIN5: PORT30 Mask         */
#define GPIO_PORT_PIN5_PORT31_Pos                             31                                                        /*!< GPIO_PORT PIN5: PORT31 Position     */
#define GPIO_PORT_PIN5_PORT31_Msk                             (0x01UL << GPIO_PORT_PIN5_PORT31_Pos)                     /*!< GPIO_PORT PIN5: PORT31 Mask         */

// -------------------------------------  GPIO_PORT_PIN6  -----------------------------------------
#define GPIO_PORT_PIN6_PORT0_Pos                              0                                                         /*!< GPIO_PORT PIN6: PORT0 Position      */
#define GPIO_PORT_PIN6_PORT0_Msk                              (0x01UL << GPIO_PORT_PIN6_PORT0_Pos)                      /*!< GPIO_PORT PIN6: PORT0 Mask          */
#define GPIO_PORT_PIN6_PORT1_Pos                              1                                                         /*!< GPIO_PORT PIN6: PORT1 Position      */
#define GPIO_PORT_PIN6_PORT1_Msk                              (0x01UL << GPIO_PORT_PIN6_PORT1_Pos)                      /*!< GPIO_PORT PIN6: PORT1 Mask          */
#define GPIO_PORT_PIN6_PORT2_Pos                              2                                                         /*!< GPIO_PORT PIN6: PORT2 Position      */
#define GPIO_PORT_PIN6_PORT2_Msk                              (0x01UL << GPIO_PORT_PIN6_PORT2_Pos)                      /*!< GPIO_PORT PIN6: PORT2 Mask          */
#define GPIO_PORT_PIN6_PORT3_Pos                              3                                                         /*!< GPIO_PORT PIN6: PORT3 Position      */
#define GPIO_PORT_PIN6_PORT3_Msk                              (0x01UL << GPIO_PORT_PIN6_PORT3_Pos)                      /*!< GPIO_PORT PIN6: PORT3 Mask          */
#define GPIO_PORT_PIN6_PORT4_Pos                              4                                                         /*!< GPIO_PORT PIN6: PORT4 Position      */
#define GPIO_PORT_PIN6_PORT4_Msk                              (0x01UL << GPIO_PORT_PIN6_PORT4_Pos)                      /*!< GPIO_PORT PIN6: PORT4 Mask          */
#define GPIO_PORT_PIN6_PORT5_Pos                              5                                                         /*!< GPIO_PORT PIN6: PORT5 Position      */
#define GPIO_PORT_PIN6_PORT5_Msk                              (0x01UL << GPIO_PORT_PIN6_PORT5_Pos)                      /*!< GPIO_PORT PIN6: PORT5 Mask          */
#define GPIO_PORT_PIN6_PORT6_Pos                              6                                                         /*!< GPIO_PORT PIN6: PORT6 Position      */
#define GPIO_PORT_PIN6_PORT6_Msk                              (0x01UL << GPIO_PORT_PIN6_PORT6_Pos)                      /*!< GPIO_PORT PIN6: PORT6 Mask          */
#define GPIO_PORT_PIN6_PORT7_Pos                              7                                                         /*!< GPIO_PORT PIN6: PORT7 Position      */
#define GPIO_PORT_PIN6_PORT7_Msk                              (0x01UL << GPIO_PORT_PIN6_PORT7_Pos)                      /*!< GPIO_PORT PIN6: PORT7 Mask          */
#define GPIO_PORT_PIN6_PORT8_Pos                              8                                                         /*!< GPIO_PORT PIN6: PORT8 Position      */
#define GPIO_PORT_PIN6_PORT8_Msk                              (0x01UL << GPIO_PORT_PIN6_PORT8_Pos)                      /*!< GPIO_PORT PIN6: PORT8 Mask          */
#define GPIO_PORT_PIN6_PORT9_Pos                              9                                                         /*!< GPIO_PORT PIN6: PORT9 Position      */
#define GPIO_PORT_PIN6_PORT9_Msk                              (0x01UL << GPIO_PORT_PIN6_PORT9_Pos)                      /*!< GPIO_PORT PIN6: PORT9 Mask          */
#define GPIO_PORT_PIN6_PORT10_Pos                             10                                                        /*!< GPIO_PORT PIN6: PORT10 Position     */
#define GPIO_PORT_PIN6_PORT10_Msk                             (0x01UL << GPIO_PORT_PIN6_PORT10_Pos)                     /*!< GPIO_PORT PIN6: PORT10 Mask         */
#define GPIO_PORT_PIN6_PORT11_Pos                             11                                                        /*!< GPIO_PORT PIN6: PORT11 Position     */
#define GPIO_PORT_PIN6_PORT11_Msk                             (0x01UL << GPIO_PORT_PIN6_PORT11_Pos)                     /*!< GPIO_PORT PIN6: PORT11 Mask         */
#define GPIO_PORT_PIN6_PORT12_Pos                             12                                                        /*!< GPIO_PORT PIN6: PORT12 Position     */
#define GPIO_PORT_PIN6_PORT12_Msk                             (0x01UL << GPIO_PORT_PIN6_PORT12_Pos)                     /*!< GPIO_PORT PIN6: PORT12 Mask         */
#define GPIO_PORT_PIN6_PORT13_Pos                             13                                                        /*!< GPIO_PORT PIN6: PORT13 Position     */
#define GPIO_PORT_PIN6_PORT13_Msk                             (0x01UL << GPIO_PORT_PIN6_PORT13_Pos)                     /*!< GPIO_PORT PIN6: PORT13 Mask         */
#define GPIO_PORT_PIN6_PORT14_Pos                             14                                                        /*!< GPIO_PORT PIN6: PORT14 Position     */
#define GPIO_PORT_PIN6_PORT14_Msk                             (0x01UL << GPIO_PORT_PIN6_PORT14_Pos)                     /*!< GPIO_PORT PIN6: PORT14 Mask         */
#define GPIO_PORT_PIN6_PORT15_Pos                             15                                                        /*!< GPIO_PORT PIN6: PORT15 Position     */
#define GPIO_PORT_PIN6_PORT15_Msk                             (0x01UL << GPIO_PORT_PIN6_PORT15_Pos)                     /*!< GPIO_PORT PIN6: PORT15 Mask         */
#define GPIO_PORT_PIN6_PORT16_Pos                             16                                                        /*!< GPIO_PORT PIN6: PORT16 Position     */
#define GPIO_PORT_PIN6_PORT16_Msk                             (0x01UL << GPIO_PORT_PIN6_PORT16_Pos)                     /*!< GPIO_PORT PIN6: PORT16 Mask         */
#define GPIO_PORT_PIN6_PORT17_Pos                             17                                                        /*!< GPIO_PORT PIN6: PORT17 Position     */
#define GPIO_PORT_PIN6_PORT17_Msk                             (0x01UL << GPIO_PORT_PIN6_PORT17_Pos)                     /*!< GPIO_PORT PIN6: PORT17 Mask         */
#define GPIO_PORT_PIN6_PORT18_Pos                             18                                                        /*!< GPIO_PORT PIN6: PORT18 Position     */
#define GPIO_PORT_PIN6_PORT18_Msk                             (0x01UL << GPIO_PORT_PIN6_PORT18_Pos)                     /*!< GPIO_PORT PIN6: PORT18 Mask         */
#define GPIO_PORT_PIN6_PORT19_Pos                             19                                                        /*!< GPIO_PORT PIN6: PORT19 Position     */
#define GPIO_PORT_PIN6_PORT19_Msk                             (0x01UL << GPIO_PORT_PIN6_PORT19_Pos)                     /*!< GPIO_PORT PIN6: PORT19 Mask         */
#define GPIO_PORT_PIN6_PORT20_Pos                             20                                                        /*!< GPIO_PORT PIN6: PORT20 Position     */
#define GPIO_PORT_PIN6_PORT20_Msk                             (0x01UL << GPIO_PORT_PIN6_PORT20_Pos)                     /*!< GPIO_PORT PIN6: PORT20 Mask         */
#define GPIO_PORT_PIN6_PORT21_Pos                             21                                                        /*!< GPIO_PORT PIN6: PORT21 Position     */
#define GPIO_PORT_PIN6_PORT21_Msk                             (0x01UL << GPIO_PORT_PIN6_PORT21_Pos)                     /*!< GPIO_PORT PIN6: PORT21 Mask         */
#define GPIO_PORT_PIN6_PORT22_Pos                             22                                                        /*!< GPIO_PORT PIN6: PORT22 Position     */
#define GPIO_PORT_PIN6_PORT22_Msk                             (0x01UL << GPIO_PORT_PIN6_PORT22_Pos)                     /*!< GPIO_PORT PIN6: PORT22 Mask         */
#define GPIO_PORT_PIN6_PORT23_Pos                             23                                                        /*!< GPIO_PORT PIN6: PORT23 Position     */
#define GPIO_PORT_PIN6_PORT23_Msk                             (0x01UL << GPIO_PORT_PIN6_PORT23_Pos)                     /*!< GPIO_PORT PIN6: PORT23 Mask         */
#define GPIO_PORT_PIN6_PORT24_Pos                             24                                                        /*!< GPIO_PORT PIN6: PORT24 Position     */
#define GPIO_PORT_PIN6_PORT24_Msk                             (0x01UL << GPIO_PORT_PIN6_PORT24_Pos)                     /*!< GPIO_PORT PIN6: PORT24 Mask         */
#define GPIO_PORT_PIN6_PORT25_Pos                             25                                                        /*!< GPIO_PORT PIN6: PORT25 Position     */
#define GPIO_PORT_PIN6_PORT25_Msk                             (0x01UL << GPIO_PORT_PIN6_PORT25_Pos)                     /*!< GPIO_PORT PIN6: PORT25 Mask         */
#define GPIO_PORT_PIN6_PORT26_Pos                             26                                                        /*!< GPIO_PORT PIN6: PORT26 Position     */
#define GPIO_PORT_PIN6_PORT26_Msk                             (0x01UL << GPIO_PORT_PIN6_PORT26_Pos)                     /*!< GPIO_PORT PIN6: PORT26 Mask         */
#define GPIO_PORT_PIN6_PORT27_Pos                             27                                                        /*!< GPIO_PORT PIN6: PORT27 Position     */
#define GPIO_PORT_PIN6_PORT27_Msk                             (0x01UL << GPIO_PORT_PIN6_PORT27_Pos)                     /*!< GPIO_PORT PIN6: PORT27 Mask         */
#define GPIO_PORT_PIN6_PORT28_Pos                             28                                                        /*!< GPIO_PORT PIN6: PORT28 Position     */
#define GPIO_PORT_PIN6_PORT28_Msk                             (0x01UL << GPIO_PORT_PIN6_PORT28_Pos)                     /*!< GPIO_PORT PIN6: PORT28 Mask         */
#define GPIO_PORT_PIN6_PORT29_Pos                             29                                                        /*!< GPIO_PORT PIN6: PORT29 Position     */
#define GPIO_PORT_PIN6_PORT29_Msk                             (0x01UL << GPIO_PORT_PIN6_PORT29_Pos)                     /*!< GPIO_PORT PIN6: PORT29 Mask         */
#define GPIO_PORT_PIN6_PORT30_Pos                             30                                                        /*!< GPIO_PORT PIN6: PORT30 Position     */
#define GPIO_PORT_PIN6_PORT30_Msk                             (0x01UL << GPIO_PORT_PIN6_PORT30_Pos)                     /*!< GPIO_PORT PIN6: PORT30 Mask         */
#define GPIO_PORT_PIN6_PORT31_Pos                             31                                                        /*!< GPIO_PORT PIN6: PORT31 Position     */
#define GPIO_PORT_PIN6_PORT31_Msk                             (0x01UL << GPIO_PORT_PIN6_PORT31_Pos)                     /*!< GPIO_PORT PIN6: PORT31 Mask         */

// -------------------------------------  GPIO_PORT_PIN7  -----------------------------------------
#define GPIO_PORT_PIN7_PORT0_Pos                              0                                                         /*!< GPIO_PORT PIN7: PORT0 Position      */
#define GPIO_PORT_PIN7_PORT0_Msk                              (0x01UL << GPIO_PORT_PIN7_PORT0_Pos)                      /*!< GPIO_PORT PIN7: PORT0 Mask          */
#define GPIO_PORT_PIN7_PORT1_Pos                              1                                                         /*!< GPIO_PORT PIN7: PORT1 Position      */
#define GPIO_PORT_PIN7_PORT1_Msk                              (0x01UL << GPIO_PORT_PIN7_PORT1_Pos)                      /*!< GPIO_PORT PIN7: PORT1 Mask          */
#define GPIO_PORT_PIN7_PORT2_Pos                              2                                                         /*!< GPIO_PORT PIN7: PORT2 Position      */
#define GPIO_PORT_PIN7_PORT2_Msk                              (0x01UL << GPIO_PORT_PIN7_PORT2_Pos)                      /*!< GPIO_PORT PIN7: PORT2 Mask          */
#define GPIO_PORT_PIN7_PORT3_Pos                              3                                                         /*!< GPIO_PORT PIN7: PORT3 Position      */
#define GPIO_PORT_PIN7_PORT3_Msk                              (0x01UL << GPIO_PORT_PIN7_PORT3_Pos)                      /*!< GPIO_PORT PIN7: PORT3 Mask          */
#define GPIO_PORT_PIN7_PORT4_Pos                              4                                                         /*!< GPIO_PORT PIN7: PORT4 Position      */
#define GPIO_PORT_PIN7_PORT4_Msk                              (0x01UL << GPIO_PORT_PIN7_PORT4_Pos)                      /*!< GPIO_PORT PIN7: PORT4 Mask          */
#define GPIO_PORT_PIN7_PORT5_Pos                              5                                                         /*!< GPIO_PORT PIN7: PORT5 Position      */
#define GPIO_PORT_PIN7_PORT5_Msk                              (0x01UL << GPIO_PORT_PIN7_PORT5_Pos)                      /*!< GPIO_PORT PIN7: PORT5 Mask          */
#define GPIO_PORT_PIN7_PORT6_Pos                              6                                                         /*!< GPIO_PORT PIN7: PORT6 Position      */
#define GPIO_PORT_PIN7_PORT6_Msk                              (0x01UL << GPIO_PORT_PIN7_PORT6_Pos)                      /*!< GPIO_PORT PIN7: PORT6 Mask          */
#define GPIO_PORT_PIN7_PORT7_Pos                              7                                                         /*!< GPIO_PORT PIN7: PORT7 Position      */
#define GPIO_PORT_PIN7_PORT7_Msk                              (0x01UL << GPIO_PORT_PIN7_PORT7_Pos)                      /*!< GPIO_PORT PIN7: PORT7 Mask          */
#define GPIO_PORT_PIN7_PORT8_Pos                              8                                                         /*!< GPIO_PORT PIN7: PORT8 Position      */
#define GPIO_PORT_PIN7_PORT8_Msk                              (0x01UL << GPIO_PORT_PIN7_PORT8_Pos)                      /*!< GPIO_PORT PIN7: PORT8 Mask          */
#define GPIO_PORT_PIN7_PORT9_Pos                              9                                                         /*!< GPIO_PORT PIN7: PORT9 Position      */
#define GPIO_PORT_PIN7_PORT9_Msk                              (0x01UL << GPIO_PORT_PIN7_PORT9_Pos)                      /*!< GPIO_PORT PIN7: PORT9 Mask          */
#define GPIO_PORT_PIN7_PORT10_Pos                             10                                                        /*!< GPIO_PORT PIN7: PORT10 Position     */
#define GPIO_PORT_PIN7_PORT10_Msk                             (0x01UL << GPIO_PORT_PIN7_PORT10_Pos)                     /*!< GPIO_PORT PIN7: PORT10 Mask         */
#define GPIO_PORT_PIN7_PORT11_Pos                             11                                                        /*!< GPIO_PORT PIN7: PORT11 Position     */
#define GPIO_PORT_PIN7_PORT11_Msk                             (0x01UL << GPIO_PORT_PIN7_PORT11_Pos)                     /*!< GPIO_PORT PIN7: PORT11 Mask         */
#define GPIO_PORT_PIN7_PORT12_Pos                             12                                                        /*!< GPIO_PORT PIN7: PORT12 Position     */
#define GPIO_PORT_PIN7_PORT12_Msk                             (0x01UL << GPIO_PORT_PIN7_PORT12_Pos)                     /*!< GPIO_PORT PIN7: PORT12 Mask         */
#define GPIO_PORT_PIN7_PORT13_Pos                             13                                                        /*!< GPIO_PORT PIN7: PORT13 Position     */
#define GPIO_PORT_PIN7_PORT13_Msk                             (0x01UL << GPIO_PORT_PIN7_PORT13_Pos)                     /*!< GPIO_PORT PIN7: PORT13 Mask         */
#define GPIO_PORT_PIN7_PORT14_Pos                             14                                                        /*!< GPIO_PORT PIN7: PORT14 Position     */
#define GPIO_PORT_PIN7_PORT14_Msk                             (0x01UL << GPIO_PORT_PIN7_PORT14_Pos)                     /*!< GPIO_PORT PIN7: PORT14 Mask         */
#define GPIO_PORT_PIN7_PORT15_Pos                             15                                                        /*!< GPIO_PORT PIN7: PORT15 Position     */
#define GPIO_PORT_PIN7_PORT15_Msk                             (0x01UL << GPIO_PORT_PIN7_PORT15_Pos)                     /*!< GPIO_PORT PIN7: PORT15 Mask         */
#define GPIO_PORT_PIN7_PORT16_Pos                             16                                                        /*!< GPIO_PORT PIN7: PORT16 Position     */
#define GPIO_PORT_PIN7_PORT16_Msk                             (0x01UL << GPIO_PORT_PIN7_PORT16_Pos)                     /*!< GPIO_PORT PIN7: PORT16 Mask         */
#define GPIO_PORT_PIN7_PORT17_Pos                             17                                                        /*!< GPIO_PORT PIN7: PORT17 Position     */
#define GPIO_PORT_PIN7_PORT17_Msk                             (0x01UL << GPIO_PORT_PIN7_PORT17_Pos)                     /*!< GPIO_PORT PIN7: PORT17 Mask         */
#define GPIO_PORT_PIN7_PORT18_Pos                             18                                                        /*!< GPIO_PORT PIN7: PORT18 Position     */
#define GPIO_PORT_PIN7_PORT18_Msk                             (0x01UL << GPIO_PORT_PIN7_PORT18_Pos)                     /*!< GPIO_PORT PIN7: PORT18 Mask         */
#define GPIO_PORT_PIN7_PORT19_Pos                             19                                                        /*!< GPIO_PORT PIN7: PORT19 Position     */
#define GPIO_PORT_PIN7_PORT19_Msk                             (0x01UL << GPIO_PORT_PIN7_PORT19_Pos)                     /*!< GPIO_PORT PIN7: PORT19 Mask         */
#define GPIO_PORT_PIN7_PORT20_Pos                             20                                                        /*!< GPIO_PORT PIN7: PORT20 Position     */
#define GPIO_PORT_PIN7_PORT20_Msk                             (0x01UL << GPIO_PORT_PIN7_PORT20_Pos)                     /*!< GPIO_PORT PIN7: PORT20 Mask         */
#define GPIO_PORT_PIN7_PORT21_Pos                             21                                                        /*!< GPIO_PORT PIN7: PORT21 Position     */
#define GPIO_PORT_PIN7_PORT21_Msk                             (0x01UL << GPIO_PORT_PIN7_PORT21_Pos)                     /*!< GPIO_PORT PIN7: PORT21 Mask         */
#define GPIO_PORT_PIN7_PORT22_Pos                             22                                                        /*!< GPIO_PORT PIN7: PORT22 Position     */
#define GPIO_PORT_PIN7_PORT22_Msk                             (0x01UL << GPIO_PORT_PIN7_PORT22_Pos)                     /*!< GPIO_PORT PIN7: PORT22 Mask         */
#define GPIO_PORT_PIN7_PORT23_Pos                             23                                                        /*!< GPIO_PORT PIN7: PORT23 Position     */
#define GPIO_PORT_PIN7_PORT23_Msk                             (0x01UL << GPIO_PORT_PIN7_PORT23_Pos)                     /*!< GPIO_PORT PIN7: PORT23 Mask         */
#define GPIO_PORT_PIN7_PORT24_Pos                             24                                                        /*!< GPIO_PORT PIN7: PORT24 Position     */
#define GPIO_PORT_PIN7_PORT24_Msk                             (0x01UL << GPIO_PORT_PIN7_PORT24_Pos)                     /*!< GPIO_PORT PIN7: PORT24 Mask         */
#define GPIO_PORT_PIN7_PORT25_Pos                             25                                                        /*!< GPIO_PORT PIN7: PORT25 Position     */
#define GPIO_PORT_PIN7_PORT25_Msk                             (0x01UL << GPIO_PORT_PIN7_PORT25_Pos)                     /*!< GPIO_PORT PIN7: PORT25 Mask         */
#define GPIO_PORT_PIN7_PORT26_Pos                             26                                                        /*!< GPIO_PORT PIN7: PORT26 Position     */
#define GPIO_PORT_PIN7_PORT26_Msk                             (0x01UL << GPIO_PORT_PIN7_PORT26_Pos)                     /*!< GPIO_PORT PIN7: PORT26 Mask         */
#define GPIO_PORT_PIN7_PORT27_Pos                             27                                                        /*!< GPIO_PORT PIN7: PORT27 Position     */
#define GPIO_PORT_PIN7_PORT27_Msk                             (0x01UL << GPIO_PORT_PIN7_PORT27_Pos)                     /*!< GPIO_PORT PIN7: PORT27 Mask         */
#define GPIO_PORT_PIN7_PORT28_Pos                             28                                                        /*!< GPIO_PORT PIN7: PORT28 Position     */
#define GPIO_PORT_PIN7_PORT28_Msk                             (0x01UL << GPIO_PORT_PIN7_PORT28_Pos)                     /*!< GPIO_PORT PIN7: PORT28 Mask         */
#define GPIO_PORT_PIN7_PORT29_Pos                             29                                                        /*!< GPIO_PORT PIN7: PORT29 Position     */
#define GPIO_PORT_PIN7_PORT29_Msk                             (0x01UL << GPIO_PORT_PIN7_PORT29_Pos)                     /*!< GPIO_PORT PIN7: PORT29 Mask         */
#define GPIO_PORT_PIN7_PORT30_Pos                             30                                                        /*!< GPIO_PORT PIN7: PORT30 Position     */
#define GPIO_PORT_PIN7_PORT30_Msk                             (0x01UL << GPIO_PORT_PIN7_PORT30_Pos)                     /*!< GPIO_PORT PIN7: PORT30 Mask         */
#define GPIO_PORT_PIN7_PORT31_Pos                             31                                                        /*!< GPIO_PORT PIN7: PORT31 Position     */
#define GPIO_PORT_PIN7_PORT31_Msk                             (0x01UL << GPIO_PORT_PIN7_PORT31_Pos)                     /*!< GPIO_PORT PIN7: PORT31 Mask         */

// -------------------------------------  GPIO_PORT_MPIN0  ----------------------------------------
#define GPIO_PORT_MPIN0_MPORTP0_Pos                           0                                                         /*!< GPIO_PORT MPIN0: MPORTP0 Position   */
#define GPIO_PORT_MPIN0_MPORTP0_Msk                           (0x01UL << GPIO_PORT_MPIN0_MPORTP0_Pos)                   /*!< GPIO_PORT MPIN0: MPORTP0 Mask       */
#define GPIO_PORT_MPIN0_MPORTP1_Pos                           1                                                         /*!< GPIO_PORT MPIN0: MPORTP1 Position   */
#define GPIO_PORT_MPIN0_MPORTP1_Msk                           (0x01UL << GPIO_PORT_MPIN0_MPORTP1_Pos)                   /*!< GPIO_PORT MPIN0: MPORTP1 Mask       */
#define GPIO_PORT_MPIN0_MPORTP2_Pos                           2                                                         /*!< GPIO_PORT MPIN0: MPORTP2 Position   */
#define GPIO_PORT_MPIN0_MPORTP2_Msk                           (0x01UL << GPIO_PORT_MPIN0_MPORTP2_Pos)                   /*!< GPIO_PORT MPIN0: MPORTP2 Mask       */
#define GPIO_PORT_MPIN0_MPORTP3_Pos                           3                                                         /*!< GPIO_PORT MPIN0: MPORTP3 Position   */
#define GPIO_PORT_MPIN0_MPORTP3_Msk                           (0x01UL << GPIO_PORT_MPIN0_MPORTP3_Pos)                   /*!< GPIO_PORT MPIN0: MPORTP3 Mask       */
#define GPIO_PORT_MPIN0_MPORTP4_Pos                           4                                                         /*!< GPIO_PORT MPIN0: MPORTP4 Position   */
#define GPIO_PORT_MPIN0_MPORTP4_Msk                           (0x01UL << GPIO_PORT_MPIN0_MPORTP4_Pos)                   /*!< GPIO_PORT MPIN0: MPORTP4 Mask       */
#define GPIO_PORT_MPIN0_MPORTP5_Pos                           5                                                         /*!< GPIO_PORT MPIN0: MPORTP5 Position   */
#define GPIO_PORT_MPIN0_MPORTP5_Msk                           (0x01UL << GPIO_PORT_MPIN0_MPORTP5_Pos)                   /*!< GPIO_PORT MPIN0: MPORTP5 Mask       */
#define GPIO_PORT_MPIN0_MPORTP6_Pos                           6                                                         /*!< GPIO_PORT MPIN0: MPORTP6 Position   */
#define GPIO_PORT_MPIN0_MPORTP6_Msk                           (0x01UL << GPIO_PORT_MPIN0_MPORTP6_Pos)                   /*!< GPIO_PORT MPIN0: MPORTP6 Mask       */
#define GPIO_PORT_MPIN0_MPORTP7_Pos                           7                                                         /*!< GPIO_PORT MPIN0: MPORTP7 Position   */
#define GPIO_PORT_MPIN0_MPORTP7_Msk                           (0x01UL << GPIO_PORT_MPIN0_MPORTP7_Pos)                   /*!< GPIO_PORT MPIN0: MPORTP7 Mask       */
#define GPIO_PORT_MPIN0_MPORTP8_Pos                           8                                                         /*!< GPIO_PORT MPIN0: MPORTP8 Position   */
#define GPIO_PORT_MPIN0_MPORTP8_Msk                           (0x01UL << GPIO_PORT_MPIN0_MPORTP8_Pos)                   /*!< GPIO_PORT MPIN0: MPORTP8 Mask       */
#define GPIO_PORT_MPIN0_MPORTP9_Pos                           9                                                         /*!< GPIO_PORT MPIN0: MPORTP9 Position   */
#define GPIO_PORT_MPIN0_MPORTP9_Msk                           (0x01UL << GPIO_PORT_MPIN0_MPORTP9_Pos)                   /*!< GPIO_PORT MPIN0: MPORTP9 Mask       */
#define GPIO_PORT_MPIN0_MPORTP10_Pos                          10                                                        /*!< GPIO_PORT MPIN0: MPORTP10 Position  */
#define GPIO_PORT_MPIN0_MPORTP10_Msk                          (0x01UL << GPIO_PORT_MPIN0_MPORTP10_Pos)                  /*!< GPIO_PORT MPIN0: MPORTP10 Mask      */
#define GPIO_PORT_MPIN0_MPORTP11_Pos                          11                                                        /*!< GPIO_PORT MPIN0: MPORTP11 Position  */
#define GPIO_PORT_MPIN0_MPORTP11_Msk                          (0x01UL << GPIO_PORT_MPIN0_MPORTP11_Pos)                  /*!< GPIO_PORT MPIN0: MPORTP11 Mask      */
#define GPIO_PORT_MPIN0_MPORTP12_Pos                          12                                                        /*!< GPIO_PORT MPIN0: MPORTP12 Position  */
#define GPIO_PORT_MPIN0_MPORTP12_Msk                          (0x01UL << GPIO_PORT_MPIN0_MPORTP12_Pos)                  /*!< GPIO_PORT MPIN0: MPORTP12 Mask      */
#define GPIO_PORT_MPIN0_MPORTP13_Pos                          13                                                        /*!< GPIO_PORT MPIN0: MPORTP13 Position  */
#define GPIO_PORT_MPIN0_MPORTP13_Msk                          (0x01UL << GPIO_PORT_MPIN0_MPORTP13_Pos)                  /*!< GPIO_PORT MPIN0: MPORTP13 Mask      */
#define GPIO_PORT_MPIN0_MPORTP14_Pos                          14                                                        /*!< GPIO_PORT MPIN0: MPORTP14 Position  */
#define GPIO_PORT_MPIN0_MPORTP14_Msk                          (0x01UL << GPIO_PORT_MPIN0_MPORTP14_Pos)                  /*!< GPIO_PORT MPIN0: MPORTP14 Mask      */
#define GPIO_PORT_MPIN0_MPORTP15_Pos                          15                                                        /*!< GPIO_PORT MPIN0: MPORTP15 Position  */
#define GPIO_PORT_MPIN0_MPORTP15_Msk                          (0x01UL << GPIO_PORT_MPIN0_MPORTP15_Pos)                  /*!< GPIO_PORT MPIN0: MPORTP15 Mask      */
#define GPIO_PORT_MPIN0_MPORTP16_Pos                          16                                                        /*!< GPIO_PORT MPIN0: MPORTP16 Position  */
#define GPIO_PORT_MPIN0_MPORTP16_Msk                          (0x01UL << GPIO_PORT_MPIN0_MPORTP16_Pos)                  /*!< GPIO_PORT MPIN0: MPORTP16 Mask      */
#define GPIO_PORT_MPIN0_MPORTP17_Pos                          17                                                        /*!< GPIO_PORT MPIN0: MPORTP17 Position  */
#define GPIO_PORT_MPIN0_MPORTP17_Msk                          (0x01UL << GPIO_PORT_MPIN0_MPORTP17_Pos)                  /*!< GPIO_PORT MPIN0: MPORTP17 Mask      */
#define GPIO_PORT_MPIN0_MPORTP18_Pos                          18                                                        /*!< GPIO_PORT MPIN0: MPORTP18 Position  */
#define GPIO_PORT_MPIN0_MPORTP18_Msk                          (0x01UL << GPIO_PORT_MPIN0_MPORTP18_Pos)                  /*!< GPIO_PORT MPIN0: MPORTP18 Mask      */
#define GPIO_PORT_MPIN0_MPORTP19_Pos                          19                                                        /*!< GPIO_PORT MPIN0: MPORTP19 Position  */
#define GPIO_PORT_MPIN0_MPORTP19_Msk                          (0x01UL << GPIO_PORT_MPIN0_MPORTP19_Pos)                  /*!< GPIO_PORT MPIN0: MPORTP19 Mask      */
#define GPIO_PORT_MPIN0_MPORTP20_Pos                          20                                                        /*!< GPIO_PORT MPIN0: MPORTP20 Position  */
#define GPIO_PORT_MPIN0_MPORTP20_Msk                          (0x01UL << GPIO_PORT_MPIN0_MPORTP20_Pos)                  /*!< GPIO_PORT MPIN0: MPORTP20 Mask      */
#define GPIO_PORT_MPIN0_MPORTP21_Pos                          21                                                        /*!< GPIO_PORT MPIN0: MPORTP21 Position  */
#define GPIO_PORT_MPIN0_MPORTP21_Msk                          (0x01UL << GPIO_PORT_MPIN0_MPORTP21_Pos)                  /*!< GPIO_PORT MPIN0: MPORTP21 Mask      */
#define GPIO_PORT_MPIN0_MPORTP22_Pos                          22                                                        /*!< GPIO_PORT MPIN0: MPORTP22 Position  */
#define GPIO_PORT_MPIN0_MPORTP22_Msk                          (0x01UL << GPIO_PORT_MPIN0_MPORTP22_Pos)                  /*!< GPIO_PORT MPIN0: MPORTP22 Mask      */
#define GPIO_PORT_MPIN0_MPORTP23_Pos                          23                                                        /*!< GPIO_PORT MPIN0: MPORTP23 Position  */
#define GPIO_PORT_MPIN0_MPORTP23_Msk                          (0x01UL << GPIO_PORT_MPIN0_MPORTP23_Pos)                  /*!< GPIO_PORT MPIN0: MPORTP23 Mask      */
#define GPIO_PORT_MPIN0_MPORTP24_Pos                          24                                                        /*!< GPIO_PORT MPIN0: MPORTP24 Position  */
#define GPIO_PORT_MPIN0_MPORTP24_Msk                          (0x01UL << GPIO_PORT_MPIN0_MPORTP24_Pos)                  /*!< GPIO_PORT MPIN0: MPORTP24 Mask      */
#define GPIO_PORT_MPIN0_MPORTP25_Pos                          25                                                        /*!< GPIO_PORT MPIN0: MPORTP25 Position  */
#define GPIO_PORT_MPIN0_MPORTP25_Msk                          (0x01UL << GPIO_PORT_MPIN0_MPORTP25_Pos)                  /*!< GPIO_PORT MPIN0: MPORTP25 Mask      */
#define GPIO_PORT_MPIN0_MPORTP26_Pos                          26                                                        /*!< GPIO_PORT MPIN0: MPORTP26 Position  */
#define GPIO_PORT_MPIN0_MPORTP26_Msk                          (0x01UL << GPIO_PORT_MPIN0_MPORTP26_Pos)                  /*!< GPIO_PORT MPIN0: MPORTP26 Mask      */
#define GPIO_PORT_MPIN0_MPORTP27_Pos                          27                                                        /*!< GPIO_PORT MPIN0: MPORTP27 Position  */
#define GPIO_PORT_MPIN0_MPORTP27_Msk                          (0x01UL << GPIO_PORT_MPIN0_MPORTP27_Pos)                  /*!< GPIO_PORT MPIN0: MPORTP27 Mask      */
#define GPIO_PORT_MPIN0_MPORTP28_Pos                          28                                                        /*!< GPIO_PORT MPIN0: MPORTP28 Position  */
#define GPIO_PORT_MPIN0_MPORTP28_Msk                          (0x01UL << GPIO_PORT_MPIN0_MPORTP28_Pos)                  /*!< GPIO_PORT MPIN0: MPORTP28 Mask      */
#define GPIO_PORT_MPIN0_MPORTP29_Pos                          29                                                        /*!< GPIO_PORT MPIN0: MPORTP29 Position  */
#define GPIO_PORT_MPIN0_MPORTP29_Msk                          (0x01UL << GPIO_PORT_MPIN0_MPORTP29_Pos)                  /*!< GPIO_PORT MPIN0: MPORTP29 Mask      */
#define GPIO_PORT_MPIN0_MPORTP30_Pos                          30                                                        /*!< GPIO_PORT MPIN0: MPORTP30 Position  */
#define GPIO_PORT_MPIN0_MPORTP30_Msk                          (0x01UL << GPIO_PORT_MPIN0_MPORTP30_Pos)                  /*!< GPIO_PORT MPIN0: MPORTP30 Mask      */
#define GPIO_PORT_MPIN0_MPORTP31_Pos                          31                                                        /*!< GPIO_PORT MPIN0: MPORTP31 Position  */
#define GPIO_PORT_MPIN0_MPORTP31_Msk                          (0x01UL << GPIO_PORT_MPIN0_MPORTP31_Pos)                  /*!< GPIO_PORT MPIN0: MPORTP31 Mask      */

// -------------------------------------  GPIO_PORT_MPIN1  ----------------------------------------
#define GPIO_PORT_MPIN1_MPORTP0_Pos                           0                                                         /*!< GPIO_PORT MPIN1: MPORTP0 Position   */
#define GPIO_PORT_MPIN1_MPORTP0_Msk                           (0x01UL << GPIO_PORT_MPIN1_MPORTP0_Pos)                   /*!< GPIO_PORT MPIN1: MPORTP0 Mask       */
#define GPIO_PORT_MPIN1_MPORTP1_Pos                           1                                                         /*!< GPIO_PORT MPIN1: MPORTP1 Position   */
#define GPIO_PORT_MPIN1_MPORTP1_Msk                           (0x01UL << GPIO_PORT_MPIN1_MPORTP1_Pos)                   /*!< GPIO_PORT MPIN1: MPORTP1 Mask       */
#define GPIO_PORT_MPIN1_MPORTP2_Pos                           2                                                         /*!< GPIO_PORT MPIN1: MPORTP2 Position   */
#define GPIO_PORT_MPIN1_MPORTP2_Msk                           (0x01UL << GPIO_PORT_MPIN1_MPORTP2_Pos)                   /*!< GPIO_PORT MPIN1: MPORTP2 Mask       */
#define GPIO_PORT_MPIN1_MPORTP3_Pos                           3                                                         /*!< GPIO_PORT MPIN1: MPORTP3 Position   */
#define GPIO_PORT_MPIN1_MPORTP3_Msk                           (0x01UL << GPIO_PORT_MPIN1_MPORTP3_Pos)                   /*!< GPIO_PORT MPIN1: MPORTP3 Mask       */
#define GPIO_PORT_MPIN1_MPORTP4_Pos                           4                                                         /*!< GPIO_PORT MPIN1: MPORTP4 Position   */
#define GPIO_PORT_MPIN1_MPORTP4_Msk                           (0x01UL << GPIO_PORT_MPIN1_MPORTP4_Pos)                   /*!< GPIO_PORT MPIN1: MPORTP4 Mask       */
#define GPIO_PORT_MPIN1_MPORTP5_Pos                           5                                                         /*!< GPIO_PORT MPIN1: MPORTP5 Position   */
#define GPIO_PORT_MPIN1_MPORTP5_Msk                           (0x01UL << GPIO_PORT_MPIN1_MPORTP5_Pos)                   /*!< GPIO_PORT MPIN1: MPORTP5 Mask       */
#define GPIO_PORT_MPIN1_MPORTP6_Pos                           6                                                         /*!< GPIO_PORT MPIN1: MPORTP6 Position   */
#define GPIO_PORT_MPIN1_MPORTP6_Msk                           (0x01UL << GPIO_PORT_MPIN1_MPORTP6_Pos)                   /*!< GPIO_PORT MPIN1: MPORTP6 Mask       */
#define GPIO_PORT_MPIN1_MPORTP7_Pos                           7                                                         /*!< GPIO_PORT MPIN1: MPORTP7 Position   */
#define GPIO_PORT_MPIN1_MPORTP7_Msk                           (0x01UL << GPIO_PORT_MPIN1_MPORTP7_Pos)                   /*!< GPIO_PORT MPIN1: MPORTP7 Mask       */
#define GPIO_PORT_MPIN1_MPORTP8_Pos                           8                                                         /*!< GPIO_PORT MPIN1: MPORTP8 Position   */
#define GPIO_PORT_MPIN1_MPORTP8_Msk                           (0x01UL << GPIO_PORT_MPIN1_MPORTP8_Pos)                   /*!< GPIO_PORT MPIN1: MPORTP8 Mask       */
#define GPIO_PORT_MPIN1_MPORTP9_Pos                           9                                                         /*!< GPIO_PORT MPIN1: MPORTP9 Position   */
#define GPIO_PORT_MPIN1_MPORTP9_Msk                           (0x01UL << GPIO_PORT_MPIN1_MPORTP9_Pos)                   /*!< GPIO_PORT MPIN1: MPORTP9 Mask       */
#define GPIO_PORT_MPIN1_MPORTP10_Pos                          10                                                        /*!< GPIO_PORT MPIN1: MPORTP10 Position  */
#define GPIO_PORT_MPIN1_MPORTP10_Msk                          (0x01UL << GPIO_PORT_MPIN1_MPORTP10_Pos)                  /*!< GPIO_PORT MPIN1: MPORTP10 Mask      */
#define GPIO_PORT_MPIN1_MPORTP11_Pos                          11                                                        /*!< GPIO_PORT MPIN1: MPORTP11 Position  */
#define GPIO_PORT_MPIN1_MPORTP11_Msk                          (0x01UL << GPIO_PORT_MPIN1_MPORTP11_Pos)                  /*!< GPIO_PORT MPIN1: MPORTP11 Mask      */
#define GPIO_PORT_MPIN1_MPORTP12_Pos                          12                                                        /*!< GPIO_PORT MPIN1: MPORTP12 Position  */
#define GPIO_PORT_MPIN1_MPORTP12_Msk                          (0x01UL << GPIO_PORT_MPIN1_MPORTP12_Pos)                  /*!< GPIO_PORT MPIN1: MPORTP12 Mask      */
#define GPIO_PORT_MPIN1_MPORTP13_Pos                          13                                                        /*!< GPIO_PORT MPIN1: MPORTP13 Position  */
#define GPIO_PORT_MPIN1_MPORTP13_Msk                          (0x01UL << GPIO_PORT_MPIN1_MPORTP13_Pos)                  /*!< GPIO_PORT MPIN1: MPORTP13 Mask      */
#define GPIO_PORT_MPIN1_MPORTP14_Pos                          14                                                        /*!< GPIO_PORT MPIN1: MPORTP14 Position  */
#define GPIO_PORT_MPIN1_MPORTP14_Msk                          (0x01UL << GPIO_PORT_MPIN1_MPORTP14_Pos)                  /*!< GPIO_PORT MPIN1: MPORTP14 Mask      */
#define GPIO_PORT_MPIN1_MPORTP15_Pos                          15                                                        /*!< GPIO_PORT MPIN1: MPORTP15 Position  */
#define GPIO_PORT_MPIN1_MPORTP15_Msk                          (0x01UL << GPIO_PORT_MPIN1_MPORTP15_Pos)                  /*!< GPIO_PORT MPIN1: MPORTP15 Mask      */
#define GPIO_PORT_MPIN1_MPORTP16_Pos                          16                                                        /*!< GPIO_PORT MPIN1: MPORTP16 Position  */
#define GPIO_PORT_MPIN1_MPORTP16_Msk                          (0x01UL << GPIO_PORT_MPIN1_MPORTP16_Pos)                  /*!< GPIO_PORT MPIN1: MPORTP16 Mask      */
#define GPIO_PORT_MPIN1_MPORTP17_Pos                          17                                                        /*!< GPIO_PORT MPIN1: MPORTP17 Position  */
#define GPIO_PORT_MPIN1_MPORTP17_Msk                          (0x01UL << GPIO_PORT_MPIN1_MPORTP17_Pos)                  /*!< GPIO_PORT MPIN1: MPORTP17 Mask      */
#define GPIO_PORT_MPIN1_MPORTP18_Pos                          18                                                        /*!< GPIO_PORT MPIN1: MPORTP18 Position  */
#define GPIO_PORT_MPIN1_MPORTP18_Msk                          (0x01UL << GPIO_PORT_MPIN1_MPORTP18_Pos)                  /*!< GPIO_PORT MPIN1: MPORTP18 Mask      */
#define GPIO_PORT_MPIN1_MPORTP19_Pos                          19                                                        /*!< GPIO_PORT MPIN1: MPORTP19 Position  */
#define GPIO_PORT_MPIN1_MPORTP19_Msk                          (0x01UL << GPIO_PORT_MPIN1_MPORTP19_Pos)                  /*!< GPIO_PORT MPIN1: MPORTP19 Mask      */
#define GPIO_PORT_MPIN1_MPORTP20_Pos                          20                                                        /*!< GPIO_PORT MPIN1: MPORTP20 Position  */
#define GPIO_PORT_MPIN1_MPORTP20_Msk                          (0x01UL << GPIO_PORT_MPIN1_MPORTP20_Pos)                  /*!< GPIO_PORT MPIN1: MPORTP20 Mask      */
#define GPIO_PORT_MPIN1_MPORTP21_Pos                          21                                                        /*!< GPIO_PORT MPIN1: MPORTP21 Position  */
#define GPIO_PORT_MPIN1_MPORTP21_Msk                          (0x01UL << GPIO_PORT_MPIN1_MPORTP21_Pos)                  /*!< GPIO_PORT MPIN1: MPORTP21 Mask      */
#define GPIO_PORT_MPIN1_MPORTP22_Pos                          22                                                        /*!< GPIO_PORT MPIN1: MPORTP22 Position  */
#define GPIO_PORT_MPIN1_MPORTP22_Msk                          (0x01UL << GPIO_PORT_MPIN1_MPORTP22_Pos)                  /*!< GPIO_PORT MPIN1: MPORTP22 Mask      */
#define GPIO_PORT_MPIN1_MPORTP23_Pos                          23                                                        /*!< GPIO_PORT MPIN1: MPORTP23 Position  */
#define GPIO_PORT_MPIN1_MPORTP23_Msk                          (0x01UL << GPIO_PORT_MPIN1_MPORTP23_Pos)                  /*!< GPIO_PORT MPIN1: MPORTP23 Mask      */
#define GPIO_PORT_MPIN1_MPORTP24_Pos                          24                                                        /*!< GPIO_PORT MPIN1: MPORTP24 Position  */
#define GPIO_PORT_MPIN1_MPORTP24_Msk                          (0x01UL << GPIO_PORT_MPIN1_MPORTP24_Pos)                  /*!< GPIO_PORT MPIN1: MPORTP24 Mask      */
#define GPIO_PORT_MPIN1_MPORTP25_Pos                          25                                                        /*!< GPIO_PORT MPIN1: MPORTP25 Position  */
#define GPIO_PORT_MPIN1_MPORTP25_Msk                          (0x01UL << GPIO_PORT_MPIN1_MPORTP25_Pos)                  /*!< GPIO_PORT MPIN1: MPORTP25 Mask      */
#define GPIO_PORT_MPIN1_MPORTP26_Pos                          26                                                        /*!< GPIO_PORT MPIN1: MPORTP26 Position  */
#define GPIO_PORT_MPIN1_MPORTP26_Msk                          (0x01UL << GPIO_PORT_MPIN1_MPORTP26_Pos)                  /*!< GPIO_PORT MPIN1: MPORTP26 Mask      */
#define GPIO_PORT_MPIN1_MPORTP27_Pos                          27                                                        /*!< GPIO_PORT MPIN1: MPORTP27 Position  */
#define GPIO_PORT_MPIN1_MPORTP27_Msk                          (0x01UL << GPIO_PORT_MPIN1_MPORTP27_Pos)                  /*!< GPIO_PORT MPIN1: MPORTP27 Mask      */
#define GPIO_PORT_MPIN1_MPORTP28_Pos                          28                                                        /*!< GPIO_PORT MPIN1: MPORTP28 Position  */
#define GPIO_PORT_MPIN1_MPORTP28_Msk                          (0x01UL << GPIO_PORT_MPIN1_MPORTP28_Pos)                  /*!< GPIO_PORT MPIN1: MPORTP28 Mask      */
#define GPIO_PORT_MPIN1_MPORTP29_Pos                          29                                                        /*!< GPIO_PORT MPIN1: MPORTP29 Position  */
#define GPIO_PORT_MPIN1_MPORTP29_Msk                          (0x01UL << GPIO_PORT_MPIN1_MPORTP29_Pos)                  /*!< GPIO_PORT MPIN1: MPORTP29 Mask      */
#define GPIO_PORT_MPIN1_MPORTP30_Pos                          30                                                        /*!< GPIO_PORT MPIN1: MPORTP30 Position  */
#define GPIO_PORT_MPIN1_MPORTP30_Msk                          (0x01UL << GPIO_PORT_MPIN1_MPORTP30_Pos)                  /*!< GPIO_PORT MPIN1: MPORTP30 Mask      */
#define GPIO_PORT_MPIN1_MPORTP31_Pos                          31                                                        /*!< GPIO_PORT MPIN1: MPORTP31 Position  */
#define GPIO_PORT_MPIN1_MPORTP31_Msk                          (0x01UL << GPIO_PORT_MPIN1_MPORTP31_Pos)                  /*!< GPIO_PORT MPIN1: MPORTP31 Mask      */

// -------------------------------------  GPIO_PORT_MPIN2  ----------------------------------------
#define GPIO_PORT_MPIN2_MPORTP0_Pos                           0                                                         /*!< GPIO_PORT MPIN2: MPORTP0 Position   */
#define GPIO_PORT_MPIN2_MPORTP0_Msk                           (0x01UL << GPIO_PORT_MPIN2_MPORTP0_Pos)                   /*!< GPIO_PORT MPIN2: MPORTP0 Mask       */
#define GPIO_PORT_MPIN2_MPORTP1_Pos                           1                                                         /*!< GPIO_PORT MPIN2: MPORTP1 Position   */
#define GPIO_PORT_MPIN2_MPORTP1_Msk                           (0x01UL << GPIO_PORT_MPIN2_MPORTP1_Pos)                   /*!< GPIO_PORT MPIN2: MPORTP1 Mask       */
#define GPIO_PORT_MPIN2_MPORTP2_Pos                           2                                                         /*!< GPIO_PORT MPIN2: MPORTP2 Position   */
#define GPIO_PORT_MPIN2_MPORTP2_Msk                           (0x01UL << GPIO_PORT_MPIN2_MPORTP2_Pos)                   /*!< GPIO_PORT MPIN2: MPORTP2 Mask       */
#define GPIO_PORT_MPIN2_MPORTP3_Pos                           3                                                         /*!< GPIO_PORT MPIN2: MPORTP3 Position   */
#define GPIO_PORT_MPIN2_MPORTP3_Msk                           (0x01UL << GPIO_PORT_MPIN2_MPORTP3_Pos)                   /*!< GPIO_PORT MPIN2: MPORTP3 Mask       */
#define GPIO_PORT_MPIN2_MPORTP4_Pos                           4                                                         /*!< GPIO_PORT MPIN2: MPORTP4 Position   */
#define GPIO_PORT_MPIN2_MPORTP4_Msk                           (0x01UL << GPIO_PORT_MPIN2_MPORTP4_Pos)                   /*!< GPIO_PORT MPIN2: MPORTP4 Mask       */
#define GPIO_PORT_MPIN2_MPORTP5_Pos                           5                                                         /*!< GPIO_PORT MPIN2: MPORTP5 Position   */
#define GPIO_PORT_MPIN2_MPORTP5_Msk                           (0x01UL << GPIO_PORT_MPIN2_MPORTP5_Pos)                   /*!< GPIO_PORT MPIN2: MPORTP5 Mask       */
#define GPIO_PORT_MPIN2_MPORTP6_Pos                           6                                                         /*!< GPIO_PORT MPIN2: MPORTP6 Position   */
#define GPIO_PORT_MPIN2_MPORTP6_Msk                           (0x01UL << GPIO_PORT_MPIN2_MPORTP6_Pos)                   /*!< GPIO_PORT MPIN2: MPORTP6 Mask       */
#define GPIO_PORT_MPIN2_MPORTP7_Pos                           7                                                         /*!< GPIO_PORT MPIN2: MPORTP7 Position   */
#define GPIO_PORT_MPIN2_MPORTP7_Msk                           (0x01UL << GPIO_PORT_MPIN2_MPORTP7_Pos)                   /*!< GPIO_PORT MPIN2: MPORTP7 Mask       */
#define GPIO_PORT_MPIN2_MPORTP8_Pos                           8                                                         /*!< GPIO_PORT MPIN2: MPORTP8 Position   */
#define GPIO_PORT_MPIN2_MPORTP8_Msk                           (0x01UL << GPIO_PORT_MPIN2_MPORTP8_Pos)                   /*!< GPIO_PORT MPIN2: MPORTP8 Mask       */
#define GPIO_PORT_MPIN2_MPORTP9_Pos                           9                                                         /*!< GPIO_PORT MPIN2: MPORTP9 Position   */
#define GPIO_PORT_MPIN2_MPORTP9_Msk                           (0x01UL << GPIO_PORT_MPIN2_MPORTP9_Pos)                   /*!< GPIO_PORT MPIN2: MPORTP9 Mask       */
#define GPIO_PORT_MPIN2_MPORTP10_Pos                          10                                                        /*!< GPIO_PORT MPIN2: MPORTP10 Position  */
#define GPIO_PORT_MPIN2_MPORTP10_Msk                          (0x01UL << GPIO_PORT_MPIN2_MPORTP10_Pos)                  /*!< GPIO_PORT MPIN2: MPORTP10 Mask      */
#define GPIO_PORT_MPIN2_MPORTP11_Pos                          11                                                        /*!< GPIO_PORT MPIN2: MPORTP11 Position  */
#define GPIO_PORT_MPIN2_MPORTP11_Msk                          (0x01UL << GPIO_PORT_MPIN2_MPORTP11_Pos)                  /*!< GPIO_PORT MPIN2: MPORTP11 Mask      */
#define GPIO_PORT_MPIN2_MPORTP12_Pos                          12                                                        /*!< GPIO_PORT MPIN2: MPORTP12 Position  */
#define GPIO_PORT_MPIN2_MPORTP12_Msk                          (0x01UL << GPIO_PORT_MPIN2_MPORTP12_Pos)                  /*!< GPIO_PORT MPIN2: MPORTP12 Mask      */
#define GPIO_PORT_MPIN2_MPORTP13_Pos                          13                                                        /*!< GPIO_PORT MPIN2: MPORTP13 Position  */
#define GPIO_PORT_MPIN2_MPORTP13_Msk                          (0x01UL << GPIO_PORT_MPIN2_MPORTP13_Pos)                  /*!< GPIO_PORT MPIN2: MPORTP13 Mask      */
#define GPIO_PORT_MPIN2_MPORTP14_Pos                          14                                                        /*!< GPIO_PORT MPIN2: MPORTP14 Position  */
#define GPIO_PORT_MPIN2_MPORTP14_Msk                          (0x01UL << GPIO_PORT_MPIN2_MPORTP14_Pos)                  /*!< GPIO_PORT MPIN2: MPORTP14 Mask      */
#define GPIO_PORT_MPIN2_MPORTP15_Pos                          15                                                        /*!< GPIO_PORT MPIN2: MPORTP15 Position  */
#define GPIO_PORT_MPIN2_MPORTP15_Msk                          (0x01UL << GPIO_PORT_MPIN2_MPORTP15_Pos)                  /*!< GPIO_PORT MPIN2: MPORTP15 Mask      */
#define GPIO_PORT_MPIN2_MPORTP16_Pos                          16                                                        /*!< GPIO_PORT MPIN2: MPORTP16 Position  */
#define GPIO_PORT_MPIN2_MPORTP16_Msk                          (0x01UL << GPIO_PORT_MPIN2_MPORTP16_Pos)                  /*!< GPIO_PORT MPIN2: MPORTP16 Mask      */
#define GPIO_PORT_MPIN2_MPORTP17_Pos                          17                                                        /*!< GPIO_PORT MPIN2: MPORTP17 Position  */
#define GPIO_PORT_MPIN2_MPORTP17_Msk                          (0x01UL << GPIO_PORT_MPIN2_MPORTP17_Pos)                  /*!< GPIO_PORT MPIN2: MPORTP17 Mask      */
#define GPIO_PORT_MPIN2_MPORTP18_Pos                          18                                                        /*!< GPIO_PORT MPIN2: MPORTP18 Position  */
#define GPIO_PORT_MPIN2_MPORTP18_Msk                          (0x01UL << GPIO_PORT_MPIN2_MPORTP18_Pos)                  /*!< GPIO_PORT MPIN2: MPORTP18 Mask      */
#define GPIO_PORT_MPIN2_MPORTP19_Pos                          19                                                        /*!< GPIO_PORT MPIN2: MPORTP19 Position  */
#define GPIO_PORT_MPIN2_MPORTP19_Msk                          (0x01UL << GPIO_PORT_MPIN2_MPORTP19_Pos)                  /*!< GPIO_PORT MPIN2: MPORTP19 Mask      */
#define GPIO_PORT_MPIN2_MPORTP20_Pos                          20                                                        /*!< GPIO_PORT MPIN2: MPORTP20 Position  */
#define GPIO_PORT_MPIN2_MPORTP20_Msk                          (0x01UL << GPIO_PORT_MPIN2_MPORTP20_Pos)                  /*!< GPIO_PORT MPIN2: MPORTP20 Mask      */
#define GPIO_PORT_MPIN2_MPORTP21_Pos                          21                                                        /*!< GPIO_PORT MPIN2: MPORTP21 Position  */
#define GPIO_PORT_MPIN2_MPORTP21_Msk                          (0x01UL << GPIO_PORT_MPIN2_MPORTP21_Pos)                  /*!< GPIO_PORT MPIN2: MPORTP21 Mask      */
#define GPIO_PORT_MPIN2_MPORTP22_Pos                          22                                                        /*!< GPIO_PORT MPIN2: MPORTP22 Position  */
#define GPIO_PORT_MPIN2_MPORTP22_Msk                          (0x01UL << GPIO_PORT_MPIN2_MPORTP22_Pos)                  /*!< GPIO_PORT MPIN2: MPORTP22 Mask      */
#define GPIO_PORT_MPIN2_MPORTP23_Pos                          23                                                        /*!< GPIO_PORT MPIN2: MPORTP23 Position  */
#define GPIO_PORT_MPIN2_MPORTP23_Msk                          (0x01UL << GPIO_PORT_MPIN2_MPORTP23_Pos)                  /*!< GPIO_PORT MPIN2: MPORTP23 Mask      */
#define GPIO_PORT_MPIN2_MPORTP24_Pos                          24                                                        /*!< GPIO_PORT MPIN2: MPORTP24 Position  */
#define GPIO_PORT_MPIN2_MPORTP24_Msk                          (0x01UL << GPIO_PORT_MPIN2_MPORTP24_Pos)                  /*!< GPIO_PORT MPIN2: MPORTP24 Mask      */
#define GPIO_PORT_MPIN2_MPORTP25_Pos                          25                                                        /*!< GPIO_PORT MPIN2: MPORTP25 Position  */
#define GPIO_PORT_MPIN2_MPORTP25_Msk                          (0x01UL << GPIO_PORT_MPIN2_MPORTP25_Pos)                  /*!< GPIO_PORT MPIN2: MPORTP25 Mask      */
#define GPIO_PORT_MPIN2_MPORTP26_Pos                          26                                                        /*!< GPIO_PORT MPIN2: MPORTP26 Position  */
#define GPIO_PORT_MPIN2_MPORTP26_Msk                          (0x01UL << GPIO_PORT_MPIN2_MPORTP26_Pos)                  /*!< GPIO_PORT MPIN2: MPORTP26 Mask      */
#define GPIO_PORT_MPIN2_MPORTP27_Pos                          27                                                        /*!< GPIO_PORT MPIN2: MPORTP27 Position  */
#define GPIO_PORT_MPIN2_MPORTP27_Msk                          (0x01UL << GPIO_PORT_MPIN2_MPORTP27_Pos)                  /*!< GPIO_PORT MPIN2: MPORTP27 Mask      */
#define GPIO_PORT_MPIN2_MPORTP28_Pos                          28                                                        /*!< GPIO_PORT MPIN2: MPORTP28 Position  */
#define GPIO_PORT_MPIN2_MPORTP28_Msk                          (0x01UL << GPIO_PORT_MPIN2_MPORTP28_Pos)                  /*!< GPIO_PORT MPIN2: MPORTP28 Mask      */
#define GPIO_PORT_MPIN2_MPORTP29_Pos                          29                                                        /*!< GPIO_PORT MPIN2: MPORTP29 Position  */
#define GPIO_PORT_MPIN2_MPORTP29_Msk                          (0x01UL << GPIO_PORT_MPIN2_MPORTP29_Pos)                  /*!< GPIO_PORT MPIN2: MPORTP29 Mask      */
#define GPIO_PORT_MPIN2_MPORTP30_Pos                          30                                                        /*!< GPIO_PORT MPIN2: MPORTP30 Position  */
#define GPIO_PORT_MPIN2_MPORTP30_Msk                          (0x01UL << GPIO_PORT_MPIN2_MPORTP30_Pos)                  /*!< GPIO_PORT MPIN2: MPORTP30 Mask      */
#define GPIO_PORT_MPIN2_MPORTP31_Pos                          31                                                        /*!< GPIO_PORT MPIN2: MPORTP31 Position  */
#define GPIO_PORT_MPIN2_MPORTP31_Msk                          (0x01UL << GPIO_PORT_MPIN2_MPORTP31_Pos)                  /*!< GPIO_PORT MPIN2: MPORTP31 Mask      */

// -------------------------------------  GPIO_PORT_MPIN3  ----------------------------------------
#define GPIO_PORT_MPIN3_MPORTP0_Pos                           0                                                         /*!< GPIO_PORT MPIN3: MPORTP0 Position   */
#define GPIO_PORT_MPIN3_MPORTP0_Msk                           (0x01UL << GPIO_PORT_MPIN3_MPORTP0_Pos)                   /*!< GPIO_PORT MPIN3: MPORTP0 Mask       */
#define GPIO_PORT_MPIN3_MPORTP1_Pos                           1                                                         /*!< GPIO_PORT MPIN3: MPORTP1 Position   */
#define GPIO_PORT_MPIN3_MPORTP1_Msk                           (0x01UL << GPIO_PORT_MPIN3_MPORTP1_Pos)                   /*!< GPIO_PORT MPIN3: MPORTP1 Mask       */
#define GPIO_PORT_MPIN3_MPORTP2_Pos                           2                                                         /*!< GPIO_PORT MPIN3: MPORTP2 Position   */
#define GPIO_PORT_MPIN3_MPORTP2_Msk                           (0x01UL << GPIO_PORT_MPIN3_MPORTP2_Pos)                   /*!< GPIO_PORT MPIN3: MPORTP2 Mask       */
#define GPIO_PORT_MPIN3_MPORTP3_Pos                           3                                                         /*!< GPIO_PORT MPIN3: MPORTP3 Position   */
#define GPIO_PORT_MPIN3_MPORTP3_Msk                           (0x01UL << GPIO_PORT_MPIN3_MPORTP3_Pos)                   /*!< GPIO_PORT MPIN3: MPORTP3 Mask       */
#define GPIO_PORT_MPIN3_MPORTP4_Pos                           4                                                         /*!< GPIO_PORT MPIN3: MPORTP4 Position   */
#define GPIO_PORT_MPIN3_MPORTP4_Msk                           (0x01UL << GPIO_PORT_MPIN3_MPORTP4_Pos)                   /*!< GPIO_PORT MPIN3: MPORTP4 Mask       */
#define GPIO_PORT_MPIN3_MPORTP5_Pos                           5                                                         /*!< GPIO_PORT MPIN3: MPORTP5 Position   */
#define GPIO_PORT_MPIN3_MPORTP5_Msk                           (0x01UL << GPIO_PORT_MPIN3_MPORTP5_Pos)                   /*!< GPIO_PORT MPIN3: MPORTP5 Mask       */
#define GPIO_PORT_MPIN3_MPORTP6_Pos                           6                                                         /*!< GPIO_PORT MPIN3: MPORTP6 Position   */
#define GPIO_PORT_MPIN3_MPORTP6_Msk                           (0x01UL << GPIO_PORT_MPIN3_MPORTP6_Pos)                   /*!< GPIO_PORT MPIN3: MPORTP6 Mask       */
#define GPIO_PORT_MPIN3_MPORTP7_Pos                           7                                                         /*!< GPIO_PORT MPIN3: MPORTP7 Position   */
#define GPIO_PORT_MPIN3_MPORTP7_Msk                           (0x01UL << GPIO_PORT_MPIN3_MPORTP7_Pos)                   /*!< GPIO_PORT MPIN3: MPORTP7 Mask       */
#define GPIO_PORT_MPIN3_MPORTP8_Pos                           8                                                         /*!< GPIO_PORT MPIN3: MPORTP8 Position   */
#define GPIO_PORT_MPIN3_MPORTP8_Msk                           (0x01UL << GPIO_PORT_MPIN3_MPORTP8_Pos)                   /*!< GPIO_PORT MPIN3: MPORTP8 Mask       */
#define GPIO_PORT_MPIN3_MPORTP9_Pos                           9                                                         /*!< GPIO_PORT MPIN3: MPORTP9 Position   */
#define GPIO_PORT_MPIN3_MPORTP9_Msk                           (0x01UL << GPIO_PORT_MPIN3_MPORTP9_Pos)                   /*!< GPIO_PORT MPIN3: MPORTP9 Mask       */
#define GPIO_PORT_MPIN3_MPORTP10_Pos                          10                                                        /*!< GPIO_PORT MPIN3: MPORTP10 Position  */
#define GPIO_PORT_MPIN3_MPORTP10_Msk                          (0x01UL << GPIO_PORT_MPIN3_MPORTP10_Pos)                  /*!< GPIO_PORT MPIN3: MPORTP10 Mask      */
#define GPIO_PORT_MPIN3_MPORTP11_Pos                          11                                                        /*!< GPIO_PORT MPIN3: MPORTP11 Position  */
#define GPIO_PORT_MPIN3_MPORTP11_Msk                          (0x01UL << GPIO_PORT_MPIN3_MPORTP11_Pos)                  /*!< GPIO_PORT MPIN3: MPORTP11 Mask      */
#define GPIO_PORT_MPIN3_MPORTP12_Pos                          12                                                        /*!< GPIO_PORT MPIN3: MPORTP12 Position  */
#define GPIO_PORT_MPIN3_MPORTP12_Msk                          (0x01UL << GPIO_PORT_MPIN3_MPORTP12_Pos)                  /*!< GPIO_PORT MPIN3: MPORTP12 Mask      */
#define GPIO_PORT_MPIN3_MPORTP13_Pos                          13                                                        /*!< GPIO_PORT MPIN3: MPORTP13 Position  */
#define GPIO_PORT_MPIN3_MPORTP13_Msk                          (0x01UL << GPIO_PORT_MPIN3_MPORTP13_Pos)                  /*!< GPIO_PORT MPIN3: MPORTP13 Mask      */
#define GPIO_PORT_MPIN3_MPORTP14_Pos                          14                                                        /*!< GPIO_PORT MPIN3: MPORTP14 Position  */
#define GPIO_PORT_MPIN3_MPORTP14_Msk                          (0x01UL << GPIO_PORT_MPIN3_MPORTP14_Pos)                  /*!< GPIO_PORT MPIN3: MPORTP14 Mask      */
#define GPIO_PORT_MPIN3_MPORTP15_Pos                          15                                                        /*!< GPIO_PORT MPIN3: MPORTP15 Position  */
#define GPIO_PORT_MPIN3_MPORTP15_Msk                          (0x01UL << GPIO_PORT_MPIN3_MPORTP15_Pos)                  /*!< GPIO_PORT MPIN3: MPORTP15 Mask      */
#define GPIO_PORT_MPIN3_MPORTP16_Pos                          16                                                        /*!< GPIO_PORT MPIN3: MPORTP16 Position  */
#define GPIO_PORT_MPIN3_MPORTP16_Msk                          (0x01UL << GPIO_PORT_MPIN3_MPORTP16_Pos)                  /*!< GPIO_PORT MPIN3: MPORTP16 Mask      */
#define GPIO_PORT_MPIN3_MPORTP17_Pos                          17                                                        /*!< GPIO_PORT MPIN3: MPORTP17 Position  */
#define GPIO_PORT_MPIN3_MPORTP17_Msk                          (0x01UL << GPIO_PORT_MPIN3_MPORTP17_Pos)                  /*!< GPIO_PORT MPIN3: MPORTP17 Mask      */
#define GPIO_PORT_MPIN3_MPORTP18_Pos                          18                                                        /*!< GPIO_PORT MPIN3: MPORTP18 Position  */
#define GPIO_PORT_MPIN3_MPORTP18_Msk                          (0x01UL << GPIO_PORT_MPIN3_MPORTP18_Pos)                  /*!< GPIO_PORT MPIN3: MPORTP18 Mask      */
#define GPIO_PORT_MPIN3_MPORTP19_Pos                          19                                                        /*!< GPIO_PORT MPIN3: MPORTP19 Position  */
#define GPIO_PORT_MPIN3_MPORTP19_Msk                          (0x01UL << GPIO_PORT_MPIN3_MPORTP19_Pos)                  /*!< GPIO_PORT MPIN3: MPORTP19 Mask      */
#define GPIO_PORT_MPIN3_MPORTP20_Pos                          20                                                        /*!< GPIO_PORT MPIN3: MPORTP20 Position  */
#define GPIO_PORT_MPIN3_MPORTP20_Msk                          (0x01UL << GPIO_PORT_MPIN3_MPORTP20_Pos)                  /*!< GPIO_PORT MPIN3: MPORTP20 Mask      */
#define GPIO_PORT_MPIN3_MPORTP21_Pos                          21                                                        /*!< GPIO_PORT MPIN3: MPORTP21 Position  */
#define GPIO_PORT_MPIN3_MPORTP21_Msk                          (0x01UL << GPIO_PORT_MPIN3_MPORTP21_Pos)                  /*!< GPIO_PORT MPIN3: MPORTP21 Mask      */
#define GPIO_PORT_MPIN3_MPORTP22_Pos                          22                                                        /*!< GPIO_PORT MPIN3: MPORTP22 Position  */
#define GPIO_PORT_MPIN3_MPORTP22_Msk                          (0x01UL << GPIO_PORT_MPIN3_MPORTP22_Pos)                  /*!< GPIO_PORT MPIN3: MPORTP22 Mask      */
#define GPIO_PORT_MPIN3_MPORTP23_Pos                          23                                                        /*!< GPIO_PORT MPIN3: MPORTP23 Position  */
#define GPIO_PORT_MPIN3_MPORTP23_Msk                          (0x01UL << GPIO_PORT_MPIN3_MPORTP23_Pos)                  /*!< GPIO_PORT MPIN3: MPORTP23 Mask      */
#define GPIO_PORT_MPIN3_MPORTP24_Pos                          24                                                        /*!< GPIO_PORT MPIN3: MPORTP24 Position  */
#define GPIO_PORT_MPIN3_MPORTP24_Msk                          (0x01UL << GPIO_PORT_MPIN3_MPORTP24_Pos)                  /*!< GPIO_PORT MPIN3: MPORTP24 Mask      */
#define GPIO_PORT_MPIN3_MPORTP25_Pos                          25                                                        /*!< GPIO_PORT MPIN3: MPORTP25 Position  */
#define GPIO_PORT_MPIN3_MPORTP25_Msk                          (0x01UL << GPIO_PORT_MPIN3_MPORTP25_Pos)                  /*!< GPIO_PORT MPIN3: MPORTP25 Mask      */
#define GPIO_PORT_MPIN3_MPORTP26_Pos                          26                                                        /*!< GPIO_PORT MPIN3: MPORTP26 Position  */
#define GPIO_PORT_MPIN3_MPORTP26_Msk                          (0x01UL << GPIO_PORT_MPIN3_MPORTP26_Pos)                  /*!< GPIO_PORT MPIN3: MPORTP26 Mask      */
#define GPIO_PORT_MPIN3_MPORTP27_Pos                          27                                                        /*!< GPIO_PORT MPIN3: MPORTP27 Position  */
#define GPIO_PORT_MPIN3_MPORTP27_Msk                          (0x01UL << GPIO_PORT_MPIN3_MPORTP27_Pos)                  /*!< GPIO_PORT MPIN3: MPORTP27 Mask      */
#define GPIO_PORT_MPIN3_MPORTP28_Pos                          28                                                        /*!< GPIO_PORT MPIN3: MPORTP28 Position  */
#define GPIO_PORT_MPIN3_MPORTP28_Msk                          (0x01UL << GPIO_PORT_MPIN3_MPORTP28_Pos)                  /*!< GPIO_PORT MPIN3: MPORTP28 Mask      */
#define GPIO_PORT_MPIN3_MPORTP29_Pos                          29                                                        /*!< GPIO_PORT MPIN3: MPORTP29 Position  */
#define GPIO_PORT_MPIN3_MPORTP29_Msk                          (0x01UL << GPIO_PORT_MPIN3_MPORTP29_Pos)                  /*!< GPIO_PORT MPIN3: MPORTP29 Mask      */
#define GPIO_PORT_MPIN3_MPORTP30_Pos                          30                                                        /*!< GPIO_PORT MPIN3: MPORTP30 Position  */
#define GPIO_PORT_MPIN3_MPORTP30_Msk                          (0x01UL << GPIO_PORT_MPIN3_MPORTP30_Pos)                  /*!< GPIO_PORT MPIN3: MPORTP30 Mask      */
#define GPIO_PORT_MPIN3_MPORTP31_Pos                          31                                                        /*!< GPIO_PORT MPIN3: MPORTP31 Position  */
#define GPIO_PORT_MPIN3_MPORTP31_Msk                          (0x01UL << GPIO_PORT_MPIN3_MPORTP31_Pos)                  /*!< GPIO_PORT MPIN3: MPORTP31 Mask      */

// -------------------------------------  GPIO_PORT_MPIN4  ----------------------------------------
#define GPIO_PORT_MPIN4_MPORTP0_Pos                           0                                                         /*!< GPIO_PORT MPIN4: MPORTP0 Position   */
#define GPIO_PORT_MPIN4_MPORTP0_Msk                           (0x01UL << GPIO_PORT_MPIN4_MPORTP0_Pos)                   /*!< GPIO_PORT MPIN4: MPORTP0 Mask       */
#define GPIO_PORT_MPIN4_MPORTP1_Pos                           1                                                         /*!< GPIO_PORT MPIN4: MPORTP1 Position   */
#define GPIO_PORT_MPIN4_MPORTP1_Msk                           (0x01UL << GPIO_PORT_MPIN4_MPORTP1_Pos)                   /*!< GPIO_PORT MPIN4: MPORTP1 Mask       */
#define GPIO_PORT_MPIN4_MPORTP2_Pos                           2                                                         /*!< GPIO_PORT MPIN4: MPORTP2 Position   */
#define GPIO_PORT_MPIN4_MPORTP2_Msk                           (0x01UL << GPIO_PORT_MPIN4_MPORTP2_Pos)                   /*!< GPIO_PORT MPIN4: MPORTP2 Mask       */
#define GPIO_PORT_MPIN4_MPORTP3_Pos                           3                                                         /*!< GPIO_PORT MPIN4: MPORTP3 Position   */
#define GPIO_PORT_MPIN4_MPORTP3_Msk                           (0x01UL << GPIO_PORT_MPIN4_MPORTP3_Pos)                   /*!< GPIO_PORT MPIN4: MPORTP3 Mask       */
#define GPIO_PORT_MPIN4_MPORTP4_Pos                           4                                                         /*!< GPIO_PORT MPIN4: MPORTP4 Position   */
#define GPIO_PORT_MPIN4_MPORTP4_Msk                           (0x01UL << GPIO_PORT_MPIN4_MPORTP4_Pos)                   /*!< GPIO_PORT MPIN4: MPORTP4 Mask       */
#define GPIO_PORT_MPIN4_MPORTP5_Pos                           5                                                         /*!< GPIO_PORT MPIN4: MPORTP5 Position   */
#define GPIO_PORT_MPIN4_MPORTP5_Msk                           (0x01UL << GPIO_PORT_MPIN4_MPORTP5_Pos)                   /*!< GPIO_PORT MPIN4: MPORTP5 Mask       */
#define GPIO_PORT_MPIN4_MPORTP6_Pos                           6                                                         /*!< GPIO_PORT MPIN4: MPORTP6 Position   */
#define GPIO_PORT_MPIN4_MPORTP6_Msk                           (0x01UL << GPIO_PORT_MPIN4_MPORTP6_Pos)                   /*!< GPIO_PORT MPIN4: MPORTP6 Mask       */
#define GPIO_PORT_MPIN4_MPORTP7_Pos                           7                                                         /*!< GPIO_PORT MPIN4: MPORTP7 Position   */
#define GPIO_PORT_MPIN4_MPORTP7_Msk                           (0x01UL << GPIO_PORT_MPIN4_MPORTP7_Pos)                   /*!< GPIO_PORT MPIN4: MPORTP7 Mask       */
#define GPIO_PORT_MPIN4_MPORTP8_Pos                           8                                                         /*!< GPIO_PORT MPIN4: MPORTP8 Position   */
#define GPIO_PORT_MPIN4_MPORTP8_Msk                           (0x01UL << GPIO_PORT_MPIN4_MPORTP8_Pos)                   /*!< GPIO_PORT MPIN4: MPORTP8 Mask       */
#define GPIO_PORT_MPIN4_MPORTP9_Pos                           9                                                         /*!< GPIO_PORT MPIN4: MPORTP9 Position   */
#define GPIO_PORT_MPIN4_MPORTP9_Msk                           (0x01UL << GPIO_PORT_MPIN4_MPORTP9_Pos)                   /*!< GPIO_PORT MPIN4: MPORTP9 Mask       */
#define GPIO_PORT_MPIN4_MPORTP10_Pos                          10                                                        /*!< GPIO_PORT MPIN4: MPORTP10 Position  */
#define GPIO_PORT_MPIN4_MPORTP10_Msk                          (0x01UL << GPIO_PORT_MPIN4_MPORTP10_Pos)                  /*!< GPIO_PORT MPIN4: MPORTP10 Mask      */
#define GPIO_PORT_MPIN4_MPORTP11_Pos                          11                                                        /*!< GPIO_PORT MPIN4: MPORTP11 Position  */
#define GPIO_PORT_MPIN4_MPORTP11_Msk                          (0x01UL << GPIO_PORT_MPIN4_MPORTP11_Pos)                  /*!< GPIO_PORT MPIN4: MPORTP11 Mask      */
#define GPIO_PORT_MPIN4_MPORTP12_Pos                          12                                                        /*!< GPIO_PORT MPIN4: MPORTP12 Position  */
#define GPIO_PORT_MPIN4_MPORTP12_Msk                          (0x01UL << GPIO_PORT_MPIN4_MPORTP12_Pos)                  /*!< GPIO_PORT MPIN4: MPORTP12 Mask      */
#define GPIO_PORT_MPIN4_MPORTP13_Pos                          13                                                        /*!< GPIO_PORT MPIN4: MPORTP13 Position  */
#define GPIO_PORT_MPIN4_MPORTP13_Msk                          (0x01UL << GPIO_PORT_MPIN4_MPORTP13_Pos)                  /*!< GPIO_PORT MPIN4: MPORTP13 Mask      */
#define GPIO_PORT_MPIN4_MPORTP14_Pos                          14                                                        /*!< GPIO_PORT MPIN4: MPORTP14 Position  */
#define GPIO_PORT_MPIN4_MPORTP14_Msk                          (0x01UL << GPIO_PORT_MPIN4_MPORTP14_Pos)                  /*!< GPIO_PORT MPIN4: MPORTP14 Mask      */
#define GPIO_PORT_MPIN4_MPORTP15_Pos                          15                                                        /*!< GPIO_PORT MPIN4: MPORTP15 Position  */
#define GPIO_PORT_MPIN4_MPORTP15_Msk                          (0x01UL << GPIO_PORT_MPIN4_MPORTP15_Pos)                  /*!< GPIO_PORT MPIN4: MPORTP15 Mask      */
#define GPIO_PORT_MPIN4_MPORTP16_Pos                          16                                                        /*!< GPIO_PORT MPIN4: MPORTP16 Position  */
#define GPIO_PORT_MPIN4_MPORTP16_Msk                          (0x01UL << GPIO_PORT_MPIN4_MPORTP16_Pos)                  /*!< GPIO_PORT MPIN4: MPORTP16 Mask      */
#define GPIO_PORT_MPIN4_MPORTP17_Pos                          17                                                        /*!< GPIO_PORT MPIN4: MPORTP17 Position  */
#define GPIO_PORT_MPIN4_MPORTP17_Msk                          (0x01UL << GPIO_PORT_MPIN4_MPORTP17_Pos)                  /*!< GPIO_PORT MPIN4: MPORTP17 Mask      */
#define GPIO_PORT_MPIN4_MPORTP18_Pos                          18                                                        /*!< GPIO_PORT MPIN4: MPORTP18 Position  */
#define GPIO_PORT_MPIN4_MPORTP18_Msk                          (0x01UL << GPIO_PORT_MPIN4_MPORTP18_Pos)                  /*!< GPIO_PORT MPIN4: MPORTP18 Mask      */
#define GPIO_PORT_MPIN4_MPORTP19_Pos                          19                                                        /*!< GPIO_PORT MPIN4: MPORTP19 Position  */
#define GPIO_PORT_MPIN4_MPORTP19_Msk                          (0x01UL << GPIO_PORT_MPIN4_MPORTP19_Pos)                  /*!< GPIO_PORT MPIN4: MPORTP19 Mask      */
#define GPIO_PORT_MPIN4_MPORTP20_Pos                          20                                                        /*!< GPIO_PORT MPIN4: MPORTP20 Position  */
#define GPIO_PORT_MPIN4_MPORTP20_Msk                          (0x01UL << GPIO_PORT_MPIN4_MPORTP20_Pos)                  /*!< GPIO_PORT MPIN4: MPORTP20 Mask      */
#define GPIO_PORT_MPIN4_MPORTP21_Pos                          21                                                        /*!< GPIO_PORT MPIN4: MPORTP21 Position  */
#define GPIO_PORT_MPIN4_MPORTP21_Msk                          (0x01UL << GPIO_PORT_MPIN4_MPORTP21_Pos)                  /*!< GPIO_PORT MPIN4: MPORTP21 Mask      */
#define GPIO_PORT_MPIN4_MPORTP22_Pos                          22                                                        /*!< GPIO_PORT MPIN4: MPORTP22 Position  */
#define GPIO_PORT_MPIN4_MPORTP22_Msk                          (0x01UL << GPIO_PORT_MPIN4_MPORTP22_Pos)                  /*!< GPIO_PORT MPIN4: MPORTP22 Mask      */
#define GPIO_PORT_MPIN4_MPORTP23_Pos                          23                                                        /*!< GPIO_PORT MPIN4: MPORTP23 Position  */
#define GPIO_PORT_MPIN4_MPORTP23_Msk                          (0x01UL << GPIO_PORT_MPIN4_MPORTP23_Pos)                  /*!< GPIO_PORT MPIN4: MPORTP23 Mask      */
#define GPIO_PORT_MPIN4_MPORTP24_Pos                          24                                                        /*!< GPIO_PORT MPIN4: MPORTP24 Position  */
#define GPIO_PORT_MPIN4_MPORTP24_Msk                          (0x01UL << GPIO_PORT_MPIN4_MPORTP24_Pos)                  /*!< GPIO_PORT MPIN4: MPORTP24 Mask      */
#define GPIO_PORT_MPIN4_MPORTP25_Pos                          25                                                        /*!< GPIO_PORT MPIN4: MPORTP25 Position  */
#define GPIO_PORT_MPIN4_MPORTP25_Msk                          (0x01UL << GPIO_PORT_MPIN4_MPORTP25_Pos)                  /*!< GPIO_PORT MPIN4: MPORTP25 Mask      */
#define GPIO_PORT_MPIN4_MPORTP26_Pos                          26                                                        /*!< GPIO_PORT MPIN4: MPORTP26 Position  */
#define GPIO_PORT_MPIN4_MPORTP26_Msk                          (0x01UL << GPIO_PORT_MPIN4_MPORTP26_Pos)                  /*!< GPIO_PORT MPIN4: MPORTP26 Mask      */
#define GPIO_PORT_MPIN4_MPORTP27_Pos                          27                                                        /*!< GPIO_PORT MPIN4: MPORTP27 Position  */
#define GPIO_PORT_MPIN4_MPORTP27_Msk                          (0x01UL << GPIO_PORT_MPIN4_MPORTP27_Pos)                  /*!< GPIO_PORT MPIN4: MPORTP27 Mask      */
#define GPIO_PORT_MPIN4_MPORTP28_Pos                          28                                                        /*!< GPIO_PORT MPIN4: MPORTP28 Position  */
#define GPIO_PORT_MPIN4_MPORTP28_Msk                          (0x01UL << GPIO_PORT_MPIN4_MPORTP28_Pos)                  /*!< GPIO_PORT MPIN4: MPORTP28 Mask      */
#define GPIO_PORT_MPIN4_MPORTP29_Pos                          29                                                        /*!< GPIO_PORT MPIN4: MPORTP29 Position  */
#define GPIO_PORT_MPIN4_MPORTP29_Msk                          (0x01UL << GPIO_PORT_MPIN4_MPORTP29_Pos)                  /*!< GPIO_PORT MPIN4: MPORTP29 Mask      */
#define GPIO_PORT_MPIN4_MPORTP30_Pos                          30                                                        /*!< GPIO_PORT MPIN4: MPORTP30 Position  */
#define GPIO_PORT_MPIN4_MPORTP30_Msk                          (0x01UL << GPIO_PORT_MPIN4_MPORTP30_Pos)                  /*!< GPIO_PORT MPIN4: MPORTP30 Mask      */
#define GPIO_PORT_MPIN4_MPORTP31_Pos                          31                                                        /*!< GPIO_PORT MPIN4: MPORTP31 Position  */
#define GPIO_PORT_MPIN4_MPORTP31_Msk                          (0x01UL << GPIO_PORT_MPIN4_MPORTP31_Pos)                  /*!< GPIO_PORT MPIN4: MPORTP31 Mask      */

// -------------------------------------  GPIO_PORT_MPIN5  ----------------------------------------
#define GPIO_PORT_MPIN5_MPORTP0_Pos                           0                                                         /*!< GPIO_PORT MPIN5: MPORTP0 Position   */
#define GPIO_PORT_MPIN5_MPORTP0_Msk                           (0x01UL << GPIO_PORT_MPIN5_MPORTP0_Pos)                   /*!< GPIO_PORT MPIN5: MPORTP0 Mask       */
#define GPIO_PORT_MPIN5_MPORTP1_Pos                           1                                                         /*!< GPIO_PORT MPIN5: MPORTP1 Position   */
#define GPIO_PORT_MPIN5_MPORTP1_Msk                           (0x01UL << GPIO_PORT_MPIN5_MPORTP1_Pos)                   /*!< GPIO_PORT MPIN5: MPORTP1 Mask       */
#define GPIO_PORT_MPIN5_MPORTP2_Pos                           2                                                         /*!< GPIO_PORT MPIN5: MPORTP2 Position   */
#define GPIO_PORT_MPIN5_MPORTP2_Msk                           (0x01UL << GPIO_PORT_MPIN5_MPORTP2_Pos)                   /*!< GPIO_PORT MPIN5: MPORTP2 Mask       */
#define GPIO_PORT_MPIN5_MPORTP3_Pos                           3                                                         /*!< GPIO_PORT MPIN5: MPORTP3 Position   */
#define GPIO_PORT_MPIN5_MPORTP3_Msk                           (0x01UL << GPIO_PORT_MPIN5_MPORTP3_Pos)                   /*!< GPIO_PORT MPIN5: MPORTP3 Mask       */
#define GPIO_PORT_MPIN5_MPORTP4_Pos                           4                                                         /*!< GPIO_PORT MPIN5: MPORTP4 Position   */
#define GPIO_PORT_MPIN5_MPORTP4_Msk                           (0x01UL << GPIO_PORT_MPIN5_MPORTP4_Pos)                   /*!< GPIO_PORT MPIN5: MPORTP4 Mask       */
#define GPIO_PORT_MPIN5_MPORTP5_Pos                           5                                                         /*!< GPIO_PORT MPIN5: MPORTP5 Position   */
#define GPIO_PORT_MPIN5_MPORTP5_Msk                           (0x01UL << GPIO_PORT_MPIN5_MPORTP5_Pos)                   /*!< GPIO_PORT MPIN5: MPORTP5 Mask       */
#define GPIO_PORT_MPIN5_MPORTP6_Pos                           6                                                         /*!< GPIO_PORT MPIN5: MPORTP6 Position   */
#define GPIO_PORT_MPIN5_MPORTP6_Msk                           (0x01UL << GPIO_PORT_MPIN5_MPORTP6_Pos)                   /*!< GPIO_PORT MPIN5: MPORTP6 Mask       */
#define GPIO_PORT_MPIN5_MPORTP7_Pos                           7                                                         /*!< GPIO_PORT MPIN5: MPORTP7 Position   */
#define GPIO_PORT_MPIN5_MPORTP7_Msk                           (0x01UL << GPIO_PORT_MPIN5_MPORTP7_Pos)                   /*!< GPIO_PORT MPIN5: MPORTP7 Mask       */
#define GPIO_PORT_MPIN5_MPORTP8_Pos                           8                                                         /*!< GPIO_PORT MPIN5: MPORTP8 Position   */
#define GPIO_PORT_MPIN5_MPORTP8_Msk                           (0x01UL << GPIO_PORT_MPIN5_MPORTP8_Pos)                   /*!< GPIO_PORT MPIN5: MPORTP8 Mask       */
#define GPIO_PORT_MPIN5_MPORTP9_Pos                           9                                                         /*!< GPIO_PORT MPIN5: MPORTP9 Position   */
#define GPIO_PORT_MPIN5_MPORTP9_Msk                           (0x01UL << GPIO_PORT_MPIN5_MPORTP9_Pos)                   /*!< GPIO_PORT MPIN5: MPORTP9 Mask       */
#define GPIO_PORT_MPIN5_MPORTP10_Pos                          10                                                        /*!< GPIO_PORT MPIN5: MPORTP10 Position  */
#define GPIO_PORT_MPIN5_MPORTP10_Msk                          (0x01UL << GPIO_PORT_MPIN5_MPORTP10_Pos)                  /*!< GPIO_PORT MPIN5: MPORTP10 Mask      */
#define GPIO_PORT_MPIN5_MPORTP11_Pos                          11                                                        /*!< GPIO_PORT MPIN5: MPORTP11 Position  */
#define GPIO_PORT_MPIN5_MPORTP11_Msk                          (0x01UL << GPIO_PORT_MPIN5_MPORTP11_Pos)                  /*!< GPIO_PORT MPIN5: MPORTP11 Mask      */
#define GPIO_PORT_MPIN5_MPORTP12_Pos                          12                                                        /*!< GPIO_PORT MPIN5: MPORTP12 Position  */
#define GPIO_PORT_MPIN5_MPORTP12_Msk                          (0x01UL << GPIO_PORT_MPIN5_MPORTP12_Pos)                  /*!< GPIO_PORT MPIN5: MPORTP12 Mask      */
#define GPIO_PORT_MPIN5_MPORTP13_Pos                          13                                                        /*!< GPIO_PORT MPIN5: MPORTP13 Position  */
#define GPIO_PORT_MPIN5_MPORTP13_Msk                          (0x01UL << GPIO_PORT_MPIN5_MPORTP13_Pos)                  /*!< GPIO_PORT MPIN5: MPORTP13 Mask      */
#define GPIO_PORT_MPIN5_MPORTP14_Pos                          14                                                        /*!< GPIO_PORT MPIN5: MPORTP14 Position  */
#define GPIO_PORT_MPIN5_MPORTP14_Msk                          (0x01UL << GPIO_PORT_MPIN5_MPORTP14_Pos)                  /*!< GPIO_PORT MPIN5: MPORTP14 Mask      */
#define GPIO_PORT_MPIN5_MPORTP15_Pos                          15                                                        /*!< GPIO_PORT MPIN5: MPORTP15 Position  */
#define GPIO_PORT_MPIN5_MPORTP15_Msk                          (0x01UL << GPIO_PORT_MPIN5_MPORTP15_Pos)                  /*!< GPIO_PORT MPIN5: MPORTP15 Mask      */
#define GPIO_PORT_MPIN5_MPORTP16_Pos                          16                                                        /*!< GPIO_PORT MPIN5: MPORTP16 Position  */
#define GPIO_PORT_MPIN5_MPORTP16_Msk                          (0x01UL << GPIO_PORT_MPIN5_MPORTP16_Pos)                  /*!< GPIO_PORT MPIN5: MPORTP16 Mask      */
#define GPIO_PORT_MPIN5_MPORTP17_Pos                          17                                                        /*!< GPIO_PORT MPIN5: MPORTP17 Position  */
#define GPIO_PORT_MPIN5_MPORTP17_Msk                          (0x01UL << GPIO_PORT_MPIN5_MPORTP17_Pos)                  /*!< GPIO_PORT MPIN5: MPORTP17 Mask      */
#define GPIO_PORT_MPIN5_MPORTP18_Pos                          18                                                        /*!< GPIO_PORT MPIN5: MPORTP18 Position  */
#define GPIO_PORT_MPIN5_MPORTP18_Msk                          (0x01UL << GPIO_PORT_MPIN5_MPORTP18_Pos)                  /*!< GPIO_PORT MPIN5: MPORTP18 Mask      */
#define GPIO_PORT_MPIN5_MPORTP19_Pos                          19                                                        /*!< GPIO_PORT MPIN5: MPORTP19 Position  */
#define GPIO_PORT_MPIN5_MPORTP19_Msk                          (0x01UL << GPIO_PORT_MPIN5_MPORTP19_Pos)                  /*!< GPIO_PORT MPIN5: MPORTP19 Mask      */
#define GPIO_PORT_MPIN5_MPORTP20_Pos                          20                                                        /*!< GPIO_PORT MPIN5: MPORTP20 Position  */
#define GPIO_PORT_MPIN5_MPORTP20_Msk                          (0x01UL << GPIO_PORT_MPIN5_MPORTP20_Pos)                  /*!< GPIO_PORT MPIN5: MPORTP20 Mask      */
#define GPIO_PORT_MPIN5_MPORTP21_Pos                          21                                                        /*!< GPIO_PORT MPIN5: MPORTP21 Position  */
#define GPIO_PORT_MPIN5_MPORTP21_Msk                          (0x01UL << GPIO_PORT_MPIN5_MPORTP21_Pos)                  /*!< GPIO_PORT MPIN5: MPORTP21 Mask      */
#define GPIO_PORT_MPIN5_MPORTP22_Pos                          22                                                        /*!< GPIO_PORT MPIN5: MPORTP22 Position  */
#define GPIO_PORT_MPIN5_MPORTP22_Msk                          (0x01UL << GPIO_PORT_MPIN5_MPORTP22_Pos)                  /*!< GPIO_PORT MPIN5: MPORTP22 Mask      */
#define GPIO_PORT_MPIN5_MPORTP23_Pos                          23                                                        /*!< GPIO_PORT MPIN5: MPORTP23 Position  */
#define GPIO_PORT_MPIN5_MPORTP23_Msk                          (0x01UL << GPIO_PORT_MPIN5_MPORTP23_Pos)                  /*!< GPIO_PORT MPIN5: MPORTP23 Mask      */
#define GPIO_PORT_MPIN5_MPORTP24_Pos                          24                                                        /*!< GPIO_PORT MPIN5: MPORTP24 Position  */
#define GPIO_PORT_MPIN5_MPORTP24_Msk                          (0x01UL << GPIO_PORT_MPIN5_MPORTP24_Pos)                  /*!< GPIO_PORT MPIN5: MPORTP24 Mask      */
#define GPIO_PORT_MPIN5_MPORTP25_Pos                          25                                                        /*!< GPIO_PORT MPIN5: MPORTP25 Position  */
#define GPIO_PORT_MPIN5_MPORTP25_Msk                          (0x01UL << GPIO_PORT_MPIN5_MPORTP25_Pos)                  /*!< GPIO_PORT MPIN5: MPORTP25 Mask      */
#define GPIO_PORT_MPIN5_MPORTP26_Pos                          26                                                        /*!< GPIO_PORT MPIN5: MPORTP26 Position  */
#define GPIO_PORT_MPIN5_MPORTP26_Msk                          (0x01UL << GPIO_PORT_MPIN5_MPORTP26_Pos)                  /*!< GPIO_PORT MPIN5: MPORTP26 Mask      */
#define GPIO_PORT_MPIN5_MPORTP27_Pos                          27                                                        /*!< GPIO_PORT MPIN5: MPORTP27 Position  */
#define GPIO_PORT_MPIN5_MPORTP27_Msk                          (0x01UL << GPIO_PORT_MPIN5_MPORTP27_Pos)                  /*!< GPIO_PORT MPIN5: MPORTP27 Mask      */
#define GPIO_PORT_MPIN5_MPORTP28_Pos                          28                                                        /*!< GPIO_PORT MPIN5: MPORTP28 Position  */
#define GPIO_PORT_MPIN5_MPORTP28_Msk                          (0x01UL << GPIO_PORT_MPIN5_MPORTP28_Pos)                  /*!< GPIO_PORT MPIN5: MPORTP28 Mask      */
#define GPIO_PORT_MPIN5_MPORTP29_Pos                          29                                                        /*!< GPIO_PORT MPIN5: MPORTP29 Position  */
#define GPIO_PORT_MPIN5_MPORTP29_Msk                          (0x01UL << GPIO_PORT_MPIN5_MPORTP29_Pos)                  /*!< GPIO_PORT MPIN5: MPORTP29 Mask      */
#define GPIO_PORT_MPIN5_MPORTP30_Pos                          30                                                        /*!< GPIO_PORT MPIN5: MPORTP30 Position  */
#define GPIO_PORT_MPIN5_MPORTP30_Msk                          (0x01UL << GPIO_PORT_MPIN5_MPORTP30_Pos)                  /*!< GPIO_PORT MPIN5: MPORTP30 Mask      */
#define GPIO_PORT_MPIN5_MPORTP31_Pos                          31                                                        /*!< GPIO_PORT MPIN5: MPORTP31 Position  */
#define GPIO_PORT_MPIN5_MPORTP31_Msk                          (0x01UL << GPIO_PORT_MPIN5_MPORTP31_Pos)                  /*!< GPIO_PORT MPIN5: MPORTP31 Mask      */

// -------------------------------------  GPIO_PORT_MPIN6  ----------------------------------------
#define GPIO_PORT_MPIN6_MPORTP0_Pos                           0                                                         /*!< GPIO_PORT MPIN6: MPORTP0 Position   */
#define GPIO_PORT_MPIN6_MPORTP0_Msk                           (0x01UL << GPIO_PORT_MPIN6_MPORTP0_Pos)                   /*!< GPIO_PORT MPIN6: MPORTP0 Mask       */
#define GPIO_PORT_MPIN6_MPORTP1_Pos                           1                                                         /*!< GPIO_PORT MPIN6: MPORTP1 Position   */
#define GPIO_PORT_MPIN6_MPORTP1_Msk                           (0x01UL << GPIO_PORT_MPIN6_MPORTP1_Pos)                   /*!< GPIO_PORT MPIN6: MPORTP1 Mask       */
#define GPIO_PORT_MPIN6_MPORTP2_Pos                           2                                                         /*!< GPIO_PORT MPIN6: MPORTP2 Position   */
#define GPIO_PORT_MPIN6_MPORTP2_Msk                           (0x01UL << GPIO_PORT_MPIN6_MPORTP2_Pos)                   /*!< GPIO_PORT MPIN6: MPORTP2 Mask       */
#define GPIO_PORT_MPIN6_MPORTP3_Pos                           3                                                         /*!< GPIO_PORT MPIN6: MPORTP3 Position   */
#define GPIO_PORT_MPIN6_MPORTP3_Msk                           (0x01UL << GPIO_PORT_MPIN6_MPORTP3_Pos)                   /*!< GPIO_PORT MPIN6: MPORTP3 Mask       */
#define GPIO_PORT_MPIN6_MPORTP4_Pos                           4                                                         /*!< GPIO_PORT MPIN6: MPORTP4 Position   */
#define GPIO_PORT_MPIN6_MPORTP4_Msk                           (0x01UL << GPIO_PORT_MPIN6_MPORTP4_Pos)                   /*!< GPIO_PORT MPIN6: MPORTP4 Mask       */
#define GPIO_PORT_MPIN6_MPORTP5_Pos                           5                                                         /*!< GPIO_PORT MPIN6: MPORTP5 Position   */
#define GPIO_PORT_MPIN6_MPORTP5_Msk                           (0x01UL << GPIO_PORT_MPIN6_MPORTP5_Pos)                   /*!< GPIO_PORT MPIN6: MPORTP5 Mask       */
#define GPIO_PORT_MPIN6_MPORTP6_Pos                           6                                                         /*!< GPIO_PORT MPIN6: MPORTP6 Position   */
#define GPIO_PORT_MPIN6_MPORTP6_Msk                           (0x01UL << GPIO_PORT_MPIN6_MPORTP6_Pos)                   /*!< GPIO_PORT MPIN6: MPORTP6 Mask       */
#define GPIO_PORT_MPIN6_MPORTP7_Pos                           7                                                         /*!< GPIO_PORT MPIN6: MPORTP7 Position   */
#define GPIO_PORT_MPIN6_MPORTP7_Msk                           (0x01UL << GPIO_PORT_MPIN6_MPORTP7_Pos)                   /*!< GPIO_PORT MPIN6: MPORTP7 Mask       */
#define GPIO_PORT_MPIN6_MPORTP8_Pos                           8                                                         /*!< GPIO_PORT MPIN6: MPORTP8 Position   */
#define GPIO_PORT_MPIN6_MPORTP8_Msk                           (0x01UL << GPIO_PORT_MPIN6_MPORTP8_Pos)                   /*!< GPIO_PORT MPIN6: MPORTP8 Mask       */
#define GPIO_PORT_MPIN6_MPORTP9_Pos                           9                                                         /*!< GPIO_PORT MPIN6: MPORTP9 Position   */
#define GPIO_PORT_MPIN6_MPORTP9_Msk                           (0x01UL << GPIO_PORT_MPIN6_MPORTP9_Pos)                   /*!< GPIO_PORT MPIN6: MPORTP9 Mask       */
#define GPIO_PORT_MPIN6_MPORTP10_Pos                          10                                                        /*!< GPIO_PORT MPIN6: MPORTP10 Position  */
#define GPIO_PORT_MPIN6_MPORTP10_Msk                          (0x01UL << GPIO_PORT_MPIN6_MPORTP10_Pos)                  /*!< GPIO_PORT MPIN6: MPORTP10 Mask      */
#define GPIO_PORT_MPIN6_MPORTP11_Pos                          11                                                        /*!< GPIO_PORT MPIN6: MPORTP11 Position  */
#define GPIO_PORT_MPIN6_MPORTP11_Msk                          (0x01UL << GPIO_PORT_MPIN6_MPORTP11_Pos)                  /*!< GPIO_PORT MPIN6: MPORTP11 Mask      */
#define GPIO_PORT_MPIN6_MPORTP12_Pos                          12                                                        /*!< GPIO_PORT MPIN6: MPORTP12 Position  */
#define GPIO_PORT_MPIN6_MPORTP12_Msk                          (0x01UL << GPIO_PORT_MPIN6_MPORTP12_Pos)                  /*!< GPIO_PORT MPIN6: MPORTP12 Mask      */
#define GPIO_PORT_MPIN6_MPORTP13_Pos                          13                                                        /*!< GPIO_PORT MPIN6: MPORTP13 Position  */
#define GPIO_PORT_MPIN6_MPORTP13_Msk                          (0x01UL << GPIO_PORT_MPIN6_MPORTP13_Pos)                  /*!< GPIO_PORT MPIN6: MPORTP13 Mask      */
#define GPIO_PORT_MPIN6_MPORTP14_Pos                          14                                                        /*!< GPIO_PORT MPIN6: MPORTP14 Position  */
#define GPIO_PORT_MPIN6_MPORTP14_Msk                          (0x01UL << GPIO_PORT_MPIN6_MPORTP14_Pos)                  /*!< GPIO_PORT MPIN6: MPORTP14 Mask      */
#define GPIO_PORT_MPIN6_MPORTP15_Pos                          15                                                        /*!< GPIO_PORT MPIN6: MPORTP15 Position  */
#define GPIO_PORT_MPIN6_MPORTP15_Msk                          (0x01UL << GPIO_PORT_MPIN6_MPORTP15_Pos)                  /*!< GPIO_PORT MPIN6: MPORTP15 Mask      */
#define GPIO_PORT_MPIN6_MPORTP16_Pos                          16                                                        /*!< GPIO_PORT MPIN6: MPORTP16 Position  */
#define GPIO_PORT_MPIN6_MPORTP16_Msk                          (0x01UL << GPIO_PORT_MPIN6_MPORTP16_Pos)                  /*!< GPIO_PORT MPIN6: MPORTP16 Mask      */
#define GPIO_PORT_MPIN6_MPORTP17_Pos                          17                                                        /*!< GPIO_PORT MPIN6: MPORTP17 Position  */
#define GPIO_PORT_MPIN6_MPORTP17_Msk                          (0x01UL << GPIO_PORT_MPIN6_MPORTP17_Pos)                  /*!< GPIO_PORT MPIN6: MPORTP17 Mask      */
#define GPIO_PORT_MPIN6_MPORTP18_Pos                          18                                                        /*!< GPIO_PORT MPIN6: MPORTP18 Position  */
#define GPIO_PORT_MPIN6_MPORTP18_Msk                          (0x01UL << GPIO_PORT_MPIN6_MPORTP18_Pos)                  /*!< GPIO_PORT MPIN6: MPORTP18 Mask      */
#define GPIO_PORT_MPIN6_MPORTP19_Pos                          19                                                        /*!< GPIO_PORT MPIN6: MPORTP19 Position  */
#define GPIO_PORT_MPIN6_MPORTP19_Msk                          (0x01UL << GPIO_PORT_MPIN6_MPORTP19_Pos)                  /*!< GPIO_PORT MPIN6: MPORTP19 Mask      */
#define GPIO_PORT_MPIN6_MPORTP20_Pos                          20                                                        /*!< GPIO_PORT MPIN6: MPORTP20 Position  */
#define GPIO_PORT_MPIN6_MPORTP20_Msk                          (0x01UL << GPIO_PORT_MPIN6_MPORTP20_Pos)                  /*!< GPIO_PORT MPIN6: MPORTP20 Mask      */
#define GPIO_PORT_MPIN6_MPORTP21_Pos                          21                                                        /*!< GPIO_PORT MPIN6: MPORTP21 Position  */
#define GPIO_PORT_MPIN6_MPORTP21_Msk                          (0x01UL << GPIO_PORT_MPIN6_MPORTP21_Pos)                  /*!< GPIO_PORT MPIN6: MPORTP21 Mask      */
#define GPIO_PORT_MPIN6_MPORTP22_Pos                          22                                                        /*!< GPIO_PORT MPIN6: MPORTP22 Position  */
#define GPIO_PORT_MPIN6_MPORTP22_Msk                          (0x01UL << GPIO_PORT_MPIN6_MPORTP22_Pos)                  /*!< GPIO_PORT MPIN6: MPORTP22 Mask      */
#define GPIO_PORT_MPIN6_MPORTP23_Pos                          23                                                        /*!< GPIO_PORT MPIN6: MPORTP23 Position  */
#define GPIO_PORT_MPIN6_MPORTP23_Msk                          (0x01UL << GPIO_PORT_MPIN6_MPORTP23_Pos)                  /*!< GPIO_PORT MPIN6: MPORTP23 Mask      */
#define GPIO_PORT_MPIN6_MPORTP24_Pos                          24                                                        /*!< GPIO_PORT MPIN6: MPORTP24 Position  */
#define GPIO_PORT_MPIN6_MPORTP24_Msk                          (0x01UL << GPIO_PORT_MPIN6_MPORTP24_Pos)                  /*!< GPIO_PORT MPIN6: MPORTP24 Mask      */
#define GPIO_PORT_MPIN6_MPORTP25_Pos                          25                                                        /*!< GPIO_PORT MPIN6: MPORTP25 Position  */
#define GPIO_PORT_MPIN6_MPORTP25_Msk                          (0x01UL << GPIO_PORT_MPIN6_MPORTP25_Pos)                  /*!< GPIO_PORT MPIN6: MPORTP25 Mask      */
#define GPIO_PORT_MPIN6_MPORTP26_Pos                          26                                                        /*!< GPIO_PORT MPIN6: MPORTP26 Position  */
#define GPIO_PORT_MPIN6_MPORTP26_Msk                          (0x01UL << GPIO_PORT_MPIN6_MPORTP26_Pos)                  /*!< GPIO_PORT MPIN6: MPORTP26 Mask      */
#define GPIO_PORT_MPIN6_MPORTP27_Pos                          27                                                        /*!< GPIO_PORT MPIN6: MPORTP27 Position  */
#define GPIO_PORT_MPIN6_MPORTP27_Msk                          (0x01UL << GPIO_PORT_MPIN6_MPORTP27_Pos)                  /*!< GPIO_PORT MPIN6: MPORTP27 Mask      */
#define GPIO_PORT_MPIN6_MPORTP28_Pos                          28                                                        /*!< GPIO_PORT MPIN6: MPORTP28 Position  */
#define GPIO_PORT_MPIN6_MPORTP28_Msk                          (0x01UL << GPIO_PORT_MPIN6_MPORTP28_Pos)                  /*!< GPIO_PORT MPIN6: MPORTP28 Mask      */
#define GPIO_PORT_MPIN6_MPORTP29_Pos                          29                                                        /*!< GPIO_PORT MPIN6: MPORTP29 Position  */
#define GPIO_PORT_MPIN6_MPORTP29_Msk                          (0x01UL << GPIO_PORT_MPIN6_MPORTP29_Pos)                  /*!< GPIO_PORT MPIN6: MPORTP29 Mask      */
#define GPIO_PORT_MPIN6_MPORTP30_Pos                          30                                                        /*!< GPIO_PORT MPIN6: MPORTP30 Position  */
#define GPIO_PORT_MPIN6_MPORTP30_Msk                          (0x01UL << GPIO_PORT_MPIN6_MPORTP30_Pos)                  /*!< GPIO_PORT MPIN6: MPORTP30 Mask      */
#define GPIO_PORT_MPIN6_MPORTP31_Pos                          31                                                        /*!< GPIO_PORT MPIN6: MPORTP31 Position  */
#define GPIO_PORT_MPIN6_MPORTP31_Msk                          (0x01UL << GPIO_PORT_MPIN6_MPORTP31_Pos)                  /*!< GPIO_PORT MPIN6: MPORTP31 Mask      */

// -------------------------------------  GPIO_PORT_MPIN7  ----------------------------------------
#define GPIO_PORT_MPIN7_MPORTP0_Pos                           0                                                         /*!< GPIO_PORT MPIN7: MPORTP0 Position   */
#define GPIO_PORT_MPIN7_MPORTP0_Msk                           (0x01UL << GPIO_PORT_MPIN7_MPORTP0_Pos)                   /*!< GPIO_PORT MPIN7: MPORTP0 Mask       */
#define GPIO_PORT_MPIN7_MPORTP1_Pos                           1                                                         /*!< GPIO_PORT MPIN7: MPORTP1 Position   */
#define GPIO_PORT_MPIN7_MPORTP1_Msk                           (0x01UL << GPIO_PORT_MPIN7_MPORTP1_Pos)                   /*!< GPIO_PORT MPIN7: MPORTP1 Mask       */
#define GPIO_PORT_MPIN7_MPORTP2_Pos                           2                                                         /*!< GPIO_PORT MPIN7: MPORTP2 Position   */
#define GPIO_PORT_MPIN7_MPORTP2_Msk                           (0x01UL << GPIO_PORT_MPIN7_MPORTP2_Pos)                   /*!< GPIO_PORT MPIN7: MPORTP2 Mask       */
#define GPIO_PORT_MPIN7_MPORTP3_Pos                           3                                                         /*!< GPIO_PORT MPIN7: MPORTP3 Position   */
#define GPIO_PORT_MPIN7_MPORTP3_Msk                           (0x01UL << GPIO_PORT_MPIN7_MPORTP3_Pos)                   /*!< GPIO_PORT MPIN7: MPORTP3 Mask       */
#define GPIO_PORT_MPIN7_MPORTP4_Pos                           4                                                         /*!< GPIO_PORT MPIN7: MPORTP4 Position   */
#define GPIO_PORT_MPIN7_MPORTP4_Msk                           (0x01UL << GPIO_PORT_MPIN7_MPORTP4_Pos)                   /*!< GPIO_PORT MPIN7: MPORTP4 Mask       */
#define GPIO_PORT_MPIN7_MPORTP5_Pos                           5                                                         /*!< GPIO_PORT MPIN7: MPORTP5 Position   */
#define GPIO_PORT_MPIN7_MPORTP5_Msk                           (0x01UL << GPIO_PORT_MPIN7_MPORTP5_Pos)                   /*!< GPIO_PORT MPIN7: MPORTP5 Mask       */
#define GPIO_PORT_MPIN7_MPORTP6_Pos                           6                                                         /*!< GPIO_PORT MPIN7: MPORTP6 Position   */
#define GPIO_PORT_MPIN7_MPORTP6_Msk                           (0x01UL << GPIO_PORT_MPIN7_MPORTP6_Pos)                   /*!< GPIO_PORT MPIN7: MPORTP6 Mask       */
#define GPIO_PORT_MPIN7_MPORTP7_Pos                           7                                                         /*!< GPIO_PORT MPIN7: MPORTP7 Position   */
#define GPIO_PORT_MPIN7_MPORTP7_Msk                           (0x01UL << GPIO_PORT_MPIN7_MPORTP7_Pos)                   /*!< GPIO_PORT MPIN7: MPORTP7 Mask       */
#define GPIO_PORT_MPIN7_MPORTP8_Pos                           8                                                         /*!< GPIO_PORT MPIN7: MPORTP8 Position   */
#define GPIO_PORT_MPIN7_MPORTP8_Msk                           (0x01UL << GPIO_PORT_MPIN7_MPORTP8_Pos)                   /*!< GPIO_PORT MPIN7: MPORTP8 Mask       */
#define GPIO_PORT_MPIN7_MPORTP9_Pos                           9                                                         /*!< GPIO_PORT MPIN7: MPORTP9 Position   */
#define GPIO_PORT_MPIN7_MPORTP9_Msk                           (0x01UL << GPIO_PORT_MPIN7_MPORTP9_Pos)                   /*!< GPIO_PORT MPIN7: MPORTP9 Mask       */
#define GPIO_PORT_MPIN7_MPORTP10_Pos                          10                                                        /*!< GPIO_PORT MPIN7: MPORTP10 Position  */
#define GPIO_PORT_MPIN7_MPORTP10_Msk                          (0x01UL << GPIO_PORT_MPIN7_MPORTP10_Pos)                  /*!< GPIO_PORT MPIN7: MPORTP10 Mask      */
#define GPIO_PORT_MPIN7_MPORTP11_Pos                          11                                                        /*!< GPIO_PORT MPIN7: MPORTP11 Position  */
#define GPIO_PORT_MPIN7_MPORTP11_Msk                          (0x01UL << GPIO_PORT_MPIN7_MPORTP11_Pos)                  /*!< GPIO_PORT MPIN7: MPORTP11 Mask      */
#define GPIO_PORT_MPIN7_MPORTP12_Pos                          12                                                        /*!< GPIO_PORT MPIN7: MPORTP12 Position  */
#define GPIO_PORT_MPIN7_MPORTP12_Msk                          (0x01UL << GPIO_PORT_MPIN7_MPORTP12_Pos)                  /*!< GPIO_PORT MPIN7: MPORTP12 Mask      */
#define GPIO_PORT_MPIN7_MPORTP13_Pos                          13                                                        /*!< GPIO_PORT MPIN7: MPORTP13 Position  */
#define GPIO_PORT_MPIN7_MPORTP13_Msk                          (0x01UL << GPIO_PORT_MPIN7_MPORTP13_Pos)                  /*!< GPIO_PORT MPIN7: MPORTP13 Mask      */
#define GPIO_PORT_MPIN7_MPORTP14_Pos                          14                                                        /*!< GPIO_PORT MPIN7: MPORTP14 Position  */
#define GPIO_PORT_MPIN7_MPORTP14_Msk                          (0x01UL << GPIO_PORT_MPIN7_MPORTP14_Pos)                  /*!< GPIO_PORT MPIN7: MPORTP14 Mask      */
#define GPIO_PORT_MPIN7_MPORTP15_Pos                          15                                                        /*!< GPIO_PORT MPIN7: MPORTP15 Position  */
#define GPIO_PORT_MPIN7_MPORTP15_Msk                          (0x01UL << GPIO_PORT_MPIN7_MPORTP15_Pos)                  /*!< GPIO_PORT MPIN7: MPORTP15 Mask      */
#define GPIO_PORT_MPIN7_MPORTP16_Pos                          16                                                        /*!< GPIO_PORT MPIN7: MPORTP16 Position  */
#define GPIO_PORT_MPIN7_MPORTP16_Msk                          (0x01UL << GPIO_PORT_MPIN7_MPORTP16_Pos)                  /*!< GPIO_PORT MPIN7: MPORTP16 Mask      */
#define GPIO_PORT_MPIN7_MPORTP17_Pos                          17                                                        /*!< GPIO_PORT MPIN7: MPORTP17 Position  */
#define GPIO_PORT_MPIN7_MPORTP17_Msk                          (0x01UL << GPIO_PORT_MPIN7_MPORTP17_Pos)                  /*!< GPIO_PORT MPIN7: MPORTP17 Mask      */
#define GPIO_PORT_MPIN7_MPORTP18_Pos                          18                                                        /*!< GPIO_PORT MPIN7: MPORTP18 Position  */
#define GPIO_PORT_MPIN7_MPORTP18_Msk                          (0x01UL << GPIO_PORT_MPIN7_MPORTP18_Pos)                  /*!< GPIO_PORT MPIN7: MPORTP18 Mask      */
#define GPIO_PORT_MPIN7_MPORTP19_Pos                          19                                                        /*!< GPIO_PORT MPIN7: MPORTP19 Position  */
#define GPIO_PORT_MPIN7_MPORTP19_Msk                          (0x01UL << GPIO_PORT_MPIN7_MPORTP19_Pos)                  /*!< GPIO_PORT MPIN7: MPORTP19 Mask      */
#define GPIO_PORT_MPIN7_MPORTP20_Pos                          20                                                        /*!< GPIO_PORT MPIN7: MPORTP20 Position  */
#define GPIO_PORT_MPIN7_MPORTP20_Msk                          (0x01UL << GPIO_PORT_MPIN7_MPORTP20_Pos)                  /*!< GPIO_PORT MPIN7: MPORTP20 Mask      */
#define GPIO_PORT_MPIN7_MPORTP21_Pos                          21                                                        /*!< GPIO_PORT MPIN7: MPORTP21 Position  */
#define GPIO_PORT_MPIN7_MPORTP21_Msk                          (0x01UL << GPIO_PORT_MPIN7_MPORTP21_Pos)                  /*!< GPIO_PORT MPIN7: MPORTP21 Mask      */
#define GPIO_PORT_MPIN7_MPORTP22_Pos                          22                                                        /*!< GPIO_PORT MPIN7: MPORTP22 Position  */
#define GPIO_PORT_MPIN7_MPORTP22_Msk                          (0x01UL << GPIO_PORT_MPIN7_MPORTP22_Pos)                  /*!< GPIO_PORT MPIN7: MPORTP22 Mask      */
#define GPIO_PORT_MPIN7_MPORTP23_Pos                          23                                                        /*!< GPIO_PORT MPIN7: MPORTP23 Position  */
#define GPIO_PORT_MPIN7_MPORTP23_Msk                          (0x01UL << GPIO_PORT_MPIN7_MPORTP23_Pos)                  /*!< GPIO_PORT MPIN7: MPORTP23 Mask      */
#define GPIO_PORT_MPIN7_MPORTP24_Pos                          24                                                        /*!< GPIO_PORT MPIN7: MPORTP24 Position  */
#define GPIO_PORT_MPIN7_MPORTP24_Msk                          (0x01UL << GPIO_PORT_MPIN7_MPORTP24_Pos)                  /*!< GPIO_PORT MPIN7: MPORTP24 Mask      */
#define GPIO_PORT_MPIN7_MPORTP25_Pos                          25                                                        /*!< GPIO_PORT MPIN7: MPORTP25 Position  */
#define GPIO_PORT_MPIN7_MPORTP25_Msk                          (0x01UL << GPIO_PORT_MPIN7_MPORTP25_Pos)                  /*!< GPIO_PORT MPIN7: MPORTP25 Mask      */
#define GPIO_PORT_MPIN7_MPORTP26_Pos                          26                                                        /*!< GPIO_PORT MPIN7: MPORTP26 Position  */
#define GPIO_PORT_MPIN7_MPORTP26_Msk                          (0x01UL << GPIO_PORT_MPIN7_MPORTP26_Pos)                  /*!< GPIO_PORT MPIN7: MPORTP26 Mask      */
#define GPIO_PORT_MPIN7_MPORTP27_Pos                          27                                                        /*!< GPIO_PORT MPIN7: MPORTP27 Position  */
#define GPIO_PORT_MPIN7_MPORTP27_Msk                          (0x01UL << GPIO_PORT_MPIN7_MPORTP27_Pos)                  /*!< GPIO_PORT MPIN7: MPORTP27 Mask      */
#define GPIO_PORT_MPIN7_MPORTP28_Pos                          28                                                        /*!< GPIO_PORT MPIN7: MPORTP28 Position  */
#define GPIO_PORT_MPIN7_MPORTP28_Msk                          (0x01UL << GPIO_PORT_MPIN7_MPORTP28_Pos)                  /*!< GPIO_PORT MPIN7: MPORTP28 Mask      */
#define GPIO_PORT_MPIN7_MPORTP29_Pos                          29                                                        /*!< GPIO_PORT MPIN7: MPORTP29 Position  */
#define GPIO_PORT_MPIN7_MPORTP29_Msk                          (0x01UL << GPIO_PORT_MPIN7_MPORTP29_Pos)                  /*!< GPIO_PORT MPIN7: MPORTP29 Mask      */
#define GPIO_PORT_MPIN7_MPORTP30_Pos                          30                                                        /*!< GPIO_PORT MPIN7: MPORTP30 Position  */
#define GPIO_PORT_MPIN7_MPORTP30_Msk                          (0x01UL << GPIO_PORT_MPIN7_MPORTP30_Pos)                  /*!< GPIO_PORT MPIN7: MPORTP30 Mask      */
#define GPIO_PORT_MPIN7_MPORTP31_Pos                          31                                                        /*!< GPIO_PORT MPIN7: MPORTP31 Position  */
#define GPIO_PORT_MPIN7_MPORTP31_Msk                          (0x01UL << GPIO_PORT_MPIN7_MPORTP31_Pos)                  /*!< GPIO_PORT MPIN7: MPORTP31 Mask      */

// -------------------------------------  GPIO_PORT_SET0  -----------------------------------------
#define GPIO_PORT_SET0_SETP0_Pos                              0                                                         /*!< GPIO_PORT SET0: SETP0 Position      */
#define GPIO_PORT_SET0_SETP0_Msk                              (0x01UL << GPIO_PORT_SET0_SETP0_Pos)                      /*!< GPIO_PORT SET0: SETP0 Mask          */
#define GPIO_PORT_SET0_SETP1_Pos                              1                                                         /*!< GPIO_PORT SET0: SETP1 Position      */
#define GPIO_PORT_SET0_SETP1_Msk                              (0x01UL << GPIO_PORT_SET0_SETP1_Pos)                      /*!< GPIO_PORT SET0: SETP1 Mask          */
#define GPIO_PORT_SET0_SETP2_Pos                              2                                                         /*!< GPIO_PORT SET0: SETP2 Position      */
#define GPIO_PORT_SET0_SETP2_Msk                              (0x01UL << GPIO_PORT_SET0_SETP2_Pos)                      /*!< GPIO_PORT SET0: SETP2 Mask          */
#define GPIO_PORT_SET0_SETP3_Pos                              3                                                         /*!< GPIO_PORT SET0: SETP3 Position      */
#define GPIO_PORT_SET0_SETP3_Msk                              (0x01UL << GPIO_PORT_SET0_SETP3_Pos)                      /*!< GPIO_PORT SET0: SETP3 Mask          */
#define GPIO_PORT_SET0_SETP4_Pos                              4                                                         /*!< GPIO_PORT SET0: SETP4 Position      */
#define GPIO_PORT_SET0_SETP4_Msk                              (0x01UL << GPIO_PORT_SET0_SETP4_Pos)                      /*!< GPIO_PORT SET0: SETP4 Mask          */
#define GPIO_PORT_SET0_SETP5_Pos                              5                                                         /*!< GPIO_PORT SET0: SETP5 Position      */
#define GPIO_PORT_SET0_SETP5_Msk                              (0x01UL << GPIO_PORT_SET0_SETP5_Pos)                      /*!< GPIO_PORT SET0: SETP5 Mask          */
#define GPIO_PORT_SET0_SETP6_Pos                              6                                                         /*!< GPIO_PORT SET0: SETP6 Position      */
#define GPIO_PORT_SET0_SETP6_Msk                              (0x01UL << GPIO_PORT_SET0_SETP6_Pos)                      /*!< GPIO_PORT SET0: SETP6 Mask          */
#define GPIO_PORT_SET0_SETP7_Pos                              7                                                         /*!< GPIO_PORT SET0: SETP7 Position      */
#define GPIO_PORT_SET0_SETP7_Msk                              (0x01UL << GPIO_PORT_SET0_SETP7_Pos)                      /*!< GPIO_PORT SET0: SETP7 Mask          */
#define GPIO_PORT_SET0_SETP8_Pos                              8                                                         /*!< GPIO_PORT SET0: SETP8 Position      */
#define GPIO_PORT_SET0_SETP8_Msk                              (0x01UL << GPIO_PORT_SET0_SETP8_Pos)                      /*!< GPIO_PORT SET0: SETP8 Mask          */
#define GPIO_PORT_SET0_SETP9_Pos                              9                                                         /*!< GPIO_PORT SET0: SETP9 Position      */
#define GPIO_PORT_SET0_SETP9_Msk                              (0x01UL << GPIO_PORT_SET0_SETP9_Pos)                      /*!< GPIO_PORT SET0: SETP9 Mask          */
#define GPIO_PORT_SET0_SETP10_Pos                             10                                                        /*!< GPIO_PORT SET0: SETP10 Position     */
#define GPIO_PORT_SET0_SETP10_Msk                             (0x01UL << GPIO_PORT_SET0_SETP10_Pos)                     /*!< GPIO_PORT SET0: SETP10 Mask         */
#define GPIO_PORT_SET0_SETP11_Pos                             11                                                        /*!< GPIO_PORT SET0: SETP11 Position     */
#define GPIO_PORT_SET0_SETP11_Msk                             (0x01UL << GPIO_PORT_SET0_SETP11_Pos)                     /*!< GPIO_PORT SET0: SETP11 Mask         */
#define GPIO_PORT_SET0_SETP12_Pos                             12                                                        /*!< GPIO_PORT SET0: SETP12 Position     */
#define GPIO_PORT_SET0_SETP12_Msk                             (0x01UL << GPIO_PORT_SET0_SETP12_Pos)                     /*!< GPIO_PORT SET0: SETP12 Mask         */
#define GPIO_PORT_SET0_SETP13_Pos                             13                                                        /*!< GPIO_PORT SET0: SETP13 Position     */
#define GPIO_PORT_SET0_SETP13_Msk                             (0x01UL << GPIO_PORT_SET0_SETP13_Pos)                     /*!< GPIO_PORT SET0: SETP13 Mask         */
#define GPIO_PORT_SET0_SETP14_Pos                             14                                                        /*!< GPIO_PORT SET0: SETP14 Position     */
#define GPIO_PORT_SET0_SETP14_Msk                             (0x01UL << GPIO_PORT_SET0_SETP14_Pos)                     /*!< GPIO_PORT SET0: SETP14 Mask         */
#define GPIO_PORT_SET0_SETP15_Pos                             15                                                        /*!< GPIO_PORT SET0: SETP15 Position     */
#define GPIO_PORT_SET0_SETP15_Msk                             (0x01UL << GPIO_PORT_SET0_SETP15_Pos)                     /*!< GPIO_PORT SET0: SETP15 Mask         */
#define GPIO_PORT_SET0_SETP16_Pos                             16                                                        /*!< GPIO_PORT SET0: SETP16 Position     */
#define GPIO_PORT_SET0_SETP16_Msk                             (0x01UL << GPIO_PORT_SET0_SETP16_Pos)                     /*!< GPIO_PORT SET0: SETP16 Mask         */
#define GPIO_PORT_SET0_SETP17_Pos                             17                                                        /*!< GPIO_PORT SET0: SETP17 Position     */
#define GPIO_PORT_SET0_SETP17_Msk                             (0x01UL << GPIO_PORT_SET0_SETP17_Pos)                     /*!< GPIO_PORT SET0: SETP17 Mask         */
#define GPIO_PORT_SET0_SETP18_Pos                             18                                                        /*!< GPIO_PORT SET0: SETP18 Position     */
#define GPIO_PORT_SET0_SETP18_Msk                             (0x01UL << GPIO_PORT_SET0_SETP18_Pos)                     /*!< GPIO_PORT SET0: SETP18 Mask         */
#define GPIO_PORT_SET0_SETP19_Pos                             19                                                        /*!< GPIO_PORT SET0: SETP19 Position     */
#define GPIO_PORT_SET0_SETP19_Msk                             (0x01UL << GPIO_PORT_SET0_SETP19_Pos)                     /*!< GPIO_PORT SET0: SETP19 Mask         */
#define GPIO_PORT_SET0_SETP20_Pos                             20                                                        /*!< GPIO_PORT SET0: SETP20 Position     */
#define GPIO_PORT_SET0_SETP20_Msk                             (0x01UL << GPIO_PORT_SET0_SETP20_Pos)                     /*!< GPIO_PORT SET0: SETP20 Mask         */
#define GPIO_PORT_SET0_SETP21_Pos                             21                                                        /*!< GPIO_PORT SET0: SETP21 Position     */
#define GPIO_PORT_SET0_SETP21_Msk                             (0x01UL << GPIO_PORT_SET0_SETP21_Pos)                     /*!< GPIO_PORT SET0: SETP21 Mask         */
#define GPIO_PORT_SET0_SETP22_Pos                             22                                                        /*!< GPIO_PORT SET0: SETP22 Position     */
#define GPIO_PORT_SET0_SETP22_Msk                             (0x01UL << GPIO_PORT_SET0_SETP22_Pos)                     /*!< GPIO_PORT SET0: SETP22 Mask         */
#define GPIO_PORT_SET0_SETP23_Pos                             23                                                        /*!< GPIO_PORT SET0: SETP23 Position     */
#define GPIO_PORT_SET0_SETP23_Msk                             (0x01UL << GPIO_PORT_SET0_SETP23_Pos)                     /*!< GPIO_PORT SET0: SETP23 Mask         */
#define GPIO_PORT_SET0_SETP24_Pos                             24                                                        /*!< GPIO_PORT SET0: SETP24 Position     */
#define GPIO_PORT_SET0_SETP24_Msk                             (0x01UL << GPIO_PORT_SET0_SETP24_Pos)                     /*!< GPIO_PORT SET0: SETP24 Mask         */
#define GPIO_PORT_SET0_SETP25_Pos                             25                                                        /*!< GPIO_PORT SET0: SETP25 Position     */
#define GPIO_PORT_SET0_SETP25_Msk                             (0x01UL << GPIO_PORT_SET0_SETP25_Pos)                     /*!< GPIO_PORT SET0: SETP25 Mask         */
#define GPIO_PORT_SET0_SETP26_Pos                             26                                                        /*!< GPIO_PORT SET0: SETP26 Position     */
#define GPIO_PORT_SET0_SETP26_Msk                             (0x01UL << GPIO_PORT_SET0_SETP26_Pos)                     /*!< GPIO_PORT SET0: SETP26 Mask         */
#define GPIO_PORT_SET0_SETP27_Pos                             27                                                        /*!< GPIO_PORT SET0: SETP27 Position     */
#define GPIO_PORT_SET0_SETP27_Msk                             (0x01UL << GPIO_PORT_SET0_SETP27_Pos)                     /*!< GPIO_PORT SET0: SETP27 Mask         */
#define GPIO_PORT_SET0_SETP28_Pos                             28                                                        /*!< GPIO_PORT SET0: SETP28 Position     */
#define GPIO_PORT_SET0_SETP28_Msk                             (0x01UL << GPIO_PORT_SET0_SETP28_Pos)                     /*!< GPIO_PORT SET0: SETP28 Mask         */
#define GPIO_PORT_SET0_SETP29_Pos                             29                                                        /*!< GPIO_PORT SET0: SETP29 Position     */
#define GPIO_PORT_SET0_SETP29_Msk                             (0x01UL << GPIO_PORT_SET0_SETP29_Pos)                     /*!< GPIO_PORT SET0: SETP29 Mask         */
#define GPIO_PORT_SET0_SETP30_Pos                             30                                                        /*!< GPIO_PORT SET0: SETP30 Position     */
#define GPIO_PORT_SET0_SETP30_Msk                             (0x01UL << GPIO_PORT_SET0_SETP30_Pos)                     /*!< GPIO_PORT SET0: SETP30 Mask         */
#define GPIO_PORT_SET0_SETP31_Pos                             31                                                        /*!< GPIO_PORT SET0: SETP31 Position     */
#define GPIO_PORT_SET0_SETP31_Msk                             (0x01UL << GPIO_PORT_SET0_SETP31_Pos)                     /*!< GPIO_PORT SET0: SETP31 Mask         */

// -------------------------------------  GPIO_PORT_SET1  -----------------------------------------
#define GPIO_PORT_SET1_SETP0_Pos                              0                                                         /*!< GPIO_PORT SET1: SETP0 Position      */
#define GPIO_PORT_SET1_SETP0_Msk                              (0x01UL << GPIO_PORT_SET1_SETP0_Pos)                      /*!< GPIO_PORT SET1: SETP0 Mask          */
#define GPIO_PORT_SET1_SETP1_Pos                              1                                                         /*!< GPIO_PORT SET1: SETP1 Position      */
#define GPIO_PORT_SET1_SETP1_Msk                              (0x01UL << GPIO_PORT_SET1_SETP1_Pos)                      /*!< GPIO_PORT SET1: SETP1 Mask          */
#define GPIO_PORT_SET1_SETP2_Pos                              2                                                         /*!< GPIO_PORT SET1: SETP2 Position      */
#define GPIO_PORT_SET1_SETP2_Msk                              (0x01UL << GPIO_PORT_SET1_SETP2_Pos)                      /*!< GPIO_PORT SET1: SETP2 Mask          */
#define GPIO_PORT_SET1_SETP3_Pos                              3                                                         /*!< GPIO_PORT SET1: SETP3 Position      */
#define GPIO_PORT_SET1_SETP3_Msk                              (0x01UL << GPIO_PORT_SET1_SETP3_Pos)                      /*!< GPIO_PORT SET1: SETP3 Mask          */
#define GPIO_PORT_SET1_SETP4_Pos                              4                                                         /*!< GPIO_PORT SET1: SETP4 Position      */
#define GPIO_PORT_SET1_SETP4_Msk                              (0x01UL << GPIO_PORT_SET1_SETP4_Pos)                      /*!< GPIO_PORT SET1: SETP4 Mask          */
#define GPIO_PORT_SET1_SETP5_Pos                              5                                                         /*!< GPIO_PORT SET1: SETP5 Position      */
#define GPIO_PORT_SET1_SETP5_Msk                              (0x01UL << GPIO_PORT_SET1_SETP5_Pos)                      /*!< GPIO_PORT SET1: SETP5 Mask          */
#define GPIO_PORT_SET1_SETP6_Pos                              6                                                         /*!< GPIO_PORT SET1: SETP6 Position      */
#define GPIO_PORT_SET1_SETP6_Msk                              (0x01UL << GPIO_PORT_SET1_SETP6_Pos)                      /*!< GPIO_PORT SET1: SETP6 Mask          */
#define GPIO_PORT_SET1_SETP7_Pos                              7                                                         /*!< GPIO_PORT SET1: SETP7 Position      */
#define GPIO_PORT_SET1_SETP7_Msk                              (0x01UL << GPIO_PORT_SET1_SETP7_Pos)                      /*!< GPIO_PORT SET1: SETP7 Mask          */
#define GPIO_PORT_SET1_SETP8_Pos                              8                                                         /*!< GPIO_PORT SET1: SETP8 Position      */
#define GPIO_PORT_SET1_SETP8_Msk                              (0x01UL << GPIO_PORT_SET1_SETP8_Pos)                      /*!< GPIO_PORT SET1: SETP8 Mask          */
#define GPIO_PORT_SET1_SETP9_Pos                              9                                                         /*!< GPIO_PORT SET1: SETP9 Position      */
#define GPIO_PORT_SET1_SETP9_Msk                              (0x01UL << GPIO_PORT_SET1_SETP9_Pos)                      /*!< GPIO_PORT SET1: SETP9 Mask          */
#define GPIO_PORT_SET1_SETP10_Pos                             10                                                        /*!< GPIO_PORT SET1: SETP10 Position     */
#define GPIO_PORT_SET1_SETP10_Msk                             (0x01UL << GPIO_PORT_SET1_SETP10_Pos)                     /*!< GPIO_PORT SET1: SETP10 Mask         */
#define GPIO_PORT_SET1_SETP11_Pos                             11                                                        /*!< GPIO_PORT SET1: SETP11 Position     */
#define GPIO_PORT_SET1_SETP11_Msk                             (0x01UL << GPIO_PORT_SET1_SETP11_Pos)                     /*!< GPIO_PORT SET1: SETP11 Mask         */
#define GPIO_PORT_SET1_SETP12_Pos                             12                                                        /*!< GPIO_PORT SET1: SETP12 Position     */
#define GPIO_PORT_SET1_SETP12_Msk                             (0x01UL << GPIO_PORT_SET1_SETP12_Pos)                     /*!< GPIO_PORT SET1: SETP12 Mask         */
#define GPIO_PORT_SET1_SETP13_Pos                             13                                                        /*!< GPIO_PORT SET1: SETP13 Position     */
#define GPIO_PORT_SET1_SETP13_Msk                             (0x01UL << GPIO_PORT_SET1_SETP13_Pos)                     /*!< GPIO_PORT SET1: SETP13 Mask         */
#define GPIO_PORT_SET1_SETP14_Pos                             14                                                        /*!< GPIO_PORT SET1: SETP14 Position     */
#define GPIO_PORT_SET1_SETP14_Msk                             (0x01UL << GPIO_PORT_SET1_SETP14_Pos)                     /*!< GPIO_PORT SET1: SETP14 Mask         */
#define GPIO_PORT_SET1_SETP15_Pos                             15                                                        /*!< GPIO_PORT SET1: SETP15 Position     */
#define GPIO_PORT_SET1_SETP15_Msk                             (0x01UL << GPIO_PORT_SET1_SETP15_Pos)                     /*!< GPIO_PORT SET1: SETP15 Mask         */
#define GPIO_PORT_SET1_SETP16_Pos                             16                                                        /*!< GPIO_PORT SET1: SETP16 Position     */
#define GPIO_PORT_SET1_SETP16_Msk                             (0x01UL << GPIO_PORT_SET1_SETP16_Pos)                     /*!< GPIO_PORT SET1: SETP16 Mask         */
#define GPIO_PORT_SET1_SETP17_Pos                             17                                                        /*!< GPIO_PORT SET1: SETP17 Position     */
#define GPIO_PORT_SET1_SETP17_Msk                             (0x01UL << GPIO_PORT_SET1_SETP17_Pos)                     /*!< GPIO_PORT SET1: SETP17 Mask         */
#define GPIO_PORT_SET1_SETP18_Pos                             18                                                        /*!< GPIO_PORT SET1: SETP18 Position     */
#define GPIO_PORT_SET1_SETP18_Msk                             (0x01UL << GPIO_PORT_SET1_SETP18_Pos)                     /*!< GPIO_PORT SET1: SETP18 Mask         */
#define GPIO_PORT_SET1_SETP19_Pos                             19                                                        /*!< GPIO_PORT SET1: SETP19 Position     */
#define GPIO_PORT_SET1_SETP19_Msk                             (0x01UL << GPIO_PORT_SET1_SETP19_Pos)                     /*!< GPIO_PORT SET1: SETP19 Mask         */
#define GPIO_PORT_SET1_SETP20_Pos                             20                                                        /*!< GPIO_PORT SET1: SETP20 Position     */
#define GPIO_PORT_SET1_SETP20_Msk                             (0x01UL << GPIO_PORT_SET1_SETP20_Pos)                     /*!< GPIO_PORT SET1: SETP20 Mask         */
#define GPIO_PORT_SET1_SETP21_Pos                             21                                                        /*!< GPIO_PORT SET1: SETP21 Position     */
#define GPIO_PORT_SET1_SETP21_Msk                             (0x01UL << GPIO_PORT_SET1_SETP21_Pos)                     /*!< GPIO_PORT SET1: SETP21 Mask         */
#define GPIO_PORT_SET1_SETP22_Pos                             22                                                        /*!< GPIO_PORT SET1: SETP22 Position     */
#define GPIO_PORT_SET1_SETP22_Msk                             (0x01UL << GPIO_PORT_SET1_SETP22_Pos)                     /*!< GPIO_PORT SET1: SETP22 Mask         */
#define GPIO_PORT_SET1_SETP23_Pos                             23                                                        /*!< GPIO_PORT SET1: SETP23 Position     */
#define GPIO_PORT_SET1_SETP23_Msk                             (0x01UL << GPIO_PORT_SET1_SETP23_Pos)                     /*!< GPIO_PORT SET1: SETP23 Mask         */
#define GPIO_PORT_SET1_SETP24_Pos                             24                                                        /*!< GPIO_PORT SET1: SETP24 Position     */
#define GPIO_PORT_SET1_SETP24_Msk                             (0x01UL << GPIO_PORT_SET1_SETP24_Pos)                     /*!< GPIO_PORT SET1: SETP24 Mask         */
#define GPIO_PORT_SET1_SETP25_Pos                             25                                                        /*!< GPIO_PORT SET1: SETP25 Position     */
#define GPIO_PORT_SET1_SETP25_Msk                             (0x01UL << GPIO_PORT_SET1_SETP25_Pos)                     /*!< GPIO_PORT SET1: SETP25 Mask         */
#define GPIO_PORT_SET1_SETP26_Pos                             26                                                        /*!< GPIO_PORT SET1: SETP26 Position     */
#define GPIO_PORT_SET1_SETP26_Msk                             (0x01UL << GPIO_PORT_SET1_SETP26_Pos)                     /*!< GPIO_PORT SET1: SETP26 Mask         */
#define GPIO_PORT_SET1_SETP27_Pos                             27                                                        /*!< GPIO_PORT SET1: SETP27 Position     */
#define GPIO_PORT_SET1_SETP27_Msk                             (0x01UL << GPIO_PORT_SET1_SETP27_Pos)                     /*!< GPIO_PORT SET1: SETP27 Mask         */
#define GPIO_PORT_SET1_SETP28_Pos                             28                                                        /*!< GPIO_PORT SET1: SETP28 Position     */
#define GPIO_PORT_SET1_SETP28_Msk                             (0x01UL << GPIO_PORT_SET1_SETP28_Pos)                     /*!< GPIO_PORT SET1: SETP28 Mask         */
#define GPIO_PORT_SET1_SETP29_Pos                             29                                                        /*!< GPIO_PORT SET1: SETP29 Position     */
#define GPIO_PORT_SET1_SETP29_Msk                             (0x01UL << GPIO_PORT_SET1_SETP29_Pos)                     /*!< GPIO_PORT SET1: SETP29 Mask         */
#define GPIO_PORT_SET1_SETP30_Pos                             30                                                        /*!< GPIO_PORT SET1: SETP30 Position     */
#define GPIO_PORT_SET1_SETP30_Msk                             (0x01UL << GPIO_PORT_SET1_SETP30_Pos)                     /*!< GPIO_PORT SET1: SETP30 Mask         */
#define GPIO_PORT_SET1_SETP31_Pos                             31                                                        /*!< GPIO_PORT SET1: SETP31 Position     */
#define GPIO_PORT_SET1_SETP31_Msk                             (0x01UL << GPIO_PORT_SET1_SETP31_Pos)                     /*!< GPIO_PORT SET1: SETP31 Mask         */

// -------------------------------------  GPIO_PORT_SET2  -----------------------------------------
#define GPIO_PORT_SET2_SETP0_Pos                              0                                                         /*!< GPIO_PORT SET2: SETP0 Position      */
#define GPIO_PORT_SET2_SETP0_Msk                              (0x01UL << GPIO_PORT_SET2_SETP0_Pos)                      /*!< GPIO_PORT SET2: SETP0 Mask          */
#define GPIO_PORT_SET2_SETP1_Pos                              1                                                         /*!< GPIO_PORT SET2: SETP1 Position      */
#define GPIO_PORT_SET2_SETP1_Msk                              (0x01UL << GPIO_PORT_SET2_SETP1_Pos)                      /*!< GPIO_PORT SET2: SETP1 Mask          */
#define GPIO_PORT_SET2_SETP2_Pos                              2                                                         /*!< GPIO_PORT SET2: SETP2 Position      */
#define GPIO_PORT_SET2_SETP2_Msk                              (0x01UL << GPIO_PORT_SET2_SETP2_Pos)                      /*!< GPIO_PORT SET2: SETP2 Mask          */
#define GPIO_PORT_SET2_SETP3_Pos                              3                                                         /*!< GPIO_PORT SET2: SETP3 Position      */
#define GPIO_PORT_SET2_SETP3_Msk                              (0x01UL << GPIO_PORT_SET2_SETP3_Pos)                      /*!< GPIO_PORT SET2: SETP3 Mask          */
#define GPIO_PORT_SET2_SETP4_Pos                              4                                                         /*!< GPIO_PORT SET2: SETP4 Position      */
#define GPIO_PORT_SET2_SETP4_Msk                              (0x01UL << GPIO_PORT_SET2_SETP4_Pos)                      /*!< GPIO_PORT SET2: SETP4 Mask          */
#define GPIO_PORT_SET2_SETP5_Pos                              5                                                         /*!< GPIO_PORT SET2: SETP5 Position      */
#define GPIO_PORT_SET2_SETP5_Msk                              (0x01UL << GPIO_PORT_SET2_SETP5_Pos)                      /*!< GPIO_PORT SET2: SETP5 Mask          */
#define GPIO_PORT_SET2_SETP6_Pos                              6                                                         /*!< GPIO_PORT SET2: SETP6 Position      */
#define GPIO_PORT_SET2_SETP6_Msk                              (0x01UL << GPIO_PORT_SET2_SETP6_Pos)                      /*!< GPIO_PORT SET2: SETP6 Mask          */
#define GPIO_PORT_SET2_SETP7_Pos                              7                                                         /*!< GPIO_PORT SET2: SETP7 Position      */
#define GPIO_PORT_SET2_SETP7_Msk                              (0x01UL << GPIO_PORT_SET2_SETP7_Pos)                      /*!< GPIO_PORT SET2: SETP7 Mask          */
#define GPIO_PORT_SET2_SETP8_Pos                              8                                                         /*!< GPIO_PORT SET2: SETP8 Position      */
#define GPIO_PORT_SET2_SETP8_Msk                              (0x01UL << GPIO_PORT_SET2_SETP8_Pos)                      /*!< GPIO_PORT SET2: SETP8 Mask          */
#define GPIO_PORT_SET2_SETP9_Pos                              9                                                         /*!< GPIO_PORT SET2: SETP9 Position      */
#define GPIO_PORT_SET2_SETP9_Msk                              (0x01UL << GPIO_PORT_SET2_SETP9_Pos)                      /*!< GPIO_PORT SET2: SETP9 Mask          */
#define GPIO_PORT_SET2_SETP10_Pos                             10                                                        /*!< GPIO_PORT SET2: SETP10 Position     */
#define GPIO_PORT_SET2_SETP10_Msk                             (0x01UL << GPIO_PORT_SET2_SETP10_Pos)                     /*!< GPIO_PORT SET2: SETP10 Mask         */
#define GPIO_PORT_SET2_SETP11_Pos                             11                                                        /*!< GPIO_PORT SET2: SETP11 Position     */
#define GPIO_PORT_SET2_SETP11_Msk                             (0x01UL << GPIO_PORT_SET2_SETP11_Pos)                     /*!< GPIO_PORT SET2: SETP11 Mask         */
#define GPIO_PORT_SET2_SETP12_Pos                             12                                                        /*!< GPIO_PORT SET2: SETP12 Position     */
#define GPIO_PORT_SET2_SETP12_Msk                             (0x01UL << GPIO_PORT_SET2_SETP12_Pos)                     /*!< GPIO_PORT SET2: SETP12 Mask         */
#define GPIO_PORT_SET2_SETP13_Pos                             13                                                        /*!< GPIO_PORT SET2: SETP13 Position     */
#define GPIO_PORT_SET2_SETP13_Msk                             (0x01UL << GPIO_PORT_SET2_SETP13_Pos)                     /*!< GPIO_PORT SET2: SETP13 Mask         */
#define GPIO_PORT_SET2_SETP14_Pos                             14                                                        /*!< GPIO_PORT SET2: SETP14 Position     */
#define GPIO_PORT_SET2_SETP14_Msk                             (0x01UL << GPIO_PORT_SET2_SETP14_Pos)                     /*!< GPIO_PORT SET2: SETP14 Mask         */
#define GPIO_PORT_SET2_SETP15_Pos                             15                                                        /*!< GPIO_PORT SET2: SETP15 Position     */
#define GPIO_PORT_SET2_SETP15_Msk                             (0x01UL << GPIO_PORT_SET2_SETP15_Pos)                     /*!< GPIO_PORT SET2: SETP15 Mask         */
#define GPIO_PORT_SET2_SETP16_Pos                             16                                                        /*!< GPIO_PORT SET2: SETP16 Position     */
#define GPIO_PORT_SET2_SETP16_Msk                             (0x01UL << GPIO_PORT_SET2_SETP16_Pos)                     /*!< GPIO_PORT SET2: SETP16 Mask         */
#define GPIO_PORT_SET2_SETP17_Pos                             17                                                        /*!< GPIO_PORT SET2: SETP17 Position     */
#define GPIO_PORT_SET2_SETP17_Msk                             (0x01UL << GPIO_PORT_SET2_SETP17_Pos)                     /*!< GPIO_PORT SET2: SETP17 Mask         */
#define GPIO_PORT_SET2_SETP18_Pos                             18                                                        /*!< GPIO_PORT SET2: SETP18 Position     */
#define GPIO_PORT_SET2_SETP18_Msk                             (0x01UL << GPIO_PORT_SET2_SETP18_Pos)                     /*!< GPIO_PORT SET2: SETP18 Mask         */
#define GPIO_PORT_SET2_SETP19_Pos                             19                                                        /*!< GPIO_PORT SET2: SETP19 Position     */
#define GPIO_PORT_SET2_SETP19_Msk                             (0x01UL << GPIO_PORT_SET2_SETP19_Pos)                     /*!< GPIO_PORT SET2: SETP19 Mask         */
#define GPIO_PORT_SET2_SETP20_Pos                             20                                                        /*!< GPIO_PORT SET2: SETP20 Position     */
#define GPIO_PORT_SET2_SETP20_Msk                             (0x01UL << GPIO_PORT_SET2_SETP20_Pos)                     /*!< GPIO_PORT SET2: SETP20 Mask         */
#define GPIO_PORT_SET2_SETP21_Pos                             21                                                        /*!< GPIO_PORT SET2: SETP21 Position     */
#define GPIO_PORT_SET2_SETP21_Msk                             (0x01UL << GPIO_PORT_SET2_SETP21_Pos)                     /*!< GPIO_PORT SET2: SETP21 Mask         */
#define GPIO_PORT_SET2_SETP22_Pos                             22                                                        /*!< GPIO_PORT SET2: SETP22 Position     */
#define GPIO_PORT_SET2_SETP22_Msk                             (0x01UL << GPIO_PORT_SET2_SETP22_Pos)                     /*!< GPIO_PORT SET2: SETP22 Mask         */
#define GPIO_PORT_SET2_SETP23_Pos                             23                                                        /*!< GPIO_PORT SET2: SETP23 Position     */
#define GPIO_PORT_SET2_SETP23_Msk                             (0x01UL << GPIO_PORT_SET2_SETP23_Pos)                     /*!< GPIO_PORT SET2: SETP23 Mask         */
#define GPIO_PORT_SET2_SETP24_Pos                             24                                                        /*!< GPIO_PORT SET2: SETP24 Position     */
#define GPIO_PORT_SET2_SETP24_Msk                             (0x01UL << GPIO_PORT_SET2_SETP24_Pos)                     /*!< GPIO_PORT SET2: SETP24 Mask         */
#define GPIO_PORT_SET2_SETP25_Pos                             25                                                        /*!< GPIO_PORT SET2: SETP25 Position     */
#define GPIO_PORT_SET2_SETP25_Msk                             (0x01UL << GPIO_PORT_SET2_SETP25_Pos)                     /*!< GPIO_PORT SET2: SETP25 Mask         */
#define GPIO_PORT_SET2_SETP26_Pos                             26                                                        /*!< GPIO_PORT SET2: SETP26 Position     */
#define GPIO_PORT_SET2_SETP26_Msk                             (0x01UL << GPIO_PORT_SET2_SETP26_Pos)                     /*!< GPIO_PORT SET2: SETP26 Mask         */
#define GPIO_PORT_SET2_SETP27_Pos                             27                                                        /*!< GPIO_PORT SET2: SETP27 Position     */
#define GPIO_PORT_SET2_SETP27_Msk                             (0x01UL << GPIO_PORT_SET2_SETP27_Pos)                     /*!< GPIO_PORT SET2: SETP27 Mask         */
#define GPIO_PORT_SET2_SETP28_Pos                             28                                                        /*!< GPIO_PORT SET2: SETP28 Position     */
#define GPIO_PORT_SET2_SETP28_Msk                             (0x01UL << GPIO_PORT_SET2_SETP28_Pos)                     /*!< GPIO_PORT SET2: SETP28 Mask         */
#define GPIO_PORT_SET2_SETP29_Pos                             29                                                        /*!< GPIO_PORT SET2: SETP29 Position     */
#define GPIO_PORT_SET2_SETP29_Msk                             (0x01UL << GPIO_PORT_SET2_SETP29_Pos)                     /*!< GPIO_PORT SET2: SETP29 Mask         */
#define GPIO_PORT_SET2_SETP30_Pos                             30                                                        /*!< GPIO_PORT SET2: SETP30 Position     */
#define GPIO_PORT_SET2_SETP30_Msk                             (0x01UL << GPIO_PORT_SET2_SETP30_Pos)                     /*!< GPIO_PORT SET2: SETP30 Mask         */
#define GPIO_PORT_SET2_SETP31_Pos                             31                                                        /*!< GPIO_PORT SET2: SETP31 Position     */
#define GPIO_PORT_SET2_SETP31_Msk                             (0x01UL << GPIO_PORT_SET2_SETP31_Pos)                     /*!< GPIO_PORT SET2: SETP31 Mask         */

// -------------------------------------  GPIO_PORT_SET3  -----------------------------------------
#define GPIO_PORT_SET3_SETP0_Pos                              0                                                         /*!< GPIO_PORT SET3: SETP0 Position      */
#define GPIO_PORT_SET3_SETP0_Msk                              (0x01UL << GPIO_PORT_SET3_SETP0_Pos)                      /*!< GPIO_PORT SET3: SETP0 Mask          */
#define GPIO_PORT_SET3_SETP1_Pos                              1                                                         /*!< GPIO_PORT SET3: SETP1 Position      */
#define GPIO_PORT_SET3_SETP1_Msk                              (0x01UL << GPIO_PORT_SET3_SETP1_Pos)                      /*!< GPIO_PORT SET3: SETP1 Mask          */
#define GPIO_PORT_SET3_SETP2_Pos                              2                                                         /*!< GPIO_PORT SET3: SETP2 Position      */
#define GPIO_PORT_SET3_SETP2_Msk                              (0x01UL << GPIO_PORT_SET3_SETP2_Pos)                      /*!< GPIO_PORT SET3: SETP2 Mask          */
#define GPIO_PORT_SET3_SETP3_Pos                              3                                                         /*!< GPIO_PORT SET3: SETP3 Position      */
#define GPIO_PORT_SET3_SETP3_Msk                              (0x01UL << GPIO_PORT_SET3_SETP3_Pos)                      /*!< GPIO_PORT SET3: SETP3 Mask          */
#define GPIO_PORT_SET3_SETP4_Pos                              4                                                         /*!< GPIO_PORT SET3: SETP4 Position      */
#define GPIO_PORT_SET3_SETP4_Msk                              (0x01UL << GPIO_PORT_SET3_SETP4_Pos)                      /*!< GPIO_PORT SET3: SETP4 Mask          */
#define GPIO_PORT_SET3_SETP5_Pos                              5                                                         /*!< GPIO_PORT SET3: SETP5 Position      */
#define GPIO_PORT_SET3_SETP5_Msk                              (0x01UL << GPIO_PORT_SET3_SETP5_Pos)                      /*!< GPIO_PORT SET3: SETP5 Mask          */
#define GPIO_PORT_SET3_SETP6_Pos                              6                                                         /*!< GPIO_PORT SET3: SETP6 Position      */
#define GPIO_PORT_SET3_SETP6_Msk                              (0x01UL << GPIO_PORT_SET3_SETP6_Pos)                      /*!< GPIO_PORT SET3: SETP6 Mask          */
#define GPIO_PORT_SET3_SETP7_Pos                              7                                                         /*!< GPIO_PORT SET3: SETP7 Position      */
#define GPIO_PORT_SET3_SETP7_Msk                              (0x01UL << GPIO_PORT_SET3_SETP7_Pos)                      /*!< GPIO_PORT SET3: SETP7 Mask          */
#define GPIO_PORT_SET3_SETP8_Pos                              8                                                         /*!< GPIO_PORT SET3: SETP8 Position      */
#define GPIO_PORT_SET3_SETP8_Msk                              (0x01UL << GPIO_PORT_SET3_SETP8_Pos)                      /*!< GPIO_PORT SET3: SETP8 Mask          */
#define GPIO_PORT_SET3_SETP9_Pos                              9                                                         /*!< GPIO_PORT SET3: SETP9 Position      */
#define GPIO_PORT_SET3_SETP9_Msk                              (0x01UL << GPIO_PORT_SET3_SETP9_Pos)                      /*!< GPIO_PORT SET3: SETP9 Mask          */
#define GPIO_PORT_SET3_SETP10_Pos                             10                                                        /*!< GPIO_PORT SET3: SETP10 Position     */
#define GPIO_PORT_SET3_SETP10_Msk                             (0x01UL << GPIO_PORT_SET3_SETP10_Pos)                     /*!< GPIO_PORT SET3: SETP10 Mask         */
#define GPIO_PORT_SET3_SETP11_Pos                             11                                                        /*!< GPIO_PORT SET3: SETP11 Position     */
#define GPIO_PORT_SET3_SETP11_Msk                             (0x01UL << GPIO_PORT_SET3_SETP11_Pos)                     /*!< GPIO_PORT SET3: SETP11 Mask         */
#define GPIO_PORT_SET3_SETP12_Pos                             12                                                        /*!< GPIO_PORT SET3: SETP12 Position     */
#define GPIO_PORT_SET3_SETP12_Msk                             (0x01UL << GPIO_PORT_SET3_SETP12_Pos)                     /*!< GPIO_PORT SET3: SETP12 Mask         */
#define GPIO_PORT_SET3_SETP13_Pos                             13                                                        /*!< GPIO_PORT SET3: SETP13 Position     */
#define GPIO_PORT_SET3_SETP13_Msk                             (0x01UL << GPIO_PORT_SET3_SETP13_Pos)                     /*!< GPIO_PORT SET3: SETP13 Mask         */
#define GPIO_PORT_SET3_SETP14_Pos                             14                                                        /*!< GPIO_PORT SET3: SETP14 Position     */
#define GPIO_PORT_SET3_SETP14_Msk                             (0x01UL << GPIO_PORT_SET3_SETP14_Pos)                     /*!< GPIO_PORT SET3: SETP14 Mask         */
#define GPIO_PORT_SET3_SETP15_Pos                             15                                                        /*!< GPIO_PORT SET3: SETP15 Position     */
#define GPIO_PORT_SET3_SETP15_Msk                             (0x01UL << GPIO_PORT_SET3_SETP15_Pos)                     /*!< GPIO_PORT SET3: SETP15 Mask         */
#define GPIO_PORT_SET3_SETP16_Pos                             16                                                        /*!< GPIO_PORT SET3: SETP16 Position     */
#define GPIO_PORT_SET3_SETP16_Msk                             (0x01UL << GPIO_PORT_SET3_SETP16_Pos)                     /*!< GPIO_PORT SET3: SETP16 Mask         */
#define GPIO_PORT_SET3_SETP17_Pos                             17                                                        /*!< GPIO_PORT SET3: SETP17 Position     */
#define GPIO_PORT_SET3_SETP17_Msk                             (0x01UL << GPIO_PORT_SET3_SETP17_Pos)                     /*!< GPIO_PORT SET3: SETP17 Mask         */
#define GPIO_PORT_SET3_SETP18_Pos                             18                                                        /*!< GPIO_PORT SET3: SETP18 Position     */
#define GPIO_PORT_SET3_SETP18_Msk                             (0x01UL << GPIO_PORT_SET3_SETP18_Pos)                     /*!< GPIO_PORT SET3: SETP18 Mask         */
#define GPIO_PORT_SET3_SETP19_Pos                             19                                                        /*!< GPIO_PORT SET3: SETP19 Position     */
#define GPIO_PORT_SET3_SETP19_Msk                             (0x01UL << GPIO_PORT_SET3_SETP19_Pos)                     /*!< GPIO_PORT SET3: SETP19 Mask         */
#define GPIO_PORT_SET3_SETP20_Pos                             20                                                        /*!< GPIO_PORT SET3: SETP20 Position     */
#define GPIO_PORT_SET3_SETP20_Msk                             (0x01UL << GPIO_PORT_SET3_SETP20_Pos)                     /*!< GPIO_PORT SET3: SETP20 Mask         */
#define GPIO_PORT_SET3_SETP21_Pos                             21                                                        /*!< GPIO_PORT SET3: SETP21 Position     */
#define GPIO_PORT_SET3_SETP21_Msk                             (0x01UL << GPIO_PORT_SET3_SETP21_Pos)                     /*!< GPIO_PORT SET3: SETP21 Mask         */
#define GPIO_PORT_SET3_SETP22_Pos                             22                                                        /*!< GPIO_PORT SET3: SETP22 Position     */
#define GPIO_PORT_SET3_SETP22_Msk                             (0x01UL << GPIO_PORT_SET3_SETP22_Pos)                     /*!< GPIO_PORT SET3: SETP22 Mask         */
#define GPIO_PORT_SET3_SETP23_Pos                             23                                                        /*!< GPIO_PORT SET3: SETP23 Position     */
#define GPIO_PORT_SET3_SETP23_Msk                             (0x01UL << GPIO_PORT_SET3_SETP23_Pos)                     /*!< GPIO_PORT SET3: SETP23 Mask         */
#define GPIO_PORT_SET3_SETP24_Pos                             24                                                        /*!< GPIO_PORT SET3: SETP24 Position     */
#define GPIO_PORT_SET3_SETP24_Msk                             (0x01UL << GPIO_PORT_SET3_SETP24_Pos)                     /*!< GPIO_PORT SET3: SETP24 Mask         */
#define GPIO_PORT_SET3_SETP25_Pos                             25                                                        /*!< GPIO_PORT SET3: SETP25 Position     */
#define GPIO_PORT_SET3_SETP25_Msk                             (0x01UL << GPIO_PORT_SET3_SETP25_Pos)                     /*!< GPIO_PORT SET3: SETP25 Mask         */
#define GPIO_PORT_SET3_SETP26_Pos                             26                                                        /*!< GPIO_PORT SET3: SETP26 Position     */
#define GPIO_PORT_SET3_SETP26_Msk                             (0x01UL << GPIO_PORT_SET3_SETP26_Pos)                     /*!< GPIO_PORT SET3: SETP26 Mask         */
#define GPIO_PORT_SET3_SETP27_Pos                             27                                                        /*!< GPIO_PORT SET3: SETP27 Position     */
#define GPIO_PORT_SET3_SETP27_Msk                             (0x01UL << GPIO_PORT_SET3_SETP27_Pos)                     /*!< GPIO_PORT SET3: SETP27 Mask         */
#define GPIO_PORT_SET3_SETP28_Pos                             28                                                        /*!< GPIO_PORT SET3: SETP28 Position     */
#define GPIO_PORT_SET3_SETP28_Msk                             (0x01UL << GPIO_PORT_SET3_SETP28_Pos)                     /*!< GPIO_PORT SET3: SETP28 Mask         */
#define GPIO_PORT_SET3_SETP29_Pos                             29                                                        /*!< GPIO_PORT SET3: SETP29 Position     */
#define GPIO_PORT_SET3_SETP29_Msk                             (0x01UL << GPIO_PORT_SET3_SETP29_Pos)                     /*!< GPIO_PORT SET3: SETP29 Mask         */
#define GPIO_PORT_SET3_SETP30_Pos                             30                                                        /*!< GPIO_PORT SET3: SETP30 Position     */
#define GPIO_PORT_SET3_SETP30_Msk                             (0x01UL << GPIO_PORT_SET3_SETP30_Pos)                     /*!< GPIO_PORT SET3: SETP30 Mask         */
#define GPIO_PORT_SET3_SETP31_Pos                             31                                                        /*!< GPIO_PORT SET3: SETP31 Position     */
#define GPIO_PORT_SET3_SETP31_Msk                             (0x01UL << GPIO_PORT_SET3_SETP31_Pos)                     /*!< GPIO_PORT SET3: SETP31 Mask         */

// -------------------------------------  GPIO_PORT_SET4  -----------------------------------------
#define GPIO_PORT_SET4_SETP0_Pos                              0                                                         /*!< GPIO_PORT SET4: SETP0 Position      */
#define GPIO_PORT_SET4_SETP0_Msk                              (0x01UL << GPIO_PORT_SET4_SETP0_Pos)                      /*!< GPIO_PORT SET4: SETP0 Mask          */
#define GPIO_PORT_SET4_SETP1_Pos                              1                                                         /*!< GPIO_PORT SET4: SETP1 Position      */
#define GPIO_PORT_SET4_SETP1_Msk                              (0x01UL << GPIO_PORT_SET4_SETP1_Pos)                      /*!< GPIO_PORT SET4: SETP1 Mask          */
#define GPIO_PORT_SET4_SETP2_Pos                              2                                                         /*!< GPIO_PORT SET4: SETP2 Position      */
#define GPIO_PORT_SET4_SETP2_Msk                              (0x01UL << GPIO_PORT_SET4_SETP2_Pos)                      /*!< GPIO_PORT SET4: SETP2 Mask          */
#define GPIO_PORT_SET4_SETP3_Pos                              3                                                         /*!< GPIO_PORT SET4: SETP3 Position      */
#define GPIO_PORT_SET4_SETP3_Msk                              (0x01UL << GPIO_PORT_SET4_SETP3_Pos)                      /*!< GPIO_PORT SET4: SETP3 Mask          */
#define GPIO_PORT_SET4_SETP4_Pos                              4                                                         /*!< GPIO_PORT SET4: SETP4 Position      */
#define GPIO_PORT_SET4_SETP4_Msk                              (0x01UL << GPIO_PORT_SET4_SETP4_Pos)                      /*!< GPIO_PORT SET4: SETP4 Mask          */
#define GPIO_PORT_SET4_SETP5_Pos                              5                                                         /*!< GPIO_PORT SET4: SETP5 Position      */
#define GPIO_PORT_SET4_SETP5_Msk                              (0x01UL << GPIO_PORT_SET4_SETP5_Pos)                      /*!< GPIO_PORT SET4: SETP5 Mask          */
#define GPIO_PORT_SET4_SETP6_Pos                              6                                                         /*!< GPIO_PORT SET4: SETP6 Position      */
#define GPIO_PORT_SET4_SETP6_Msk                              (0x01UL << GPIO_PORT_SET4_SETP6_Pos)                      /*!< GPIO_PORT SET4: SETP6 Mask          */
#define GPIO_PORT_SET4_SETP7_Pos                              7                                                         /*!< GPIO_PORT SET4: SETP7 Position      */
#define GPIO_PORT_SET4_SETP7_Msk                              (0x01UL << GPIO_PORT_SET4_SETP7_Pos)                      /*!< GPIO_PORT SET4: SETP7 Mask          */
#define GPIO_PORT_SET4_SETP8_Pos                              8                                                         /*!< GPIO_PORT SET4: SETP8 Position      */
#define GPIO_PORT_SET4_SETP8_Msk                              (0x01UL << GPIO_PORT_SET4_SETP8_Pos)                      /*!< GPIO_PORT SET4: SETP8 Mask          */
#define GPIO_PORT_SET4_SETP9_Pos                              9                                                         /*!< GPIO_PORT SET4: SETP9 Position      */
#define GPIO_PORT_SET4_SETP9_Msk                              (0x01UL << GPIO_PORT_SET4_SETP9_Pos)                      /*!< GPIO_PORT SET4: SETP9 Mask          */
#define GPIO_PORT_SET4_SETP10_Pos                             10                                                        /*!< GPIO_PORT SET4: SETP10 Position     */
#define GPIO_PORT_SET4_SETP10_Msk                             (0x01UL << GPIO_PORT_SET4_SETP10_Pos)                     /*!< GPIO_PORT SET4: SETP10 Mask         */
#define GPIO_PORT_SET4_SETP11_Pos                             11                                                        /*!< GPIO_PORT SET4: SETP11 Position     */
#define GPIO_PORT_SET4_SETP11_Msk                             (0x01UL << GPIO_PORT_SET4_SETP11_Pos)                     /*!< GPIO_PORT SET4: SETP11 Mask         */
#define GPIO_PORT_SET4_SETP12_Pos                             12                                                        /*!< GPIO_PORT SET4: SETP12 Position     */
#define GPIO_PORT_SET4_SETP12_Msk                             (0x01UL << GPIO_PORT_SET4_SETP12_Pos)                     /*!< GPIO_PORT SET4: SETP12 Mask         */
#define GPIO_PORT_SET4_SETP13_Pos                             13                                                        /*!< GPIO_PORT SET4: SETP13 Position     */
#define GPIO_PORT_SET4_SETP13_Msk                             (0x01UL << GPIO_PORT_SET4_SETP13_Pos)                     /*!< GPIO_PORT SET4: SETP13 Mask         */
#define GPIO_PORT_SET4_SETP14_Pos                             14                                                        /*!< GPIO_PORT SET4: SETP14 Position     */
#define GPIO_PORT_SET4_SETP14_Msk                             (0x01UL << GPIO_PORT_SET4_SETP14_Pos)                     /*!< GPIO_PORT SET4: SETP14 Mask         */
#define GPIO_PORT_SET4_SETP15_Pos                             15                                                        /*!< GPIO_PORT SET4: SETP15 Position     */
#define GPIO_PORT_SET4_SETP15_Msk                             (0x01UL << GPIO_PORT_SET4_SETP15_Pos)                     /*!< GPIO_PORT SET4: SETP15 Mask         */
#define GPIO_PORT_SET4_SETP16_Pos                             16                                                        /*!< GPIO_PORT SET4: SETP16 Position     */
#define GPIO_PORT_SET4_SETP16_Msk                             (0x01UL << GPIO_PORT_SET4_SETP16_Pos)                     /*!< GPIO_PORT SET4: SETP16 Mask         */
#define GPIO_PORT_SET4_SETP17_Pos                             17                                                        /*!< GPIO_PORT SET4: SETP17 Position     */
#define GPIO_PORT_SET4_SETP17_Msk                             (0x01UL << GPIO_PORT_SET4_SETP17_Pos)                     /*!< GPIO_PORT SET4: SETP17 Mask         */
#define GPIO_PORT_SET4_SETP18_Pos                             18                                                        /*!< GPIO_PORT SET4: SETP18 Position     */
#define GPIO_PORT_SET4_SETP18_Msk                             (0x01UL << GPIO_PORT_SET4_SETP18_Pos)                     /*!< GPIO_PORT SET4: SETP18 Mask         */
#define GPIO_PORT_SET4_SETP19_Pos                             19                                                        /*!< GPIO_PORT SET4: SETP19 Position     */
#define GPIO_PORT_SET4_SETP19_Msk                             (0x01UL << GPIO_PORT_SET4_SETP19_Pos)                     /*!< GPIO_PORT SET4: SETP19 Mask         */
#define GPIO_PORT_SET4_SETP20_Pos                             20                                                        /*!< GPIO_PORT SET4: SETP20 Position     */
#define GPIO_PORT_SET4_SETP20_Msk                             (0x01UL << GPIO_PORT_SET4_SETP20_Pos)                     /*!< GPIO_PORT SET4: SETP20 Mask         */
#define GPIO_PORT_SET4_SETP21_Pos                             21                                                        /*!< GPIO_PORT SET4: SETP21 Position     */
#define GPIO_PORT_SET4_SETP21_Msk                             (0x01UL << GPIO_PORT_SET4_SETP21_Pos)                     /*!< GPIO_PORT SET4: SETP21 Mask         */
#define GPIO_PORT_SET4_SETP22_Pos                             22                                                        /*!< GPIO_PORT SET4: SETP22 Position     */
#define GPIO_PORT_SET4_SETP22_Msk                             (0x01UL << GPIO_PORT_SET4_SETP22_Pos)                     /*!< GPIO_PORT SET4: SETP22 Mask         */
#define GPIO_PORT_SET4_SETP23_Pos                             23                                                        /*!< GPIO_PORT SET4: SETP23 Position     */
#define GPIO_PORT_SET4_SETP23_Msk                             (0x01UL << GPIO_PORT_SET4_SETP23_Pos)                     /*!< GPIO_PORT SET4: SETP23 Mask         */
#define GPIO_PORT_SET4_SETP24_Pos                             24                                                        /*!< GPIO_PORT SET4: SETP24 Position     */
#define GPIO_PORT_SET4_SETP24_Msk                             (0x01UL << GPIO_PORT_SET4_SETP24_Pos)                     /*!< GPIO_PORT SET4: SETP24 Mask         */
#define GPIO_PORT_SET4_SETP25_Pos                             25                                                        /*!< GPIO_PORT SET4: SETP25 Position     */
#define GPIO_PORT_SET4_SETP25_Msk                             (0x01UL << GPIO_PORT_SET4_SETP25_Pos)                     /*!< GPIO_PORT SET4: SETP25 Mask         */
#define GPIO_PORT_SET4_SETP26_Pos                             26                                                        /*!< GPIO_PORT SET4: SETP26 Position     */
#define GPIO_PORT_SET4_SETP26_Msk                             (0x01UL << GPIO_PORT_SET4_SETP26_Pos)                     /*!< GPIO_PORT SET4: SETP26 Mask         */
#define GPIO_PORT_SET4_SETP27_Pos                             27                                                        /*!< GPIO_PORT SET4: SETP27 Position     */
#define GPIO_PORT_SET4_SETP27_Msk                             (0x01UL << GPIO_PORT_SET4_SETP27_Pos)                     /*!< GPIO_PORT SET4: SETP27 Mask         */
#define GPIO_PORT_SET4_SETP28_Pos                             28                                                        /*!< GPIO_PORT SET4: SETP28 Position     */
#define GPIO_PORT_SET4_SETP28_Msk                             (0x01UL << GPIO_PORT_SET4_SETP28_Pos)                     /*!< GPIO_PORT SET4: SETP28 Mask         */
#define GPIO_PORT_SET4_SETP29_Pos                             29                                                        /*!< GPIO_PORT SET4: SETP29 Position     */
#define GPIO_PORT_SET4_SETP29_Msk                             (0x01UL << GPIO_PORT_SET4_SETP29_Pos)                     /*!< GPIO_PORT SET4: SETP29 Mask         */
#define GPIO_PORT_SET4_SETP30_Pos                             30                                                        /*!< GPIO_PORT SET4: SETP30 Position     */
#define GPIO_PORT_SET4_SETP30_Msk                             (0x01UL << GPIO_PORT_SET4_SETP30_Pos)                     /*!< GPIO_PORT SET4: SETP30 Mask         */
#define GPIO_PORT_SET4_SETP31_Pos                             31                                                        /*!< GPIO_PORT SET4: SETP31 Position     */
#define GPIO_PORT_SET4_SETP31_Msk                             (0x01UL << GPIO_PORT_SET4_SETP31_Pos)                     /*!< GPIO_PORT SET4: SETP31 Mask         */

// -------------------------------------  GPIO_PORT_SET5  -----------------------------------------
#define GPIO_PORT_SET5_SETP0_Pos                              0                                                         /*!< GPIO_PORT SET5: SETP0 Position      */
#define GPIO_PORT_SET5_SETP0_Msk                              (0x01UL << GPIO_PORT_SET5_SETP0_Pos)                      /*!< GPIO_PORT SET5: SETP0 Mask          */
#define GPIO_PORT_SET5_SETP1_Pos                              1                                                         /*!< GPIO_PORT SET5: SETP1 Position      */
#define GPIO_PORT_SET5_SETP1_Msk                              (0x01UL << GPIO_PORT_SET5_SETP1_Pos)                      /*!< GPIO_PORT SET5: SETP1 Mask          */
#define GPIO_PORT_SET5_SETP2_Pos                              2                                                         /*!< GPIO_PORT SET5: SETP2 Position      */
#define GPIO_PORT_SET5_SETP2_Msk                              (0x01UL << GPIO_PORT_SET5_SETP2_Pos)                      /*!< GPIO_PORT SET5: SETP2 Mask          */
#define GPIO_PORT_SET5_SETP3_Pos                              3                                                         /*!< GPIO_PORT SET5: SETP3 Position      */
#define GPIO_PORT_SET5_SETP3_Msk                              (0x01UL << GPIO_PORT_SET5_SETP3_Pos)                      /*!< GPIO_PORT SET5: SETP3 Mask          */
#define GPIO_PORT_SET5_SETP4_Pos                              4                                                         /*!< GPIO_PORT SET5: SETP4 Position      */
#define GPIO_PORT_SET5_SETP4_Msk                              (0x01UL << GPIO_PORT_SET5_SETP4_Pos)                      /*!< GPIO_PORT SET5: SETP4 Mask          */
#define GPIO_PORT_SET5_SETP5_Pos                              5                                                         /*!< GPIO_PORT SET5: SETP5 Position      */
#define GPIO_PORT_SET5_SETP5_Msk                              (0x01UL << GPIO_PORT_SET5_SETP5_Pos)                      /*!< GPIO_PORT SET5: SETP5 Mask          */
#define GPIO_PORT_SET5_SETP6_Pos                              6                                                         /*!< GPIO_PORT SET5: SETP6 Position      */
#define GPIO_PORT_SET5_SETP6_Msk                              (0x01UL << GPIO_PORT_SET5_SETP6_Pos)                      /*!< GPIO_PORT SET5: SETP6 Mask          */
#define GPIO_PORT_SET5_SETP7_Pos                              7                                                         /*!< GPIO_PORT SET5: SETP7 Position      */
#define GPIO_PORT_SET5_SETP7_Msk                              (0x01UL << GPIO_PORT_SET5_SETP7_Pos)                      /*!< GPIO_PORT SET5: SETP7 Mask          */
#define GPIO_PORT_SET5_SETP8_Pos                              8                                                         /*!< GPIO_PORT SET5: SETP8 Position      */
#define GPIO_PORT_SET5_SETP8_Msk                              (0x01UL << GPIO_PORT_SET5_SETP8_Pos)                      /*!< GPIO_PORT SET5: SETP8 Mask          */
#define GPIO_PORT_SET5_SETP9_Pos                              9                                                         /*!< GPIO_PORT SET5: SETP9 Position      */
#define GPIO_PORT_SET5_SETP9_Msk                              (0x01UL << GPIO_PORT_SET5_SETP9_Pos)                      /*!< GPIO_PORT SET5: SETP9 Mask          */
#define GPIO_PORT_SET5_SETP10_Pos                             10                                                        /*!< GPIO_PORT SET5: SETP10 Position     */
#define GPIO_PORT_SET5_SETP10_Msk                             (0x01UL << GPIO_PORT_SET5_SETP10_Pos)                     /*!< GPIO_PORT SET5: SETP10 Mask         */
#define GPIO_PORT_SET5_SETP11_Pos                             11                                                        /*!< GPIO_PORT SET5: SETP11 Position     */
#define GPIO_PORT_SET5_SETP11_Msk                             (0x01UL << GPIO_PORT_SET5_SETP11_Pos)                     /*!< GPIO_PORT SET5: SETP11 Mask         */
#define GPIO_PORT_SET5_SETP12_Pos                             12                                                        /*!< GPIO_PORT SET5: SETP12 Position     */
#define GPIO_PORT_SET5_SETP12_Msk                             (0x01UL << GPIO_PORT_SET5_SETP12_Pos)                     /*!< GPIO_PORT SET5: SETP12 Mask         */
#define GPIO_PORT_SET5_SETP13_Pos                             13                                                        /*!< GPIO_PORT SET5: SETP13 Position     */
#define GPIO_PORT_SET5_SETP13_Msk                             (0x01UL << GPIO_PORT_SET5_SETP13_Pos)                     /*!< GPIO_PORT SET5: SETP13 Mask         */
#define GPIO_PORT_SET5_SETP14_Pos                             14                                                        /*!< GPIO_PORT SET5: SETP14 Position     */
#define GPIO_PORT_SET5_SETP14_Msk                             (0x01UL << GPIO_PORT_SET5_SETP14_Pos)                     /*!< GPIO_PORT SET5: SETP14 Mask         */
#define GPIO_PORT_SET5_SETP15_Pos                             15                                                        /*!< GPIO_PORT SET5: SETP15 Position     */
#define GPIO_PORT_SET5_SETP15_Msk                             (0x01UL << GPIO_PORT_SET5_SETP15_Pos)                     /*!< GPIO_PORT SET5: SETP15 Mask         */
#define GPIO_PORT_SET5_SETP16_Pos                             16                                                        /*!< GPIO_PORT SET5: SETP16 Position     */
#define GPIO_PORT_SET5_SETP16_Msk                             (0x01UL << GPIO_PORT_SET5_SETP16_Pos)                     /*!< GPIO_PORT SET5: SETP16 Mask         */
#define GPIO_PORT_SET5_SETP17_Pos                             17                                                        /*!< GPIO_PORT SET5: SETP17 Position     */
#define GPIO_PORT_SET5_SETP17_Msk                             (0x01UL << GPIO_PORT_SET5_SETP17_Pos)                     /*!< GPIO_PORT SET5: SETP17 Mask         */
#define GPIO_PORT_SET5_SETP18_Pos                             18                                                        /*!< GPIO_PORT SET5: SETP18 Position     */
#define GPIO_PORT_SET5_SETP18_Msk                             (0x01UL << GPIO_PORT_SET5_SETP18_Pos)                     /*!< GPIO_PORT SET5: SETP18 Mask         */
#define GPIO_PORT_SET5_SETP19_Pos                             19                                                        /*!< GPIO_PORT SET5: SETP19 Position     */
#define GPIO_PORT_SET5_SETP19_Msk                             (0x01UL << GPIO_PORT_SET5_SETP19_Pos)                     /*!< GPIO_PORT SET5: SETP19 Mask         */
#define GPIO_PORT_SET5_SETP20_Pos                             20                                                        /*!< GPIO_PORT SET5: SETP20 Position     */
#define GPIO_PORT_SET5_SETP20_Msk                             (0x01UL << GPIO_PORT_SET5_SETP20_Pos)                     /*!< GPIO_PORT SET5: SETP20 Mask         */
#define GPIO_PORT_SET5_SETP21_Pos                             21                                                        /*!< GPIO_PORT SET5: SETP21 Position     */
#define GPIO_PORT_SET5_SETP21_Msk                             (0x01UL << GPIO_PORT_SET5_SETP21_Pos)                     /*!< GPIO_PORT SET5: SETP21 Mask         */
#define GPIO_PORT_SET5_SETP22_Pos                             22                                                        /*!< GPIO_PORT SET5: SETP22 Position     */
#define GPIO_PORT_SET5_SETP22_Msk                             (0x01UL << GPIO_PORT_SET5_SETP22_Pos)                     /*!< GPIO_PORT SET5: SETP22 Mask         */
#define GPIO_PORT_SET5_SETP23_Pos                             23                                                        /*!< GPIO_PORT SET5: SETP23 Position     */
#define GPIO_PORT_SET5_SETP23_Msk                             (0x01UL << GPIO_PORT_SET5_SETP23_Pos)                     /*!< GPIO_PORT SET5: SETP23 Mask         */
#define GPIO_PORT_SET5_SETP24_Pos                             24                                                        /*!< GPIO_PORT SET5: SETP24 Position     */
#define GPIO_PORT_SET5_SETP24_Msk                             (0x01UL << GPIO_PORT_SET5_SETP24_Pos)                     /*!< GPIO_PORT SET5: SETP24 Mask         */
#define GPIO_PORT_SET5_SETP25_Pos                             25                                                        /*!< GPIO_PORT SET5: SETP25 Position     */
#define GPIO_PORT_SET5_SETP25_Msk                             (0x01UL << GPIO_PORT_SET5_SETP25_Pos)                     /*!< GPIO_PORT SET5: SETP25 Mask         */
#define GPIO_PORT_SET5_SETP26_Pos                             26                                                        /*!< GPIO_PORT SET5: SETP26 Position     */
#define GPIO_PORT_SET5_SETP26_Msk                             (0x01UL << GPIO_PORT_SET5_SETP26_Pos)                     /*!< GPIO_PORT SET5: SETP26 Mask         */
#define GPIO_PORT_SET5_SETP27_Pos                             27                                                        /*!< GPIO_PORT SET5: SETP27 Position     */
#define GPIO_PORT_SET5_SETP27_Msk                             (0x01UL << GPIO_PORT_SET5_SETP27_Pos)                     /*!< GPIO_PORT SET5: SETP27 Mask         */
#define GPIO_PORT_SET5_SETP28_Pos                             28                                                        /*!< GPIO_PORT SET5: SETP28 Position     */
#define GPIO_PORT_SET5_SETP28_Msk                             (0x01UL << GPIO_PORT_SET5_SETP28_Pos)                     /*!< GPIO_PORT SET5: SETP28 Mask         */
#define GPIO_PORT_SET5_SETP29_Pos                             29                                                        /*!< GPIO_PORT SET5: SETP29 Position     */
#define GPIO_PORT_SET5_SETP29_Msk                             (0x01UL << GPIO_PORT_SET5_SETP29_Pos)                     /*!< GPIO_PORT SET5: SETP29 Mask         */
#define GPIO_PORT_SET5_SETP30_Pos                             30                                                        /*!< GPIO_PORT SET5: SETP30 Position     */
#define GPIO_PORT_SET5_SETP30_Msk                             (0x01UL << GPIO_PORT_SET5_SETP30_Pos)                     /*!< GPIO_PORT SET5: SETP30 Mask         */
#define GPIO_PORT_SET5_SETP31_Pos                             31                                                        /*!< GPIO_PORT SET5: SETP31 Position     */
#define GPIO_PORT_SET5_SETP31_Msk                             (0x01UL << GPIO_PORT_SET5_SETP31_Pos)                     /*!< GPIO_PORT SET5: SETP31 Mask         */

// -------------------------------------  GPIO_PORT_SET6  -----------------------------------------
#define GPIO_PORT_SET6_SETP0_Pos                              0                                                         /*!< GPIO_PORT SET6: SETP0 Position      */
#define GPIO_PORT_SET6_SETP0_Msk                              (0x01UL << GPIO_PORT_SET6_SETP0_Pos)                      /*!< GPIO_PORT SET6: SETP0 Mask          */
#define GPIO_PORT_SET6_SETP1_Pos                              1                                                         /*!< GPIO_PORT SET6: SETP1 Position      */
#define GPIO_PORT_SET6_SETP1_Msk                              (0x01UL << GPIO_PORT_SET6_SETP1_Pos)                      /*!< GPIO_PORT SET6: SETP1 Mask          */
#define GPIO_PORT_SET6_SETP2_Pos                              2                                                         /*!< GPIO_PORT SET6: SETP2 Position      */
#define GPIO_PORT_SET6_SETP2_Msk                              (0x01UL << GPIO_PORT_SET6_SETP2_Pos)                      /*!< GPIO_PORT SET6: SETP2 Mask          */
#define GPIO_PORT_SET6_SETP3_Pos                              3                                                         /*!< GPIO_PORT SET6: SETP3 Position      */
#define GPIO_PORT_SET6_SETP3_Msk                              (0x01UL << GPIO_PORT_SET6_SETP3_Pos)                      /*!< GPIO_PORT SET6: SETP3 Mask          */
#define GPIO_PORT_SET6_SETP4_Pos                              4                                                         /*!< GPIO_PORT SET6: SETP4 Position      */
#define GPIO_PORT_SET6_SETP4_Msk                              (0x01UL << GPIO_PORT_SET6_SETP4_Pos)                      /*!< GPIO_PORT SET6: SETP4 Mask          */
#define GPIO_PORT_SET6_SETP5_Pos                              5                                                         /*!< GPIO_PORT SET6: SETP5 Position      */
#define GPIO_PORT_SET6_SETP5_Msk                              (0x01UL << GPIO_PORT_SET6_SETP5_Pos)                      /*!< GPIO_PORT SET6: SETP5 Mask          */
#define GPIO_PORT_SET6_SETP6_Pos                              6                                                         /*!< GPIO_PORT SET6: SETP6 Position      */
#define GPIO_PORT_SET6_SETP6_Msk                              (0x01UL << GPIO_PORT_SET6_SETP6_Pos)                      /*!< GPIO_PORT SET6: SETP6 Mask          */
#define GPIO_PORT_SET6_SETP7_Pos                              7                                                         /*!< GPIO_PORT SET6: SETP7 Position      */
#define GPIO_PORT_SET6_SETP7_Msk                              (0x01UL << GPIO_PORT_SET6_SETP7_Pos)                      /*!< GPIO_PORT SET6: SETP7 Mask          */
#define GPIO_PORT_SET6_SETP8_Pos                              8                                                         /*!< GPIO_PORT SET6: SETP8 Position      */
#define GPIO_PORT_SET6_SETP8_Msk                              (0x01UL << GPIO_PORT_SET6_SETP8_Pos)                      /*!< GPIO_PORT SET6: SETP8 Mask          */
#define GPIO_PORT_SET6_SETP9_Pos                              9                                                         /*!< GPIO_PORT SET6: SETP9 Position      */
#define GPIO_PORT_SET6_SETP9_Msk                              (0x01UL << GPIO_PORT_SET6_SETP9_Pos)                      /*!< GPIO_PORT SET6: SETP9 Mask          */
#define GPIO_PORT_SET6_SETP10_Pos                             10                                                        /*!< GPIO_PORT SET6: SETP10 Position     */
#define GPIO_PORT_SET6_SETP10_Msk                             (0x01UL << GPIO_PORT_SET6_SETP10_Pos)                     /*!< GPIO_PORT SET6: SETP10 Mask         */
#define GPIO_PORT_SET6_SETP11_Pos                             11                                                        /*!< GPIO_PORT SET6: SETP11 Position     */
#define GPIO_PORT_SET6_SETP11_Msk                             (0x01UL << GPIO_PORT_SET6_SETP11_Pos)                     /*!< GPIO_PORT SET6: SETP11 Mask         */
#define GPIO_PORT_SET6_SETP12_Pos                             12                                                        /*!< GPIO_PORT SET6: SETP12 Position     */
#define GPIO_PORT_SET6_SETP12_Msk                             (0x01UL << GPIO_PORT_SET6_SETP12_Pos)                     /*!< GPIO_PORT SET6: SETP12 Mask         */
#define GPIO_PORT_SET6_SETP13_Pos                             13                                                        /*!< GPIO_PORT SET6: SETP13 Position     */
#define GPIO_PORT_SET6_SETP13_Msk                             (0x01UL << GPIO_PORT_SET6_SETP13_Pos)                     /*!< GPIO_PORT SET6: SETP13 Mask         */
#define GPIO_PORT_SET6_SETP14_Pos                             14                                                        /*!< GPIO_PORT SET6: SETP14 Position     */
#define GPIO_PORT_SET6_SETP14_Msk                             (0x01UL << GPIO_PORT_SET6_SETP14_Pos)                     /*!< GPIO_PORT SET6: SETP14 Mask         */
#define GPIO_PORT_SET6_SETP15_Pos                             15                                                        /*!< GPIO_PORT SET6: SETP15 Position     */
#define GPIO_PORT_SET6_SETP15_Msk                             (0x01UL << GPIO_PORT_SET6_SETP15_Pos)                     /*!< GPIO_PORT SET6: SETP15 Mask         */
#define GPIO_PORT_SET6_SETP16_Pos                             16                                                        /*!< GPIO_PORT SET6: SETP16 Position     */
#define GPIO_PORT_SET6_SETP16_Msk                             (0x01UL << GPIO_PORT_SET6_SETP16_Pos)                     /*!< GPIO_PORT SET6: SETP16 Mask         */
#define GPIO_PORT_SET6_SETP17_Pos                             17                                                        /*!< GPIO_PORT SET6: SETP17 Position     */
#define GPIO_PORT_SET6_SETP17_Msk                             (0x01UL << GPIO_PORT_SET6_SETP17_Pos)                     /*!< GPIO_PORT SET6: SETP17 Mask         */
#define GPIO_PORT_SET6_SETP18_Pos                             18                                                        /*!< GPIO_PORT SET6: SETP18 Position     */
#define GPIO_PORT_SET6_SETP18_Msk                             (0x01UL << GPIO_PORT_SET6_SETP18_Pos)                     /*!< GPIO_PORT SET6: SETP18 Mask         */
#define GPIO_PORT_SET6_SETP19_Pos                             19                                                        /*!< GPIO_PORT SET6: SETP19 Position     */
#define GPIO_PORT_SET6_SETP19_Msk                             (0x01UL << GPIO_PORT_SET6_SETP19_Pos)                     /*!< GPIO_PORT SET6: SETP19 Mask         */
#define GPIO_PORT_SET6_SETP20_Pos                             20                                                        /*!< GPIO_PORT SET6: SETP20 Position     */
#define GPIO_PORT_SET6_SETP20_Msk                             (0x01UL << GPIO_PORT_SET6_SETP20_Pos)                     /*!< GPIO_PORT SET6: SETP20 Mask         */
#define GPIO_PORT_SET6_SETP21_Pos                             21                                                        /*!< GPIO_PORT SET6: SETP21 Position     */
#define GPIO_PORT_SET6_SETP21_Msk                             (0x01UL << GPIO_PORT_SET6_SETP21_Pos)                     /*!< GPIO_PORT SET6: SETP21 Mask         */
#define GPIO_PORT_SET6_SETP22_Pos                             22                                                        /*!< GPIO_PORT SET6: SETP22 Position     */
#define GPIO_PORT_SET6_SETP22_Msk                             (0x01UL << GPIO_PORT_SET6_SETP22_Pos)                     /*!< GPIO_PORT SET6: SETP22 Mask         */
#define GPIO_PORT_SET6_SETP23_Pos                             23                                                        /*!< GPIO_PORT SET6: SETP23 Position     */
#define GPIO_PORT_SET6_SETP23_Msk                             (0x01UL << GPIO_PORT_SET6_SETP23_Pos)                     /*!< GPIO_PORT SET6: SETP23 Mask         */
#define GPIO_PORT_SET6_SETP24_Pos                             24                                                        /*!< GPIO_PORT SET6: SETP24 Position     */
#define GPIO_PORT_SET6_SETP24_Msk                             (0x01UL << GPIO_PORT_SET6_SETP24_Pos)                     /*!< GPIO_PORT SET6: SETP24 Mask         */
#define GPIO_PORT_SET6_SETP25_Pos                             25                                                        /*!< GPIO_PORT SET6: SETP25 Position     */
#define GPIO_PORT_SET6_SETP25_Msk                             (0x01UL << GPIO_PORT_SET6_SETP25_Pos)                     /*!< GPIO_PORT SET6: SETP25 Mask         */
#define GPIO_PORT_SET6_SETP26_Pos                             26                                                        /*!< GPIO_PORT SET6: SETP26 Position     */
#define GPIO_PORT_SET6_SETP26_Msk                             (0x01UL << GPIO_PORT_SET6_SETP26_Pos)                     /*!< GPIO_PORT SET6: SETP26 Mask         */
#define GPIO_PORT_SET6_SETP27_Pos                             27                                                        /*!< GPIO_PORT SET6: SETP27 Position     */
#define GPIO_PORT_SET6_SETP27_Msk                             (0x01UL << GPIO_PORT_SET6_SETP27_Pos)                     /*!< GPIO_PORT SET6: SETP27 Mask         */
#define GPIO_PORT_SET6_SETP28_Pos                             28                                                        /*!< GPIO_PORT SET6: SETP28 Position     */
#define GPIO_PORT_SET6_SETP28_Msk                             (0x01UL << GPIO_PORT_SET6_SETP28_Pos)                     /*!< GPIO_PORT SET6: SETP28 Mask         */
#define GPIO_PORT_SET6_SETP29_Pos                             29                                                        /*!< GPIO_PORT SET6: SETP29 Position     */
#define GPIO_PORT_SET6_SETP29_Msk                             (0x01UL << GPIO_PORT_SET6_SETP29_Pos)                     /*!< GPIO_PORT SET6: SETP29 Mask         */
#define GPIO_PORT_SET6_SETP30_Pos                             30                                                        /*!< GPIO_PORT SET6: SETP30 Position     */
#define GPIO_PORT_SET6_SETP30_Msk                             (0x01UL << GPIO_PORT_SET6_SETP30_Pos)                     /*!< GPIO_PORT SET6: SETP30 Mask         */
#define GPIO_PORT_SET6_SETP31_Pos                             31                                                        /*!< GPIO_PORT SET6: SETP31 Position     */
#define GPIO_PORT_SET6_SETP31_Msk                             (0x01UL << GPIO_PORT_SET6_SETP31_Pos)                     /*!< GPIO_PORT SET6: SETP31 Mask         */

// -------------------------------------  GPIO_PORT_SET7  -----------------------------------------
#define GPIO_PORT_SET7_SETP0_Pos                              0                                                         /*!< GPIO_PORT SET7: SETP0 Position      */
#define GPIO_PORT_SET7_SETP0_Msk                              (0x01UL << GPIO_PORT_SET7_SETP0_Pos)                      /*!< GPIO_PORT SET7: SETP0 Mask          */
#define GPIO_PORT_SET7_SETP1_Pos                              1                                                         /*!< GPIO_PORT SET7: SETP1 Position      */
#define GPIO_PORT_SET7_SETP1_Msk                              (0x01UL << GPIO_PORT_SET7_SETP1_Pos)                      /*!< GPIO_PORT SET7: SETP1 Mask          */
#define GPIO_PORT_SET7_SETP2_Pos                              2                                                         /*!< GPIO_PORT SET7: SETP2 Position      */
#define GPIO_PORT_SET7_SETP2_Msk                              (0x01UL << GPIO_PORT_SET7_SETP2_Pos)                      /*!< GPIO_PORT SET7: SETP2 Mask          */
#define GPIO_PORT_SET7_SETP3_Pos                              3                                                         /*!< GPIO_PORT SET7: SETP3 Position      */
#define GPIO_PORT_SET7_SETP3_Msk                              (0x01UL << GPIO_PORT_SET7_SETP3_Pos)                      /*!< GPIO_PORT SET7: SETP3 Mask          */
#define GPIO_PORT_SET7_SETP4_Pos                              4                                                         /*!< GPIO_PORT SET7: SETP4 Position      */
#define GPIO_PORT_SET7_SETP4_Msk                              (0x01UL << GPIO_PORT_SET7_SETP4_Pos)                      /*!< GPIO_PORT SET7: SETP4 Mask          */
#define GPIO_PORT_SET7_SETP5_Pos                              5                                                         /*!< GPIO_PORT SET7: SETP5 Position      */
#define GPIO_PORT_SET7_SETP5_Msk                              (0x01UL << GPIO_PORT_SET7_SETP5_Pos)                      /*!< GPIO_PORT SET7: SETP5 Mask          */
#define GPIO_PORT_SET7_SETP6_Pos                              6                                                         /*!< GPIO_PORT SET7: SETP6 Position      */
#define GPIO_PORT_SET7_SETP6_Msk                              (0x01UL << GPIO_PORT_SET7_SETP6_Pos)                      /*!< GPIO_PORT SET7: SETP6 Mask          */
#define GPIO_PORT_SET7_SETP7_Pos                              7                                                         /*!< GPIO_PORT SET7: SETP7 Position      */
#define GPIO_PORT_SET7_SETP7_Msk                              (0x01UL << GPIO_PORT_SET7_SETP7_Pos)                      /*!< GPIO_PORT SET7: SETP7 Mask          */
#define GPIO_PORT_SET7_SETP8_Pos                              8                                                         /*!< GPIO_PORT SET7: SETP8 Position      */
#define GPIO_PORT_SET7_SETP8_Msk                              (0x01UL << GPIO_PORT_SET7_SETP8_Pos)                      /*!< GPIO_PORT SET7: SETP8 Mask          */
#define GPIO_PORT_SET7_SETP9_Pos                              9                                                         /*!< GPIO_PORT SET7: SETP9 Position      */
#define GPIO_PORT_SET7_SETP9_Msk                              (0x01UL << GPIO_PORT_SET7_SETP9_Pos)                      /*!< GPIO_PORT SET7: SETP9 Mask          */
#define GPIO_PORT_SET7_SETP10_Pos                             10                                                        /*!< GPIO_PORT SET7: SETP10 Position     */
#define GPIO_PORT_SET7_SETP10_Msk                             (0x01UL << GPIO_PORT_SET7_SETP10_Pos)                     /*!< GPIO_PORT SET7: SETP10 Mask         */
#define GPIO_PORT_SET7_SETP11_Pos                             11                                                        /*!< GPIO_PORT SET7: SETP11 Position     */
#define GPIO_PORT_SET7_SETP11_Msk                             (0x01UL << GPIO_PORT_SET7_SETP11_Pos)                     /*!< GPIO_PORT SET7: SETP11 Mask         */
#define GPIO_PORT_SET7_SETP12_Pos                             12                                                        /*!< GPIO_PORT SET7: SETP12 Position     */
#define GPIO_PORT_SET7_SETP12_Msk                             (0x01UL << GPIO_PORT_SET7_SETP12_Pos)                     /*!< GPIO_PORT SET7: SETP12 Mask         */
#define GPIO_PORT_SET7_SETP13_Pos                             13                                                        /*!< GPIO_PORT SET7: SETP13 Position     */
#define GPIO_PORT_SET7_SETP13_Msk                             (0x01UL << GPIO_PORT_SET7_SETP13_Pos)                     /*!< GPIO_PORT SET7: SETP13 Mask         */
#define GPIO_PORT_SET7_SETP14_Pos                             14                                                        /*!< GPIO_PORT SET7: SETP14 Position     */
#define GPIO_PORT_SET7_SETP14_Msk                             (0x01UL << GPIO_PORT_SET7_SETP14_Pos)                     /*!< GPIO_PORT SET7: SETP14 Mask         */
#define GPIO_PORT_SET7_SETP15_Pos                             15                                                        /*!< GPIO_PORT SET7: SETP15 Position     */
#define GPIO_PORT_SET7_SETP15_Msk                             (0x01UL << GPIO_PORT_SET7_SETP15_Pos)                     /*!< GPIO_PORT SET7: SETP15 Mask         */
#define GPIO_PORT_SET7_SETP16_Pos                             16                                                        /*!< GPIO_PORT SET7: SETP16 Position     */
#define GPIO_PORT_SET7_SETP16_Msk                             (0x01UL << GPIO_PORT_SET7_SETP16_Pos)                     /*!< GPIO_PORT SET7: SETP16 Mask         */
#define GPIO_PORT_SET7_SETP17_Pos                             17                                                        /*!< GPIO_PORT SET7: SETP17 Position     */
#define GPIO_PORT_SET7_SETP17_Msk                             (0x01UL << GPIO_PORT_SET7_SETP17_Pos)                     /*!< GPIO_PORT SET7: SETP17 Mask         */
#define GPIO_PORT_SET7_SETP18_Pos                             18                                                        /*!< GPIO_PORT SET7: SETP18 Position     */
#define GPIO_PORT_SET7_SETP18_Msk                             (0x01UL << GPIO_PORT_SET7_SETP18_Pos)                     /*!< GPIO_PORT SET7: SETP18 Mask         */
#define GPIO_PORT_SET7_SETP19_Pos                             19                                                        /*!< GPIO_PORT SET7: SETP19 Position     */
#define GPIO_PORT_SET7_SETP19_Msk                             (0x01UL << GPIO_PORT_SET7_SETP19_Pos)                     /*!< GPIO_PORT SET7: SETP19 Mask         */
#define GPIO_PORT_SET7_SETP20_Pos                             20                                                        /*!< GPIO_PORT SET7: SETP20 Position     */
#define GPIO_PORT_SET7_SETP20_Msk                             (0x01UL << GPIO_PORT_SET7_SETP20_Pos)                     /*!< GPIO_PORT SET7: SETP20 Mask         */
#define GPIO_PORT_SET7_SETP21_Pos                             21                                                        /*!< GPIO_PORT SET7: SETP21 Position     */
#define GPIO_PORT_SET7_SETP21_Msk                             (0x01UL << GPIO_PORT_SET7_SETP21_Pos)                     /*!< GPIO_PORT SET7: SETP21 Mask         */
#define GPIO_PORT_SET7_SETP22_Pos                             22                                                        /*!< GPIO_PORT SET7: SETP22 Position     */
#define GPIO_PORT_SET7_SETP22_Msk                             (0x01UL << GPIO_PORT_SET7_SETP22_Pos)                     /*!< GPIO_PORT SET7: SETP22 Mask         */
#define GPIO_PORT_SET7_SETP23_Pos                             23                                                        /*!< GPIO_PORT SET7: SETP23 Position     */
#define GPIO_PORT_SET7_SETP23_Msk                             (0x01UL << GPIO_PORT_SET7_SETP23_Pos)                     /*!< GPIO_PORT SET7: SETP23 Mask         */
#define GPIO_PORT_SET7_SETP24_Pos                             24                                                        /*!< GPIO_PORT SET7: SETP24 Position     */
#define GPIO_PORT_SET7_SETP24_Msk                             (0x01UL << GPIO_PORT_SET7_SETP24_Pos)                     /*!< GPIO_PORT SET7: SETP24 Mask         */
#define GPIO_PORT_SET7_SETP25_Pos                             25                                                        /*!< GPIO_PORT SET7: SETP25 Position     */
#define GPIO_PORT_SET7_SETP25_Msk                             (0x01UL << GPIO_PORT_SET7_SETP25_Pos)                     /*!< GPIO_PORT SET7: SETP25 Mask         */
#define GPIO_PORT_SET7_SETP26_Pos                             26                                                        /*!< GPIO_PORT SET7: SETP26 Position     */
#define GPIO_PORT_SET7_SETP26_Msk                             (0x01UL << GPIO_PORT_SET7_SETP26_Pos)                     /*!< GPIO_PORT SET7: SETP26 Mask         */
#define GPIO_PORT_SET7_SETP27_Pos                             27                                                        /*!< GPIO_PORT SET7: SETP27 Position     */
#define GPIO_PORT_SET7_SETP27_Msk                             (0x01UL << GPIO_PORT_SET7_SETP27_Pos)                     /*!< GPIO_PORT SET7: SETP27 Mask         */
#define GPIO_PORT_SET7_SETP28_Pos                             28                                                        /*!< GPIO_PORT SET7: SETP28 Position     */
#define GPIO_PORT_SET7_SETP28_Msk                             (0x01UL << GPIO_PORT_SET7_SETP28_Pos)                     /*!< GPIO_PORT SET7: SETP28 Mask         */
#define GPIO_PORT_SET7_SETP29_Pos                             29                                                        /*!< GPIO_PORT SET7: SETP29 Position     */
#define GPIO_PORT_SET7_SETP29_Msk                             (0x01UL << GPIO_PORT_SET7_SETP29_Pos)                     /*!< GPIO_PORT SET7: SETP29 Mask         */
#define GPIO_PORT_SET7_SETP30_Pos                             30                                                        /*!< GPIO_PORT SET7: SETP30 Position     */
#define GPIO_PORT_SET7_SETP30_Msk                             (0x01UL << GPIO_PORT_SET7_SETP30_Pos)                     /*!< GPIO_PORT SET7: SETP30 Mask         */
#define GPIO_PORT_SET7_SETP31_Pos                             31                                                        /*!< GPIO_PORT SET7: SETP31 Position     */
#define GPIO_PORT_SET7_SETP31_Msk                             (0x01UL << GPIO_PORT_SET7_SETP31_Pos)                     /*!< GPIO_PORT SET7: SETP31 Mask         */

// -------------------------------------  GPIO_PORT_CLR0  -----------------------------------------
#define GPIO_PORT_CLR0_CLRP00_Pos                             0                                                         /*!< GPIO_PORT CLR0: CLRP00 Position     */
#define GPIO_PORT_CLR0_CLRP00_Msk                             (0x01UL << GPIO_PORT_CLR0_CLRP00_Pos)                     /*!< GPIO_PORT CLR0: CLRP00 Mask         */
#define GPIO_PORT_CLR0_CLRP01_Pos                             1                                                         /*!< GPIO_PORT CLR0: CLRP01 Position     */
#define GPIO_PORT_CLR0_CLRP01_Msk                             (0x01UL << GPIO_PORT_CLR0_CLRP01_Pos)                     /*!< GPIO_PORT CLR0: CLRP01 Mask         */
#define GPIO_PORT_CLR0_CLRP02_Pos                             2                                                         /*!< GPIO_PORT CLR0: CLRP02 Position     */
#define GPIO_PORT_CLR0_CLRP02_Msk                             (0x01UL << GPIO_PORT_CLR0_CLRP02_Pos)                     /*!< GPIO_PORT CLR0: CLRP02 Mask         */
#define GPIO_PORT_CLR0_CLRP03_Pos                             3                                                         /*!< GPIO_PORT CLR0: CLRP03 Position     */
#define GPIO_PORT_CLR0_CLRP03_Msk                             (0x01UL << GPIO_PORT_CLR0_CLRP03_Pos)                     /*!< GPIO_PORT CLR0: CLRP03 Mask         */
#define GPIO_PORT_CLR0_CLRP04_Pos                             4                                                         /*!< GPIO_PORT CLR0: CLRP04 Position     */
#define GPIO_PORT_CLR0_CLRP04_Msk                             (0x01UL << GPIO_PORT_CLR0_CLRP04_Pos)                     /*!< GPIO_PORT CLR0: CLRP04 Mask         */
#define GPIO_PORT_CLR0_CLRP05_Pos                             5                                                         /*!< GPIO_PORT CLR0: CLRP05 Position     */
#define GPIO_PORT_CLR0_CLRP05_Msk                             (0x01UL << GPIO_PORT_CLR0_CLRP05_Pos)                     /*!< GPIO_PORT CLR0: CLRP05 Mask         */
#define GPIO_PORT_CLR0_CLRP06_Pos                             6                                                         /*!< GPIO_PORT CLR0: CLRP06 Position     */
#define GPIO_PORT_CLR0_CLRP06_Msk                             (0x01UL << GPIO_PORT_CLR0_CLRP06_Pos)                     /*!< GPIO_PORT CLR0: CLRP06 Mask         */
#define GPIO_PORT_CLR0_CLRP07_Pos                             7                                                         /*!< GPIO_PORT CLR0: CLRP07 Position     */
#define GPIO_PORT_CLR0_CLRP07_Msk                             (0x01UL << GPIO_PORT_CLR0_CLRP07_Pos)                     /*!< GPIO_PORT CLR0: CLRP07 Mask         */
#define GPIO_PORT_CLR0_CLRP08_Pos                             8                                                         /*!< GPIO_PORT CLR0: CLRP08 Position     */
#define GPIO_PORT_CLR0_CLRP08_Msk                             (0x01UL << GPIO_PORT_CLR0_CLRP08_Pos)                     /*!< GPIO_PORT CLR0: CLRP08 Mask         */
#define GPIO_PORT_CLR0_CLRP09_Pos                             9                                                         /*!< GPIO_PORT CLR0: CLRP09 Position     */
#define GPIO_PORT_CLR0_CLRP09_Msk                             (0x01UL << GPIO_PORT_CLR0_CLRP09_Pos)                     /*!< GPIO_PORT CLR0: CLRP09 Mask         */
#define GPIO_PORT_CLR0_CLRP010_Pos                            10                                                        /*!< GPIO_PORT CLR0: CLRP010 Position    */
#define GPIO_PORT_CLR0_CLRP010_Msk                            (0x01UL << GPIO_PORT_CLR0_CLRP010_Pos)                    /*!< GPIO_PORT CLR0: CLRP010 Mask        */
#define GPIO_PORT_CLR0_CLRP011_Pos                            11                                                        /*!< GPIO_PORT CLR0: CLRP011 Position    */
#define GPIO_PORT_CLR0_CLRP011_Msk                            (0x01UL << GPIO_PORT_CLR0_CLRP011_Pos)                    /*!< GPIO_PORT CLR0: CLRP011 Mask        */
#define GPIO_PORT_CLR0_CLRP012_Pos                            12                                                        /*!< GPIO_PORT CLR0: CLRP012 Position    */
#define GPIO_PORT_CLR0_CLRP012_Msk                            (0x01UL << GPIO_PORT_CLR0_CLRP012_Pos)                    /*!< GPIO_PORT CLR0: CLRP012 Mask        */
#define GPIO_PORT_CLR0_CLRP013_Pos                            13                                                        /*!< GPIO_PORT CLR0: CLRP013 Position    */
#define GPIO_PORT_CLR0_CLRP013_Msk                            (0x01UL << GPIO_PORT_CLR0_CLRP013_Pos)                    /*!< GPIO_PORT CLR0: CLRP013 Mask        */
#define GPIO_PORT_CLR0_CLRP014_Pos                            14                                                        /*!< GPIO_PORT CLR0: CLRP014 Position    */
#define GPIO_PORT_CLR0_CLRP014_Msk                            (0x01UL << GPIO_PORT_CLR0_CLRP014_Pos)                    /*!< GPIO_PORT CLR0: CLRP014 Mask        */
#define GPIO_PORT_CLR0_CLRP015_Pos                            15                                                        /*!< GPIO_PORT CLR0: CLRP015 Position    */
#define GPIO_PORT_CLR0_CLRP015_Msk                            (0x01UL << GPIO_PORT_CLR0_CLRP015_Pos)                    /*!< GPIO_PORT CLR0: CLRP015 Mask        */
#define GPIO_PORT_CLR0_CLRP016_Pos                            16                                                        /*!< GPIO_PORT CLR0: CLRP016 Position    */
#define GPIO_PORT_CLR0_CLRP016_Msk                            (0x01UL << GPIO_PORT_CLR0_CLRP016_Pos)                    /*!< GPIO_PORT CLR0: CLRP016 Mask        */
#define GPIO_PORT_CLR0_CLRP017_Pos                            17                                                        /*!< GPIO_PORT CLR0: CLRP017 Position    */
#define GPIO_PORT_CLR0_CLRP017_Msk                            (0x01UL << GPIO_PORT_CLR0_CLRP017_Pos)                    /*!< GPIO_PORT CLR0: CLRP017 Mask        */
#define GPIO_PORT_CLR0_CLRP018_Pos                            18                                                        /*!< GPIO_PORT CLR0: CLRP018 Position    */
#define GPIO_PORT_CLR0_CLRP018_Msk                            (0x01UL << GPIO_PORT_CLR0_CLRP018_Pos)                    /*!< GPIO_PORT CLR0: CLRP018 Mask        */
#define GPIO_PORT_CLR0_CLRP019_Pos                            19                                                        /*!< GPIO_PORT CLR0: CLRP019 Position    */
#define GPIO_PORT_CLR0_CLRP019_Msk                            (0x01UL << GPIO_PORT_CLR0_CLRP019_Pos)                    /*!< GPIO_PORT CLR0: CLRP019 Mask        */
#define GPIO_PORT_CLR0_CLRP020_Pos                            20                                                        /*!< GPIO_PORT CLR0: CLRP020 Position    */
#define GPIO_PORT_CLR0_CLRP020_Msk                            (0x01UL << GPIO_PORT_CLR0_CLRP020_Pos)                    /*!< GPIO_PORT CLR0: CLRP020 Mask        */
#define GPIO_PORT_CLR0_CLRP021_Pos                            21                                                        /*!< GPIO_PORT CLR0: CLRP021 Position    */
#define GPIO_PORT_CLR0_CLRP021_Msk                            (0x01UL << GPIO_PORT_CLR0_CLRP021_Pos)                    /*!< GPIO_PORT CLR0: CLRP021 Mask        */
#define GPIO_PORT_CLR0_CLRP022_Pos                            22                                                        /*!< GPIO_PORT CLR0: CLRP022 Position    */
#define GPIO_PORT_CLR0_CLRP022_Msk                            (0x01UL << GPIO_PORT_CLR0_CLRP022_Pos)                    /*!< GPIO_PORT CLR0: CLRP022 Mask        */
#define GPIO_PORT_CLR0_CLRP023_Pos                            23                                                        /*!< GPIO_PORT CLR0: CLRP023 Position    */
#define GPIO_PORT_CLR0_CLRP023_Msk                            (0x01UL << GPIO_PORT_CLR0_CLRP023_Pos)                    /*!< GPIO_PORT CLR0: CLRP023 Mask        */
#define GPIO_PORT_CLR0_CLRP024_Pos                            24                                                        /*!< GPIO_PORT CLR0: CLRP024 Position    */
#define GPIO_PORT_CLR0_CLRP024_Msk                            (0x01UL << GPIO_PORT_CLR0_CLRP024_Pos)                    /*!< GPIO_PORT CLR0: CLRP024 Mask        */
#define GPIO_PORT_CLR0_CLRP025_Pos                            25                                                        /*!< GPIO_PORT CLR0: CLRP025 Position    */
#define GPIO_PORT_CLR0_CLRP025_Msk                            (0x01UL << GPIO_PORT_CLR0_CLRP025_Pos)                    /*!< GPIO_PORT CLR0: CLRP025 Mask        */
#define GPIO_PORT_CLR0_CLRP026_Pos                            26                                                        /*!< GPIO_PORT CLR0: CLRP026 Position    */
#define GPIO_PORT_CLR0_CLRP026_Msk                            (0x01UL << GPIO_PORT_CLR0_CLRP026_Pos)                    /*!< GPIO_PORT CLR0: CLRP026 Mask        */
#define GPIO_PORT_CLR0_CLRP027_Pos                            27                                                        /*!< GPIO_PORT CLR0: CLRP027 Position    */
#define GPIO_PORT_CLR0_CLRP027_Msk                            (0x01UL << GPIO_PORT_CLR0_CLRP027_Pos)                    /*!< GPIO_PORT CLR0: CLRP027 Mask        */
#define GPIO_PORT_CLR0_CLRP028_Pos                            28                                                        /*!< GPIO_PORT CLR0: CLRP028 Position    */
#define GPIO_PORT_CLR0_CLRP028_Msk                            (0x01UL << GPIO_PORT_CLR0_CLRP028_Pos)                    /*!< GPIO_PORT CLR0: CLRP028 Mask        */
#define GPIO_PORT_CLR0_CLRP029_Pos                            29                                                        /*!< GPIO_PORT CLR0: CLRP029 Position    */
#define GPIO_PORT_CLR0_CLRP029_Msk                            (0x01UL << GPIO_PORT_CLR0_CLRP029_Pos)                    /*!< GPIO_PORT CLR0: CLRP029 Mask        */
#define GPIO_PORT_CLR0_CLRP030_Pos                            30                                                        /*!< GPIO_PORT CLR0: CLRP030 Position    */
#define GPIO_PORT_CLR0_CLRP030_Msk                            (0x01UL << GPIO_PORT_CLR0_CLRP030_Pos)                    /*!< GPIO_PORT CLR0: CLRP030 Mask        */
#define GPIO_PORT_CLR0_CLRP031_Pos                            31                                                        /*!< GPIO_PORT CLR0: CLRP031 Position    */
#define GPIO_PORT_CLR0_CLRP031_Msk                            (0x01UL << GPIO_PORT_CLR0_CLRP031_Pos)                    /*!< GPIO_PORT CLR0: CLRP031 Mask        */

// -------------------------------------  GPIO_PORT_CLR1  -----------------------------------------
#define GPIO_PORT_CLR1_CLRP00_Pos                             0                                                         /*!< GPIO_PORT CLR1: CLRP00 Position     */
#define GPIO_PORT_CLR1_CLRP00_Msk                             (0x01UL << GPIO_PORT_CLR1_CLRP00_Pos)                     /*!< GPIO_PORT CLR1: CLRP00 Mask         */
#define GPIO_PORT_CLR1_CLRP01_Pos                             1                                                         /*!< GPIO_PORT CLR1: CLRP01 Position     */
#define GPIO_PORT_CLR1_CLRP01_Msk                             (0x01UL << GPIO_PORT_CLR1_CLRP01_Pos)                     /*!< GPIO_PORT CLR1: CLRP01 Mask         */
#define GPIO_PORT_CLR1_CLRP02_Pos                             2                                                         /*!< GPIO_PORT CLR1: CLRP02 Position     */
#define GPIO_PORT_CLR1_CLRP02_Msk                             (0x01UL << GPIO_PORT_CLR1_CLRP02_Pos)                     /*!< GPIO_PORT CLR1: CLRP02 Mask         */
#define GPIO_PORT_CLR1_CLRP03_Pos                             3                                                         /*!< GPIO_PORT CLR1: CLRP03 Position     */
#define GPIO_PORT_CLR1_CLRP03_Msk                             (0x01UL << GPIO_PORT_CLR1_CLRP03_Pos)                     /*!< GPIO_PORT CLR1: CLRP03 Mask         */
#define GPIO_PORT_CLR1_CLRP04_Pos                             4                                                         /*!< GPIO_PORT CLR1: CLRP04 Position     */
#define GPIO_PORT_CLR1_CLRP04_Msk                             (0x01UL << GPIO_PORT_CLR1_CLRP04_Pos)                     /*!< GPIO_PORT CLR1: CLRP04 Mask         */
#define GPIO_PORT_CLR1_CLRP05_Pos                             5                                                         /*!< GPIO_PORT CLR1: CLRP05 Position     */
#define GPIO_PORT_CLR1_CLRP05_Msk                             (0x01UL << GPIO_PORT_CLR1_CLRP05_Pos)                     /*!< GPIO_PORT CLR1: CLRP05 Mask         */
#define GPIO_PORT_CLR1_CLRP06_Pos                             6                                                         /*!< GPIO_PORT CLR1: CLRP06 Position     */
#define GPIO_PORT_CLR1_CLRP06_Msk                             (0x01UL << GPIO_PORT_CLR1_CLRP06_Pos)                     /*!< GPIO_PORT CLR1: CLRP06 Mask         */
#define GPIO_PORT_CLR1_CLRP07_Pos                             7                                                         /*!< GPIO_PORT CLR1: CLRP07 Position     */
#define GPIO_PORT_CLR1_CLRP07_Msk                             (0x01UL << GPIO_PORT_CLR1_CLRP07_Pos)                     /*!< GPIO_PORT CLR1: CLRP07 Mask         */
#define GPIO_PORT_CLR1_CLRP08_Pos                             8                                                         /*!< GPIO_PORT CLR1: CLRP08 Position     */
#define GPIO_PORT_CLR1_CLRP08_Msk                             (0x01UL << GPIO_PORT_CLR1_CLRP08_Pos)                     /*!< GPIO_PORT CLR1: CLRP08 Mask         */
#define GPIO_PORT_CLR1_CLRP09_Pos                             9                                                         /*!< GPIO_PORT CLR1: CLRP09 Position     */
#define GPIO_PORT_CLR1_CLRP09_Msk                             (0x01UL << GPIO_PORT_CLR1_CLRP09_Pos)                     /*!< GPIO_PORT CLR1: CLRP09 Mask         */
#define GPIO_PORT_CLR1_CLRP010_Pos                            10                                                        /*!< GPIO_PORT CLR1: CLRP010 Position    */
#define GPIO_PORT_CLR1_CLRP010_Msk                            (0x01UL << GPIO_PORT_CLR1_CLRP010_Pos)                    /*!< GPIO_PORT CLR1: CLRP010 Mask        */
#define GPIO_PORT_CLR1_CLRP011_Pos                            11                                                        /*!< GPIO_PORT CLR1: CLRP011 Position    */
#define GPIO_PORT_CLR1_CLRP011_Msk                            (0x01UL << GPIO_PORT_CLR1_CLRP011_Pos)                    /*!< GPIO_PORT CLR1: CLRP011 Mask        */
#define GPIO_PORT_CLR1_CLRP012_Pos                            12                                                        /*!< GPIO_PORT CLR1: CLRP012 Position    */
#define GPIO_PORT_CLR1_CLRP012_Msk                            (0x01UL << GPIO_PORT_CLR1_CLRP012_Pos)                    /*!< GPIO_PORT CLR1: CLRP012 Mask        */
#define GPIO_PORT_CLR1_CLRP013_Pos                            13                                                        /*!< GPIO_PORT CLR1: CLRP013 Position    */
#define GPIO_PORT_CLR1_CLRP013_Msk                            (0x01UL << GPIO_PORT_CLR1_CLRP013_Pos)                    /*!< GPIO_PORT CLR1: CLRP013 Mask        */
#define GPIO_PORT_CLR1_CLRP014_Pos                            14                                                        /*!< GPIO_PORT CLR1: CLRP014 Position    */
#define GPIO_PORT_CLR1_CLRP014_Msk                            (0x01UL << GPIO_PORT_CLR1_CLRP014_Pos)                    /*!< GPIO_PORT CLR1: CLRP014 Mask        */
#define GPIO_PORT_CLR1_CLRP015_Pos                            15                                                        /*!< GPIO_PORT CLR1: CLRP015 Position    */
#define GPIO_PORT_CLR1_CLRP015_Msk                            (0x01UL << GPIO_PORT_CLR1_CLRP015_Pos)                    /*!< GPIO_PORT CLR1: CLRP015 Mask        */
#define GPIO_PORT_CLR1_CLRP016_Pos                            16                                                        /*!< GPIO_PORT CLR1: CLRP016 Position    */
#define GPIO_PORT_CLR1_CLRP016_Msk                            (0x01UL << GPIO_PORT_CLR1_CLRP016_Pos)                    /*!< GPIO_PORT CLR1: CLRP016 Mask        */
#define GPIO_PORT_CLR1_CLRP017_Pos                            17                                                        /*!< GPIO_PORT CLR1: CLRP017 Position    */
#define GPIO_PORT_CLR1_CLRP017_Msk                            (0x01UL << GPIO_PORT_CLR1_CLRP017_Pos)                    /*!< GPIO_PORT CLR1: CLRP017 Mask        */
#define GPIO_PORT_CLR1_CLRP018_Pos                            18                                                        /*!< GPIO_PORT CLR1: CLRP018 Position    */
#define GPIO_PORT_CLR1_CLRP018_Msk                            (0x01UL << GPIO_PORT_CLR1_CLRP018_Pos)                    /*!< GPIO_PORT CLR1: CLRP018 Mask        */
#define GPIO_PORT_CLR1_CLRP019_Pos                            19                                                        /*!< GPIO_PORT CLR1: CLRP019 Position    */
#define GPIO_PORT_CLR1_CLRP019_Msk                            (0x01UL << GPIO_PORT_CLR1_CLRP019_Pos)                    /*!< GPIO_PORT CLR1: CLRP019 Mask        */
#define GPIO_PORT_CLR1_CLRP020_Pos                            20                                                        /*!< GPIO_PORT CLR1: CLRP020 Position    */
#define GPIO_PORT_CLR1_CLRP020_Msk                            (0x01UL << GPIO_PORT_CLR1_CLRP020_Pos)                    /*!< GPIO_PORT CLR1: CLRP020 Mask        */
#define GPIO_PORT_CLR1_CLRP021_Pos                            21                                                        /*!< GPIO_PORT CLR1: CLRP021 Position    */
#define GPIO_PORT_CLR1_CLRP021_Msk                            (0x01UL << GPIO_PORT_CLR1_CLRP021_Pos)                    /*!< GPIO_PORT CLR1: CLRP021 Mask        */
#define GPIO_PORT_CLR1_CLRP022_Pos                            22                                                        /*!< GPIO_PORT CLR1: CLRP022 Position    */
#define GPIO_PORT_CLR1_CLRP022_Msk                            (0x01UL << GPIO_PORT_CLR1_CLRP022_Pos)                    /*!< GPIO_PORT CLR1: CLRP022 Mask        */
#define GPIO_PORT_CLR1_CLRP023_Pos                            23                                                        /*!< GPIO_PORT CLR1: CLRP023 Position    */
#define GPIO_PORT_CLR1_CLRP023_Msk                            (0x01UL << GPIO_PORT_CLR1_CLRP023_Pos)                    /*!< GPIO_PORT CLR1: CLRP023 Mask        */
#define GPIO_PORT_CLR1_CLRP024_Pos                            24                                                        /*!< GPIO_PORT CLR1: CLRP024 Position    */
#define GPIO_PORT_CLR1_CLRP024_Msk                            (0x01UL << GPIO_PORT_CLR1_CLRP024_Pos)                    /*!< GPIO_PORT CLR1: CLRP024 Mask        */
#define GPIO_PORT_CLR1_CLRP025_Pos                            25                                                        /*!< GPIO_PORT CLR1: CLRP025 Position    */
#define GPIO_PORT_CLR1_CLRP025_Msk                            (0x01UL << GPIO_PORT_CLR1_CLRP025_Pos)                    /*!< GPIO_PORT CLR1: CLRP025 Mask        */
#define GPIO_PORT_CLR1_CLRP026_Pos                            26                                                        /*!< GPIO_PORT CLR1: CLRP026 Position    */
#define GPIO_PORT_CLR1_CLRP026_Msk                            (0x01UL << GPIO_PORT_CLR1_CLRP026_Pos)                    /*!< GPIO_PORT CLR1: CLRP026 Mask        */
#define GPIO_PORT_CLR1_CLRP027_Pos                            27                                                        /*!< GPIO_PORT CLR1: CLRP027 Position    */
#define GPIO_PORT_CLR1_CLRP027_Msk                            (0x01UL << GPIO_PORT_CLR1_CLRP027_Pos)                    /*!< GPIO_PORT CLR1: CLRP027 Mask        */
#define GPIO_PORT_CLR1_CLRP028_Pos                            28                                                        /*!< GPIO_PORT CLR1: CLRP028 Position    */
#define GPIO_PORT_CLR1_CLRP028_Msk                            (0x01UL << GPIO_PORT_CLR1_CLRP028_Pos)                    /*!< GPIO_PORT CLR1: CLRP028 Mask        */
#define GPIO_PORT_CLR1_CLRP029_Pos                            29                                                        /*!< GPIO_PORT CLR1: CLRP029 Position    */
#define GPIO_PORT_CLR1_CLRP029_Msk                            (0x01UL << GPIO_PORT_CLR1_CLRP029_Pos)                    /*!< GPIO_PORT CLR1: CLRP029 Mask        */
#define GPIO_PORT_CLR1_CLRP030_Pos                            30                                                        /*!< GPIO_PORT CLR1: CLRP030 Position    */
#define GPIO_PORT_CLR1_CLRP030_Msk                            (0x01UL << GPIO_PORT_CLR1_CLRP030_Pos)                    /*!< GPIO_PORT CLR1: CLRP030 Mask        */
#define GPIO_PORT_CLR1_CLRP031_Pos                            31                                                        /*!< GPIO_PORT CLR1: CLRP031 Position    */
#define GPIO_PORT_CLR1_CLRP031_Msk                            (0x01UL << GPIO_PORT_CLR1_CLRP031_Pos)                    /*!< GPIO_PORT CLR1: CLRP031 Mask        */

// -------------------------------------  GPIO_PORT_CLR2  -----------------------------------------
#define GPIO_PORT_CLR2_CLRP00_Pos                             0                                                         /*!< GPIO_PORT CLR2: CLRP00 Position     */
#define GPIO_PORT_CLR2_CLRP00_Msk                             (0x01UL << GPIO_PORT_CLR2_CLRP00_Pos)                     /*!< GPIO_PORT CLR2: CLRP00 Mask         */
#define GPIO_PORT_CLR2_CLRP01_Pos                             1                                                         /*!< GPIO_PORT CLR2: CLRP01 Position     */
#define GPIO_PORT_CLR2_CLRP01_Msk                             (0x01UL << GPIO_PORT_CLR2_CLRP01_Pos)                     /*!< GPIO_PORT CLR2: CLRP01 Mask         */
#define GPIO_PORT_CLR2_CLRP02_Pos                             2                                                         /*!< GPIO_PORT CLR2: CLRP02 Position     */
#define GPIO_PORT_CLR2_CLRP02_Msk                             (0x01UL << GPIO_PORT_CLR2_CLRP02_Pos)                     /*!< GPIO_PORT CLR2: CLRP02 Mask         */
#define GPIO_PORT_CLR2_CLRP03_Pos                             3                                                         /*!< GPIO_PORT CLR2: CLRP03 Position     */
#define GPIO_PORT_CLR2_CLRP03_Msk                             (0x01UL << GPIO_PORT_CLR2_CLRP03_Pos)                     /*!< GPIO_PORT CLR2: CLRP03 Mask         */
#define GPIO_PORT_CLR2_CLRP04_Pos                             4                                                         /*!< GPIO_PORT CLR2: CLRP04 Position     */
#define GPIO_PORT_CLR2_CLRP04_Msk                             (0x01UL << GPIO_PORT_CLR2_CLRP04_Pos)                     /*!< GPIO_PORT CLR2: CLRP04 Mask         */
#define GPIO_PORT_CLR2_CLRP05_Pos                             5                                                         /*!< GPIO_PORT CLR2: CLRP05 Position     */
#define GPIO_PORT_CLR2_CLRP05_Msk                             (0x01UL << GPIO_PORT_CLR2_CLRP05_Pos)                     /*!< GPIO_PORT CLR2: CLRP05 Mask         */
#define GPIO_PORT_CLR2_CLRP06_Pos                             6                                                         /*!< GPIO_PORT CLR2: CLRP06 Position     */
#define GPIO_PORT_CLR2_CLRP06_Msk                             (0x01UL << GPIO_PORT_CLR2_CLRP06_Pos)                     /*!< GPIO_PORT CLR2: CLRP06 Mask         */
#define GPIO_PORT_CLR2_CLRP07_Pos                             7                                                         /*!< GPIO_PORT CLR2: CLRP07 Position     */
#define GPIO_PORT_CLR2_CLRP07_Msk                             (0x01UL << GPIO_PORT_CLR2_CLRP07_Pos)                     /*!< GPIO_PORT CLR2: CLRP07 Mask         */
#define GPIO_PORT_CLR2_CLRP08_Pos                             8                                                         /*!< GPIO_PORT CLR2: CLRP08 Position     */
#define GPIO_PORT_CLR2_CLRP08_Msk                             (0x01UL << GPIO_PORT_CLR2_CLRP08_Pos)                     /*!< GPIO_PORT CLR2: CLRP08 Mask         */
#define GPIO_PORT_CLR2_CLRP09_Pos                             9                                                         /*!< GPIO_PORT CLR2: CLRP09 Position     */
#define GPIO_PORT_CLR2_CLRP09_Msk                             (0x01UL << GPIO_PORT_CLR2_CLRP09_Pos)                     /*!< GPIO_PORT CLR2: CLRP09 Mask         */
#define GPIO_PORT_CLR2_CLRP010_Pos                            10                                                        /*!< GPIO_PORT CLR2: CLRP010 Position    */
#define GPIO_PORT_CLR2_CLRP010_Msk                            (0x01UL << GPIO_PORT_CLR2_CLRP010_Pos)                    /*!< GPIO_PORT CLR2: CLRP010 Mask        */
#define GPIO_PORT_CLR2_CLRP011_Pos                            11                                                        /*!< GPIO_PORT CLR2: CLRP011 Position    */
#define GPIO_PORT_CLR2_CLRP011_Msk                            (0x01UL << GPIO_PORT_CLR2_CLRP011_Pos)                    /*!< GPIO_PORT CLR2: CLRP011 Mask        */
#define GPIO_PORT_CLR2_CLRP012_Pos                            12                                                        /*!< GPIO_PORT CLR2: CLRP012 Position    */
#define GPIO_PORT_CLR2_CLRP012_Msk                            (0x01UL << GPIO_PORT_CLR2_CLRP012_Pos)                    /*!< GPIO_PORT CLR2: CLRP012 Mask        */
#define GPIO_PORT_CLR2_CLRP013_Pos                            13                                                        /*!< GPIO_PORT CLR2: CLRP013 Position    */
#define GPIO_PORT_CLR2_CLRP013_Msk                            (0x01UL << GPIO_PORT_CLR2_CLRP013_Pos)                    /*!< GPIO_PORT CLR2: CLRP013 Mask        */
#define GPIO_PORT_CLR2_CLRP014_Pos                            14                                                        /*!< GPIO_PORT CLR2: CLRP014 Position    */
#define GPIO_PORT_CLR2_CLRP014_Msk                            (0x01UL << GPIO_PORT_CLR2_CLRP014_Pos)                    /*!< GPIO_PORT CLR2: CLRP014 Mask        */
#define GPIO_PORT_CLR2_CLRP015_Pos                            15                                                        /*!< GPIO_PORT CLR2: CLRP015 Position    */
#define GPIO_PORT_CLR2_CLRP015_Msk                            (0x01UL << GPIO_PORT_CLR2_CLRP015_Pos)                    /*!< GPIO_PORT CLR2: CLRP015 Mask        */
#define GPIO_PORT_CLR2_CLRP016_Pos                            16                                                        /*!< GPIO_PORT CLR2: CLRP016 Position    */
#define GPIO_PORT_CLR2_CLRP016_Msk                            (0x01UL << GPIO_PORT_CLR2_CLRP016_Pos)                    /*!< GPIO_PORT CLR2: CLRP016 Mask        */
#define GPIO_PORT_CLR2_CLRP017_Pos                            17                                                        /*!< GPIO_PORT CLR2: CLRP017 Position    */
#define GPIO_PORT_CLR2_CLRP017_Msk                            (0x01UL << GPIO_PORT_CLR2_CLRP017_Pos)                    /*!< GPIO_PORT CLR2: CLRP017 Mask        */
#define GPIO_PORT_CLR2_CLRP018_Pos                            18                                                        /*!< GPIO_PORT CLR2: CLRP018 Position    */
#define GPIO_PORT_CLR2_CLRP018_Msk                            (0x01UL << GPIO_PORT_CLR2_CLRP018_Pos)                    /*!< GPIO_PORT CLR2: CLRP018 Mask        */
#define GPIO_PORT_CLR2_CLRP019_Pos                            19                                                        /*!< GPIO_PORT CLR2: CLRP019 Position    */
#define GPIO_PORT_CLR2_CLRP019_Msk                            (0x01UL << GPIO_PORT_CLR2_CLRP019_Pos)                    /*!< GPIO_PORT CLR2: CLRP019 Mask        */
#define GPIO_PORT_CLR2_CLRP020_Pos                            20                                                        /*!< GPIO_PORT CLR2: CLRP020 Position    */
#define GPIO_PORT_CLR2_CLRP020_Msk                            (0x01UL << GPIO_PORT_CLR2_CLRP020_Pos)                    /*!< GPIO_PORT CLR2: CLRP020 Mask        */
#define GPIO_PORT_CLR2_CLRP021_Pos                            21                                                        /*!< GPIO_PORT CLR2: CLRP021 Position    */
#define GPIO_PORT_CLR2_CLRP021_Msk                            (0x01UL << GPIO_PORT_CLR2_CLRP021_Pos)                    /*!< GPIO_PORT CLR2: CLRP021 Mask        */
#define GPIO_PORT_CLR2_CLRP022_Pos                            22                                                        /*!< GPIO_PORT CLR2: CLRP022 Position    */
#define GPIO_PORT_CLR2_CLRP022_Msk                            (0x01UL << GPIO_PORT_CLR2_CLRP022_Pos)                    /*!< GPIO_PORT CLR2: CLRP022 Mask        */
#define GPIO_PORT_CLR2_CLRP023_Pos                            23                                                        /*!< GPIO_PORT CLR2: CLRP023 Position    */
#define GPIO_PORT_CLR2_CLRP023_Msk                            (0x01UL << GPIO_PORT_CLR2_CLRP023_Pos)                    /*!< GPIO_PORT CLR2: CLRP023 Mask        */
#define GPIO_PORT_CLR2_CLRP024_Pos                            24                                                        /*!< GPIO_PORT CLR2: CLRP024 Position    */
#define GPIO_PORT_CLR2_CLRP024_Msk                            (0x01UL << GPIO_PORT_CLR2_CLRP024_Pos)                    /*!< GPIO_PORT CLR2: CLRP024 Mask        */
#define GPIO_PORT_CLR2_CLRP025_Pos                            25                                                        /*!< GPIO_PORT CLR2: CLRP025 Position    */
#define GPIO_PORT_CLR2_CLRP025_Msk                            (0x01UL << GPIO_PORT_CLR2_CLRP025_Pos)                    /*!< GPIO_PORT CLR2: CLRP025 Mask        */
#define GPIO_PORT_CLR2_CLRP026_Pos                            26                                                        /*!< GPIO_PORT CLR2: CLRP026 Position    */
#define GPIO_PORT_CLR2_CLRP026_Msk                            (0x01UL << GPIO_PORT_CLR2_CLRP026_Pos)                    /*!< GPIO_PORT CLR2: CLRP026 Mask        */
#define GPIO_PORT_CLR2_CLRP027_Pos                            27                                                        /*!< GPIO_PORT CLR2: CLRP027 Position    */
#define GPIO_PORT_CLR2_CLRP027_Msk                            (0x01UL << GPIO_PORT_CLR2_CLRP027_Pos)                    /*!< GPIO_PORT CLR2: CLRP027 Mask        */
#define GPIO_PORT_CLR2_CLRP028_Pos                            28                                                        /*!< GPIO_PORT CLR2: CLRP028 Position    */
#define GPIO_PORT_CLR2_CLRP028_Msk                            (0x01UL << GPIO_PORT_CLR2_CLRP028_Pos)                    /*!< GPIO_PORT CLR2: CLRP028 Mask        */
#define GPIO_PORT_CLR2_CLRP029_Pos                            29                                                        /*!< GPIO_PORT CLR2: CLRP029 Position    */
#define GPIO_PORT_CLR2_CLRP029_Msk                            (0x01UL << GPIO_PORT_CLR2_CLRP029_Pos)                    /*!< GPIO_PORT CLR2: CLRP029 Mask        */
#define GPIO_PORT_CLR2_CLRP030_Pos                            30                                                        /*!< GPIO_PORT CLR2: CLRP030 Position    */
#define GPIO_PORT_CLR2_CLRP030_Msk                            (0x01UL << GPIO_PORT_CLR2_CLRP030_Pos)                    /*!< GPIO_PORT CLR2: CLRP030 Mask        */
#define GPIO_PORT_CLR2_CLRP031_Pos                            31                                                        /*!< GPIO_PORT CLR2: CLRP031 Position    */
#define GPIO_PORT_CLR2_CLRP031_Msk                            (0x01UL << GPIO_PORT_CLR2_CLRP031_Pos)                    /*!< GPIO_PORT CLR2: CLRP031 Mask        */

// -------------------------------------  GPIO_PORT_CLR3  -----------------------------------------
#define GPIO_PORT_CLR3_CLRP00_Pos                             0                                                         /*!< GPIO_PORT CLR3: CLRP00 Position     */
#define GPIO_PORT_CLR3_CLRP00_Msk                             (0x01UL << GPIO_PORT_CLR3_CLRP00_Pos)                     /*!< GPIO_PORT CLR3: CLRP00 Mask         */
#define GPIO_PORT_CLR3_CLRP01_Pos                             1                                                         /*!< GPIO_PORT CLR3: CLRP01 Position     */
#define GPIO_PORT_CLR3_CLRP01_Msk                             (0x01UL << GPIO_PORT_CLR3_CLRP01_Pos)                     /*!< GPIO_PORT CLR3: CLRP01 Mask         */
#define GPIO_PORT_CLR3_CLRP02_Pos                             2                                                         /*!< GPIO_PORT CLR3: CLRP02 Position     */
#define GPIO_PORT_CLR3_CLRP02_Msk                             (0x01UL << GPIO_PORT_CLR3_CLRP02_Pos)                     /*!< GPIO_PORT CLR3: CLRP02 Mask         */
#define GPIO_PORT_CLR3_CLRP03_Pos                             3                                                         /*!< GPIO_PORT CLR3: CLRP03 Position     */
#define GPIO_PORT_CLR3_CLRP03_Msk                             (0x01UL << GPIO_PORT_CLR3_CLRP03_Pos)                     /*!< GPIO_PORT CLR3: CLRP03 Mask         */
#define GPIO_PORT_CLR3_CLRP04_Pos                             4                                                         /*!< GPIO_PORT CLR3: CLRP04 Position     */
#define GPIO_PORT_CLR3_CLRP04_Msk                             (0x01UL << GPIO_PORT_CLR3_CLRP04_Pos)                     /*!< GPIO_PORT CLR3: CLRP04 Mask         */
#define GPIO_PORT_CLR3_CLRP05_Pos                             5                                                         /*!< GPIO_PORT CLR3: CLRP05 Position     */
#define GPIO_PORT_CLR3_CLRP05_Msk                             (0x01UL << GPIO_PORT_CLR3_CLRP05_Pos)                     /*!< GPIO_PORT CLR3: CLRP05 Mask         */
#define GPIO_PORT_CLR3_CLRP06_Pos                             6                                                         /*!< GPIO_PORT CLR3: CLRP06 Position     */
#define GPIO_PORT_CLR3_CLRP06_Msk                             (0x01UL << GPIO_PORT_CLR3_CLRP06_Pos)                     /*!< GPIO_PORT CLR3: CLRP06 Mask         */
#define GPIO_PORT_CLR3_CLRP07_Pos                             7                                                         /*!< GPIO_PORT CLR3: CLRP07 Position     */
#define GPIO_PORT_CLR3_CLRP07_Msk                             (0x01UL << GPIO_PORT_CLR3_CLRP07_Pos)                     /*!< GPIO_PORT CLR3: CLRP07 Mask         */
#define GPIO_PORT_CLR3_CLRP08_Pos                             8                                                         /*!< GPIO_PORT CLR3: CLRP08 Position     */
#define GPIO_PORT_CLR3_CLRP08_Msk                             (0x01UL << GPIO_PORT_CLR3_CLRP08_Pos)                     /*!< GPIO_PORT CLR3: CLRP08 Mask         */
#define GPIO_PORT_CLR3_CLRP09_Pos                             9                                                         /*!< GPIO_PORT CLR3: CLRP09 Position     */
#define GPIO_PORT_CLR3_CLRP09_Msk                             (0x01UL << GPIO_PORT_CLR3_CLRP09_Pos)                     /*!< GPIO_PORT CLR3: CLRP09 Mask         */
#define GPIO_PORT_CLR3_CLRP010_Pos                            10                                                        /*!< GPIO_PORT CLR3: CLRP010 Position    */
#define GPIO_PORT_CLR3_CLRP010_Msk                            (0x01UL << GPIO_PORT_CLR3_CLRP010_Pos)                    /*!< GPIO_PORT CLR3: CLRP010 Mask        */
#define GPIO_PORT_CLR3_CLRP011_Pos                            11                                                        /*!< GPIO_PORT CLR3: CLRP011 Position    */
#define GPIO_PORT_CLR3_CLRP011_Msk                            (0x01UL << GPIO_PORT_CLR3_CLRP011_Pos)                    /*!< GPIO_PORT CLR3: CLRP011 Mask        */
#define GPIO_PORT_CLR3_CLRP012_Pos                            12                                                        /*!< GPIO_PORT CLR3: CLRP012 Position    */
#define GPIO_PORT_CLR3_CLRP012_Msk                            (0x01UL << GPIO_PORT_CLR3_CLRP012_Pos)                    /*!< GPIO_PORT CLR3: CLRP012 Mask        */
#define GPIO_PORT_CLR3_CLRP013_Pos                            13                                                        /*!< GPIO_PORT CLR3: CLRP013 Position    */
#define GPIO_PORT_CLR3_CLRP013_Msk                            (0x01UL << GPIO_PORT_CLR3_CLRP013_Pos)                    /*!< GPIO_PORT CLR3: CLRP013 Mask        */
#define GPIO_PORT_CLR3_CLRP014_Pos                            14                                                        /*!< GPIO_PORT CLR3: CLRP014 Position    */
#define GPIO_PORT_CLR3_CLRP014_Msk                            (0x01UL << GPIO_PORT_CLR3_CLRP014_Pos)                    /*!< GPIO_PORT CLR3: CLRP014 Mask        */
#define GPIO_PORT_CLR3_CLRP015_Pos                            15                                                        /*!< GPIO_PORT CLR3: CLRP015 Position    */
#define GPIO_PORT_CLR3_CLRP015_Msk                            (0x01UL << GPIO_PORT_CLR3_CLRP015_Pos)                    /*!< GPIO_PORT CLR3: CLRP015 Mask        */
#define GPIO_PORT_CLR3_CLRP016_Pos                            16                                                        /*!< GPIO_PORT CLR3: CLRP016 Position    */
#define GPIO_PORT_CLR3_CLRP016_Msk                            (0x01UL << GPIO_PORT_CLR3_CLRP016_Pos)                    /*!< GPIO_PORT CLR3: CLRP016 Mask        */
#define GPIO_PORT_CLR3_CLRP017_Pos                            17                                                        /*!< GPIO_PORT CLR3: CLRP017 Position    */
#define GPIO_PORT_CLR3_CLRP017_Msk                            (0x01UL << GPIO_PORT_CLR3_CLRP017_Pos)                    /*!< GPIO_PORT CLR3: CLRP017 Mask        */
#define GPIO_PORT_CLR3_CLRP018_Pos                            18                                                        /*!< GPIO_PORT CLR3: CLRP018 Position    */
#define GPIO_PORT_CLR3_CLRP018_Msk                            (0x01UL << GPIO_PORT_CLR3_CLRP018_Pos)                    /*!< GPIO_PORT CLR3: CLRP018 Mask        */
#define GPIO_PORT_CLR3_CLRP019_Pos                            19                                                        /*!< GPIO_PORT CLR3: CLRP019 Position    */
#define GPIO_PORT_CLR3_CLRP019_Msk                            (0x01UL << GPIO_PORT_CLR3_CLRP019_Pos)                    /*!< GPIO_PORT CLR3: CLRP019 Mask        */
#define GPIO_PORT_CLR3_CLRP020_Pos                            20                                                        /*!< GPIO_PORT CLR3: CLRP020 Position    */
#define GPIO_PORT_CLR3_CLRP020_Msk                            (0x01UL << GPIO_PORT_CLR3_CLRP020_Pos)                    /*!< GPIO_PORT CLR3: CLRP020 Mask        */
#define GPIO_PORT_CLR3_CLRP021_Pos                            21                                                        /*!< GPIO_PORT CLR3: CLRP021 Position    */
#define GPIO_PORT_CLR3_CLRP021_Msk                            (0x01UL << GPIO_PORT_CLR3_CLRP021_Pos)                    /*!< GPIO_PORT CLR3: CLRP021 Mask        */
#define GPIO_PORT_CLR3_CLRP022_Pos                            22                                                        /*!< GPIO_PORT CLR3: CLRP022 Position    */
#define GPIO_PORT_CLR3_CLRP022_Msk                            (0x01UL << GPIO_PORT_CLR3_CLRP022_Pos)                    /*!< GPIO_PORT CLR3: CLRP022 Mask        */
#define GPIO_PORT_CLR3_CLRP023_Pos                            23                                                        /*!< GPIO_PORT CLR3: CLRP023 Position    */
#define GPIO_PORT_CLR3_CLRP023_Msk                            (0x01UL << GPIO_PORT_CLR3_CLRP023_Pos)                    /*!< GPIO_PORT CLR3: CLRP023 Mask        */
#define GPIO_PORT_CLR3_CLRP024_Pos                            24                                                        /*!< GPIO_PORT CLR3: CLRP024 Position    */
#define GPIO_PORT_CLR3_CLRP024_Msk                            (0x01UL << GPIO_PORT_CLR3_CLRP024_Pos)                    /*!< GPIO_PORT CLR3: CLRP024 Mask        */
#define GPIO_PORT_CLR3_CLRP025_Pos                            25                                                        /*!< GPIO_PORT CLR3: CLRP025 Position    */
#define GPIO_PORT_CLR3_CLRP025_Msk                            (0x01UL << GPIO_PORT_CLR3_CLRP025_Pos)                    /*!< GPIO_PORT CLR3: CLRP025 Mask        */
#define GPIO_PORT_CLR3_CLRP026_Pos                            26                                                        /*!< GPIO_PORT CLR3: CLRP026 Position    */
#define GPIO_PORT_CLR3_CLRP026_Msk                            (0x01UL << GPIO_PORT_CLR3_CLRP026_Pos)                    /*!< GPIO_PORT CLR3: CLRP026 Mask        */
#define GPIO_PORT_CLR3_CLRP027_Pos                            27                                                        /*!< GPIO_PORT CLR3: CLRP027 Position    */
#define GPIO_PORT_CLR3_CLRP027_Msk                            (0x01UL << GPIO_PORT_CLR3_CLRP027_Pos)                    /*!< GPIO_PORT CLR3: CLRP027 Mask        */
#define GPIO_PORT_CLR3_CLRP028_Pos                            28                                                        /*!< GPIO_PORT CLR3: CLRP028 Position    */
#define GPIO_PORT_CLR3_CLRP028_Msk                            (0x01UL << GPIO_PORT_CLR3_CLRP028_Pos)                    /*!< GPIO_PORT CLR3: CLRP028 Mask        */
#define GPIO_PORT_CLR3_CLRP029_Pos                            29                                                        /*!< GPIO_PORT CLR3: CLRP029 Position    */
#define GPIO_PORT_CLR3_CLRP029_Msk                            (0x01UL << GPIO_PORT_CLR3_CLRP029_Pos)                    /*!< GPIO_PORT CLR3: CLRP029 Mask        */
#define GPIO_PORT_CLR3_CLRP030_Pos                            30                                                        /*!< GPIO_PORT CLR3: CLRP030 Position    */
#define GPIO_PORT_CLR3_CLRP030_Msk                            (0x01UL << GPIO_PORT_CLR3_CLRP030_Pos)                    /*!< GPIO_PORT CLR3: CLRP030 Mask        */
#define GPIO_PORT_CLR3_CLRP031_Pos                            31                                                        /*!< GPIO_PORT CLR3: CLRP031 Position    */
#define GPIO_PORT_CLR3_CLRP031_Msk                            (0x01UL << GPIO_PORT_CLR3_CLRP031_Pos)                    /*!< GPIO_PORT CLR3: CLRP031 Mask        */

// -------------------------------------  GPIO_PORT_CLR4  -----------------------------------------
#define GPIO_PORT_CLR4_CLRP00_Pos                             0                                                         /*!< GPIO_PORT CLR4: CLRP00 Position     */
#define GPIO_PORT_CLR4_CLRP00_Msk                             (0x01UL << GPIO_PORT_CLR4_CLRP00_Pos)                     /*!< GPIO_PORT CLR4: CLRP00 Mask         */
#define GPIO_PORT_CLR4_CLRP01_Pos                             1                                                         /*!< GPIO_PORT CLR4: CLRP01 Position     */
#define GPIO_PORT_CLR4_CLRP01_Msk                             (0x01UL << GPIO_PORT_CLR4_CLRP01_Pos)                     /*!< GPIO_PORT CLR4: CLRP01 Mask         */
#define GPIO_PORT_CLR4_CLRP02_Pos                             2                                                         /*!< GPIO_PORT CLR4: CLRP02 Position     */
#define GPIO_PORT_CLR4_CLRP02_Msk                             (0x01UL << GPIO_PORT_CLR4_CLRP02_Pos)                     /*!< GPIO_PORT CLR4: CLRP02 Mask         */
#define GPIO_PORT_CLR4_CLRP03_Pos                             3                                                         /*!< GPIO_PORT CLR4: CLRP03 Position     */
#define GPIO_PORT_CLR4_CLRP03_Msk                             (0x01UL << GPIO_PORT_CLR4_CLRP03_Pos)                     /*!< GPIO_PORT CLR4: CLRP03 Mask         */
#define GPIO_PORT_CLR4_CLRP04_Pos                             4                                                         /*!< GPIO_PORT CLR4: CLRP04 Position     */
#define GPIO_PORT_CLR4_CLRP04_Msk                             (0x01UL << GPIO_PORT_CLR4_CLRP04_Pos)                     /*!< GPIO_PORT CLR4: CLRP04 Mask         */
#define GPIO_PORT_CLR4_CLRP05_Pos                             5                                                         /*!< GPIO_PORT CLR4: CLRP05 Position     */
#define GPIO_PORT_CLR4_CLRP05_Msk                             (0x01UL << GPIO_PORT_CLR4_CLRP05_Pos)                     /*!< GPIO_PORT CLR4: CLRP05 Mask         */
#define GPIO_PORT_CLR4_CLRP06_Pos                             6                                                         /*!< GPIO_PORT CLR4: CLRP06 Position     */
#define GPIO_PORT_CLR4_CLRP06_Msk                             (0x01UL << GPIO_PORT_CLR4_CLRP06_Pos)                     /*!< GPIO_PORT CLR4: CLRP06 Mask         */
#define GPIO_PORT_CLR4_CLRP07_Pos                             7                                                         /*!< GPIO_PORT CLR4: CLRP07 Position     */
#define GPIO_PORT_CLR4_CLRP07_Msk                             (0x01UL << GPIO_PORT_CLR4_CLRP07_Pos)                     /*!< GPIO_PORT CLR4: CLRP07 Mask         */
#define GPIO_PORT_CLR4_CLRP08_Pos                             8                                                         /*!< GPIO_PORT CLR4: CLRP08 Position     */
#define GPIO_PORT_CLR4_CLRP08_Msk                             (0x01UL << GPIO_PORT_CLR4_CLRP08_Pos)                     /*!< GPIO_PORT CLR4: CLRP08 Mask         */
#define GPIO_PORT_CLR4_CLRP09_Pos                             9                                                         /*!< GPIO_PORT CLR4: CLRP09 Position     */
#define GPIO_PORT_CLR4_CLRP09_Msk                             (0x01UL << GPIO_PORT_CLR4_CLRP09_Pos)                     /*!< GPIO_PORT CLR4: CLRP09 Mask         */
#define GPIO_PORT_CLR4_CLRP010_Pos                            10                                                        /*!< GPIO_PORT CLR4: CLRP010 Position    */
#define GPIO_PORT_CLR4_CLRP010_Msk                            (0x01UL << GPIO_PORT_CLR4_CLRP010_Pos)                    /*!< GPIO_PORT CLR4: CLRP010 Mask        */
#define GPIO_PORT_CLR4_CLRP011_Pos                            11                                                        /*!< GPIO_PORT CLR4: CLRP011 Position    */
#define GPIO_PORT_CLR4_CLRP011_Msk                            (0x01UL << GPIO_PORT_CLR4_CLRP011_Pos)                    /*!< GPIO_PORT CLR4: CLRP011 Mask        */
#define GPIO_PORT_CLR4_CLRP012_Pos                            12                                                        /*!< GPIO_PORT CLR4: CLRP012 Position    */
#define GPIO_PORT_CLR4_CLRP012_Msk                            (0x01UL << GPIO_PORT_CLR4_CLRP012_Pos)                    /*!< GPIO_PORT CLR4: CLRP012 Mask        */
#define GPIO_PORT_CLR4_CLRP013_Pos                            13                                                        /*!< GPIO_PORT CLR4: CLRP013 Position    */
#define GPIO_PORT_CLR4_CLRP013_Msk                            (0x01UL << GPIO_PORT_CLR4_CLRP013_Pos)                    /*!< GPIO_PORT CLR4: CLRP013 Mask        */
#define GPIO_PORT_CLR4_CLRP014_Pos                            14                                                        /*!< GPIO_PORT CLR4: CLRP014 Position    */
#define GPIO_PORT_CLR4_CLRP014_Msk                            (0x01UL << GPIO_PORT_CLR4_CLRP014_Pos)                    /*!< GPIO_PORT CLR4: CLRP014 Mask        */
#define GPIO_PORT_CLR4_CLRP015_Pos                            15                                                        /*!< GPIO_PORT CLR4: CLRP015 Position    */
#define GPIO_PORT_CLR4_CLRP015_Msk                            (0x01UL << GPIO_PORT_CLR4_CLRP015_Pos)                    /*!< GPIO_PORT CLR4: CLRP015 Mask        */
#define GPIO_PORT_CLR4_CLRP016_Pos                            16                                                        /*!< GPIO_PORT CLR4: CLRP016 Position    */
#define GPIO_PORT_CLR4_CLRP016_Msk                            (0x01UL << GPIO_PORT_CLR4_CLRP016_Pos)                    /*!< GPIO_PORT CLR4: CLRP016 Mask        */
#define GPIO_PORT_CLR4_CLRP017_Pos                            17                                                        /*!< GPIO_PORT CLR4: CLRP017 Position    */
#define GPIO_PORT_CLR4_CLRP017_Msk                            (0x01UL << GPIO_PORT_CLR4_CLRP017_Pos)                    /*!< GPIO_PORT CLR4: CLRP017 Mask        */
#define GPIO_PORT_CLR4_CLRP018_Pos                            18                                                        /*!< GPIO_PORT CLR4: CLRP018 Position    */
#define GPIO_PORT_CLR4_CLRP018_Msk                            (0x01UL << GPIO_PORT_CLR4_CLRP018_Pos)                    /*!< GPIO_PORT CLR4: CLRP018 Mask        */
#define GPIO_PORT_CLR4_CLRP019_Pos                            19                                                        /*!< GPIO_PORT CLR4: CLRP019 Position    */
#define GPIO_PORT_CLR4_CLRP019_Msk                            (0x01UL << GPIO_PORT_CLR4_CLRP019_Pos)                    /*!< GPIO_PORT CLR4: CLRP019 Mask        */
#define GPIO_PORT_CLR4_CLRP020_Pos                            20                                                        /*!< GPIO_PORT CLR4: CLRP020 Position    */
#define GPIO_PORT_CLR4_CLRP020_Msk                            (0x01UL << GPIO_PORT_CLR4_CLRP020_Pos)                    /*!< GPIO_PORT CLR4: CLRP020 Mask        */
#define GPIO_PORT_CLR4_CLRP021_Pos                            21                                                        /*!< GPIO_PORT CLR4: CLRP021 Position    */
#define GPIO_PORT_CLR4_CLRP021_Msk                            (0x01UL << GPIO_PORT_CLR4_CLRP021_Pos)                    /*!< GPIO_PORT CLR4: CLRP021 Mask        */
#define GPIO_PORT_CLR4_CLRP022_Pos                            22                                                        /*!< GPIO_PORT CLR4: CLRP022 Position    */
#define GPIO_PORT_CLR4_CLRP022_Msk                            (0x01UL << GPIO_PORT_CLR4_CLRP022_Pos)                    /*!< GPIO_PORT CLR4: CLRP022 Mask        */
#define GPIO_PORT_CLR4_CLRP023_Pos                            23                                                        /*!< GPIO_PORT CLR4: CLRP023 Position    */
#define GPIO_PORT_CLR4_CLRP023_Msk                            (0x01UL << GPIO_PORT_CLR4_CLRP023_Pos)                    /*!< GPIO_PORT CLR4: CLRP023 Mask        */
#define GPIO_PORT_CLR4_CLRP024_Pos                            24                                                        /*!< GPIO_PORT CLR4: CLRP024 Position    */
#define GPIO_PORT_CLR4_CLRP024_Msk                            (0x01UL << GPIO_PORT_CLR4_CLRP024_Pos)                    /*!< GPIO_PORT CLR4: CLRP024 Mask        */
#define GPIO_PORT_CLR4_CLRP025_Pos                            25                                                        /*!< GPIO_PORT CLR4: CLRP025 Position    */
#define GPIO_PORT_CLR4_CLRP025_Msk                            (0x01UL << GPIO_PORT_CLR4_CLRP025_Pos)                    /*!< GPIO_PORT CLR4: CLRP025 Mask        */
#define GPIO_PORT_CLR4_CLRP026_Pos                            26                                                        /*!< GPIO_PORT CLR4: CLRP026 Position    */
#define GPIO_PORT_CLR4_CLRP026_Msk                            (0x01UL << GPIO_PORT_CLR4_CLRP026_Pos)                    /*!< GPIO_PORT CLR4: CLRP026 Mask        */
#define GPIO_PORT_CLR4_CLRP027_Pos                            27                                                        /*!< GPIO_PORT CLR4: CLRP027 Position    */
#define GPIO_PORT_CLR4_CLRP027_Msk                            (0x01UL << GPIO_PORT_CLR4_CLRP027_Pos)                    /*!< GPIO_PORT CLR4: CLRP027 Mask        */
#define GPIO_PORT_CLR4_CLRP028_Pos                            28                                                        /*!< GPIO_PORT CLR4: CLRP028 Position    */
#define GPIO_PORT_CLR4_CLRP028_Msk                            (0x01UL << GPIO_PORT_CLR4_CLRP028_Pos)                    /*!< GPIO_PORT CLR4: CLRP028 Mask        */
#define GPIO_PORT_CLR4_CLRP029_Pos                            29                                                        /*!< GPIO_PORT CLR4: CLRP029 Position    */
#define GPIO_PORT_CLR4_CLRP029_Msk                            (0x01UL << GPIO_PORT_CLR4_CLRP029_Pos)                    /*!< GPIO_PORT CLR4: CLRP029 Mask        */
#define GPIO_PORT_CLR4_CLRP030_Pos                            30                                                        /*!< GPIO_PORT CLR4: CLRP030 Position    */
#define GPIO_PORT_CLR4_CLRP030_Msk                            (0x01UL << GPIO_PORT_CLR4_CLRP030_Pos)                    /*!< GPIO_PORT CLR4: CLRP030 Mask        */
#define GPIO_PORT_CLR4_CLRP031_Pos                            31                                                        /*!< GPIO_PORT CLR4: CLRP031 Position    */
#define GPIO_PORT_CLR4_CLRP031_Msk                            (0x01UL << GPIO_PORT_CLR4_CLRP031_Pos)                    /*!< GPIO_PORT CLR4: CLRP031 Mask        */

// -------------------------------------  GPIO_PORT_CLR5  -----------------------------------------
#define GPIO_PORT_CLR5_CLRP00_Pos                             0                                                         /*!< GPIO_PORT CLR5: CLRP00 Position     */
#define GPIO_PORT_CLR5_CLRP00_Msk                             (0x01UL << GPIO_PORT_CLR5_CLRP00_Pos)                     /*!< GPIO_PORT CLR5: CLRP00 Mask         */
#define GPIO_PORT_CLR5_CLRP01_Pos                             1                                                         /*!< GPIO_PORT CLR5: CLRP01 Position     */
#define GPIO_PORT_CLR5_CLRP01_Msk                             (0x01UL << GPIO_PORT_CLR5_CLRP01_Pos)                     /*!< GPIO_PORT CLR5: CLRP01 Mask         */
#define GPIO_PORT_CLR5_CLRP02_Pos                             2                                                         /*!< GPIO_PORT CLR5: CLRP02 Position     */
#define GPIO_PORT_CLR5_CLRP02_Msk                             (0x01UL << GPIO_PORT_CLR5_CLRP02_Pos)                     /*!< GPIO_PORT CLR5: CLRP02 Mask         */
#define GPIO_PORT_CLR5_CLRP03_Pos                             3                                                         /*!< GPIO_PORT CLR5: CLRP03 Position     */
#define GPIO_PORT_CLR5_CLRP03_Msk                             (0x01UL << GPIO_PORT_CLR5_CLRP03_Pos)                     /*!< GPIO_PORT CLR5: CLRP03 Mask         */
#define GPIO_PORT_CLR5_CLRP04_Pos                             4                                                         /*!< GPIO_PORT CLR5: CLRP04 Position     */
#define GPIO_PORT_CLR5_CLRP04_Msk                             (0x01UL << GPIO_PORT_CLR5_CLRP04_Pos)                     /*!< GPIO_PORT CLR5: CLRP04 Mask         */
#define GPIO_PORT_CLR5_CLRP05_Pos                             5                                                         /*!< GPIO_PORT CLR5: CLRP05 Position     */
#define GPIO_PORT_CLR5_CLRP05_Msk                             (0x01UL << GPIO_PORT_CLR5_CLRP05_Pos)                     /*!< GPIO_PORT CLR5: CLRP05 Mask         */
#define GPIO_PORT_CLR5_CLRP06_Pos                             6                                                         /*!< GPIO_PORT CLR5: CLRP06 Position     */
#define GPIO_PORT_CLR5_CLRP06_Msk                             (0x01UL << GPIO_PORT_CLR5_CLRP06_Pos)                     /*!< GPIO_PORT CLR5: CLRP06 Mask         */
#define GPIO_PORT_CLR5_CLRP07_Pos                             7                                                         /*!< GPIO_PORT CLR5: CLRP07 Position     */
#define GPIO_PORT_CLR5_CLRP07_Msk                             (0x01UL << GPIO_PORT_CLR5_CLRP07_Pos)                     /*!< GPIO_PORT CLR5: CLRP07 Mask         */
#define GPIO_PORT_CLR5_CLRP08_Pos                             8                                                         /*!< GPIO_PORT CLR5: CLRP08 Position     */
#define GPIO_PORT_CLR5_CLRP08_Msk                             (0x01UL << GPIO_PORT_CLR5_CLRP08_Pos)                     /*!< GPIO_PORT CLR5: CLRP08 Mask         */
#define GPIO_PORT_CLR5_CLRP09_Pos                             9                                                         /*!< GPIO_PORT CLR5: CLRP09 Position     */
#define GPIO_PORT_CLR5_CLRP09_Msk                             (0x01UL << GPIO_PORT_CLR5_CLRP09_Pos)                     /*!< GPIO_PORT CLR5: CLRP09 Mask         */
#define GPIO_PORT_CLR5_CLRP010_Pos                            10                                                        /*!< GPIO_PORT CLR5: CLRP010 Position    */
#define GPIO_PORT_CLR5_CLRP010_Msk                            (0x01UL << GPIO_PORT_CLR5_CLRP010_Pos)                    /*!< GPIO_PORT CLR5: CLRP010 Mask        */
#define GPIO_PORT_CLR5_CLRP011_Pos                            11                                                        /*!< GPIO_PORT CLR5: CLRP011 Position    */
#define GPIO_PORT_CLR5_CLRP011_Msk                            (0x01UL << GPIO_PORT_CLR5_CLRP011_Pos)                    /*!< GPIO_PORT CLR5: CLRP011 Mask        */
#define GPIO_PORT_CLR5_CLRP012_Pos                            12                                                        /*!< GPIO_PORT CLR5: CLRP012 Position    */
#define GPIO_PORT_CLR5_CLRP012_Msk                            (0x01UL << GPIO_PORT_CLR5_CLRP012_Pos)                    /*!< GPIO_PORT CLR5: CLRP012 Mask        */
#define GPIO_PORT_CLR5_CLRP013_Pos                            13                                                        /*!< GPIO_PORT CLR5: CLRP013 Position    */
#define GPIO_PORT_CLR5_CLRP013_Msk                            (0x01UL << GPIO_PORT_CLR5_CLRP013_Pos)                    /*!< GPIO_PORT CLR5: CLRP013 Mask        */
#define GPIO_PORT_CLR5_CLRP014_Pos                            14                                                        /*!< GPIO_PORT CLR5: CLRP014 Position    */
#define GPIO_PORT_CLR5_CLRP014_Msk                            (0x01UL << GPIO_PORT_CLR5_CLRP014_Pos)                    /*!< GPIO_PORT CLR5: CLRP014 Mask        */
#define GPIO_PORT_CLR5_CLRP015_Pos                            15                                                        /*!< GPIO_PORT CLR5: CLRP015 Position    */
#define GPIO_PORT_CLR5_CLRP015_Msk                            (0x01UL << GPIO_PORT_CLR5_CLRP015_Pos)                    /*!< GPIO_PORT CLR5: CLRP015 Mask        */
#define GPIO_PORT_CLR5_CLRP016_Pos                            16                                                        /*!< GPIO_PORT CLR5: CLRP016 Position    */
#define GPIO_PORT_CLR5_CLRP016_Msk                            (0x01UL << GPIO_PORT_CLR5_CLRP016_Pos)                    /*!< GPIO_PORT CLR5: CLRP016 Mask        */
#define GPIO_PORT_CLR5_CLRP017_Pos                            17                                                        /*!< GPIO_PORT CLR5: CLRP017 Position    */
#define GPIO_PORT_CLR5_CLRP017_Msk                            (0x01UL << GPIO_PORT_CLR5_CLRP017_Pos)                    /*!< GPIO_PORT CLR5: CLRP017 Mask        */
#define GPIO_PORT_CLR5_CLRP018_Pos                            18                                                        /*!< GPIO_PORT CLR5: CLRP018 Position    */
#define GPIO_PORT_CLR5_CLRP018_Msk                            (0x01UL << GPIO_PORT_CLR5_CLRP018_Pos)                    /*!< GPIO_PORT CLR5: CLRP018 Mask        */
#define GPIO_PORT_CLR5_CLRP019_Pos                            19                                                        /*!< GPIO_PORT CLR5: CLRP019 Position    */
#define GPIO_PORT_CLR5_CLRP019_Msk                            (0x01UL << GPIO_PORT_CLR5_CLRP019_Pos)                    /*!< GPIO_PORT CLR5: CLRP019 Mask        */
#define GPIO_PORT_CLR5_CLRP020_Pos                            20                                                        /*!< GPIO_PORT CLR5: CLRP020 Position    */
#define GPIO_PORT_CLR5_CLRP020_Msk                            (0x01UL << GPIO_PORT_CLR5_CLRP020_Pos)                    /*!< GPIO_PORT CLR5: CLRP020 Mask        */
#define GPIO_PORT_CLR5_CLRP021_Pos                            21                                                        /*!< GPIO_PORT CLR5: CLRP021 Position    */
#define GPIO_PORT_CLR5_CLRP021_Msk                            (0x01UL << GPIO_PORT_CLR5_CLRP021_Pos)                    /*!< GPIO_PORT CLR5: CLRP021 Mask        */
#define GPIO_PORT_CLR5_CLRP022_Pos                            22                                                        /*!< GPIO_PORT CLR5: CLRP022 Position    */
#define GPIO_PORT_CLR5_CLRP022_Msk                            (0x01UL << GPIO_PORT_CLR5_CLRP022_Pos)                    /*!< GPIO_PORT CLR5: CLRP022 Mask        */
#define GPIO_PORT_CLR5_CLRP023_Pos                            23                                                        /*!< GPIO_PORT CLR5: CLRP023 Position    */
#define GPIO_PORT_CLR5_CLRP023_Msk                            (0x01UL << GPIO_PORT_CLR5_CLRP023_Pos)                    /*!< GPIO_PORT CLR5: CLRP023 Mask        */
#define GPIO_PORT_CLR5_CLRP024_Pos                            24                                                        /*!< GPIO_PORT CLR5: CLRP024 Position    */
#define GPIO_PORT_CLR5_CLRP024_Msk                            (0x01UL << GPIO_PORT_CLR5_CLRP024_Pos)                    /*!< GPIO_PORT CLR5: CLRP024 Mask        */
#define GPIO_PORT_CLR5_CLRP025_Pos                            25                                                        /*!< GPIO_PORT CLR5: CLRP025 Position    */
#define GPIO_PORT_CLR5_CLRP025_Msk                            (0x01UL << GPIO_PORT_CLR5_CLRP025_Pos)                    /*!< GPIO_PORT CLR5: CLRP025 Mask        */
#define GPIO_PORT_CLR5_CLRP026_Pos                            26                                                        /*!< GPIO_PORT CLR5: CLRP026 Position    */
#define GPIO_PORT_CLR5_CLRP026_Msk                            (0x01UL << GPIO_PORT_CLR5_CLRP026_Pos)                    /*!< GPIO_PORT CLR5: CLRP026 Mask        */
#define GPIO_PORT_CLR5_CLRP027_Pos                            27                                                        /*!< GPIO_PORT CLR5: CLRP027 Position    */
#define GPIO_PORT_CLR5_CLRP027_Msk                            (0x01UL << GPIO_PORT_CLR5_CLRP027_Pos)                    /*!< GPIO_PORT CLR5: CLRP027 Mask        */
#define GPIO_PORT_CLR5_CLRP028_Pos                            28                                                        /*!< GPIO_PORT CLR5: CLRP028 Position    */
#define GPIO_PORT_CLR5_CLRP028_Msk                            (0x01UL << GPIO_PORT_CLR5_CLRP028_Pos)                    /*!< GPIO_PORT CLR5: CLRP028 Mask        */
#define GPIO_PORT_CLR5_CLRP029_Pos                            29                                                        /*!< GPIO_PORT CLR5: CLRP029 Position    */
#define GPIO_PORT_CLR5_CLRP029_Msk                            (0x01UL << GPIO_PORT_CLR5_CLRP029_Pos)                    /*!< GPIO_PORT CLR5: CLRP029 Mask        */
#define GPIO_PORT_CLR5_CLRP030_Pos                            30                                                        /*!< GPIO_PORT CLR5: CLRP030 Position    */
#define GPIO_PORT_CLR5_CLRP030_Msk                            (0x01UL << GPIO_PORT_CLR5_CLRP030_Pos)                    /*!< GPIO_PORT CLR5: CLRP030 Mask        */
#define GPIO_PORT_CLR5_CLRP031_Pos                            31                                                        /*!< GPIO_PORT CLR5: CLRP031 Position    */
#define GPIO_PORT_CLR5_CLRP031_Msk                            (0x01UL << GPIO_PORT_CLR5_CLRP031_Pos)                    /*!< GPIO_PORT CLR5: CLRP031 Mask        */

// -------------------------------------  GPIO_PORT_CLR6  -----------------------------------------
#define GPIO_PORT_CLR6_CLRP00_Pos                             0                                                         /*!< GPIO_PORT CLR6: CLRP00 Position     */
#define GPIO_PORT_CLR6_CLRP00_Msk                             (0x01UL << GPIO_PORT_CLR6_CLRP00_Pos)                     /*!< GPIO_PORT CLR6: CLRP00 Mask         */
#define GPIO_PORT_CLR6_CLRP01_Pos                             1                                                         /*!< GPIO_PORT CLR6: CLRP01 Position     */
#define GPIO_PORT_CLR6_CLRP01_Msk                             (0x01UL << GPIO_PORT_CLR6_CLRP01_Pos)                     /*!< GPIO_PORT CLR6: CLRP01 Mask         */
#define GPIO_PORT_CLR6_CLRP02_Pos                             2                                                         /*!< GPIO_PORT CLR6: CLRP02 Position     */
#define GPIO_PORT_CLR6_CLRP02_Msk                             (0x01UL << GPIO_PORT_CLR6_CLRP02_Pos)                     /*!< GPIO_PORT CLR6: CLRP02 Mask         */
#define GPIO_PORT_CLR6_CLRP03_Pos                             3                                                         /*!< GPIO_PORT CLR6: CLRP03 Position     */
#define GPIO_PORT_CLR6_CLRP03_Msk                             (0x01UL << GPIO_PORT_CLR6_CLRP03_Pos)                     /*!< GPIO_PORT CLR6: CLRP03 Mask         */
#define GPIO_PORT_CLR6_CLRP04_Pos                             4                                                         /*!< GPIO_PORT CLR6: CLRP04 Position     */
#define GPIO_PORT_CLR6_CLRP04_Msk                             (0x01UL << GPIO_PORT_CLR6_CLRP04_Pos)                     /*!< GPIO_PORT CLR6: CLRP04 Mask         */
#define GPIO_PORT_CLR6_CLRP05_Pos                             5                                                         /*!< GPIO_PORT CLR6: CLRP05 Position     */
#define GPIO_PORT_CLR6_CLRP05_Msk                             (0x01UL << GPIO_PORT_CLR6_CLRP05_Pos)                     /*!< GPIO_PORT CLR6: CLRP05 Mask         */
#define GPIO_PORT_CLR6_CLRP06_Pos                             6                                                         /*!< GPIO_PORT CLR6: CLRP06 Position     */
#define GPIO_PORT_CLR6_CLRP06_Msk                             (0x01UL << GPIO_PORT_CLR6_CLRP06_Pos)                     /*!< GPIO_PORT CLR6: CLRP06 Mask         */
#define GPIO_PORT_CLR6_CLRP07_Pos                             7                                                         /*!< GPIO_PORT CLR6: CLRP07 Position     */
#define GPIO_PORT_CLR6_CLRP07_Msk                             (0x01UL << GPIO_PORT_CLR6_CLRP07_Pos)                     /*!< GPIO_PORT CLR6: CLRP07 Mask         */
#define GPIO_PORT_CLR6_CLRP08_Pos                             8                                                         /*!< GPIO_PORT CLR6: CLRP08 Position     */
#define GPIO_PORT_CLR6_CLRP08_Msk                             (0x01UL << GPIO_PORT_CLR6_CLRP08_Pos)                     /*!< GPIO_PORT CLR6: CLRP08 Mask         */
#define GPIO_PORT_CLR6_CLRP09_Pos                             9                                                         /*!< GPIO_PORT CLR6: CLRP09 Position     */
#define GPIO_PORT_CLR6_CLRP09_Msk                             (0x01UL << GPIO_PORT_CLR6_CLRP09_Pos)                     /*!< GPIO_PORT CLR6: CLRP09 Mask         */
#define GPIO_PORT_CLR6_CLRP010_Pos                            10                                                        /*!< GPIO_PORT CLR6: CLRP010 Position    */
#define GPIO_PORT_CLR6_CLRP010_Msk                            (0x01UL << GPIO_PORT_CLR6_CLRP010_Pos)                    /*!< GPIO_PORT CLR6: CLRP010 Mask        */
#define GPIO_PORT_CLR6_CLRP011_Pos                            11                                                        /*!< GPIO_PORT CLR6: CLRP011 Position    */
#define GPIO_PORT_CLR6_CLRP011_Msk                            (0x01UL << GPIO_PORT_CLR6_CLRP011_Pos)                    /*!< GPIO_PORT CLR6: CLRP011 Mask        */
#define GPIO_PORT_CLR6_CLRP012_Pos                            12                                                        /*!< GPIO_PORT CLR6: CLRP012 Position    */
#define GPIO_PORT_CLR6_CLRP012_Msk                            (0x01UL << GPIO_PORT_CLR6_CLRP012_Pos)                    /*!< GPIO_PORT CLR6: CLRP012 Mask        */
#define GPIO_PORT_CLR6_CLRP013_Pos                            13                                                        /*!< GPIO_PORT CLR6: CLRP013 Position    */
#define GPIO_PORT_CLR6_CLRP013_Msk                            (0x01UL << GPIO_PORT_CLR6_CLRP013_Pos)                    /*!< GPIO_PORT CLR6: CLRP013 Mask        */
#define GPIO_PORT_CLR6_CLRP014_Pos                            14                                                        /*!< GPIO_PORT CLR6: CLRP014 Position    */
#define GPIO_PORT_CLR6_CLRP014_Msk                            (0x01UL << GPIO_PORT_CLR6_CLRP014_Pos)                    /*!< GPIO_PORT CLR6: CLRP014 Mask        */
#define GPIO_PORT_CLR6_CLRP015_Pos                            15                                                        /*!< GPIO_PORT CLR6: CLRP015 Position    */
#define GPIO_PORT_CLR6_CLRP015_Msk                            (0x01UL << GPIO_PORT_CLR6_CLRP015_Pos)                    /*!< GPIO_PORT CLR6: CLRP015 Mask        */
#define GPIO_PORT_CLR6_CLRP016_Pos                            16                                                        /*!< GPIO_PORT CLR6: CLRP016 Position    */
#define GPIO_PORT_CLR6_CLRP016_Msk                            (0x01UL << GPIO_PORT_CLR6_CLRP016_Pos)                    /*!< GPIO_PORT CLR6: CLRP016 Mask        */
#define GPIO_PORT_CLR6_CLRP017_Pos                            17                                                        /*!< GPIO_PORT CLR6: CLRP017 Position    */
#define GPIO_PORT_CLR6_CLRP017_Msk                            (0x01UL << GPIO_PORT_CLR6_CLRP017_Pos)                    /*!< GPIO_PORT CLR6: CLRP017 Mask        */
#define GPIO_PORT_CLR6_CLRP018_Pos                            18                                                        /*!< GPIO_PORT CLR6: CLRP018 Position    */
#define GPIO_PORT_CLR6_CLRP018_Msk                            (0x01UL << GPIO_PORT_CLR6_CLRP018_Pos)                    /*!< GPIO_PORT CLR6: CLRP018 Mask        */
#define GPIO_PORT_CLR6_CLRP019_Pos                            19                                                        /*!< GPIO_PORT CLR6: CLRP019 Position    */
#define GPIO_PORT_CLR6_CLRP019_Msk                            (0x01UL << GPIO_PORT_CLR6_CLRP019_Pos)                    /*!< GPIO_PORT CLR6: CLRP019 Mask        */
#define GPIO_PORT_CLR6_CLRP020_Pos                            20                                                        /*!< GPIO_PORT CLR6: CLRP020 Position    */
#define GPIO_PORT_CLR6_CLRP020_Msk                            (0x01UL << GPIO_PORT_CLR6_CLRP020_Pos)                    /*!< GPIO_PORT CLR6: CLRP020 Mask        */
#define GPIO_PORT_CLR6_CLRP021_Pos                            21                                                        /*!< GPIO_PORT CLR6: CLRP021 Position    */
#define GPIO_PORT_CLR6_CLRP021_Msk                            (0x01UL << GPIO_PORT_CLR6_CLRP021_Pos)                    /*!< GPIO_PORT CLR6: CLRP021 Mask        */
#define GPIO_PORT_CLR6_CLRP022_Pos                            22                                                        /*!< GPIO_PORT CLR6: CLRP022 Position    */
#define GPIO_PORT_CLR6_CLRP022_Msk                            (0x01UL << GPIO_PORT_CLR6_CLRP022_Pos)                    /*!< GPIO_PORT CLR6: CLRP022 Mask        */
#define GPIO_PORT_CLR6_CLRP023_Pos                            23                                                        /*!< GPIO_PORT CLR6: CLRP023 Position    */
#define GPIO_PORT_CLR6_CLRP023_Msk                            (0x01UL << GPIO_PORT_CLR6_CLRP023_Pos)                    /*!< GPIO_PORT CLR6: CLRP023 Mask        */
#define GPIO_PORT_CLR6_CLRP024_Pos                            24                                                        /*!< GPIO_PORT CLR6: CLRP024 Position    */
#define GPIO_PORT_CLR6_CLRP024_Msk                            (0x01UL << GPIO_PORT_CLR6_CLRP024_Pos)                    /*!< GPIO_PORT CLR6: CLRP024 Mask        */
#define GPIO_PORT_CLR6_CLRP025_Pos                            25                                                        /*!< GPIO_PORT CLR6: CLRP025 Position    */
#define GPIO_PORT_CLR6_CLRP025_Msk                            (0x01UL << GPIO_PORT_CLR6_CLRP025_Pos)                    /*!< GPIO_PORT CLR6: CLRP025 Mask        */
#define GPIO_PORT_CLR6_CLRP026_Pos                            26                                                        /*!< GPIO_PORT CLR6: CLRP026 Position    */
#define GPIO_PORT_CLR6_CLRP026_Msk                            (0x01UL << GPIO_PORT_CLR6_CLRP026_Pos)                    /*!< GPIO_PORT CLR6: CLRP026 Mask        */
#define GPIO_PORT_CLR6_CLRP027_Pos                            27                                                        /*!< GPIO_PORT CLR6: CLRP027 Position    */
#define GPIO_PORT_CLR6_CLRP027_Msk                            (0x01UL << GPIO_PORT_CLR6_CLRP027_Pos)                    /*!< GPIO_PORT CLR6: CLRP027 Mask        */
#define GPIO_PORT_CLR6_CLRP028_Pos                            28                                                        /*!< GPIO_PORT CLR6: CLRP028 Position    */
#define GPIO_PORT_CLR6_CLRP028_Msk                            (0x01UL << GPIO_PORT_CLR6_CLRP028_Pos)                    /*!< GPIO_PORT CLR6: CLRP028 Mask        */
#define GPIO_PORT_CLR6_CLRP029_Pos                            29                                                        /*!< GPIO_PORT CLR6: CLRP029 Position    */
#define GPIO_PORT_CLR6_CLRP029_Msk                            (0x01UL << GPIO_PORT_CLR6_CLRP029_Pos)                    /*!< GPIO_PORT CLR6: CLRP029 Mask        */
#define GPIO_PORT_CLR6_CLRP030_Pos                            30                                                        /*!< GPIO_PORT CLR6: CLRP030 Position    */
#define GPIO_PORT_CLR6_CLRP030_Msk                            (0x01UL << GPIO_PORT_CLR6_CLRP030_Pos)                    /*!< GPIO_PORT CLR6: CLRP030 Mask        */
#define GPIO_PORT_CLR6_CLRP031_Pos                            31                                                        /*!< GPIO_PORT CLR6: CLRP031 Position    */
#define GPIO_PORT_CLR6_CLRP031_Msk                            (0x01UL << GPIO_PORT_CLR6_CLRP031_Pos)                    /*!< GPIO_PORT CLR6: CLRP031 Mask        */

// -------------------------------------  GPIO_PORT_CLR7  -----------------------------------------
#define GPIO_PORT_CLR7_CLRP00_Pos                             0                                                         /*!< GPIO_PORT CLR7: CLRP00 Position     */
#define GPIO_PORT_CLR7_CLRP00_Msk                             (0x01UL << GPIO_PORT_CLR7_CLRP00_Pos)                     /*!< GPIO_PORT CLR7: CLRP00 Mask         */
#define GPIO_PORT_CLR7_CLRP01_Pos                             1                                                         /*!< GPIO_PORT CLR7: CLRP01 Position     */
#define GPIO_PORT_CLR7_CLRP01_Msk                             (0x01UL << GPIO_PORT_CLR7_CLRP01_Pos)                     /*!< GPIO_PORT CLR7: CLRP01 Mask         */
#define GPIO_PORT_CLR7_CLRP02_Pos                             2                                                         /*!< GPIO_PORT CLR7: CLRP02 Position     */
#define GPIO_PORT_CLR7_CLRP02_Msk                             (0x01UL << GPIO_PORT_CLR7_CLRP02_Pos)                     /*!< GPIO_PORT CLR7: CLRP02 Mask         */
#define GPIO_PORT_CLR7_CLRP03_Pos                             3                                                         /*!< GPIO_PORT CLR7: CLRP03 Position     */
#define GPIO_PORT_CLR7_CLRP03_Msk                             (0x01UL << GPIO_PORT_CLR7_CLRP03_Pos)                     /*!< GPIO_PORT CLR7: CLRP03 Mask         */
#define GPIO_PORT_CLR7_CLRP04_Pos                             4                                                         /*!< GPIO_PORT CLR7: CLRP04 Position     */
#define GPIO_PORT_CLR7_CLRP04_Msk                             (0x01UL << GPIO_PORT_CLR7_CLRP04_Pos)                     /*!< GPIO_PORT CLR7: CLRP04 Mask         */
#define GPIO_PORT_CLR7_CLRP05_Pos                             5                                                         /*!< GPIO_PORT CLR7: CLRP05 Position     */
#define GPIO_PORT_CLR7_CLRP05_Msk                             (0x01UL << GPIO_PORT_CLR7_CLRP05_Pos)                     /*!< GPIO_PORT CLR7: CLRP05 Mask         */
#define GPIO_PORT_CLR7_CLRP06_Pos                             6                                                         /*!< GPIO_PORT CLR7: CLRP06 Position     */
#define GPIO_PORT_CLR7_CLRP06_Msk                             (0x01UL << GPIO_PORT_CLR7_CLRP06_Pos)                     /*!< GPIO_PORT CLR7: CLRP06 Mask         */
#define GPIO_PORT_CLR7_CLRP07_Pos                             7                                                         /*!< GPIO_PORT CLR7: CLRP07 Position     */
#define GPIO_PORT_CLR7_CLRP07_Msk                             (0x01UL << GPIO_PORT_CLR7_CLRP07_Pos)                     /*!< GPIO_PORT CLR7: CLRP07 Mask         */
#define GPIO_PORT_CLR7_CLRP08_Pos                             8                                                         /*!< GPIO_PORT CLR7: CLRP08 Position     */
#define GPIO_PORT_CLR7_CLRP08_Msk                             (0x01UL << GPIO_PORT_CLR7_CLRP08_Pos)                     /*!< GPIO_PORT CLR7: CLRP08 Mask         */
#define GPIO_PORT_CLR7_CLRP09_Pos                             9                                                         /*!< GPIO_PORT CLR7: CLRP09 Position     */
#define GPIO_PORT_CLR7_CLRP09_Msk                             (0x01UL << GPIO_PORT_CLR7_CLRP09_Pos)                     /*!< GPIO_PORT CLR7: CLRP09 Mask         */
#define GPIO_PORT_CLR7_CLRP010_Pos                            10                                                        /*!< GPIO_PORT CLR7: CLRP010 Position    */
#define GPIO_PORT_CLR7_CLRP010_Msk                            (0x01UL << GPIO_PORT_CLR7_CLRP010_Pos)                    /*!< GPIO_PORT CLR7: CLRP010 Mask        */
#define GPIO_PORT_CLR7_CLRP011_Pos                            11                                                        /*!< GPIO_PORT CLR7: CLRP011 Position    */
#define GPIO_PORT_CLR7_CLRP011_Msk                            (0x01UL << GPIO_PORT_CLR7_CLRP011_Pos)                    /*!< GPIO_PORT CLR7: CLRP011 Mask        */
#define GPIO_PORT_CLR7_CLRP012_Pos                            12                                                        /*!< GPIO_PORT CLR7: CLRP012 Position    */
#define GPIO_PORT_CLR7_CLRP012_Msk                            (0x01UL << GPIO_PORT_CLR7_CLRP012_Pos)                    /*!< GPIO_PORT CLR7: CLRP012 Mask        */
#define GPIO_PORT_CLR7_CLRP013_Pos                            13                                                        /*!< GPIO_PORT CLR7: CLRP013 Position    */
#define GPIO_PORT_CLR7_CLRP013_Msk                            (0x01UL << GPIO_PORT_CLR7_CLRP013_Pos)                    /*!< GPIO_PORT CLR7: CLRP013 Mask        */
#define GPIO_PORT_CLR7_CLRP014_Pos                            14                                                        /*!< GPIO_PORT CLR7: CLRP014 Position    */
#define GPIO_PORT_CLR7_CLRP014_Msk                            (0x01UL << GPIO_PORT_CLR7_CLRP014_Pos)                    /*!< GPIO_PORT CLR7: CLRP014 Mask        */
#define GPIO_PORT_CLR7_CLRP015_Pos                            15                                                        /*!< GPIO_PORT CLR7: CLRP015 Position    */
#define GPIO_PORT_CLR7_CLRP015_Msk                            (0x01UL << GPIO_PORT_CLR7_CLRP015_Pos)                    /*!< GPIO_PORT CLR7: CLRP015 Mask        */
#define GPIO_PORT_CLR7_CLRP016_Pos                            16                                                        /*!< GPIO_PORT CLR7: CLRP016 Position    */
#define GPIO_PORT_CLR7_CLRP016_Msk                            (0x01UL << GPIO_PORT_CLR7_CLRP016_Pos)                    /*!< GPIO_PORT CLR7: CLRP016 Mask        */
#define GPIO_PORT_CLR7_CLRP017_Pos                            17                                                        /*!< GPIO_PORT CLR7: CLRP017 Position    */
#define GPIO_PORT_CLR7_CLRP017_Msk                            (0x01UL << GPIO_PORT_CLR7_CLRP017_Pos)                    /*!< GPIO_PORT CLR7: CLRP017 Mask        */
#define GPIO_PORT_CLR7_CLRP018_Pos                            18                                                        /*!< GPIO_PORT CLR7: CLRP018 Position    */
#define GPIO_PORT_CLR7_CLRP018_Msk                            (0x01UL << GPIO_PORT_CLR7_CLRP018_Pos)                    /*!< GPIO_PORT CLR7: CLRP018 Mask        */
#define GPIO_PORT_CLR7_CLRP019_Pos                            19                                                        /*!< GPIO_PORT CLR7: CLRP019 Position    */
#define GPIO_PORT_CLR7_CLRP019_Msk                            (0x01UL << GPIO_PORT_CLR7_CLRP019_Pos)                    /*!< GPIO_PORT CLR7: CLRP019 Mask        */
#define GPIO_PORT_CLR7_CLRP020_Pos                            20                                                        /*!< GPIO_PORT CLR7: CLRP020 Position    */
#define GPIO_PORT_CLR7_CLRP020_Msk                            (0x01UL << GPIO_PORT_CLR7_CLRP020_Pos)                    /*!< GPIO_PORT CLR7: CLRP020 Mask        */
#define GPIO_PORT_CLR7_CLRP021_Pos                            21                                                        /*!< GPIO_PORT CLR7: CLRP021 Position    */
#define GPIO_PORT_CLR7_CLRP021_Msk                            (0x01UL << GPIO_PORT_CLR7_CLRP021_Pos)                    /*!< GPIO_PORT CLR7: CLRP021 Mask        */
#define GPIO_PORT_CLR7_CLRP022_Pos                            22                                                        /*!< GPIO_PORT CLR7: CLRP022 Position    */
#define GPIO_PORT_CLR7_CLRP022_Msk                            (0x01UL << GPIO_PORT_CLR7_CLRP022_Pos)                    /*!< GPIO_PORT CLR7: CLRP022 Mask        */
#define GPIO_PORT_CLR7_CLRP023_Pos                            23                                                        /*!< GPIO_PORT CLR7: CLRP023 Position    */
#define GPIO_PORT_CLR7_CLRP023_Msk                            (0x01UL << GPIO_PORT_CLR7_CLRP023_Pos)                    /*!< GPIO_PORT CLR7: CLRP023 Mask        */
#define GPIO_PORT_CLR7_CLRP024_Pos                            24                                                        /*!< GPIO_PORT CLR7: CLRP024 Position    */
#define GPIO_PORT_CLR7_CLRP024_Msk                            (0x01UL << GPIO_PORT_CLR7_CLRP024_Pos)                    /*!< GPIO_PORT CLR7: CLRP024 Mask        */
#define GPIO_PORT_CLR7_CLRP025_Pos                            25                                                        /*!< GPIO_PORT CLR7: CLRP025 Position    */
#define GPIO_PORT_CLR7_CLRP025_Msk                            (0x01UL << GPIO_PORT_CLR7_CLRP025_Pos)                    /*!< GPIO_PORT CLR7: CLRP025 Mask        */
#define GPIO_PORT_CLR7_CLRP026_Pos                            26                                                        /*!< GPIO_PORT CLR7: CLRP026 Position    */
#define GPIO_PORT_CLR7_CLRP026_Msk                            (0x01UL << GPIO_PORT_CLR7_CLRP026_Pos)                    /*!< GPIO_PORT CLR7: CLRP026 Mask        */
#define GPIO_PORT_CLR7_CLRP027_Pos                            27                                                        /*!< GPIO_PORT CLR7: CLRP027 Position    */
#define GPIO_PORT_CLR7_CLRP027_Msk                            (0x01UL << GPIO_PORT_CLR7_CLRP027_Pos)                    /*!< GPIO_PORT CLR7: CLRP027 Mask        */
#define GPIO_PORT_CLR7_CLRP028_Pos                            28                                                        /*!< GPIO_PORT CLR7: CLRP028 Position    */
#define GPIO_PORT_CLR7_CLRP028_Msk                            (0x01UL << GPIO_PORT_CLR7_CLRP028_Pos)                    /*!< GPIO_PORT CLR7: CLRP028 Mask        */
#define GPIO_PORT_CLR7_CLRP029_Pos                            29                                                        /*!< GPIO_PORT CLR7: CLRP029 Position    */
#define GPIO_PORT_CLR7_CLRP029_Msk                            (0x01UL << GPIO_PORT_CLR7_CLRP029_Pos)                    /*!< GPIO_PORT CLR7: CLRP029 Mask        */
#define GPIO_PORT_CLR7_CLRP030_Pos                            30                                                        /*!< GPIO_PORT CLR7: CLRP030 Position    */
#define GPIO_PORT_CLR7_CLRP030_Msk                            (0x01UL << GPIO_PORT_CLR7_CLRP030_Pos)                    /*!< GPIO_PORT CLR7: CLRP030 Mask        */
#define GPIO_PORT_CLR7_CLRP031_Pos                            31                                                        /*!< GPIO_PORT CLR7: CLRP031 Position    */
#define GPIO_PORT_CLR7_CLRP031_Msk                            (0x01UL << GPIO_PORT_CLR7_CLRP031_Pos)                    /*!< GPIO_PORT CLR7: CLRP031 Mask        */

// -------------------------------------  GPIO_PORT_NOT0  -----------------------------------------
#define GPIO_PORT_NOT0_NOTP0_Pos                              0                                                         /*!< GPIO_PORT NOT0: NOTP0 Position      */
#define GPIO_PORT_NOT0_NOTP0_Msk                              (0x01UL << GPIO_PORT_NOT0_NOTP0_Pos)                      /*!< GPIO_PORT NOT0: NOTP0 Mask          */
#define GPIO_PORT_NOT0_NOTP1_Pos                              1                                                         /*!< GPIO_PORT NOT0: NOTP1 Position      */
#define GPIO_PORT_NOT0_NOTP1_Msk                              (0x01UL << GPIO_PORT_NOT0_NOTP1_Pos)                      /*!< GPIO_PORT NOT0: NOTP1 Mask          */
#define GPIO_PORT_NOT0_NOTP2_Pos                              2                                                         /*!< GPIO_PORT NOT0: NOTP2 Position      */
#define GPIO_PORT_NOT0_NOTP2_Msk                              (0x01UL << GPIO_PORT_NOT0_NOTP2_Pos)                      /*!< GPIO_PORT NOT0: NOTP2 Mask          */
#define GPIO_PORT_NOT0_NOTP3_Pos                              3                                                         /*!< GPIO_PORT NOT0: NOTP3 Position      */
#define GPIO_PORT_NOT0_NOTP3_Msk                              (0x01UL << GPIO_PORT_NOT0_NOTP3_Pos)                      /*!< GPIO_PORT NOT0: NOTP3 Mask          */
#define GPIO_PORT_NOT0_NOTP4_Pos                              4                                                         /*!< GPIO_PORT NOT0: NOTP4 Position      */
#define GPIO_PORT_NOT0_NOTP4_Msk                              (0x01UL << GPIO_PORT_NOT0_NOTP4_Pos)                      /*!< GPIO_PORT NOT0: NOTP4 Mask          */
#define GPIO_PORT_NOT0_NOTP5_Pos                              5                                                         /*!< GPIO_PORT NOT0: NOTP5 Position      */
#define GPIO_PORT_NOT0_NOTP5_Msk                              (0x01UL << GPIO_PORT_NOT0_NOTP5_Pos)                      /*!< GPIO_PORT NOT0: NOTP5 Mask          */
#define GPIO_PORT_NOT0_NOTP6_Pos                              6                                                         /*!< GPIO_PORT NOT0: NOTP6 Position      */
#define GPIO_PORT_NOT0_NOTP6_Msk                              (0x01UL << GPIO_PORT_NOT0_NOTP6_Pos)                      /*!< GPIO_PORT NOT0: NOTP6 Mask          */
#define GPIO_PORT_NOT0_NOTP7_Pos                              7                                                         /*!< GPIO_PORT NOT0: NOTP7 Position      */
#define GPIO_PORT_NOT0_NOTP7_Msk                              (0x01UL << GPIO_PORT_NOT0_NOTP7_Pos)                      /*!< GPIO_PORT NOT0: NOTP7 Mask          */
#define GPIO_PORT_NOT0_NOTP8_Pos                              8                                                         /*!< GPIO_PORT NOT0: NOTP8 Position      */
#define GPIO_PORT_NOT0_NOTP8_Msk                              (0x01UL << GPIO_PORT_NOT0_NOTP8_Pos)                      /*!< GPIO_PORT NOT0: NOTP8 Mask          */
#define GPIO_PORT_NOT0_NOTP9_Pos                              9                                                         /*!< GPIO_PORT NOT0: NOTP9 Position      */
#define GPIO_PORT_NOT0_NOTP9_Msk                              (0x01UL << GPIO_PORT_NOT0_NOTP9_Pos)                      /*!< GPIO_PORT NOT0: NOTP9 Mask          */
#define GPIO_PORT_NOT0_NOTP10_Pos                             10                                                        /*!< GPIO_PORT NOT0: NOTP10 Position     */
#define GPIO_PORT_NOT0_NOTP10_Msk                             (0x01UL << GPIO_PORT_NOT0_NOTP10_Pos)                     /*!< GPIO_PORT NOT0: NOTP10 Mask         */
#define GPIO_PORT_NOT0_NOTP11_Pos                             11                                                        /*!< GPIO_PORT NOT0: NOTP11 Position     */
#define GPIO_PORT_NOT0_NOTP11_Msk                             (0x01UL << GPIO_PORT_NOT0_NOTP11_Pos)                     /*!< GPIO_PORT NOT0: NOTP11 Mask         */
#define GPIO_PORT_NOT0_NOTP12_Pos                             12                                                        /*!< GPIO_PORT NOT0: NOTP12 Position     */
#define GPIO_PORT_NOT0_NOTP12_Msk                             (0x01UL << GPIO_PORT_NOT0_NOTP12_Pos)                     /*!< GPIO_PORT NOT0: NOTP12 Mask         */
#define GPIO_PORT_NOT0_NOTP13_Pos                             13                                                        /*!< GPIO_PORT NOT0: NOTP13 Position     */
#define GPIO_PORT_NOT0_NOTP13_Msk                             (0x01UL << GPIO_PORT_NOT0_NOTP13_Pos)                     /*!< GPIO_PORT NOT0: NOTP13 Mask         */
#define GPIO_PORT_NOT0_NOTP14_Pos                             14                                                        /*!< GPIO_PORT NOT0: NOTP14 Position     */
#define GPIO_PORT_NOT0_NOTP14_Msk                             (0x01UL << GPIO_PORT_NOT0_NOTP14_Pos)                     /*!< GPIO_PORT NOT0: NOTP14 Mask         */
#define GPIO_PORT_NOT0_NOTP15_Pos                             15                                                        /*!< GPIO_PORT NOT0: NOTP15 Position     */
#define GPIO_PORT_NOT0_NOTP15_Msk                             (0x01UL << GPIO_PORT_NOT0_NOTP15_Pos)                     /*!< GPIO_PORT NOT0: NOTP15 Mask         */
#define GPIO_PORT_NOT0_NOTP16_Pos                             16                                                        /*!< GPIO_PORT NOT0: NOTP16 Position     */
#define GPIO_PORT_NOT0_NOTP16_Msk                             (0x01UL << GPIO_PORT_NOT0_NOTP16_Pos)                     /*!< GPIO_PORT NOT0: NOTP16 Mask         */
#define GPIO_PORT_NOT0_NOTP17_Pos                             17                                                        /*!< GPIO_PORT NOT0: NOTP17 Position     */
#define GPIO_PORT_NOT0_NOTP17_Msk                             (0x01UL << GPIO_PORT_NOT0_NOTP17_Pos)                     /*!< GPIO_PORT NOT0: NOTP17 Mask         */
#define GPIO_PORT_NOT0_NOTP18_Pos                             18                                                        /*!< GPIO_PORT NOT0: NOTP18 Position     */
#define GPIO_PORT_NOT0_NOTP18_Msk                             (0x01UL << GPIO_PORT_NOT0_NOTP18_Pos)                     /*!< GPIO_PORT NOT0: NOTP18 Mask         */
#define GPIO_PORT_NOT0_NOTP19_Pos                             19                                                        /*!< GPIO_PORT NOT0: NOTP19 Position     */
#define GPIO_PORT_NOT0_NOTP19_Msk                             (0x01UL << GPIO_PORT_NOT0_NOTP19_Pos)                     /*!< GPIO_PORT NOT0: NOTP19 Mask         */
#define GPIO_PORT_NOT0_NOTP20_Pos                             20                                                        /*!< GPIO_PORT NOT0: NOTP20 Position     */
#define GPIO_PORT_NOT0_NOTP20_Msk                             (0x01UL << GPIO_PORT_NOT0_NOTP20_Pos)                     /*!< GPIO_PORT NOT0: NOTP20 Mask         */
#define GPIO_PORT_NOT0_NOTP21_Pos                             21                                                        /*!< GPIO_PORT NOT0: NOTP21 Position     */
#define GPIO_PORT_NOT0_NOTP21_Msk                             (0x01UL << GPIO_PORT_NOT0_NOTP21_Pos)                     /*!< GPIO_PORT NOT0: NOTP21 Mask         */
#define GPIO_PORT_NOT0_NOTP22_Pos                             22                                                        /*!< GPIO_PORT NOT0: NOTP22 Position     */
#define GPIO_PORT_NOT0_NOTP22_Msk                             (0x01UL << GPIO_PORT_NOT0_NOTP22_Pos)                     /*!< GPIO_PORT NOT0: NOTP22 Mask         */
#define GPIO_PORT_NOT0_NOTP23_Pos                             23                                                        /*!< GPIO_PORT NOT0: NOTP23 Position     */
#define GPIO_PORT_NOT0_NOTP23_Msk                             (0x01UL << GPIO_PORT_NOT0_NOTP23_Pos)                     /*!< GPIO_PORT NOT0: NOTP23 Mask         */
#define GPIO_PORT_NOT0_NOTP24_Pos                             24                                                        /*!< GPIO_PORT NOT0: NOTP24 Position     */
#define GPIO_PORT_NOT0_NOTP24_Msk                             (0x01UL << GPIO_PORT_NOT0_NOTP24_Pos)                     /*!< GPIO_PORT NOT0: NOTP24 Mask         */
#define GPIO_PORT_NOT0_NOTP25_Pos                             25                                                        /*!< GPIO_PORT NOT0: NOTP25 Position     */
#define GPIO_PORT_NOT0_NOTP25_Msk                             (0x01UL << GPIO_PORT_NOT0_NOTP25_Pos)                     /*!< GPIO_PORT NOT0: NOTP25 Mask         */
#define GPIO_PORT_NOT0_NOTP26_Pos                             26                                                        /*!< GPIO_PORT NOT0: NOTP26 Position     */
#define GPIO_PORT_NOT0_NOTP26_Msk                             (0x01UL << GPIO_PORT_NOT0_NOTP26_Pos)                     /*!< GPIO_PORT NOT0: NOTP26 Mask         */
#define GPIO_PORT_NOT0_NOTP27_Pos                             27                                                        /*!< GPIO_PORT NOT0: NOTP27 Position     */
#define GPIO_PORT_NOT0_NOTP27_Msk                             (0x01UL << GPIO_PORT_NOT0_NOTP27_Pos)                     /*!< GPIO_PORT NOT0: NOTP27 Mask         */
#define GPIO_PORT_NOT0_NOTP28_Pos                             28                                                        /*!< GPIO_PORT NOT0: NOTP28 Position     */
#define GPIO_PORT_NOT0_NOTP28_Msk                             (0x01UL << GPIO_PORT_NOT0_NOTP28_Pos)                     /*!< GPIO_PORT NOT0: NOTP28 Mask         */
#define GPIO_PORT_NOT0_NOTP29_Pos                             29                                                        /*!< GPIO_PORT NOT0: NOTP29 Position     */
#define GPIO_PORT_NOT0_NOTP29_Msk                             (0x01UL << GPIO_PORT_NOT0_NOTP29_Pos)                     /*!< GPIO_PORT NOT0: NOTP29 Mask         */
#define GPIO_PORT_NOT0_NOTP30_Pos                             30                                                        /*!< GPIO_PORT NOT0: NOTP30 Position     */
#define GPIO_PORT_NOT0_NOTP30_Msk                             (0x01UL << GPIO_PORT_NOT0_NOTP30_Pos)                     /*!< GPIO_PORT NOT0: NOTP30 Mask         */
#define GPIO_PORT_NOT0_NOTP31_Pos                             31                                                        /*!< GPIO_PORT NOT0: NOTP31 Position     */
#define GPIO_PORT_NOT0_NOTP31_Msk                             (0x01UL << GPIO_PORT_NOT0_NOTP31_Pos)                     /*!< GPIO_PORT NOT0: NOTP31 Mask         */

// -------------------------------------  GPIO_PORT_NOT1  -----------------------------------------
#define GPIO_PORT_NOT1_NOTP0_Pos                              0                                                         /*!< GPIO_PORT NOT1: NOTP0 Position      */
#define GPIO_PORT_NOT1_NOTP0_Msk                              (0x01UL << GPIO_PORT_NOT1_NOTP0_Pos)                      /*!< GPIO_PORT NOT1: NOTP0 Mask          */
#define GPIO_PORT_NOT1_NOTP1_Pos                              1                                                         /*!< GPIO_PORT NOT1: NOTP1 Position      */
#define GPIO_PORT_NOT1_NOTP1_Msk                              (0x01UL << GPIO_PORT_NOT1_NOTP1_Pos)                      /*!< GPIO_PORT NOT1: NOTP1 Mask          */
#define GPIO_PORT_NOT1_NOTP2_Pos                              2                                                         /*!< GPIO_PORT NOT1: NOTP2 Position      */
#define GPIO_PORT_NOT1_NOTP2_Msk                              (0x01UL << GPIO_PORT_NOT1_NOTP2_Pos)                      /*!< GPIO_PORT NOT1: NOTP2 Mask          */
#define GPIO_PORT_NOT1_NOTP3_Pos                              3                                                         /*!< GPIO_PORT NOT1: NOTP3 Position      */
#define GPIO_PORT_NOT1_NOTP3_Msk                              (0x01UL << GPIO_PORT_NOT1_NOTP3_Pos)                      /*!< GPIO_PORT NOT1: NOTP3 Mask          */
#define GPIO_PORT_NOT1_NOTP4_Pos                              4                                                         /*!< GPIO_PORT NOT1: NOTP4 Position      */
#define GPIO_PORT_NOT1_NOTP4_Msk                              (0x01UL << GPIO_PORT_NOT1_NOTP4_Pos)                      /*!< GPIO_PORT NOT1: NOTP4 Mask          */
#define GPIO_PORT_NOT1_NOTP5_Pos                              5                                                         /*!< GPIO_PORT NOT1: NOTP5 Position      */
#define GPIO_PORT_NOT1_NOTP5_Msk                              (0x01UL << GPIO_PORT_NOT1_NOTP5_Pos)                      /*!< GPIO_PORT NOT1: NOTP5 Mask          */
#define GPIO_PORT_NOT1_NOTP6_Pos                              6                                                         /*!< GPIO_PORT NOT1: NOTP6 Position      */
#define GPIO_PORT_NOT1_NOTP6_Msk                              (0x01UL << GPIO_PORT_NOT1_NOTP6_Pos)                      /*!< GPIO_PORT NOT1: NOTP6 Mask          */
#define GPIO_PORT_NOT1_NOTP7_Pos                              7                                                         /*!< GPIO_PORT NOT1: NOTP7 Position      */
#define GPIO_PORT_NOT1_NOTP7_Msk                              (0x01UL << GPIO_PORT_NOT1_NOTP7_Pos)                      /*!< GPIO_PORT NOT1: NOTP7 Mask          */
#define GPIO_PORT_NOT1_NOTP8_Pos                              8                                                         /*!< GPIO_PORT NOT1: NOTP8 Position      */
#define GPIO_PORT_NOT1_NOTP8_Msk                              (0x01UL << GPIO_PORT_NOT1_NOTP8_Pos)                      /*!< GPIO_PORT NOT1: NOTP8 Mask          */
#define GPIO_PORT_NOT1_NOTP9_Pos                              9                                                         /*!< GPIO_PORT NOT1: NOTP9 Position      */
#define GPIO_PORT_NOT1_NOTP9_Msk                              (0x01UL << GPIO_PORT_NOT1_NOTP9_Pos)                      /*!< GPIO_PORT NOT1: NOTP9 Mask          */
#define GPIO_PORT_NOT1_NOTP10_Pos                             10                                                        /*!< GPIO_PORT NOT1: NOTP10 Position     */
#define GPIO_PORT_NOT1_NOTP10_Msk                             (0x01UL << GPIO_PORT_NOT1_NOTP10_Pos)                     /*!< GPIO_PORT NOT1: NOTP10 Mask         */
#define GPIO_PORT_NOT1_NOTP11_Pos                             11                                                        /*!< GPIO_PORT NOT1: NOTP11 Position     */
#define GPIO_PORT_NOT1_NOTP11_Msk                             (0x01UL << GPIO_PORT_NOT1_NOTP11_Pos)                     /*!< GPIO_PORT NOT1: NOTP11 Mask         */
#define GPIO_PORT_NOT1_NOTP12_Pos                             12                                                        /*!< GPIO_PORT NOT1: NOTP12 Position     */
#define GPIO_PORT_NOT1_NOTP12_Msk                             (0x01UL << GPIO_PORT_NOT1_NOTP12_Pos)                     /*!< GPIO_PORT NOT1: NOTP12 Mask         */
#define GPIO_PORT_NOT1_NOTP13_Pos                             13                                                        /*!< GPIO_PORT NOT1: NOTP13 Position     */
#define GPIO_PORT_NOT1_NOTP13_Msk                             (0x01UL << GPIO_PORT_NOT1_NOTP13_Pos)                     /*!< GPIO_PORT NOT1: NOTP13 Mask         */
#define GPIO_PORT_NOT1_NOTP14_Pos                             14                                                        /*!< GPIO_PORT NOT1: NOTP14 Position     */
#define GPIO_PORT_NOT1_NOTP14_Msk                             (0x01UL << GPIO_PORT_NOT1_NOTP14_Pos)                     /*!< GPIO_PORT NOT1: NOTP14 Mask         */
#define GPIO_PORT_NOT1_NOTP15_Pos                             15                                                        /*!< GPIO_PORT NOT1: NOTP15 Position     */
#define GPIO_PORT_NOT1_NOTP15_Msk                             (0x01UL << GPIO_PORT_NOT1_NOTP15_Pos)                     /*!< GPIO_PORT NOT1: NOTP15 Mask         */
#define GPIO_PORT_NOT1_NOTP16_Pos                             16                                                        /*!< GPIO_PORT NOT1: NOTP16 Position     */
#define GPIO_PORT_NOT1_NOTP16_Msk                             (0x01UL << GPIO_PORT_NOT1_NOTP16_Pos)                     /*!< GPIO_PORT NOT1: NOTP16 Mask         */
#define GPIO_PORT_NOT1_NOTP17_Pos                             17                                                        /*!< GPIO_PORT NOT1: NOTP17 Position     */
#define GPIO_PORT_NOT1_NOTP17_Msk                             (0x01UL << GPIO_PORT_NOT1_NOTP17_Pos)                     /*!< GPIO_PORT NOT1: NOTP17 Mask         */
#define GPIO_PORT_NOT1_NOTP18_Pos                             18                                                        /*!< GPIO_PORT NOT1: NOTP18 Position     */
#define GPIO_PORT_NOT1_NOTP18_Msk                             (0x01UL << GPIO_PORT_NOT1_NOTP18_Pos)                     /*!< GPIO_PORT NOT1: NOTP18 Mask         */
#define GPIO_PORT_NOT1_NOTP19_Pos                             19                                                        /*!< GPIO_PORT NOT1: NOTP19 Position     */
#define GPIO_PORT_NOT1_NOTP19_Msk                             (0x01UL << GPIO_PORT_NOT1_NOTP19_Pos)                     /*!< GPIO_PORT NOT1: NOTP19 Mask         */
#define GPIO_PORT_NOT1_NOTP20_Pos                             20                                                        /*!< GPIO_PORT NOT1: NOTP20 Position     */
#define GPIO_PORT_NOT1_NOTP20_Msk                             (0x01UL << GPIO_PORT_NOT1_NOTP20_Pos)                     /*!< GPIO_PORT NOT1: NOTP20 Mask         */
#define GPIO_PORT_NOT1_NOTP21_Pos                             21                                                        /*!< GPIO_PORT NOT1: NOTP21 Position     */
#define GPIO_PORT_NOT1_NOTP21_Msk                             (0x01UL << GPIO_PORT_NOT1_NOTP21_Pos)                     /*!< GPIO_PORT NOT1: NOTP21 Mask         */
#define GPIO_PORT_NOT1_NOTP22_Pos                             22                                                        /*!< GPIO_PORT NOT1: NOTP22 Position     */
#define GPIO_PORT_NOT1_NOTP22_Msk                             (0x01UL << GPIO_PORT_NOT1_NOTP22_Pos)                     /*!< GPIO_PORT NOT1: NOTP22 Mask         */
#define GPIO_PORT_NOT1_NOTP23_Pos                             23                                                        /*!< GPIO_PORT NOT1: NOTP23 Position     */
#define GPIO_PORT_NOT1_NOTP23_Msk                             (0x01UL << GPIO_PORT_NOT1_NOTP23_Pos)                     /*!< GPIO_PORT NOT1: NOTP23 Mask         */
#define GPIO_PORT_NOT1_NOTP24_Pos                             24                                                        /*!< GPIO_PORT NOT1: NOTP24 Position     */
#define GPIO_PORT_NOT1_NOTP24_Msk                             (0x01UL << GPIO_PORT_NOT1_NOTP24_Pos)                     /*!< GPIO_PORT NOT1: NOTP24 Mask         */
#define GPIO_PORT_NOT1_NOTP25_Pos                             25                                                        /*!< GPIO_PORT NOT1: NOTP25 Position     */
#define GPIO_PORT_NOT1_NOTP25_Msk                             (0x01UL << GPIO_PORT_NOT1_NOTP25_Pos)                     /*!< GPIO_PORT NOT1: NOTP25 Mask         */
#define GPIO_PORT_NOT1_NOTP26_Pos                             26                                                        /*!< GPIO_PORT NOT1: NOTP26 Position     */
#define GPIO_PORT_NOT1_NOTP26_Msk                             (0x01UL << GPIO_PORT_NOT1_NOTP26_Pos)                     /*!< GPIO_PORT NOT1: NOTP26 Mask         */
#define GPIO_PORT_NOT1_NOTP27_Pos                             27                                                        /*!< GPIO_PORT NOT1: NOTP27 Position     */
#define GPIO_PORT_NOT1_NOTP27_Msk                             (0x01UL << GPIO_PORT_NOT1_NOTP27_Pos)                     /*!< GPIO_PORT NOT1: NOTP27 Mask         */
#define GPIO_PORT_NOT1_NOTP28_Pos                             28                                                        /*!< GPIO_PORT NOT1: NOTP28 Position     */
#define GPIO_PORT_NOT1_NOTP28_Msk                             (0x01UL << GPIO_PORT_NOT1_NOTP28_Pos)                     /*!< GPIO_PORT NOT1: NOTP28 Mask         */
#define GPIO_PORT_NOT1_NOTP29_Pos                             29                                                        /*!< GPIO_PORT NOT1: NOTP29 Position     */
#define GPIO_PORT_NOT1_NOTP29_Msk                             (0x01UL << GPIO_PORT_NOT1_NOTP29_Pos)                     /*!< GPIO_PORT NOT1: NOTP29 Mask         */
#define GPIO_PORT_NOT1_NOTP30_Pos                             30                                                        /*!< GPIO_PORT NOT1: NOTP30 Position     */
#define GPIO_PORT_NOT1_NOTP30_Msk                             (0x01UL << GPIO_PORT_NOT1_NOTP30_Pos)                     /*!< GPIO_PORT NOT1: NOTP30 Mask         */
#define GPIO_PORT_NOT1_NOTP31_Pos                             31                                                        /*!< GPIO_PORT NOT1: NOTP31 Position     */
#define GPIO_PORT_NOT1_NOTP31_Msk                             (0x01UL << GPIO_PORT_NOT1_NOTP31_Pos)                     /*!< GPIO_PORT NOT1: NOTP31 Mask         */

// -------------------------------------  GPIO_PORT_NOT2  -----------------------------------------
#define GPIO_PORT_NOT2_NOTP0_Pos                              0                                                         /*!< GPIO_PORT NOT2: NOTP0 Position      */
#define GPIO_PORT_NOT2_NOTP0_Msk                              (0x01UL << GPIO_PORT_NOT2_NOTP0_Pos)                      /*!< GPIO_PORT NOT2: NOTP0 Mask          */
#define GPIO_PORT_NOT2_NOTP1_Pos                              1                                                         /*!< GPIO_PORT NOT2: NOTP1 Position      */
#define GPIO_PORT_NOT2_NOTP1_Msk                              (0x01UL << GPIO_PORT_NOT2_NOTP1_Pos)                      /*!< GPIO_PORT NOT2: NOTP1 Mask          */
#define GPIO_PORT_NOT2_NOTP2_Pos                              2                                                         /*!< GPIO_PORT NOT2: NOTP2 Position      */
#define GPIO_PORT_NOT2_NOTP2_Msk                              (0x01UL << GPIO_PORT_NOT2_NOTP2_Pos)                      /*!< GPIO_PORT NOT2: NOTP2 Mask          */
#define GPIO_PORT_NOT2_NOTP3_Pos                              3                                                         /*!< GPIO_PORT NOT2: NOTP3 Position      */
#define GPIO_PORT_NOT2_NOTP3_Msk                              (0x01UL << GPIO_PORT_NOT2_NOTP3_Pos)                      /*!< GPIO_PORT NOT2: NOTP3 Mask          */
#define GPIO_PORT_NOT2_NOTP4_Pos                              4                                                         /*!< GPIO_PORT NOT2: NOTP4 Position      */
#define GPIO_PORT_NOT2_NOTP4_Msk                              (0x01UL << GPIO_PORT_NOT2_NOTP4_Pos)                      /*!< GPIO_PORT NOT2: NOTP4 Mask          */
#define GPIO_PORT_NOT2_NOTP5_Pos                              5                                                         /*!< GPIO_PORT NOT2: NOTP5 Position      */
#define GPIO_PORT_NOT2_NOTP5_Msk                              (0x01UL << GPIO_PORT_NOT2_NOTP5_Pos)                      /*!< GPIO_PORT NOT2: NOTP5 Mask          */
#define GPIO_PORT_NOT2_NOTP6_Pos                              6                                                         /*!< GPIO_PORT NOT2: NOTP6 Position      */
#define GPIO_PORT_NOT2_NOTP6_Msk                              (0x01UL << GPIO_PORT_NOT2_NOTP6_Pos)                      /*!< GPIO_PORT NOT2: NOTP6 Mask          */
#define GPIO_PORT_NOT2_NOTP7_Pos                              7                                                         /*!< GPIO_PORT NOT2: NOTP7 Position      */
#define GPIO_PORT_NOT2_NOTP7_Msk                              (0x01UL << GPIO_PORT_NOT2_NOTP7_Pos)                      /*!< GPIO_PORT NOT2: NOTP7 Mask          */
#define GPIO_PORT_NOT2_NOTP8_Pos                              8                                                         /*!< GPIO_PORT NOT2: NOTP8 Position      */
#define GPIO_PORT_NOT2_NOTP8_Msk                              (0x01UL << GPIO_PORT_NOT2_NOTP8_Pos)                      /*!< GPIO_PORT NOT2: NOTP8 Mask          */
#define GPIO_PORT_NOT2_NOTP9_Pos                              9                                                         /*!< GPIO_PORT NOT2: NOTP9 Position      */
#define GPIO_PORT_NOT2_NOTP9_Msk                              (0x01UL << GPIO_PORT_NOT2_NOTP9_Pos)                      /*!< GPIO_PORT NOT2: NOTP9 Mask          */
#define GPIO_PORT_NOT2_NOTP10_Pos                             10                                                        /*!< GPIO_PORT NOT2: NOTP10 Position     */
#define GPIO_PORT_NOT2_NOTP10_Msk                             (0x01UL << GPIO_PORT_NOT2_NOTP10_Pos)                     /*!< GPIO_PORT NOT2: NOTP10 Mask         */
#define GPIO_PORT_NOT2_NOTP11_Pos                             11                                                        /*!< GPIO_PORT NOT2: NOTP11 Position     */
#define GPIO_PORT_NOT2_NOTP11_Msk                             (0x01UL << GPIO_PORT_NOT2_NOTP11_Pos)                     /*!< GPIO_PORT NOT2: NOTP11 Mask         */
#define GPIO_PORT_NOT2_NOTP12_Pos                             12                                                        /*!< GPIO_PORT NOT2: NOTP12 Position     */
#define GPIO_PORT_NOT2_NOTP12_Msk                             (0x01UL << GPIO_PORT_NOT2_NOTP12_Pos)                     /*!< GPIO_PORT NOT2: NOTP12 Mask         */
#define GPIO_PORT_NOT2_NOTP13_Pos                             13                                                        /*!< GPIO_PORT NOT2: NOTP13 Position     */
#define GPIO_PORT_NOT2_NOTP13_Msk                             (0x01UL << GPIO_PORT_NOT2_NOTP13_Pos)                     /*!< GPIO_PORT NOT2: NOTP13 Mask         */
#define GPIO_PORT_NOT2_NOTP14_Pos                             14                                                        /*!< GPIO_PORT NOT2: NOTP14 Position     */
#define GPIO_PORT_NOT2_NOTP14_Msk                             (0x01UL << GPIO_PORT_NOT2_NOTP14_Pos)                     /*!< GPIO_PORT NOT2: NOTP14 Mask         */
#define GPIO_PORT_NOT2_NOTP15_Pos                             15                                                        /*!< GPIO_PORT NOT2: NOTP15 Position     */
#define GPIO_PORT_NOT2_NOTP15_Msk                             (0x01UL << GPIO_PORT_NOT2_NOTP15_Pos)                     /*!< GPIO_PORT NOT2: NOTP15 Mask         */
#define GPIO_PORT_NOT2_NOTP16_Pos                             16                                                        /*!< GPIO_PORT NOT2: NOTP16 Position     */
#define GPIO_PORT_NOT2_NOTP16_Msk                             (0x01UL << GPIO_PORT_NOT2_NOTP16_Pos)                     /*!< GPIO_PORT NOT2: NOTP16 Mask         */
#define GPIO_PORT_NOT2_NOTP17_Pos                             17                                                        /*!< GPIO_PORT NOT2: NOTP17 Position     */
#define GPIO_PORT_NOT2_NOTP17_Msk                             (0x01UL << GPIO_PORT_NOT2_NOTP17_Pos)                     /*!< GPIO_PORT NOT2: NOTP17 Mask         */
#define GPIO_PORT_NOT2_NOTP18_Pos                             18                                                        /*!< GPIO_PORT NOT2: NOTP18 Position     */
#define GPIO_PORT_NOT2_NOTP18_Msk                             (0x01UL << GPIO_PORT_NOT2_NOTP18_Pos)                     /*!< GPIO_PORT NOT2: NOTP18 Mask         */
#define GPIO_PORT_NOT2_NOTP19_Pos                             19                                                        /*!< GPIO_PORT NOT2: NOTP19 Position     */
#define GPIO_PORT_NOT2_NOTP19_Msk                             (0x01UL << GPIO_PORT_NOT2_NOTP19_Pos)                     /*!< GPIO_PORT NOT2: NOTP19 Mask         */
#define GPIO_PORT_NOT2_NOTP20_Pos                             20                                                        /*!< GPIO_PORT NOT2: NOTP20 Position     */
#define GPIO_PORT_NOT2_NOTP20_Msk                             (0x01UL << GPIO_PORT_NOT2_NOTP20_Pos)                     /*!< GPIO_PORT NOT2: NOTP20 Mask         */
#define GPIO_PORT_NOT2_NOTP21_Pos                             21                                                        /*!< GPIO_PORT NOT2: NOTP21 Position     */
#define GPIO_PORT_NOT2_NOTP21_Msk                             (0x01UL << GPIO_PORT_NOT2_NOTP21_Pos)                     /*!< GPIO_PORT NOT2: NOTP21 Mask         */
#define GPIO_PORT_NOT2_NOTP22_Pos                             22                                                        /*!< GPIO_PORT NOT2: NOTP22 Position     */
#define GPIO_PORT_NOT2_NOTP22_Msk                             (0x01UL << GPIO_PORT_NOT2_NOTP22_Pos)                     /*!< GPIO_PORT NOT2: NOTP22 Mask         */
#define GPIO_PORT_NOT2_NOTP23_Pos                             23                                                        /*!< GPIO_PORT NOT2: NOTP23 Position     */
#define GPIO_PORT_NOT2_NOTP23_Msk                             (0x01UL << GPIO_PORT_NOT2_NOTP23_Pos)                     /*!< GPIO_PORT NOT2: NOTP23 Mask         */
#define GPIO_PORT_NOT2_NOTP24_Pos                             24                                                        /*!< GPIO_PORT NOT2: NOTP24 Position     */
#define GPIO_PORT_NOT2_NOTP24_Msk                             (0x01UL << GPIO_PORT_NOT2_NOTP24_Pos)                     /*!< GPIO_PORT NOT2: NOTP24 Mask         */
#define GPIO_PORT_NOT2_NOTP25_Pos                             25                                                        /*!< GPIO_PORT NOT2: NOTP25 Position     */
#define GPIO_PORT_NOT2_NOTP25_Msk                             (0x01UL << GPIO_PORT_NOT2_NOTP25_Pos)                     /*!< GPIO_PORT NOT2: NOTP25 Mask         */
#define GPIO_PORT_NOT2_NOTP26_Pos                             26                                                        /*!< GPIO_PORT NOT2: NOTP26 Position     */
#define GPIO_PORT_NOT2_NOTP26_Msk                             (0x01UL << GPIO_PORT_NOT2_NOTP26_Pos)                     /*!< GPIO_PORT NOT2: NOTP26 Mask         */
#define GPIO_PORT_NOT2_NOTP27_Pos                             27                                                        /*!< GPIO_PORT NOT2: NOTP27 Position     */
#define GPIO_PORT_NOT2_NOTP27_Msk                             (0x01UL << GPIO_PORT_NOT2_NOTP27_Pos)                     /*!< GPIO_PORT NOT2: NOTP27 Mask         */
#define GPIO_PORT_NOT2_NOTP28_Pos                             28                                                        /*!< GPIO_PORT NOT2: NOTP28 Position     */
#define GPIO_PORT_NOT2_NOTP28_Msk                             (0x01UL << GPIO_PORT_NOT2_NOTP28_Pos)                     /*!< GPIO_PORT NOT2: NOTP28 Mask         */
#define GPIO_PORT_NOT2_NOTP29_Pos                             29                                                        /*!< GPIO_PORT NOT2: NOTP29 Position     */
#define GPIO_PORT_NOT2_NOTP29_Msk                             (0x01UL << GPIO_PORT_NOT2_NOTP29_Pos)                     /*!< GPIO_PORT NOT2: NOTP29 Mask         */
#define GPIO_PORT_NOT2_NOTP30_Pos                             30                                                        /*!< GPIO_PORT NOT2: NOTP30 Position     */
#define GPIO_PORT_NOT2_NOTP30_Msk                             (0x01UL << GPIO_PORT_NOT2_NOTP30_Pos)                     /*!< GPIO_PORT NOT2: NOTP30 Mask         */
#define GPIO_PORT_NOT2_NOTP31_Pos                             31                                                        /*!< GPIO_PORT NOT2: NOTP31 Position     */
#define GPIO_PORT_NOT2_NOTP31_Msk                             (0x01UL << GPIO_PORT_NOT2_NOTP31_Pos)                     /*!< GPIO_PORT NOT2: NOTP31 Mask         */

// -------------------------------------  GPIO_PORT_NOT3  -----------------------------------------
#define GPIO_PORT_NOT3_NOTP0_Pos                              0                                                         /*!< GPIO_PORT NOT3: NOTP0 Position      */
#define GPIO_PORT_NOT3_NOTP0_Msk                              (0x01UL << GPIO_PORT_NOT3_NOTP0_Pos)                      /*!< GPIO_PORT NOT3: NOTP0 Mask          */
#define GPIO_PORT_NOT3_NOTP1_Pos                              1                                                         /*!< GPIO_PORT NOT3: NOTP1 Position      */
#define GPIO_PORT_NOT3_NOTP1_Msk                              (0x01UL << GPIO_PORT_NOT3_NOTP1_Pos)                      /*!< GPIO_PORT NOT3: NOTP1 Mask          */
#define GPIO_PORT_NOT3_NOTP2_Pos                              2                                                         /*!< GPIO_PORT NOT3: NOTP2 Position      */
#define GPIO_PORT_NOT3_NOTP2_Msk                              (0x01UL << GPIO_PORT_NOT3_NOTP2_Pos)                      /*!< GPIO_PORT NOT3: NOTP2 Mask          */
#define GPIO_PORT_NOT3_NOTP3_Pos                              3                                                         /*!< GPIO_PORT NOT3: NOTP3 Position      */
#define GPIO_PORT_NOT3_NOTP3_Msk                              (0x01UL << GPIO_PORT_NOT3_NOTP3_Pos)                      /*!< GPIO_PORT NOT3: NOTP3 Mask          */
#define GPIO_PORT_NOT3_NOTP4_Pos                              4                                                         /*!< GPIO_PORT NOT3: NOTP4 Position      */
#define GPIO_PORT_NOT3_NOTP4_Msk                              (0x01UL << GPIO_PORT_NOT3_NOTP4_Pos)                      /*!< GPIO_PORT NOT3: NOTP4 Mask          */
#define GPIO_PORT_NOT3_NOTP5_Pos                              5                                                         /*!< GPIO_PORT NOT3: NOTP5 Position      */
#define GPIO_PORT_NOT3_NOTP5_Msk                              (0x01UL << GPIO_PORT_NOT3_NOTP5_Pos)                      /*!< GPIO_PORT NOT3: NOTP5 Mask          */
#define GPIO_PORT_NOT3_NOTP6_Pos                              6                                                         /*!< GPIO_PORT NOT3: NOTP6 Position      */
#define GPIO_PORT_NOT3_NOTP6_Msk                              (0x01UL << GPIO_PORT_NOT3_NOTP6_Pos)                      /*!< GPIO_PORT NOT3: NOTP6 Mask          */
#define GPIO_PORT_NOT3_NOTP7_Pos                              7                                                         /*!< GPIO_PORT NOT3: NOTP7 Position      */
#define GPIO_PORT_NOT3_NOTP7_Msk                              (0x01UL << GPIO_PORT_NOT3_NOTP7_Pos)                      /*!< GPIO_PORT NOT3: NOTP7 Mask          */
#define GPIO_PORT_NOT3_NOTP8_Pos                              8                                                         /*!< GPIO_PORT NOT3: NOTP8 Position      */
#define GPIO_PORT_NOT3_NOTP8_Msk                              (0x01UL << GPIO_PORT_NOT3_NOTP8_Pos)                      /*!< GPIO_PORT NOT3: NOTP8 Mask          */
#define GPIO_PORT_NOT3_NOTP9_Pos                              9                                                         /*!< GPIO_PORT NOT3: NOTP9 Position      */
#define GPIO_PORT_NOT3_NOTP9_Msk                              (0x01UL << GPIO_PORT_NOT3_NOTP9_Pos)                      /*!< GPIO_PORT NOT3: NOTP9 Mask          */
#define GPIO_PORT_NOT3_NOTP10_Pos                             10                                                        /*!< GPIO_PORT NOT3: NOTP10 Position     */
#define GPIO_PORT_NOT3_NOTP10_Msk                             (0x01UL << GPIO_PORT_NOT3_NOTP10_Pos)                     /*!< GPIO_PORT NOT3: NOTP10 Mask         */
#define GPIO_PORT_NOT3_NOTP11_Pos                             11                                                        /*!< GPIO_PORT NOT3: NOTP11 Position     */
#define GPIO_PORT_NOT3_NOTP11_Msk                             (0x01UL << GPIO_PORT_NOT3_NOTP11_Pos)                     /*!< GPIO_PORT NOT3: NOTP11 Mask         */
#define GPIO_PORT_NOT3_NOTP12_Pos                             12                                                        /*!< GPIO_PORT NOT3: NOTP12 Position     */
#define GPIO_PORT_NOT3_NOTP12_Msk                             (0x01UL << GPIO_PORT_NOT3_NOTP12_Pos)                     /*!< GPIO_PORT NOT3: NOTP12 Mask         */
#define GPIO_PORT_NOT3_NOTP13_Pos                             13                                                        /*!< GPIO_PORT NOT3: NOTP13 Position     */
#define GPIO_PORT_NOT3_NOTP13_Msk                             (0x01UL << GPIO_PORT_NOT3_NOTP13_Pos)                     /*!< GPIO_PORT NOT3: NOTP13 Mask         */
#define GPIO_PORT_NOT3_NOTP14_Pos                             14                                                        /*!< GPIO_PORT NOT3: NOTP14 Position     */
#define GPIO_PORT_NOT3_NOTP14_Msk                             (0x01UL << GPIO_PORT_NOT3_NOTP14_Pos)                     /*!< GPIO_PORT NOT3: NOTP14 Mask         */
#define GPIO_PORT_NOT3_NOTP15_Pos                             15                                                        /*!< GPIO_PORT NOT3: NOTP15 Position     */
#define GPIO_PORT_NOT3_NOTP15_Msk                             (0x01UL << GPIO_PORT_NOT3_NOTP15_Pos)                     /*!< GPIO_PORT NOT3: NOTP15 Mask         */
#define GPIO_PORT_NOT3_NOTP16_Pos                             16                                                        /*!< GPIO_PORT NOT3: NOTP16 Position     */
#define GPIO_PORT_NOT3_NOTP16_Msk                             (0x01UL << GPIO_PORT_NOT3_NOTP16_Pos)                     /*!< GPIO_PORT NOT3: NOTP16 Mask         */
#define GPIO_PORT_NOT3_NOTP17_Pos                             17                                                        /*!< GPIO_PORT NOT3: NOTP17 Position     */
#define GPIO_PORT_NOT3_NOTP17_Msk                             (0x01UL << GPIO_PORT_NOT3_NOTP17_Pos)                     /*!< GPIO_PORT NOT3: NOTP17 Mask         */
#define GPIO_PORT_NOT3_NOTP18_Pos                             18                                                        /*!< GPIO_PORT NOT3: NOTP18 Position     */
#define GPIO_PORT_NOT3_NOTP18_Msk                             (0x01UL << GPIO_PORT_NOT3_NOTP18_Pos)                     /*!< GPIO_PORT NOT3: NOTP18 Mask         */
#define GPIO_PORT_NOT3_NOTP19_Pos                             19                                                        /*!< GPIO_PORT NOT3: NOTP19 Position     */
#define GPIO_PORT_NOT3_NOTP19_Msk                             (0x01UL << GPIO_PORT_NOT3_NOTP19_Pos)                     /*!< GPIO_PORT NOT3: NOTP19 Mask         */
#define GPIO_PORT_NOT3_NOTP20_Pos                             20                                                        /*!< GPIO_PORT NOT3: NOTP20 Position     */
#define GPIO_PORT_NOT3_NOTP20_Msk                             (0x01UL << GPIO_PORT_NOT3_NOTP20_Pos)                     /*!< GPIO_PORT NOT3: NOTP20 Mask         */
#define GPIO_PORT_NOT3_NOTP21_Pos                             21                                                        /*!< GPIO_PORT NOT3: NOTP21 Position     */
#define GPIO_PORT_NOT3_NOTP21_Msk                             (0x01UL << GPIO_PORT_NOT3_NOTP21_Pos)                     /*!< GPIO_PORT NOT3: NOTP21 Mask         */
#define GPIO_PORT_NOT3_NOTP22_Pos                             22                                                        /*!< GPIO_PORT NOT3: NOTP22 Position     */
#define GPIO_PORT_NOT3_NOTP22_Msk                             (0x01UL << GPIO_PORT_NOT3_NOTP22_Pos)                     /*!< GPIO_PORT NOT3: NOTP22 Mask         */
#define GPIO_PORT_NOT3_NOTP23_Pos                             23                                                        /*!< GPIO_PORT NOT3: NOTP23 Position     */
#define GPIO_PORT_NOT3_NOTP23_Msk                             (0x01UL << GPIO_PORT_NOT3_NOTP23_Pos)                     /*!< GPIO_PORT NOT3: NOTP23 Mask         */
#define GPIO_PORT_NOT3_NOTP24_Pos                             24                                                        /*!< GPIO_PORT NOT3: NOTP24 Position     */
#define GPIO_PORT_NOT3_NOTP24_Msk                             (0x01UL << GPIO_PORT_NOT3_NOTP24_Pos)                     /*!< GPIO_PORT NOT3: NOTP24 Mask         */
#define GPIO_PORT_NOT3_NOTP25_Pos                             25                                                        /*!< GPIO_PORT NOT3: NOTP25 Position     */
#define GPIO_PORT_NOT3_NOTP25_Msk                             (0x01UL << GPIO_PORT_NOT3_NOTP25_Pos)                     /*!< GPIO_PORT NOT3: NOTP25 Mask         */
#define GPIO_PORT_NOT3_NOTP26_Pos                             26                                                        /*!< GPIO_PORT NOT3: NOTP26 Position     */
#define GPIO_PORT_NOT3_NOTP26_Msk                             (0x01UL << GPIO_PORT_NOT3_NOTP26_Pos)                     /*!< GPIO_PORT NOT3: NOTP26 Mask         */
#define GPIO_PORT_NOT3_NOTP27_Pos                             27                                                        /*!< GPIO_PORT NOT3: NOTP27 Position     */
#define GPIO_PORT_NOT3_NOTP27_Msk                             (0x01UL << GPIO_PORT_NOT3_NOTP27_Pos)                     /*!< GPIO_PORT NOT3: NOTP27 Mask         */
#define GPIO_PORT_NOT3_NOTP28_Pos                             28                                                        /*!< GPIO_PORT NOT3: NOTP28 Position     */
#define GPIO_PORT_NOT3_NOTP28_Msk                             (0x01UL << GPIO_PORT_NOT3_NOTP28_Pos)                     /*!< GPIO_PORT NOT3: NOTP28 Mask         */
#define GPIO_PORT_NOT3_NOTP29_Pos                             29                                                        /*!< GPIO_PORT NOT3: NOTP29 Position     */
#define GPIO_PORT_NOT3_NOTP29_Msk                             (0x01UL << GPIO_PORT_NOT3_NOTP29_Pos)                     /*!< GPIO_PORT NOT3: NOTP29 Mask         */
#define GPIO_PORT_NOT3_NOTP30_Pos                             30                                                        /*!< GPIO_PORT NOT3: NOTP30 Position     */
#define GPIO_PORT_NOT3_NOTP30_Msk                             (0x01UL << GPIO_PORT_NOT3_NOTP30_Pos)                     /*!< GPIO_PORT NOT3: NOTP30 Mask         */
#define GPIO_PORT_NOT3_NOTP31_Pos                             31                                                        /*!< GPIO_PORT NOT3: NOTP31 Position     */
#define GPIO_PORT_NOT3_NOTP31_Msk                             (0x01UL << GPIO_PORT_NOT3_NOTP31_Pos)                     /*!< GPIO_PORT NOT3: NOTP31 Mask         */

// -------------------------------------  GPIO_PORT_NOT4  -----------------------------------------
#define GPIO_PORT_NOT4_NOTP0_Pos                              0                                                         /*!< GPIO_PORT NOT4: NOTP0 Position      */
#define GPIO_PORT_NOT4_NOTP0_Msk                              (0x01UL << GPIO_PORT_NOT4_NOTP0_Pos)                      /*!< GPIO_PORT NOT4: NOTP0 Mask          */
#define GPIO_PORT_NOT4_NOTP1_Pos                              1                                                         /*!< GPIO_PORT NOT4: NOTP1 Position      */
#define GPIO_PORT_NOT4_NOTP1_Msk                              (0x01UL << GPIO_PORT_NOT4_NOTP1_Pos)                      /*!< GPIO_PORT NOT4: NOTP1 Mask          */
#define GPIO_PORT_NOT4_NOTP2_Pos                              2                                                         /*!< GPIO_PORT NOT4: NOTP2 Position      */
#define GPIO_PORT_NOT4_NOTP2_Msk                              (0x01UL << GPIO_PORT_NOT4_NOTP2_Pos)                      /*!< GPIO_PORT NOT4: NOTP2 Mask          */
#define GPIO_PORT_NOT4_NOTP3_Pos                              3                                                         /*!< GPIO_PORT NOT4: NOTP3 Position      */
#define GPIO_PORT_NOT4_NOTP3_Msk                              (0x01UL << GPIO_PORT_NOT4_NOTP3_Pos)                      /*!< GPIO_PORT NOT4: NOTP3 Mask          */
#define GPIO_PORT_NOT4_NOTP4_Pos                              4                                                         /*!< GPIO_PORT NOT4: NOTP4 Position      */
#define GPIO_PORT_NOT4_NOTP4_Msk                              (0x01UL << GPIO_PORT_NOT4_NOTP4_Pos)                      /*!< GPIO_PORT NOT4: NOTP4 Mask          */
#define GPIO_PORT_NOT4_NOTP5_Pos                              5                                                         /*!< GPIO_PORT NOT4: NOTP5 Position      */
#define GPIO_PORT_NOT4_NOTP5_Msk                              (0x01UL << GPIO_PORT_NOT4_NOTP5_Pos)                      /*!< GPIO_PORT NOT4: NOTP5 Mask          */
#define GPIO_PORT_NOT4_NOTP6_Pos                              6                                                         /*!< GPIO_PORT NOT4: NOTP6 Position      */
#define GPIO_PORT_NOT4_NOTP6_Msk                              (0x01UL << GPIO_PORT_NOT4_NOTP6_Pos)                      /*!< GPIO_PORT NOT4: NOTP6 Mask          */
#define GPIO_PORT_NOT4_NOTP7_Pos                              7                                                         /*!< GPIO_PORT NOT4: NOTP7 Position      */
#define GPIO_PORT_NOT4_NOTP7_Msk                              (0x01UL << GPIO_PORT_NOT4_NOTP7_Pos)                      /*!< GPIO_PORT NOT4: NOTP7 Mask          */
#define GPIO_PORT_NOT4_NOTP8_Pos                              8                                                         /*!< GPIO_PORT NOT4: NOTP8 Position      */
#define GPIO_PORT_NOT4_NOTP8_Msk                              (0x01UL << GPIO_PORT_NOT4_NOTP8_Pos)                      /*!< GPIO_PORT NOT4: NOTP8 Mask          */
#define GPIO_PORT_NOT4_NOTP9_Pos                              9                                                         /*!< GPIO_PORT NOT4: NOTP9 Position      */
#define GPIO_PORT_NOT4_NOTP9_Msk                              (0x01UL << GPIO_PORT_NOT4_NOTP9_Pos)                      /*!< GPIO_PORT NOT4: NOTP9 Mask          */
#define GPIO_PORT_NOT4_NOTP10_Pos                             10                                                        /*!< GPIO_PORT NOT4: NOTP10 Position     */
#define GPIO_PORT_NOT4_NOTP10_Msk                             (0x01UL << GPIO_PORT_NOT4_NOTP10_Pos)                     /*!< GPIO_PORT NOT4: NOTP10 Mask         */
#define GPIO_PORT_NOT4_NOTP11_Pos                             11                                                        /*!< GPIO_PORT NOT4: NOTP11 Position     */
#define GPIO_PORT_NOT4_NOTP11_Msk                             (0x01UL << GPIO_PORT_NOT4_NOTP11_Pos)                     /*!< GPIO_PORT NOT4: NOTP11 Mask         */
#define GPIO_PORT_NOT4_NOTP12_Pos                             12                                                        /*!< GPIO_PORT NOT4: NOTP12 Position     */
#define GPIO_PORT_NOT4_NOTP12_Msk                             (0x01UL << GPIO_PORT_NOT4_NOTP12_Pos)                     /*!< GPIO_PORT NOT4: NOTP12 Mask         */
#define GPIO_PORT_NOT4_NOTP13_Pos                             13                                                        /*!< GPIO_PORT NOT4: NOTP13 Position     */
#define GPIO_PORT_NOT4_NOTP13_Msk                             (0x01UL << GPIO_PORT_NOT4_NOTP13_Pos)                     /*!< GPIO_PORT NOT4: NOTP13 Mask         */
#define GPIO_PORT_NOT4_NOTP14_Pos                             14                                                        /*!< GPIO_PORT NOT4: NOTP14 Position     */
#define GPIO_PORT_NOT4_NOTP14_Msk                             (0x01UL << GPIO_PORT_NOT4_NOTP14_Pos)                     /*!< GPIO_PORT NOT4: NOTP14 Mask         */
#define GPIO_PORT_NOT4_NOTP15_Pos                             15                                                        /*!< GPIO_PORT NOT4: NOTP15 Position     */
#define GPIO_PORT_NOT4_NOTP15_Msk                             (0x01UL << GPIO_PORT_NOT4_NOTP15_Pos)                     /*!< GPIO_PORT NOT4: NOTP15 Mask         */
#define GPIO_PORT_NOT4_NOTP16_Pos                             16                                                        /*!< GPIO_PORT NOT4: NOTP16 Position     */
#define GPIO_PORT_NOT4_NOTP16_Msk                             (0x01UL << GPIO_PORT_NOT4_NOTP16_Pos)                     /*!< GPIO_PORT NOT4: NOTP16 Mask         */
#define GPIO_PORT_NOT4_NOTP17_Pos                             17                                                        /*!< GPIO_PORT NOT4: NOTP17 Position     */
#define GPIO_PORT_NOT4_NOTP17_Msk                             (0x01UL << GPIO_PORT_NOT4_NOTP17_Pos)                     /*!< GPIO_PORT NOT4: NOTP17 Mask         */
#define GPIO_PORT_NOT4_NOTP18_Pos                             18                                                        /*!< GPIO_PORT NOT4: NOTP18 Position     */
#define GPIO_PORT_NOT4_NOTP18_Msk                             (0x01UL << GPIO_PORT_NOT4_NOTP18_Pos)                     /*!< GPIO_PORT NOT4: NOTP18 Mask         */
#define GPIO_PORT_NOT4_NOTP19_Pos                             19                                                        /*!< GPIO_PORT NOT4: NOTP19 Position     */
#define GPIO_PORT_NOT4_NOTP19_Msk                             (0x01UL << GPIO_PORT_NOT4_NOTP19_Pos)                     /*!< GPIO_PORT NOT4: NOTP19 Mask         */
#define GPIO_PORT_NOT4_NOTP20_Pos                             20                                                        /*!< GPIO_PORT NOT4: NOTP20 Position     */
#define GPIO_PORT_NOT4_NOTP20_Msk                             (0x01UL << GPIO_PORT_NOT4_NOTP20_Pos)                     /*!< GPIO_PORT NOT4: NOTP20 Mask         */
#define GPIO_PORT_NOT4_NOTP21_Pos                             21                                                        /*!< GPIO_PORT NOT4: NOTP21 Position     */
#define GPIO_PORT_NOT4_NOTP21_Msk                             (0x01UL << GPIO_PORT_NOT4_NOTP21_Pos)                     /*!< GPIO_PORT NOT4: NOTP21 Mask         */
#define GPIO_PORT_NOT4_NOTP22_Pos                             22                                                        /*!< GPIO_PORT NOT4: NOTP22 Position     */
#define GPIO_PORT_NOT4_NOTP22_Msk                             (0x01UL << GPIO_PORT_NOT4_NOTP22_Pos)                     /*!< GPIO_PORT NOT4: NOTP22 Mask         */
#define GPIO_PORT_NOT4_NOTP23_Pos                             23                                                        /*!< GPIO_PORT NOT4: NOTP23 Position     */
#define GPIO_PORT_NOT4_NOTP23_Msk                             (0x01UL << GPIO_PORT_NOT4_NOTP23_Pos)                     /*!< GPIO_PORT NOT4: NOTP23 Mask         */
#define GPIO_PORT_NOT4_NOTP24_Pos                             24                                                        /*!< GPIO_PORT NOT4: NOTP24 Position     */
#define GPIO_PORT_NOT4_NOTP24_Msk                             (0x01UL << GPIO_PORT_NOT4_NOTP24_Pos)                     /*!< GPIO_PORT NOT4: NOTP24 Mask         */
#define GPIO_PORT_NOT4_NOTP25_Pos                             25                                                        /*!< GPIO_PORT NOT4: NOTP25 Position     */
#define GPIO_PORT_NOT4_NOTP25_Msk                             (0x01UL << GPIO_PORT_NOT4_NOTP25_Pos)                     /*!< GPIO_PORT NOT4: NOTP25 Mask         */
#define GPIO_PORT_NOT4_NOTP26_Pos                             26                                                        /*!< GPIO_PORT NOT4: NOTP26 Position     */
#define GPIO_PORT_NOT4_NOTP26_Msk                             (0x01UL << GPIO_PORT_NOT4_NOTP26_Pos)                     /*!< GPIO_PORT NOT4: NOTP26 Mask         */
#define GPIO_PORT_NOT4_NOTP27_Pos                             27                                                        /*!< GPIO_PORT NOT4: NOTP27 Position     */
#define GPIO_PORT_NOT4_NOTP27_Msk                             (0x01UL << GPIO_PORT_NOT4_NOTP27_Pos)                     /*!< GPIO_PORT NOT4: NOTP27 Mask         */
#define GPIO_PORT_NOT4_NOTP28_Pos                             28                                                        /*!< GPIO_PORT NOT4: NOTP28 Position     */
#define GPIO_PORT_NOT4_NOTP28_Msk                             (0x01UL << GPIO_PORT_NOT4_NOTP28_Pos)                     /*!< GPIO_PORT NOT4: NOTP28 Mask         */
#define GPIO_PORT_NOT4_NOTP29_Pos                             29                                                        /*!< GPIO_PORT NOT4: NOTP29 Position     */
#define GPIO_PORT_NOT4_NOTP29_Msk                             (0x01UL << GPIO_PORT_NOT4_NOTP29_Pos)                     /*!< GPIO_PORT NOT4: NOTP29 Mask         */
#define GPIO_PORT_NOT4_NOTP30_Pos                             30                                                        /*!< GPIO_PORT NOT4: NOTP30 Position     */
#define GPIO_PORT_NOT4_NOTP30_Msk                             (0x01UL << GPIO_PORT_NOT4_NOTP30_Pos)                     /*!< GPIO_PORT NOT4: NOTP30 Mask         */
#define GPIO_PORT_NOT4_NOTP31_Pos                             31                                                        /*!< GPIO_PORT NOT4: NOTP31 Position     */
#define GPIO_PORT_NOT4_NOTP31_Msk                             (0x01UL << GPIO_PORT_NOT4_NOTP31_Pos)                     /*!< GPIO_PORT NOT4: NOTP31 Mask         */

// -------------------------------------  GPIO_PORT_NOT5  -----------------------------------------
#define GPIO_PORT_NOT5_NOTP0_Pos                              0                                                         /*!< GPIO_PORT NOT5: NOTP0 Position      */
#define GPIO_PORT_NOT5_NOTP0_Msk                              (0x01UL << GPIO_PORT_NOT5_NOTP0_Pos)                      /*!< GPIO_PORT NOT5: NOTP0 Mask          */
#define GPIO_PORT_NOT5_NOTP1_Pos                              1                                                         /*!< GPIO_PORT NOT5: NOTP1 Position      */
#define GPIO_PORT_NOT5_NOTP1_Msk                              (0x01UL << GPIO_PORT_NOT5_NOTP1_Pos)                      /*!< GPIO_PORT NOT5: NOTP1 Mask          */
#define GPIO_PORT_NOT5_NOTP2_Pos                              2                                                         /*!< GPIO_PORT NOT5: NOTP2 Position      */
#define GPIO_PORT_NOT5_NOTP2_Msk                              (0x01UL << GPIO_PORT_NOT5_NOTP2_Pos)                      /*!< GPIO_PORT NOT5: NOTP2 Mask          */
#define GPIO_PORT_NOT5_NOTP3_Pos                              3                                                         /*!< GPIO_PORT NOT5: NOTP3 Position      */
#define GPIO_PORT_NOT5_NOTP3_Msk                              (0x01UL << GPIO_PORT_NOT5_NOTP3_Pos)                      /*!< GPIO_PORT NOT5: NOTP3 Mask          */
#define GPIO_PORT_NOT5_NOTP4_Pos                              4                                                         /*!< GPIO_PORT NOT5: NOTP4 Position      */
#define GPIO_PORT_NOT5_NOTP4_Msk                              (0x01UL << GPIO_PORT_NOT5_NOTP4_Pos)                      /*!< GPIO_PORT NOT5: NOTP4 Mask          */
#define GPIO_PORT_NOT5_NOTP5_Pos                              5                                                         /*!< GPIO_PORT NOT5: NOTP5 Position      */
#define GPIO_PORT_NOT5_NOTP5_Msk                              (0x01UL << GPIO_PORT_NOT5_NOTP5_Pos)                      /*!< GPIO_PORT NOT5: NOTP5 Mask          */
#define GPIO_PORT_NOT5_NOTP6_Pos                              6                                                         /*!< GPIO_PORT NOT5: NOTP6 Position      */
#define GPIO_PORT_NOT5_NOTP6_Msk                              (0x01UL << GPIO_PORT_NOT5_NOTP6_Pos)                      /*!< GPIO_PORT NOT5: NOTP6 Mask          */
#define GPIO_PORT_NOT5_NOTP7_Pos                              7                                                         /*!< GPIO_PORT NOT5: NOTP7 Position      */
#define GPIO_PORT_NOT5_NOTP7_Msk                              (0x01UL << GPIO_PORT_NOT5_NOTP7_Pos)                      /*!< GPIO_PORT NOT5: NOTP7 Mask          */
#define GPIO_PORT_NOT5_NOTP8_Pos                              8                                                         /*!< GPIO_PORT NOT5: NOTP8 Position      */
#define GPIO_PORT_NOT5_NOTP8_Msk                              (0x01UL << GPIO_PORT_NOT5_NOTP8_Pos)                      /*!< GPIO_PORT NOT5: NOTP8 Mask          */
#define GPIO_PORT_NOT5_NOTP9_Pos                              9                                                         /*!< GPIO_PORT NOT5: NOTP9 Position      */
#define GPIO_PORT_NOT5_NOTP9_Msk                              (0x01UL << GPIO_PORT_NOT5_NOTP9_Pos)                      /*!< GPIO_PORT NOT5: NOTP9 Mask          */
#define GPIO_PORT_NOT5_NOTP10_Pos                             10                                                        /*!< GPIO_PORT NOT5: NOTP10 Position     */
#define GPIO_PORT_NOT5_NOTP10_Msk                             (0x01UL << GPIO_PORT_NOT5_NOTP10_Pos)                     /*!< GPIO_PORT NOT5: NOTP10 Mask         */
#define GPIO_PORT_NOT5_NOTP11_Pos                             11                                                        /*!< GPIO_PORT NOT5: NOTP11 Position     */
#define GPIO_PORT_NOT5_NOTP11_Msk                             (0x01UL << GPIO_PORT_NOT5_NOTP11_Pos)                     /*!< GPIO_PORT NOT5: NOTP11 Mask         */
#define GPIO_PORT_NOT5_NOTP12_Pos                             12                                                        /*!< GPIO_PORT NOT5: NOTP12 Position     */
#define GPIO_PORT_NOT5_NOTP12_Msk                             (0x01UL << GPIO_PORT_NOT5_NOTP12_Pos)                     /*!< GPIO_PORT NOT5: NOTP12 Mask         */
#define GPIO_PORT_NOT5_NOTP13_Pos                             13                                                        /*!< GPIO_PORT NOT5: NOTP13 Position     */
#define GPIO_PORT_NOT5_NOTP13_Msk                             (0x01UL << GPIO_PORT_NOT5_NOTP13_Pos)                     /*!< GPIO_PORT NOT5: NOTP13 Mask         */
#define GPIO_PORT_NOT5_NOTP14_Pos                             14                                                        /*!< GPIO_PORT NOT5: NOTP14 Position     */
#define GPIO_PORT_NOT5_NOTP14_Msk                             (0x01UL << GPIO_PORT_NOT5_NOTP14_Pos)                     /*!< GPIO_PORT NOT5: NOTP14 Mask         */
#define GPIO_PORT_NOT5_NOTP15_Pos                             15                                                        /*!< GPIO_PORT NOT5: NOTP15 Position     */
#define GPIO_PORT_NOT5_NOTP15_Msk                             (0x01UL << GPIO_PORT_NOT5_NOTP15_Pos)                     /*!< GPIO_PORT NOT5: NOTP15 Mask         */
#define GPIO_PORT_NOT5_NOTP16_Pos                             16                                                        /*!< GPIO_PORT NOT5: NOTP16 Position     */
#define GPIO_PORT_NOT5_NOTP16_Msk                             (0x01UL << GPIO_PORT_NOT5_NOTP16_Pos)                     /*!< GPIO_PORT NOT5: NOTP16 Mask         */
#define GPIO_PORT_NOT5_NOTP17_Pos                             17                                                        /*!< GPIO_PORT NOT5: NOTP17 Position     */
#define GPIO_PORT_NOT5_NOTP17_Msk                             (0x01UL << GPIO_PORT_NOT5_NOTP17_Pos)                     /*!< GPIO_PORT NOT5: NOTP17 Mask         */
#define GPIO_PORT_NOT5_NOTP18_Pos                             18                                                        /*!< GPIO_PORT NOT5: NOTP18 Position     */
#define GPIO_PORT_NOT5_NOTP18_Msk                             (0x01UL << GPIO_PORT_NOT5_NOTP18_Pos)                     /*!< GPIO_PORT NOT5: NOTP18 Mask         */
#define GPIO_PORT_NOT5_NOTP19_Pos                             19                                                        /*!< GPIO_PORT NOT5: NOTP19 Position     */
#define GPIO_PORT_NOT5_NOTP19_Msk                             (0x01UL << GPIO_PORT_NOT5_NOTP19_Pos)                     /*!< GPIO_PORT NOT5: NOTP19 Mask         */
#define GPIO_PORT_NOT5_NOTP20_Pos                             20                                                        /*!< GPIO_PORT NOT5: NOTP20 Position     */
#define GPIO_PORT_NOT5_NOTP20_Msk                             (0x01UL << GPIO_PORT_NOT5_NOTP20_Pos)                     /*!< GPIO_PORT NOT5: NOTP20 Mask         */
#define GPIO_PORT_NOT5_NOTP21_Pos                             21                                                        /*!< GPIO_PORT NOT5: NOTP21 Position     */
#define GPIO_PORT_NOT5_NOTP21_Msk                             (0x01UL << GPIO_PORT_NOT5_NOTP21_Pos)                     /*!< GPIO_PORT NOT5: NOTP21 Mask         */
#define GPIO_PORT_NOT5_NOTP22_Pos                             22                                                        /*!< GPIO_PORT NOT5: NOTP22 Position     */
#define GPIO_PORT_NOT5_NOTP22_Msk                             (0x01UL << GPIO_PORT_NOT5_NOTP22_Pos)                     /*!< GPIO_PORT NOT5: NOTP22 Mask         */
#define GPIO_PORT_NOT5_NOTP23_Pos                             23                                                        /*!< GPIO_PORT NOT5: NOTP23 Position     */
#define GPIO_PORT_NOT5_NOTP23_Msk                             (0x01UL << GPIO_PORT_NOT5_NOTP23_Pos)                     /*!< GPIO_PORT NOT5: NOTP23 Mask         */
#define GPIO_PORT_NOT5_NOTP24_Pos                             24                                                        /*!< GPIO_PORT NOT5: NOTP24 Position     */
#define GPIO_PORT_NOT5_NOTP24_Msk                             (0x01UL << GPIO_PORT_NOT5_NOTP24_Pos)                     /*!< GPIO_PORT NOT5: NOTP24 Mask         */
#define GPIO_PORT_NOT5_NOTP25_Pos                             25                                                        /*!< GPIO_PORT NOT5: NOTP25 Position     */
#define GPIO_PORT_NOT5_NOTP25_Msk                             (0x01UL << GPIO_PORT_NOT5_NOTP25_Pos)                     /*!< GPIO_PORT NOT5: NOTP25 Mask         */
#define GPIO_PORT_NOT5_NOTP26_Pos                             26                                                        /*!< GPIO_PORT NOT5: NOTP26 Position     */
#define GPIO_PORT_NOT5_NOTP26_Msk                             (0x01UL << GPIO_PORT_NOT5_NOTP26_Pos)                     /*!< GPIO_PORT NOT5: NOTP26 Mask         */
#define GPIO_PORT_NOT5_NOTP27_Pos                             27                                                        /*!< GPIO_PORT NOT5: NOTP27 Position     */
#define GPIO_PORT_NOT5_NOTP27_Msk                             (0x01UL << GPIO_PORT_NOT5_NOTP27_Pos)                     /*!< GPIO_PORT NOT5: NOTP27 Mask         */
#define GPIO_PORT_NOT5_NOTP28_Pos                             28                                                        /*!< GPIO_PORT NOT5: NOTP28 Position     */
#define GPIO_PORT_NOT5_NOTP28_Msk                             (0x01UL << GPIO_PORT_NOT5_NOTP28_Pos)                     /*!< GPIO_PORT NOT5: NOTP28 Mask         */
#define GPIO_PORT_NOT5_NOTP29_Pos                             29                                                        /*!< GPIO_PORT NOT5: NOTP29 Position     */
#define GPIO_PORT_NOT5_NOTP29_Msk                             (0x01UL << GPIO_PORT_NOT5_NOTP29_Pos)                     /*!< GPIO_PORT NOT5: NOTP29 Mask         */
#define GPIO_PORT_NOT5_NOTP30_Pos                             30                                                        /*!< GPIO_PORT NOT5: NOTP30 Position     */
#define GPIO_PORT_NOT5_NOTP30_Msk                             (0x01UL << GPIO_PORT_NOT5_NOTP30_Pos)                     /*!< GPIO_PORT NOT5: NOTP30 Mask         */
#define GPIO_PORT_NOT5_NOTP31_Pos                             31                                                        /*!< GPIO_PORT NOT5: NOTP31 Position     */
#define GPIO_PORT_NOT5_NOTP31_Msk                             (0x01UL << GPIO_PORT_NOT5_NOTP31_Pos)                     /*!< GPIO_PORT NOT5: NOTP31 Mask         */

// -------------------------------------  GPIO_PORT_NOT6  -----------------------------------------
#define GPIO_PORT_NOT6_NOTP0_Pos                              0                                                         /*!< GPIO_PORT NOT6: NOTP0 Position      */
#define GPIO_PORT_NOT6_NOTP0_Msk                              (0x01UL << GPIO_PORT_NOT6_NOTP0_Pos)                      /*!< GPIO_PORT NOT6: NOTP0 Mask          */
#define GPIO_PORT_NOT6_NOTP1_Pos                              1                                                         /*!< GPIO_PORT NOT6: NOTP1 Position      */
#define GPIO_PORT_NOT6_NOTP1_Msk                              (0x01UL << GPIO_PORT_NOT6_NOTP1_Pos)                      /*!< GPIO_PORT NOT6: NOTP1 Mask          */
#define GPIO_PORT_NOT6_NOTP2_Pos                              2                                                         /*!< GPIO_PORT NOT6: NOTP2 Position      */
#define GPIO_PORT_NOT6_NOTP2_Msk                              (0x01UL << GPIO_PORT_NOT6_NOTP2_Pos)                      /*!< GPIO_PORT NOT6: NOTP2 Mask          */
#define GPIO_PORT_NOT6_NOTP3_Pos                              3                                                         /*!< GPIO_PORT NOT6: NOTP3 Position      */
#define GPIO_PORT_NOT6_NOTP3_Msk                              (0x01UL << GPIO_PORT_NOT6_NOTP3_Pos)                      /*!< GPIO_PORT NOT6: NOTP3 Mask          */
#define GPIO_PORT_NOT6_NOTP4_Pos                              4                                                         /*!< GPIO_PORT NOT6: NOTP4 Position      */
#define GPIO_PORT_NOT6_NOTP4_Msk                              (0x01UL << GPIO_PORT_NOT6_NOTP4_Pos)                      /*!< GPIO_PORT NOT6: NOTP4 Mask          */
#define GPIO_PORT_NOT6_NOTP5_Pos                              5                                                         /*!< GPIO_PORT NOT6: NOTP5 Position      */
#define GPIO_PORT_NOT6_NOTP5_Msk                              (0x01UL << GPIO_PORT_NOT6_NOTP5_Pos)                      /*!< GPIO_PORT NOT6: NOTP5 Mask          */
#define GPIO_PORT_NOT6_NOTP6_Pos                              6                                                         /*!< GPIO_PORT NOT6: NOTP6 Position      */
#define GPIO_PORT_NOT6_NOTP6_Msk                              (0x01UL << GPIO_PORT_NOT6_NOTP6_Pos)                      /*!< GPIO_PORT NOT6: NOTP6 Mask          */
#define GPIO_PORT_NOT6_NOTP7_Pos                              7                                                         /*!< GPIO_PORT NOT6: NOTP7 Position      */
#define GPIO_PORT_NOT6_NOTP7_Msk                              (0x01UL << GPIO_PORT_NOT6_NOTP7_Pos)                      /*!< GPIO_PORT NOT6: NOTP7 Mask          */
#define GPIO_PORT_NOT6_NOTP8_Pos                              8                                                         /*!< GPIO_PORT NOT6: NOTP8 Position      */
#define GPIO_PORT_NOT6_NOTP8_Msk                              (0x01UL << GPIO_PORT_NOT6_NOTP8_Pos)                      /*!< GPIO_PORT NOT6: NOTP8 Mask          */
#define GPIO_PORT_NOT6_NOTP9_Pos                              9                                                         /*!< GPIO_PORT NOT6: NOTP9 Position      */
#define GPIO_PORT_NOT6_NOTP9_Msk                              (0x01UL << GPIO_PORT_NOT6_NOTP9_Pos)                      /*!< GPIO_PORT NOT6: NOTP9 Mask          */
#define GPIO_PORT_NOT6_NOTP10_Pos                             10                                                        /*!< GPIO_PORT NOT6: NOTP10 Position     */
#define GPIO_PORT_NOT6_NOTP10_Msk                             (0x01UL << GPIO_PORT_NOT6_NOTP10_Pos)                     /*!< GPIO_PORT NOT6: NOTP10 Mask         */
#define GPIO_PORT_NOT6_NOTP11_Pos                             11                                                        /*!< GPIO_PORT NOT6: NOTP11 Position     */
#define GPIO_PORT_NOT6_NOTP11_Msk                             (0x01UL << GPIO_PORT_NOT6_NOTP11_Pos)                     /*!< GPIO_PORT NOT6: NOTP11 Mask         */
#define GPIO_PORT_NOT6_NOTP12_Pos                             12                                                        /*!< GPIO_PORT NOT6: NOTP12 Position     */
#define GPIO_PORT_NOT6_NOTP12_Msk                             (0x01UL << GPIO_PORT_NOT6_NOTP12_Pos)                     /*!< GPIO_PORT NOT6: NOTP12 Mask         */
#define GPIO_PORT_NOT6_NOTP13_Pos                             13                                                        /*!< GPIO_PORT NOT6: NOTP13 Position     */
#define GPIO_PORT_NOT6_NOTP13_Msk                             (0x01UL << GPIO_PORT_NOT6_NOTP13_Pos)                     /*!< GPIO_PORT NOT6: NOTP13 Mask         */
#define GPIO_PORT_NOT6_NOTP14_Pos                             14                                                        /*!< GPIO_PORT NOT6: NOTP14 Position     */
#define GPIO_PORT_NOT6_NOTP14_Msk                             (0x01UL << GPIO_PORT_NOT6_NOTP14_Pos)                     /*!< GPIO_PORT NOT6: NOTP14 Mask         */
#define GPIO_PORT_NOT6_NOTP15_Pos                             15                                                        /*!< GPIO_PORT NOT6: NOTP15 Position     */
#define GPIO_PORT_NOT6_NOTP15_Msk                             (0x01UL << GPIO_PORT_NOT6_NOTP15_Pos)                     /*!< GPIO_PORT NOT6: NOTP15 Mask         */
#define GPIO_PORT_NOT6_NOTP16_Pos                             16                                                        /*!< GPIO_PORT NOT6: NOTP16 Position     */
#define GPIO_PORT_NOT6_NOTP16_Msk                             (0x01UL << GPIO_PORT_NOT6_NOTP16_Pos)                     /*!< GPIO_PORT NOT6: NOTP16 Mask         */
#define GPIO_PORT_NOT6_NOTP17_Pos                             17                                                        /*!< GPIO_PORT NOT6: NOTP17 Position     */
#define GPIO_PORT_NOT6_NOTP17_Msk                             (0x01UL << GPIO_PORT_NOT6_NOTP17_Pos)                     /*!< GPIO_PORT NOT6: NOTP17 Mask         */
#define GPIO_PORT_NOT6_NOTP18_Pos                             18                                                        /*!< GPIO_PORT NOT6: NOTP18 Position     */
#define GPIO_PORT_NOT6_NOTP18_Msk                             (0x01UL << GPIO_PORT_NOT6_NOTP18_Pos)                     /*!< GPIO_PORT NOT6: NOTP18 Mask         */
#define GPIO_PORT_NOT6_NOTP19_Pos                             19                                                        /*!< GPIO_PORT NOT6: NOTP19 Position     */
#define GPIO_PORT_NOT6_NOTP19_Msk                             (0x01UL << GPIO_PORT_NOT6_NOTP19_Pos)                     /*!< GPIO_PORT NOT6: NOTP19 Mask         */
#define GPIO_PORT_NOT6_NOTP20_Pos                             20                                                        /*!< GPIO_PORT NOT6: NOTP20 Position     */
#define GPIO_PORT_NOT6_NOTP20_Msk                             (0x01UL << GPIO_PORT_NOT6_NOTP20_Pos)                     /*!< GPIO_PORT NOT6: NOTP20 Mask         */
#define GPIO_PORT_NOT6_NOTP21_Pos                             21                                                        /*!< GPIO_PORT NOT6: NOTP21 Position     */
#define GPIO_PORT_NOT6_NOTP21_Msk                             (0x01UL << GPIO_PORT_NOT6_NOTP21_Pos)                     /*!< GPIO_PORT NOT6: NOTP21 Mask         */
#define GPIO_PORT_NOT6_NOTP22_Pos                             22                                                        /*!< GPIO_PORT NOT6: NOTP22 Position     */
#define GPIO_PORT_NOT6_NOTP22_Msk                             (0x01UL << GPIO_PORT_NOT6_NOTP22_Pos)                     /*!< GPIO_PORT NOT6: NOTP22 Mask         */
#define GPIO_PORT_NOT6_NOTP23_Pos                             23                                                        /*!< GPIO_PORT NOT6: NOTP23 Position     */
#define GPIO_PORT_NOT6_NOTP23_Msk                             (0x01UL << GPIO_PORT_NOT6_NOTP23_Pos)                     /*!< GPIO_PORT NOT6: NOTP23 Mask         */
#define GPIO_PORT_NOT6_NOTP24_Pos                             24                                                        /*!< GPIO_PORT NOT6: NOTP24 Position     */
#define GPIO_PORT_NOT6_NOTP24_Msk                             (0x01UL << GPIO_PORT_NOT6_NOTP24_Pos)                     /*!< GPIO_PORT NOT6: NOTP24 Mask         */
#define GPIO_PORT_NOT6_NOTP25_Pos                             25                                                        /*!< GPIO_PORT NOT6: NOTP25 Position     */
#define GPIO_PORT_NOT6_NOTP25_Msk                             (0x01UL << GPIO_PORT_NOT6_NOTP25_Pos)                     /*!< GPIO_PORT NOT6: NOTP25 Mask         */
#define GPIO_PORT_NOT6_NOTP26_Pos                             26                                                        /*!< GPIO_PORT NOT6: NOTP26 Position     */
#define GPIO_PORT_NOT6_NOTP26_Msk                             (0x01UL << GPIO_PORT_NOT6_NOTP26_Pos)                     /*!< GPIO_PORT NOT6: NOTP26 Mask         */
#define GPIO_PORT_NOT6_NOTP27_Pos                             27                                                        /*!< GPIO_PORT NOT6: NOTP27 Position     */
#define GPIO_PORT_NOT6_NOTP27_Msk                             (0x01UL << GPIO_PORT_NOT6_NOTP27_Pos)                     /*!< GPIO_PORT NOT6: NOTP27 Mask         */
#define GPIO_PORT_NOT6_NOTP28_Pos                             28                                                        /*!< GPIO_PORT NOT6: NOTP28 Position     */
#define GPIO_PORT_NOT6_NOTP28_Msk                             (0x01UL << GPIO_PORT_NOT6_NOTP28_Pos)                     /*!< GPIO_PORT NOT6: NOTP28 Mask         */
#define GPIO_PORT_NOT6_NOTP29_Pos                             29                                                        /*!< GPIO_PORT NOT6: NOTP29 Position     */
#define GPIO_PORT_NOT6_NOTP29_Msk                             (0x01UL << GPIO_PORT_NOT6_NOTP29_Pos)                     /*!< GPIO_PORT NOT6: NOTP29 Mask         */
#define GPIO_PORT_NOT6_NOTP30_Pos                             30                                                        /*!< GPIO_PORT NOT6: NOTP30 Position     */
#define GPIO_PORT_NOT6_NOTP30_Msk                             (0x01UL << GPIO_PORT_NOT6_NOTP30_Pos)                     /*!< GPIO_PORT NOT6: NOTP30 Mask         */
#define GPIO_PORT_NOT6_NOTP31_Pos                             31                                                        /*!< GPIO_PORT NOT6: NOTP31 Position     */
#define GPIO_PORT_NOT6_NOTP31_Msk                             (0x01UL << GPIO_PORT_NOT6_NOTP31_Pos)                     /*!< GPIO_PORT NOT6: NOTP31 Mask         */

// -------------------------------------  GPIO_PORT_NOT7  -----------------------------------------
#define GPIO_PORT_NOT7_NOTP0_Pos                              0                                                         /*!< GPIO_PORT NOT7: NOTP0 Position      */
#define GPIO_PORT_NOT7_NOTP0_Msk                              (0x01UL << GPIO_PORT_NOT7_NOTP0_Pos)                      /*!< GPIO_PORT NOT7: NOTP0 Mask          */
#define GPIO_PORT_NOT7_NOTP1_Pos                              1                                                         /*!< GPIO_PORT NOT7: NOTP1 Position      */
#define GPIO_PORT_NOT7_NOTP1_Msk                              (0x01UL << GPIO_PORT_NOT7_NOTP1_Pos)                      /*!< GPIO_PORT NOT7: NOTP1 Mask          */
#define GPIO_PORT_NOT7_NOTP2_Pos                              2                                                         /*!< GPIO_PORT NOT7: NOTP2 Position      */
#define GPIO_PORT_NOT7_NOTP2_Msk                              (0x01UL << GPIO_PORT_NOT7_NOTP2_Pos)                      /*!< GPIO_PORT NOT7: NOTP2 Mask          */
#define GPIO_PORT_NOT7_NOTP3_Pos                              3                                                         /*!< GPIO_PORT NOT7: NOTP3 Position      */
#define GPIO_PORT_NOT7_NOTP3_Msk                              (0x01UL << GPIO_PORT_NOT7_NOTP3_Pos)                      /*!< GPIO_PORT NOT7: NOTP3 Mask          */
#define GPIO_PORT_NOT7_NOTP4_Pos                              4                                                         /*!< GPIO_PORT NOT7: NOTP4 Position      */
#define GPIO_PORT_NOT7_NOTP4_Msk                              (0x01UL << GPIO_PORT_NOT7_NOTP4_Pos)                      /*!< GPIO_PORT NOT7: NOTP4 Mask          */
#define GPIO_PORT_NOT7_NOTP5_Pos                              5                                                         /*!< GPIO_PORT NOT7: NOTP5 Position      */
#define GPIO_PORT_NOT7_NOTP5_Msk                              (0x01UL << GPIO_PORT_NOT7_NOTP5_Pos)                      /*!< GPIO_PORT NOT7: NOTP5 Mask          */
#define GPIO_PORT_NOT7_NOTP6_Pos                              6                                                         /*!< GPIO_PORT NOT7: NOTP6 Position      */
#define GPIO_PORT_NOT7_NOTP6_Msk                              (0x01UL << GPIO_PORT_NOT7_NOTP6_Pos)                      /*!< GPIO_PORT NOT7: NOTP6 Mask          */
#define GPIO_PORT_NOT7_NOTP7_Pos                              7                                                         /*!< GPIO_PORT NOT7: NOTP7 Position      */
#define GPIO_PORT_NOT7_NOTP7_Msk                              (0x01UL << GPIO_PORT_NOT7_NOTP7_Pos)                      /*!< GPIO_PORT NOT7: NOTP7 Mask          */
#define GPIO_PORT_NOT7_NOTP8_Pos                              8                                                         /*!< GPIO_PORT NOT7: NOTP8 Position      */
#define GPIO_PORT_NOT7_NOTP8_Msk                              (0x01UL << GPIO_PORT_NOT7_NOTP8_Pos)                      /*!< GPIO_PORT NOT7: NOTP8 Mask          */
#define GPIO_PORT_NOT7_NOTP9_Pos                              9                                                         /*!< GPIO_PORT NOT7: NOTP9 Position      */
#define GPIO_PORT_NOT7_NOTP9_Msk                              (0x01UL << GPIO_PORT_NOT7_NOTP9_Pos)                      /*!< GPIO_PORT NOT7: NOTP9 Mask          */
#define GPIO_PORT_NOT7_NOTP10_Pos                             10                                                        /*!< GPIO_PORT NOT7: NOTP10 Position     */
#define GPIO_PORT_NOT7_NOTP10_Msk                             (0x01UL << GPIO_PORT_NOT7_NOTP10_Pos)                     /*!< GPIO_PORT NOT7: NOTP10 Mask         */
#define GPIO_PORT_NOT7_NOTP11_Pos                             11                                                        /*!< GPIO_PORT NOT7: NOTP11 Position     */
#define GPIO_PORT_NOT7_NOTP11_Msk                             (0x01UL << GPIO_PORT_NOT7_NOTP11_Pos)                     /*!< GPIO_PORT NOT7: NOTP11 Mask         */
#define GPIO_PORT_NOT7_NOTP12_Pos                             12                                                        /*!< GPIO_PORT NOT7: NOTP12 Position     */
#define GPIO_PORT_NOT7_NOTP12_Msk                             (0x01UL << GPIO_PORT_NOT7_NOTP12_Pos)                     /*!< GPIO_PORT NOT7: NOTP12 Mask         */
#define GPIO_PORT_NOT7_NOTP13_Pos                             13                                                        /*!< GPIO_PORT NOT7: NOTP13 Position     */
#define GPIO_PORT_NOT7_NOTP13_Msk                             (0x01UL << GPIO_PORT_NOT7_NOTP13_Pos)                     /*!< GPIO_PORT NOT7: NOTP13 Mask         */
#define GPIO_PORT_NOT7_NOTP14_Pos                             14                                                        /*!< GPIO_PORT NOT7: NOTP14 Position     */
#define GPIO_PORT_NOT7_NOTP14_Msk                             (0x01UL << GPIO_PORT_NOT7_NOTP14_Pos)                     /*!< GPIO_PORT NOT7: NOTP14 Mask         */
#define GPIO_PORT_NOT7_NOTP15_Pos                             15                                                        /*!< GPIO_PORT NOT7: NOTP15 Position     */
#define GPIO_PORT_NOT7_NOTP15_Msk                             (0x01UL << GPIO_PORT_NOT7_NOTP15_Pos)                     /*!< GPIO_PORT NOT7: NOTP15 Mask         */
#define GPIO_PORT_NOT7_NOTP16_Pos                             16                                                        /*!< GPIO_PORT NOT7: NOTP16 Position     */
#define GPIO_PORT_NOT7_NOTP16_Msk                             (0x01UL << GPIO_PORT_NOT7_NOTP16_Pos)                     /*!< GPIO_PORT NOT7: NOTP16 Mask         */
#define GPIO_PORT_NOT7_NOTP17_Pos                             17                                                        /*!< GPIO_PORT NOT7: NOTP17 Position     */
#define GPIO_PORT_NOT7_NOTP17_Msk                             (0x01UL << GPIO_PORT_NOT7_NOTP17_Pos)                     /*!< GPIO_PORT NOT7: NOTP17 Mask         */
#define GPIO_PORT_NOT7_NOTP18_Pos                             18                                                        /*!< GPIO_PORT NOT7: NOTP18 Position     */
#define GPIO_PORT_NOT7_NOTP18_Msk                             (0x01UL << GPIO_PORT_NOT7_NOTP18_Pos)                     /*!< GPIO_PORT NOT7: NOTP18 Mask         */
#define GPIO_PORT_NOT7_NOTP19_Pos                             19                                                        /*!< GPIO_PORT NOT7: NOTP19 Position     */
#define GPIO_PORT_NOT7_NOTP19_Msk                             (0x01UL << GPIO_PORT_NOT7_NOTP19_Pos)                     /*!< GPIO_PORT NOT7: NOTP19 Mask         */
#define GPIO_PORT_NOT7_NOTP20_Pos                             20                                                        /*!< GPIO_PORT NOT7: NOTP20 Position     */
#define GPIO_PORT_NOT7_NOTP20_Msk                             (0x01UL << GPIO_PORT_NOT7_NOTP20_Pos)                     /*!< GPIO_PORT NOT7: NOTP20 Mask         */
#define GPIO_PORT_NOT7_NOTP21_Pos                             21                                                        /*!< GPIO_PORT NOT7: NOTP21 Position     */
#define GPIO_PORT_NOT7_NOTP21_Msk                             (0x01UL << GPIO_PORT_NOT7_NOTP21_Pos)                     /*!< GPIO_PORT NOT7: NOTP21 Mask         */
#define GPIO_PORT_NOT7_NOTP22_Pos                             22                                                        /*!< GPIO_PORT NOT7: NOTP22 Position     */
#define GPIO_PORT_NOT7_NOTP22_Msk                             (0x01UL << GPIO_PORT_NOT7_NOTP22_Pos)                     /*!< GPIO_PORT NOT7: NOTP22 Mask         */
#define GPIO_PORT_NOT7_NOTP23_Pos                             23                                                        /*!< GPIO_PORT NOT7: NOTP23 Position     */
#define GPIO_PORT_NOT7_NOTP23_Msk                             (0x01UL << GPIO_PORT_NOT7_NOTP23_Pos)                     /*!< GPIO_PORT NOT7: NOTP23 Mask         */
#define GPIO_PORT_NOT7_NOTP24_Pos                             24                                                        /*!< GPIO_PORT NOT7: NOTP24 Position     */
#define GPIO_PORT_NOT7_NOTP24_Msk                             (0x01UL << GPIO_PORT_NOT7_NOTP24_Pos)                     /*!< GPIO_PORT NOT7: NOTP24 Mask         */
#define GPIO_PORT_NOT7_NOTP25_Pos                             25                                                        /*!< GPIO_PORT NOT7: NOTP25 Position     */
#define GPIO_PORT_NOT7_NOTP25_Msk                             (0x01UL << GPIO_PORT_NOT7_NOTP25_Pos)                     /*!< GPIO_PORT NOT7: NOTP25 Mask         */
#define GPIO_PORT_NOT7_NOTP26_Pos                             26                                                        /*!< GPIO_PORT NOT7: NOTP26 Position     */
#define GPIO_PORT_NOT7_NOTP26_Msk                             (0x01UL << GPIO_PORT_NOT7_NOTP26_Pos)                     /*!< GPIO_PORT NOT7: NOTP26 Mask         */
#define GPIO_PORT_NOT7_NOTP27_Pos                             27                                                        /*!< GPIO_PORT NOT7: NOTP27 Position     */
#define GPIO_PORT_NOT7_NOTP27_Msk                             (0x01UL << GPIO_PORT_NOT7_NOTP27_Pos)                     /*!< GPIO_PORT NOT7: NOTP27 Mask         */
#define GPIO_PORT_NOT7_NOTP28_Pos                             28                                                        /*!< GPIO_PORT NOT7: NOTP28 Position     */
#define GPIO_PORT_NOT7_NOTP28_Msk                             (0x01UL << GPIO_PORT_NOT7_NOTP28_Pos)                     /*!< GPIO_PORT NOT7: NOTP28 Mask         */
#define GPIO_PORT_NOT7_NOTP29_Pos                             29                                                        /*!< GPIO_PORT NOT7: NOTP29 Position     */
#define GPIO_PORT_NOT7_NOTP29_Msk                             (0x01UL << GPIO_PORT_NOT7_NOTP29_Pos)                     /*!< GPIO_PORT NOT7: NOTP29 Mask         */
#define GPIO_PORT_NOT7_NOTP30_Pos                             30                                                        /*!< GPIO_PORT NOT7: NOTP30 Position     */
#define GPIO_PORT_NOT7_NOTP30_Msk                             (0x01UL << GPIO_PORT_NOT7_NOTP30_Pos)                     /*!< GPIO_PORT NOT7: NOTP30 Mask         */
#define GPIO_PORT_NOT7_NOTP31_Pos                             31                                                        /*!< GPIO_PORT NOT7: NOTP31 Position     */
#define GPIO_PORT_NOT7_NOTP31_Msk                             (0x01UL << GPIO_PORT_NOT7_NOTP31_Pos)                     /*!< GPIO_PORT NOT7: NOTP31 Mask         */


// ------------------------------------------------------------------------------------------------
// -----                                  SPI Position & Mask                                 -----
// ------------------------------------------------------------------------------------------------


// -----------------------------------------  SPI_CR  ---------------------------------------------
#define SPI_CR_BITENABLE_Pos                                  2                                                         /*!< SPI CR: BITENABLE Position          */
#define SPI_CR_BITENABLE_Msk                                  (0x01UL << SPI_CR_BITENABLE_Pos)                          /*!< SPI CR: BITENABLE Mask              */
#define SPI_CR_CPHA_Pos                                       3                                                         /*!< SPI CR: CPHA Position               */
#define SPI_CR_CPHA_Msk                                       (0x01UL << SPI_CR_CPHA_Pos)                               /*!< SPI CR: CPHA Mask                   */
#define SPI_CR_CPOL_Pos                                       4                                                         /*!< SPI CR: CPOL Position               */
#define SPI_CR_CPOL_Msk                                       (0x01UL << SPI_CR_CPOL_Pos)                               /*!< SPI CR: CPOL Mask                   */
#define SPI_CR_MSTR_Pos                                       5                                                         /*!< SPI CR: MSTR Position               */
#define SPI_CR_MSTR_Msk                                       (0x01UL << SPI_CR_MSTR_Pos)                               /*!< SPI CR: MSTR Mask                   */
#define SPI_CR_LSBF_Pos                                       6                                                         /*!< SPI CR: LSBF Position               */
#define SPI_CR_LSBF_Msk                                       (0x01UL << SPI_CR_LSBF_Pos)                               /*!< SPI CR: LSBF Mask                   */
#define SPI_CR_SPIE_Pos                                       7                                                         /*!< SPI CR: SPIE Position               */
#define SPI_CR_SPIE_Msk                                       (0x01UL << SPI_CR_SPIE_Pos)                               /*!< SPI CR: SPIE Mask                   */
#define SPI_CR_BITS_Pos                                       8                                                         /*!< SPI CR: BITS Position               */
#define SPI_CR_BITS_Msk                                       (0x0fUL << SPI_CR_BITS_Pos)                               /*!< SPI CR: BITS Mask                   */

// -----------------------------------------  SPI_SR  ---------------------------------------------
#define SPI_SR_ABRT_Pos                                       3                                                         /*!< SPI SR: ABRT Position               */
#define SPI_SR_ABRT_Msk                                       (0x01UL << SPI_SR_ABRT_Pos)                               /*!< SPI SR: ABRT Mask                   */
#define SPI_SR_MODF_Pos                                       4                                                         /*!< SPI SR: MODF Position               */
#define SPI_SR_MODF_Msk                                       (0x01UL << SPI_SR_MODF_Pos)                               /*!< SPI SR: MODF Mask                   */
#define SPI_SR_ROVR_Pos                                       5                                                         /*!< SPI SR: ROVR Position               */
#define SPI_SR_ROVR_Msk                                       (0x01UL << SPI_SR_ROVR_Pos)                               /*!< SPI SR: ROVR Mask                   */
#define SPI_SR_WCOL_Pos                                       6                                                         /*!< SPI SR: WCOL Position               */
#define SPI_SR_WCOL_Msk                                       (0x01UL << SPI_SR_WCOL_Pos)                               /*!< SPI SR: WCOL Mask                   */
#define SPI_SR_SPIF_Pos                                       7                                                         /*!< SPI SR: SPIF Position               */
#define SPI_SR_SPIF_Msk                                       (0x01UL << SPI_SR_SPIF_Pos)                               /*!< SPI SR: SPIF Mask                   */

// -----------------------------------------  SPI_DR  ---------------------------------------------
#define SPI_DR_DATALOW_Pos                                    0                                                         /*!< SPI DR: DATALOW Position            */
#define SPI_DR_DATALOW_Msk                                    (0x000000ffUL << SPI_DR_DATALOW_Pos)                      /*!< SPI DR: DATALOW Mask                */
#define SPI_DR_DATAHIGH_Pos                                   8                                                         /*!< SPI DR: DATAHIGH Position           */
#define SPI_DR_DATAHIGH_Msk                                   (0x000000ffUL << SPI_DR_DATAHIGH_Pos)                     /*!< SPI DR: DATAHIGH Mask               */

// -----------------------------------------  SPI_CCR  --------------------------------------------
#define SPI_CCR_COUNTER_Pos                                   0                                                         /*!< SPI CCR: COUNTER Position           */
#define SPI_CCR_COUNTER_Msk                                   (0x000000ffUL << SPI_CCR_COUNTER_Pos)                     /*!< SPI CCR: COUNTER Mask               */

// -----------------------------------------  SPI_TCR  --------------------------------------------
#define SPI_TCR_TEST_Pos                                      1                                                         /*!< SPI TCR: TEST Position              */
#define SPI_TCR_TEST_Msk                                      (0x7fUL << SPI_TCR_TEST_Pos)                              /*!< SPI TCR: TEST Mask                  */

// -----------------------------------------  SPI_TSR  --------------------------------------------
#define SPI_TSR_ABRT_Pos                                      3                                                         /*!< SPI TSR: ABRT Position              */
#define SPI_TSR_ABRT_Msk                                      (0x01UL << SPI_TSR_ABRT_Pos)                              /*!< SPI TSR: ABRT Mask                  */
#define SPI_TSR_MODF_Pos                                      4                                                         /*!< SPI TSR: MODF Position              */
#define SPI_TSR_MODF_Msk                                      (0x01UL << SPI_TSR_MODF_Pos)                              /*!< SPI TSR: MODF Mask                  */
#define SPI_TSR_ROVR_Pos                                      5                                                         /*!< SPI TSR: ROVR Position              */
#define SPI_TSR_ROVR_Msk                                      (0x01UL << SPI_TSR_ROVR_Pos)                              /*!< SPI TSR: ROVR Mask                  */
#define SPI_TSR_WCOL_Pos                                      6                                                         /*!< SPI TSR: WCOL Position              */
#define SPI_TSR_WCOL_Msk                                      (0x01UL << SPI_TSR_WCOL_Pos)                              /*!< SPI TSR: WCOL Mask                  */
#define SPI_TSR_SPIF_Pos                                      7                                                         /*!< SPI TSR: SPIF Position              */
#define SPI_TSR_SPIF_Msk                                      (0x01UL << SPI_TSR_SPIF_Pos)                              /*!< SPI TSR: SPIF Mask                  */

// -----------------------------------------  SPI_INT  --------------------------------------------
#define SPI_INT_SPIF_Pos                                      0                                                         /*!< SPI INT: SPIF Position              */
#define SPI_INT_SPIF_Msk                                      (0x01UL << SPI_INT_SPIF_Pos)                              /*!< SPI INT: SPIF Mask                  */


// ------------------------------------------------------------------------------------------------
// -----                                 SGPIO Position & Mask                                -----
// ------------------------------------------------------------------------------------------------


// -----------------------------------  SGPIO_OUT_MUX_CFG0  ---------------------------------------
#define SGPIO_OUT_MUX_CFG0_P_OUT_CFG_Pos                      0                                                         /*!< SGPIO OUT_MUX_CFG0: P_OUT_CFG Position */
#define SGPIO_OUT_MUX_CFG0_P_OUT_CFG_Msk                      (0x0fUL << SGPIO_OUT_MUX_CFG0_P_OUT_CFG_Pos)              /*!< SGPIO OUT_MUX_CFG0: P_OUT_CFG Mask  */
#define SGPIO_OUT_MUX_CFG0_P_OE_CFG_Pos                       4                                                         /*!< SGPIO OUT_MUX_CFG0: P_OE_CFG Position */
#define SGPIO_OUT_MUX_CFG0_P_OE_CFG_Msk                       (0x07UL << SGPIO_OUT_MUX_CFG0_P_OE_CFG_Pos)               /*!< SGPIO OUT_MUX_CFG0: P_OE_CFG Mask   */

// -----------------------------------  SGPIO_OUT_MUX_CFG1  ---------------------------------------
#define SGPIO_OUT_MUX_CFG1_P_OUT_CFG_Pos                      0                                                         /*!< SGPIO OUT_MUX_CFG1: P_OUT_CFG Position */
#define SGPIO_OUT_MUX_CFG1_P_OUT_CFG_Msk                      (0x0fUL << SGPIO_OUT_MUX_CFG1_P_OUT_CFG_Pos)              /*!< SGPIO OUT_MUX_CFG1: P_OUT_CFG Mask  */
#define SGPIO_OUT_MUX_CFG1_P_OE_CFG_Pos                       4                                                         /*!< SGPIO OUT_MUX_CFG1: P_OE_CFG Position */
#define SGPIO_OUT_MUX_CFG1_P_OE_CFG_Msk                       (0x07UL << SGPIO_OUT_MUX_CFG1_P_OE_CFG_Pos)               /*!< SGPIO OUT_MUX_CFG1: P_OE_CFG Mask   */

// -----------------------------------  SGPIO_OUT_MUX_CFG2  ---------------------------------------
#define SGPIO_OUT_MUX_CFG2_P_OUT_CFG_Pos                      0                                                         /*!< SGPIO OUT_MUX_CFG2: P_OUT_CFG Position */
#define SGPIO_OUT_MUX_CFG2_P_OUT_CFG_Msk                      (0x0fUL << SGPIO_OUT_MUX_CFG2_P_OUT_CFG_Pos)              /*!< SGPIO OUT_MUX_CFG2: P_OUT_CFG Mask  */
#define SGPIO_OUT_MUX_CFG2_P_OE_CFG_Pos                       4                                                         /*!< SGPIO OUT_MUX_CFG2: P_OE_CFG Position */
#define SGPIO_OUT_MUX_CFG2_P_OE_CFG_Msk                       (0x07UL << SGPIO_OUT_MUX_CFG2_P_OE_CFG_Pos)               /*!< SGPIO OUT_MUX_CFG2: P_OE_CFG Mask   */

// -----------------------------------  SGPIO_OUT_MUX_CFG3  ---------------------------------------
#define SGPIO_OUT_MUX_CFG3_P_OUT_CFG_Pos                      0                                                         /*!< SGPIO OUT_MUX_CFG3: P_OUT_CFG Position */
#define SGPIO_OUT_MUX_CFG3_P_OUT_CFG_Msk                      (0x0fUL << SGPIO_OUT_MUX_CFG3_P_OUT_CFG_Pos)              /*!< SGPIO OUT_MUX_CFG3: P_OUT_CFG Mask  */
#define SGPIO_OUT_MUX_CFG3_P_OE_CFG_Pos                       4                                                         /*!< SGPIO OUT_MUX_CFG3: P_OE_CFG Position */
#define SGPIO_OUT_MUX_CFG3_P_OE_CFG_Msk                       (0x07UL << SGPIO_OUT_MUX_CFG3_P_OE_CFG_Pos)               /*!< SGPIO OUT_MUX_CFG3: P_OE_CFG Mask   */

// -----------------------------------  SGPIO_OUT_MUX_CFG4  ---------------------------------------
#define SGPIO_OUT_MUX_CFG4_P_OUT_CFG_Pos                      0                                                         /*!< SGPIO OUT_MUX_CFG4: P_OUT_CFG Position */
#define SGPIO_OUT_MUX_CFG4_P_OUT_CFG_Msk                      (0x0fUL << SGPIO_OUT_MUX_CFG4_P_OUT_CFG_Pos)              /*!< SGPIO OUT_MUX_CFG4: P_OUT_CFG Mask  */
#define SGPIO_OUT_MUX_CFG4_P_OE_CFG_Pos                       4                                                         /*!< SGPIO OUT_MUX_CFG4: P_OE_CFG Position */
#define SGPIO_OUT_MUX_CFG4_P_OE_CFG_Msk                       (0x07UL << SGPIO_OUT_MUX_CFG4_P_OE_CFG_Pos)               /*!< SGPIO OUT_MUX_CFG4: P_OE_CFG Mask   */

// -----------------------------------  SGPIO_OUT_MUX_CFG5  ---------------------------------------
#define SGPIO_OUT_MUX_CFG5_P_OUT_CFG_Pos                      0                                                         /*!< SGPIO OUT_MUX_CFG5: P_OUT_CFG Position */
#define SGPIO_OUT_MUX_CFG5_P_OUT_CFG_Msk                      (0x0fUL << SGPIO_OUT_MUX_CFG5_P_OUT_CFG_Pos)              /*!< SGPIO OUT_MUX_CFG5: P_OUT_CFG Mask  */
#define SGPIO_OUT_MUX_CFG5_P_OE_CFG_Pos                       4                                                         /*!< SGPIO OUT_MUX_CFG5: P_OE_CFG Position */
#define SGPIO_OUT_MUX_CFG5_P_OE_CFG_Msk                       (0x07UL << SGPIO_OUT_MUX_CFG5_P_OE_CFG_Pos)               /*!< SGPIO OUT_MUX_CFG5: P_OE_CFG Mask   */

// -----------------------------------  SGPIO_OUT_MUX_CFG6  ---------------------------------------
#define SGPIO_OUT_MUX_CFG6_P_OUT_CFG_Pos                      0                                                         /*!< SGPIO OUT_MUX_CFG6: P_OUT_CFG Position */
#define SGPIO_OUT_MUX_CFG6_P_OUT_CFG_Msk                      (0x0fUL << SGPIO_OUT_MUX_CFG6_P_OUT_CFG_Pos)              /*!< SGPIO OUT_MUX_CFG6: P_OUT_CFG Mask  */
#define SGPIO_OUT_MUX_CFG6_P_OE_CFG_Pos                       4                                                         /*!< SGPIO OUT_MUX_CFG6: P_OE_CFG Position */
#define SGPIO_OUT_MUX_CFG6_P_OE_CFG_Msk                       (0x07UL << SGPIO_OUT_MUX_CFG6_P_OE_CFG_Pos)               /*!< SGPIO OUT_MUX_CFG6: P_OE_CFG Mask   */

// -----------------------------------  SGPIO_OUT_MUX_CFG7  ---------------------------------------
#define SGPIO_OUT_MUX_CFG7_P_OUT_CFG_Pos                      0                                                         /*!< SGPIO OUT_MUX_CFG7: P_OUT_CFG Position */
#define SGPIO_OUT_MUX_CFG7_P_OUT_CFG_Msk                      (0x0fUL << SGPIO_OUT_MUX_CFG7_P_OUT_CFG_Pos)              /*!< SGPIO OUT_MUX_CFG7: P_OUT_CFG Mask  */
#define SGPIO_OUT_MUX_CFG7_P_OE_CFG_Pos                       4                                                         /*!< SGPIO OUT_MUX_CFG7: P_OE_CFG Position */
#define SGPIO_OUT_MUX_CFG7_P_OE_CFG_Msk                       (0x07UL << SGPIO_OUT_MUX_CFG7_P_OE_CFG_Pos)               /*!< SGPIO OUT_MUX_CFG7: P_OE_CFG Mask   */

// -----------------------------------  SGPIO_OUT_MUX_CFG8  ---------------------------------------
#define SGPIO_OUT_MUX_CFG8_P_OUT_CFG_Pos                      0                                                         /*!< SGPIO OUT_MUX_CFG8: P_OUT_CFG Position */
#define SGPIO_OUT_MUX_CFG8_P_OUT_CFG_Msk                      (0x0fUL << SGPIO_OUT_MUX_CFG8_P_OUT_CFG_Pos)              /*!< SGPIO OUT_MUX_CFG8: P_OUT_CFG Mask  */
#define SGPIO_OUT_MUX_CFG8_P_OE_CFG_Pos                       4                                                         /*!< SGPIO OUT_MUX_CFG8: P_OE_CFG Position */
#define SGPIO_OUT_MUX_CFG8_P_OE_CFG_Msk                       (0x07UL << SGPIO_OUT_MUX_CFG8_P_OE_CFG_Pos)               /*!< SGPIO OUT_MUX_CFG8: P_OE_CFG Mask   */

// -----------------------------------  SGPIO_OUT_MUX_CFG9  ---------------------------------------
#define SGPIO_OUT_MUX_CFG9_P_OUT_CFG_Pos                      0                                                         /*!< SGPIO OUT_MUX_CFG9: P_OUT_CFG Position */
#define SGPIO_OUT_MUX_CFG9_P_OUT_CFG_Msk                      (0x0fUL << SGPIO_OUT_MUX_CFG9_P_OUT_CFG_Pos)              /*!< SGPIO OUT_MUX_CFG9: P_OUT_CFG Mask  */
#define SGPIO_OUT_MUX_CFG9_P_OE_CFG_Pos                       4                                                         /*!< SGPIO OUT_MUX_CFG9: P_OE_CFG Position */
#define SGPIO_OUT_MUX_CFG9_P_OE_CFG_Msk                       (0x07UL << SGPIO_OUT_MUX_CFG9_P_OE_CFG_Pos)               /*!< SGPIO OUT_MUX_CFG9: P_OE_CFG Mask   */

// -----------------------------------  SGPIO_OUT_MUX_CFG10  --------------------------------------
#define SGPIO_OUT_MUX_CFG10_P_OUT_CFG_Pos                     0                                                         /*!< SGPIO OUT_MUX_CFG10: P_OUT_CFG Position */
#define SGPIO_OUT_MUX_CFG10_P_OUT_CFG_Msk                     (0x0fUL << SGPIO_OUT_MUX_CFG10_P_OUT_CFG_Pos)             /*!< SGPIO OUT_MUX_CFG10: P_OUT_CFG Mask */
#define SGPIO_OUT_MUX_CFG10_P_OE_CFG_Pos                      4                                                         /*!< SGPIO OUT_MUX_CFG10: P_OE_CFG Position */
#define SGPIO_OUT_MUX_CFG10_P_OE_CFG_Msk                      (0x07UL << SGPIO_OUT_MUX_CFG10_P_OE_CFG_Pos)              /*!< SGPIO OUT_MUX_CFG10: P_OE_CFG Mask  */

// -----------------------------------  SGPIO_OUT_MUX_CFG11  --------------------------------------
#define SGPIO_OUT_MUX_CFG11_P_OUT_CFG_Pos                     0                                                         /*!< SGPIO OUT_MUX_CFG11: P_OUT_CFG Position */
#define SGPIO_OUT_MUX_CFG11_P_OUT_CFG_Msk                     (0x0fUL << SGPIO_OUT_MUX_CFG11_P_OUT_CFG_Pos)             /*!< SGPIO OUT_MUX_CFG11: P_OUT_CFG Mask */
#define SGPIO_OUT_MUX_CFG11_P_OE_CFG_Pos                      4                                                         /*!< SGPIO OUT_MUX_CFG11: P_OE_CFG Position */
#define SGPIO_OUT_MUX_CFG11_P_OE_CFG_Msk                      (0x07UL << SGPIO_OUT_MUX_CFG11_P_OE_CFG_Pos)              /*!< SGPIO OUT_MUX_CFG11: P_OE_CFG Mask  */

// -----------------------------------  SGPIO_OUT_MUX_CFG12  --------------------------------------
#define SGPIO_OUT_MUX_CFG12_P_OUT_CFG_Pos                     0                                                         /*!< SGPIO OUT_MUX_CFG12: P_OUT_CFG Position */
#define SGPIO_OUT_MUX_CFG12_P_OUT_CFG_Msk                     (0x0fUL << SGPIO_OUT_MUX_CFG12_P_OUT_CFG_Pos)             /*!< SGPIO OUT_MUX_CFG12: P_OUT_CFG Mask */
#define SGPIO_OUT_MUX_CFG12_P_OE_CFG_Pos                      4                                                         /*!< SGPIO OUT_MUX_CFG12: P_OE_CFG Position */
#define SGPIO_OUT_MUX_CFG12_P_OE_CFG_Msk                      (0x07UL << SGPIO_OUT_MUX_CFG12_P_OE_CFG_Pos)              /*!< SGPIO OUT_MUX_CFG12: P_OE_CFG Mask  */

// -----------------------------------  SGPIO_OUT_MUX_CFG13  --------------------------------------
#define SGPIO_OUT_MUX_CFG13_P_OUT_CFG_Pos                     0                                                         /*!< SGPIO OUT_MUX_CFG13: P_OUT_CFG Position */
#define SGPIO_OUT_MUX_CFG13_P_OUT_CFG_Msk                     (0x0fUL << SGPIO_OUT_MUX_CFG13_P_OUT_CFG_Pos)             /*!< SGPIO OUT_MUX_CFG13: P_OUT_CFG Mask */
#define SGPIO_OUT_MUX_CFG13_P_OE_CFG_Pos                      4                                                         /*!< SGPIO OUT_MUX_CFG13: P_OE_CFG Position */
#define SGPIO_OUT_MUX_CFG13_P_OE_CFG_Msk                      (0x07UL << SGPIO_OUT_MUX_CFG13_P_OE_CFG_Pos)              /*!< SGPIO OUT_MUX_CFG13: P_OE_CFG Mask  */

// -----------------------------------  SGPIO_OUT_MUX_CFG14  --------------------------------------
#define SGPIO_OUT_MUX_CFG14_P_OUT_CFG_Pos                     0                                                         /*!< SGPIO OUT_MUX_CFG14: P_OUT_CFG Position */
#define SGPIO_OUT_MUX_CFG14_P_OUT_CFG_Msk                     (0x0fUL << SGPIO_OUT_MUX_CFG14_P_OUT_CFG_Pos)             /*!< SGPIO OUT_MUX_CFG14: P_OUT_CFG Mask */
#define SGPIO_OUT_MUX_CFG14_P_OE_CFG_Pos                      4                                                         /*!< SGPIO OUT_MUX_CFG14: P_OE_CFG Position */
#define SGPIO_OUT_MUX_CFG14_P_OE_CFG_Msk                      (0x07UL << SGPIO_OUT_MUX_CFG14_P_OE_CFG_Pos)              /*!< SGPIO OUT_MUX_CFG14: P_OE_CFG Mask  */

// -----------------------------------  SGPIO_OUT_MUX_CFG15  --------------------------------------
#define SGPIO_OUT_MUX_CFG15_P_OUT_CFG_Pos                     0                                                         /*!< SGPIO OUT_MUX_CFG15: P_OUT_CFG Position */
#define SGPIO_OUT_MUX_CFG15_P_OUT_CFG_Msk                     (0x0fUL << SGPIO_OUT_MUX_CFG15_P_OUT_CFG_Pos)             /*!< SGPIO OUT_MUX_CFG15: P_OUT_CFG Mask */
#define SGPIO_OUT_MUX_CFG15_P_OE_CFG_Pos                      4                                                         /*!< SGPIO OUT_MUX_CFG15: P_OE_CFG Position */
#define SGPIO_OUT_MUX_CFG15_P_OE_CFG_Msk                      (0x07UL << SGPIO_OUT_MUX_CFG15_P_OE_CFG_Pos)              /*!< SGPIO OUT_MUX_CFG15: P_OE_CFG Mask  */

// ----------------------------------  SGPIO_SGPIO_MUX_CFG0  --------------------------------------
#define SGPIO_SGPIO_MUX_CFG0_EXT_CLK_ENABLE_Pos               0                                                         /*!< SGPIO SGPIO_MUX_CFG0: EXT_CLK_ENABLE Position */
#define SGPIO_SGPIO_MUX_CFG0_EXT_CLK_ENABLE_Msk               (0x01UL << SGPIO_SGPIO_MUX_CFG0_EXT_CLK_ENABLE_Pos)       /*!< SGPIO SGPIO_MUX_CFG0: EXT_CLK_ENABLE Mask */
#define SGPIO_SGPIO_MUX_CFG0_CLK_SOURCE_PIN_MODE_Pos          1                                                         /*!< SGPIO SGPIO_MUX_CFG0: CLK_SOURCE_PIN_MODE Position */
#define SGPIO_SGPIO_MUX_CFG0_CLK_SOURCE_PIN_MODE_Msk          (0x03UL << SGPIO_SGPIO_MUX_CFG0_CLK_SOURCE_PIN_MODE_Pos)  /*!< SGPIO SGPIO_MUX_CFG0: CLK_SOURCE_PIN_MODE Mask */
#define SGPIO_SGPIO_MUX_CFG0_CLK_SOURCE_SLICE_MODE_Pos        3                                                         /*!< SGPIO SGPIO_MUX_CFG0: CLK_SOURCE_SLICE_MODE Position */
#define SGPIO_SGPIO_MUX_CFG0_CLK_SOURCE_SLICE_MODE_Msk        (0x03UL << SGPIO_SGPIO_MUX_CFG0_CLK_SOURCE_SLICE_MODE_Pos)/*!< SGPIO SGPIO_MUX_CFG0: CLK_SOURCE_SLICE_MODE Mask */
#define SGPIO_SGPIO_MUX_CFG0_QUALIFIER_MODE_Pos               5                                                         /*!< SGPIO SGPIO_MUX_CFG0: QUALIFIER_MODE Position */
#define SGPIO_SGPIO_MUX_CFG0_QUALIFIER_MODE_Msk               (0x03UL << SGPIO_SGPIO_MUX_CFG0_QUALIFIER_MODE_Pos)       /*!< SGPIO SGPIO_MUX_CFG0: QUALIFIER_MODE Mask */
#define SGPIO_SGPIO_MUX_CFG0_QUALIFIER_PIN_MODE_Pos           7                                                         /*!< SGPIO SGPIO_MUX_CFG0: QUALIFIER_PIN_MODE Position */
#define SGPIO_SGPIO_MUX_CFG0_QUALIFIER_PIN_MODE_Msk           (0x03UL << SGPIO_SGPIO_MUX_CFG0_QUALIFIER_PIN_MODE_Pos)   /*!< SGPIO SGPIO_MUX_CFG0: QUALIFIER_PIN_MODE Mask */
#define SGPIO_SGPIO_MUX_CFG0_QUALIFIER_SLICE_MODE_Pos         9                                                         /*!< SGPIO SGPIO_MUX_CFG0: QUALIFIER_SLICE_MODE Position */
#define SGPIO_SGPIO_MUX_CFG0_QUALIFIER_SLICE_MODE_Msk         (0x03UL << SGPIO_SGPIO_MUX_CFG0_QUALIFIER_SLICE_MODE_Pos) /*!< SGPIO SGPIO_MUX_CFG0: QUALIFIER_SLICE_MODE Mask */
#define SGPIO_SGPIO_MUX_CFG0_CONCAT_ENABLE_Pos                11                                                        /*!< SGPIO SGPIO_MUX_CFG0: CONCAT_ENABLE Position */
#define SGPIO_SGPIO_MUX_CFG0_CONCAT_ENABLE_Msk                (0x01UL << SGPIO_SGPIO_MUX_CFG0_CONCAT_ENABLE_Pos)        /*!< SGPIO SGPIO_MUX_CFG0: CONCAT_ENABLE Mask */
#define SGPIO_SGPIO_MUX_CFG0_CONCAT_ORDER_Pos                 12                                                        /*!< SGPIO SGPIO_MUX_CFG0: CONCAT_ORDER Position */
#define SGPIO_SGPIO_MUX_CFG0_CONCAT_ORDER_Msk                 (0x03UL << SGPIO_SGPIO_MUX_CFG0_CONCAT_ORDER_Pos)         /*!< SGPIO SGPIO_MUX_CFG0: CONCAT_ORDER Mask */

// ----------------------------------  SGPIO_SGPIO_MUX_CFG1  --------------------------------------
#define SGPIO_SGPIO_MUX_CFG1_EXT_CLK_ENABLE_Pos               0                                                         /*!< SGPIO SGPIO_MUX_CFG1: EXT_CLK_ENABLE Position */
#define SGPIO_SGPIO_MUX_CFG1_EXT_CLK_ENABLE_Msk               (0x01UL << SGPIO_SGPIO_MUX_CFG1_EXT_CLK_ENABLE_Pos)       /*!< SGPIO SGPIO_MUX_CFG1: EXT_CLK_ENABLE Mask */
#define SGPIO_SGPIO_MUX_CFG1_CLK_SOURCE_PIN_MODE_Pos          1                                                         /*!< SGPIO SGPIO_MUX_CFG1: CLK_SOURCE_PIN_MODE Position */
#define SGPIO_SGPIO_MUX_CFG1_CLK_SOURCE_PIN_MODE_Msk          (0x03UL << SGPIO_SGPIO_MUX_CFG1_CLK_SOURCE_PIN_MODE_Pos)  /*!< SGPIO SGPIO_MUX_CFG1: CLK_SOURCE_PIN_MODE Mask */
#define SGPIO_SGPIO_MUX_CFG1_CLK_SOURCE_SLICE_MODE_Pos        3                                                         /*!< SGPIO SGPIO_MUX_CFG1: CLK_SOURCE_SLICE_MODE Position */
#define SGPIO_SGPIO_MUX_CFG1_CLK_SOURCE_SLICE_MODE_Msk        (0x03UL << SGPIO_SGPIO_MUX_CFG1_CLK_SOURCE_SLICE_MODE_Pos)/*!< SGPIO SGPIO_MUX_CFG1: CLK_SOURCE_SLICE_MODE Mask */
#define SGPIO_SGPIO_MUX_CFG1_QUALIFIER_MODE_Pos               5                                                         /*!< SGPIO SGPIO_MUX_CFG1: QUALIFIER_MODE Position */
#define SGPIO_SGPIO_MUX_CFG1_QUALIFIER_MODE_Msk               (0x03UL << SGPIO_SGPIO_MUX_CFG1_QUALIFIER_MODE_Pos)       /*!< SGPIO SGPIO_MUX_CFG1: QUALIFIER_MODE Mask */
#define SGPIO_SGPIO_MUX_CFG1_QUALIFIER_PIN_MODE_Pos           7                                                         /*!< SGPIO SGPIO_MUX_CFG1: QUALIFIER_PIN_MODE Position */
#define SGPIO_SGPIO_MUX_CFG1_QUALIFIER_PIN_MODE_Msk           (0x03UL << SGPIO_SGPIO_MUX_CFG1_QUALIFIER_PIN_MODE_Pos)   /*!< SGPIO SGPIO_MUX_CFG1: QUALIFIER_PIN_MODE Mask */
#define SGPIO_SGPIO_MUX_CFG1_QUALIFIER_SLICE_MODE_Pos         9                                                         /*!< SGPIO SGPIO_MUX_CFG1: QUALIFIER_SLICE_MODE Position */
#define SGPIO_SGPIO_MUX_CFG1_QUALIFIER_SLICE_MODE_Msk         (0x03UL << SGPIO_SGPIO_MUX_CFG1_QUALIFIER_SLICE_MODE_Pos) /*!< SGPIO SGPIO_MUX_CFG1: QUALIFIER_SLICE_MODE Mask */
#define SGPIO_SGPIO_MUX_CFG1_CONCAT_ENABLE_Pos                11                                                        /*!< SGPIO SGPIO_MUX_CFG1: CONCAT_ENABLE Position */
#define SGPIO_SGPIO_MUX_CFG1_CONCAT_ENABLE_Msk                (0x01UL << SGPIO_SGPIO_MUX_CFG1_CONCAT_ENABLE_Pos)        /*!< SGPIO SGPIO_MUX_CFG1: CONCAT_ENABLE Mask */
#define SGPIO_SGPIO_MUX_CFG1_CONCAT_ORDER_Pos                 12                                                        /*!< SGPIO SGPIO_MUX_CFG1: CONCAT_ORDER Position */
#define SGPIO_SGPIO_MUX_CFG1_CONCAT_ORDER_Msk                 (0x03UL << SGPIO_SGPIO_MUX_CFG1_CONCAT_ORDER_Pos)         /*!< SGPIO SGPIO_MUX_CFG1: CONCAT_ORDER Mask */

// ----------------------------------  SGPIO_SGPIO_MUX_CFG2  --------------------------------------
#define SGPIO_SGPIO_MUX_CFG2_EXT_CLK_ENABLE_Pos               0                                                         /*!< SGPIO SGPIO_MUX_CFG2: EXT_CLK_ENABLE Position */
#define SGPIO_SGPIO_MUX_CFG2_EXT_CLK_ENABLE_Msk               (0x01UL << SGPIO_SGPIO_MUX_CFG2_EXT_CLK_ENABLE_Pos)       /*!< SGPIO SGPIO_MUX_CFG2: EXT_CLK_ENABLE Mask */
#define SGPIO_SGPIO_MUX_CFG2_CLK_SOURCE_PIN_MODE_Pos          1                                                         /*!< SGPIO SGPIO_MUX_CFG2: CLK_SOURCE_PIN_MODE Position */
#define SGPIO_SGPIO_MUX_CFG2_CLK_SOURCE_PIN_MODE_Msk          (0x03UL << SGPIO_SGPIO_MUX_CFG2_CLK_SOURCE_PIN_MODE_Pos)  /*!< SGPIO SGPIO_MUX_CFG2: CLK_SOURCE_PIN_MODE Mask */
#define SGPIO_SGPIO_MUX_CFG2_CLK_SOURCE_SLICE_MODE_Pos        3                                                         /*!< SGPIO SGPIO_MUX_CFG2: CLK_SOURCE_SLICE_MODE Position */
#define SGPIO_SGPIO_MUX_CFG2_CLK_SOURCE_SLICE_MODE_Msk        (0x03UL << SGPIO_SGPIO_MUX_CFG2_CLK_SOURCE_SLICE_MODE_Pos)/*!< SGPIO SGPIO_MUX_CFG2: CLK_SOURCE_SLICE_MODE Mask */
#define SGPIO_SGPIO_MUX_CFG2_QUALIFIER_MODE_Pos               5                                                         /*!< SGPIO SGPIO_MUX_CFG2: QUALIFIER_MODE Position */
#define SGPIO_SGPIO_MUX_CFG2_QUALIFIER_MODE_Msk               (0x03UL << SGPIO_SGPIO_MUX_CFG2_QUALIFIER_MODE_Pos)       /*!< SGPIO SGPIO_MUX_CFG2: QUALIFIER_MODE Mask */
#define SGPIO_SGPIO_MUX_CFG2_QUALIFIER_PIN_MODE_Pos           7                                                         /*!< SGPIO SGPIO_MUX_CFG2: QUALIFIER_PIN_MODE Position */
#define SGPIO_SGPIO_MUX_CFG2_QUALIFIER_PIN_MODE_Msk           (0x03UL << SGPIO_SGPIO_MUX_CFG2_QUALIFIER_PIN_MODE_Pos)   /*!< SGPIO SGPIO_MUX_CFG2: QUALIFIER_PIN_MODE Mask */
#define SGPIO_SGPIO_MUX_CFG2_QUALIFIER_SLICE_MODE_Pos         9                                                         /*!< SGPIO SGPIO_MUX_CFG2: QUALIFIER_SLICE_MODE Position */
#define SGPIO_SGPIO_MUX_CFG2_QUALIFIER_SLICE_MODE_Msk         (0x03UL << SGPIO_SGPIO_MUX_CFG2_QUALIFIER_SLICE_MODE_Pos) /*!< SGPIO SGPIO_MUX_CFG2: QUALIFIER_SLICE_MODE Mask */
#define SGPIO_SGPIO_MUX_CFG2_CONCAT_ENABLE_Pos                11                                                        /*!< SGPIO SGPIO_MUX_CFG2: CONCAT_ENABLE Position */
#define SGPIO_SGPIO_MUX_CFG2_CONCAT_ENABLE_Msk                (0x01UL << SGPIO_SGPIO_MUX_CFG2_CONCAT_ENABLE_Pos)        /*!< SGPIO SGPIO_MUX_CFG2: CONCAT_ENABLE Mask */
#define SGPIO_SGPIO_MUX_CFG2_CONCAT_ORDER_Pos                 12                                                        /*!< SGPIO SGPIO_MUX_CFG2: CONCAT_ORDER Position */
#define SGPIO_SGPIO_MUX_CFG2_CONCAT_ORDER_Msk                 (0x03UL << SGPIO_SGPIO_MUX_CFG2_CONCAT_ORDER_Pos)         /*!< SGPIO SGPIO_MUX_CFG2: CONCAT_ORDER Mask */

// ----------------------------------  SGPIO_SGPIO_MUX_CFG3  --------------------------------------
#define SGPIO_SGPIO_MUX_CFG3_EXT_CLK_ENABLE_Pos               0                                                         /*!< SGPIO SGPIO_MUX_CFG3: EXT_CLK_ENABLE Position */
#define SGPIO_SGPIO_MUX_CFG3_EXT_CLK_ENABLE_Msk               (0x01UL << SGPIO_SGPIO_MUX_CFG3_EXT_CLK_ENABLE_Pos)       /*!< SGPIO SGPIO_MUX_CFG3: EXT_CLK_ENABLE Mask */
#define SGPIO_SGPIO_MUX_CFG3_CLK_SOURCE_PIN_MODE_Pos          1                                                         /*!< SGPIO SGPIO_MUX_CFG3: CLK_SOURCE_PIN_MODE Position */
#define SGPIO_SGPIO_MUX_CFG3_CLK_SOURCE_PIN_MODE_Msk          (0x03UL << SGPIO_SGPIO_MUX_CFG3_CLK_SOURCE_PIN_MODE_Pos)  /*!< SGPIO SGPIO_MUX_CFG3: CLK_SOURCE_PIN_MODE Mask */
#define SGPIO_SGPIO_MUX_CFG3_CLK_SOURCE_SLICE_MODE_Pos        3                                                         /*!< SGPIO SGPIO_MUX_CFG3: CLK_SOURCE_SLICE_MODE Position */
#define SGPIO_SGPIO_MUX_CFG3_CLK_SOURCE_SLICE_MODE_Msk        (0x03UL << SGPIO_SGPIO_MUX_CFG3_CLK_SOURCE_SLICE_MODE_Pos)/*!< SGPIO SGPIO_MUX_CFG3: CLK_SOURCE_SLICE_MODE Mask */
#define SGPIO_SGPIO_MUX_CFG3_QUALIFIER_MODE_Pos               5                                                         /*!< SGPIO SGPIO_MUX_CFG3: QUALIFIER_MODE Position */
#define SGPIO_SGPIO_MUX_CFG3_QUALIFIER_MODE_Msk               (0x03UL << SGPIO_SGPIO_MUX_CFG3_QUALIFIER_MODE_Pos)       /*!< SGPIO SGPIO_MUX_CFG3: QUALIFIER_MODE Mask */
#define SGPIO_SGPIO_MUX_CFG3_QUALIFIER_PIN_MODE_Pos           7                                                         /*!< SGPIO SGPIO_MUX_CFG3: QUALIFIER_PIN_MODE Position */
#define SGPIO_SGPIO_MUX_CFG3_QUALIFIER_PIN_MODE_Msk           (0x03UL << SGPIO_SGPIO_MUX_CFG3_QUALIFIER_PIN_MODE_Pos)   /*!< SGPIO SGPIO_MUX_CFG3: QUALIFIER_PIN_MODE Mask */
#define SGPIO_SGPIO_MUX_CFG3_QUALIFIER_SLICE_MODE_Pos         9                                                         /*!< SGPIO SGPIO_MUX_CFG3: QUALIFIER_SLICE_MODE Position */
#define SGPIO_SGPIO_MUX_CFG3_QUALIFIER_SLICE_MODE_Msk         (0x03UL << SGPIO_SGPIO_MUX_CFG3_QUALIFIER_SLICE_MODE_Pos) /*!< SGPIO SGPIO_MUX_CFG3: QUALIFIER_SLICE_MODE Mask */
#define SGPIO_SGPIO_MUX_CFG3_CONCAT_ENABLE_Pos                11                                                        /*!< SGPIO SGPIO_MUX_CFG3: CONCAT_ENABLE Position */
#define SGPIO_SGPIO_MUX_CFG3_CONCAT_ENABLE_Msk                (0x01UL << SGPIO_SGPIO_MUX_CFG3_CONCAT_ENABLE_Pos)        /*!< SGPIO SGPIO_MUX_CFG3: CONCAT_ENABLE Mask */
#define SGPIO_SGPIO_MUX_CFG3_CONCAT_ORDER_Pos                 12                                                        /*!< SGPIO SGPIO_MUX_CFG3: CONCAT_ORDER Position */
#define SGPIO_SGPIO_MUX_CFG3_CONCAT_ORDER_Msk                 (0x03UL << SGPIO_SGPIO_MUX_CFG3_CONCAT_ORDER_Pos)         /*!< SGPIO SGPIO_MUX_CFG3: CONCAT_ORDER Mask */

// ----------------------------------  SGPIO_SGPIO_MUX_CFG4  --------------------------------------
#define SGPIO_SGPIO_MUX_CFG4_EXT_CLK_ENABLE_Pos               0                                                         /*!< SGPIO SGPIO_MUX_CFG4: EXT_CLK_ENABLE Position */
#define SGPIO_SGPIO_MUX_CFG4_EXT_CLK_ENABLE_Msk               (0x01UL << SGPIO_SGPIO_MUX_CFG4_EXT_CLK_ENABLE_Pos)       /*!< SGPIO SGPIO_MUX_CFG4: EXT_CLK_ENABLE Mask */
#define SGPIO_SGPIO_MUX_CFG4_CLK_SOURCE_PIN_MODE_Pos          1                                                         /*!< SGPIO SGPIO_MUX_CFG4: CLK_SOURCE_PIN_MODE Position */
#define SGPIO_SGPIO_MUX_CFG4_CLK_SOURCE_PIN_MODE_Msk          (0x03UL << SGPIO_SGPIO_MUX_CFG4_CLK_SOURCE_PIN_MODE_Pos)  /*!< SGPIO SGPIO_MUX_CFG4: CLK_SOURCE_PIN_MODE Mask */
#define SGPIO_SGPIO_MUX_CFG4_CLK_SOURCE_SLICE_MODE_Pos        3                                                         /*!< SGPIO SGPIO_MUX_CFG4: CLK_SOURCE_SLICE_MODE Position */
#define SGPIO_SGPIO_MUX_CFG4_CLK_SOURCE_SLICE_MODE_Msk        (0x03UL << SGPIO_SGPIO_MUX_CFG4_CLK_SOURCE_SLICE_MODE_Pos)/*!< SGPIO SGPIO_MUX_CFG4: CLK_SOURCE_SLICE_MODE Mask */
#define SGPIO_SGPIO_MUX_CFG4_QUALIFIER_MODE_Pos               5                                                         /*!< SGPIO SGPIO_MUX_CFG4: QUALIFIER_MODE Position */
#define SGPIO_SGPIO_MUX_CFG4_QUALIFIER_MODE_Msk               (0x03UL << SGPIO_SGPIO_MUX_CFG4_QUALIFIER_MODE_Pos)       /*!< SGPIO SGPIO_MUX_CFG4: QUALIFIER_MODE Mask */
#define SGPIO_SGPIO_MUX_CFG4_QUALIFIER_PIN_MODE_Pos           7                                                         /*!< SGPIO SGPIO_MUX_CFG4: QUALIFIER_PIN_MODE Position */
#define SGPIO_SGPIO_MUX_CFG4_QUALIFIER_PIN_MODE_Msk           (0x03UL << SGPIO_SGPIO_MUX_CFG4_QUALIFIER_PIN_MODE_Pos)   /*!< SGPIO SGPIO_MUX_CFG4: QUALIFIER_PIN_MODE Mask */
#define SGPIO_SGPIO_MUX_CFG4_QUALIFIER_SLICE_MODE_Pos         9                                                         /*!< SGPIO SGPIO_MUX_CFG4: QUALIFIER_SLICE_MODE Position */
#define SGPIO_SGPIO_MUX_CFG4_QUALIFIER_SLICE_MODE_Msk         (0x03UL << SGPIO_SGPIO_MUX_CFG4_QUALIFIER_SLICE_MODE_Pos) /*!< SGPIO SGPIO_MUX_CFG4: QUALIFIER_SLICE_MODE Mask */
#define SGPIO_SGPIO_MUX_CFG4_CONCAT_ENABLE_Pos                11                                                        /*!< SGPIO SGPIO_MUX_CFG4: CONCAT_ENABLE Position */
#define SGPIO_SGPIO_MUX_CFG4_CONCAT_ENABLE_Msk                (0x01UL << SGPIO_SGPIO_MUX_CFG4_CONCAT_ENABLE_Pos)        /*!< SGPIO SGPIO_MUX_CFG4: CONCAT_ENABLE Mask */
#define SGPIO_SGPIO_MUX_CFG4_CONCAT_ORDER_Pos                 12                                                        /*!< SGPIO SGPIO_MUX_CFG4: CONCAT_ORDER Position */
#define SGPIO_SGPIO_MUX_CFG4_CONCAT_ORDER_Msk                 (0x03UL << SGPIO_SGPIO_MUX_CFG4_CONCAT_ORDER_Pos)         /*!< SGPIO SGPIO_MUX_CFG4: CONCAT_ORDER Mask */

// ----------------------------------  SGPIO_SGPIO_MUX_CFG5  --------------------------------------
#define SGPIO_SGPIO_MUX_CFG5_EXT_CLK_ENABLE_Pos               0                                                         /*!< SGPIO SGPIO_MUX_CFG5: EXT_CLK_ENABLE Position */
#define SGPIO_SGPIO_MUX_CFG5_EXT_CLK_ENABLE_Msk               (0x01UL << SGPIO_SGPIO_MUX_CFG5_EXT_CLK_ENABLE_Pos)       /*!< SGPIO SGPIO_MUX_CFG5: EXT_CLK_ENABLE Mask */
#define SGPIO_SGPIO_MUX_CFG5_CLK_SOURCE_PIN_MODE_Pos          1                                                         /*!< SGPIO SGPIO_MUX_CFG5: CLK_SOURCE_PIN_MODE Position */
#define SGPIO_SGPIO_MUX_CFG5_CLK_SOURCE_PIN_MODE_Msk          (0x03UL << SGPIO_SGPIO_MUX_CFG5_CLK_SOURCE_PIN_MODE_Pos)  /*!< SGPIO SGPIO_MUX_CFG5: CLK_SOURCE_PIN_MODE Mask */
#define SGPIO_SGPIO_MUX_CFG5_CLK_SOURCE_SLICE_MODE_Pos        3                                                         /*!< SGPIO SGPIO_MUX_CFG5: CLK_SOURCE_SLICE_MODE Position */
#define SGPIO_SGPIO_MUX_CFG5_CLK_SOURCE_SLICE_MODE_Msk        (0x03UL << SGPIO_SGPIO_MUX_CFG5_CLK_SOURCE_SLICE_MODE_Pos)/*!< SGPIO SGPIO_MUX_CFG5: CLK_SOURCE_SLICE_MODE Mask */
#define SGPIO_SGPIO_MUX_CFG5_QUALIFIER_MODE_Pos               5                                                         /*!< SGPIO SGPIO_MUX_CFG5: QUALIFIER_MODE Position */
#define SGPIO_SGPIO_MUX_CFG5_QUALIFIER_MODE_Msk               (0x03UL << SGPIO_SGPIO_MUX_CFG5_QUALIFIER_MODE_Pos)       /*!< SGPIO SGPIO_MUX_CFG5: QUALIFIER_MODE Mask */
#define SGPIO_SGPIO_MUX_CFG5_QUALIFIER_PIN_MODE_Pos           7                                                         /*!< SGPIO SGPIO_MUX_CFG5: QUALIFIER_PIN_MODE Position */
#define SGPIO_SGPIO_MUX_CFG5_QUALIFIER_PIN_MODE_Msk           (0x03UL << SGPIO_SGPIO_MUX_CFG5_QUALIFIER_PIN_MODE_Pos)   /*!< SGPIO SGPIO_MUX_CFG5: QUALIFIER_PIN_MODE Mask */
#define SGPIO_SGPIO_MUX_CFG5_QUALIFIER_SLICE_MODE_Pos         9                                                         /*!< SGPIO SGPIO_MUX_CFG5: QUALIFIER_SLICE_MODE Position */
#define SGPIO_SGPIO_MUX_CFG5_QUALIFIER_SLICE_MODE_Msk         (0x03UL << SGPIO_SGPIO_MUX_CFG5_QUALIFIER_SLICE_MODE_Pos) /*!< SGPIO SGPIO_MUX_CFG5: QUALIFIER_SLICE_MODE Mask */
#define SGPIO_SGPIO_MUX_CFG5_CONCAT_ENABLE_Pos                11                                                        /*!< SGPIO SGPIO_MUX_CFG5: CONCAT_ENABLE Position */
#define SGPIO_SGPIO_MUX_CFG5_CONCAT_ENABLE_Msk                (0x01UL << SGPIO_SGPIO_MUX_CFG5_CONCAT_ENABLE_Pos)        /*!< SGPIO SGPIO_MUX_CFG5: CONCAT_ENABLE Mask */
#define SGPIO_SGPIO_MUX_CFG5_CONCAT_ORDER_Pos                 12                                                        /*!< SGPIO SGPIO_MUX_CFG5: CONCAT_ORDER Position */
#define SGPIO_SGPIO_MUX_CFG5_CONCAT_ORDER_Msk                 (0x03UL << SGPIO_SGPIO_MUX_CFG5_CONCAT_ORDER_Pos)         /*!< SGPIO SGPIO_MUX_CFG5: CONCAT_ORDER Mask */

// ----------------------------------  SGPIO_SGPIO_MUX_CFG6  --------------------------------------
#define SGPIO_SGPIO_MUX_CFG6_EXT_CLK_ENABLE_Pos               0                                                         /*!< SGPIO SGPIO_MUX_CFG6: EXT_CLK_ENABLE Position */
#define SGPIO_SGPIO_MUX_CFG6_EXT_CLK_ENABLE_Msk               (0x01UL << SGPIO_SGPIO_MUX_CFG6_EXT_CLK_ENABLE_Pos)       /*!< SGPIO SGPIO_MUX_CFG6: EXT_CLK_ENABLE Mask */
#define SGPIO_SGPIO_MUX_CFG6_CLK_SOURCE_PIN_MODE_Pos          1                                                         /*!< SGPIO SGPIO_MUX_CFG6: CLK_SOURCE_PIN_MODE Position */
#define SGPIO_SGPIO_MUX_CFG6_CLK_SOURCE_PIN_MODE_Msk          (0x03UL << SGPIO_SGPIO_MUX_CFG6_CLK_SOURCE_PIN_MODE_Pos)  /*!< SGPIO SGPIO_MUX_CFG6: CLK_SOURCE_PIN_MODE Mask */
#define SGPIO_SGPIO_MUX_CFG6_CLK_SOURCE_SLICE_MODE_Pos        3                                                         /*!< SGPIO SGPIO_MUX_CFG6: CLK_SOURCE_SLICE_MODE Position */
#define SGPIO_SGPIO_MUX_CFG6_CLK_SOURCE_SLICE_MODE_Msk        (0x03UL << SGPIO_SGPIO_MUX_CFG6_CLK_SOURCE_SLICE_MODE_Pos)/*!< SGPIO SGPIO_MUX_CFG6: CLK_SOURCE_SLICE_MODE Mask */
#define SGPIO_SGPIO_MUX_CFG6_QUALIFIER_MODE_Pos               5                                                         /*!< SGPIO SGPIO_MUX_CFG6: QUALIFIER_MODE Position */
#define SGPIO_SGPIO_MUX_CFG6_QUALIFIER_MODE_Msk               (0x03UL << SGPIO_SGPIO_MUX_CFG6_QUALIFIER_MODE_Pos)       /*!< SGPIO SGPIO_MUX_CFG6: QUALIFIER_MODE Mask */
#define SGPIO_SGPIO_MUX_CFG6_QUALIFIER_PIN_MODE_Pos           7                                                         /*!< SGPIO SGPIO_MUX_CFG6: QUALIFIER_PIN_MODE Position */
#define SGPIO_SGPIO_MUX_CFG6_QUALIFIER_PIN_MODE_Msk           (0x03UL << SGPIO_SGPIO_MUX_CFG6_QUALIFIER_PIN_MODE_Pos)   /*!< SGPIO SGPIO_MUX_CFG6: QUALIFIER_PIN_MODE Mask */
#define SGPIO_SGPIO_MUX_CFG6_QUALIFIER_SLICE_MODE_Pos         9                                                         /*!< SGPIO SGPIO_MUX_CFG6: QUALIFIER_SLICE_MODE Position */
#define SGPIO_SGPIO_MUX_CFG6_QUALIFIER_SLICE_MODE_Msk         (0x03UL << SGPIO_SGPIO_MUX_CFG6_QUALIFIER_SLICE_MODE_Pos) /*!< SGPIO SGPIO_MUX_CFG6: QUALIFIER_SLICE_MODE Mask */
#define SGPIO_SGPIO_MUX_CFG6_CONCAT_ENABLE_Pos                11                                                        /*!< SGPIO SGPIO_MUX_CFG6: CONCAT_ENABLE Position */
#define SGPIO_SGPIO_MUX_CFG6_CONCAT_ENABLE_Msk                (0x01UL << SGPIO_SGPIO_MUX_CFG6_CONCAT_ENABLE_Pos)        /*!< SGPIO SGPIO_MUX_CFG6: CONCAT_ENABLE Mask */
#define SGPIO_SGPIO_MUX_CFG6_CONCAT_ORDER_Pos                 12                                                        /*!< SGPIO SGPIO_MUX_CFG6: CONCAT_ORDER Position */
#define SGPIO_SGPIO_MUX_CFG6_CONCAT_ORDER_Msk                 (0x03UL << SGPIO_SGPIO_MUX_CFG6_CONCAT_ORDER_Pos)         /*!< SGPIO SGPIO_MUX_CFG6: CONCAT_ORDER Mask */

// ----------------------------------  SGPIO_SGPIO_MUX_CFG7  --------------------------------------
#define SGPIO_SGPIO_MUX_CFG7_EXT_CLK_ENABLE_Pos               0                                                         /*!< SGPIO SGPIO_MUX_CFG7: EXT_CLK_ENABLE Position */
#define SGPIO_SGPIO_MUX_CFG7_EXT_CLK_ENABLE_Msk               (0x01UL << SGPIO_SGPIO_MUX_CFG7_EXT_CLK_ENABLE_Pos)       /*!< SGPIO SGPIO_MUX_CFG7: EXT_CLK_ENABLE Mask */
#define SGPIO_SGPIO_MUX_CFG7_CLK_SOURCE_PIN_MODE_Pos          1                                                         /*!< SGPIO SGPIO_MUX_CFG7: CLK_SOURCE_PIN_MODE Position */
#define SGPIO_SGPIO_MUX_CFG7_CLK_SOURCE_PIN_MODE_Msk          (0x03UL << SGPIO_SGPIO_MUX_CFG7_CLK_SOURCE_PIN_MODE_Pos)  /*!< SGPIO SGPIO_MUX_CFG7: CLK_SOURCE_PIN_MODE Mask */
#define SGPIO_SGPIO_MUX_CFG7_CLK_SOURCE_SLICE_MODE_Pos        3                                                         /*!< SGPIO SGPIO_MUX_CFG7: CLK_SOURCE_SLICE_MODE Position */
#define SGPIO_SGPIO_MUX_CFG7_CLK_SOURCE_SLICE_MODE_Msk        (0x03UL << SGPIO_SGPIO_MUX_CFG7_CLK_SOURCE_SLICE_MODE_Pos)/*!< SGPIO SGPIO_MUX_CFG7: CLK_SOURCE_SLICE_MODE Mask */
#define SGPIO_SGPIO_MUX_CFG7_QUALIFIER_MODE_Pos               5                                                         /*!< SGPIO SGPIO_MUX_CFG7: QUALIFIER_MODE Position */
#define SGPIO_SGPIO_MUX_CFG7_QUALIFIER_MODE_Msk               (0x03UL << SGPIO_SGPIO_MUX_CFG7_QUALIFIER_MODE_Pos)       /*!< SGPIO SGPIO_MUX_CFG7: QUALIFIER_MODE Mask */
#define SGPIO_SGPIO_MUX_CFG7_QUALIFIER_PIN_MODE_Pos           7                                                         /*!< SGPIO SGPIO_MUX_CFG7: QUALIFIER_PIN_MODE Position */
#define SGPIO_SGPIO_MUX_CFG7_QUALIFIER_PIN_MODE_Msk           (0x03UL << SGPIO_SGPIO_MUX_CFG7_QUALIFIER_PIN_MODE_Pos)   /*!< SGPIO SGPIO_MUX_CFG7: QUALIFIER_PIN_MODE Mask */
#define SGPIO_SGPIO_MUX_CFG7_QUALIFIER_SLICE_MODE_Pos         9                                                         /*!< SGPIO SGPIO_MUX_CFG7: QUALIFIER_SLICE_MODE Position */
#define SGPIO_SGPIO_MUX_CFG7_QUALIFIER_SLICE_MODE_Msk         (0x03UL << SGPIO_SGPIO_MUX_CFG7_QUALIFIER_SLICE_MODE_Pos) /*!< SGPIO SGPIO_MUX_CFG7: QUALIFIER_SLICE_MODE Mask */
#define SGPIO_SGPIO_MUX_CFG7_CONCAT_ENABLE_Pos                11                                                        /*!< SGPIO SGPIO_MUX_CFG7: CONCAT_ENABLE Position */
#define SGPIO_SGPIO_MUX_CFG7_CONCAT_ENABLE_Msk                (0x01UL << SGPIO_SGPIO_MUX_CFG7_CONCAT_ENABLE_Pos)        /*!< SGPIO SGPIO_MUX_CFG7: CONCAT_ENABLE Mask */
#define SGPIO_SGPIO_MUX_CFG7_CONCAT_ORDER_Pos                 12                                                        /*!< SGPIO SGPIO_MUX_CFG7: CONCAT_ORDER Position */
#define SGPIO_SGPIO_MUX_CFG7_CONCAT_ORDER_Msk                 (0x03UL << SGPIO_SGPIO_MUX_CFG7_CONCAT_ORDER_Pos)         /*!< SGPIO SGPIO_MUX_CFG7: CONCAT_ORDER Mask */

// ----------------------------------  SGPIO_SGPIO_MUX_CFG8  --------------------------------------
#define SGPIO_SGPIO_MUX_CFG8_EXT_CLK_ENABLE_Pos               0                                                         /*!< SGPIO SGPIO_MUX_CFG8: EXT_CLK_ENABLE Position */
#define SGPIO_SGPIO_MUX_CFG8_EXT_CLK_ENABLE_Msk               (0x01UL << SGPIO_SGPIO_MUX_CFG8_EXT_CLK_ENABLE_Pos)       /*!< SGPIO SGPIO_MUX_CFG8: EXT_CLK_ENABLE Mask */
#define SGPIO_SGPIO_MUX_CFG8_CLK_SOURCE_PIN_MODE_Pos          1                                                         /*!< SGPIO SGPIO_MUX_CFG8: CLK_SOURCE_PIN_MODE Position */
#define SGPIO_SGPIO_MUX_CFG8_CLK_SOURCE_PIN_MODE_Msk          (0x03UL << SGPIO_SGPIO_MUX_CFG8_CLK_SOURCE_PIN_MODE_Pos)  /*!< SGPIO SGPIO_MUX_CFG8: CLK_SOURCE_PIN_MODE Mask */
#define SGPIO_SGPIO_MUX_CFG8_CLK_SOURCE_SLICE_MODE_Pos        3                                                         /*!< SGPIO SGPIO_MUX_CFG8: CLK_SOURCE_SLICE_MODE Position */
#define SGPIO_SGPIO_MUX_CFG8_CLK_SOURCE_SLICE_MODE_Msk        (0x03UL << SGPIO_SGPIO_MUX_CFG8_CLK_SOURCE_SLICE_MODE_Pos)/*!< SGPIO SGPIO_MUX_CFG8: CLK_SOURCE_SLICE_MODE Mask */
#define SGPIO_SGPIO_MUX_CFG8_QUALIFIER_MODE_Pos               5                                                         /*!< SGPIO SGPIO_MUX_CFG8: QUALIFIER_MODE Position */
#define SGPIO_SGPIO_MUX_CFG8_QUALIFIER_MODE_Msk               (0x03UL << SGPIO_SGPIO_MUX_CFG8_QUALIFIER_MODE_Pos)       /*!< SGPIO SGPIO_MUX_CFG8: QUALIFIER_MODE Mask */
#define SGPIO_SGPIO_MUX_CFG8_QUALIFIER_PIN_MODE_Pos           7                                                         /*!< SGPIO SGPIO_MUX_CFG8: QUALIFIER_PIN_MODE Position */
#define SGPIO_SGPIO_MUX_CFG8_QUALIFIER_PIN_MODE_Msk           (0x03UL << SGPIO_SGPIO_MUX_CFG8_QUALIFIER_PIN_MODE_Pos)   /*!< SGPIO SGPIO_MUX_CFG8: QUALIFIER_PIN_MODE Mask */
#define SGPIO_SGPIO_MUX_CFG8_QUALIFIER_SLICE_MODE_Pos         9                                                         /*!< SGPIO SGPIO_MUX_CFG8: QUALIFIER_SLICE_MODE Position */
#define SGPIO_SGPIO_MUX_CFG8_QUALIFIER_SLICE_MODE_Msk         (0x03UL << SGPIO_SGPIO_MUX_CFG8_QUALIFIER_SLICE_MODE_Pos) /*!< SGPIO SGPIO_MUX_CFG8: QUALIFIER_SLICE_MODE Mask */
#define SGPIO_SGPIO_MUX_CFG8_CONCAT_ENABLE_Pos                11                                                        /*!< SGPIO SGPIO_MUX_CFG8: CONCAT_ENABLE Position */
#define SGPIO_SGPIO_MUX_CFG8_CONCAT_ENABLE_Msk                (0x01UL << SGPIO_SGPIO_MUX_CFG8_CONCAT_ENABLE_Pos)        /*!< SGPIO SGPIO_MUX_CFG8: CONCAT_ENABLE Mask */
#define SGPIO_SGPIO_MUX_CFG8_CONCAT_ORDER_Pos                 12                                                        /*!< SGPIO SGPIO_MUX_CFG8: CONCAT_ORDER Position */
#define SGPIO_SGPIO_MUX_CFG8_CONCAT_ORDER_Msk                 (0x03UL << SGPIO_SGPIO_MUX_CFG8_CONCAT_ORDER_Pos)         /*!< SGPIO SGPIO_MUX_CFG8: CONCAT_ORDER Mask */

// ----------------------------------  SGPIO_SGPIO_MUX_CFG9  --------------------------------------
#define SGPIO_SGPIO_MUX_CFG9_EXT_CLK_ENABLE_Pos               0                                                         /*!< SGPIO SGPIO_MUX_CFG9: EXT_CLK_ENABLE Position */
#define SGPIO_SGPIO_MUX_CFG9_EXT_CLK_ENABLE_Msk               (0x01UL << SGPIO_SGPIO_MUX_CFG9_EXT_CLK_ENABLE_Pos)       /*!< SGPIO SGPIO_MUX_CFG9: EXT_CLK_ENABLE Mask */
#define SGPIO_SGPIO_MUX_CFG9_CLK_SOURCE_PIN_MODE_Pos          1                                                         /*!< SGPIO SGPIO_MUX_CFG9: CLK_SOURCE_PIN_MODE Position */
#define SGPIO_SGPIO_MUX_CFG9_CLK_SOURCE_PIN_MODE_Msk          (0x03UL << SGPIO_SGPIO_MUX_CFG9_CLK_SOURCE_PIN_MODE_Pos)  /*!< SGPIO SGPIO_MUX_CFG9: CLK_SOURCE_PIN_MODE Mask */
#define SGPIO_SGPIO_MUX_CFG9_CLK_SOURCE_SLICE_MODE_Pos        3                                                         /*!< SGPIO SGPIO_MUX_CFG9: CLK_SOURCE_SLICE_MODE Position */
#define SGPIO_SGPIO_MUX_CFG9_CLK_SOURCE_SLICE_MODE_Msk        (0x03UL << SGPIO_SGPIO_MUX_CFG9_CLK_SOURCE_SLICE_MODE_Pos)/*!< SGPIO SGPIO_MUX_CFG9: CLK_SOURCE_SLICE_MODE Mask */
#define SGPIO_SGPIO_MUX_CFG9_QUALIFIER_MODE_Pos               5                                                         /*!< SGPIO SGPIO_MUX_CFG9: QUALIFIER_MODE Position */
#define SGPIO_SGPIO_MUX_CFG9_QUALIFIER_MODE_Msk               (0x03UL << SGPIO_SGPIO_MUX_CFG9_QUALIFIER_MODE_Pos)       /*!< SGPIO SGPIO_MUX_CFG9: QUALIFIER_MODE Mask */
#define SGPIO_SGPIO_MUX_CFG9_QUALIFIER_PIN_MODE_Pos           7                                                         /*!< SGPIO SGPIO_MUX_CFG9: QUALIFIER_PIN_MODE Position */
#define SGPIO_SGPIO_MUX_CFG9_QUALIFIER_PIN_MODE_Msk           (0x03UL << SGPIO_SGPIO_MUX_CFG9_QUALIFIER_PIN_MODE_Pos)   /*!< SGPIO SGPIO_MUX_CFG9: QUALIFIER_PIN_MODE Mask */
#define SGPIO_SGPIO_MUX_CFG9_QUALIFIER_SLICE_MODE_Pos         9                                                         /*!< SGPIO SGPIO_MUX_CFG9: QUALIFIER_SLICE_MODE Position */
#define SGPIO_SGPIO_MUX_CFG9_QUALIFIER_SLICE_MODE_Msk         (0x03UL << SGPIO_SGPIO_MUX_CFG9_QUALIFIER_SLICE_MODE_Pos) /*!< SGPIO SGPIO_MUX_CFG9: QUALIFIER_SLICE_MODE Mask */
#define SGPIO_SGPIO_MUX_CFG9_CONCAT_ENABLE_Pos                11                                                        /*!< SGPIO SGPIO_MUX_CFG9: CONCAT_ENABLE Position */
#define SGPIO_SGPIO_MUX_CFG9_CONCAT_ENABLE_Msk                (0x01UL << SGPIO_SGPIO_MUX_CFG9_CONCAT_ENABLE_Pos)        /*!< SGPIO SGPIO_MUX_CFG9: CONCAT_ENABLE Mask */
#define SGPIO_SGPIO_MUX_CFG9_CONCAT_ORDER_Pos                 12                                                        /*!< SGPIO SGPIO_MUX_CFG9: CONCAT_ORDER Position */
#define SGPIO_SGPIO_MUX_CFG9_CONCAT_ORDER_Msk                 (0x03UL << SGPIO_SGPIO_MUX_CFG9_CONCAT_ORDER_Pos)         /*!< SGPIO SGPIO_MUX_CFG9: CONCAT_ORDER Mask */

// ----------------------------------  SGPIO_SGPIO_MUX_CFG10  -------------------------------------
#define SGPIO_SGPIO_MUX_CFG10_EXT_CLK_ENABLE_Pos              0                                                         /*!< SGPIO SGPIO_MUX_CFG10: EXT_CLK_ENABLE Position */
#define SGPIO_SGPIO_MUX_CFG10_EXT_CLK_ENABLE_Msk              (0x01UL << SGPIO_SGPIO_MUX_CFG10_EXT_CLK_ENABLE_Pos)      /*!< SGPIO SGPIO_MUX_CFG10: EXT_CLK_ENABLE Mask */
#define SGPIO_SGPIO_MUX_CFG10_CLK_SOURCE_PIN_MODE_Pos         1                                                         /*!< SGPIO SGPIO_MUX_CFG10: CLK_SOURCE_PIN_MODE Position */
#define SGPIO_SGPIO_MUX_CFG10_CLK_SOURCE_PIN_MODE_Msk         (0x03UL << SGPIO_SGPIO_MUX_CFG10_CLK_SOURCE_PIN_MODE_Pos) /*!< SGPIO SGPIO_MUX_CFG10: CLK_SOURCE_PIN_MODE Mask */
#define SGPIO_SGPIO_MUX_CFG10_CLK_SOURCE_SLICE_MODE_Pos       3                                                         /*!< SGPIO SGPIO_MUX_CFG10: CLK_SOURCE_SLICE_MODE Position */
#define SGPIO_SGPIO_MUX_CFG10_CLK_SOURCE_SLICE_MODE_Msk       (0x03UL << SGPIO_SGPIO_MUX_CFG10_CLK_SOURCE_SLICE_MODE_Pos)/*!< SGPIO SGPIO_MUX_CFG10: CLK_SOURCE_SLICE_MODE Mask */
#define SGPIO_SGPIO_MUX_CFG10_QUALIFIER_MODE_Pos              5                                                         /*!< SGPIO SGPIO_MUX_CFG10: QUALIFIER_MODE Position */
#define SGPIO_SGPIO_MUX_CFG10_QUALIFIER_MODE_Msk              (0x03UL << SGPIO_SGPIO_MUX_CFG10_QUALIFIER_MODE_Pos)      /*!< SGPIO SGPIO_MUX_CFG10: QUALIFIER_MODE Mask */
#define SGPIO_SGPIO_MUX_CFG10_QUALIFIER_PIN_MODE_Pos          7                                                         /*!< SGPIO SGPIO_MUX_CFG10: QUALIFIER_PIN_MODE Position */
#define SGPIO_SGPIO_MUX_CFG10_QUALIFIER_PIN_MODE_Msk          (0x03UL << SGPIO_SGPIO_MUX_CFG10_QUALIFIER_PIN_MODE_Pos)  /*!< SGPIO SGPIO_MUX_CFG10: QUALIFIER_PIN_MODE Mask */
#define SGPIO_SGPIO_MUX_CFG10_QUALIFIER_SLICE_MODE_Pos        9                                                         /*!< SGPIO SGPIO_MUX_CFG10: QUALIFIER_SLICE_MODE Position */
#define SGPIO_SGPIO_MUX_CFG10_QUALIFIER_SLICE_MODE_Msk        (0x03UL << SGPIO_SGPIO_MUX_CFG10_QUALIFIER_SLICE_MODE_Pos)/*!< SGPIO SGPIO_MUX_CFG10: QUALIFIER_SLICE_MODE Mask */
#define SGPIO_SGPIO_MUX_CFG10_CONCAT_ENABLE_Pos               11                                                        /*!< SGPIO SGPIO_MUX_CFG10: CONCAT_ENABLE Position */
#define SGPIO_SGPIO_MUX_CFG10_CONCAT_ENABLE_Msk               (0x01UL << SGPIO_SGPIO_MUX_CFG10_CONCAT_ENABLE_Pos)       /*!< SGPIO SGPIO_MUX_CFG10: CONCAT_ENABLE Mask */
#define SGPIO_SGPIO_MUX_CFG10_CONCAT_ORDER_Pos                12                                                        /*!< SGPIO SGPIO_MUX_CFG10: CONCAT_ORDER Position */
#define SGPIO_SGPIO_MUX_CFG10_CONCAT_ORDER_Msk                (0x03UL << SGPIO_SGPIO_MUX_CFG10_CONCAT_ORDER_Pos)        /*!< SGPIO SGPIO_MUX_CFG10: CONCAT_ORDER Mask */

// ----------------------------------  SGPIO_SGPIO_MUX_CFG11  -------------------------------------
#define SGPIO_SGPIO_MUX_CFG11_EXT_CLK_ENABLE_Pos              0                                                         /*!< SGPIO SGPIO_MUX_CFG11: EXT_CLK_ENABLE Position */
#define SGPIO_SGPIO_MUX_CFG11_EXT_CLK_ENABLE_Msk              (0x01UL << SGPIO_SGPIO_MUX_CFG11_EXT_CLK_ENABLE_Pos)      /*!< SGPIO SGPIO_MUX_CFG11: EXT_CLK_ENABLE Mask */
#define SGPIO_SGPIO_MUX_CFG11_CLK_SOURCE_PIN_MODE_Pos         1                                                         /*!< SGPIO SGPIO_MUX_CFG11: CLK_SOURCE_PIN_MODE Position */
#define SGPIO_SGPIO_MUX_CFG11_CLK_SOURCE_PIN_MODE_Msk         (0x03UL << SGPIO_SGPIO_MUX_CFG11_CLK_SOURCE_PIN_MODE_Pos) /*!< SGPIO SGPIO_MUX_CFG11: CLK_SOURCE_PIN_MODE Mask */
#define SGPIO_SGPIO_MUX_CFG11_CLK_SOURCE_SLICE_MODE_Pos       3                                                         /*!< SGPIO SGPIO_MUX_CFG11: CLK_SOURCE_SLICE_MODE Position */
#define SGPIO_SGPIO_MUX_CFG11_CLK_SOURCE_SLICE_MODE_Msk       (0x03UL << SGPIO_SGPIO_MUX_CFG11_CLK_SOURCE_SLICE_MODE_Pos)/*!< SGPIO SGPIO_MUX_CFG11: CLK_SOURCE_SLICE_MODE Mask */
#define SGPIO_SGPIO_MUX_CFG11_QUALIFIER_MODE_Pos              5                                                         /*!< SGPIO SGPIO_MUX_CFG11: QUALIFIER_MODE Position */
#define SGPIO_SGPIO_MUX_CFG11_QUALIFIER_MODE_Msk              (0x03UL << SGPIO_SGPIO_MUX_CFG11_QUALIFIER_MODE_Pos)      /*!< SGPIO SGPIO_MUX_CFG11: QUALIFIER_MODE Mask */
#define SGPIO_SGPIO_MUX_CFG11_QUALIFIER_PIN_MODE_Pos          7                                                         /*!< SGPIO SGPIO_MUX_CFG11: QUALIFIER_PIN_MODE Position */
#define SGPIO_SGPIO_MUX_CFG11_QUALIFIER_PIN_MODE_Msk          (0x03UL << SGPIO_SGPIO_MUX_CFG11_QUALIFIER_PIN_MODE_Pos)  /*!< SGPIO SGPIO_MUX_CFG11: QUALIFIER_PIN_MODE Mask */
#define SGPIO_SGPIO_MUX_CFG11_QUALIFIER_SLICE_MODE_Pos        9                                                         /*!< SGPIO SGPIO_MUX_CFG11: QUALIFIER_SLICE_MODE Position */
#define SGPIO_SGPIO_MUX_CFG11_QUALIFIER_SLICE_MODE_Msk        (0x03UL << SGPIO_SGPIO_MUX_CFG11_QUALIFIER_SLICE_MODE_Pos)/*!< SGPIO SGPIO_MUX_CFG11: QUALIFIER_SLICE_MODE Mask */
#define SGPIO_SGPIO_MUX_CFG11_CONCAT_ENABLE_Pos               11                                                        /*!< SGPIO SGPIO_MUX_CFG11: CONCAT_ENABLE Position */
#define SGPIO_SGPIO_MUX_CFG11_CONCAT_ENABLE_Msk               (0x01UL << SGPIO_SGPIO_MUX_CFG11_CONCAT_ENABLE_Pos)       /*!< SGPIO SGPIO_MUX_CFG11: CONCAT_ENABLE Mask */
#define SGPIO_SGPIO_MUX_CFG11_CONCAT_ORDER_Pos                12                                                        /*!< SGPIO SGPIO_MUX_CFG11: CONCAT_ORDER Position */
#define SGPIO_SGPIO_MUX_CFG11_CONCAT_ORDER_Msk                (0x03UL << SGPIO_SGPIO_MUX_CFG11_CONCAT_ORDER_Pos)        /*!< SGPIO SGPIO_MUX_CFG11: CONCAT_ORDER Mask */

// ----------------------------------  SGPIO_SGPIO_MUX_CFG12  -------------------------------------
#define SGPIO_SGPIO_MUX_CFG12_EXT_CLK_ENABLE_Pos              0                                                         /*!< SGPIO SGPIO_MUX_CFG12: EXT_CLK_ENABLE Position */
#define SGPIO_SGPIO_MUX_CFG12_EXT_CLK_ENABLE_Msk              (0x01UL << SGPIO_SGPIO_MUX_CFG12_EXT_CLK_ENABLE_Pos)      /*!< SGPIO SGPIO_MUX_CFG12: EXT_CLK_ENABLE Mask */
#define SGPIO_SGPIO_MUX_CFG12_CLK_SOURCE_PIN_MODE_Pos         1                                                         /*!< SGPIO SGPIO_MUX_CFG12: CLK_SOURCE_PIN_MODE Position */
#define SGPIO_SGPIO_MUX_CFG12_CLK_SOURCE_PIN_MODE_Msk         (0x03UL << SGPIO_SGPIO_MUX_CFG12_CLK_SOURCE_PIN_MODE_Pos) /*!< SGPIO SGPIO_MUX_CFG12: CLK_SOURCE_PIN_MODE Mask */
#define SGPIO_SGPIO_MUX_CFG12_CLK_SOURCE_SLICE_MODE_Pos       3                                                         /*!< SGPIO SGPIO_MUX_CFG12: CLK_SOURCE_SLICE_MODE Position */
#define SGPIO_SGPIO_MUX_CFG12_CLK_SOURCE_SLICE_MODE_Msk       (0x03UL << SGPIO_SGPIO_MUX_CFG12_CLK_SOURCE_SLICE_MODE_Pos)/*!< SGPIO SGPIO_MUX_CFG12: CLK_SOURCE_SLICE_MODE Mask */
#define SGPIO_SGPIO_MUX_CFG12_QUALIFIER_MODE_Pos              5                                                         /*!< SGPIO SGPIO_MUX_CFG12: QUALIFIER_MODE Position */
#define SGPIO_SGPIO_MUX_CFG12_QUALIFIER_MODE_Msk              (0x03UL << SGPIO_SGPIO_MUX_CFG12_QUALIFIER_MODE_Pos)      /*!< SGPIO SGPIO_MUX_CFG12: QUALIFIER_MODE Mask */
#define SGPIO_SGPIO_MUX_CFG12_QUALIFIER_PIN_MODE_Pos          7                                                         /*!< SGPIO SGPIO_MUX_CFG12: QUALIFIER_PIN_MODE Position */
#define SGPIO_SGPIO_MUX_CFG12_QUALIFIER_PIN_MODE_Msk          (0x03UL << SGPIO_SGPIO_MUX_CFG12_QUALIFIER_PIN_MODE_Pos)  /*!< SGPIO SGPIO_MUX_CFG12: QUALIFIER_PIN_MODE Mask */
#define SGPIO_SGPIO_MUX_CFG12_QUALIFIER_SLICE_MODE_Pos        9                                                         /*!< SGPIO SGPIO_MUX_CFG12: QUALIFIER_SLICE_MODE Position */
#define SGPIO_SGPIO_MUX_CFG12_QUALIFIER_SLICE_MODE_Msk        (0x03UL << SGPIO_SGPIO_MUX_CFG12_QUALIFIER_SLICE_MODE_Pos)/*!< SGPIO SGPIO_MUX_CFG12: QUALIFIER_SLICE_MODE Mask */
#define SGPIO_SGPIO_MUX_CFG12_CONCAT_ENABLE_Pos               11                                                        /*!< SGPIO SGPIO_MUX_CFG12: CONCAT_ENABLE Position */
#define SGPIO_SGPIO_MUX_CFG12_CONCAT_ENABLE_Msk               (0x01UL << SGPIO_SGPIO_MUX_CFG12_CONCAT_ENABLE_Pos)       /*!< SGPIO SGPIO_MUX_CFG12: CONCAT_ENABLE Mask */
#define SGPIO_SGPIO_MUX_CFG12_CONCAT_ORDER_Pos                12                                                        /*!< SGPIO SGPIO_MUX_CFG12: CONCAT_ORDER Position */
#define SGPIO_SGPIO_MUX_CFG12_CONCAT_ORDER_Msk                (0x03UL << SGPIO_SGPIO_MUX_CFG12_CONCAT_ORDER_Pos)        /*!< SGPIO SGPIO_MUX_CFG12: CONCAT_ORDER Mask */

// ----------------------------------  SGPIO_SGPIO_MUX_CFG13  -------------------------------------
#define SGPIO_SGPIO_MUX_CFG13_EXT_CLK_ENABLE_Pos              0                                                         /*!< SGPIO SGPIO_MUX_CFG13: EXT_CLK_ENABLE Position */
#define SGPIO_SGPIO_MUX_CFG13_EXT_CLK_ENABLE_Msk              (0x01UL << SGPIO_SGPIO_MUX_CFG13_EXT_CLK_ENABLE_Pos)      /*!< SGPIO SGPIO_MUX_CFG13: EXT_CLK_ENABLE Mask */
#define SGPIO_SGPIO_MUX_CFG13_CLK_SOURCE_PIN_MODE_Pos         1                                                         /*!< SGPIO SGPIO_MUX_CFG13: CLK_SOURCE_PIN_MODE Position */
#define SGPIO_SGPIO_MUX_CFG13_CLK_SOURCE_PIN_MODE_Msk         (0x03UL << SGPIO_SGPIO_MUX_CFG13_CLK_SOURCE_PIN_MODE_Pos) /*!< SGPIO SGPIO_MUX_CFG13: CLK_SOURCE_PIN_MODE Mask */
#define SGPIO_SGPIO_MUX_CFG13_CLK_SOURCE_SLICE_MODE_Pos       3                                                         /*!< SGPIO SGPIO_MUX_CFG13: CLK_SOURCE_SLICE_MODE Position */
#define SGPIO_SGPIO_MUX_CFG13_CLK_SOURCE_SLICE_MODE_Msk       (0x03UL << SGPIO_SGPIO_MUX_CFG13_CLK_SOURCE_SLICE_MODE_Pos)/*!< SGPIO SGPIO_MUX_CFG13: CLK_SOURCE_SLICE_MODE Mask */
#define SGPIO_SGPIO_MUX_CFG13_QUALIFIER_MODE_Pos              5                                                         /*!< SGPIO SGPIO_MUX_CFG13: QUALIFIER_MODE Position */
#define SGPIO_SGPIO_MUX_CFG13_QUALIFIER_MODE_Msk              (0x03UL << SGPIO_SGPIO_MUX_CFG13_QUALIFIER_MODE_Pos)      /*!< SGPIO SGPIO_MUX_CFG13: QUALIFIER_MODE Mask */
#define SGPIO_SGPIO_MUX_CFG13_QUALIFIER_PIN_MODE_Pos          7                                                         /*!< SGPIO SGPIO_MUX_CFG13: QUALIFIER_PIN_MODE Position */
#define SGPIO_SGPIO_MUX_CFG13_QUALIFIER_PIN_MODE_Msk          (0x03UL << SGPIO_SGPIO_MUX_CFG13_QUALIFIER_PIN_MODE_Pos)  /*!< SGPIO SGPIO_MUX_CFG13: QUALIFIER_PIN_MODE Mask */
#define SGPIO_SGPIO_MUX_CFG13_QUALIFIER_SLICE_MODE_Pos        9                                                         /*!< SGPIO SGPIO_MUX_CFG13: QUALIFIER_SLICE_MODE Position */
#define SGPIO_SGPIO_MUX_CFG13_QUALIFIER_SLICE_MODE_Msk        (0x03UL << SGPIO_SGPIO_MUX_CFG13_QUALIFIER_SLICE_MODE_Pos)/*!< SGPIO SGPIO_MUX_CFG13: QUALIFIER_SLICE_MODE Mask */
#define SGPIO_SGPIO_MUX_CFG13_CONCAT_ENABLE_Pos               11                                                        /*!< SGPIO SGPIO_MUX_CFG13: CONCAT_ENABLE Position */
#define SGPIO_SGPIO_MUX_CFG13_CONCAT_ENABLE_Msk               (0x01UL << SGPIO_SGPIO_MUX_CFG13_CONCAT_ENABLE_Pos)       /*!< SGPIO SGPIO_MUX_CFG13: CONCAT_ENABLE Mask */
#define SGPIO_SGPIO_MUX_CFG13_CONCAT_ORDER_Pos                12                                                        /*!< SGPIO SGPIO_MUX_CFG13: CONCAT_ORDER Position */
#define SGPIO_SGPIO_MUX_CFG13_CONCAT_ORDER_Msk                (0x03UL << SGPIO_SGPIO_MUX_CFG13_CONCAT_ORDER_Pos)        /*!< SGPIO SGPIO_MUX_CFG13: CONCAT_ORDER Mask */

// ----------------------------------  SGPIO_SGPIO_MUX_CFG14  -------------------------------------
#define SGPIO_SGPIO_MUX_CFG14_EXT_CLK_ENABLE_Pos              0                                                         /*!< SGPIO SGPIO_MUX_CFG14: EXT_CLK_ENABLE Position */
#define SGPIO_SGPIO_MUX_CFG14_EXT_CLK_ENABLE_Msk              (0x01UL << SGPIO_SGPIO_MUX_CFG14_EXT_CLK_ENABLE_Pos)      /*!< SGPIO SGPIO_MUX_CFG14: EXT_CLK_ENABLE Mask */
#define SGPIO_SGPIO_MUX_CFG14_CLK_SOURCE_PIN_MODE_Pos         1                                                         /*!< SGPIO SGPIO_MUX_CFG14: CLK_SOURCE_PIN_MODE Position */
#define SGPIO_SGPIO_MUX_CFG14_CLK_SOURCE_PIN_MODE_Msk         (0x03UL << SGPIO_SGPIO_MUX_CFG14_CLK_SOURCE_PIN_MODE_Pos) /*!< SGPIO SGPIO_MUX_CFG14: CLK_SOURCE_PIN_MODE Mask */
#define SGPIO_SGPIO_MUX_CFG14_CLK_SOURCE_SLICE_MODE_Pos       3                                                         /*!< SGPIO SGPIO_MUX_CFG14: CLK_SOURCE_SLICE_MODE Position */
#define SGPIO_SGPIO_MUX_CFG14_CLK_SOURCE_SLICE_MODE_Msk       (0x03UL << SGPIO_SGPIO_MUX_CFG14_CLK_SOURCE_SLICE_MODE_Pos)/*!< SGPIO SGPIO_MUX_CFG14: CLK_SOURCE_SLICE_MODE Mask */
#define SGPIO_SGPIO_MUX_CFG14_QUALIFIER_MODE_Pos              5                                                         /*!< SGPIO SGPIO_MUX_CFG14: QUALIFIER_MODE Position */
#define SGPIO_SGPIO_MUX_CFG14_QUALIFIER_MODE_Msk              (0x03UL << SGPIO_SGPIO_MUX_CFG14_QUALIFIER_MODE_Pos)      /*!< SGPIO SGPIO_MUX_CFG14: QUALIFIER_MODE Mask */
#define SGPIO_SGPIO_MUX_CFG14_QUALIFIER_PIN_MODE_Pos          7                                                         /*!< SGPIO SGPIO_MUX_CFG14: QUALIFIER_PIN_MODE Position */
#define SGPIO_SGPIO_MUX_CFG14_QUALIFIER_PIN_MODE_Msk          (0x03UL << SGPIO_SGPIO_MUX_CFG14_QUALIFIER_PIN_MODE_Pos)  /*!< SGPIO SGPIO_MUX_CFG14: QUALIFIER_PIN_MODE Mask */
#define SGPIO_SGPIO_MUX_CFG14_QUALIFIER_SLICE_MODE_Pos        9                                                         /*!< SGPIO SGPIO_MUX_CFG14: QUALIFIER_SLICE_MODE Position */
#define SGPIO_SGPIO_MUX_CFG14_QUALIFIER_SLICE_MODE_Msk        (0x03UL << SGPIO_SGPIO_MUX_CFG14_QUALIFIER_SLICE_MODE_Pos)/*!< SGPIO SGPIO_MUX_CFG14: QUALIFIER_SLICE_MODE Mask */
#define SGPIO_SGPIO_MUX_CFG14_CONCAT_ENABLE_Pos               11                                                        /*!< SGPIO SGPIO_MUX_CFG14: CONCAT_ENABLE Position */
#define SGPIO_SGPIO_MUX_CFG14_CONCAT_ENABLE_Msk               (0x01UL << SGPIO_SGPIO_MUX_CFG14_CONCAT_ENABLE_Pos)       /*!< SGPIO SGPIO_MUX_CFG14: CONCAT_ENABLE Mask */
#define SGPIO_SGPIO_MUX_CFG14_CONCAT_ORDER_Pos                12                                                        /*!< SGPIO SGPIO_MUX_CFG14: CONCAT_ORDER Position */
#define SGPIO_SGPIO_MUX_CFG14_CONCAT_ORDER_Msk                (0x03UL << SGPIO_SGPIO_MUX_CFG14_CONCAT_ORDER_Pos)        /*!< SGPIO SGPIO_MUX_CFG14: CONCAT_ORDER Mask */

// ----------------------------------  SGPIO_SGPIO_MUX_CFG15  -------------------------------------
#define SGPIO_SGPIO_MUX_CFG15_EXT_CLK_ENABLE_Pos              0                                                         /*!< SGPIO SGPIO_MUX_CFG15: EXT_CLK_ENABLE Position */
#define SGPIO_SGPIO_MUX_CFG15_EXT_CLK_ENABLE_Msk              (0x01UL << SGPIO_SGPIO_MUX_CFG15_EXT_CLK_ENABLE_Pos)      /*!< SGPIO SGPIO_MUX_CFG15: EXT_CLK_ENABLE Mask */
#define SGPIO_SGPIO_MUX_CFG15_CLK_SOURCE_PIN_MODE_Pos         1                                                         /*!< SGPIO SGPIO_MUX_CFG15: CLK_SOURCE_PIN_MODE Position */
#define SGPIO_SGPIO_MUX_CFG15_CLK_SOURCE_PIN_MODE_Msk         (0x03UL << SGPIO_SGPIO_MUX_CFG15_CLK_SOURCE_PIN_MODE_Pos) /*!< SGPIO SGPIO_MUX_CFG15: CLK_SOURCE_PIN_MODE Mask */
#define SGPIO_SGPIO_MUX_CFG15_CLK_SOURCE_SLICE_MODE_Pos       3                                                         /*!< SGPIO SGPIO_MUX_CFG15: CLK_SOURCE_SLICE_MODE Position */
#define SGPIO_SGPIO_MUX_CFG15_CLK_SOURCE_SLICE_MODE_Msk       (0x03UL << SGPIO_SGPIO_MUX_CFG15_CLK_SOURCE_SLICE_MODE_Pos)/*!< SGPIO SGPIO_MUX_CFG15: CLK_SOURCE_SLICE_MODE Mask */
#define SGPIO_SGPIO_MUX_CFG15_QUALIFIER_MODE_Pos              5                                                         /*!< SGPIO SGPIO_MUX_CFG15: QUALIFIER_MODE Position */
#define SGPIO_SGPIO_MUX_CFG15_QUALIFIER_MODE_Msk              (0x03UL << SGPIO_SGPIO_MUX_CFG15_QUALIFIER_MODE_Pos)      /*!< SGPIO SGPIO_MUX_CFG15: QUALIFIER_MODE Mask */
#define SGPIO_SGPIO_MUX_CFG15_QUALIFIER_PIN_MODE_Pos          7                                                         /*!< SGPIO SGPIO_MUX_CFG15: QUALIFIER_PIN_MODE Position */
#define SGPIO_SGPIO_MUX_CFG15_QUALIFIER_PIN_MODE_Msk          (0x03UL << SGPIO_SGPIO_MUX_CFG15_QUALIFIER_PIN_MODE_Pos)  /*!< SGPIO SGPIO_MUX_CFG15: QUALIFIER_PIN_MODE Mask */
#define SGPIO_SGPIO_MUX_CFG15_QUALIFIER_SLICE_MODE_Pos        9                                                         /*!< SGPIO SGPIO_MUX_CFG15: QUALIFIER_SLICE_MODE Position */
#define SGPIO_SGPIO_MUX_CFG15_QUALIFIER_SLICE_MODE_Msk        (0x03UL << SGPIO_SGPIO_MUX_CFG15_QUALIFIER_SLICE_MODE_Pos)/*!< SGPIO SGPIO_MUX_CFG15: QUALIFIER_SLICE_MODE Mask */
#define SGPIO_SGPIO_MUX_CFG15_CONCAT_ENABLE_Pos               11                                                        /*!< SGPIO SGPIO_MUX_CFG15: CONCAT_ENABLE Position */
#define SGPIO_SGPIO_MUX_CFG15_CONCAT_ENABLE_Msk               (0x01UL << SGPIO_SGPIO_MUX_CFG15_CONCAT_ENABLE_Pos)       /*!< SGPIO SGPIO_MUX_CFG15: CONCAT_ENABLE Mask */
#define SGPIO_SGPIO_MUX_CFG15_CONCAT_ORDER_Pos                12                                                        /*!< SGPIO SGPIO_MUX_CFG15: CONCAT_ORDER Position */
#define SGPIO_SGPIO_MUX_CFG15_CONCAT_ORDER_Msk                (0x03UL << SGPIO_SGPIO_MUX_CFG15_CONCAT_ORDER_Pos)        /*!< SGPIO SGPIO_MUX_CFG15: CONCAT_ORDER Mask */

// ----------------------------------  SGPIO_SLICE_MUX_CFG0  --------------------------------------
#define SGPIO_SLICE_MUX_CFG0_MATCH_MODE_Pos                   0                                                         /*!< SGPIO SLICE_MUX_CFG0: MATCH_MODE Position */
#define SGPIO_SLICE_MUX_CFG0_MATCH_MODE_Msk                   (0x01UL << SGPIO_SLICE_MUX_CFG0_MATCH_MODE_Pos)           /*!< SGPIO SLICE_MUX_CFG0: MATCH_MODE Mask */
#define SGPIO_SLICE_MUX_CFG0_CLK_CAPTURE_MODE_Pos             1                                                         /*!< SGPIO SLICE_MUX_CFG0: CLK_CAPTURE_MODE Position */
#define SGPIO_SLICE_MUX_CFG0_CLK_CAPTURE_MODE_Msk             (0x01UL << SGPIO_SLICE_MUX_CFG0_CLK_CAPTURE_MODE_Pos)     /*!< SGPIO SLICE_MUX_CFG0: CLK_CAPTURE_MODE Mask */
#define SGPIO_SLICE_MUX_CFG0_CLKGEN_MODE_Pos                  2                                                         /*!< SGPIO SLICE_MUX_CFG0: CLKGEN_MODE Position */
#define SGPIO_SLICE_MUX_CFG0_CLKGEN_MODE_Msk                  (0x01UL << SGPIO_SLICE_MUX_CFG0_CLKGEN_MODE_Pos)          /*!< SGPIO SLICE_MUX_CFG0: CLKGEN_MODE Mask */
#define SGPIO_SLICE_MUX_CFG0_INV_OUT_CLK_Pos                  3                                                         /*!< SGPIO SLICE_MUX_CFG0: INV_OUT_CLK Position */
#define SGPIO_SLICE_MUX_CFG0_INV_OUT_CLK_Msk                  (0x01UL << SGPIO_SLICE_MUX_CFG0_INV_OUT_CLK_Pos)          /*!< SGPIO SLICE_MUX_CFG0: INV_OUT_CLK Mask */
#define SGPIO_SLICE_MUX_CFG0_DATA_CAPTURE_MODE_Pos            4                                                         /*!< SGPIO SLICE_MUX_CFG0: DATA_CAPTURE_MODE Position */
#define SGPIO_SLICE_MUX_CFG0_DATA_CAPTURE_MODE_Msk            (0x03UL << SGPIO_SLICE_MUX_CFG0_DATA_CAPTURE_MODE_Pos)    /*!< SGPIO SLICE_MUX_CFG0: DATA_CAPTURE_MODE Mask */
#define SGPIO_SLICE_MUX_CFG0_PARALLEL_MODE_Pos                6                                                         /*!< SGPIO SLICE_MUX_CFG0: PARALLEL_MODE Position */
#define SGPIO_SLICE_MUX_CFG0_PARALLEL_MODE_Msk                (0x03UL << SGPIO_SLICE_MUX_CFG0_PARALLEL_MODE_Pos)        /*!< SGPIO SLICE_MUX_CFG0: PARALLEL_MODE Mask */
#define SGPIO_SLICE_MUX_CFG0_INV_QUALIFIER_Pos                8                                                         /*!< SGPIO SLICE_MUX_CFG0: INV_QUALIFIER Position */
#define SGPIO_SLICE_MUX_CFG0_INV_QUALIFIER_Msk                (0x01UL << SGPIO_SLICE_MUX_CFG0_INV_QUALIFIER_Pos)        /*!< SGPIO SLICE_MUX_CFG0: INV_QUALIFIER Mask */

// ----------------------------------  SGPIO_SLICE_MUX_CFG1  --------------------------------------
#define SGPIO_SLICE_MUX_CFG1_MATCH_MODE_Pos                   0                                                         /*!< SGPIO SLICE_MUX_CFG1: MATCH_MODE Position */
#define SGPIO_SLICE_MUX_CFG1_MATCH_MODE_Msk                   (0x01UL << SGPIO_SLICE_MUX_CFG1_MATCH_MODE_Pos)           /*!< SGPIO SLICE_MUX_CFG1: MATCH_MODE Mask */
#define SGPIO_SLICE_MUX_CFG1_CLK_CAPTURE_MODE_Pos             1                                                         /*!< SGPIO SLICE_MUX_CFG1: CLK_CAPTURE_MODE Position */
#define SGPIO_SLICE_MUX_CFG1_CLK_CAPTURE_MODE_Msk             (0x01UL << SGPIO_SLICE_MUX_CFG1_CLK_CAPTURE_MODE_Pos)     /*!< SGPIO SLICE_MUX_CFG1: CLK_CAPTURE_MODE Mask */
#define SGPIO_SLICE_MUX_CFG1_CLKGEN_MODE_Pos                  2                                                         /*!< SGPIO SLICE_MUX_CFG1: CLKGEN_MODE Position */
#define SGPIO_SLICE_MUX_CFG1_CLKGEN_MODE_Msk                  (0x01UL << SGPIO_SLICE_MUX_CFG1_CLKGEN_MODE_Pos)          /*!< SGPIO SLICE_MUX_CFG1: CLKGEN_MODE Mask */
#define SGPIO_SLICE_MUX_CFG1_INV_OUT_CLK_Pos                  3                                                         /*!< SGPIO SLICE_MUX_CFG1: INV_OUT_CLK Position */
#define SGPIO_SLICE_MUX_CFG1_INV_OUT_CLK_Msk                  (0x01UL << SGPIO_SLICE_MUX_CFG1_INV_OUT_CLK_Pos)          /*!< SGPIO SLICE_MUX_CFG1: INV_OUT_CLK Mask */
#define SGPIO_SLICE_MUX_CFG1_DATA_CAPTURE_MODE_Pos            4                                                         /*!< SGPIO SLICE_MUX_CFG1: DATA_CAPTURE_MODE Position */
#define SGPIO_SLICE_MUX_CFG1_DATA_CAPTURE_MODE_Msk            (0x03UL << SGPIO_SLICE_MUX_CFG1_DATA_CAPTURE_MODE_Pos)    /*!< SGPIO SLICE_MUX_CFG1: DATA_CAPTURE_MODE Mask */
#define SGPIO_SLICE_MUX_CFG1_PARALLEL_MODE_Pos                6                                                         /*!< SGPIO SLICE_MUX_CFG1: PARALLEL_MODE Position */
#define SGPIO_SLICE_MUX_CFG1_PARALLEL_MODE_Msk                (0x03UL << SGPIO_SLICE_MUX_CFG1_PARALLEL_MODE_Pos)        /*!< SGPIO SLICE_MUX_CFG1: PARALLEL_MODE Mask */
#define SGPIO_SLICE_MUX_CFG1_INV_QUALIFIER_Pos                8                                                         /*!< SGPIO SLICE_MUX_CFG1: INV_QUALIFIER Position */
#define SGPIO_SLICE_MUX_CFG1_INV_QUALIFIER_Msk                (0x01UL << SGPIO_SLICE_MUX_CFG1_INV_QUALIFIER_Pos)        /*!< SGPIO SLICE_MUX_CFG1: INV_QUALIFIER Mask */

// ----------------------------------  SGPIO_SLICE_MUX_CFG2  --------------------------------------
#define SGPIO_SLICE_MUX_CFG2_MATCH_MODE_Pos                   0                                                         /*!< SGPIO SLICE_MUX_CFG2: MATCH_MODE Position */
#define SGPIO_SLICE_MUX_CFG2_MATCH_MODE_Msk                   (0x01UL << SGPIO_SLICE_MUX_CFG2_MATCH_MODE_Pos)           /*!< SGPIO SLICE_MUX_CFG2: MATCH_MODE Mask */
#define SGPIO_SLICE_MUX_CFG2_CLK_CAPTURE_MODE_Pos             1                                                         /*!< SGPIO SLICE_MUX_CFG2: CLK_CAPTURE_MODE Position */
#define SGPIO_SLICE_MUX_CFG2_CLK_CAPTURE_MODE_Msk             (0x01UL << SGPIO_SLICE_MUX_CFG2_CLK_CAPTURE_MODE_Pos)     /*!< SGPIO SLICE_MUX_CFG2: CLK_CAPTURE_MODE Mask */
#define SGPIO_SLICE_MUX_CFG2_CLKGEN_MODE_Pos                  2                                                         /*!< SGPIO SLICE_MUX_CFG2: CLKGEN_MODE Position */
#define SGPIO_SLICE_MUX_CFG2_CLKGEN_MODE_Msk                  (0x01UL << SGPIO_SLICE_MUX_CFG2_CLKGEN_MODE_Pos)          /*!< SGPIO SLICE_MUX_CFG2: CLKGEN_MODE Mask */
#define SGPIO_SLICE_MUX_CFG2_INV_OUT_CLK_Pos                  3                                                         /*!< SGPIO SLICE_MUX_CFG2: INV_OUT_CLK Position */
#define SGPIO_SLICE_MUX_CFG2_INV_OUT_CLK_Msk                  (0x01UL << SGPIO_SLICE_MUX_CFG2_INV_OUT_CLK_Pos)          /*!< SGPIO SLICE_MUX_CFG2: INV_OUT_CLK Mask */
#define SGPIO_SLICE_MUX_CFG2_DATA_CAPTURE_MODE_Pos            4                                                         /*!< SGPIO SLICE_MUX_CFG2: DATA_CAPTURE_MODE Position */
#define SGPIO_SLICE_MUX_CFG2_DATA_CAPTURE_MODE_Msk            (0x03UL << SGPIO_SLICE_MUX_CFG2_DATA_CAPTURE_MODE_Pos)    /*!< SGPIO SLICE_MUX_CFG2: DATA_CAPTURE_MODE Mask */
#define SGPIO_SLICE_MUX_CFG2_PARALLEL_MODE_Pos                6                                                         /*!< SGPIO SLICE_MUX_CFG2: PARALLEL_MODE Position */
#define SGPIO_SLICE_MUX_CFG2_PARALLEL_MODE_Msk                (0x03UL << SGPIO_SLICE_MUX_CFG2_PARALLEL_MODE_Pos)        /*!< SGPIO SLICE_MUX_CFG2: PARALLEL_MODE Mask */
#define SGPIO_SLICE_MUX_CFG2_INV_QUALIFIER_Pos                8                                                         /*!< SGPIO SLICE_MUX_CFG2: INV_QUALIFIER Position */
#define SGPIO_SLICE_MUX_CFG2_INV_QUALIFIER_Msk                (0x01UL << SGPIO_SLICE_MUX_CFG2_INV_QUALIFIER_Pos)        /*!< SGPIO SLICE_MUX_CFG2: INV_QUALIFIER Mask */

// ----------------------------------  SGPIO_SLICE_MUX_CFG3  --------------------------------------
#define SGPIO_SLICE_MUX_CFG3_MATCH_MODE_Pos                   0                                                         /*!< SGPIO SLICE_MUX_CFG3: MATCH_MODE Position */
#define SGPIO_SLICE_MUX_CFG3_MATCH_MODE_Msk                   (0x01UL << SGPIO_SLICE_MUX_CFG3_MATCH_MODE_Pos)           /*!< SGPIO SLICE_MUX_CFG3: MATCH_MODE Mask */
#define SGPIO_SLICE_MUX_CFG3_CLK_CAPTURE_MODE_Pos             1                                                         /*!< SGPIO SLICE_MUX_CFG3: CLK_CAPTURE_MODE Position */
#define SGPIO_SLICE_MUX_CFG3_CLK_CAPTURE_MODE_Msk             (0x01UL << SGPIO_SLICE_MUX_CFG3_CLK_CAPTURE_MODE_Pos)     /*!< SGPIO SLICE_MUX_CFG3: CLK_CAPTURE_MODE Mask */
#define SGPIO_SLICE_MUX_CFG3_CLKGEN_MODE_Pos                  2                                                         /*!< SGPIO SLICE_MUX_CFG3: CLKGEN_MODE Position */
#define SGPIO_SLICE_MUX_CFG3_CLKGEN_MODE_Msk                  (0x01UL << SGPIO_SLICE_MUX_CFG3_CLKGEN_MODE_Pos)          /*!< SGPIO SLICE_MUX_CFG3: CLKGEN_MODE Mask */
#define SGPIO_SLICE_MUX_CFG3_INV_OUT_CLK_Pos                  3                                                         /*!< SGPIO SLICE_MUX_CFG3: INV_OUT_CLK Position */
#define SGPIO_SLICE_MUX_CFG3_INV_OUT_CLK_Msk                  (0x01UL << SGPIO_SLICE_MUX_CFG3_INV_OUT_CLK_Pos)          /*!< SGPIO SLICE_MUX_CFG3: INV_OUT_CLK Mask */
#define SGPIO_SLICE_MUX_CFG3_DATA_CAPTURE_MODE_Pos            4                                                         /*!< SGPIO SLICE_MUX_CFG3: DATA_CAPTURE_MODE Position */
#define SGPIO_SLICE_MUX_CFG3_DATA_CAPTURE_MODE_Msk            (0x03UL << SGPIO_SLICE_MUX_CFG3_DATA_CAPTURE_MODE_Pos)    /*!< SGPIO SLICE_MUX_CFG3: DATA_CAPTURE_MODE Mask */
#define SGPIO_SLICE_MUX_CFG3_PARALLEL_MODE_Pos                6                                                         /*!< SGPIO SLICE_MUX_CFG3: PARALLEL_MODE Position */
#define SGPIO_SLICE_MUX_CFG3_PARALLEL_MODE_Msk                (0x03UL << SGPIO_SLICE_MUX_CFG3_PARALLEL_MODE_Pos)        /*!< SGPIO SLICE_MUX_CFG3: PARALLEL_MODE Mask */
#define SGPIO_SLICE_MUX_CFG3_INV_QUALIFIER_Pos                8                                                         /*!< SGPIO SLICE_MUX_CFG3: INV_QUALIFIER Position */
#define SGPIO_SLICE_MUX_CFG3_INV_QUALIFIER_Msk                (0x01UL << SGPIO_SLICE_MUX_CFG3_INV_QUALIFIER_Pos)        /*!< SGPIO SLICE_MUX_CFG3: INV_QUALIFIER Mask */

// ----------------------------------  SGPIO_SLICE_MUX_CFG4  --------------------------------------
#define SGPIO_SLICE_MUX_CFG4_MATCH_MODE_Pos                   0                                                         /*!< SGPIO SLICE_MUX_CFG4: MATCH_MODE Position */
#define SGPIO_SLICE_MUX_CFG4_MATCH_MODE_Msk                   (0x01UL << SGPIO_SLICE_MUX_CFG4_MATCH_MODE_Pos)           /*!< SGPIO SLICE_MUX_CFG4: MATCH_MODE Mask */
#define SGPIO_SLICE_MUX_CFG4_CLK_CAPTURE_MODE_Pos             1                                                         /*!< SGPIO SLICE_MUX_CFG4: CLK_CAPTURE_MODE Position */
#define SGPIO_SLICE_MUX_CFG4_CLK_CAPTURE_MODE_Msk             (0x01UL << SGPIO_SLICE_MUX_CFG4_CLK_CAPTURE_MODE_Pos)     /*!< SGPIO SLICE_MUX_CFG4: CLK_CAPTURE_MODE Mask */
#define SGPIO_SLICE_MUX_CFG4_CLKGEN_MODE_Pos                  2                                                         /*!< SGPIO SLICE_MUX_CFG4: CLKGEN_MODE Position */
#define SGPIO_SLICE_MUX_CFG4_CLKGEN_MODE_Msk                  (0x01UL << SGPIO_SLICE_MUX_CFG4_CLKGEN_MODE_Pos)          /*!< SGPIO SLICE_MUX_CFG4: CLKGEN_MODE Mask */
#define SGPIO_SLICE_MUX_CFG4_INV_OUT_CLK_Pos                  3                                                         /*!< SGPIO SLICE_MUX_CFG4: INV_OUT_CLK Position */
#define SGPIO_SLICE_MUX_CFG4_INV_OUT_CLK_Msk                  (0x01UL << SGPIO_SLICE_MUX_CFG4_INV_OUT_CLK_Pos)          /*!< SGPIO SLICE_MUX_CFG4: INV_OUT_CLK Mask */
#define SGPIO_SLICE_MUX_CFG4_DATA_CAPTURE_MODE_Pos            4                                                         /*!< SGPIO SLICE_MUX_CFG4: DATA_CAPTURE_MODE Position */
#define SGPIO_SLICE_MUX_CFG4_DATA_CAPTURE_MODE_Msk            (0x03UL << SGPIO_SLICE_MUX_CFG4_DATA_CAPTURE_MODE_Pos)    /*!< SGPIO SLICE_MUX_CFG4: DATA_CAPTURE_MODE Mask */
#define SGPIO_SLICE_MUX_CFG4_PARALLEL_MODE_Pos                6                                                         /*!< SGPIO SLICE_MUX_CFG4: PARALLEL_MODE Position */
#define SGPIO_SLICE_MUX_CFG4_PARALLEL_MODE_Msk                (0x03UL << SGPIO_SLICE_MUX_CFG4_PARALLEL_MODE_Pos)        /*!< SGPIO SLICE_MUX_CFG4: PARALLEL_MODE Mask */
#define SGPIO_SLICE_MUX_CFG4_INV_QUALIFIER_Pos                8                                                         /*!< SGPIO SLICE_MUX_CFG4: INV_QUALIFIER Position */
#define SGPIO_SLICE_MUX_CFG4_INV_QUALIFIER_Msk                (0x01UL << SGPIO_SLICE_MUX_CFG4_INV_QUALIFIER_Pos)        /*!< SGPIO SLICE_MUX_CFG4: INV_QUALIFIER Mask */

// ----------------------------------  SGPIO_SLICE_MUX_CFG5  --------------------------------------
#define SGPIO_SLICE_MUX_CFG5_MATCH_MODE_Pos                   0                                                         /*!< SGPIO SLICE_MUX_CFG5: MATCH_MODE Position */
#define SGPIO_SLICE_MUX_CFG5_MATCH_MODE_Msk                   (0x01UL << SGPIO_SLICE_MUX_CFG5_MATCH_MODE_Pos)           /*!< SGPIO SLICE_MUX_CFG5: MATCH_MODE Mask */
#define SGPIO_SLICE_MUX_CFG5_CLK_CAPTURE_MODE_Pos             1                                                         /*!< SGPIO SLICE_MUX_CFG5: CLK_CAPTURE_MODE Position */
#define SGPIO_SLICE_MUX_CFG5_CLK_CAPTURE_MODE_Msk             (0x01UL << SGPIO_SLICE_MUX_CFG5_CLK_CAPTURE_MODE_Pos)     /*!< SGPIO SLICE_MUX_CFG5: CLK_CAPTURE_MODE Mask */
#define SGPIO_SLICE_MUX_CFG5_CLKGEN_MODE_Pos                  2                                                         /*!< SGPIO SLICE_MUX_CFG5: CLKGEN_MODE Position */
#define SGPIO_SLICE_MUX_CFG5_CLKGEN_MODE_Msk                  (0x01UL << SGPIO_SLICE_MUX_CFG5_CLKGEN_MODE_Pos)          /*!< SGPIO SLICE_MUX_CFG5: CLKGEN_MODE Mask */
#define SGPIO_SLICE_MUX_CFG5_INV_OUT_CLK_Pos                  3                                                         /*!< SGPIO SLICE_MUX_CFG5: INV_OUT_CLK Position */
#define SGPIO_SLICE_MUX_CFG5_INV_OUT_CLK_Msk                  (0x01UL << SGPIO_SLICE_MUX_CFG5_INV_OUT_CLK_Pos)          /*!< SGPIO SLICE_MUX_CFG5: INV_OUT_CLK Mask */
#define SGPIO_SLICE_MUX_CFG5_DATA_CAPTURE_MODE_Pos            4                                                         /*!< SGPIO SLICE_MUX_CFG5: DATA_CAPTURE_MODE Position */
#define SGPIO_SLICE_MUX_CFG5_DATA_CAPTURE_MODE_Msk            (0x03UL << SGPIO_SLICE_MUX_CFG5_DATA_CAPTURE_MODE_Pos)    /*!< SGPIO SLICE_MUX_CFG5: DATA_CAPTURE_MODE Mask */
#define SGPIO_SLICE_MUX_CFG5_PARALLEL_MODE_Pos                6                                                         /*!< SGPIO SLICE_MUX_CFG5: PARALLEL_MODE Position */
#define SGPIO_SLICE_MUX_CFG5_PARALLEL_MODE_Msk                (0x03UL << SGPIO_SLICE_MUX_CFG5_PARALLEL_MODE_Pos)        /*!< SGPIO SLICE_MUX_CFG5: PARALLEL_MODE Mask */
#define SGPIO_SLICE_MUX_CFG5_INV_QUALIFIER_Pos                8                                                         /*!< SGPIO SLICE_MUX_CFG5: INV_QUALIFIER Position */
#define SGPIO_SLICE_MUX_CFG5_INV_QUALIFIER_Msk                (0x01UL << SGPIO_SLICE_MUX_CFG5_INV_QUALIFIER_Pos)        /*!< SGPIO SLICE_MUX_CFG5: INV_QUALIFIER Mask */

// ----------------------------------  SGPIO_SLICE_MUX_CFG6  --------------------------------------
#define SGPIO_SLICE_MUX_CFG6_MATCH_MODE_Pos                   0                                                         /*!< SGPIO SLICE_MUX_CFG6: MATCH_MODE Position */
#define SGPIO_SLICE_MUX_CFG6_MATCH_MODE_Msk                   (0x01UL << SGPIO_SLICE_MUX_CFG6_MATCH_MODE_Pos)           /*!< SGPIO SLICE_MUX_CFG6: MATCH_MODE Mask */
#define SGPIO_SLICE_MUX_CFG6_CLK_CAPTURE_MODE_Pos             1                                                         /*!< SGPIO SLICE_MUX_CFG6: CLK_CAPTURE_MODE Position */
#define SGPIO_SLICE_MUX_CFG6_CLK_CAPTURE_MODE_Msk             (0x01UL << SGPIO_SLICE_MUX_CFG6_CLK_CAPTURE_MODE_Pos)     /*!< SGPIO SLICE_MUX_CFG6: CLK_CAPTURE_MODE Mask */
#define SGPIO_SLICE_MUX_CFG6_CLKGEN_MODE_Pos                  2                                                         /*!< SGPIO SLICE_MUX_CFG6: CLKGEN_MODE Position */
#define SGPIO_SLICE_MUX_CFG6_CLKGEN_MODE_Msk                  (0x01UL << SGPIO_SLICE_MUX_CFG6_CLKGEN_MODE_Pos)          /*!< SGPIO SLICE_MUX_CFG6: CLKGEN_MODE Mask */
#define SGPIO_SLICE_MUX_CFG6_INV_OUT_CLK_Pos                  3                                                         /*!< SGPIO SLICE_MUX_CFG6: INV_OUT_CLK Position */
#define SGPIO_SLICE_MUX_CFG6_INV_OUT_CLK_Msk                  (0x01UL << SGPIO_SLICE_MUX_CFG6_INV_OUT_CLK_Pos)          /*!< SGPIO SLICE_MUX_CFG6: INV_OUT_CLK Mask */
#define SGPIO_SLICE_MUX_CFG6_DATA_CAPTURE_MODE_Pos            4                                                         /*!< SGPIO SLICE_MUX_CFG6: DATA_CAPTURE_MODE Position */
#define SGPIO_SLICE_MUX_CFG6_DATA_CAPTURE_MODE_Msk            (0x03UL << SGPIO_SLICE_MUX_CFG6_DATA_CAPTURE_MODE_Pos)    /*!< SGPIO SLICE_MUX_CFG6: DATA_CAPTURE_MODE Mask */
#define SGPIO_SLICE_MUX_CFG6_PARALLEL_MODE_Pos                6                                                         /*!< SGPIO SLICE_MUX_CFG6: PARALLEL_MODE Position */
#define SGPIO_SLICE_MUX_CFG6_PARALLEL_MODE_Msk                (0x03UL << SGPIO_SLICE_MUX_CFG6_PARALLEL_MODE_Pos)        /*!< SGPIO SLICE_MUX_CFG6: PARALLEL_MODE Mask */
#define SGPIO_SLICE_MUX_CFG6_INV_QUALIFIER_Pos                8                                                         /*!< SGPIO SLICE_MUX_CFG6: INV_QUALIFIER Position */
#define SGPIO_SLICE_MUX_CFG6_INV_QUALIFIER_Msk                (0x01UL << SGPIO_SLICE_MUX_CFG6_INV_QUALIFIER_Pos)        /*!< SGPIO SLICE_MUX_CFG6: INV_QUALIFIER Mask */

// ----------------------------------  SGPIO_SLICE_MUX_CFG7  --------------------------------------
#define SGPIO_SLICE_MUX_CFG7_MATCH_MODE_Pos                   0                                                         /*!< SGPIO SLICE_MUX_CFG7: MATCH_MODE Position */
#define SGPIO_SLICE_MUX_CFG7_MATCH_MODE_Msk                   (0x01UL << SGPIO_SLICE_MUX_CFG7_MATCH_MODE_Pos)           /*!< SGPIO SLICE_MUX_CFG7: MATCH_MODE Mask */
#define SGPIO_SLICE_MUX_CFG7_CLK_CAPTURE_MODE_Pos             1                                                         /*!< SGPIO SLICE_MUX_CFG7: CLK_CAPTURE_MODE Position */
#define SGPIO_SLICE_MUX_CFG7_CLK_CAPTURE_MODE_Msk             (0x01UL << SGPIO_SLICE_MUX_CFG7_CLK_CAPTURE_MODE_Pos)     /*!< SGPIO SLICE_MUX_CFG7: CLK_CAPTURE_MODE Mask */
#define SGPIO_SLICE_MUX_CFG7_CLKGEN_MODE_Pos                  2                                                         /*!< SGPIO SLICE_MUX_CFG7: CLKGEN_MODE Position */
#define SGPIO_SLICE_MUX_CFG7_CLKGEN_MODE_Msk                  (0x01UL << SGPIO_SLICE_MUX_CFG7_CLKGEN_MODE_Pos)          /*!< SGPIO SLICE_MUX_CFG7: CLKGEN_MODE Mask */
#define SGPIO_SLICE_MUX_CFG7_INV_OUT_CLK_Pos                  3                                                         /*!< SGPIO SLICE_MUX_CFG7: INV_OUT_CLK Position */
#define SGPIO_SLICE_MUX_CFG7_INV_OUT_CLK_Msk                  (0x01UL << SGPIO_SLICE_MUX_CFG7_INV_OUT_CLK_Pos)          /*!< SGPIO SLICE_MUX_CFG7: INV_OUT_CLK Mask */
#define SGPIO_SLICE_MUX_CFG7_DATA_CAPTURE_MODE_Pos            4                                                         /*!< SGPIO SLICE_MUX_CFG7: DATA_CAPTURE_MODE Position */
#define SGPIO_SLICE_MUX_CFG7_DATA_CAPTURE_MODE_Msk            (0x03UL << SGPIO_SLICE_MUX_CFG7_DATA_CAPTURE_MODE_Pos)    /*!< SGPIO SLICE_MUX_CFG7: DATA_CAPTURE_MODE Mask */
#define SGPIO_SLICE_MUX_CFG7_PARALLEL_MODE_Pos                6                                                         /*!< SGPIO SLICE_MUX_CFG7: PARALLEL_MODE Position */
#define SGPIO_SLICE_MUX_CFG7_PARALLEL_MODE_Msk                (0x03UL << SGPIO_SLICE_MUX_CFG7_PARALLEL_MODE_Pos)        /*!< SGPIO SLICE_MUX_CFG7: PARALLEL_MODE Mask */
#define SGPIO_SLICE_MUX_CFG7_INV_QUALIFIER_Pos                8                                                         /*!< SGPIO SLICE_MUX_CFG7: INV_QUALIFIER Position */
#define SGPIO_SLICE_MUX_CFG7_INV_QUALIFIER_Msk                (0x01UL << SGPIO_SLICE_MUX_CFG7_INV_QUALIFIER_Pos)        /*!< SGPIO SLICE_MUX_CFG7: INV_QUALIFIER Mask */

// ----------------------------------  SGPIO_SLICE_MUX_CFG8  --------------------------------------
#define SGPIO_SLICE_MUX_CFG8_MATCH_MODE_Pos                   0                                                         /*!< SGPIO SLICE_MUX_CFG8: MATCH_MODE Position */
#define SGPIO_SLICE_MUX_CFG8_MATCH_MODE_Msk                   (0x01UL << SGPIO_SLICE_MUX_CFG8_MATCH_MODE_Pos)           /*!< SGPIO SLICE_MUX_CFG8: MATCH_MODE Mask */
#define SGPIO_SLICE_MUX_CFG8_CLK_CAPTURE_MODE_Pos             1                                                         /*!< SGPIO SLICE_MUX_CFG8: CLK_CAPTURE_MODE Position */
#define SGPIO_SLICE_MUX_CFG8_CLK_CAPTURE_MODE_Msk             (0x01UL << SGPIO_SLICE_MUX_CFG8_CLK_CAPTURE_MODE_Pos)     /*!< SGPIO SLICE_MUX_CFG8: CLK_CAPTURE_MODE Mask */
#define SGPIO_SLICE_MUX_CFG8_CLKGEN_MODE_Pos                  2                                                         /*!< SGPIO SLICE_MUX_CFG8: CLKGEN_MODE Position */
#define SGPIO_SLICE_MUX_CFG8_CLKGEN_MODE_Msk                  (0x01UL << SGPIO_SLICE_MUX_CFG8_CLKGEN_MODE_Pos)          /*!< SGPIO SLICE_MUX_CFG8: CLKGEN_MODE Mask */
#define SGPIO_SLICE_MUX_CFG8_INV_OUT_CLK_Pos                  3                                                         /*!< SGPIO SLICE_MUX_CFG8: INV_OUT_CLK Position */
#define SGPIO_SLICE_MUX_CFG8_INV_OUT_CLK_Msk                  (0x01UL << SGPIO_SLICE_MUX_CFG8_INV_OUT_CLK_Pos)          /*!< SGPIO SLICE_MUX_CFG8: INV_OUT_CLK Mask */
#define SGPIO_SLICE_MUX_CFG8_DATA_CAPTURE_MODE_Pos            4                                                         /*!< SGPIO SLICE_MUX_CFG8: DATA_CAPTURE_MODE Position */
#define SGPIO_SLICE_MUX_CFG8_DATA_CAPTURE_MODE_Msk            (0x03UL << SGPIO_SLICE_MUX_CFG8_DATA_CAPTURE_MODE_Pos)    /*!< SGPIO SLICE_MUX_CFG8: DATA_CAPTURE_MODE Mask */
#define SGPIO_SLICE_MUX_CFG8_PARALLEL_MODE_Pos                6                                                         /*!< SGPIO SLICE_MUX_CFG8: PARALLEL_MODE Position */
#define SGPIO_SLICE_MUX_CFG8_PARALLEL_MODE_Msk                (0x03UL << SGPIO_SLICE_MUX_CFG8_PARALLEL_MODE_Pos)        /*!< SGPIO SLICE_MUX_CFG8: PARALLEL_MODE Mask */
#define SGPIO_SLICE_MUX_CFG8_INV_QUALIFIER_Pos                8                                                         /*!< SGPIO SLICE_MUX_CFG8: INV_QUALIFIER Position */
#define SGPIO_SLICE_MUX_CFG8_INV_QUALIFIER_Msk                (0x01UL << SGPIO_SLICE_MUX_CFG8_INV_QUALIFIER_Pos)        /*!< SGPIO SLICE_MUX_CFG8: INV_QUALIFIER Mask */

// ----------------------------------  SGPIO_SLICE_MUX_CFG9  --------------------------------------
#define SGPIO_SLICE_MUX_CFG9_MATCH_MODE_Pos                   0                                                         /*!< SGPIO SLICE_MUX_CFG9: MATCH_MODE Position */
#define SGPIO_SLICE_MUX_CFG9_MATCH_MODE_Msk                   (0x01UL << SGPIO_SLICE_MUX_CFG9_MATCH_MODE_Pos)           /*!< SGPIO SLICE_MUX_CFG9: MATCH_MODE Mask */
#define SGPIO_SLICE_MUX_CFG9_CLK_CAPTURE_MODE_Pos             1                                                         /*!< SGPIO SLICE_MUX_CFG9: CLK_CAPTURE_MODE Position */
#define SGPIO_SLICE_MUX_CFG9_CLK_CAPTURE_MODE_Msk             (0x01UL << SGPIO_SLICE_MUX_CFG9_CLK_CAPTURE_MODE_Pos)     /*!< SGPIO SLICE_MUX_CFG9: CLK_CAPTURE_MODE Mask */
#define SGPIO_SLICE_MUX_CFG9_CLKGEN_MODE_Pos                  2                                                         /*!< SGPIO SLICE_MUX_CFG9: CLKGEN_MODE Position */
#define SGPIO_SLICE_MUX_CFG9_CLKGEN_MODE_Msk                  (0x01UL << SGPIO_SLICE_MUX_CFG9_CLKGEN_MODE_Pos)          /*!< SGPIO SLICE_MUX_CFG9: CLKGEN_MODE Mask */
#define SGPIO_SLICE_MUX_CFG9_INV_OUT_CLK_Pos                  3                                                         /*!< SGPIO SLICE_MUX_CFG9: INV_OUT_CLK Position */
#define SGPIO_SLICE_MUX_CFG9_INV_OUT_CLK_Msk                  (0x01UL << SGPIO_SLICE_MUX_CFG9_INV_OUT_CLK_Pos)          /*!< SGPIO SLICE_MUX_CFG9: INV_OUT_CLK Mask */
#define SGPIO_SLICE_MUX_CFG9_DATA_CAPTURE_MODE_Pos            4                                                         /*!< SGPIO SLICE_MUX_CFG9: DATA_CAPTURE_MODE Position */
#define SGPIO_SLICE_MUX_CFG9_DATA_CAPTURE_MODE_Msk            (0x03UL << SGPIO_SLICE_MUX_CFG9_DATA_CAPTURE_MODE_Pos)    /*!< SGPIO SLICE_MUX_CFG9: DATA_CAPTURE_MODE Mask */
#define SGPIO_SLICE_MUX_CFG9_PARALLEL_MODE_Pos                6                                                         /*!< SGPIO SLICE_MUX_CFG9: PARALLEL_MODE Position */
#define SGPIO_SLICE_MUX_CFG9_PARALLEL_MODE_Msk                (0x03UL << SGPIO_SLICE_MUX_CFG9_PARALLEL_MODE_Pos)        /*!< SGPIO SLICE_MUX_CFG9: PARALLEL_MODE Mask */
#define SGPIO_SLICE_MUX_CFG9_INV_QUALIFIER_Pos                8                                                         /*!< SGPIO SLICE_MUX_CFG9: INV_QUALIFIER Position */
#define SGPIO_SLICE_MUX_CFG9_INV_QUALIFIER_Msk                (0x01UL << SGPIO_SLICE_MUX_CFG9_INV_QUALIFIER_Pos)        /*!< SGPIO SLICE_MUX_CFG9: INV_QUALIFIER Mask */

// ----------------------------------  SGPIO_SLICE_MUX_CFG10  -------------------------------------
#define SGPIO_SLICE_MUX_CFG10_MATCH_MODE_Pos                  0                                                         /*!< SGPIO SLICE_MUX_CFG10: MATCH_MODE Position */
#define SGPIO_SLICE_MUX_CFG10_MATCH_MODE_Msk                  (0x01UL << SGPIO_SLICE_MUX_CFG10_MATCH_MODE_Pos)          /*!< SGPIO SLICE_MUX_CFG10: MATCH_MODE Mask */
#define SGPIO_SLICE_MUX_CFG10_CLK_CAPTURE_MODE_Pos            1                                                         /*!< SGPIO SLICE_MUX_CFG10: CLK_CAPTURE_MODE Position */
#define SGPIO_SLICE_MUX_CFG10_CLK_CAPTURE_MODE_Msk            (0x01UL << SGPIO_SLICE_MUX_CFG10_CLK_CAPTURE_MODE_Pos)    /*!< SGPIO SLICE_MUX_CFG10: CLK_CAPTURE_MODE Mask */
#define SGPIO_SLICE_MUX_CFG10_CLKGEN_MODE_Pos                 2                                                         /*!< SGPIO SLICE_MUX_CFG10: CLKGEN_MODE Position */
#define SGPIO_SLICE_MUX_CFG10_CLKGEN_MODE_Msk                 (0x01UL << SGPIO_SLICE_MUX_CFG10_CLKGEN_MODE_Pos)         /*!< SGPIO SLICE_MUX_CFG10: CLKGEN_MODE Mask */
#define SGPIO_SLICE_MUX_CFG10_INV_OUT_CLK_Pos                 3                                                         /*!< SGPIO SLICE_MUX_CFG10: INV_OUT_CLK Position */
#define SGPIO_SLICE_MUX_CFG10_INV_OUT_CLK_Msk                 (0x01UL << SGPIO_SLICE_MUX_CFG10_INV_OUT_CLK_Pos)         /*!< SGPIO SLICE_MUX_CFG10: INV_OUT_CLK Mask */
#define SGPIO_SLICE_MUX_CFG10_DATA_CAPTURE_MODE_Pos           4                                                         /*!< SGPIO SLICE_MUX_CFG10: DATA_CAPTURE_MODE Position */
#define SGPIO_SLICE_MUX_CFG10_DATA_CAPTURE_MODE_Msk           (0x03UL << SGPIO_SLICE_MUX_CFG10_DATA_CAPTURE_MODE_Pos)   /*!< SGPIO SLICE_MUX_CFG10: DATA_CAPTURE_MODE Mask */
#define SGPIO_SLICE_MUX_CFG10_PARALLEL_MODE_Pos               6                                                         /*!< SGPIO SLICE_MUX_CFG10: PARALLEL_MODE Position */
#define SGPIO_SLICE_MUX_CFG10_PARALLEL_MODE_Msk               (0x03UL << SGPIO_SLICE_MUX_CFG10_PARALLEL_MODE_Pos)       /*!< SGPIO SLICE_MUX_CFG10: PARALLEL_MODE Mask */
#define SGPIO_SLICE_MUX_CFG10_INV_QUALIFIER_Pos               8                                                         /*!< SGPIO SLICE_MUX_CFG10: INV_QUALIFIER Position */
#define SGPIO_SLICE_MUX_CFG10_INV_QUALIFIER_Msk               (0x01UL << SGPIO_SLICE_MUX_CFG10_INV_QUALIFIER_Pos)       /*!< SGPIO SLICE_MUX_CFG10: INV_QUALIFIER Mask */

// ----------------------------------  SGPIO_SLICE_MUX_CFG11  -------------------------------------
#define SGPIO_SLICE_MUX_CFG11_MATCH_MODE_Pos                  0                                                         /*!< SGPIO SLICE_MUX_CFG11: MATCH_MODE Position */
#define SGPIO_SLICE_MUX_CFG11_MATCH_MODE_Msk                  (0x01UL << SGPIO_SLICE_MUX_CFG11_MATCH_MODE_Pos)          /*!< SGPIO SLICE_MUX_CFG11: MATCH_MODE Mask */
#define SGPIO_SLICE_MUX_CFG11_CLK_CAPTURE_MODE_Pos            1                                                         /*!< SGPIO SLICE_MUX_CFG11: CLK_CAPTURE_MODE Position */
#define SGPIO_SLICE_MUX_CFG11_CLK_CAPTURE_MODE_Msk            (0x01UL << SGPIO_SLICE_MUX_CFG11_CLK_CAPTURE_MODE_Pos)    /*!< SGPIO SLICE_MUX_CFG11: CLK_CAPTURE_MODE Mask */
#define SGPIO_SLICE_MUX_CFG11_CLKGEN_MODE_Pos                 2                                                         /*!< SGPIO SLICE_MUX_CFG11: CLKGEN_MODE Position */
#define SGPIO_SLICE_MUX_CFG11_CLKGEN_MODE_Msk                 (0x01UL << SGPIO_SLICE_MUX_CFG11_CLKGEN_MODE_Pos)         /*!< SGPIO SLICE_MUX_CFG11: CLKGEN_MODE Mask */
#define SGPIO_SLICE_MUX_CFG11_INV_OUT_CLK_Pos                 3                                                         /*!< SGPIO SLICE_MUX_CFG11: INV_OUT_CLK Position */
#define SGPIO_SLICE_MUX_CFG11_INV_OUT_CLK_Msk                 (0x01UL << SGPIO_SLICE_MUX_CFG11_INV_OUT_CLK_Pos)         /*!< SGPIO SLICE_MUX_CFG11: INV_OUT_CLK Mask */
#define SGPIO_SLICE_MUX_CFG11_DATA_CAPTURE_MODE_Pos           4                                                         /*!< SGPIO SLICE_MUX_CFG11: DATA_CAPTURE_MODE Position */
#define SGPIO_SLICE_MUX_CFG11_DATA_CAPTURE_MODE_Msk           (0x03UL << SGPIO_SLICE_MUX_CFG11_DATA_CAPTURE_MODE_Pos)   /*!< SGPIO SLICE_MUX_CFG11: DATA_CAPTURE_MODE Mask */
#define SGPIO_SLICE_MUX_CFG11_PARALLEL_MODE_Pos               6                                                         /*!< SGPIO SLICE_MUX_CFG11: PARALLEL_MODE Position */
#define SGPIO_SLICE_MUX_CFG11_PARALLEL_MODE_Msk               (0x03UL << SGPIO_SLICE_MUX_CFG11_PARALLEL_MODE_Pos)       /*!< SGPIO SLICE_MUX_CFG11: PARALLEL_MODE Mask */
#define SGPIO_SLICE_MUX_CFG11_INV_QUALIFIER_Pos               8                                                         /*!< SGPIO SLICE_MUX_CFG11: INV_QUALIFIER Position */
#define SGPIO_SLICE_MUX_CFG11_INV_QUALIFIER_Msk               (0x01UL << SGPIO_SLICE_MUX_CFG11_INV_QUALIFIER_Pos)       /*!< SGPIO SLICE_MUX_CFG11: INV_QUALIFIER Mask */

// ----------------------------------  SGPIO_SLICE_MUX_CFG12  -------------------------------------
#define SGPIO_SLICE_MUX_CFG12_MATCH_MODE_Pos                  0                                                         /*!< SGPIO SLICE_MUX_CFG12: MATCH_MODE Position */
#define SGPIO_SLICE_MUX_CFG12_MATCH_MODE_Msk                  (0x01UL << SGPIO_SLICE_MUX_CFG12_MATCH_MODE_Pos)          /*!< SGPIO SLICE_MUX_CFG12: MATCH_MODE Mask */
#define SGPIO_SLICE_MUX_CFG12_CLK_CAPTURE_MODE_Pos            1                                                         /*!< SGPIO SLICE_MUX_CFG12: CLK_CAPTURE_MODE Position */
#define SGPIO_SLICE_MUX_CFG12_CLK_CAPTURE_MODE_Msk            (0x01UL << SGPIO_SLICE_MUX_CFG12_CLK_CAPTURE_MODE_Pos)    /*!< SGPIO SLICE_MUX_CFG12: CLK_CAPTURE_MODE Mask */
#define SGPIO_SLICE_MUX_CFG12_CLKGEN_MODE_Pos                 2                                                         /*!< SGPIO SLICE_MUX_CFG12: CLKGEN_MODE Position */
#define SGPIO_SLICE_MUX_CFG12_CLKGEN_MODE_Msk                 (0x01UL << SGPIO_SLICE_MUX_CFG12_CLKGEN_MODE_Pos)         /*!< SGPIO SLICE_MUX_CFG12: CLKGEN_MODE Mask */
#define SGPIO_SLICE_MUX_CFG12_INV_OUT_CLK_Pos                 3                                                         /*!< SGPIO SLICE_MUX_CFG12: INV_OUT_CLK Position */
#define SGPIO_SLICE_MUX_CFG12_INV_OUT_CLK_Msk                 (0x01UL << SGPIO_SLICE_MUX_CFG12_INV_OUT_CLK_Pos)         /*!< SGPIO SLICE_MUX_CFG12: INV_OUT_CLK Mask */
#define SGPIO_SLICE_MUX_CFG12_DATA_CAPTURE_MODE_Pos           4                                                         /*!< SGPIO SLICE_MUX_CFG12: DATA_CAPTURE_MODE Position */
#define SGPIO_SLICE_MUX_CFG12_DATA_CAPTURE_MODE_Msk           (0x03UL << SGPIO_SLICE_MUX_CFG12_DATA_CAPTURE_MODE_Pos)   /*!< SGPIO SLICE_MUX_CFG12: DATA_CAPTURE_MODE Mask */
#define SGPIO_SLICE_MUX_CFG12_PARALLEL_MODE_Pos               6                                                         /*!< SGPIO SLICE_MUX_CFG12: PARALLEL_MODE Position */
#define SGPIO_SLICE_MUX_CFG12_PARALLEL_MODE_Msk               (0x03UL << SGPIO_SLICE_MUX_CFG12_PARALLEL_MODE_Pos)       /*!< SGPIO SLICE_MUX_CFG12: PARALLEL_MODE Mask */
#define SGPIO_SLICE_MUX_CFG12_INV_QUALIFIER_Pos               8                                                         /*!< SGPIO SLICE_MUX_CFG12: INV_QUALIFIER Position */
#define SGPIO_SLICE_MUX_CFG12_INV_QUALIFIER_Msk               (0x01UL << SGPIO_SLICE_MUX_CFG12_INV_QUALIFIER_Pos)       /*!< SGPIO SLICE_MUX_CFG12: INV_QUALIFIER Mask */

// ----------------------------------  SGPIO_SLICE_MUX_CFG13  -------------------------------------
#define SGPIO_SLICE_MUX_CFG13_MATCH_MODE_Pos                  0                                                         /*!< SGPIO SLICE_MUX_CFG13: MATCH_MODE Position */
#define SGPIO_SLICE_MUX_CFG13_MATCH_MODE_Msk                  (0x01UL << SGPIO_SLICE_MUX_CFG13_MATCH_MODE_Pos)          /*!< SGPIO SLICE_MUX_CFG13: MATCH_MODE Mask */
#define SGPIO_SLICE_MUX_CFG13_CLK_CAPTURE_MODE_Pos            1                                                         /*!< SGPIO SLICE_MUX_CFG13: CLK_CAPTURE_MODE Position */
#define SGPIO_SLICE_MUX_CFG13_CLK_CAPTURE_MODE_Msk            (0x01UL << SGPIO_SLICE_MUX_CFG13_CLK_CAPTURE_MODE_Pos)    /*!< SGPIO SLICE_MUX_CFG13: CLK_CAPTURE_MODE Mask */
#define SGPIO_SLICE_MUX_CFG13_CLKGEN_MODE_Pos                 2                                                         /*!< SGPIO SLICE_MUX_CFG13: CLKGEN_MODE Position */
#define SGPIO_SLICE_MUX_CFG13_CLKGEN_MODE_Msk                 (0x01UL << SGPIO_SLICE_MUX_CFG13_CLKGEN_MODE_Pos)         /*!< SGPIO SLICE_MUX_CFG13: CLKGEN_MODE Mask */
#define SGPIO_SLICE_MUX_CFG13_INV_OUT_CLK_Pos                 3                                                         /*!< SGPIO SLICE_MUX_CFG13: INV_OUT_CLK Position */
#define SGPIO_SLICE_MUX_CFG13_INV_OUT_CLK_Msk                 (0x01UL << SGPIO_SLICE_MUX_CFG13_INV_OUT_CLK_Pos)         /*!< SGPIO SLICE_MUX_CFG13: INV_OUT_CLK Mask */
#define SGPIO_SLICE_MUX_CFG13_DATA_CAPTURE_MODE_Pos           4                                                         /*!< SGPIO SLICE_MUX_CFG13: DATA_CAPTURE_MODE Position */
#define SGPIO_SLICE_MUX_CFG13_DATA_CAPTURE_MODE_Msk           (0x03UL << SGPIO_SLICE_MUX_CFG13_DATA_CAPTURE_MODE_Pos)   /*!< SGPIO SLICE_MUX_CFG13: DATA_CAPTURE_MODE Mask */
#define SGPIO_SLICE_MUX_CFG13_PARALLEL_MODE_Pos               6                                                         /*!< SGPIO SLICE_MUX_CFG13: PARALLEL_MODE Position */
#define SGPIO_SLICE_MUX_CFG13_PARALLEL_MODE_Msk               (0x03UL << SGPIO_SLICE_MUX_CFG13_PARALLEL_MODE_Pos)       /*!< SGPIO SLICE_MUX_CFG13: PARALLEL_MODE Mask */
#define SGPIO_SLICE_MUX_CFG13_INV_QUALIFIER_Pos               8                                                         /*!< SGPIO SLICE_MUX_CFG13: INV_QUALIFIER Position */
#define SGPIO_SLICE_MUX_CFG13_INV_QUALIFIER_Msk               (0x01UL << SGPIO_SLICE_MUX_CFG13_INV_QUALIFIER_Pos)       /*!< SGPIO SLICE_MUX_CFG13: INV_QUALIFIER Mask */

// ----------------------------------  SGPIO_SLICE_MUX_CFG14  -------------------------------------
#define SGPIO_SLICE_MUX_CFG14_MATCH_MODE_Pos                  0                                                         /*!< SGPIO SLICE_MUX_CFG14: MATCH_MODE Position */
#define SGPIO_SLICE_MUX_CFG14_MATCH_MODE_Msk                  (0x01UL << SGPIO_SLICE_MUX_CFG14_MATCH_MODE_Pos)          /*!< SGPIO SLICE_MUX_CFG14: MATCH_MODE Mask */
#define SGPIO_SLICE_MUX_CFG14_CLK_CAPTURE_MODE_Pos            1                                                         /*!< SGPIO SLICE_MUX_CFG14: CLK_CAPTURE_MODE Position */
#define SGPIO_SLICE_MUX_CFG14_CLK_CAPTURE_MODE_Msk            (0x01UL << SGPIO_SLICE_MUX_CFG14_CLK_CAPTURE_MODE_Pos)    /*!< SGPIO SLICE_MUX_CFG14: CLK_CAPTURE_MODE Mask */
#define SGPIO_SLICE_MUX_CFG14_CLKGEN_MODE_Pos                 2                                                         /*!< SGPIO SLICE_MUX_CFG14: CLKGEN_MODE Position */
#define SGPIO_SLICE_MUX_CFG14_CLKGEN_MODE_Msk                 (0x01UL << SGPIO_SLICE_MUX_CFG14_CLKGEN_MODE_Pos)         /*!< SGPIO SLICE_MUX_CFG14: CLKGEN_MODE Mask */
#define SGPIO_SLICE_MUX_CFG14_INV_OUT_CLK_Pos                 3                                                         /*!< SGPIO SLICE_MUX_CFG14: INV_OUT_CLK Position */
#define SGPIO_SLICE_MUX_CFG14_INV_OUT_CLK_Msk                 (0x01UL << SGPIO_SLICE_MUX_CFG14_INV_OUT_CLK_Pos)         /*!< SGPIO SLICE_MUX_CFG14: INV_OUT_CLK Mask */
#define SGPIO_SLICE_MUX_CFG14_DATA_CAPTURE_MODE_Pos           4                                                         /*!< SGPIO SLICE_MUX_CFG14: DATA_CAPTURE_MODE Position */
#define SGPIO_SLICE_MUX_CFG14_DATA_CAPTURE_MODE_Msk           (0x03UL << SGPIO_SLICE_MUX_CFG14_DATA_CAPTURE_MODE_Pos)   /*!< SGPIO SLICE_MUX_CFG14: DATA_CAPTURE_MODE Mask */
#define SGPIO_SLICE_MUX_CFG14_PARALLEL_MODE_Pos               6                                                         /*!< SGPIO SLICE_MUX_CFG14: PARALLEL_MODE Position */
#define SGPIO_SLICE_MUX_CFG14_PARALLEL_MODE_Msk               (0x03UL << SGPIO_SLICE_MUX_CFG14_PARALLEL_MODE_Pos)       /*!< SGPIO SLICE_MUX_CFG14: PARALLEL_MODE Mask */
#define SGPIO_SLICE_MUX_CFG14_INV_QUALIFIER_Pos               8                                                         /*!< SGPIO SLICE_MUX_CFG14: INV_QUALIFIER Position */
#define SGPIO_SLICE_MUX_CFG14_INV_QUALIFIER_Msk               (0x01UL << SGPIO_SLICE_MUX_CFG14_INV_QUALIFIER_Pos)       /*!< SGPIO SLICE_MUX_CFG14: INV_QUALIFIER Mask */

// ----------------------------------  SGPIO_SLICE_MUX_CFG15  -------------------------------------
#define SGPIO_SLICE_MUX_CFG15_MATCH_MODE_Pos                  0                                                         /*!< SGPIO SLICE_MUX_CFG15: MATCH_MODE Position */
#define SGPIO_SLICE_MUX_CFG15_MATCH_MODE_Msk                  (0x01UL << SGPIO_SLICE_MUX_CFG15_MATCH_MODE_Pos)          /*!< SGPIO SLICE_MUX_CFG15: MATCH_MODE Mask */
#define SGPIO_SLICE_MUX_CFG15_CLK_CAPTURE_MODE_Pos            1                                                         /*!< SGPIO SLICE_MUX_CFG15: CLK_CAPTURE_MODE Position */
#define SGPIO_SLICE_MUX_CFG15_CLK_CAPTURE_MODE_Msk            (0x01UL << SGPIO_SLICE_MUX_CFG15_CLK_CAPTURE_MODE_Pos)    /*!< SGPIO SLICE_MUX_CFG15: CLK_CAPTURE_MODE Mask */
#define SGPIO_SLICE_MUX_CFG15_CLKGEN_MODE_Pos                 2                                                         /*!< SGPIO SLICE_MUX_CFG15: CLKGEN_MODE Position */
#define SGPIO_SLICE_MUX_CFG15_CLKGEN_MODE_Msk                 (0x01UL << SGPIO_SLICE_MUX_CFG15_CLKGEN_MODE_Pos)         /*!< SGPIO SLICE_MUX_CFG15: CLKGEN_MODE Mask */
#define SGPIO_SLICE_MUX_CFG15_INV_OUT_CLK_Pos                 3                                                         /*!< SGPIO SLICE_MUX_CFG15: INV_OUT_CLK Position */
#define SGPIO_SLICE_MUX_CFG15_INV_OUT_CLK_Msk                 (0x01UL << SGPIO_SLICE_MUX_CFG15_INV_OUT_CLK_Pos)         /*!< SGPIO SLICE_MUX_CFG15: INV_OUT_CLK Mask */
#define SGPIO_SLICE_MUX_CFG15_DATA_CAPTURE_MODE_Pos           4                                                         /*!< SGPIO SLICE_MUX_CFG15: DATA_CAPTURE_MODE Position */
#define SGPIO_SLICE_MUX_CFG15_DATA_CAPTURE_MODE_Msk           (0x03UL << SGPIO_SLICE_MUX_CFG15_DATA_CAPTURE_MODE_Pos)   /*!< SGPIO SLICE_MUX_CFG15: DATA_CAPTURE_MODE Mask */
#define SGPIO_SLICE_MUX_CFG15_PARALLEL_MODE_Pos               6                                                         /*!< SGPIO SLICE_MUX_CFG15: PARALLEL_MODE Position */
#define SGPIO_SLICE_MUX_CFG15_PARALLEL_MODE_Msk               (0x03UL << SGPIO_SLICE_MUX_CFG15_PARALLEL_MODE_Pos)       /*!< SGPIO SLICE_MUX_CFG15: PARALLEL_MODE Mask */
#define SGPIO_SLICE_MUX_CFG15_INV_QUALIFIER_Pos               8                                                         /*!< SGPIO SLICE_MUX_CFG15: INV_QUALIFIER Position */
#define SGPIO_SLICE_MUX_CFG15_INV_QUALIFIER_Msk               (0x01UL << SGPIO_SLICE_MUX_CFG15_INV_QUALIFIER_Pos)       /*!< SGPIO SLICE_MUX_CFG15: INV_QUALIFIER Mask */

// ---------------------------------------  SGPIO_REG0  -------------------------------------------
#define SGPIO_REG0_REG_Pos                                    0                                                         /*!< SGPIO REG0: REG Position            */
#define SGPIO_REG0_REG_Msk                                    (0xffffffffUL << SGPIO_REG0_REG_Pos)                      /*!< SGPIO REG0: REG Mask                */

// ---------------------------------------  SGPIO_REG1  -------------------------------------------
#define SGPIO_REG1_REG_Pos                                    0                                                         /*!< SGPIO REG1: REG Position            */
#define SGPIO_REG1_REG_Msk                                    (0xffffffffUL << SGPIO_REG1_REG_Pos)                      /*!< SGPIO REG1: REG Mask                */

// ---------------------------------------  SGPIO_REG2  -------------------------------------------
#define SGPIO_REG2_REG_Pos                                    0                                                         /*!< SGPIO REG2: REG Position            */
#define SGPIO_REG2_REG_Msk                                    (0xffffffffUL << SGPIO_REG2_REG_Pos)                      /*!< SGPIO REG2: REG Mask                */

// ---------------------------------------  SGPIO_REG3  -------------------------------------------
#define SGPIO_REG3_REG_Pos                                    0                                                         /*!< SGPIO REG3: REG Position            */
#define SGPIO_REG3_REG_Msk                                    (0xffffffffUL << SGPIO_REG3_REG_Pos)                      /*!< SGPIO REG3: REG Mask                */

// ---------------------------------------  SGPIO_REG4  -------------------------------------------
#define SGPIO_REG4_REG_Pos                                    0                                                         /*!< SGPIO REG4: REG Position            */
#define SGPIO_REG4_REG_Msk                                    (0xffffffffUL << SGPIO_REG4_REG_Pos)                      /*!< SGPIO REG4: REG Mask                */

// ---------------------------------------  SGPIO_REG5  -------------------------------------------
#define SGPIO_REG5_REG_Pos                                    0                                                         /*!< SGPIO REG5: REG Position            */
#define SGPIO_REG5_REG_Msk                                    (0xffffffffUL << SGPIO_REG5_REG_Pos)                      /*!< SGPIO REG5: REG Mask                */

// ---------------------------------------  SGPIO_REG6  -------------------------------------------
#define SGPIO_REG6_REG_Pos                                    0                                                         /*!< SGPIO REG6: REG Position            */
#define SGPIO_REG6_REG_Msk                                    (0xffffffffUL << SGPIO_REG6_REG_Pos)                      /*!< SGPIO REG6: REG Mask                */

// ---------------------------------------  SGPIO_REG7  -------------------------------------------
#define SGPIO_REG7_REG_Pos                                    0                                                         /*!< SGPIO REG7: REG Position            */
#define SGPIO_REG7_REG_Msk                                    (0xffffffffUL << SGPIO_REG7_REG_Pos)                      /*!< SGPIO REG7: REG Mask                */

// ---------------------------------------  SGPIO_REG8  -------------------------------------------
#define SGPIO_REG8_REG_Pos                                    0                                                         /*!< SGPIO REG8: REG Position            */
#define SGPIO_REG8_REG_Msk                                    (0xffffffffUL << SGPIO_REG8_REG_Pos)                      /*!< SGPIO REG8: REG Mask                */

// ---------------------------------------  SGPIO_REG9  -------------------------------------------
#define SGPIO_REG9_REG_Pos                                    0                                                         /*!< SGPIO REG9: REG Position            */
#define SGPIO_REG9_REG_Msk                                    (0xffffffffUL << SGPIO_REG9_REG_Pos)                      /*!< SGPIO REG9: REG Mask                */

// ---------------------------------------  SGPIO_REG10  ------------------------------------------
#define SGPIO_REG10_REG_Pos                                   0                                                         /*!< SGPIO REG10: REG Position           */
#define SGPIO_REG10_REG_Msk                                   (0xffffffffUL << SGPIO_REG10_REG_Pos)                     /*!< SGPIO REG10: REG Mask               */

// ---------------------------------------  SGPIO_REG11  ------------------------------------------
#define SGPIO_REG11_REG_Pos                                   0                                                         /*!< SGPIO REG11: REG Position           */
#define SGPIO_REG11_REG_Msk                                   (0xffffffffUL << SGPIO_REG11_REG_Pos)                     /*!< SGPIO REG11: REG Mask               */

// ---------------------------------------  SGPIO_REG12  ------------------------------------------
#define SGPIO_REG12_REG_Pos                                   0                                                         /*!< SGPIO REG12: REG Position           */
#define SGPIO_REG12_REG_Msk                                   (0xffffffffUL << SGPIO_REG12_REG_Pos)                     /*!< SGPIO REG12: REG Mask               */

// ---------------------------------------  SGPIO_REG13  ------------------------------------------
#define SGPIO_REG13_REG_Pos                                   0                                                         /*!< SGPIO REG13: REG Position           */
#define SGPIO_REG13_REG_Msk                                   (0xffffffffUL << SGPIO_REG13_REG_Pos)                     /*!< SGPIO REG13: REG Mask               */

// ---------------------------------------  SGPIO_REG14  ------------------------------------------
#define SGPIO_REG14_REG_Pos                                   0                                                         /*!< SGPIO REG14: REG Position           */
#define SGPIO_REG14_REG_Msk                                   (0xffffffffUL << SGPIO_REG14_REG_Pos)                     /*!< SGPIO REG14: REG Mask               */

// ---------------------------------------  SGPIO_REG15  ------------------------------------------
#define SGPIO_REG15_REG_Pos                                   0                                                         /*!< SGPIO REG15: REG Position           */
#define SGPIO_REG15_REG_Msk                                   (0xffffffffUL << SGPIO_REG15_REG_Pos)                     /*!< SGPIO REG15: REG Mask               */

// --------------------------------------  SGPIO_REG_SS0  -----------------------------------------
#define SGPIO_REG_SS0_REG_SS_Pos                              0                                                         /*!< SGPIO REG_SS0: REG_SS Position      */
#define SGPIO_REG_SS0_REG_SS_Msk                              (0xffffffffUL << SGPIO_REG_SS0_REG_SS_Pos)                /*!< SGPIO REG_SS0: REG_SS Mask          */

// --------------------------------------  SGPIO_REG_SS1  -----------------------------------------
#define SGPIO_REG_SS1_REG_SS_Pos                              0                                                         /*!< SGPIO REG_SS1: REG_SS Position      */
#define SGPIO_REG_SS1_REG_SS_Msk                              (0xffffffffUL << SGPIO_REG_SS1_REG_SS_Pos)                /*!< SGPIO REG_SS1: REG_SS Mask          */

// --------------------------------------  SGPIO_REG_SS2  -----------------------------------------
#define SGPIO_REG_SS2_REG_SS_Pos                              0                                                         /*!< SGPIO REG_SS2: REG_SS Position      */
#define SGPIO_REG_SS2_REG_SS_Msk                              (0xffffffffUL << SGPIO_REG_SS2_REG_SS_Pos)                /*!< SGPIO REG_SS2: REG_SS Mask          */

// --------------------------------------  SGPIO_REG_SS3  -----------------------------------------
#define SGPIO_REG_SS3_REG_SS_Pos                              0                                                         /*!< SGPIO REG_SS3: REG_SS Position      */
#define SGPIO_REG_SS3_REG_SS_Msk                              (0xffffffffUL << SGPIO_REG_SS3_REG_SS_Pos)                /*!< SGPIO REG_SS3: REG_SS Mask          */

// --------------------------------------  SGPIO_REG_SS4  -----------------------------------------
#define SGPIO_REG_SS4_REG_SS_Pos                              0                                                         /*!< SGPIO REG_SS4: REG_SS Position      */
#define SGPIO_REG_SS4_REG_SS_Msk                              (0xffffffffUL << SGPIO_REG_SS4_REG_SS_Pos)                /*!< SGPIO REG_SS4: REG_SS Mask          */

// --------------------------------------  SGPIO_REG_SS5  -----------------------------------------
#define SGPIO_REG_SS5_REG_SS_Pos                              0                                                         /*!< SGPIO REG_SS5: REG_SS Position      */
#define SGPIO_REG_SS5_REG_SS_Msk                              (0xffffffffUL << SGPIO_REG_SS5_REG_SS_Pos)                /*!< SGPIO REG_SS5: REG_SS Mask          */

// --------------------------------------  SGPIO_REG_SS6  -----------------------------------------
#define SGPIO_REG_SS6_REG_SS_Pos                              0                                                         /*!< SGPIO REG_SS6: REG_SS Position      */
#define SGPIO_REG_SS6_REG_SS_Msk                              (0xffffffffUL << SGPIO_REG_SS6_REG_SS_Pos)                /*!< SGPIO REG_SS6: REG_SS Mask          */

// --------------------------------------  SGPIO_REG_SS7  -----------------------------------------
#define SGPIO_REG_SS7_REG_SS_Pos                              0                                                         /*!< SGPIO REG_SS7: REG_SS Position      */
#define SGPIO_REG_SS7_REG_SS_Msk                              (0xffffffffUL << SGPIO_REG_SS7_REG_SS_Pos)                /*!< SGPIO REG_SS7: REG_SS Mask          */

// --------------------------------------  SGPIO_REG_SS8  -----------------------------------------
#define SGPIO_REG_SS8_REG_SS_Pos                              0                                                         /*!< SGPIO REG_SS8: REG_SS Position      */
#define SGPIO_REG_SS8_REG_SS_Msk                              (0xffffffffUL << SGPIO_REG_SS8_REG_SS_Pos)                /*!< SGPIO REG_SS8: REG_SS Mask          */

// --------------------------------------  SGPIO_REG_SS9  -----------------------------------------
#define SGPIO_REG_SS9_REG_SS_Pos                              0                                                         /*!< SGPIO REG_SS9: REG_SS Position      */
#define SGPIO_REG_SS9_REG_SS_Msk                              (0xffffffffUL << SGPIO_REG_SS9_REG_SS_Pos)                /*!< SGPIO REG_SS9: REG_SS Mask          */

// -------------------------------------  SGPIO_REG_SS10  -----------------------------------------
#define SGPIO_REG_SS10_REG_SS_Pos                             0                                                         /*!< SGPIO REG_SS10: REG_SS Position     */
#define SGPIO_REG_SS10_REG_SS_Msk                             (0xffffffffUL << SGPIO_REG_SS10_REG_SS_Pos)               /*!< SGPIO REG_SS10: REG_SS Mask         */

// -------------------------------------  SGPIO_REG_SS11  -----------------------------------------
#define SGPIO_REG_SS11_REG_SS_Pos                             0                                                         /*!< SGPIO REG_SS11: REG_SS Position     */
#define SGPIO_REG_SS11_REG_SS_Msk                             (0xffffffffUL << SGPIO_REG_SS11_REG_SS_Pos)               /*!< SGPIO REG_SS11: REG_SS Mask         */

// -------------------------------------  SGPIO_REG_SS12  -----------------------------------------
#define SGPIO_REG_SS12_REG_SS_Pos                             0                                                         /*!< SGPIO REG_SS12: REG_SS Position     */
#define SGPIO_REG_SS12_REG_SS_Msk                             (0xffffffffUL << SGPIO_REG_SS12_REG_SS_Pos)               /*!< SGPIO REG_SS12: REG_SS Mask         */

// -------------------------------------  SGPIO_REG_SS13  -----------------------------------------
#define SGPIO_REG_SS13_REG_SS_Pos                             0                                                         /*!< SGPIO REG_SS13: REG_SS Position     */
#define SGPIO_REG_SS13_REG_SS_Msk                             (0xffffffffUL << SGPIO_REG_SS13_REG_SS_Pos)               /*!< SGPIO REG_SS13: REG_SS Mask         */

// -------------------------------------  SGPIO_REG_SS14  -----------------------------------------
#define SGPIO_REG_SS14_REG_SS_Pos                             0                                                         /*!< SGPIO REG_SS14: REG_SS Position     */
#define SGPIO_REG_SS14_REG_SS_Msk                             (0xffffffffUL << SGPIO_REG_SS14_REG_SS_Pos)               /*!< SGPIO REG_SS14: REG_SS Mask         */

// -------------------------------------  SGPIO_REG_SS15  -----------------------------------------
#define SGPIO_REG_SS15_REG_SS_Pos                             0                                                         /*!< SGPIO REG_SS15: REG_SS Position     */
#define SGPIO_REG_SS15_REG_SS_Msk                             (0xffffffffUL << SGPIO_REG_SS15_REG_SS_Pos)               /*!< SGPIO REG_SS15: REG_SS Mask         */

// --------------------------------------  SGPIO_PRESET0  -----------------------------------------
#define SGPIO_PRESET0_PRESET_Pos                              0                                                         /*!< SGPIO PRESET0: PRESET Position      */
#define SGPIO_PRESET0_PRESET_Msk                              (0x00000fffUL << SGPIO_PRESET0_PRESET_Pos)                /*!< SGPIO PRESET0: PRESET Mask          */

// --------------------------------------  SGPIO_PRESET1  -----------------------------------------
#define SGPIO_PRESET1_PRESET_Pos                              0                                                         /*!< SGPIO PRESET1: PRESET Position      */
#define SGPIO_PRESET1_PRESET_Msk                              (0x00000fffUL << SGPIO_PRESET1_PRESET_Pos)                /*!< SGPIO PRESET1: PRESET Mask          */

// --------------------------------------  SGPIO_PRESET2  -----------------------------------------
#define SGPIO_PRESET2_PRESET_Pos                              0                                                         /*!< SGPIO PRESET2: PRESET Position      */
#define SGPIO_PRESET2_PRESET_Msk                              (0x00000fffUL << SGPIO_PRESET2_PRESET_Pos)                /*!< SGPIO PRESET2: PRESET Mask          */

// --------------------------------------  SGPIO_PRESET3  -----------------------------------------
#define SGPIO_PRESET3_PRESET_Pos                              0                                                         /*!< SGPIO PRESET3: PRESET Position      */
#define SGPIO_PRESET3_PRESET_Msk                              (0x00000fffUL << SGPIO_PRESET3_PRESET_Pos)                /*!< SGPIO PRESET3: PRESET Mask          */

// --------------------------------------  SGPIO_PRESET4  -----------------------------------------
#define SGPIO_PRESET4_PRESET_Pos                              0                                                         /*!< SGPIO PRESET4: PRESET Position      */
#define SGPIO_PRESET4_PRESET_Msk                              (0x00000fffUL << SGPIO_PRESET4_PRESET_Pos)                /*!< SGPIO PRESET4: PRESET Mask          */

// --------------------------------------  SGPIO_PRESET5  -----------------------------------------
#define SGPIO_PRESET5_PRESET_Pos                              0                                                         /*!< SGPIO PRESET5: PRESET Position      */
#define SGPIO_PRESET5_PRESET_Msk                              (0x00000fffUL << SGPIO_PRESET5_PRESET_Pos)                /*!< SGPIO PRESET5: PRESET Mask          */

// --------------------------------------  SGPIO_PRESET6  -----------------------------------------
#define SGPIO_PRESET6_PRESET_Pos                              0                                                         /*!< SGPIO PRESET6: PRESET Position      */
#define SGPIO_PRESET6_PRESET_Msk                              (0x00000fffUL << SGPIO_PRESET6_PRESET_Pos)                /*!< SGPIO PRESET6: PRESET Mask          */

// --------------------------------------  SGPIO_PRESET7  -----------------------------------------
#define SGPIO_PRESET7_PRESET_Pos                              0                                                         /*!< SGPIO PRESET7: PRESET Position      */
#define SGPIO_PRESET7_PRESET_Msk                              (0x00000fffUL << SGPIO_PRESET7_PRESET_Pos)                /*!< SGPIO PRESET7: PRESET Mask          */

// --------------------------------------  SGPIO_PRESET8  -----------------------------------------
#define SGPIO_PRESET8_PRESET_Pos                              0                                                         /*!< SGPIO PRESET8: PRESET Position      */
#define SGPIO_PRESET8_PRESET_Msk                              (0x00000fffUL << SGPIO_PRESET8_PRESET_Pos)                /*!< SGPIO PRESET8: PRESET Mask          */

// --------------------------------------  SGPIO_PRESET9  -----------------------------------------
#define SGPIO_PRESET9_PRESET_Pos                              0                                                         /*!< SGPIO PRESET9: PRESET Position      */
#define SGPIO_PRESET9_PRESET_Msk                              (0x00000fffUL << SGPIO_PRESET9_PRESET_Pos)                /*!< SGPIO PRESET9: PRESET Mask          */

// -------------------------------------  SGPIO_PRESET10  -----------------------------------------
#define SGPIO_PRESET10_PRESET_Pos                             0                                                         /*!< SGPIO PRESET10: PRESET Position     */
#define SGPIO_PRESET10_PRESET_Msk                             (0x00000fffUL << SGPIO_PRESET10_PRESET_Pos)               /*!< SGPIO PRESET10: PRESET Mask         */

// -------------------------------------  SGPIO_PRESET11  -----------------------------------------
#define SGPIO_PRESET11_PRESET_Pos                             0                                                         /*!< SGPIO PRESET11: PRESET Position     */
#define SGPIO_PRESET11_PRESET_Msk                             (0x00000fffUL << SGPIO_PRESET11_PRESET_Pos)               /*!< SGPIO PRESET11: PRESET Mask         */

// -------------------------------------  SGPIO_PRESET12  -----------------------------------------
#define SGPIO_PRESET12_PRESET_Pos                             0                                                         /*!< SGPIO PRESET12: PRESET Position     */
#define SGPIO_PRESET12_PRESET_Msk                             (0x00000fffUL << SGPIO_PRESET12_PRESET_Pos)               /*!< SGPIO PRESET12: PRESET Mask         */

// -------------------------------------  SGPIO_PRESET13  -----------------------------------------
#define SGPIO_PRESET13_PRESET_Pos                             0                                                         /*!< SGPIO PRESET13: PRESET Position     */
#define SGPIO_PRESET13_PRESET_Msk                             (0x00000fffUL << SGPIO_PRESET13_PRESET_Pos)               /*!< SGPIO PRESET13: PRESET Mask         */

// -------------------------------------  SGPIO_PRESET14  -----------------------------------------
#define SGPIO_PRESET14_PRESET_Pos                             0                                                         /*!< SGPIO PRESET14: PRESET Position     */
#define SGPIO_PRESET14_PRESET_Msk                             (0x00000fffUL << SGPIO_PRESET14_PRESET_Pos)               /*!< SGPIO PRESET14: PRESET Mask         */

// -------------------------------------  SGPIO_PRESET15  -----------------------------------------
#define SGPIO_PRESET15_PRESET_Pos                             0                                                         /*!< SGPIO PRESET15: PRESET Position     */
#define SGPIO_PRESET15_PRESET_Msk                             (0x00000fffUL << SGPIO_PRESET15_PRESET_Pos)               /*!< SGPIO PRESET15: PRESET Mask         */

// --------------------------------------  SGPIO_COUNT0  ------------------------------------------
#define SGPIO_COUNT0_COUNT_Pos                                0                                                         /*!< SGPIO COUNT0: COUNT Position        */
#define SGPIO_COUNT0_COUNT_Msk                                (0x00000fffUL << SGPIO_COUNT0_COUNT_Pos)                  /*!< SGPIO COUNT0: COUNT Mask            */

// --------------------------------------  SGPIO_COUNT1  ------------------------------------------
#define SGPIO_COUNT1_COUNT_Pos                                0                                                         /*!< SGPIO COUNT1: COUNT Position        */
#define SGPIO_COUNT1_COUNT_Msk                                (0x00000fffUL << SGPIO_COUNT1_COUNT_Pos)                  /*!< SGPIO COUNT1: COUNT Mask            */

// --------------------------------------  SGPIO_COUNT2  ------------------------------------------
#define SGPIO_COUNT2_COUNT_Pos                                0                                                         /*!< SGPIO COUNT2: COUNT Position        */
#define SGPIO_COUNT2_COUNT_Msk                                (0x00000fffUL << SGPIO_COUNT2_COUNT_Pos)                  /*!< SGPIO COUNT2: COUNT Mask            */

// --------------------------------------  SGPIO_COUNT3  ------------------------------------------
#define SGPIO_COUNT3_COUNT_Pos                                0                                                         /*!< SGPIO COUNT3: COUNT Position        */
#define SGPIO_COUNT3_COUNT_Msk                                (0x00000fffUL << SGPIO_COUNT3_COUNT_Pos)                  /*!< SGPIO COUNT3: COUNT Mask            */

// --------------------------------------  SGPIO_COUNT4  ------------------------------------------
#define SGPIO_COUNT4_COUNT_Pos                                0                                                         /*!< SGPIO COUNT4: COUNT Position        */
#define SGPIO_COUNT4_COUNT_Msk                                (0x00000fffUL << SGPIO_COUNT4_COUNT_Pos)                  /*!< SGPIO COUNT4: COUNT Mask            */

// --------------------------------------  SGPIO_COUNT5  ------------------------------------------
#define SGPIO_COUNT5_COUNT_Pos                                0                                                         /*!< SGPIO COUNT5: COUNT Position        */
#define SGPIO_COUNT5_COUNT_Msk                                (0x00000fffUL << SGPIO_COUNT5_COUNT_Pos)                  /*!< SGPIO COUNT5: COUNT Mask            */

// --------------------------------------  SGPIO_COUNT6  ------------------------------------------
#define SGPIO_COUNT6_COUNT_Pos                                0                                                         /*!< SGPIO COUNT6: COUNT Position        */
#define SGPIO_COUNT6_COUNT_Msk                                (0x00000fffUL << SGPIO_COUNT6_COUNT_Pos)                  /*!< SGPIO COUNT6: COUNT Mask            */

// --------------------------------------  SGPIO_COUNT7  ------------------------------------------
#define SGPIO_COUNT7_COUNT_Pos                                0                                                         /*!< SGPIO COUNT7: COUNT Position        */
#define SGPIO_COUNT7_COUNT_Msk                                (0x00000fffUL << SGPIO_COUNT7_COUNT_Pos)                  /*!< SGPIO COUNT7: COUNT Mask            */

// --------------------------------------  SGPIO_COUNT8  ------------------------------------------
#define SGPIO_COUNT8_COUNT_Pos                                0                                                         /*!< SGPIO COUNT8: COUNT Position        */
#define SGPIO_COUNT8_COUNT_Msk                                (0x00000fffUL << SGPIO_COUNT8_COUNT_Pos)                  /*!< SGPIO COUNT8: COUNT Mask            */

// --------------------------------------  SGPIO_COUNT9  ------------------------------------------
#define SGPIO_COUNT9_COUNT_Pos                                0                                                         /*!< SGPIO COUNT9: COUNT Position        */
#define SGPIO_COUNT9_COUNT_Msk                                (0x00000fffUL << SGPIO_COUNT9_COUNT_Pos)                  /*!< SGPIO COUNT9: COUNT Mask            */

// --------------------------------------  SGPIO_COUNT10  -----------------------------------------
#define SGPIO_COUNT10_COUNT_Pos                               0                                                         /*!< SGPIO COUNT10: COUNT Position       */
#define SGPIO_COUNT10_COUNT_Msk                               (0x00000fffUL << SGPIO_COUNT10_COUNT_Pos)                 /*!< SGPIO COUNT10: COUNT Mask           */

// --------------------------------------  SGPIO_COUNT11  -----------------------------------------
#define SGPIO_COUNT11_COUNT_Pos                               0                                                         /*!< SGPIO COUNT11: COUNT Position       */
#define SGPIO_COUNT11_COUNT_Msk                               (0x00000fffUL << SGPIO_COUNT11_COUNT_Pos)                 /*!< SGPIO COUNT11: COUNT Mask           */

// --------------------------------------  SGPIO_COUNT12  -----------------------------------------
#define SGPIO_COUNT12_COUNT_Pos                               0                                                         /*!< SGPIO COUNT12: COUNT Position       */
#define SGPIO_COUNT12_COUNT_Msk                               (0x00000fffUL << SGPIO_COUNT12_COUNT_Pos)                 /*!< SGPIO COUNT12: COUNT Mask           */

// --------------------------------------  SGPIO_COUNT13  -----------------------------------------
#define SGPIO_COUNT13_COUNT_Pos                               0                                                         /*!< SGPIO COUNT13: COUNT Position       */
#define SGPIO_COUNT13_COUNT_Msk                               (0x00000fffUL << SGPIO_COUNT13_COUNT_Pos)                 /*!< SGPIO COUNT13: COUNT Mask           */

// --------------------------------------  SGPIO_COUNT14  -----------------------------------------
#define SGPIO_COUNT14_COUNT_Pos                               0                                                         /*!< SGPIO COUNT14: COUNT Position       */
#define SGPIO_COUNT14_COUNT_Msk                               (0x00000fffUL << SGPIO_COUNT14_COUNT_Pos)                 /*!< SGPIO COUNT14: COUNT Mask           */

// --------------------------------------  SGPIO_COUNT15  -----------------------------------------
#define SGPIO_COUNT15_COUNT_Pos                               0                                                         /*!< SGPIO COUNT15: COUNT Position       */
#define SGPIO_COUNT15_COUNT_Msk                               (0x00000fffUL << SGPIO_COUNT15_COUNT_Pos)                 /*!< SGPIO COUNT15: COUNT Mask           */

// ---------------------------------------  SGPIO_POS0  -------------------------------------------
#define SGPIO_POS0_POS_Pos                                    0                                                         /*!< SGPIO POS0: POS Position            */
#define SGPIO_POS0_POS_Msk                                    (0x000000ffUL << SGPIO_POS0_POS_Pos)                      /*!< SGPIO POS0: POS Mask                */
#define SGPIO_POS0_POS_RESET_Pos                              8                                                         /*!< SGPIO POS0: POS_RESET Position      */
#define SGPIO_POS0_POS_RESET_Msk                              (0x000000ffUL << SGPIO_POS0_POS_RESET_Pos)                /*!< SGPIO POS0: POS_RESET Mask          */

// ---------------------------------------  SGPIO_POS1  -------------------------------------------
#define SGPIO_POS1_POS_Pos                                    0                                                         /*!< SGPIO POS1: POS Position            */
#define SGPIO_POS1_POS_Msk                                    (0x000000ffUL << SGPIO_POS1_POS_Pos)                      /*!< SGPIO POS1: POS Mask                */
#define SGPIO_POS1_POS_RESET_Pos                              8                                                         /*!< SGPIO POS1: POS_RESET Position      */
#define SGPIO_POS1_POS_RESET_Msk                              (0x000000ffUL << SGPIO_POS1_POS_RESET_Pos)                /*!< SGPIO POS1: POS_RESET Mask          */

// ---------------------------------------  SGPIO_POS2  -------------------------------------------
#define SGPIO_POS2_POS_Pos                                    0                                                         /*!< SGPIO POS2: POS Position            */
#define SGPIO_POS2_POS_Msk                                    (0x000000ffUL << SGPIO_POS2_POS_Pos)                      /*!< SGPIO POS2: POS Mask                */
#define SGPIO_POS2_POS_RESET_Pos                              8                                                         /*!< SGPIO POS2: POS_RESET Position      */
#define SGPIO_POS2_POS_RESET_Msk                              (0x000000ffUL << SGPIO_POS2_POS_RESET_Pos)                /*!< SGPIO POS2: POS_RESET Mask          */

// ---------------------------------------  SGPIO_POS3  -------------------------------------------
#define SGPIO_POS3_POS_Pos                                    0                                                         /*!< SGPIO POS3: POS Position            */
#define SGPIO_POS3_POS_Msk                                    (0x000000ffUL << SGPIO_POS3_POS_Pos)                      /*!< SGPIO POS3: POS Mask                */
#define SGPIO_POS3_POS_RESET_Pos                              8                                                         /*!< SGPIO POS3: POS_RESET Position      */
#define SGPIO_POS3_POS_RESET_Msk                              (0x000000ffUL << SGPIO_POS3_POS_RESET_Pos)                /*!< SGPIO POS3: POS_RESET Mask          */

// ---------------------------------------  SGPIO_POS4  -------------------------------------------
#define SGPIO_POS4_POS_Pos                                    0                                                         /*!< SGPIO POS4: POS Position            */
#define SGPIO_POS4_POS_Msk                                    (0x000000ffUL << SGPIO_POS4_POS_Pos)                      /*!< SGPIO POS4: POS Mask                */
#define SGPIO_POS4_POS_RESET_Pos                              8                                                         /*!< SGPIO POS4: POS_RESET Position      */
#define SGPIO_POS4_POS_RESET_Msk                              (0x000000ffUL << SGPIO_POS4_POS_RESET_Pos)                /*!< SGPIO POS4: POS_RESET Mask          */

// ---------------------------------------  SGPIO_POS5  -------------------------------------------
#define SGPIO_POS5_POS_Pos                                    0                                                         /*!< SGPIO POS5: POS Position            */
#define SGPIO_POS5_POS_Msk                                    (0x000000ffUL << SGPIO_POS5_POS_Pos)                      /*!< SGPIO POS5: POS Mask                */
#define SGPIO_POS5_POS_RESET_Pos                              8                                                         /*!< SGPIO POS5: POS_RESET Position      */
#define SGPIO_POS5_POS_RESET_Msk                              (0x000000ffUL << SGPIO_POS5_POS_RESET_Pos)                /*!< SGPIO POS5: POS_RESET Mask          */

// ---------------------------------------  SGPIO_POS6  -------------------------------------------
#define SGPIO_POS6_POS_Pos                                    0                                                         /*!< SGPIO POS6: POS Position            */
#define SGPIO_POS6_POS_Msk                                    (0x000000ffUL << SGPIO_POS6_POS_Pos)                      /*!< SGPIO POS6: POS Mask                */
#define SGPIO_POS6_POS_RESET_Pos                              8                                                         /*!< SGPIO POS6: POS_RESET Position      */
#define SGPIO_POS6_POS_RESET_Msk                              (0x000000ffUL << SGPIO_POS6_POS_RESET_Pos)                /*!< SGPIO POS6: POS_RESET Mask          */

// ---------------------------------------  SGPIO_POS7  -------------------------------------------
#define SGPIO_POS7_POS_Pos                                    0                                                         /*!< SGPIO POS7: POS Position            */
#define SGPIO_POS7_POS_Msk                                    (0x000000ffUL << SGPIO_POS7_POS_Pos)                      /*!< SGPIO POS7: POS Mask                */
#define SGPIO_POS7_POS_RESET_Pos                              8                                                         /*!< SGPIO POS7: POS_RESET Position      */
#define SGPIO_POS7_POS_RESET_Msk                              (0x000000ffUL << SGPIO_POS7_POS_RESET_Pos)                /*!< SGPIO POS7: POS_RESET Mask          */

// ---------------------------------------  SGPIO_POS8  -------------------------------------------
#define SGPIO_POS8_POS_Pos                                    0                                                         /*!< SGPIO POS8: POS Position            */
#define SGPIO_POS8_POS_Msk                                    (0x000000ffUL << SGPIO_POS8_POS_Pos)                      /*!< SGPIO POS8: POS Mask                */
#define SGPIO_POS8_POS_RESET_Pos                              8                                                         /*!< SGPIO POS8: POS_RESET Position      */
#define SGPIO_POS8_POS_RESET_Msk                              (0x000000ffUL << SGPIO_POS8_POS_RESET_Pos)                /*!< SGPIO POS8: POS_RESET Mask          */

// ---------------------------------------  SGPIO_POS9  -------------------------------------------
#define SGPIO_POS9_POS_Pos                                    0                                                         /*!< SGPIO POS9: POS Position            */
#define SGPIO_POS9_POS_Msk                                    (0x000000ffUL << SGPIO_POS9_POS_Pos)                      /*!< SGPIO POS9: POS Mask                */
#define SGPIO_POS9_POS_RESET_Pos                              8                                                         /*!< SGPIO POS9: POS_RESET Position      */
#define SGPIO_POS9_POS_RESET_Msk                              (0x000000ffUL << SGPIO_POS9_POS_RESET_Pos)                /*!< SGPIO POS9: POS_RESET Mask          */

// ---------------------------------------  SGPIO_POS10  ------------------------------------------
#define SGPIO_POS10_POS_Pos                                   0                                                         /*!< SGPIO POS10: POS Position           */
#define SGPIO_POS10_POS_Msk                                   (0x000000ffUL << SGPIO_POS10_POS_Pos)                     /*!< SGPIO POS10: POS Mask               */
#define SGPIO_POS10_POS_RESET_Pos                             8                                                         /*!< SGPIO POS10: POS_RESET Position     */
#define SGPIO_POS10_POS_RESET_Msk                             (0x000000ffUL << SGPIO_POS10_POS_RESET_Pos)               /*!< SGPIO POS10: POS_RESET Mask         */

// ---------------------------------------  SGPIO_POS11  ------------------------------------------
#define SGPIO_POS11_POS_Pos                                   0                                                         /*!< SGPIO POS11: POS Position           */
#define SGPIO_POS11_POS_Msk                                   (0x000000ffUL << SGPIO_POS11_POS_Pos)                     /*!< SGPIO POS11: POS Mask               */
#define SGPIO_POS11_POS_RESET_Pos                             8                                                         /*!< SGPIO POS11: POS_RESET Position     */
#define SGPIO_POS11_POS_RESET_Msk                             (0x000000ffUL << SGPIO_POS11_POS_RESET_Pos)               /*!< SGPIO POS11: POS_RESET Mask         */

// ---------------------------------------  SGPIO_POS12  ------------------------------------------
#define SGPIO_POS12_POS_Pos                                   0                                                         /*!< SGPIO POS12: POS Position           */
#define SGPIO_POS12_POS_Msk                                   (0x000000ffUL << SGPIO_POS12_POS_Pos)                     /*!< SGPIO POS12: POS Mask               */
#define SGPIO_POS12_POS_RESET_Pos                             8                                                         /*!< SGPIO POS12: POS_RESET Position     */
#define SGPIO_POS12_POS_RESET_Msk                             (0x000000ffUL << SGPIO_POS12_POS_RESET_Pos)               /*!< SGPIO POS12: POS_RESET Mask         */

// ---------------------------------------  SGPIO_POS13  ------------------------------------------
#define SGPIO_POS13_POS_Pos                                   0                                                         /*!< SGPIO POS13: POS Position           */
#define SGPIO_POS13_POS_Msk                                   (0x000000ffUL << SGPIO_POS13_POS_Pos)                     /*!< SGPIO POS13: POS Mask               */
#define SGPIO_POS13_POS_RESET_Pos                             8                                                         /*!< SGPIO POS13: POS_RESET Position     */
#define SGPIO_POS13_POS_RESET_Msk                             (0x000000ffUL << SGPIO_POS13_POS_RESET_Pos)               /*!< SGPIO POS13: POS_RESET Mask         */

// ---------------------------------------  SGPIO_POS14  ------------------------------------------
#define SGPIO_POS14_POS_Pos                                   0                                                         /*!< SGPIO POS14: POS Position           */
#define SGPIO_POS14_POS_Msk                                   (0x000000ffUL << SGPIO_POS14_POS_Pos)                     /*!< SGPIO POS14: POS Mask               */
#define SGPIO_POS14_POS_RESET_Pos                             8                                                         /*!< SGPIO POS14: POS_RESET Position     */
#define SGPIO_POS14_POS_RESET_Msk                             (0x000000ffUL << SGPIO_POS14_POS_RESET_Pos)               /*!< SGPIO POS14: POS_RESET Mask         */

// ---------------------------------------  SGPIO_POS15  ------------------------------------------
#define SGPIO_POS15_POS_Pos                                   0                                                         /*!< SGPIO POS15: POS Position           */
#define SGPIO_POS15_POS_Msk                                   (0x000000ffUL << SGPIO_POS15_POS_Pos)                     /*!< SGPIO POS15: POS Mask               */
#define SGPIO_POS15_POS_RESET_Pos                             8                                                         /*!< SGPIO POS15: POS_RESET Position     */
#define SGPIO_POS15_POS_RESET_Msk                             (0x000000ffUL << SGPIO_POS15_POS_RESET_Pos)               /*!< SGPIO POS15: POS_RESET Mask         */

// --------------------------------------  SGPIO_MASK_A  ------------------------------------------
#define SGPIO_MASK_A_MASK_A0_Pos                              0                                                         /*!< SGPIO MASK_A: MASK_A0 Position      */
#define SGPIO_MASK_A_MASK_A0_Msk                              (0x01UL << SGPIO_MASK_A_MASK_A0_Pos)                      /*!< SGPIO MASK_A: MASK_A0 Mask          */
#define SGPIO_MASK_A_MASK_A1_Pos                              1                                                         /*!< SGPIO MASK_A: MASK_A1 Position      */
#define SGPIO_MASK_A_MASK_A1_Msk                              (0x01UL << SGPIO_MASK_A_MASK_A1_Pos)                      /*!< SGPIO MASK_A: MASK_A1 Mask          */
#define SGPIO_MASK_A_MASK_A2_Pos                              2                                                         /*!< SGPIO MASK_A: MASK_A2 Position      */
#define SGPIO_MASK_A_MASK_A2_Msk                              (0x01UL << SGPIO_MASK_A_MASK_A2_Pos)                      /*!< SGPIO MASK_A: MASK_A2 Mask          */
#define SGPIO_MASK_A_MASK_A3_Pos                              3                                                         /*!< SGPIO MASK_A: MASK_A3 Position      */
#define SGPIO_MASK_A_MASK_A3_Msk                              (0x01UL << SGPIO_MASK_A_MASK_A3_Pos)                      /*!< SGPIO MASK_A: MASK_A3 Mask          */
#define SGPIO_MASK_A_MASK_A4_Pos                              4                                                         /*!< SGPIO MASK_A: MASK_A4 Position      */
#define SGPIO_MASK_A_MASK_A4_Msk                              (0x01UL << SGPIO_MASK_A_MASK_A4_Pos)                      /*!< SGPIO MASK_A: MASK_A4 Mask          */
#define SGPIO_MASK_A_MASK_A5_Pos                              5                                                         /*!< SGPIO MASK_A: MASK_A5 Position      */
#define SGPIO_MASK_A_MASK_A5_Msk                              (0x01UL << SGPIO_MASK_A_MASK_A5_Pos)                      /*!< SGPIO MASK_A: MASK_A5 Mask          */
#define SGPIO_MASK_A_MASK_A6_Pos                              6                                                         /*!< SGPIO MASK_A: MASK_A6 Position      */
#define SGPIO_MASK_A_MASK_A6_Msk                              (0x01UL << SGPIO_MASK_A_MASK_A6_Pos)                      /*!< SGPIO MASK_A: MASK_A6 Mask          */
#define SGPIO_MASK_A_MASK_A7_Pos                              7                                                         /*!< SGPIO MASK_A: MASK_A7 Position      */
#define SGPIO_MASK_A_MASK_A7_Msk                              (0x01UL << SGPIO_MASK_A_MASK_A7_Pos)                      /*!< SGPIO MASK_A: MASK_A7 Mask          */
#define SGPIO_MASK_A_MASK_A8_Pos                              8                                                         /*!< SGPIO MASK_A: MASK_A8 Position      */
#define SGPIO_MASK_A_MASK_A8_Msk                              (0x01UL << SGPIO_MASK_A_MASK_A8_Pos)                      /*!< SGPIO MASK_A: MASK_A8 Mask          */
#define SGPIO_MASK_A_MASK_A9_Pos                              9                                                         /*!< SGPIO MASK_A: MASK_A9 Position      */
#define SGPIO_MASK_A_MASK_A9_Msk                              (0x01UL << SGPIO_MASK_A_MASK_A9_Pos)                      /*!< SGPIO MASK_A: MASK_A9 Mask          */
#define SGPIO_MASK_A_MASK_A10_Pos                             10                                                        /*!< SGPIO MASK_A: MASK_A10 Position     */
#define SGPIO_MASK_A_MASK_A10_Msk                             (0x01UL << SGPIO_MASK_A_MASK_A10_Pos)                     /*!< SGPIO MASK_A: MASK_A10 Mask         */
#define SGPIO_MASK_A_MASK_A11_Pos                             11                                                        /*!< SGPIO MASK_A: MASK_A11 Position     */
#define SGPIO_MASK_A_MASK_A11_Msk                             (0x01UL << SGPIO_MASK_A_MASK_A11_Pos)                     /*!< SGPIO MASK_A: MASK_A11 Mask         */
#define SGPIO_MASK_A_MASK_A12_Pos                             12                                                        /*!< SGPIO MASK_A: MASK_A12 Position     */
#define SGPIO_MASK_A_MASK_A12_Msk                             (0x01UL << SGPIO_MASK_A_MASK_A12_Pos)                     /*!< SGPIO MASK_A: MASK_A12 Mask         */
#define SGPIO_MASK_A_MASK_A13_Pos                             13                                                        /*!< SGPIO MASK_A: MASK_A13 Position     */
#define SGPIO_MASK_A_MASK_A13_Msk                             (0x01UL << SGPIO_MASK_A_MASK_A13_Pos)                     /*!< SGPIO MASK_A: MASK_A13 Mask         */
#define SGPIO_MASK_A_MASK_A14_Pos                             14                                                        /*!< SGPIO MASK_A: MASK_A14 Position     */
#define SGPIO_MASK_A_MASK_A14_Msk                             (0x01UL << SGPIO_MASK_A_MASK_A14_Pos)                     /*!< SGPIO MASK_A: MASK_A14 Mask         */
#define SGPIO_MASK_A_MASK_A15_Pos                             15                                                        /*!< SGPIO MASK_A: MASK_A15 Position     */
#define SGPIO_MASK_A_MASK_A15_Msk                             (0x01UL << SGPIO_MASK_A_MASK_A15_Pos)                     /*!< SGPIO MASK_A: MASK_A15 Mask         */
#define SGPIO_MASK_A_MASK_A16_Pos                             16                                                        /*!< SGPIO MASK_A: MASK_A16 Position     */
#define SGPIO_MASK_A_MASK_A16_Msk                             (0x01UL << SGPIO_MASK_A_MASK_A16_Pos)                     /*!< SGPIO MASK_A: MASK_A16 Mask         */
#define SGPIO_MASK_A_MASK_A17_Pos                             17                                                        /*!< SGPIO MASK_A: MASK_A17 Position     */
#define SGPIO_MASK_A_MASK_A17_Msk                             (0x01UL << SGPIO_MASK_A_MASK_A17_Pos)                     /*!< SGPIO MASK_A: MASK_A17 Mask         */
#define SGPIO_MASK_A_MASK_A18_Pos                             18                                                        /*!< SGPIO MASK_A: MASK_A18 Position     */
#define SGPIO_MASK_A_MASK_A18_Msk                             (0x01UL << SGPIO_MASK_A_MASK_A18_Pos)                     /*!< SGPIO MASK_A: MASK_A18 Mask         */
#define SGPIO_MASK_A_MASK_A19_Pos                             19                                                        /*!< SGPIO MASK_A: MASK_A19 Position     */
#define SGPIO_MASK_A_MASK_A19_Msk                             (0x01UL << SGPIO_MASK_A_MASK_A19_Pos)                     /*!< SGPIO MASK_A: MASK_A19 Mask         */
#define SGPIO_MASK_A_MASK_A20_Pos                             20                                                        /*!< SGPIO MASK_A: MASK_A20 Position     */
#define SGPIO_MASK_A_MASK_A20_Msk                             (0x01UL << SGPIO_MASK_A_MASK_A20_Pos)                     /*!< SGPIO MASK_A: MASK_A20 Mask         */
#define SGPIO_MASK_A_MASK_A21_Pos                             21                                                        /*!< SGPIO MASK_A: MASK_A21 Position     */
#define SGPIO_MASK_A_MASK_A21_Msk                             (0x01UL << SGPIO_MASK_A_MASK_A21_Pos)                     /*!< SGPIO MASK_A: MASK_A21 Mask         */
#define SGPIO_MASK_A_MASK_A22_Pos                             22                                                        /*!< SGPIO MASK_A: MASK_A22 Position     */
#define SGPIO_MASK_A_MASK_A22_Msk                             (0x01UL << SGPIO_MASK_A_MASK_A22_Pos)                     /*!< SGPIO MASK_A: MASK_A22 Mask         */
#define SGPIO_MASK_A_MASK_A23_Pos                             23                                                        /*!< SGPIO MASK_A: MASK_A23 Position     */
#define SGPIO_MASK_A_MASK_A23_Msk                             (0x01UL << SGPIO_MASK_A_MASK_A23_Pos)                     /*!< SGPIO MASK_A: MASK_A23 Mask         */
#define SGPIO_MASK_A_MASK_A24_Pos                             24                                                        /*!< SGPIO MASK_A: MASK_A24 Position     */
#define SGPIO_MASK_A_MASK_A24_Msk                             (0x01UL << SGPIO_MASK_A_MASK_A24_Pos)                     /*!< SGPIO MASK_A: MASK_A24 Mask         */
#define SGPIO_MASK_A_MASK_A25_Pos                             25                                                        /*!< SGPIO MASK_A: MASK_A25 Position     */
#define SGPIO_MASK_A_MASK_A25_Msk                             (0x01UL << SGPIO_MASK_A_MASK_A25_Pos)                     /*!< SGPIO MASK_A: MASK_A25 Mask         */
#define SGPIO_MASK_A_MASK_A26_Pos                             26                                                        /*!< SGPIO MASK_A: MASK_A26 Position     */
#define SGPIO_MASK_A_MASK_A26_Msk                             (0x01UL << SGPIO_MASK_A_MASK_A26_Pos)                     /*!< SGPIO MASK_A: MASK_A26 Mask         */
#define SGPIO_MASK_A_MASK_A27_Pos                             27                                                        /*!< SGPIO MASK_A: MASK_A27 Position     */
#define SGPIO_MASK_A_MASK_A27_Msk                             (0x01UL << SGPIO_MASK_A_MASK_A27_Pos)                     /*!< SGPIO MASK_A: MASK_A27 Mask         */
#define SGPIO_MASK_A_MASK_A28_Pos                             28                                                        /*!< SGPIO MASK_A: MASK_A28 Position     */
#define SGPIO_MASK_A_MASK_A28_Msk                             (0x01UL << SGPIO_MASK_A_MASK_A28_Pos)                     /*!< SGPIO MASK_A: MASK_A28 Mask         */
#define SGPIO_MASK_A_MASK_A29_Pos                             29                                                        /*!< SGPIO MASK_A: MASK_A29 Position     */
#define SGPIO_MASK_A_MASK_A29_Msk                             (0x01UL << SGPIO_MASK_A_MASK_A29_Pos)                     /*!< SGPIO MASK_A: MASK_A29 Mask         */
#define SGPIO_MASK_A_MASK_A30_Pos                             30                                                        /*!< SGPIO MASK_A: MASK_A30 Position     */
#define SGPIO_MASK_A_MASK_A30_Msk                             (0x01UL << SGPIO_MASK_A_MASK_A30_Pos)                     /*!< SGPIO MASK_A: MASK_A30 Mask         */
#define SGPIO_MASK_A_MASK_A31_Pos                             31                                                        /*!< SGPIO MASK_A: MASK_A31 Position     */
#define SGPIO_MASK_A_MASK_A31_Msk                             (0x01UL << SGPIO_MASK_A_MASK_A31_Pos)                     /*!< SGPIO MASK_A: MASK_A31 Mask         */

// --------------------------------------  SGPIO_MASK_H  ------------------------------------------
#define SGPIO_MASK_H_MASK_H0_Pos                              0                                                         /*!< SGPIO MASK_H: MASK_H0 Position      */
#define SGPIO_MASK_H_MASK_H0_Msk                              (0x01UL << SGPIO_MASK_H_MASK_H0_Pos)                      /*!< SGPIO MASK_H: MASK_H0 Mask          */
#define SGPIO_MASK_H_MASK_H1_Pos                              1                                                         /*!< SGPIO MASK_H: MASK_H1 Position      */
#define SGPIO_MASK_H_MASK_H1_Msk                              (0x01UL << SGPIO_MASK_H_MASK_H1_Pos)                      /*!< SGPIO MASK_H: MASK_H1 Mask          */
#define SGPIO_MASK_H_MASK_H2_Pos                              2                                                         /*!< SGPIO MASK_H: MASK_H2 Position      */
#define SGPIO_MASK_H_MASK_H2_Msk                              (0x01UL << SGPIO_MASK_H_MASK_H2_Pos)                      /*!< SGPIO MASK_H: MASK_H2 Mask          */
#define SGPIO_MASK_H_MASK_H3_Pos                              3                                                         /*!< SGPIO MASK_H: MASK_H3 Position      */
#define SGPIO_MASK_H_MASK_H3_Msk                              (0x01UL << SGPIO_MASK_H_MASK_H3_Pos)                      /*!< SGPIO MASK_H: MASK_H3 Mask          */
#define SGPIO_MASK_H_MASK_H4_Pos                              4                                                         /*!< SGPIO MASK_H: MASK_H4 Position      */
#define SGPIO_MASK_H_MASK_H4_Msk                              (0x01UL << SGPIO_MASK_H_MASK_H4_Pos)                      /*!< SGPIO MASK_H: MASK_H4 Mask          */
#define SGPIO_MASK_H_MASK_H5_Pos                              5                                                         /*!< SGPIO MASK_H: MASK_H5 Position      */
#define SGPIO_MASK_H_MASK_H5_Msk                              (0x01UL << SGPIO_MASK_H_MASK_H5_Pos)                      /*!< SGPIO MASK_H: MASK_H5 Mask          */
#define SGPIO_MASK_H_MASK_H6_Pos                              6                                                         /*!< SGPIO MASK_H: MASK_H6 Position      */
#define SGPIO_MASK_H_MASK_H6_Msk                              (0x01UL << SGPIO_MASK_H_MASK_H6_Pos)                      /*!< SGPIO MASK_H: MASK_H6 Mask          */
#define SGPIO_MASK_H_MASK_H7_Pos                              7                                                         /*!< SGPIO MASK_H: MASK_H7 Position      */
#define SGPIO_MASK_H_MASK_H7_Msk                              (0x01UL << SGPIO_MASK_H_MASK_H7_Pos)                      /*!< SGPIO MASK_H: MASK_H7 Mask          */
#define SGPIO_MASK_H_MASK_H8_Pos                              8                                                         /*!< SGPIO MASK_H: MASK_H8 Position      */
#define SGPIO_MASK_H_MASK_H8_Msk                              (0x01UL << SGPIO_MASK_H_MASK_H8_Pos)                      /*!< SGPIO MASK_H: MASK_H8 Mask          */
#define SGPIO_MASK_H_MASK_H9_Pos                              9                                                         /*!< SGPIO MASK_H: MASK_H9 Position      */
#define SGPIO_MASK_H_MASK_H9_Msk                              (0x01UL << SGPIO_MASK_H_MASK_H9_Pos)                      /*!< SGPIO MASK_H: MASK_H9 Mask          */
#define SGPIO_MASK_H_MASK_H10_Pos                             10                                                        /*!< SGPIO MASK_H: MASK_H10 Position     */
#define SGPIO_MASK_H_MASK_H10_Msk                             (0x01UL << SGPIO_MASK_H_MASK_H10_Pos)                     /*!< SGPIO MASK_H: MASK_H10 Mask         */
#define SGPIO_MASK_H_MASK_H11_Pos                             11                                                        /*!< SGPIO MASK_H: MASK_H11 Position     */
#define SGPIO_MASK_H_MASK_H11_Msk                             (0x01UL << SGPIO_MASK_H_MASK_H11_Pos)                     /*!< SGPIO MASK_H: MASK_H11 Mask         */
#define SGPIO_MASK_H_MASK_H12_Pos                             12                                                        /*!< SGPIO MASK_H: MASK_H12 Position     */
#define SGPIO_MASK_H_MASK_H12_Msk                             (0x01UL << SGPIO_MASK_H_MASK_H12_Pos)                     /*!< SGPIO MASK_H: MASK_H12 Mask         */
#define SGPIO_MASK_H_MASK_H13_Pos                             13                                                        /*!< SGPIO MASK_H: MASK_H13 Position     */
#define SGPIO_MASK_H_MASK_H13_Msk                             (0x01UL << SGPIO_MASK_H_MASK_H13_Pos)                     /*!< SGPIO MASK_H: MASK_H13 Mask         */
#define SGPIO_MASK_H_MASK_H14_Pos                             14                                                        /*!< SGPIO MASK_H: MASK_H14 Position     */
#define SGPIO_MASK_H_MASK_H14_Msk                             (0x01UL << SGPIO_MASK_H_MASK_H14_Pos)                     /*!< SGPIO MASK_H: MASK_H14 Mask         */
#define SGPIO_MASK_H_MASK_H15_Pos                             15                                                        /*!< SGPIO MASK_H: MASK_H15 Position     */
#define SGPIO_MASK_H_MASK_H15_Msk                             (0x01UL << SGPIO_MASK_H_MASK_H15_Pos)                     /*!< SGPIO MASK_H: MASK_H15 Mask         */
#define SGPIO_MASK_H_MASK_H16_Pos                             16                                                        /*!< SGPIO MASK_H: MASK_H16 Position     */
#define SGPIO_MASK_H_MASK_H16_Msk                             (0x01UL << SGPIO_MASK_H_MASK_H16_Pos)                     /*!< SGPIO MASK_H: MASK_H16 Mask         */
#define SGPIO_MASK_H_MASK_H17_Pos                             17                                                        /*!< SGPIO MASK_H: MASK_H17 Position     */
#define SGPIO_MASK_H_MASK_H17_Msk                             (0x01UL << SGPIO_MASK_H_MASK_H17_Pos)                     /*!< SGPIO MASK_H: MASK_H17 Mask         */
#define SGPIO_MASK_H_MASK_H18_Pos                             18                                                        /*!< SGPIO MASK_H: MASK_H18 Position     */
#define SGPIO_MASK_H_MASK_H18_Msk                             (0x01UL << SGPIO_MASK_H_MASK_H18_Pos)                     /*!< SGPIO MASK_H: MASK_H18 Mask         */
#define SGPIO_MASK_H_MASK_H19_Pos                             19                                                        /*!< SGPIO MASK_H: MASK_H19 Position     */
#define SGPIO_MASK_H_MASK_H19_Msk                             (0x01UL << SGPIO_MASK_H_MASK_H19_Pos)                     /*!< SGPIO MASK_H: MASK_H19 Mask         */
#define SGPIO_MASK_H_MASK_H20_Pos                             20                                                        /*!< SGPIO MASK_H: MASK_H20 Position     */
#define SGPIO_MASK_H_MASK_H20_Msk                             (0x01UL << SGPIO_MASK_H_MASK_H20_Pos)                     /*!< SGPIO MASK_H: MASK_H20 Mask         */
#define SGPIO_MASK_H_MASK_H21_Pos                             21                                                        /*!< SGPIO MASK_H: MASK_H21 Position     */
#define SGPIO_MASK_H_MASK_H21_Msk                             (0x01UL << SGPIO_MASK_H_MASK_H21_Pos)                     /*!< SGPIO MASK_H: MASK_H21 Mask         */
#define SGPIO_MASK_H_MASK_H22_Pos                             22                                                        /*!< SGPIO MASK_H: MASK_H22 Position     */
#define SGPIO_MASK_H_MASK_H22_Msk                             (0x01UL << SGPIO_MASK_H_MASK_H22_Pos)                     /*!< SGPIO MASK_H: MASK_H22 Mask         */
#define SGPIO_MASK_H_MASK_H23_Pos                             23                                                        /*!< SGPIO MASK_H: MASK_H23 Position     */
#define SGPIO_MASK_H_MASK_H23_Msk                             (0x01UL << SGPIO_MASK_H_MASK_H23_Pos)                     /*!< SGPIO MASK_H: MASK_H23 Mask         */
#define SGPIO_MASK_H_MASK_H24_Pos                             24                                                        /*!< SGPIO MASK_H: MASK_H24 Position     */
#define SGPIO_MASK_H_MASK_H24_Msk                             (0x01UL << SGPIO_MASK_H_MASK_H24_Pos)                     /*!< SGPIO MASK_H: MASK_H24 Mask         */
#define SGPIO_MASK_H_MASK_H25_Pos                             25                                                        /*!< SGPIO MASK_H: MASK_H25 Position     */
#define SGPIO_MASK_H_MASK_H25_Msk                             (0x01UL << SGPIO_MASK_H_MASK_H25_Pos)                     /*!< SGPIO MASK_H: MASK_H25 Mask         */
#define SGPIO_MASK_H_MASK_H26_Pos                             26                                                        /*!< SGPIO MASK_H: MASK_H26 Position     */
#define SGPIO_MASK_H_MASK_H26_Msk                             (0x01UL << SGPIO_MASK_H_MASK_H26_Pos)                     /*!< SGPIO MASK_H: MASK_H26 Mask         */
#define SGPIO_MASK_H_MASK_H27_Pos                             27                                                        /*!< SGPIO MASK_H: MASK_H27 Position     */
#define SGPIO_MASK_H_MASK_H27_Msk                             (0x01UL << SGPIO_MASK_H_MASK_H27_Pos)                     /*!< SGPIO MASK_H: MASK_H27 Mask         */
#define SGPIO_MASK_H_MASK_H28_Pos                             28                                                        /*!< SGPIO MASK_H: MASK_H28 Position     */
#define SGPIO_MASK_H_MASK_H28_Msk                             (0x01UL << SGPIO_MASK_H_MASK_H28_Pos)                     /*!< SGPIO MASK_H: MASK_H28 Mask         */
#define SGPIO_MASK_H_MASK_H29_Pos                             29                                                        /*!< SGPIO MASK_H: MASK_H29 Position     */
#define SGPIO_MASK_H_MASK_H29_Msk                             (0x01UL << SGPIO_MASK_H_MASK_H29_Pos)                     /*!< SGPIO MASK_H: MASK_H29 Mask         */
#define SGPIO_MASK_H_MASK_H30_Pos                             30                                                        /*!< SGPIO MASK_H: MASK_H30 Position     */
#define SGPIO_MASK_H_MASK_H30_Msk                             (0x01UL << SGPIO_MASK_H_MASK_H30_Pos)                     /*!< SGPIO MASK_H: MASK_H30 Mask         */
#define SGPIO_MASK_H_MASK_H31_Pos                             31                                                        /*!< SGPIO MASK_H: MASK_H31 Position     */
#define SGPIO_MASK_H_MASK_H31_Msk                             (0x01UL << SGPIO_MASK_H_MASK_H31_Pos)                     /*!< SGPIO MASK_H: MASK_H31 Mask         */

// --------------------------------------  SGPIO_MASK_I  ------------------------------------------
#define SGPIO_MASK_I_MASK_I0_Pos                              0                                                         /*!< SGPIO MASK_I: MASK_I0 Position      */
#define SGPIO_MASK_I_MASK_I0_Msk                              (0x01UL << SGPIO_MASK_I_MASK_I0_Pos)                      /*!< SGPIO MASK_I: MASK_I0 Mask          */
#define SGPIO_MASK_I_MASK_I1_Pos                              1                                                         /*!< SGPIO MASK_I: MASK_I1 Position      */
#define SGPIO_MASK_I_MASK_I1_Msk                              (0x01UL << SGPIO_MASK_I_MASK_I1_Pos)                      /*!< SGPIO MASK_I: MASK_I1 Mask          */
#define SGPIO_MASK_I_MASK_I2_Pos                              2                                                         /*!< SGPIO MASK_I: MASK_I2 Position      */
#define SGPIO_MASK_I_MASK_I2_Msk                              (0x01UL << SGPIO_MASK_I_MASK_I2_Pos)                      /*!< SGPIO MASK_I: MASK_I2 Mask          */
#define SGPIO_MASK_I_MASK_I3_Pos                              3                                                         /*!< SGPIO MASK_I: MASK_I3 Position      */
#define SGPIO_MASK_I_MASK_I3_Msk                              (0x01UL << SGPIO_MASK_I_MASK_I3_Pos)                      /*!< SGPIO MASK_I: MASK_I3 Mask          */
#define SGPIO_MASK_I_MASK_I4_Pos                              4                                                         /*!< SGPIO MASK_I: MASK_I4 Position      */
#define SGPIO_MASK_I_MASK_I4_Msk                              (0x01UL << SGPIO_MASK_I_MASK_I4_Pos)                      /*!< SGPIO MASK_I: MASK_I4 Mask          */
#define SGPIO_MASK_I_MASK_I5_Pos                              5                                                         /*!< SGPIO MASK_I: MASK_I5 Position      */
#define SGPIO_MASK_I_MASK_I5_Msk                              (0x01UL << SGPIO_MASK_I_MASK_I5_Pos)                      /*!< SGPIO MASK_I: MASK_I5 Mask          */
#define SGPIO_MASK_I_MASK_I6_Pos                              6                                                         /*!< SGPIO MASK_I: MASK_I6 Position      */
#define SGPIO_MASK_I_MASK_I6_Msk                              (0x01UL << SGPIO_MASK_I_MASK_I6_Pos)                      /*!< SGPIO MASK_I: MASK_I6 Mask          */
#define SGPIO_MASK_I_MASK_I7_Pos                              7                                                         /*!< SGPIO MASK_I: MASK_I7 Position      */
#define SGPIO_MASK_I_MASK_I7_Msk                              (0x01UL << SGPIO_MASK_I_MASK_I7_Pos)                      /*!< SGPIO MASK_I: MASK_I7 Mask          */
#define SGPIO_MASK_I_MASK_I8_Pos                              8                                                         /*!< SGPIO MASK_I: MASK_I8 Position      */
#define SGPIO_MASK_I_MASK_I8_Msk                              (0x01UL << SGPIO_MASK_I_MASK_I8_Pos)                      /*!< SGPIO MASK_I: MASK_I8 Mask          */
#define SGPIO_MASK_I_MASK_I9_Pos                              9                                                         /*!< SGPIO MASK_I: MASK_I9 Position      */
#define SGPIO_MASK_I_MASK_I9_Msk                              (0x01UL << SGPIO_MASK_I_MASK_I9_Pos)                      /*!< SGPIO MASK_I: MASK_I9 Mask          */
#define SGPIO_MASK_I_MASK_I10_Pos                             10                                                        /*!< SGPIO MASK_I: MASK_I10 Position     */
#define SGPIO_MASK_I_MASK_I10_Msk                             (0x01UL << SGPIO_MASK_I_MASK_I10_Pos)                     /*!< SGPIO MASK_I: MASK_I10 Mask         */
#define SGPIO_MASK_I_MASK_I11_Pos                             11                                                        /*!< SGPIO MASK_I: MASK_I11 Position     */
#define SGPIO_MASK_I_MASK_I11_Msk                             (0x01UL << SGPIO_MASK_I_MASK_I11_Pos)                     /*!< SGPIO MASK_I: MASK_I11 Mask         */
#define SGPIO_MASK_I_MASK_I12_Pos                             12                                                        /*!< SGPIO MASK_I: MASK_I12 Position     */
#define SGPIO_MASK_I_MASK_I12_Msk                             (0x01UL << SGPIO_MASK_I_MASK_I12_Pos)                     /*!< SGPIO MASK_I: MASK_I12 Mask         */
#define SGPIO_MASK_I_MASK_I13_Pos                             13                                                        /*!< SGPIO MASK_I: MASK_I13 Position     */
#define SGPIO_MASK_I_MASK_I13_Msk                             (0x01UL << SGPIO_MASK_I_MASK_I13_Pos)                     /*!< SGPIO MASK_I: MASK_I13 Mask         */
#define SGPIO_MASK_I_MASK_I14_Pos                             14                                                        /*!< SGPIO MASK_I: MASK_I14 Position     */
#define SGPIO_MASK_I_MASK_I14_Msk                             (0x01UL << SGPIO_MASK_I_MASK_I14_Pos)                     /*!< SGPIO MASK_I: MASK_I14 Mask         */
#define SGPIO_MASK_I_MASK_I15_Pos                             15                                                        /*!< SGPIO MASK_I: MASK_I15 Position     */
#define SGPIO_MASK_I_MASK_I15_Msk                             (0x01UL << SGPIO_MASK_I_MASK_I15_Pos)                     /*!< SGPIO MASK_I: MASK_I15 Mask         */
#define SGPIO_MASK_I_MASK_I16_Pos                             16                                                        /*!< SGPIO MASK_I: MASK_I16 Position     */
#define SGPIO_MASK_I_MASK_I16_Msk                             (0x01UL << SGPIO_MASK_I_MASK_I16_Pos)                     /*!< SGPIO MASK_I: MASK_I16 Mask         */
#define SGPIO_MASK_I_MASK_I17_Pos                             17                                                        /*!< SGPIO MASK_I: MASK_I17 Position     */
#define SGPIO_MASK_I_MASK_I17_Msk                             (0x01UL << SGPIO_MASK_I_MASK_I17_Pos)                     /*!< SGPIO MASK_I: MASK_I17 Mask         */
#define SGPIO_MASK_I_MASK_I18_Pos                             18                                                        /*!< SGPIO MASK_I: MASK_I18 Position     */
#define SGPIO_MASK_I_MASK_I18_Msk                             (0x01UL << SGPIO_MASK_I_MASK_I18_Pos)                     /*!< SGPIO MASK_I: MASK_I18 Mask         */
#define SGPIO_MASK_I_MASK_I19_Pos                             19                                                        /*!< SGPIO MASK_I: MASK_I19 Position     */
#define SGPIO_MASK_I_MASK_I19_Msk                             (0x01UL << SGPIO_MASK_I_MASK_I19_Pos)                     /*!< SGPIO MASK_I: MASK_I19 Mask         */
#define SGPIO_MASK_I_MASK_I20_Pos                             20                                                        /*!< SGPIO MASK_I: MASK_I20 Position     */
#define SGPIO_MASK_I_MASK_I20_Msk                             (0x01UL << SGPIO_MASK_I_MASK_I20_Pos)                     /*!< SGPIO MASK_I: MASK_I20 Mask         */
#define SGPIO_MASK_I_MASK_I21_Pos                             21                                                        /*!< SGPIO MASK_I: MASK_I21 Position     */
#define SGPIO_MASK_I_MASK_I21_Msk                             (0x01UL << SGPIO_MASK_I_MASK_I21_Pos)                     /*!< SGPIO MASK_I: MASK_I21 Mask         */
#define SGPIO_MASK_I_MASK_I22_Pos                             22                                                        /*!< SGPIO MASK_I: MASK_I22 Position     */
#define SGPIO_MASK_I_MASK_I22_Msk                             (0x01UL << SGPIO_MASK_I_MASK_I22_Pos)                     /*!< SGPIO MASK_I: MASK_I22 Mask         */
#define SGPIO_MASK_I_MASK_I23_Pos                             23                                                        /*!< SGPIO MASK_I: MASK_I23 Position     */
#define SGPIO_MASK_I_MASK_I23_Msk                             (0x01UL << SGPIO_MASK_I_MASK_I23_Pos)                     /*!< SGPIO MASK_I: MASK_I23 Mask         */
#define SGPIO_MASK_I_MASK_I24_Pos                             24                                                        /*!< SGPIO MASK_I: MASK_I24 Position     */
#define SGPIO_MASK_I_MASK_I24_Msk                             (0x01UL << SGPIO_MASK_I_MASK_I24_Pos)                     /*!< SGPIO MASK_I: MASK_I24 Mask         */
#define SGPIO_MASK_I_MASK_I25_Pos                             25                                                        /*!< SGPIO MASK_I: MASK_I25 Position     */
#define SGPIO_MASK_I_MASK_I25_Msk                             (0x01UL << SGPIO_MASK_I_MASK_I25_Pos)                     /*!< SGPIO MASK_I: MASK_I25 Mask         */
#define SGPIO_MASK_I_MASK_I26_Pos                             26                                                        /*!< SGPIO MASK_I: MASK_I26 Position     */
#define SGPIO_MASK_I_MASK_I26_Msk                             (0x01UL << SGPIO_MASK_I_MASK_I26_Pos)                     /*!< SGPIO MASK_I: MASK_I26 Mask         */
#define SGPIO_MASK_I_MASK_I27_Pos                             27                                                        /*!< SGPIO MASK_I: MASK_I27 Position     */
#define SGPIO_MASK_I_MASK_I27_Msk                             (0x01UL << SGPIO_MASK_I_MASK_I27_Pos)                     /*!< SGPIO MASK_I: MASK_I27 Mask         */
#define SGPIO_MASK_I_MASK_I28_Pos                             28                                                        /*!< SGPIO MASK_I: MASK_I28 Position     */
#define SGPIO_MASK_I_MASK_I28_Msk                             (0x01UL << SGPIO_MASK_I_MASK_I28_Pos)                     /*!< SGPIO MASK_I: MASK_I28 Mask         */
#define SGPIO_MASK_I_MASK_I29_Pos                             29                                                        /*!< SGPIO MASK_I: MASK_I29 Position     */
#define SGPIO_MASK_I_MASK_I29_Msk                             (0x01UL << SGPIO_MASK_I_MASK_I29_Pos)                     /*!< SGPIO MASK_I: MASK_I29 Mask         */
#define SGPIO_MASK_I_MASK_I30_Pos                             30                                                        /*!< SGPIO MASK_I: MASK_I30 Position     */
#define SGPIO_MASK_I_MASK_I30_Msk                             (0x01UL << SGPIO_MASK_I_MASK_I30_Pos)                     /*!< SGPIO MASK_I: MASK_I30 Mask         */
#define SGPIO_MASK_I_MASK_I31_Pos                             31                                                        /*!< SGPIO MASK_I: MASK_I31 Position     */
#define SGPIO_MASK_I_MASK_I31_Msk                             (0x01UL << SGPIO_MASK_I_MASK_I31_Pos)                     /*!< SGPIO MASK_I: MASK_I31 Mask         */

// --------------------------------------  SGPIO_MASK_P  ------------------------------------------
#define SGPIO_MASK_P_MASK_P0_Pos                              0                                                         /*!< SGPIO MASK_P: MASK_P0 Position      */
#define SGPIO_MASK_P_MASK_P0_Msk                              (0x01UL << SGPIO_MASK_P_MASK_P0_Pos)                      /*!< SGPIO MASK_P: MASK_P0 Mask          */
#define SGPIO_MASK_P_MASK_P1_Pos                              1                                                         /*!< SGPIO MASK_P: MASK_P1 Position      */
#define SGPIO_MASK_P_MASK_P1_Msk                              (0x01UL << SGPIO_MASK_P_MASK_P1_Pos)                      /*!< SGPIO MASK_P: MASK_P1 Mask          */
#define SGPIO_MASK_P_MASK_P2_Pos                              2                                                         /*!< SGPIO MASK_P: MASK_P2 Position      */
#define SGPIO_MASK_P_MASK_P2_Msk                              (0x01UL << SGPIO_MASK_P_MASK_P2_Pos)                      /*!< SGPIO MASK_P: MASK_P2 Mask          */
#define SGPIO_MASK_P_MASK_P3_Pos                              3                                                         /*!< SGPIO MASK_P: MASK_P3 Position      */
#define SGPIO_MASK_P_MASK_P3_Msk                              (0x01UL << SGPIO_MASK_P_MASK_P3_Pos)                      /*!< SGPIO MASK_P: MASK_P3 Mask          */
#define SGPIO_MASK_P_MASK_P4_Pos                              4                                                         /*!< SGPIO MASK_P: MASK_P4 Position      */
#define SGPIO_MASK_P_MASK_P4_Msk                              (0x01UL << SGPIO_MASK_P_MASK_P4_Pos)                      /*!< SGPIO MASK_P: MASK_P4 Mask          */
#define SGPIO_MASK_P_MASK_P5_Pos                              5                                                         /*!< SGPIO MASK_P: MASK_P5 Position      */
#define SGPIO_MASK_P_MASK_P5_Msk                              (0x01UL << SGPIO_MASK_P_MASK_P5_Pos)                      /*!< SGPIO MASK_P: MASK_P5 Mask          */
#define SGPIO_MASK_P_MASK_P6_Pos                              6                                                         /*!< SGPIO MASK_P: MASK_P6 Position      */
#define SGPIO_MASK_P_MASK_P6_Msk                              (0x01UL << SGPIO_MASK_P_MASK_P6_Pos)                      /*!< SGPIO MASK_P: MASK_P6 Mask          */
#define SGPIO_MASK_P_MASK_P7_Pos                              7                                                         /*!< SGPIO MASK_P: MASK_P7 Position      */
#define SGPIO_MASK_P_MASK_P7_Msk                              (0x01UL << SGPIO_MASK_P_MASK_P7_Pos)                      /*!< SGPIO MASK_P: MASK_P7 Mask          */
#define SGPIO_MASK_P_MASK_P8_Pos                              8                                                         /*!< SGPIO MASK_P: MASK_P8 Position      */
#define SGPIO_MASK_P_MASK_P8_Msk                              (0x01UL << SGPIO_MASK_P_MASK_P8_Pos)                      /*!< SGPIO MASK_P: MASK_P8 Mask          */
#define SGPIO_MASK_P_MASK_P9_Pos                              9                                                         /*!< SGPIO MASK_P: MASK_P9 Position      */
#define SGPIO_MASK_P_MASK_P9_Msk                              (0x01UL << SGPIO_MASK_P_MASK_P9_Pos)                      /*!< SGPIO MASK_P: MASK_P9 Mask          */
#define SGPIO_MASK_P_MASK_P10_Pos                             10                                                        /*!< SGPIO MASK_P: MASK_P10 Position     */
#define SGPIO_MASK_P_MASK_P10_Msk                             (0x01UL << SGPIO_MASK_P_MASK_P10_Pos)                     /*!< SGPIO MASK_P: MASK_P10 Mask         */
#define SGPIO_MASK_P_MASK_P11_Pos                             11                                                        /*!< SGPIO MASK_P: MASK_P11 Position     */
#define SGPIO_MASK_P_MASK_P11_Msk                             (0x01UL << SGPIO_MASK_P_MASK_P11_Pos)                     /*!< SGPIO MASK_P: MASK_P11 Mask         */
#define SGPIO_MASK_P_MASK_P12_Pos                             12                                                        /*!< SGPIO MASK_P: MASK_P12 Position     */
#define SGPIO_MASK_P_MASK_P12_Msk                             (0x01UL << SGPIO_MASK_P_MASK_P12_Pos)                     /*!< SGPIO MASK_P: MASK_P12 Mask         */
#define SGPIO_MASK_P_MASK_P13_Pos                             13                                                        /*!< SGPIO MASK_P: MASK_P13 Position     */
#define SGPIO_MASK_P_MASK_P13_Msk                             (0x01UL << SGPIO_MASK_P_MASK_P13_Pos)                     /*!< SGPIO MASK_P: MASK_P13 Mask         */
#define SGPIO_MASK_P_MASK_P14_Pos                             14                                                        /*!< SGPIO MASK_P: MASK_P14 Position     */
#define SGPIO_MASK_P_MASK_P14_Msk                             (0x01UL << SGPIO_MASK_P_MASK_P14_Pos)                     /*!< SGPIO MASK_P: MASK_P14 Mask         */
#define SGPIO_MASK_P_MASK_P15_Pos                             15                                                        /*!< SGPIO MASK_P: MASK_P15 Position     */
#define SGPIO_MASK_P_MASK_P15_Msk                             (0x01UL << SGPIO_MASK_P_MASK_P15_Pos)                     /*!< SGPIO MASK_P: MASK_P15 Mask         */
#define SGPIO_MASK_P_MASK_P16_Pos                             16                                                        /*!< SGPIO MASK_P: MASK_P16 Position     */
#define SGPIO_MASK_P_MASK_P16_Msk                             (0x01UL << SGPIO_MASK_P_MASK_P16_Pos)                     /*!< SGPIO MASK_P: MASK_P16 Mask         */
#define SGPIO_MASK_P_MASK_P17_Pos                             17                                                        /*!< SGPIO MASK_P: MASK_P17 Position     */
#define SGPIO_MASK_P_MASK_P17_Msk                             (0x01UL << SGPIO_MASK_P_MASK_P17_Pos)                     /*!< SGPIO MASK_P: MASK_P17 Mask         */
#define SGPIO_MASK_P_MASK_P18_Pos                             18                                                        /*!< SGPIO MASK_P: MASK_P18 Position     */
#define SGPIO_MASK_P_MASK_P18_Msk                             (0x01UL << SGPIO_MASK_P_MASK_P18_Pos)                     /*!< SGPIO MASK_P: MASK_P18 Mask         */
#define SGPIO_MASK_P_MASK_P19_Pos                             19                                                        /*!< SGPIO MASK_P: MASK_P19 Position     */
#define SGPIO_MASK_P_MASK_P19_Msk                             (0x01UL << SGPIO_MASK_P_MASK_P19_Pos)                     /*!< SGPIO MASK_P: MASK_P19 Mask         */
#define SGPIO_MASK_P_MASK_P20_Pos                             20                                                        /*!< SGPIO MASK_P: MASK_P20 Position     */
#define SGPIO_MASK_P_MASK_P20_Msk                             (0x01UL << SGPIO_MASK_P_MASK_P20_Pos)                     /*!< SGPIO MASK_P: MASK_P20 Mask         */
#define SGPIO_MASK_P_MASK_P21_Pos                             21                                                        /*!< SGPIO MASK_P: MASK_P21 Position     */
#define SGPIO_MASK_P_MASK_P21_Msk                             (0x01UL << SGPIO_MASK_P_MASK_P21_Pos)                     /*!< SGPIO MASK_P: MASK_P21 Mask         */
#define SGPIO_MASK_P_MASK_P22_Pos                             22                                                        /*!< SGPIO MASK_P: MASK_P22 Position     */
#define SGPIO_MASK_P_MASK_P22_Msk                             (0x01UL << SGPIO_MASK_P_MASK_P22_Pos)                     /*!< SGPIO MASK_P: MASK_P22 Mask         */
#define SGPIO_MASK_P_MASK_P23_Pos                             23                                                        /*!< SGPIO MASK_P: MASK_P23 Position     */
#define SGPIO_MASK_P_MASK_P23_Msk                             (0x01UL << SGPIO_MASK_P_MASK_P23_Pos)                     /*!< SGPIO MASK_P: MASK_P23 Mask         */
#define SGPIO_MASK_P_MASK_P24_Pos                             24                                                        /*!< SGPIO MASK_P: MASK_P24 Position     */
#define SGPIO_MASK_P_MASK_P24_Msk                             (0x01UL << SGPIO_MASK_P_MASK_P24_Pos)                     /*!< SGPIO MASK_P: MASK_P24 Mask         */
#define SGPIO_MASK_P_MASK_P25_Pos                             25                                                        /*!< SGPIO MASK_P: MASK_P25 Position     */
#define SGPIO_MASK_P_MASK_P25_Msk                             (0x01UL << SGPIO_MASK_P_MASK_P25_Pos)                     /*!< SGPIO MASK_P: MASK_P25 Mask         */
#define SGPIO_MASK_P_MASK_P26_Pos                             26                                                        /*!< SGPIO MASK_P: MASK_P26 Position     */
#define SGPIO_MASK_P_MASK_P26_Msk                             (0x01UL << SGPIO_MASK_P_MASK_P26_Pos)                     /*!< SGPIO MASK_P: MASK_P26 Mask         */
#define SGPIO_MASK_P_MASK_P27_Pos                             27                                                        /*!< SGPIO MASK_P: MASK_P27 Position     */
#define SGPIO_MASK_P_MASK_P27_Msk                             (0x01UL << SGPIO_MASK_P_MASK_P27_Pos)                     /*!< SGPIO MASK_P: MASK_P27 Mask         */
#define SGPIO_MASK_P_MASK_P28_Pos                             28                                                        /*!< SGPIO MASK_P: MASK_P28 Position     */
#define SGPIO_MASK_P_MASK_P28_Msk                             (0x01UL << SGPIO_MASK_P_MASK_P28_Pos)                     /*!< SGPIO MASK_P: MASK_P28 Mask         */
#define SGPIO_MASK_P_MASK_P29_Pos                             29                                                        /*!< SGPIO MASK_P: MASK_P29 Position     */
#define SGPIO_MASK_P_MASK_P29_Msk                             (0x01UL << SGPIO_MASK_P_MASK_P29_Pos)                     /*!< SGPIO MASK_P: MASK_P29 Mask         */
#define SGPIO_MASK_P_MASK_P30_Pos                             30                                                        /*!< SGPIO MASK_P: MASK_P30 Position     */
#define SGPIO_MASK_P_MASK_P30_Msk                             (0x01UL << SGPIO_MASK_P_MASK_P30_Pos)                     /*!< SGPIO MASK_P: MASK_P30 Mask         */
#define SGPIO_MASK_P_MASK_P31_Pos                             31                                                        /*!< SGPIO MASK_P: MASK_P31 Position     */
#define SGPIO_MASK_P_MASK_P31_Msk                             (0x01UL << SGPIO_MASK_P_MASK_P31_Pos)                     /*!< SGPIO MASK_P: MASK_P31 Mask         */

// ------------------------------------  SGPIO_GPIO_INREG  ----------------------------------------
#define SGPIO_GPIO_INREG_GPIO_IN0_Pos                         0                                                         /*!< SGPIO GPIO_INREG: GPIO_IN0 Position */
#define SGPIO_GPIO_INREG_GPIO_IN0_Msk                         (0x01UL << SGPIO_GPIO_INREG_GPIO_IN0_Pos)                 /*!< SGPIO GPIO_INREG: GPIO_IN0 Mask     */
#define SGPIO_GPIO_INREG_GPIO_IN1_Pos                         1                                                         /*!< SGPIO GPIO_INREG: GPIO_IN1 Position */
#define SGPIO_GPIO_INREG_GPIO_IN1_Msk                         (0x01UL << SGPIO_GPIO_INREG_GPIO_IN1_Pos)                 /*!< SGPIO GPIO_INREG: GPIO_IN1 Mask     */
#define SGPIO_GPIO_INREG_GPIO_IN2_Pos                         2                                                         /*!< SGPIO GPIO_INREG: GPIO_IN2 Position */
#define SGPIO_GPIO_INREG_GPIO_IN2_Msk                         (0x01UL << SGPIO_GPIO_INREG_GPIO_IN2_Pos)                 /*!< SGPIO GPIO_INREG: GPIO_IN2 Mask     */
#define SGPIO_GPIO_INREG_GPIO_IN3_Pos                         3                                                         /*!< SGPIO GPIO_INREG: GPIO_IN3 Position */
#define SGPIO_GPIO_INREG_GPIO_IN3_Msk                         (0x01UL << SGPIO_GPIO_INREG_GPIO_IN3_Pos)                 /*!< SGPIO GPIO_INREG: GPIO_IN3 Mask     */
#define SGPIO_GPIO_INREG_GPIO_IN4_Pos                         4                                                         /*!< SGPIO GPIO_INREG: GPIO_IN4 Position */
#define SGPIO_GPIO_INREG_GPIO_IN4_Msk                         (0x01UL << SGPIO_GPIO_INREG_GPIO_IN4_Pos)                 /*!< SGPIO GPIO_INREG: GPIO_IN4 Mask     */
#define SGPIO_GPIO_INREG_GPIO_IN5_Pos                         5                                                         /*!< SGPIO GPIO_INREG: GPIO_IN5 Position */
#define SGPIO_GPIO_INREG_GPIO_IN5_Msk                         (0x01UL << SGPIO_GPIO_INREG_GPIO_IN5_Pos)                 /*!< SGPIO GPIO_INREG: GPIO_IN5 Mask     */
#define SGPIO_GPIO_INREG_GPIO_IN6_Pos                         6                                                         /*!< SGPIO GPIO_INREG: GPIO_IN6 Position */
#define SGPIO_GPIO_INREG_GPIO_IN6_Msk                         (0x01UL << SGPIO_GPIO_INREG_GPIO_IN6_Pos)                 /*!< SGPIO GPIO_INREG: GPIO_IN6 Mask     */
#define SGPIO_GPIO_INREG_GPIO_IN7_Pos                         7                                                         /*!< SGPIO GPIO_INREG: GPIO_IN7 Position */
#define SGPIO_GPIO_INREG_GPIO_IN7_Msk                         (0x01UL << SGPIO_GPIO_INREG_GPIO_IN7_Pos)                 /*!< SGPIO GPIO_INREG: GPIO_IN7 Mask     */
#define SGPIO_GPIO_INREG_GPIO_IN8_Pos                         8                                                         /*!< SGPIO GPIO_INREG: GPIO_IN8 Position */
#define SGPIO_GPIO_INREG_GPIO_IN8_Msk                         (0x01UL << SGPIO_GPIO_INREG_GPIO_IN8_Pos)                 /*!< SGPIO GPIO_INREG: GPIO_IN8 Mask     */
#define SGPIO_GPIO_INREG_GPIO_IN9_Pos                         9                                                         /*!< SGPIO GPIO_INREG: GPIO_IN9 Position */
#define SGPIO_GPIO_INREG_GPIO_IN9_Msk                         (0x01UL << SGPIO_GPIO_INREG_GPIO_IN9_Pos)                 /*!< SGPIO GPIO_INREG: GPIO_IN9 Mask     */
#define SGPIO_GPIO_INREG_GPIO_IN10_Pos                        10                                                        /*!< SGPIO GPIO_INREG: GPIO_IN10 Position */
#define SGPIO_GPIO_INREG_GPIO_IN10_Msk                        (0x01UL << SGPIO_GPIO_INREG_GPIO_IN10_Pos)                /*!< SGPIO GPIO_INREG: GPIO_IN10 Mask    */
#define SGPIO_GPIO_INREG_GPIO_IN11_Pos                        11                                                        /*!< SGPIO GPIO_INREG: GPIO_IN11 Position */
#define SGPIO_GPIO_INREG_GPIO_IN11_Msk                        (0x01UL << SGPIO_GPIO_INREG_GPIO_IN11_Pos)                /*!< SGPIO GPIO_INREG: GPIO_IN11 Mask    */
#define SGPIO_GPIO_INREG_GPIO_IN12_Pos                        12                                                        /*!< SGPIO GPIO_INREG: GPIO_IN12 Position */
#define SGPIO_GPIO_INREG_GPIO_IN12_Msk                        (0x01UL << SGPIO_GPIO_INREG_GPIO_IN12_Pos)                /*!< SGPIO GPIO_INREG: GPIO_IN12 Mask    */
#define SGPIO_GPIO_INREG_GPIO_IN13_Pos                        13                                                        /*!< SGPIO GPIO_INREG: GPIO_IN13 Position */
#define SGPIO_GPIO_INREG_GPIO_IN13_Msk                        (0x01UL << SGPIO_GPIO_INREG_GPIO_IN13_Pos)                /*!< SGPIO GPIO_INREG: GPIO_IN13 Mask    */
#define SGPIO_GPIO_INREG_GPIO_IN14_Pos                        14                                                        /*!< SGPIO GPIO_INREG: GPIO_IN14 Position */
#define SGPIO_GPIO_INREG_GPIO_IN14_Msk                        (0x01UL << SGPIO_GPIO_INREG_GPIO_IN14_Pos)                /*!< SGPIO GPIO_INREG: GPIO_IN14 Mask    */
#define SGPIO_GPIO_INREG_GPIO_IN15_Pos                        15                                                        /*!< SGPIO GPIO_INREG: GPIO_IN15 Position */
#define SGPIO_GPIO_INREG_GPIO_IN15_Msk                        (0x01UL << SGPIO_GPIO_INREG_GPIO_IN15_Pos)                /*!< SGPIO GPIO_INREG: GPIO_IN15 Mask    */

// ------------------------------------  SGPIO_GPIO_OUTREG  ---------------------------------------
#define SGPIO_GPIO_OUTREG_GPIO_OUT0_Pos                       0                                                         /*!< SGPIO GPIO_OUTREG: GPIO_OUT0 Position */
#define SGPIO_GPIO_OUTREG_GPIO_OUT0_Msk                       (0x01UL << SGPIO_GPIO_OUTREG_GPIO_OUT0_Pos)               /*!< SGPIO GPIO_OUTREG: GPIO_OUT0 Mask   */
#define SGPIO_GPIO_OUTREG_GPIO_OUT1_Pos                       1                                                         /*!< SGPIO GPIO_OUTREG: GPIO_OUT1 Position */
#define SGPIO_GPIO_OUTREG_GPIO_OUT1_Msk                       (0x01UL << SGPIO_GPIO_OUTREG_GPIO_OUT1_Pos)               /*!< SGPIO GPIO_OUTREG: GPIO_OUT1 Mask   */
#define SGPIO_GPIO_OUTREG_GPIO_OUT2_Pos                       2                                                         /*!< SGPIO GPIO_OUTREG: GPIO_OUT2 Position */
#define SGPIO_GPIO_OUTREG_GPIO_OUT2_Msk                       (0x01UL << SGPIO_GPIO_OUTREG_GPIO_OUT2_Pos)               /*!< SGPIO GPIO_OUTREG: GPIO_OUT2 Mask   */
#define SGPIO_GPIO_OUTREG_GPIO_OUT3_Pos                       3                                                         /*!< SGPIO GPIO_OUTREG: GPIO_OUT3 Position */
#define SGPIO_GPIO_OUTREG_GPIO_OUT3_Msk                       (0x01UL << SGPIO_GPIO_OUTREG_GPIO_OUT3_Pos)               /*!< SGPIO GPIO_OUTREG: GPIO_OUT3 Mask   */
#define SGPIO_GPIO_OUTREG_GPIO_OUT4_Pos                       4                                                         /*!< SGPIO GPIO_OUTREG: GPIO_OUT4 Position */
#define SGPIO_GPIO_OUTREG_GPIO_OUT4_Msk                       (0x01UL << SGPIO_GPIO_OUTREG_GPIO_OUT4_Pos)               /*!< SGPIO GPIO_OUTREG: GPIO_OUT4 Mask   */
#define SGPIO_GPIO_OUTREG_GPIO_OUT5_Pos                       5                                                         /*!< SGPIO GPIO_OUTREG: GPIO_OUT5 Position */
#define SGPIO_GPIO_OUTREG_GPIO_OUT5_Msk                       (0x01UL << SGPIO_GPIO_OUTREG_GPIO_OUT5_Pos)               /*!< SGPIO GPIO_OUTREG: GPIO_OUT5 Mask   */
#define SGPIO_GPIO_OUTREG_GPIO_OUT6_Pos                       6                                                         /*!< SGPIO GPIO_OUTREG: GPIO_OUT6 Position */
#define SGPIO_GPIO_OUTREG_GPIO_OUT6_Msk                       (0x01UL << SGPIO_GPIO_OUTREG_GPIO_OUT6_Pos)               /*!< SGPIO GPIO_OUTREG: GPIO_OUT6 Mask   */
#define SGPIO_GPIO_OUTREG_GPIO_OUT7_Pos                       7                                                         /*!< SGPIO GPIO_OUTREG: GPIO_OUT7 Position */
#define SGPIO_GPIO_OUTREG_GPIO_OUT7_Msk                       (0x01UL << SGPIO_GPIO_OUTREG_GPIO_OUT7_Pos)               /*!< SGPIO GPIO_OUTREG: GPIO_OUT7 Mask   */
#define SGPIO_GPIO_OUTREG_GPIO_OUT8_Pos                       8                                                         /*!< SGPIO GPIO_OUTREG: GPIO_OUT8 Position */
#define SGPIO_GPIO_OUTREG_GPIO_OUT8_Msk                       (0x01UL << SGPIO_GPIO_OUTREG_GPIO_OUT8_Pos)               /*!< SGPIO GPIO_OUTREG: GPIO_OUT8 Mask   */
#define SGPIO_GPIO_OUTREG_GPIO_OUT9_Pos                       9                                                         /*!< SGPIO GPIO_OUTREG: GPIO_OUT9 Position */
#define SGPIO_GPIO_OUTREG_GPIO_OUT9_Msk                       (0x01UL << SGPIO_GPIO_OUTREG_GPIO_OUT9_Pos)               /*!< SGPIO GPIO_OUTREG: GPIO_OUT9 Mask   */
#define SGPIO_GPIO_OUTREG_GPIO_OUT10_Pos                      10                                                        /*!< SGPIO GPIO_OUTREG: GPIO_OUT10 Position */
#define SGPIO_GPIO_OUTREG_GPIO_OUT10_Msk                      (0x01UL << SGPIO_GPIO_OUTREG_GPIO_OUT10_Pos)              /*!< SGPIO GPIO_OUTREG: GPIO_OUT10 Mask  */
#define SGPIO_GPIO_OUTREG_GPIO_OUT11_Pos                      11                                                        /*!< SGPIO GPIO_OUTREG: GPIO_OUT11 Position */
#define SGPIO_GPIO_OUTREG_GPIO_OUT11_Msk                      (0x01UL << SGPIO_GPIO_OUTREG_GPIO_OUT11_Pos)              /*!< SGPIO GPIO_OUTREG: GPIO_OUT11 Mask  */
#define SGPIO_GPIO_OUTREG_GPIO_OUT12_Pos                      12                                                        /*!< SGPIO GPIO_OUTREG: GPIO_OUT12 Position */
#define SGPIO_GPIO_OUTREG_GPIO_OUT12_Msk                      (0x01UL << SGPIO_GPIO_OUTREG_GPIO_OUT12_Pos)              /*!< SGPIO GPIO_OUTREG: GPIO_OUT12 Mask  */
#define SGPIO_GPIO_OUTREG_GPIO_OUT13_Pos                      13                                                        /*!< SGPIO GPIO_OUTREG: GPIO_OUT13 Position */
#define SGPIO_GPIO_OUTREG_GPIO_OUT13_Msk                      (0x01UL << SGPIO_GPIO_OUTREG_GPIO_OUT13_Pos)              /*!< SGPIO GPIO_OUTREG: GPIO_OUT13 Mask  */
#define SGPIO_GPIO_OUTREG_GPIO_OUT14_Pos                      14                                                        /*!< SGPIO GPIO_OUTREG: GPIO_OUT14 Position */
#define SGPIO_GPIO_OUTREG_GPIO_OUT14_Msk                      (0x01UL << SGPIO_GPIO_OUTREG_GPIO_OUT14_Pos)              /*!< SGPIO GPIO_OUTREG: GPIO_OUT14 Mask  */
#define SGPIO_GPIO_OUTREG_GPIO_OUT15_Pos                      15                                                        /*!< SGPIO GPIO_OUTREG: GPIO_OUT15 Position */
#define SGPIO_GPIO_OUTREG_GPIO_OUT15_Msk                      (0x01UL << SGPIO_GPIO_OUTREG_GPIO_OUT15_Pos)              /*!< SGPIO GPIO_OUTREG: GPIO_OUT15 Mask  */

// ------------------------------------  SGPIO_GPIO_OENREG  ---------------------------------------
#define SGPIO_GPIO_OENREG_GPIO_OE0_Pos                        0                                                         /*!< SGPIO GPIO_OENREG: GPIO_OE0 Position */
#define SGPIO_GPIO_OENREG_GPIO_OE0_Msk                        (0x01UL << SGPIO_GPIO_OENREG_GPIO_OE0_Pos)                /*!< SGPIO GPIO_OENREG: GPIO_OE0 Mask    */
#define SGPIO_GPIO_OENREG_GPIO_OE1_Pos                        1                                                         /*!< SGPIO GPIO_OENREG: GPIO_OE1 Position */
#define SGPIO_GPIO_OENREG_GPIO_OE1_Msk                        (0x01UL << SGPIO_GPIO_OENREG_GPIO_OE1_Pos)                /*!< SGPIO GPIO_OENREG: GPIO_OE1 Mask    */
#define SGPIO_GPIO_OENREG_GPIO_OE2_Pos                        2                                                         /*!< SGPIO GPIO_OENREG: GPIO_OE2 Position */
#define SGPIO_GPIO_OENREG_GPIO_OE2_Msk                        (0x01UL << SGPIO_GPIO_OENREG_GPIO_OE2_Pos)                /*!< SGPIO GPIO_OENREG: GPIO_OE2 Mask    */
#define SGPIO_GPIO_OENREG_GPIO_OE3_Pos                        3                                                         /*!< SGPIO GPIO_OENREG: GPIO_OE3 Position */
#define SGPIO_GPIO_OENREG_GPIO_OE3_Msk                        (0x01UL << SGPIO_GPIO_OENREG_GPIO_OE3_Pos)                /*!< SGPIO GPIO_OENREG: GPIO_OE3 Mask    */
#define SGPIO_GPIO_OENREG_GPIO_OE4_Pos                        4                                                         /*!< SGPIO GPIO_OENREG: GPIO_OE4 Position */
#define SGPIO_GPIO_OENREG_GPIO_OE4_Msk                        (0x01UL << SGPIO_GPIO_OENREG_GPIO_OE4_Pos)                /*!< SGPIO GPIO_OENREG: GPIO_OE4 Mask    */
#define SGPIO_GPIO_OENREG_GPIO_OE5_Pos                        5                                                         /*!< SGPIO GPIO_OENREG: GPIO_OE5 Position */
#define SGPIO_GPIO_OENREG_GPIO_OE5_Msk                        (0x01UL << SGPIO_GPIO_OENREG_GPIO_OE5_Pos)                /*!< SGPIO GPIO_OENREG: GPIO_OE5 Mask    */
#define SGPIO_GPIO_OENREG_GPIO_OE6_Pos                        6                                                         /*!< SGPIO GPIO_OENREG: GPIO_OE6 Position */
#define SGPIO_GPIO_OENREG_GPIO_OE6_Msk                        (0x01UL << SGPIO_GPIO_OENREG_GPIO_OE6_Pos)                /*!< SGPIO GPIO_OENREG: GPIO_OE6 Mask    */
#define SGPIO_GPIO_OENREG_GPIO_OE7_Pos                        7                                                         /*!< SGPIO GPIO_OENREG: GPIO_OE7 Position */
#define SGPIO_GPIO_OENREG_GPIO_OE7_Msk                        (0x01UL << SGPIO_GPIO_OENREG_GPIO_OE7_Pos)                /*!< SGPIO GPIO_OENREG: GPIO_OE7 Mask    */
#define SGPIO_GPIO_OENREG_GPIO_OE8_Pos                        8                                                         /*!< SGPIO GPIO_OENREG: GPIO_OE8 Position */
#define SGPIO_GPIO_OENREG_GPIO_OE8_Msk                        (0x01UL << SGPIO_GPIO_OENREG_GPIO_OE8_Pos)                /*!< SGPIO GPIO_OENREG: GPIO_OE8 Mask    */
#define SGPIO_GPIO_OENREG_GPIO_OE9_Pos                        9                                                         /*!< SGPIO GPIO_OENREG: GPIO_OE9 Position */
#define SGPIO_GPIO_OENREG_GPIO_OE9_Msk                        (0x01UL << SGPIO_GPIO_OENREG_GPIO_OE9_Pos)                /*!< SGPIO GPIO_OENREG: GPIO_OE9 Mask    */
#define SGPIO_GPIO_OENREG_GPIO_OE10_Pos                       10                                                        /*!< SGPIO GPIO_OENREG: GPIO_OE10 Position */
#define SGPIO_GPIO_OENREG_GPIO_OE10_Msk                       (0x01UL << SGPIO_GPIO_OENREG_GPIO_OE10_Pos)               /*!< SGPIO GPIO_OENREG: GPIO_OE10 Mask   */
#define SGPIO_GPIO_OENREG_GPIO_OE11_Pos                       11                                                        /*!< SGPIO GPIO_OENREG: GPIO_OE11 Position */
#define SGPIO_GPIO_OENREG_GPIO_OE11_Msk                       (0x01UL << SGPIO_GPIO_OENREG_GPIO_OE11_Pos)               /*!< SGPIO GPIO_OENREG: GPIO_OE11 Mask   */
#define SGPIO_GPIO_OENREG_GPIO_OE12_Pos                       12                                                        /*!< SGPIO GPIO_OENREG: GPIO_OE12 Position */
#define SGPIO_GPIO_OENREG_GPIO_OE12_Msk                       (0x01UL << SGPIO_GPIO_OENREG_GPIO_OE12_Pos)               /*!< SGPIO GPIO_OENREG: GPIO_OE12 Mask   */
#define SGPIO_GPIO_OENREG_GPIO_OE13_Pos                       13                                                        /*!< SGPIO GPIO_OENREG: GPIO_OE13 Position */
#define SGPIO_GPIO_OENREG_GPIO_OE13_Msk                       (0x01UL << SGPIO_GPIO_OENREG_GPIO_OE13_Pos)               /*!< SGPIO GPIO_OENREG: GPIO_OE13 Mask   */
#define SGPIO_GPIO_OENREG_GPIO_OE14_Pos                       14                                                        /*!< SGPIO GPIO_OENREG: GPIO_OE14 Position */
#define SGPIO_GPIO_OENREG_GPIO_OE14_Msk                       (0x01UL << SGPIO_GPIO_OENREG_GPIO_OE14_Pos)               /*!< SGPIO GPIO_OENREG: GPIO_OE14 Mask   */
#define SGPIO_GPIO_OENREG_GPIO_OE15_Pos                       15                                                        /*!< SGPIO GPIO_OENREG: GPIO_OE15 Position */
#define SGPIO_GPIO_OENREG_GPIO_OE15_Msk                       (0x01UL << SGPIO_GPIO_OENREG_GPIO_OE15_Pos)               /*!< SGPIO GPIO_OENREG: GPIO_OE15 Mask   */

// -----------------------------------  SGPIO_CTRL_ENABLED  ---------------------------------------
#define SGPIO_CTRL_ENABLED_CTRL_ENABLED0_Pos                  0                                                         /*!< SGPIO CTRL_ENABLED: CTRL_ENABLED0 Position */
#define SGPIO_CTRL_ENABLED_CTRL_ENABLED0_Msk                  (0x01UL << SGPIO_CTRL_ENABLED_CTRL_ENABLED0_Pos)          /*!< SGPIO CTRL_ENABLED: CTRL_ENABLED0 Mask */
#define SGPIO_CTRL_ENABLED_CTRL_ENABLED1_Pos                  1                                                         /*!< SGPIO CTRL_ENABLED: CTRL_ENABLED1 Position */
#define SGPIO_CTRL_ENABLED_CTRL_ENABLED1_Msk                  (0x01UL << SGPIO_CTRL_ENABLED_CTRL_ENABLED1_Pos)          /*!< SGPIO CTRL_ENABLED: CTRL_ENABLED1 Mask */
#define SGPIO_CTRL_ENABLED_CTRL_ENABLED2_Pos                  2                                                         /*!< SGPIO CTRL_ENABLED: CTRL_ENABLED2 Position */
#define SGPIO_CTRL_ENABLED_CTRL_ENABLED2_Msk                  (0x01UL << SGPIO_CTRL_ENABLED_CTRL_ENABLED2_Pos)          /*!< SGPIO CTRL_ENABLED: CTRL_ENABLED2 Mask */
#define SGPIO_CTRL_ENABLED_CTRL_ENABLED3_Pos                  3                                                         /*!< SGPIO CTRL_ENABLED: CTRL_ENABLED3 Position */
#define SGPIO_CTRL_ENABLED_CTRL_ENABLED3_Msk                  (0x01UL << SGPIO_CTRL_ENABLED_CTRL_ENABLED3_Pos)          /*!< SGPIO CTRL_ENABLED: CTRL_ENABLED3 Mask */
#define SGPIO_CTRL_ENABLED_CTRL_ENABLED4_Pos                  4                                                         /*!< SGPIO CTRL_ENABLED: CTRL_ENABLED4 Position */
#define SGPIO_CTRL_ENABLED_CTRL_ENABLED4_Msk                  (0x01UL << SGPIO_CTRL_ENABLED_CTRL_ENABLED4_Pos)          /*!< SGPIO CTRL_ENABLED: CTRL_ENABLED4 Mask */
#define SGPIO_CTRL_ENABLED_CTRL_ENABLED5_Pos                  5                                                         /*!< SGPIO CTRL_ENABLED: CTRL_ENABLED5 Position */
#define SGPIO_CTRL_ENABLED_CTRL_ENABLED5_Msk                  (0x01UL << SGPIO_CTRL_ENABLED_CTRL_ENABLED5_Pos)          /*!< SGPIO CTRL_ENABLED: CTRL_ENABLED5 Mask */
#define SGPIO_CTRL_ENABLED_CTRL_ENABLED6_Pos                  6                                                         /*!< SGPIO CTRL_ENABLED: CTRL_ENABLED6 Position */
#define SGPIO_CTRL_ENABLED_CTRL_ENABLED6_Msk                  (0x01UL << SGPIO_CTRL_ENABLED_CTRL_ENABLED6_Pos)          /*!< SGPIO CTRL_ENABLED: CTRL_ENABLED6 Mask */
#define SGPIO_CTRL_ENABLED_CTRL_ENABLED7_Pos                  7                                                         /*!< SGPIO CTRL_ENABLED: CTRL_ENABLED7 Position */
#define SGPIO_CTRL_ENABLED_CTRL_ENABLED7_Msk                  (0x01UL << SGPIO_CTRL_ENABLED_CTRL_ENABLED7_Pos)          /*!< SGPIO CTRL_ENABLED: CTRL_ENABLED7 Mask */
#define SGPIO_CTRL_ENABLED_CTRL_ENABLED8_Pos                  8                                                         /*!< SGPIO CTRL_ENABLED: CTRL_ENABLED8 Position */
#define SGPIO_CTRL_ENABLED_CTRL_ENABLED8_Msk                  (0x01UL << SGPIO_CTRL_ENABLED_CTRL_ENABLED8_Pos)          /*!< SGPIO CTRL_ENABLED: CTRL_ENABLED8 Mask */
#define SGPIO_CTRL_ENABLED_CTRL_ENABLED9_Pos                  9                                                         /*!< SGPIO CTRL_ENABLED: CTRL_ENABLED9 Position */
#define SGPIO_CTRL_ENABLED_CTRL_ENABLED9_Msk                  (0x01UL << SGPIO_CTRL_ENABLED_CTRL_ENABLED9_Pos)          /*!< SGPIO CTRL_ENABLED: CTRL_ENABLED9 Mask */
#define SGPIO_CTRL_ENABLED_CTRL_ENABLED10_Pos                 10                                                        /*!< SGPIO CTRL_ENABLED: CTRL_ENABLED10 Position */
#define SGPIO_CTRL_ENABLED_CTRL_ENABLED10_Msk                 (0x01UL << SGPIO_CTRL_ENABLED_CTRL_ENABLED10_Pos)         /*!< SGPIO CTRL_ENABLED: CTRL_ENABLED10 Mask */
#define SGPIO_CTRL_ENABLED_CTRL_ENABLED11_Pos                 11                                                        /*!< SGPIO CTRL_ENABLED: CTRL_ENABLED11 Position */
#define SGPIO_CTRL_ENABLED_CTRL_ENABLED11_Msk                 (0x01UL << SGPIO_CTRL_ENABLED_CTRL_ENABLED11_Pos)         /*!< SGPIO CTRL_ENABLED: CTRL_ENABLED11 Mask */
#define SGPIO_CTRL_ENABLED_CTRL_ENABLED12_Pos                 12                                                        /*!< SGPIO CTRL_ENABLED: CTRL_ENABLED12 Position */
#define SGPIO_CTRL_ENABLED_CTRL_ENABLED12_Msk                 (0x01UL << SGPIO_CTRL_ENABLED_CTRL_ENABLED12_Pos)         /*!< SGPIO CTRL_ENABLED: CTRL_ENABLED12 Mask */
#define SGPIO_CTRL_ENABLED_CTRL_ENABLED13_Pos                 13                                                        /*!< SGPIO CTRL_ENABLED: CTRL_ENABLED13 Position */
#define SGPIO_CTRL_ENABLED_CTRL_ENABLED13_Msk                 (0x01UL << SGPIO_CTRL_ENABLED_CTRL_ENABLED13_Pos)         /*!< SGPIO CTRL_ENABLED: CTRL_ENABLED13 Mask */
#define SGPIO_CTRL_ENABLED_CTRL_ENABLED14_Pos                 14                                                        /*!< SGPIO CTRL_ENABLED: CTRL_ENABLED14 Position */
#define SGPIO_CTRL_ENABLED_CTRL_ENABLED14_Msk                 (0x01UL << SGPIO_CTRL_ENABLED_CTRL_ENABLED14_Pos)         /*!< SGPIO CTRL_ENABLED: CTRL_ENABLED14 Mask */
#define SGPIO_CTRL_ENABLED_CTRL_ENABLED15_Pos                 15                                                        /*!< SGPIO CTRL_ENABLED: CTRL_ENABLED15 Position */
#define SGPIO_CTRL_ENABLED_CTRL_ENABLED15_Msk                 (0x01UL << SGPIO_CTRL_ENABLED_CTRL_ENABLED15_Pos)         /*!< SGPIO CTRL_ENABLED: CTRL_ENABLED15 Mask */

// -----------------------------------  SGPIO_CTRL_DISABLED  --------------------------------------
#define SGPIO_CTRL_DISABLED_CTRL_DISABLEDn0_Pos               0                                                         /*!< SGPIO CTRL_DISABLED: CTRL_DISABLEDn0 Position */
#define SGPIO_CTRL_DISABLED_CTRL_DISABLEDn0_Msk               (0x01UL << SGPIO_CTRL_DISABLED_CTRL_DISABLEDn0_Pos)       /*!< SGPIO CTRL_DISABLED: CTRL_DISABLEDn0 Mask */
#define SGPIO_CTRL_DISABLED_CTRL_DISABLEDn1_Pos               1                                                         /*!< SGPIO CTRL_DISABLED: CTRL_DISABLEDn1 Position */
#define SGPIO_CTRL_DISABLED_CTRL_DISABLEDn1_Msk               (0x01UL << SGPIO_CTRL_DISABLED_CTRL_DISABLEDn1_Pos)       /*!< SGPIO CTRL_DISABLED: CTRL_DISABLEDn1 Mask */
#define SGPIO_CTRL_DISABLED_CTRL_DISABLEDn2_Pos               2                                                         /*!< SGPIO CTRL_DISABLED: CTRL_DISABLEDn2 Position */
#define SGPIO_CTRL_DISABLED_CTRL_DISABLEDn2_Msk               (0x01UL << SGPIO_CTRL_DISABLED_CTRL_DISABLEDn2_Pos)       /*!< SGPIO CTRL_DISABLED: CTRL_DISABLEDn2 Mask */
#define SGPIO_CTRL_DISABLED_CTRL_DISABLEDn3_Pos               3                                                         /*!< SGPIO CTRL_DISABLED: CTRL_DISABLEDn3 Position */
#define SGPIO_CTRL_DISABLED_CTRL_DISABLEDn3_Msk               (0x01UL << SGPIO_CTRL_DISABLED_CTRL_DISABLEDn3_Pos)       /*!< SGPIO CTRL_DISABLED: CTRL_DISABLEDn3 Mask */
#define SGPIO_CTRL_DISABLED_CTRL_DISABLEDn4_Pos               4                                                         /*!< SGPIO CTRL_DISABLED: CTRL_DISABLEDn4 Position */
#define SGPIO_CTRL_DISABLED_CTRL_DISABLEDn4_Msk               (0x01UL << SGPIO_CTRL_DISABLED_CTRL_DISABLEDn4_Pos)       /*!< SGPIO CTRL_DISABLED: CTRL_DISABLEDn4 Mask */
#define SGPIO_CTRL_DISABLED_CTRL_DISABLEDn5_Pos               5                                                         /*!< SGPIO CTRL_DISABLED: CTRL_DISABLEDn5 Position */
#define SGPIO_CTRL_DISABLED_CTRL_DISABLEDn5_Msk               (0x01UL << SGPIO_CTRL_DISABLED_CTRL_DISABLEDn5_Pos)       /*!< SGPIO CTRL_DISABLED: CTRL_DISABLEDn5 Mask */
#define SGPIO_CTRL_DISABLED_CTRL_DISABLEDn6_Pos               6                                                         /*!< SGPIO CTRL_DISABLED: CTRL_DISABLEDn6 Position */
#define SGPIO_CTRL_DISABLED_CTRL_DISABLEDn6_Msk               (0x01UL << SGPIO_CTRL_DISABLED_CTRL_DISABLEDn6_Pos)       /*!< SGPIO CTRL_DISABLED: CTRL_DISABLEDn6 Mask */
#define SGPIO_CTRL_DISABLED_CTRL_DISABLEDn7_Pos               7                                                         /*!< SGPIO CTRL_DISABLED: CTRL_DISABLEDn7 Position */
#define SGPIO_CTRL_DISABLED_CTRL_DISABLEDn7_Msk               (0x01UL << SGPIO_CTRL_DISABLED_CTRL_DISABLEDn7_Pos)       /*!< SGPIO CTRL_DISABLED: CTRL_DISABLEDn7 Mask */
#define SGPIO_CTRL_DISABLED_CTRL_DISABLEDn8_Pos               8                                                         /*!< SGPIO CTRL_DISABLED: CTRL_DISABLEDn8 Position */
#define SGPIO_CTRL_DISABLED_CTRL_DISABLEDn8_Msk               (0x01UL << SGPIO_CTRL_DISABLED_CTRL_DISABLEDn8_Pos)       /*!< SGPIO CTRL_DISABLED: CTRL_DISABLEDn8 Mask */
#define SGPIO_CTRL_DISABLED_CTRL_DISABLEDn9_Pos               9                                                         /*!< SGPIO CTRL_DISABLED: CTRL_DISABLEDn9 Position */
#define SGPIO_CTRL_DISABLED_CTRL_DISABLEDn9_Msk               (0x01UL << SGPIO_CTRL_DISABLED_CTRL_DISABLEDn9_Pos)       /*!< SGPIO CTRL_DISABLED: CTRL_DISABLEDn9 Mask */
#define SGPIO_CTRL_DISABLED_CTRL_DISABLEDn10_Pos              10                                                        /*!< SGPIO CTRL_DISABLED: CTRL_DISABLEDn10 Position */
#define SGPIO_CTRL_DISABLED_CTRL_DISABLEDn10_Msk              (0x01UL << SGPIO_CTRL_DISABLED_CTRL_DISABLEDn10_Pos)      /*!< SGPIO CTRL_DISABLED: CTRL_DISABLEDn10 Mask */
#define SGPIO_CTRL_DISABLED_CTRL_DISABLEDn11_Pos              11                                                        /*!< SGPIO CTRL_DISABLED: CTRL_DISABLEDn11 Position */
#define SGPIO_CTRL_DISABLED_CTRL_DISABLEDn11_Msk              (0x01UL << SGPIO_CTRL_DISABLED_CTRL_DISABLEDn11_Pos)      /*!< SGPIO CTRL_DISABLED: CTRL_DISABLEDn11 Mask */
#define SGPIO_CTRL_DISABLED_CTRL_DISABLEDn12_Pos              12                                                        /*!< SGPIO CTRL_DISABLED: CTRL_DISABLEDn12 Position */
#define SGPIO_CTRL_DISABLED_CTRL_DISABLEDn12_Msk              (0x01UL << SGPIO_CTRL_DISABLED_CTRL_DISABLEDn12_Pos)      /*!< SGPIO CTRL_DISABLED: CTRL_DISABLEDn12 Mask */
#define SGPIO_CTRL_DISABLED_CTRL_DISABLEDn13_Pos              13                                                        /*!< SGPIO CTRL_DISABLED: CTRL_DISABLEDn13 Position */
#define SGPIO_CTRL_DISABLED_CTRL_DISABLEDn13_Msk              (0x01UL << SGPIO_CTRL_DISABLED_CTRL_DISABLEDn13_Pos)      /*!< SGPIO CTRL_DISABLED: CTRL_DISABLEDn13 Mask */
#define SGPIO_CTRL_DISABLED_CTRL_DISABLEDn14_Pos              14                                                        /*!< SGPIO CTRL_DISABLED: CTRL_DISABLEDn14 Position */
#define SGPIO_CTRL_DISABLED_CTRL_DISABLEDn14_Msk              (0x01UL << SGPIO_CTRL_DISABLED_CTRL_DISABLEDn14_Pos)      /*!< SGPIO CTRL_DISABLED: CTRL_DISABLEDn14 Mask */
#define SGPIO_CTRL_DISABLED_CTRL_DISABLEDn15_Pos              15                                                        /*!< SGPIO CTRL_DISABLED: CTRL_DISABLEDn15 Position */
#define SGPIO_CTRL_DISABLED_CTRL_DISABLEDn15_Msk              (0x01UL << SGPIO_CTRL_DISABLED_CTRL_DISABLEDn15_Pos)      /*!< SGPIO CTRL_DISABLED: CTRL_DISABLEDn15 Mask */

// -------------------------------------  SGPIO_CLR_EN_0  -----------------------------------------
#define SGPIO_CLR_EN_0_CLR_SCI0_Pos                           0                                                         /*!< SGPIO CLR_EN_0: CLR_SCI0 Position   */
#define SGPIO_CLR_EN_0_CLR_SCI0_Msk                           (0x01UL << SGPIO_CLR_EN_0_CLR_SCI0_Pos)                   /*!< SGPIO CLR_EN_0: CLR_SCI0 Mask       */
#define SGPIO_CLR_EN_0_CLR_SCI1_Pos                           1                                                         /*!< SGPIO CLR_EN_0: CLR_SCI1 Position   */
#define SGPIO_CLR_EN_0_CLR_SCI1_Msk                           (0x01UL << SGPIO_CLR_EN_0_CLR_SCI1_Pos)                   /*!< SGPIO CLR_EN_0: CLR_SCI1 Mask       */
#define SGPIO_CLR_EN_0_CLR_SCI2_Pos                           2                                                         /*!< SGPIO CLR_EN_0: CLR_SCI2 Position   */
#define SGPIO_CLR_EN_0_CLR_SCI2_Msk                           (0x01UL << SGPIO_CLR_EN_0_CLR_SCI2_Pos)                   /*!< SGPIO CLR_EN_0: CLR_SCI2 Mask       */
#define SGPIO_CLR_EN_0_CLR_SCI3_Pos                           3                                                         /*!< SGPIO CLR_EN_0: CLR_SCI3 Position   */
#define SGPIO_CLR_EN_0_CLR_SCI3_Msk                           (0x01UL << SGPIO_CLR_EN_0_CLR_SCI3_Pos)                   /*!< SGPIO CLR_EN_0: CLR_SCI3 Mask       */
#define SGPIO_CLR_EN_0_CLR_SCI4_Pos                           4                                                         /*!< SGPIO CLR_EN_0: CLR_SCI4 Position   */
#define SGPIO_CLR_EN_0_CLR_SCI4_Msk                           (0x01UL << SGPIO_CLR_EN_0_CLR_SCI4_Pos)                   /*!< SGPIO CLR_EN_0: CLR_SCI4 Mask       */
#define SGPIO_CLR_EN_0_CLR_SCI5_Pos                           5                                                         /*!< SGPIO CLR_EN_0: CLR_SCI5 Position   */
#define SGPIO_CLR_EN_0_CLR_SCI5_Msk                           (0x01UL << SGPIO_CLR_EN_0_CLR_SCI5_Pos)                   /*!< SGPIO CLR_EN_0: CLR_SCI5 Mask       */
#define SGPIO_CLR_EN_0_CLR_SCI6_Pos                           6                                                         /*!< SGPIO CLR_EN_0: CLR_SCI6 Position   */
#define SGPIO_CLR_EN_0_CLR_SCI6_Msk                           (0x01UL << SGPIO_CLR_EN_0_CLR_SCI6_Pos)                   /*!< SGPIO CLR_EN_0: CLR_SCI6 Mask       */
#define SGPIO_CLR_EN_0_CLR_SCI7_Pos                           7                                                         /*!< SGPIO CLR_EN_0: CLR_SCI7 Position   */
#define SGPIO_CLR_EN_0_CLR_SCI7_Msk                           (0x01UL << SGPIO_CLR_EN_0_CLR_SCI7_Pos)                   /*!< SGPIO CLR_EN_0: CLR_SCI7 Mask       */
#define SGPIO_CLR_EN_0_CLR_SCI8_Pos                           8                                                         /*!< SGPIO CLR_EN_0: CLR_SCI8 Position   */
#define SGPIO_CLR_EN_0_CLR_SCI8_Msk                           (0x01UL << SGPIO_CLR_EN_0_CLR_SCI8_Pos)                   /*!< SGPIO CLR_EN_0: CLR_SCI8 Mask       */
#define SGPIO_CLR_EN_0_CLR_SCI9_Pos                           9                                                         /*!< SGPIO CLR_EN_0: CLR_SCI9 Position   */
#define SGPIO_CLR_EN_0_CLR_SCI9_Msk                           (0x01UL << SGPIO_CLR_EN_0_CLR_SCI9_Pos)                   /*!< SGPIO CLR_EN_0: CLR_SCI9 Mask       */
#define SGPIO_CLR_EN_0_CLR_SCI10_Pos                          10                                                        /*!< SGPIO CLR_EN_0: CLR_SCI10 Position  */
#define SGPIO_CLR_EN_0_CLR_SCI10_Msk                          (0x01UL << SGPIO_CLR_EN_0_CLR_SCI10_Pos)                  /*!< SGPIO CLR_EN_0: CLR_SCI10 Mask      */
#define SGPIO_CLR_EN_0_CLR_SCI11_Pos                          11                                                        /*!< SGPIO CLR_EN_0: CLR_SCI11 Position  */
#define SGPIO_CLR_EN_0_CLR_SCI11_Msk                          (0x01UL << SGPIO_CLR_EN_0_CLR_SCI11_Pos)                  /*!< SGPIO CLR_EN_0: CLR_SCI11 Mask      */
#define SGPIO_CLR_EN_0_CLR_SCI12_Pos                          12                                                        /*!< SGPIO CLR_EN_0: CLR_SCI12 Position  */
#define SGPIO_CLR_EN_0_CLR_SCI12_Msk                          (0x01UL << SGPIO_CLR_EN_0_CLR_SCI12_Pos)                  /*!< SGPIO CLR_EN_0: CLR_SCI12 Mask      */
#define SGPIO_CLR_EN_0_CLR_SCI13_Pos                          13                                                        /*!< SGPIO CLR_EN_0: CLR_SCI13 Position  */
#define SGPIO_CLR_EN_0_CLR_SCI13_Msk                          (0x01UL << SGPIO_CLR_EN_0_CLR_SCI13_Pos)                  /*!< SGPIO CLR_EN_0: CLR_SCI13 Mask      */
#define SGPIO_CLR_EN_0_CLR_SCI14_Pos                          14                                                        /*!< SGPIO CLR_EN_0: CLR_SCI14 Position  */
#define SGPIO_CLR_EN_0_CLR_SCI14_Msk                          (0x01UL << SGPIO_CLR_EN_0_CLR_SCI14_Pos)                  /*!< SGPIO CLR_EN_0: CLR_SCI14 Mask      */
#define SGPIO_CLR_EN_0_CLR_SCI15_Pos                          15                                                        /*!< SGPIO CLR_EN_0: CLR_SCI15 Position  */
#define SGPIO_CLR_EN_0_CLR_SCI15_Msk                          (0x01UL << SGPIO_CLR_EN_0_CLR_SCI15_Pos)                  /*!< SGPIO CLR_EN_0: CLR_SCI15 Mask      */

// -------------------------------------  SGPIO_SET_EN_0  -----------------------------------------
#define SGPIO_SET_EN_0_SET_SCI0_Pos                           0                                                         /*!< SGPIO SET_EN_0: SET_SCI0 Position   */
#define SGPIO_SET_EN_0_SET_SCI0_Msk                           (0x01UL << SGPIO_SET_EN_0_SET_SCI0_Pos)                   /*!< SGPIO SET_EN_0: SET_SCI0 Mask       */
#define SGPIO_SET_EN_0_SET_SCI1_Pos                           1                                                         /*!< SGPIO SET_EN_0: SET_SCI1 Position   */
#define SGPIO_SET_EN_0_SET_SCI1_Msk                           (0x01UL << SGPIO_SET_EN_0_SET_SCI1_Pos)                   /*!< SGPIO SET_EN_0: SET_SCI1 Mask       */
#define SGPIO_SET_EN_0_SET_SCI2_Pos                           2                                                         /*!< SGPIO SET_EN_0: SET_SCI2 Position   */
#define SGPIO_SET_EN_0_SET_SCI2_Msk                           (0x01UL << SGPIO_SET_EN_0_SET_SCI2_Pos)                   /*!< SGPIO SET_EN_0: SET_SCI2 Mask       */
#define SGPIO_SET_EN_0_SET_SCI3_Pos                           3                                                         /*!< SGPIO SET_EN_0: SET_SCI3 Position   */
#define SGPIO_SET_EN_0_SET_SCI3_Msk                           (0x01UL << SGPIO_SET_EN_0_SET_SCI3_Pos)                   /*!< SGPIO SET_EN_0: SET_SCI3 Mask       */
#define SGPIO_SET_EN_0_SET_SCI4_Pos                           4                                                         /*!< SGPIO SET_EN_0: SET_SCI4 Position   */
#define SGPIO_SET_EN_0_SET_SCI4_Msk                           (0x01UL << SGPIO_SET_EN_0_SET_SCI4_Pos)                   /*!< SGPIO SET_EN_0: SET_SCI4 Mask       */
#define SGPIO_SET_EN_0_SET_SCI5_Pos                           5                                                         /*!< SGPIO SET_EN_0: SET_SCI5 Position   */
#define SGPIO_SET_EN_0_SET_SCI5_Msk                           (0x01UL << SGPIO_SET_EN_0_SET_SCI5_Pos)                   /*!< SGPIO SET_EN_0: SET_SCI5 Mask       */
#define SGPIO_SET_EN_0_SET_SCI6_Pos                           6                                                         /*!< SGPIO SET_EN_0: SET_SCI6 Position   */
#define SGPIO_SET_EN_0_SET_SCI6_Msk                           (0x01UL << SGPIO_SET_EN_0_SET_SCI6_Pos)                   /*!< SGPIO SET_EN_0: SET_SCI6 Mask       */
#define SGPIO_SET_EN_0_SET_SCI7_Pos                           7                                                         /*!< SGPIO SET_EN_0: SET_SCI7 Position   */
#define SGPIO_SET_EN_0_SET_SCI7_Msk                           (0x01UL << SGPIO_SET_EN_0_SET_SCI7_Pos)                   /*!< SGPIO SET_EN_0: SET_SCI7 Mask       */
#define SGPIO_SET_EN_0_SET_SCI8_Pos                           8                                                         /*!< SGPIO SET_EN_0: SET_SCI8 Position   */
#define SGPIO_SET_EN_0_SET_SCI8_Msk                           (0x01UL << SGPIO_SET_EN_0_SET_SCI8_Pos)                   /*!< SGPIO SET_EN_0: SET_SCI8 Mask       */
#define SGPIO_SET_EN_0_SET_SCI9_Pos                           9                                                         /*!< SGPIO SET_EN_0: SET_SCI9 Position   */
#define SGPIO_SET_EN_0_SET_SCI9_Msk                           (0x01UL << SGPIO_SET_EN_0_SET_SCI9_Pos)                   /*!< SGPIO SET_EN_0: SET_SCI9 Mask       */
#define SGPIO_SET_EN_0_SET_SCI10_Pos                          10                                                        /*!< SGPIO SET_EN_0: SET_SCI10 Position  */
#define SGPIO_SET_EN_0_SET_SCI10_Msk                          (0x01UL << SGPIO_SET_EN_0_SET_SCI10_Pos)                  /*!< SGPIO SET_EN_0: SET_SCI10 Mask      */
#define SGPIO_SET_EN_0_SET_SCI11_Pos                          11                                                        /*!< SGPIO SET_EN_0: SET_SCI11 Position  */
#define SGPIO_SET_EN_0_SET_SCI11_Msk                          (0x01UL << SGPIO_SET_EN_0_SET_SCI11_Pos)                  /*!< SGPIO SET_EN_0: SET_SCI11 Mask      */
#define SGPIO_SET_EN_0_SET_SCI12_Pos                          12                                                        /*!< SGPIO SET_EN_0: SET_SCI12 Position  */
#define SGPIO_SET_EN_0_SET_SCI12_Msk                          (0x01UL << SGPIO_SET_EN_0_SET_SCI12_Pos)                  /*!< SGPIO SET_EN_0: SET_SCI12 Mask      */
#define SGPIO_SET_EN_0_SET_SCI13_Pos                          13                                                        /*!< SGPIO SET_EN_0: SET_SCI13 Position  */
#define SGPIO_SET_EN_0_SET_SCI13_Msk                          (0x01UL << SGPIO_SET_EN_0_SET_SCI13_Pos)                  /*!< SGPIO SET_EN_0: SET_SCI13 Mask      */
#define SGPIO_SET_EN_0_SET_SCI14_Pos                          14                                                        /*!< SGPIO SET_EN_0: SET_SCI14 Position  */
#define SGPIO_SET_EN_0_SET_SCI14_Msk                          (0x01UL << SGPIO_SET_EN_0_SET_SCI14_Pos)                  /*!< SGPIO SET_EN_0: SET_SCI14 Mask      */
#define SGPIO_SET_EN_0_SET_SCI15_Pos                          15                                                        /*!< SGPIO SET_EN_0: SET_SCI15 Position  */
#define SGPIO_SET_EN_0_SET_SCI15_Msk                          (0x01UL << SGPIO_SET_EN_0_SET_SCI15_Pos)                  /*!< SGPIO SET_EN_0: SET_SCI15 Mask      */

// -------------------------------------  SGPIO_ENABLE_0  -----------------------------------------
#define SGPIO_ENABLE_0_ENABLE_SCI0_Pos                        0                                                         /*!< SGPIO ENABLE_0: ENABLE_SCI0 Position */
#define SGPIO_ENABLE_0_ENABLE_SCI0_Msk                        (0x01UL << SGPIO_ENABLE_0_ENABLE_SCI0_Pos)                /*!< SGPIO ENABLE_0: ENABLE_SCI0 Mask    */
#define SGPIO_ENABLE_0_ENABLE_SCI1_Pos                        1                                                         /*!< SGPIO ENABLE_0: ENABLE_SCI1 Position */
#define SGPIO_ENABLE_0_ENABLE_SCI1_Msk                        (0x01UL << SGPIO_ENABLE_0_ENABLE_SCI1_Pos)                /*!< SGPIO ENABLE_0: ENABLE_SCI1 Mask    */
#define SGPIO_ENABLE_0_ENABLE_SCI2_Pos                        2                                                         /*!< SGPIO ENABLE_0: ENABLE_SCI2 Position */
#define SGPIO_ENABLE_0_ENABLE_SCI2_Msk                        (0x01UL << SGPIO_ENABLE_0_ENABLE_SCI2_Pos)                /*!< SGPIO ENABLE_0: ENABLE_SCI2 Mask    */
#define SGPIO_ENABLE_0_ENABLE_SCI3_Pos                        3                                                         /*!< SGPIO ENABLE_0: ENABLE_SCI3 Position */
#define SGPIO_ENABLE_0_ENABLE_SCI3_Msk                        (0x01UL << SGPIO_ENABLE_0_ENABLE_SCI3_Pos)                /*!< SGPIO ENABLE_0: ENABLE_SCI3 Mask    */
#define SGPIO_ENABLE_0_ENABLE_SCI4_Pos                        4                                                         /*!< SGPIO ENABLE_0: ENABLE_SCI4 Position */
#define SGPIO_ENABLE_0_ENABLE_SCI4_Msk                        (0x01UL << SGPIO_ENABLE_0_ENABLE_SCI4_Pos)                /*!< SGPIO ENABLE_0: ENABLE_SCI4 Mask    */
#define SGPIO_ENABLE_0_ENABLE_SCI5_Pos                        5                                                         /*!< SGPIO ENABLE_0: ENABLE_SCI5 Position */
#define SGPIO_ENABLE_0_ENABLE_SCI5_Msk                        (0x01UL << SGPIO_ENABLE_0_ENABLE_SCI5_Pos)                /*!< SGPIO ENABLE_0: ENABLE_SCI5 Mask    */
#define SGPIO_ENABLE_0_ENABLE_SCI6_Pos                        6                                                         /*!< SGPIO ENABLE_0: ENABLE_SCI6 Position */
#define SGPIO_ENABLE_0_ENABLE_SCI6_Msk                        (0x01UL << SGPIO_ENABLE_0_ENABLE_SCI6_Pos)                /*!< SGPIO ENABLE_0: ENABLE_SCI6 Mask    */
#define SGPIO_ENABLE_0_ENABLE_SCI7_Pos                        7                                                         /*!< SGPIO ENABLE_0: ENABLE_SCI7 Position */
#define SGPIO_ENABLE_0_ENABLE_SCI7_Msk                        (0x01UL << SGPIO_ENABLE_0_ENABLE_SCI7_Pos)                /*!< SGPIO ENABLE_0: ENABLE_SCI7 Mask    */
#define SGPIO_ENABLE_0_ENABLE_SCI8_Pos                        8                                                         /*!< SGPIO ENABLE_0: ENABLE_SCI8 Position */
#define SGPIO_ENABLE_0_ENABLE_SCI8_Msk                        (0x01UL << SGPIO_ENABLE_0_ENABLE_SCI8_Pos)                /*!< SGPIO ENABLE_0: ENABLE_SCI8 Mask    */
#define SGPIO_ENABLE_0_ENABLE_SCI9_Pos                        9                                                         /*!< SGPIO ENABLE_0: ENABLE_SCI9 Position */
#define SGPIO_ENABLE_0_ENABLE_SCI9_Msk                        (0x01UL << SGPIO_ENABLE_0_ENABLE_SCI9_Pos)                /*!< SGPIO ENABLE_0: ENABLE_SCI9 Mask    */
#define SGPIO_ENABLE_0_ENABLE_SCI10_Pos                       10                                                        /*!< SGPIO ENABLE_0: ENABLE_SCI10 Position */
#define SGPIO_ENABLE_0_ENABLE_SCI10_Msk                       (0x01UL << SGPIO_ENABLE_0_ENABLE_SCI10_Pos)               /*!< SGPIO ENABLE_0: ENABLE_SCI10 Mask   */
#define SGPIO_ENABLE_0_ENABLE_SCI11_Pos                       11                                                        /*!< SGPIO ENABLE_0: ENABLE_SCI11 Position */
#define SGPIO_ENABLE_0_ENABLE_SCI11_Msk                       (0x01UL << SGPIO_ENABLE_0_ENABLE_SCI11_Pos)               /*!< SGPIO ENABLE_0: ENABLE_SCI11 Mask   */
#define SGPIO_ENABLE_0_ENABLE_SCI12_Pos                       12                                                        /*!< SGPIO ENABLE_0: ENABLE_SCI12 Position */
#define SGPIO_ENABLE_0_ENABLE_SCI12_Msk                       (0x01UL << SGPIO_ENABLE_0_ENABLE_SCI12_Pos)               /*!< SGPIO ENABLE_0: ENABLE_SCI12 Mask   */
#define SGPIO_ENABLE_0_ENABLE_SCI13_Pos                       13                                                        /*!< SGPIO ENABLE_0: ENABLE_SCI13 Position */
#define SGPIO_ENABLE_0_ENABLE_SCI13_Msk                       (0x01UL << SGPIO_ENABLE_0_ENABLE_SCI13_Pos)               /*!< SGPIO ENABLE_0: ENABLE_SCI13 Mask   */
#define SGPIO_ENABLE_0_ENABLE_SCI14_Pos                       14                                                        /*!< SGPIO ENABLE_0: ENABLE_SCI14 Position */
#define SGPIO_ENABLE_0_ENABLE_SCI14_Msk                       (0x01UL << SGPIO_ENABLE_0_ENABLE_SCI14_Pos)               /*!< SGPIO ENABLE_0: ENABLE_SCI14 Mask   */
#define SGPIO_ENABLE_0_ENABLE_SCI15_Pos                       15                                                        /*!< SGPIO ENABLE_0: ENABLE_SCI15 Position */
#define SGPIO_ENABLE_0_ENABLE_SCI15_Msk                       (0x01UL << SGPIO_ENABLE_0_ENABLE_SCI15_Pos)               /*!< SGPIO ENABLE_0: ENABLE_SCI15 Mask   */

// -------------------------------------  SGPIO_STATUS_0  -----------------------------------------
#define SGPIO_STATUS_0_STATUS_SCI0_Pos                        0                                                         /*!< SGPIO STATUS_0: STATUS_SCI0 Position */
#define SGPIO_STATUS_0_STATUS_SCI0_Msk                        (0x01UL << SGPIO_STATUS_0_STATUS_SCI0_Pos)                /*!< SGPIO STATUS_0: STATUS_SCI0 Mask    */
#define SGPIO_STATUS_0_STATUS_SCI1_Pos                        1                                                         /*!< SGPIO STATUS_0: STATUS_SCI1 Position */
#define SGPIO_STATUS_0_STATUS_SCI1_Msk                        (0x01UL << SGPIO_STATUS_0_STATUS_SCI1_Pos)                /*!< SGPIO STATUS_0: STATUS_SCI1 Mask    */
#define SGPIO_STATUS_0_STATUS_SCI2_Pos                        2                                                         /*!< SGPIO STATUS_0: STATUS_SCI2 Position */
#define SGPIO_STATUS_0_STATUS_SCI2_Msk                        (0x01UL << SGPIO_STATUS_0_STATUS_SCI2_Pos)                /*!< SGPIO STATUS_0: STATUS_SCI2 Mask    */
#define SGPIO_STATUS_0_STATUS_SCI3_Pos                        3                                                         /*!< SGPIO STATUS_0: STATUS_SCI3 Position */
#define SGPIO_STATUS_0_STATUS_SCI3_Msk                        (0x01UL << SGPIO_STATUS_0_STATUS_SCI3_Pos)                /*!< SGPIO STATUS_0: STATUS_SCI3 Mask    */
#define SGPIO_STATUS_0_STATUS_SCI4_Pos                        4                                                         /*!< SGPIO STATUS_0: STATUS_SCI4 Position */
#define SGPIO_STATUS_0_STATUS_SCI4_Msk                        (0x01UL << SGPIO_STATUS_0_STATUS_SCI4_Pos)                /*!< SGPIO STATUS_0: STATUS_SCI4 Mask    */
#define SGPIO_STATUS_0_STATUS_SCI5_Pos                        5                                                         /*!< SGPIO STATUS_0: STATUS_SCI5 Position */
#define SGPIO_STATUS_0_STATUS_SCI5_Msk                        (0x01UL << SGPIO_STATUS_0_STATUS_SCI5_Pos)                /*!< SGPIO STATUS_0: STATUS_SCI5 Mask    */
#define SGPIO_STATUS_0_STATUS_SCI6_Pos                        6                                                         /*!< SGPIO STATUS_0: STATUS_SCI6 Position */
#define SGPIO_STATUS_0_STATUS_SCI6_Msk                        (0x01UL << SGPIO_STATUS_0_STATUS_SCI6_Pos)                /*!< SGPIO STATUS_0: STATUS_SCI6 Mask    */
#define SGPIO_STATUS_0_STATUS_SCI7_Pos                        7                                                         /*!< SGPIO STATUS_0: STATUS_SCI7 Position */
#define SGPIO_STATUS_0_STATUS_SCI7_Msk                        (0x01UL << SGPIO_STATUS_0_STATUS_SCI7_Pos)                /*!< SGPIO STATUS_0: STATUS_SCI7 Mask    */
#define SGPIO_STATUS_0_STATUS_SCI8_Pos                        8                                                         /*!< SGPIO STATUS_0: STATUS_SCI8 Position */
#define SGPIO_STATUS_0_STATUS_SCI8_Msk                        (0x01UL << SGPIO_STATUS_0_STATUS_SCI8_Pos)                /*!< SGPIO STATUS_0: STATUS_SCI8 Mask    */
#define SGPIO_STATUS_0_STATUS_SCI9_Pos                        9                                                         /*!< SGPIO STATUS_0: STATUS_SCI9 Position */
#define SGPIO_STATUS_0_STATUS_SCI9_Msk                        (0x01UL << SGPIO_STATUS_0_STATUS_SCI9_Pos)                /*!< SGPIO STATUS_0: STATUS_SCI9 Mask    */
#define SGPIO_STATUS_0_STATUS_SCI10_Pos                       10                                                        /*!< SGPIO STATUS_0: STATUS_SCI10 Position */
#define SGPIO_STATUS_0_STATUS_SCI10_Msk                       (0x01UL << SGPIO_STATUS_0_STATUS_SCI10_Pos)               /*!< SGPIO STATUS_0: STATUS_SCI10 Mask   */
#define SGPIO_STATUS_0_STATUS_SCI11_Pos                       11                                                        /*!< SGPIO STATUS_0: STATUS_SCI11 Position */
#define SGPIO_STATUS_0_STATUS_SCI11_Msk                       (0x01UL << SGPIO_STATUS_0_STATUS_SCI11_Pos)               /*!< SGPIO STATUS_0: STATUS_SCI11 Mask   */
#define SGPIO_STATUS_0_STATUS_SCI12_Pos                       12                                                        /*!< SGPIO STATUS_0: STATUS_SCI12 Position */
#define SGPIO_STATUS_0_STATUS_SCI12_Msk                       (0x01UL << SGPIO_STATUS_0_STATUS_SCI12_Pos)               /*!< SGPIO STATUS_0: STATUS_SCI12 Mask   */
#define SGPIO_STATUS_0_STATUS_SCI13_Pos                       13                                                        /*!< SGPIO STATUS_0: STATUS_SCI13 Position */
#define SGPIO_STATUS_0_STATUS_SCI13_Msk                       (0x01UL << SGPIO_STATUS_0_STATUS_SCI13_Pos)               /*!< SGPIO STATUS_0: STATUS_SCI13 Mask   */
#define SGPIO_STATUS_0_STATUS_SCI14_Pos                       14                                                        /*!< SGPIO STATUS_0: STATUS_SCI14 Position */
#define SGPIO_STATUS_0_STATUS_SCI14_Msk                       (0x01UL << SGPIO_STATUS_0_STATUS_SCI14_Pos)               /*!< SGPIO STATUS_0: STATUS_SCI14 Mask   */
#define SGPIO_STATUS_0_STATUS_SCI15_Pos                       15                                                        /*!< SGPIO STATUS_0: STATUS_SCI15 Position */
#define SGPIO_STATUS_0_STATUS_SCI15_Msk                       (0x01UL << SGPIO_STATUS_0_STATUS_SCI15_Pos)               /*!< SGPIO STATUS_0: STATUS_SCI15 Mask   */

// -----------------------------------  SGPIO_CTR_STATUS_0  ---------------------------------------
#define SGPIO_CTR_STATUS_0_CTR_STATUS_SCI0_Pos                0                                                         /*!< SGPIO CTR_STATUS_0: CTR_STATUS_SCI0 Position */
#define SGPIO_CTR_STATUS_0_CTR_STATUS_SCI0_Msk                (0x01UL << SGPIO_CTR_STATUS_0_CTR_STATUS_SCI0_Pos)        /*!< SGPIO CTR_STATUS_0: CTR_STATUS_SCI0 Mask */
#define SGPIO_CTR_STATUS_0_CTR_STATUS_SCI1_Pos                1                                                         /*!< SGPIO CTR_STATUS_0: CTR_STATUS_SCI1 Position */
#define SGPIO_CTR_STATUS_0_CTR_STATUS_SCI1_Msk                (0x01UL << SGPIO_CTR_STATUS_0_CTR_STATUS_SCI1_Pos)        /*!< SGPIO CTR_STATUS_0: CTR_STATUS_SCI1 Mask */
#define SGPIO_CTR_STATUS_0_CTR_STATUS_SCI2_Pos                2                                                         /*!< SGPIO CTR_STATUS_0: CTR_STATUS_SCI2 Position */
#define SGPIO_CTR_STATUS_0_CTR_STATUS_SCI2_Msk                (0x01UL << SGPIO_CTR_STATUS_0_CTR_STATUS_SCI2_Pos)        /*!< SGPIO CTR_STATUS_0: CTR_STATUS_SCI2 Mask */
#define SGPIO_CTR_STATUS_0_CTR_STATUS_SCI3_Pos                3                                                         /*!< SGPIO CTR_STATUS_0: CTR_STATUS_SCI3 Position */
#define SGPIO_CTR_STATUS_0_CTR_STATUS_SCI3_Msk                (0x01UL << SGPIO_CTR_STATUS_0_CTR_STATUS_SCI3_Pos)        /*!< SGPIO CTR_STATUS_0: CTR_STATUS_SCI3 Mask */
#define SGPIO_CTR_STATUS_0_CTR_STATUS_SCI4_Pos                4                                                         /*!< SGPIO CTR_STATUS_0: CTR_STATUS_SCI4 Position */
#define SGPIO_CTR_STATUS_0_CTR_STATUS_SCI4_Msk                (0x01UL << SGPIO_CTR_STATUS_0_CTR_STATUS_SCI4_Pos)        /*!< SGPIO CTR_STATUS_0: CTR_STATUS_SCI4 Mask */
#define SGPIO_CTR_STATUS_0_CTR_STATUS_SCI5_Pos                5                                                         /*!< SGPIO CTR_STATUS_0: CTR_STATUS_SCI5 Position */
#define SGPIO_CTR_STATUS_0_CTR_STATUS_SCI5_Msk                (0x01UL << SGPIO_CTR_STATUS_0_CTR_STATUS_SCI5_Pos)        /*!< SGPIO CTR_STATUS_0: CTR_STATUS_SCI5 Mask */
#define SGPIO_CTR_STATUS_0_CTR_STATUS_SCI6_Pos                6                                                         /*!< SGPIO CTR_STATUS_0: CTR_STATUS_SCI6 Position */
#define SGPIO_CTR_STATUS_0_CTR_STATUS_SCI6_Msk                (0x01UL << SGPIO_CTR_STATUS_0_CTR_STATUS_SCI6_Pos)        /*!< SGPIO CTR_STATUS_0: CTR_STATUS_SCI6 Mask */
#define SGPIO_CTR_STATUS_0_CTR_STATUS_SCI7_Pos                7                                                         /*!< SGPIO CTR_STATUS_0: CTR_STATUS_SCI7 Position */
#define SGPIO_CTR_STATUS_0_CTR_STATUS_SCI7_Msk                (0x01UL << SGPIO_CTR_STATUS_0_CTR_STATUS_SCI7_Pos)        /*!< SGPIO CTR_STATUS_0: CTR_STATUS_SCI7 Mask */
#define SGPIO_CTR_STATUS_0_CTR_STATUS_SCI8_Pos                8                                                         /*!< SGPIO CTR_STATUS_0: CTR_STATUS_SCI8 Position */
#define SGPIO_CTR_STATUS_0_CTR_STATUS_SCI8_Msk                (0x01UL << SGPIO_CTR_STATUS_0_CTR_STATUS_SCI8_Pos)        /*!< SGPIO CTR_STATUS_0: CTR_STATUS_SCI8 Mask */
#define SGPIO_CTR_STATUS_0_CTR_STATUS_SCI9_Pos                9                                                         /*!< SGPIO CTR_STATUS_0: CTR_STATUS_SCI9 Position */
#define SGPIO_CTR_STATUS_0_CTR_STATUS_SCI9_Msk                (0x01UL << SGPIO_CTR_STATUS_0_CTR_STATUS_SCI9_Pos)        /*!< SGPIO CTR_STATUS_0: CTR_STATUS_SCI9 Mask */
#define SGPIO_CTR_STATUS_0_CTR_STATUS_SCI10_Pos               10                                                        /*!< SGPIO CTR_STATUS_0: CTR_STATUS_SCI10 Position */
#define SGPIO_CTR_STATUS_0_CTR_STATUS_SCI10_Msk               (0x01UL << SGPIO_CTR_STATUS_0_CTR_STATUS_SCI10_Pos)       /*!< SGPIO CTR_STATUS_0: CTR_STATUS_SCI10 Mask */
#define SGPIO_CTR_STATUS_0_CTR_STATUS_SCI11_Pos               11                                                        /*!< SGPIO CTR_STATUS_0: CTR_STATUS_SCI11 Position */
#define SGPIO_CTR_STATUS_0_CTR_STATUS_SCI11_Msk               (0x01UL << SGPIO_CTR_STATUS_0_CTR_STATUS_SCI11_Pos)       /*!< SGPIO CTR_STATUS_0: CTR_STATUS_SCI11 Mask */
#define SGPIO_CTR_STATUS_0_CTR_STATUS_SCI12_Pos               12                                                        /*!< SGPIO CTR_STATUS_0: CTR_STATUS_SCI12 Position */
#define SGPIO_CTR_STATUS_0_CTR_STATUS_SCI12_Msk               (0x01UL << SGPIO_CTR_STATUS_0_CTR_STATUS_SCI12_Pos)       /*!< SGPIO CTR_STATUS_0: CTR_STATUS_SCI12 Mask */
#define SGPIO_CTR_STATUS_0_CTR_STATUS_SCI13_Pos               13                                                        /*!< SGPIO CTR_STATUS_0: CTR_STATUS_SCI13 Position */
#define SGPIO_CTR_STATUS_0_CTR_STATUS_SCI13_Msk               (0x01UL << SGPIO_CTR_STATUS_0_CTR_STATUS_SCI13_Pos)       /*!< SGPIO CTR_STATUS_0: CTR_STATUS_SCI13 Mask */
#define SGPIO_CTR_STATUS_0_CTR_STATUS_SCI14_Pos               14                                                        /*!< SGPIO CTR_STATUS_0: CTR_STATUS_SCI14 Position */
#define SGPIO_CTR_STATUS_0_CTR_STATUS_SCI14_Msk               (0x01UL << SGPIO_CTR_STATUS_0_CTR_STATUS_SCI14_Pos)       /*!< SGPIO CTR_STATUS_0: CTR_STATUS_SCI14 Mask */
#define SGPIO_CTR_STATUS_0_CTR_STATUS_SCI15_Pos               15                                                        /*!< SGPIO CTR_STATUS_0: CTR_STATUS_SCI15 Position */
#define SGPIO_CTR_STATUS_0_CTR_STATUS_SCI15_Msk               (0x01UL << SGPIO_CTR_STATUS_0_CTR_STATUS_SCI15_Pos)       /*!< SGPIO CTR_STATUS_0: CTR_STATUS_SCI15 Mask */

// -----------------------------------  SGPIO_SET_STATUS_0  ---------------------------------------
#define SGPIO_SET_STATUS_0_CTR_STATUS_SCI0_Pos                0                                                         /*!< SGPIO SET_STATUS_0: CTR_STATUS_SCI0 Position */
#define SGPIO_SET_STATUS_0_CTR_STATUS_SCI0_Msk                (0x01UL << SGPIO_SET_STATUS_0_CTR_STATUS_SCI0_Pos)        /*!< SGPIO SET_STATUS_0: CTR_STATUS_SCI0 Mask */
#define SGPIO_SET_STATUS_0_CTR_STATUS_SCI1_Pos                1                                                         /*!< SGPIO SET_STATUS_0: CTR_STATUS_SCI1 Position */
#define SGPIO_SET_STATUS_0_CTR_STATUS_SCI1_Msk                (0x01UL << SGPIO_SET_STATUS_0_CTR_STATUS_SCI1_Pos)        /*!< SGPIO SET_STATUS_0: CTR_STATUS_SCI1 Mask */
#define SGPIO_SET_STATUS_0_CTR_STATUS_SCI2_Pos                2                                                         /*!< SGPIO SET_STATUS_0: CTR_STATUS_SCI2 Position */
#define SGPIO_SET_STATUS_0_CTR_STATUS_SCI2_Msk                (0x01UL << SGPIO_SET_STATUS_0_CTR_STATUS_SCI2_Pos)        /*!< SGPIO SET_STATUS_0: CTR_STATUS_SCI2 Mask */
#define SGPIO_SET_STATUS_0_CTR_STATUS_SCI3_Pos                3                                                         /*!< SGPIO SET_STATUS_0: CTR_STATUS_SCI3 Position */
#define SGPIO_SET_STATUS_0_CTR_STATUS_SCI3_Msk                (0x01UL << SGPIO_SET_STATUS_0_CTR_STATUS_SCI3_Pos)        /*!< SGPIO SET_STATUS_0: CTR_STATUS_SCI3 Mask */
#define SGPIO_SET_STATUS_0_CTR_STATUS_SCI4_Pos                4                                                         /*!< SGPIO SET_STATUS_0: CTR_STATUS_SCI4 Position */
#define SGPIO_SET_STATUS_0_CTR_STATUS_SCI4_Msk                (0x01UL << SGPIO_SET_STATUS_0_CTR_STATUS_SCI4_Pos)        /*!< SGPIO SET_STATUS_0: CTR_STATUS_SCI4 Mask */
#define SGPIO_SET_STATUS_0_CTR_STATUS_SCI5_Pos                5                                                         /*!< SGPIO SET_STATUS_0: CTR_STATUS_SCI5 Position */
#define SGPIO_SET_STATUS_0_CTR_STATUS_SCI5_Msk                (0x01UL << SGPIO_SET_STATUS_0_CTR_STATUS_SCI5_Pos)        /*!< SGPIO SET_STATUS_0: CTR_STATUS_SCI5 Mask */
#define SGPIO_SET_STATUS_0_CTR_STATUS_SCI6_Pos                6                                                         /*!< SGPIO SET_STATUS_0: CTR_STATUS_SCI6 Position */
#define SGPIO_SET_STATUS_0_CTR_STATUS_SCI6_Msk                (0x01UL << SGPIO_SET_STATUS_0_CTR_STATUS_SCI6_Pos)        /*!< SGPIO SET_STATUS_0: CTR_STATUS_SCI6 Mask */
#define SGPIO_SET_STATUS_0_CTR_STATUS_SCI7_Pos                7                                                         /*!< SGPIO SET_STATUS_0: CTR_STATUS_SCI7 Position */
#define SGPIO_SET_STATUS_0_CTR_STATUS_SCI7_Msk                (0x01UL << SGPIO_SET_STATUS_0_CTR_STATUS_SCI7_Pos)        /*!< SGPIO SET_STATUS_0: CTR_STATUS_SCI7 Mask */
#define SGPIO_SET_STATUS_0_CTR_STATUS_SCI8_Pos                8                                                         /*!< SGPIO SET_STATUS_0: CTR_STATUS_SCI8 Position */
#define SGPIO_SET_STATUS_0_CTR_STATUS_SCI8_Msk                (0x01UL << SGPIO_SET_STATUS_0_CTR_STATUS_SCI8_Pos)        /*!< SGPIO SET_STATUS_0: CTR_STATUS_SCI8 Mask */
#define SGPIO_SET_STATUS_0_CTR_STATUS_SCI9_Pos                9                                                         /*!< SGPIO SET_STATUS_0: CTR_STATUS_SCI9 Position */
#define SGPIO_SET_STATUS_0_CTR_STATUS_SCI9_Msk                (0x01UL << SGPIO_SET_STATUS_0_CTR_STATUS_SCI9_Pos)        /*!< SGPIO SET_STATUS_0: CTR_STATUS_SCI9 Mask */
#define SGPIO_SET_STATUS_0_CTR_STATUS_SCI10_Pos               10                                                        /*!< SGPIO SET_STATUS_0: CTR_STATUS_SCI10 Position */
#define SGPIO_SET_STATUS_0_CTR_STATUS_SCI10_Msk               (0x01UL << SGPIO_SET_STATUS_0_CTR_STATUS_SCI10_Pos)       /*!< SGPIO SET_STATUS_0: CTR_STATUS_SCI10 Mask */
#define SGPIO_SET_STATUS_0_CTR_STATUS_SCI11_Pos               11                                                        /*!< SGPIO SET_STATUS_0: CTR_STATUS_SCI11 Position */
#define SGPIO_SET_STATUS_0_CTR_STATUS_SCI11_Msk               (0x01UL << SGPIO_SET_STATUS_0_CTR_STATUS_SCI11_Pos)       /*!< SGPIO SET_STATUS_0: CTR_STATUS_SCI11 Mask */
#define SGPIO_SET_STATUS_0_CTR_STATUS_SCI12_Pos               12                                                        /*!< SGPIO SET_STATUS_0: CTR_STATUS_SCI12 Position */
#define SGPIO_SET_STATUS_0_CTR_STATUS_SCI12_Msk               (0x01UL << SGPIO_SET_STATUS_0_CTR_STATUS_SCI12_Pos)       /*!< SGPIO SET_STATUS_0: CTR_STATUS_SCI12 Mask */
#define SGPIO_SET_STATUS_0_CTR_STATUS_SCI13_Pos               13                                                        /*!< SGPIO SET_STATUS_0: CTR_STATUS_SCI13 Position */
#define SGPIO_SET_STATUS_0_CTR_STATUS_SCI13_Msk               (0x01UL << SGPIO_SET_STATUS_0_CTR_STATUS_SCI13_Pos)       /*!< SGPIO SET_STATUS_0: CTR_STATUS_SCI13 Mask */
#define SGPIO_SET_STATUS_0_CTR_STATUS_SCI14_Pos               14                                                        /*!< SGPIO SET_STATUS_0: CTR_STATUS_SCI14 Position */
#define SGPIO_SET_STATUS_0_CTR_STATUS_SCI14_Msk               (0x01UL << SGPIO_SET_STATUS_0_CTR_STATUS_SCI14_Pos)       /*!< SGPIO SET_STATUS_0: CTR_STATUS_SCI14 Mask */
#define SGPIO_SET_STATUS_0_CTR_STATUS_SCI15_Pos               15                                                        /*!< SGPIO SET_STATUS_0: CTR_STATUS_SCI15 Position */
#define SGPIO_SET_STATUS_0_CTR_STATUS_SCI15_Msk               (0x01UL << SGPIO_SET_STATUS_0_CTR_STATUS_SCI15_Pos)       /*!< SGPIO SET_STATUS_0: CTR_STATUS_SCI15 Mask */

// -------------------------------------  SGPIO_CLR_EN_1  -----------------------------------------
#define SGPIO_CLR_EN_1_CLR_EN_CCI0_Pos                        0                                                         /*!< SGPIO CLR_EN_1: CLR_EN_CCI0 Position */
#define SGPIO_CLR_EN_1_CLR_EN_CCI0_Msk                        (0x01UL << SGPIO_CLR_EN_1_CLR_EN_CCI0_Pos)                /*!< SGPIO CLR_EN_1: CLR_EN_CCI0 Mask    */
#define SGPIO_CLR_EN_1_CLR_EN_CCI1_Pos                        1                                                         /*!< SGPIO CLR_EN_1: CLR_EN_CCI1 Position */
#define SGPIO_CLR_EN_1_CLR_EN_CCI1_Msk                        (0x01UL << SGPIO_CLR_EN_1_CLR_EN_CCI1_Pos)                /*!< SGPIO CLR_EN_1: CLR_EN_CCI1 Mask    */
#define SGPIO_CLR_EN_1_CLR_EN_CCI2_Pos                        2                                                         /*!< SGPIO CLR_EN_1: CLR_EN_CCI2 Position */
#define SGPIO_CLR_EN_1_CLR_EN_CCI2_Msk                        (0x01UL << SGPIO_CLR_EN_1_CLR_EN_CCI2_Pos)                /*!< SGPIO CLR_EN_1: CLR_EN_CCI2 Mask    */
#define SGPIO_CLR_EN_1_CLR_EN_CCI3_Pos                        3                                                         /*!< SGPIO CLR_EN_1: CLR_EN_CCI3 Position */
#define SGPIO_CLR_EN_1_CLR_EN_CCI3_Msk                        (0x01UL << SGPIO_CLR_EN_1_CLR_EN_CCI3_Pos)                /*!< SGPIO CLR_EN_1: CLR_EN_CCI3 Mask    */
#define SGPIO_CLR_EN_1_CLR_EN_CCI4_Pos                        4                                                         /*!< SGPIO CLR_EN_1: CLR_EN_CCI4 Position */
#define SGPIO_CLR_EN_1_CLR_EN_CCI4_Msk                        (0x01UL << SGPIO_CLR_EN_1_CLR_EN_CCI4_Pos)                /*!< SGPIO CLR_EN_1: CLR_EN_CCI4 Mask    */
#define SGPIO_CLR_EN_1_CLR_EN_CCI5_Pos                        5                                                         /*!< SGPIO CLR_EN_1: CLR_EN_CCI5 Position */
#define SGPIO_CLR_EN_1_CLR_EN_CCI5_Msk                        (0x01UL << SGPIO_CLR_EN_1_CLR_EN_CCI5_Pos)                /*!< SGPIO CLR_EN_1: CLR_EN_CCI5 Mask    */
#define SGPIO_CLR_EN_1_CLR_EN_CCI6_Pos                        6                                                         /*!< SGPIO CLR_EN_1: CLR_EN_CCI6 Position */
#define SGPIO_CLR_EN_1_CLR_EN_CCI6_Msk                        (0x01UL << SGPIO_CLR_EN_1_CLR_EN_CCI6_Pos)                /*!< SGPIO CLR_EN_1: CLR_EN_CCI6 Mask    */
#define SGPIO_CLR_EN_1_CLR_EN_CCI7_Pos                        7                                                         /*!< SGPIO CLR_EN_1: CLR_EN_CCI7 Position */
#define SGPIO_CLR_EN_1_CLR_EN_CCI7_Msk                        (0x01UL << SGPIO_CLR_EN_1_CLR_EN_CCI7_Pos)                /*!< SGPIO CLR_EN_1: CLR_EN_CCI7 Mask    */
#define SGPIO_CLR_EN_1_CLR_EN_CCI8_Pos                        8                                                         /*!< SGPIO CLR_EN_1: CLR_EN_CCI8 Position */
#define SGPIO_CLR_EN_1_CLR_EN_CCI8_Msk                        (0x01UL << SGPIO_CLR_EN_1_CLR_EN_CCI8_Pos)                /*!< SGPIO CLR_EN_1: CLR_EN_CCI8 Mask    */
#define SGPIO_CLR_EN_1_CLR_EN_CCI9_Pos                        9                                                         /*!< SGPIO CLR_EN_1: CLR_EN_CCI9 Position */
#define SGPIO_CLR_EN_1_CLR_EN_CCI9_Msk                        (0x01UL << SGPIO_CLR_EN_1_CLR_EN_CCI9_Pos)                /*!< SGPIO CLR_EN_1: CLR_EN_CCI9 Mask    */
#define SGPIO_CLR_EN_1_CLR_EN_CCI10_Pos                       10                                                        /*!< SGPIO CLR_EN_1: CLR_EN_CCI10 Position */
#define SGPIO_CLR_EN_1_CLR_EN_CCI10_Msk                       (0x01UL << SGPIO_CLR_EN_1_CLR_EN_CCI10_Pos)               /*!< SGPIO CLR_EN_1: CLR_EN_CCI10 Mask   */
#define SGPIO_CLR_EN_1_CLR_EN_CCI11_Pos                       11                                                        /*!< SGPIO CLR_EN_1: CLR_EN_CCI11 Position */
#define SGPIO_CLR_EN_1_CLR_EN_CCI11_Msk                       (0x01UL << SGPIO_CLR_EN_1_CLR_EN_CCI11_Pos)               /*!< SGPIO CLR_EN_1: CLR_EN_CCI11 Mask   */
#define SGPIO_CLR_EN_1_CLR_EN_CCI12_Pos                       12                                                        /*!< SGPIO CLR_EN_1: CLR_EN_CCI12 Position */
#define SGPIO_CLR_EN_1_CLR_EN_CCI12_Msk                       (0x01UL << SGPIO_CLR_EN_1_CLR_EN_CCI12_Pos)               /*!< SGPIO CLR_EN_1: CLR_EN_CCI12 Mask   */
#define SGPIO_CLR_EN_1_CLR_EN_CCI13_Pos                       13                                                        /*!< SGPIO CLR_EN_1: CLR_EN_CCI13 Position */
#define SGPIO_CLR_EN_1_CLR_EN_CCI13_Msk                       (0x01UL << SGPIO_CLR_EN_1_CLR_EN_CCI13_Pos)               /*!< SGPIO CLR_EN_1: CLR_EN_CCI13 Mask   */
#define SGPIO_CLR_EN_1_CLR_EN_CCI14_Pos                       14                                                        /*!< SGPIO CLR_EN_1: CLR_EN_CCI14 Position */
#define SGPIO_CLR_EN_1_CLR_EN_CCI14_Msk                       (0x01UL << SGPIO_CLR_EN_1_CLR_EN_CCI14_Pos)               /*!< SGPIO CLR_EN_1: CLR_EN_CCI14 Mask   */
#define SGPIO_CLR_EN_1_CLR_EN_CCI15_Pos                       15                                                        /*!< SGPIO CLR_EN_1: CLR_EN_CCI15 Position */
#define SGPIO_CLR_EN_1_CLR_EN_CCI15_Msk                       (0x01UL << SGPIO_CLR_EN_1_CLR_EN_CCI15_Pos)               /*!< SGPIO CLR_EN_1: CLR_EN_CCI15 Mask   */

// -------------------------------------  SGPIO_SET_EN_1  -----------------------------------------
#define SGPIO_SET_EN_1_SET_EN_CCI0_Pos                        0                                                         /*!< SGPIO SET_EN_1: SET_EN_CCI0 Position */
#define SGPIO_SET_EN_1_SET_EN_CCI0_Msk                        (0x01UL << SGPIO_SET_EN_1_SET_EN_CCI0_Pos)                /*!< SGPIO SET_EN_1: SET_EN_CCI0 Mask    */
#define SGPIO_SET_EN_1_SET_EN_CCI1_Pos                        1                                                         /*!< SGPIO SET_EN_1: SET_EN_CCI1 Position */
#define SGPIO_SET_EN_1_SET_EN_CCI1_Msk                        (0x01UL << SGPIO_SET_EN_1_SET_EN_CCI1_Pos)                /*!< SGPIO SET_EN_1: SET_EN_CCI1 Mask    */
#define SGPIO_SET_EN_1_SET_EN_CCI2_Pos                        2                                                         /*!< SGPIO SET_EN_1: SET_EN_CCI2 Position */
#define SGPIO_SET_EN_1_SET_EN_CCI2_Msk                        (0x01UL << SGPIO_SET_EN_1_SET_EN_CCI2_Pos)                /*!< SGPIO SET_EN_1: SET_EN_CCI2 Mask    */
#define SGPIO_SET_EN_1_SET_EN_CCI3_Pos                        3                                                         /*!< SGPIO SET_EN_1: SET_EN_CCI3 Position */
#define SGPIO_SET_EN_1_SET_EN_CCI3_Msk                        (0x01UL << SGPIO_SET_EN_1_SET_EN_CCI3_Pos)                /*!< SGPIO SET_EN_1: SET_EN_CCI3 Mask    */
#define SGPIO_SET_EN_1_SET_EN_CCI4_Pos                        4                                                         /*!< SGPIO SET_EN_1: SET_EN_CCI4 Position */
#define SGPIO_SET_EN_1_SET_EN_CCI4_Msk                        (0x01UL << SGPIO_SET_EN_1_SET_EN_CCI4_Pos)                /*!< SGPIO SET_EN_1: SET_EN_CCI4 Mask    */
#define SGPIO_SET_EN_1_SET_EN_CCI5_Pos                        5                                                         /*!< SGPIO SET_EN_1: SET_EN_CCI5 Position */
#define SGPIO_SET_EN_1_SET_EN_CCI5_Msk                        (0x01UL << SGPIO_SET_EN_1_SET_EN_CCI5_Pos)                /*!< SGPIO SET_EN_1: SET_EN_CCI5 Mask    */
#define SGPIO_SET_EN_1_SET_EN_CCI6_Pos                        6                                                         /*!< SGPIO SET_EN_1: SET_EN_CCI6 Position */
#define SGPIO_SET_EN_1_SET_EN_CCI6_Msk                        (0x01UL << SGPIO_SET_EN_1_SET_EN_CCI6_Pos)                /*!< SGPIO SET_EN_1: SET_EN_CCI6 Mask    */
#define SGPIO_SET_EN_1_SET_EN_CCI7_Pos                        7                                                         /*!< SGPIO SET_EN_1: SET_EN_CCI7 Position */
#define SGPIO_SET_EN_1_SET_EN_CCI7_Msk                        (0x01UL << SGPIO_SET_EN_1_SET_EN_CCI7_Pos)                /*!< SGPIO SET_EN_1: SET_EN_CCI7 Mask    */
#define SGPIO_SET_EN_1_SET_EN_CCI8_Pos                        8                                                         /*!< SGPIO SET_EN_1: SET_EN_CCI8 Position */
#define SGPIO_SET_EN_1_SET_EN_CCI8_Msk                        (0x01UL << SGPIO_SET_EN_1_SET_EN_CCI8_Pos)                /*!< SGPIO SET_EN_1: SET_EN_CCI8 Mask    */
#define SGPIO_SET_EN_1_SET_EN_CCI9_Pos                        9                                                         /*!< SGPIO SET_EN_1: SET_EN_CCI9 Position */
#define SGPIO_SET_EN_1_SET_EN_CCI9_Msk                        (0x01UL << SGPIO_SET_EN_1_SET_EN_CCI9_Pos)                /*!< SGPIO SET_EN_1: SET_EN_CCI9 Mask    */
#define SGPIO_SET_EN_1_SET_EN_CCI10_Pos                       10                                                        /*!< SGPIO SET_EN_1: SET_EN_CCI10 Position */
#define SGPIO_SET_EN_1_SET_EN_CCI10_Msk                       (0x01UL << SGPIO_SET_EN_1_SET_EN_CCI10_Pos)               /*!< SGPIO SET_EN_1: SET_EN_CCI10 Mask   */
#define SGPIO_SET_EN_1_SET_EN_CCI11_Pos                       11                                                        /*!< SGPIO SET_EN_1: SET_EN_CCI11 Position */
#define SGPIO_SET_EN_1_SET_EN_CCI11_Msk                       (0x01UL << SGPIO_SET_EN_1_SET_EN_CCI11_Pos)               /*!< SGPIO SET_EN_1: SET_EN_CCI11 Mask   */
#define SGPIO_SET_EN_1_SET_EN_CCI12_Pos                       12                                                        /*!< SGPIO SET_EN_1: SET_EN_CCI12 Position */
#define SGPIO_SET_EN_1_SET_EN_CCI12_Msk                       (0x01UL << SGPIO_SET_EN_1_SET_EN_CCI12_Pos)               /*!< SGPIO SET_EN_1: SET_EN_CCI12 Mask   */
#define SGPIO_SET_EN_1_SET_EN_CCI13_Pos                       13                                                        /*!< SGPIO SET_EN_1: SET_EN_CCI13 Position */
#define SGPIO_SET_EN_1_SET_EN_CCI13_Msk                       (0x01UL << SGPIO_SET_EN_1_SET_EN_CCI13_Pos)               /*!< SGPIO SET_EN_1: SET_EN_CCI13 Mask   */
#define SGPIO_SET_EN_1_SET_EN_CCI14_Pos                       14                                                        /*!< SGPIO SET_EN_1: SET_EN_CCI14 Position */
#define SGPIO_SET_EN_1_SET_EN_CCI14_Msk                       (0x01UL << SGPIO_SET_EN_1_SET_EN_CCI14_Pos)               /*!< SGPIO SET_EN_1: SET_EN_CCI14 Mask   */
#define SGPIO_SET_EN_1_SET_EN_CCI15_Pos                       15                                                        /*!< SGPIO SET_EN_1: SET_EN_CCI15 Position */
#define SGPIO_SET_EN_1_SET_EN_CCI15_Msk                       (0x01UL << SGPIO_SET_EN_1_SET_EN_CCI15_Pos)               /*!< SGPIO SET_EN_1: SET_EN_CCI15 Mask   */

// -------------------------------------  SGPIO_ENABLE_1  -----------------------------------------
#define SGPIO_ENABLE_1_ENABLE_CCI0_Pos                        0                                                         /*!< SGPIO ENABLE_1: ENABLE_CCI0 Position */
#define SGPIO_ENABLE_1_ENABLE_CCI0_Msk                        (0x01UL << SGPIO_ENABLE_1_ENABLE_CCI0_Pos)                /*!< SGPIO ENABLE_1: ENABLE_CCI0 Mask    */
#define SGPIO_ENABLE_1_ENABLE_CCI1_Pos                        1                                                         /*!< SGPIO ENABLE_1: ENABLE_CCI1 Position */
#define SGPIO_ENABLE_1_ENABLE_CCI1_Msk                        (0x01UL << SGPIO_ENABLE_1_ENABLE_CCI1_Pos)                /*!< SGPIO ENABLE_1: ENABLE_CCI1 Mask    */
#define SGPIO_ENABLE_1_ENABLE_CCI2_Pos                        2                                                         /*!< SGPIO ENABLE_1: ENABLE_CCI2 Position */
#define SGPIO_ENABLE_1_ENABLE_CCI2_Msk                        (0x01UL << SGPIO_ENABLE_1_ENABLE_CCI2_Pos)                /*!< SGPIO ENABLE_1: ENABLE_CCI2 Mask    */
#define SGPIO_ENABLE_1_ENABLE_CCI3_Pos                        3                                                         /*!< SGPIO ENABLE_1: ENABLE_CCI3 Position */
#define SGPIO_ENABLE_1_ENABLE_CCI3_Msk                        (0x01UL << SGPIO_ENABLE_1_ENABLE_CCI3_Pos)                /*!< SGPIO ENABLE_1: ENABLE_CCI3 Mask    */
#define SGPIO_ENABLE_1_ENABLE_CCI4_Pos                        4                                                         /*!< SGPIO ENABLE_1: ENABLE_CCI4 Position */
#define SGPIO_ENABLE_1_ENABLE_CCI4_Msk                        (0x01UL << SGPIO_ENABLE_1_ENABLE_CCI4_Pos)                /*!< SGPIO ENABLE_1: ENABLE_CCI4 Mask    */
#define SGPIO_ENABLE_1_ENABLE_CCI5_Pos                        5                                                         /*!< SGPIO ENABLE_1: ENABLE_CCI5 Position */
#define SGPIO_ENABLE_1_ENABLE_CCI5_Msk                        (0x01UL << SGPIO_ENABLE_1_ENABLE_CCI5_Pos)                /*!< SGPIO ENABLE_1: ENABLE_CCI5 Mask    */
#define SGPIO_ENABLE_1_ENABLE_CCI6_Pos                        6                                                         /*!< SGPIO ENABLE_1: ENABLE_CCI6 Position */
#define SGPIO_ENABLE_1_ENABLE_CCI6_Msk                        (0x01UL << SGPIO_ENABLE_1_ENABLE_CCI6_Pos)                /*!< SGPIO ENABLE_1: ENABLE_CCI6 Mask    */
#define SGPIO_ENABLE_1_ENABLE_CCI7_Pos                        7                                                         /*!< SGPIO ENABLE_1: ENABLE_CCI7 Position */
#define SGPIO_ENABLE_1_ENABLE_CCI7_Msk                        (0x01UL << SGPIO_ENABLE_1_ENABLE_CCI7_Pos)                /*!< SGPIO ENABLE_1: ENABLE_CCI7 Mask    */
#define SGPIO_ENABLE_1_ENABLE_CCI8_Pos                        8                                                         /*!< SGPIO ENABLE_1: ENABLE_CCI8 Position */
#define SGPIO_ENABLE_1_ENABLE_CCI8_Msk                        (0x01UL << SGPIO_ENABLE_1_ENABLE_CCI8_Pos)                /*!< SGPIO ENABLE_1: ENABLE_CCI8 Mask    */
#define SGPIO_ENABLE_1_ENABLE_CCI9_Pos                        9                                                         /*!< SGPIO ENABLE_1: ENABLE_CCI9 Position */
#define SGPIO_ENABLE_1_ENABLE_CCI9_Msk                        (0x01UL << SGPIO_ENABLE_1_ENABLE_CCI9_Pos)                /*!< SGPIO ENABLE_1: ENABLE_CCI9 Mask    */
#define SGPIO_ENABLE_1_ENABLE_CCI10_Pos                       10                                                        /*!< SGPIO ENABLE_1: ENABLE_CCI10 Position */
#define SGPIO_ENABLE_1_ENABLE_CCI10_Msk                       (0x01UL << SGPIO_ENABLE_1_ENABLE_CCI10_Pos)               /*!< SGPIO ENABLE_1: ENABLE_CCI10 Mask   */
#define SGPIO_ENABLE_1_ENABLE_CCI11_Pos                       11                                                        /*!< SGPIO ENABLE_1: ENABLE_CCI11 Position */
#define SGPIO_ENABLE_1_ENABLE_CCI11_Msk                       (0x01UL << SGPIO_ENABLE_1_ENABLE_CCI11_Pos)               /*!< SGPIO ENABLE_1: ENABLE_CCI11 Mask   */
#define SGPIO_ENABLE_1_ENABLE_CCI12_Pos                       12                                                        /*!< SGPIO ENABLE_1: ENABLE_CCI12 Position */
#define SGPIO_ENABLE_1_ENABLE_CCI12_Msk                       (0x01UL << SGPIO_ENABLE_1_ENABLE_CCI12_Pos)               /*!< SGPIO ENABLE_1: ENABLE_CCI12 Mask   */
#define SGPIO_ENABLE_1_ENABLE_CCI13_Pos                       13                                                        /*!< SGPIO ENABLE_1: ENABLE_CCI13 Position */
#define SGPIO_ENABLE_1_ENABLE_CCI13_Msk                       (0x01UL << SGPIO_ENABLE_1_ENABLE_CCI13_Pos)               /*!< SGPIO ENABLE_1: ENABLE_CCI13 Mask   */
#define SGPIO_ENABLE_1_ENABLE_CCI14_Pos                       14                                                        /*!< SGPIO ENABLE_1: ENABLE_CCI14 Position */
#define SGPIO_ENABLE_1_ENABLE_CCI14_Msk                       (0x01UL << SGPIO_ENABLE_1_ENABLE_CCI14_Pos)               /*!< SGPIO ENABLE_1: ENABLE_CCI14 Mask   */
#define SGPIO_ENABLE_1_ENABLE_CCI15_Pos                       15                                                        /*!< SGPIO ENABLE_1: ENABLE_CCI15 Position */
#define SGPIO_ENABLE_1_ENABLE_CCI15_Msk                       (0x01UL << SGPIO_ENABLE_1_ENABLE_CCI15_Pos)               /*!< SGPIO ENABLE_1: ENABLE_CCI15 Mask   */

// -------------------------------------  SGPIO_STATUS_1  -----------------------------------------
#define SGPIO_STATUS_1_STATUS_CCI0_Pos                        0                                                         /*!< SGPIO STATUS_1: STATUS_CCI0 Position */
#define SGPIO_STATUS_1_STATUS_CCI0_Msk                        (0x01UL << SGPIO_STATUS_1_STATUS_CCI0_Pos)                /*!< SGPIO STATUS_1: STATUS_CCI0 Mask    */
#define SGPIO_STATUS_1_STATUS_CCI1_Pos                        1                                                         /*!< SGPIO STATUS_1: STATUS_CCI1 Position */
#define SGPIO_STATUS_1_STATUS_CCI1_Msk                        (0x01UL << SGPIO_STATUS_1_STATUS_CCI1_Pos)                /*!< SGPIO STATUS_1: STATUS_CCI1 Mask    */
#define SGPIO_STATUS_1_STATUS_CCI2_Pos                        2                                                         /*!< SGPIO STATUS_1: STATUS_CCI2 Position */
#define SGPIO_STATUS_1_STATUS_CCI2_Msk                        (0x01UL << SGPIO_STATUS_1_STATUS_CCI2_Pos)                /*!< SGPIO STATUS_1: STATUS_CCI2 Mask    */
#define SGPIO_STATUS_1_STATUS_CCI3_Pos                        3                                                         /*!< SGPIO STATUS_1: STATUS_CCI3 Position */
#define SGPIO_STATUS_1_STATUS_CCI3_Msk                        (0x01UL << SGPIO_STATUS_1_STATUS_CCI3_Pos)                /*!< SGPIO STATUS_1: STATUS_CCI3 Mask    */
#define SGPIO_STATUS_1_STATUS_CCI4_Pos                        4                                                         /*!< SGPIO STATUS_1: STATUS_CCI4 Position */
#define SGPIO_STATUS_1_STATUS_CCI4_Msk                        (0x01UL << SGPIO_STATUS_1_STATUS_CCI4_Pos)                /*!< SGPIO STATUS_1: STATUS_CCI4 Mask    */
#define SGPIO_STATUS_1_STATUS_CCI5_Pos                        5                                                         /*!< SGPIO STATUS_1: STATUS_CCI5 Position */
#define SGPIO_STATUS_1_STATUS_CCI5_Msk                        (0x01UL << SGPIO_STATUS_1_STATUS_CCI5_Pos)                /*!< SGPIO STATUS_1: STATUS_CCI5 Mask    */
#define SGPIO_STATUS_1_STATUS_CCI6_Pos                        6                                                         /*!< SGPIO STATUS_1: STATUS_CCI6 Position */
#define SGPIO_STATUS_1_STATUS_CCI6_Msk                        (0x01UL << SGPIO_STATUS_1_STATUS_CCI6_Pos)                /*!< SGPIO STATUS_1: STATUS_CCI6 Mask    */
#define SGPIO_STATUS_1_STATUS_CCI7_Pos                        7                                                         /*!< SGPIO STATUS_1: STATUS_CCI7 Position */
#define SGPIO_STATUS_1_STATUS_CCI7_Msk                        (0x01UL << SGPIO_STATUS_1_STATUS_CCI7_Pos)                /*!< SGPIO STATUS_1: STATUS_CCI7 Mask    */
#define SGPIO_STATUS_1_STATUS_CCI8_Pos                        8                                                         /*!< SGPIO STATUS_1: STATUS_CCI8 Position */
#define SGPIO_STATUS_1_STATUS_CCI8_Msk                        (0x01UL << SGPIO_STATUS_1_STATUS_CCI8_Pos)                /*!< SGPIO STATUS_1: STATUS_CCI8 Mask    */
#define SGPIO_STATUS_1_STATUS_CCI9_Pos                        9                                                         /*!< SGPIO STATUS_1: STATUS_CCI9 Position */
#define SGPIO_STATUS_1_STATUS_CCI9_Msk                        (0x01UL << SGPIO_STATUS_1_STATUS_CCI9_Pos)                /*!< SGPIO STATUS_1: STATUS_CCI9 Mask    */
#define SGPIO_STATUS_1_STATUS_CCI10_Pos                       10                                                        /*!< SGPIO STATUS_1: STATUS_CCI10 Position */
#define SGPIO_STATUS_1_STATUS_CCI10_Msk                       (0x01UL << SGPIO_STATUS_1_STATUS_CCI10_Pos)               /*!< SGPIO STATUS_1: STATUS_CCI10 Mask   */
#define SGPIO_STATUS_1_STATUS_CCI11_Pos                       11                                                        /*!< SGPIO STATUS_1: STATUS_CCI11 Position */
#define SGPIO_STATUS_1_STATUS_CCI11_Msk                       (0x01UL << SGPIO_STATUS_1_STATUS_CCI11_Pos)               /*!< SGPIO STATUS_1: STATUS_CCI11 Mask   */
#define SGPIO_STATUS_1_STATUS_CCI12_Pos                       12                                                        /*!< SGPIO STATUS_1: STATUS_CCI12 Position */
#define SGPIO_STATUS_1_STATUS_CCI12_Msk                       (0x01UL << SGPIO_STATUS_1_STATUS_CCI12_Pos)               /*!< SGPIO STATUS_1: STATUS_CCI12 Mask   */
#define SGPIO_STATUS_1_STATUS_CCI13_Pos                       13                                                        /*!< SGPIO STATUS_1: STATUS_CCI13 Position */
#define SGPIO_STATUS_1_STATUS_CCI13_Msk                       (0x01UL << SGPIO_STATUS_1_STATUS_CCI13_Pos)               /*!< SGPIO STATUS_1: STATUS_CCI13 Mask   */
#define SGPIO_STATUS_1_STATUS_CCI14_Pos                       14                                                        /*!< SGPIO STATUS_1: STATUS_CCI14 Position */
#define SGPIO_STATUS_1_STATUS_CCI14_Msk                       (0x01UL << SGPIO_STATUS_1_STATUS_CCI14_Pos)               /*!< SGPIO STATUS_1: STATUS_CCI14 Mask   */
#define SGPIO_STATUS_1_STATUS_CCI15_Pos                       15                                                        /*!< SGPIO STATUS_1: STATUS_CCI15 Position */
#define SGPIO_STATUS_1_STATUS_CCI15_Msk                       (0x01UL << SGPIO_STATUS_1_STATUS_CCI15_Pos)               /*!< SGPIO STATUS_1: STATUS_CCI15 Mask   */

// -----------------------------------  SGPIO_CTR_STATUS_1  ---------------------------------------
#define SGPIO_CTR_STATUS_1_CTR_STATUS_CCI0_Pos                0                                                         /*!< SGPIO CTR_STATUS_1: CTR_STATUS_CCI0 Position */
#define SGPIO_CTR_STATUS_1_CTR_STATUS_CCI0_Msk                (0x01UL << SGPIO_CTR_STATUS_1_CTR_STATUS_CCI0_Pos)        /*!< SGPIO CTR_STATUS_1: CTR_STATUS_CCI0 Mask */
#define SGPIO_CTR_STATUS_1_CTR_STATUS_CCI1_Pos                1                                                         /*!< SGPIO CTR_STATUS_1: CTR_STATUS_CCI1 Position */
#define SGPIO_CTR_STATUS_1_CTR_STATUS_CCI1_Msk                (0x01UL << SGPIO_CTR_STATUS_1_CTR_STATUS_CCI1_Pos)        /*!< SGPIO CTR_STATUS_1: CTR_STATUS_CCI1 Mask */
#define SGPIO_CTR_STATUS_1_CTR_STATUS_CCI2_Pos                2                                                         /*!< SGPIO CTR_STATUS_1: CTR_STATUS_CCI2 Position */
#define SGPIO_CTR_STATUS_1_CTR_STATUS_CCI2_Msk                (0x01UL << SGPIO_CTR_STATUS_1_CTR_STATUS_CCI2_Pos)        /*!< SGPIO CTR_STATUS_1: CTR_STATUS_CCI2 Mask */
#define SGPIO_CTR_STATUS_1_CTR_STATUS_CCI3_Pos                3                                                         /*!< SGPIO CTR_STATUS_1: CTR_STATUS_CCI3 Position */
#define SGPIO_CTR_STATUS_1_CTR_STATUS_CCI3_Msk                (0x01UL << SGPIO_CTR_STATUS_1_CTR_STATUS_CCI3_Pos)        /*!< SGPIO CTR_STATUS_1: CTR_STATUS_CCI3 Mask */
#define SGPIO_CTR_STATUS_1_CTR_STATUS_CCI4_Pos                4                                                         /*!< SGPIO CTR_STATUS_1: CTR_STATUS_CCI4 Position */
#define SGPIO_CTR_STATUS_1_CTR_STATUS_CCI4_Msk                (0x01UL << SGPIO_CTR_STATUS_1_CTR_STATUS_CCI4_Pos)        /*!< SGPIO CTR_STATUS_1: CTR_STATUS_CCI4 Mask */
#define SGPIO_CTR_STATUS_1_CTR_STATUS_CCI5_Pos                5                                                         /*!< SGPIO CTR_STATUS_1: CTR_STATUS_CCI5 Position */
#define SGPIO_CTR_STATUS_1_CTR_STATUS_CCI5_Msk                (0x01UL << SGPIO_CTR_STATUS_1_CTR_STATUS_CCI5_Pos)        /*!< SGPIO CTR_STATUS_1: CTR_STATUS_CCI5 Mask */
#define SGPIO_CTR_STATUS_1_CTR_STATUS_CCI6_Pos                6                                                         /*!< SGPIO CTR_STATUS_1: CTR_STATUS_CCI6 Position */
#define SGPIO_CTR_STATUS_1_CTR_STATUS_CCI6_Msk                (0x01UL << SGPIO_CTR_STATUS_1_CTR_STATUS_CCI6_Pos)        /*!< SGPIO CTR_STATUS_1: CTR_STATUS_CCI6 Mask */
#define SGPIO_CTR_STATUS_1_CTR_STATUS_CCI7_Pos                7                                                         /*!< SGPIO CTR_STATUS_1: CTR_STATUS_CCI7 Position */
#define SGPIO_CTR_STATUS_1_CTR_STATUS_CCI7_Msk                (0x01UL << SGPIO_CTR_STATUS_1_CTR_STATUS_CCI7_Pos)        /*!< SGPIO CTR_STATUS_1: CTR_STATUS_CCI7 Mask */
#define SGPIO_CTR_STATUS_1_CTR_STATUS_CCI8_Pos                8                                                         /*!< SGPIO CTR_STATUS_1: CTR_STATUS_CCI8 Position */
#define SGPIO_CTR_STATUS_1_CTR_STATUS_CCI8_Msk                (0x01UL << SGPIO_CTR_STATUS_1_CTR_STATUS_CCI8_Pos)        /*!< SGPIO CTR_STATUS_1: CTR_STATUS_CCI8 Mask */
#define SGPIO_CTR_STATUS_1_CTR_STATUS_CCI9_Pos                9                                                         /*!< SGPIO CTR_STATUS_1: CTR_STATUS_CCI9 Position */
#define SGPIO_CTR_STATUS_1_CTR_STATUS_CCI9_Msk                (0x01UL << SGPIO_CTR_STATUS_1_CTR_STATUS_CCI9_Pos)        /*!< SGPIO CTR_STATUS_1: CTR_STATUS_CCI9 Mask */
#define SGPIO_CTR_STATUS_1_CTR_STATUS_CCI10_Pos               10                                                        /*!< SGPIO CTR_STATUS_1: CTR_STATUS_CCI10 Position */
#define SGPIO_CTR_STATUS_1_CTR_STATUS_CCI10_Msk               (0x01UL << SGPIO_CTR_STATUS_1_CTR_STATUS_CCI10_Pos)       /*!< SGPIO CTR_STATUS_1: CTR_STATUS_CCI10 Mask */
#define SGPIO_CTR_STATUS_1_CTR_STATUS_CCI11_Pos               11                                                        /*!< SGPIO CTR_STATUS_1: CTR_STATUS_CCI11 Position */
#define SGPIO_CTR_STATUS_1_CTR_STATUS_CCI11_Msk               (0x01UL << SGPIO_CTR_STATUS_1_CTR_STATUS_CCI11_Pos)       /*!< SGPIO CTR_STATUS_1: CTR_STATUS_CCI11 Mask */
#define SGPIO_CTR_STATUS_1_CTR_STATUS_CCI12_Pos               12                                                        /*!< SGPIO CTR_STATUS_1: CTR_STATUS_CCI12 Position */
#define SGPIO_CTR_STATUS_1_CTR_STATUS_CCI12_Msk               (0x01UL << SGPIO_CTR_STATUS_1_CTR_STATUS_CCI12_Pos)       /*!< SGPIO CTR_STATUS_1: CTR_STATUS_CCI12 Mask */
#define SGPIO_CTR_STATUS_1_CTR_STATUS_CCI13_Pos               13                                                        /*!< SGPIO CTR_STATUS_1: CTR_STATUS_CCI13 Position */
#define SGPIO_CTR_STATUS_1_CTR_STATUS_CCI13_Msk               (0x01UL << SGPIO_CTR_STATUS_1_CTR_STATUS_CCI13_Pos)       /*!< SGPIO CTR_STATUS_1: CTR_STATUS_CCI13 Mask */
#define SGPIO_CTR_STATUS_1_CTR_STATUS_CCI14_Pos               14                                                        /*!< SGPIO CTR_STATUS_1: CTR_STATUS_CCI14 Position */
#define SGPIO_CTR_STATUS_1_CTR_STATUS_CCI14_Msk               (0x01UL << SGPIO_CTR_STATUS_1_CTR_STATUS_CCI14_Pos)       /*!< SGPIO CTR_STATUS_1: CTR_STATUS_CCI14 Mask */
#define SGPIO_CTR_STATUS_1_CTR_STATUS_CCI15_Pos               15                                                        /*!< SGPIO CTR_STATUS_1: CTR_STATUS_CCI15 Position */
#define SGPIO_CTR_STATUS_1_CTR_STATUS_CCI15_Msk               (0x01UL << SGPIO_CTR_STATUS_1_CTR_STATUS_CCI15_Pos)       /*!< SGPIO CTR_STATUS_1: CTR_STATUS_CCI15 Mask */

// -----------------------------------  SGPIO_SET_STATUS_1  ---------------------------------------
#define SGPIO_SET_STATUS_1_CTR_STATUS_CCI0_Pos                0                                                         /*!< SGPIO SET_STATUS_1: CTR_STATUS_CCI0 Position */
#define SGPIO_SET_STATUS_1_CTR_STATUS_CCI0_Msk                (0x01UL << SGPIO_SET_STATUS_1_CTR_STATUS_CCI0_Pos)        /*!< SGPIO SET_STATUS_1: CTR_STATUS_CCI0 Mask */
#define SGPIO_SET_STATUS_1_CTR_STATUS_CCI1_Pos                1                                                         /*!< SGPIO SET_STATUS_1: CTR_STATUS_CCI1 Position */
#define SGPIO_SET_STATUS_1_CTR_STATUS_CCI1_Msk                (0x01UL << SGPIO_SET_STATUS_1_CTR_STATUS_CCI1_Pos)        /*!< SGPIO SET_STATUS_1: CTR_STATUS_CCI1 Mask */
#define SGPIO_SET_STATUS_1_CTR_STATUS_CCI2_Pos                2                                                         /*!< SGPIO SET_STATUS_1: CTR_STATUS_CCI2 Position */
#define SGPIO_SET_STATUS_1_CTR_STATUS_CCI2_Msk                (0x01UL << SGPIO_SET_STATUS_1_CTR_STATUS_CCI2_Pos)        /*!< SGPIO SET_STATUS_1: CTR_STATUS_CCI2 Mask */
#define SGPIO_SET_STATUS_1_CTR_STATUS_CCI3_Pos                3                                                         /*!< SGPIO SET_STATUS_1: CTR_STATUS_CCI3 Position */
#define SGPIO_SET_STATUS_1_CTR_STATUS_CCI3_Msk                (0x01UL << SGPIO_SET_STATUS_1_CTR_STATUS_CCI3_Pos)        /*!< SGPIO SET_STATUS_1: CTR_STATUS_CCI3 Mask */
#define SGPIO_SET_STATUS_1_CTR_STATUS_CCI4_Pos                4                                                         /*!< SGPIO SET_STATUS_1: CTR_STATUS_CCI4 Position */
#define SGPIO_SET_STATUS_1_CTR_STATUS_CCI4_Msk                (0x01UL << SGPIO_SET_STATUS_1_CTR_STATUS_CCI4_Pos)        /*!< SGPIO SET_STATUS_1: CTR_STATUS_CCI4 Mask */
#define SGPIO_SET_STATUS_1_CTR_STATUS_CCI5_Pos                5                                                         /*!< SGPIO SET_STATUS_1: CTR_STATUS_CCI5 Position */
#define SGPIO_SET_STATUS_1_CTR_STATUS_CCI5_Msk                (0x01UL << SGPIO_SET_STATUS_1_CTR_STATUS_CCI5_Pos)        /*!< SGPIO SET_STATUS_1: CTR_STATUS_CCI5 Mask */
#define SGPIO_SET_STATUS_1_CTR_STATUS_CCI6_Pos                6                                                         /*!< SGPIO SET_STATUS_1: CTR_STATUS_CCI6 Position */
#define SGPIO_SET_STATUS_1_CTR_STATUS_CCI6_Msk                (0x01UL << SGPIO_SET_STATUS_1_CTR_STATUS_CCI6_Pos)        /*!< SGPIO SET_STATUS_1: CTR_STATUS_CCI6 Mask */
#define SGPIO_SET_STATUS_1_CTR_STATUS_CCI7_Pos                7                                                         /*!< SGPIO SET_STATUS_1: CTR_STATUS_CCI7 Position */
#define SGPIO_SET_STATUS_1_CTR_STATUS_CCI7_Msk                (0x01UL << SGPIO_SET_STATUS_1_CTR_STATUS_CCI7_Pos)        /*!< SGPIO SET_STATUS_1: CTR_STATUS_CCI7 Mask */
#define SGPIO_SET_STATUS_1_CTR_STATUS_CCI8_Pos                8                                                         /*!< SGPIO SET_STATUS_1: CTR_STATUS_CCI8 Position */
#define SGPIO_SET_STATUS_1_CTR_STATUS_CCI8_Msk                (0x01UL << SGPIO_SET_STATUS_1_CTR_STATUS_CCI8_Pos)        /*!< SGPIO SET_STATUS_1: CTR_STATUS_CCI8 Mask */
#define SGPIO_SET_STATUS_1_CTR_STATUS_CCI9_Pos                9                                                         /*!< SGPIO SET_STATUS_1: CTR_STATUS_CCI9 Position */
#define SGPIO_SET_STATUS_1_CTR_STATUS_CCI9_Msk                (0x01UL << SGPIO_SET_STATUS_1_CTR_STATUS_CCI9_Pos)        /*!< SGPIO SET_STATUS_1: CTR_STATUS_CCI9 Mask */
#define SGPIO_SET_STATUS_1_CTR_STATUS_CCI10_Pos               10                                                        /*!< SGPIO SET_STATUS_1: CTR_STATUS_CCI10 Position */
#define SGPIO_SET_STATUS_1_CTR_STATUS_CCI10_Msk               (0x01UL << SGPIO_SET_STATUS_1_CTR_STATUS_CCI10_Pos)       /*!< SGPIO SET_STATUS_1: CTR_STATUS_CCI10 Mask */
#define SGPIO_SET_STATUS_1_CTR_STATUS_CCI11_Pos               11                                                        /*!< SGPIO SET_STATUS_1: CTR_STATUS_CCI11 Position */
#define SGPIO_SET_STATUS_1_CTR_STATUS_CCI11_Msk               (0x01UL << SGPIO_SET_STATUS_1_CTR_STATUS_CCI11_Pos)       /*!< SGPIO SET_STATUS_1: CTR_STATUS_CCI11 Mask */
#define SGPIO_SET_STATUS_1_CTR_STATUS_CCI12_Pos               12                                                        /*!< SGPIO SET_STATUS_1: CTR_STATUS_CCI12 Position */
#define SGPIO_SET_STATUS_1_CTR_STATUS_CCI12_Msk               (0x01UL << SGPIO_SET_STATUS_1_CTR_STATUS_CCI12_Pos)       /*!< SGPIO SET_STATUS_1: CTR_STATUS_CCI12 Mask */
#define SGPIO_SET_STATUS_1_CTR_STATUS_CCI13_Pos               13                                                        /*!< SGPIO SET_STATUS_1: CTR_STATUS_CCI13 Position */
#define SGPIO_SET_STATUS_1_CTR_STATUS_CCI13_Msk               (0x01UL << SGPIO_SET_STATUS_1_CTR_STATUS_CCI13_Pos)       /*!< SGPIO SET_STATUS_1: CTR_STATUS_CCI13 Mask */
#define SGPIO_SET_STATUS_1_CTR_STATUS_CCI14_Pos               14                                                        /*!< SGPIO SET_STATUS_1: CTR_STATUS_CCI14 Position */
#define SGPIO_SET_STATUS_1_CTR_STATUS_CCI14_Msk               (0x01UL << SGPIO_SET_STATUS_1_CTR_STATUS_CCI14_Pos)       /*!< SGPIO SET_STATUS_1: CTR_STATUS_CCI14 Mask */
#define SGPIO_SET_STATUS_1_CTR_STATUS_CCI15_Pos               15                                                        /*!< SGPIO SET_STATUS_1: CTR_STATUS_CCI15 Position */
#define SGPIO_SET_STATUS_1_CTR_STATUS_CCI15_Msk               (0x01UL << SGPIO_SET_STATUS_1_CTR_STATUS_CCI15_Pos)       /*!< SGPIO SET_STATUS_1: CTR_STATUS_CCI15 Mask */

// -------------------------------------  SGPIO_CLR_EN_2  -----------------------------------------
#define SGPIO_CLR_EN_2_CLR_EN2_PMI0_Pos                       0                                                         /*!< SGPIO CLR_EN_2: CLR_EN2_PMI0 Position */
#define SGPIO_CLR_EN_2_CLR_EN2_PMI0_Msk                       (0x01UL << SGPIO_CLR_EN_2_CLR_EN2_PMI0_Pos)               /*!< SGPIO CLR_EN_2: CLR_EN2_PMI0 Mask   */
#define SGPIO_CLR_EN_2_CLR_EN2_PMI1_Pos                       1                                                         /*!< SGPIO CLR_EN_2: CLR_EN2_PMI1 Position */
#define SGPIO_CLR_EN_2_CLR_EN2_PMI1_Msk                       (0x01UL << SGPIO_CLR_EN_2_CLR_EN2_PMI1_Pos)               /*!< SGPIO CLR_EN_2: CLR_EN2_PMI1 Mask   */
#define SGPIO_CLR_EN_2_CLR_EN2_PMI2_Pos                       2                                                         /*!< SGPIO CLR_EN_2: CLR_EN2_PMI2 Position */
#define SGPIO_CLR_EN_2_CLR_EN2_PMI2_Msk                       (0x01UL << SGPIO_CLR_EN_2_CLR_EN2_PMI2_Pos)               /*!< SGPIO CLR_EN_2: CLR_EN2_PMI2 Mask   */
#define SGPIO_CLR_EN_2_CLR_EN2_PMI3_Pos                       3                                                         /*!< SGPIO CLR_EN_2: CLR_EN2_PMI3 Position */
#define SGPIO_CLR_EN_2_CLR_EN2_PMI3_Msk                       (0x01UL << SGPIO_CLR_EN_2_CLR_EN2_PMI3_Pos)               /*!< SGPIO CLR_EN_2: CLR_EN2_PMI3 Mask   */
#define SGPIO_CLR_EN_2_CLR_EN2_PMI4_Pos                       4                                                         /*!< SGPIO CLR_EN_2: CLR_EN2_PMI4 Position */
#define SGPIO_CLR_EN_2_CLR_EN2_PMI4_Msk                       (0x01UL << SGPIO_CLR_EN_2_CLR_EN2_PMI4_Pos)               /*!< SGPIO CLR_EN_2: CLR_EN2_PMI4 Mask   */
#define SGPIO_CLR_EN_2_CLR_EN2_PMI5_Pos                       5                                                         /*!< SGPIO CLR_EN_2: CLR_EN2_PMI5 Position */
#define SGPIO_CLR_EN_2_CLR_EN2_PMI5_Msk                       (0x01UL << SGPIO_CLR_EN_2_CLR_EN2_PMI5_Pos)               /*!< SGPIO CLR_EN_2: CLR_EN2_PMI5 Mask   */
#define SGPIO_CLR_EN_2_CLR_EN2_PMI6_Pos                       6                                                         /*!< SGPIO CLR_EN_2: CLR_EN2_PMI6 Position */
#define SGPIO_CLR_EN_2_CLR_EN2_PMI6_Msk                       (0x01UL << SGPIO_CLR_EN_2_CLR_EN2_PMI6_Pos)               /*!< SGPIO CLR_EN_2: CLR_EN2_PMI6 Mask   */
#define SGPIO_CLR_EN_2_CLR_EN2_PMI7_Pos                       7                                                         /*!< SGPIO CLR_EN_2: CLR_EN2_PMI7 Position */
#define SGPIO_CLR_EN_2_CLR_EN2_PMI7_Msk                       (0x01UL << SGPIO_CLR_EN_2_CLR_EN2_PMI7_Pos)               /*!< SGPIO CLR_EN_2: CLR_EN2_PMI7 Mask   */
#define SGPIO_CLR_EN_2_CLR_EN2_PMI8_Pos                       8                                                         /*!< SGPIO CLR_EN_2: CLR_EN2_PMI8 Position */
#define SGPIO_CLR_EN_2_CLR_EN2_PMI8_Msk                       (0x01UL << SGPIO_CLR_EN_2_CLR_EN2_PMI8_Pos)               /*!< SGPIO CLR_EN_2: CLR_EN2_PMI8 Mask   */
#define SGPIO_CLR_EN_2_CLR_EN2_PMI9_Pos                       9                                                         /*!< SGPIO CLR_EN_2: CLR_EN2_PMI9 Position */
#define SGPIO_CLR_EN_2_CLR_EN2_PMI9_Msk                       (0x01UL << SGPIO_CLR_EN_2_CLR_EN2_PMI9_Pos)               /*!< SGPIO CLR_EN_2: CLR_EN2_PMI9 Mask   */
#define SGPIO_CLR_EN_2_CLR_EN2_PMI10_Pos                      10                                                        /*!< SGPIO CLR_EN_2: CLR_EN2_PMI10 Position */
#define SGPIO_CLR_EN_2_CLR_EN2_PMI10_Msk                      (0x01UL << SGPIO_CLR_EN_2_CLR_EN2_PMI10_Pos)              /*!< SGPIO CLR_EN_2: CLR_EN2_PMI10 Mask  */
#define SGPIO_CLR_EN_2_CLR_EN2_PMI11_Pos                      11                                                        /*!< SGPIO CLR_EN_2: CLR_EN2_PMI11 Position */
#define SGPIO_CLR_EN_2_CLR_EN2_PMI11_Msk                      (0x01UL << SGPIO_CLR_EN_2_CLR_EN2_PMI11_Pos)              /*!< SGPIO CLR_EN_2: CLR_EN2_PMI11 Mask  */
#define SGPIO_CLR_EN_2_CLR_EN2_PMI12_Pos                      12                                                        /*!< SGPIO CLR_EN_2: CLR_EN2_PMI12 Position */
#define SGPIO_CLR_EN_2_CLR_EN2_PMI12_Msk                      (0x01UL << SGPIO_CLR_EN_2_CLR_EN2_PMI12_Pos)              /*!< SGPIO CLR_EN_2: CLR_EN2_PMI12 Mask  */
#define SGPIO_CLR_EN_2_CLR_EN2_PMI13_Pos                      13                                                        /*!< SGPIO CLR_EN_2: CLR_EN2_PMI13 Position */
#define SGPIO_CLR_EN_2_CLR_EN2_PMI13_Msk                      (0x01UL << SGPIO_CLR_EN_2_CLR_EN2_PMI13_Pos)              /*!< SGPIO CLR_EN_2: CLR_EN2_PMI13 Mask  */
#define SGPIO_CLR_EN_2_CLR_EN2_PMI14_Pos                      14                                                        /*!< SGPIO CLR_EN_2: CLR_EN2_PMI14 Position */
#define SGPIO_CLR_EN_2_CLR_EN2_PMI14_Msk                      (0x01UL << SGPIO_CLR_EN_2_CLR_EN2_PMI14_Pos)              /*!< SGPIO CLR_EN_2: CLR_EN2_PMI14 Mask  */
#define SGPIO_CLR_EN_2_CLR_EN2_PMI15_Pos                      15                                                        /*!< SGPIO CLR_EN_2: CLR_EN2_PMI15 Position */
#define SGPIO_CLR_EN_2_CLR_EN2_PMI15_Msk                      (0x01UL << SGPIO_CLR_EN_2_CLR_EN2_PMI15_Pos)              /*!< SGPIO CLR_EN_2: CLR_EN2_PMI15 Mask  */

// -------------------------------------  SGPIO_SET_EN_2  -----------------------------------------
#define SGPIO_SET_EN_2_SET_EN_PMI0_Pos                        0                                                         /*!< SGPIO SET_EN_2: SET_EN_PMI0 Position */
#define SGPIO_SET_EN_2_SET_EN_PMI0_Msk                        (0x01UL << SGPIO_SET_EN_2_SET_EN_PMI0_Pos)                /*!< SGPIO SET_EN_2: SET_EN_PMI0 Mask    */
#define SGPIO_SET_EN_2_SET_EN_PMI1_Pos                        1                                                         /*!< SGPIO SET_EN_2: SET_EN_PMI1 Position */
#define SGPIO_SET_EN_2_SET_EN_PMI1_Msk                        (0x01UL << SGPIO_SET_EN_2_SET_EN_PMI1_Pos)                /*!< SGPIO SET_EN_2: SET_EN_PMI1 Mask    */
#define SGPIO_SET_EN_2_SET_EN_PMI2_Pos                        2                                                         /*!< SGPIO SET_EN_2: SET_EN_PMI2 Position */
#define SGPIO_SET_EN_2_SET_EN_PMI2_Msk                        (0x01UL << SGPIO_SET_EN_2_SET_EN_PMI2_Pos)                /*!< SGPIO SET_EN_2: SET_EN_PMI2 Mask    */
#define SGPIO_SET_EN_2_SET_EN_PMI3_Pos                        3                                                         /*!< SGPIO SET_EN_2: SET_EN_PMI3 Position */
#define SGPIO_SET_EN_2_SET_EN_PMI3_Msk                        (0x01UL << SGPIO_SET_EN_2_SET_EN_PMI3_Pos)                /*!< SGPIO SET_EN_2: SET_EN_PMI3 Mask    */
#define SGPIO_SET_EN_2_SET_EN_PMI4_Pos                        4                                                         /*!< SGPIO SET_EN_2: SET_EN_PMI4 Position */
#define SGPIO_SET_EN_2_SET_EN_PMI4_Msk                        (0x01UL << SGPIO_SET_EN_2_SET_EN_PMI4_Pos)                /*!< SGPIO SET_EN_2: SET_EN_PMI4 Mask    */
#define SGPIO_SET_EN_2_SET_EN_PMI5_Pos                        5                                                         /*!< SGPIO SET_EN_2: SET_EN_PMI5 Position */
#define SGPIO_SET_EN_2_SET_EN_PMI5_Msk                        (0x01UL << SGPIO_SET_EN_2_SET_EN_PMI5_Pos)                /*!< SGPIO SET_EN_2: SET_EN_PMI5 Mask    */
#define SGPIO_SET_EN_2_SET_EN_PMI6_Pos                        6                                                         /*!< SGPIO SET_EN_2: SET_EN_PMI6 Position */
#define SGPIO_SET_EN_2_SET_EN_PMI6_Msk                        (0x01UL << SGPIO_SET_EN_2_SET_EN_PMI6_Pos)                /*!< SGPIO SET_EN_2: SET_EN_PMI6 Mask    */
#define SGPIO_SET_EN_2_SET_EN_PMI7_Pos                        7                                                         /*!< SGPIO SET_EN_2: SET_EN_PMI7 Position */
#define SGPIO_SET_EN_2_SET_EN_PMI7_Msk                        (0x01UL << SGPIO_SET_EN_2_SET_EN_PMI7_Pos)                /*!< SGPIO SET_EN_2: SET_EN_PMI7 Mask    */
#define SGPIO_SET_EN_2_SET_EN_PMI8_Pos                        8                                                         /*!< SGPIO SET_EN_2: SET_EN_PMI8 Position */
#define SGPIO_SET_EN_2_SET_EN_PMI8_Msk                        (0x01UL << SGPIO_SET_EN_2_SET_EN_PMI8_Pos)                /*!< SGPIO SET_EN_2: SET_EN_PMI8 Mask    */
#define SGPIO_SET_EN_2_SET_EN_PMI9_Pos                        9                                                         /*!< SGPIO SET_EN_2: SET_EN_PMI9 Position */
#define SGPIO_SET_EN_2_SET_EN_PMI9_Msk                        (0x01UL << SGPIO_SET_EN_2_SET_EN_PMI9_Pos)                /*!< SGPIO SET_EN_2: SET_EN_PMI9 Mask    */
#define SGPIO_SET_EN_2_SET_EN_PMI10_Pos                       10                                                        /*!< SGPIO SET_EN_2: SET_EN_PMI10 Position */
#define SGPIO_SET_EN_2_SET_EN_PMI10_Msk                       (0x01UL << SGPIO_SET_EN_2_SET_EN_PMI10_Pos)               /*!< SGPIO SET_EN_2: SET_EN_PMI10 Mask   */
#define SGPIO_SET_EN_2_SET_EN_PMI11_Pos                       11                                                        /*!< SGPIO SET_EN_2: SET_EN_PMI11 Position */
#define SGPIO_SET_EN_2_SET_EN_PMI11_Msk                       (0x01UL << SGPIO_SET_EN_2_SET_EN_PMI11_Pos)               /*!< SGPIO SET_EN_2: SET_EN_PMI11 Mask   */
#define SGPIO_SET_EN_2_SET_EN_PMI12_Pos                       12                                                        /*!< SGPIO SET_EN_2: SET_EN_PMI12 Position */
#define SGPIO_SET_EN_2_SET_EN_PMI12_Msk                       (0x01UL << SGPIO_SET_EN_2_SET_EN_PMI12_Pos)               /*!< SGPIO SET_EN_2: SET_EN_PMI12 Mask   */
#define SGPIO_SET_EN_2_SET_EN_PMI13_Pos                       13                                                        /*!< SGPIO SET_EN_2: SET_EN_PMI13 Position */
#define SGPIO_SET_EN_2_SET_EN_PMI13_Msk                       (0x01UL << SGPIO_SET_EN_2_SET_EN_PMI13_Pos)               /*!< SGPIO SET_EN_2: SET_EN_PMI13 Mask   */
#define SGPIO_SET_EN_2_SET_EN_PMI14_Pos                       14                                                        /*!< SGPIO SET_EN_2: SET_EN_PMI14 Position */
#define SGPIO_SET_EN_2_SET_EN_PMI14_Msk                       (0x01UL << SGPIO_SET_EN_2_SET_EN_PMI14_Pos)               /*!< SGPIO SET_EN_2: SET_EN_PMI14 Mask   */
#define SGPIO_SET_EN_2_SET_EN_PMI15_Pos                       15                                                        /*!< SGPIO SET_EN_2: SET_EN_PMI15 Position */
#define SGPIO_SET_EN_2_SET_EN_PMI15_Msk                       (0x01UL << SGPIO_SET_EN_2_SET_EN_PMI15_Pos)               /*!< SGPIO SET_EN_2: SET_EN_PMI15 Mask   */

// -------------------------------------  SGPIO_ENABLE_2  -----------------------------------------
#define SGPIO_ENABLE_2_ENABLE_PMI0_Pos                        0                                                         /*!< SGPIO ENABLE_2: ENABLE_PMI0 Position */
#define SGPIO_ENABLE_2_ENABLE_PMI0_Msk                        (0x01UL << SGPIO_ENABLE_2_ENABLE_PMI0_Pos)                /*!< SGPIO ENABLE_2: ENABLE_PMI0 Mask    */
#define SGPIO_ENABLE_2_ENABLE_PMI1_Pos                        1                                                         /*!< SGPIO ENABLE_2: ENABLE_PMI1 Position */
#define SGPIO_ENABLE_2_ENABLE_PMI1_Msk                        (0x01UL << SGPIO_ENABLE_2_ENABLE_PMI1_Pos)                /*!< SGPIO ENABLE_2: ENABLE_PMI1 Mask    */
#define SGPIO_ENABLE_2_ENABLE_PMI2_Pos                        2                                                         /*!< SGPIO ENABLE_2: ENABLE_PMI2 Position */
#define SGPIO_ENABLE_2_ENABLE_PMI2_Msk                        (0x01UL << SGPIO_ENABLE_2_ENABLE_PMI2_Pos)                /*!< SGPIO ENABLE_2: ENABLE_PMI2 Mask    */
#define SGPIO_ENABLE_2_ENABLE_PMI3_Pos                        3                                                         /*!< SGPIO ENABLE_2: ENABLE_PMI3 Position */
#define SGPIO_ENABLE_2_ENABLE_PMI3_Msk                        (0x01UL << SGPIO_ENABLE_2_ENABLE_PMI3_Pos)                /*!< SGPIO ENABLE_2: ENABLE_PMI3 Mask    */
#define SGPIO_ENABLE_2_ENABLE_PMI4_Pos                        4                                                         /*!< SGPIO ENABLE_2: ENABLE_PMI4 Position */
#define SGPIO_ENABLE_2_ENABLE_PMI4_Msk                        (0x01UL << SGPIO_ENABLE_2_ENABLE_PMI4_Pos)                /*!< SGPIO ENABLE_2: ENABLE_PMI4 Mask    */
#define SGPIO_ENABLE_2_ENABLE_PMI5_Pos                        5                                                         /*!< SGPIO ENABLE_2: ENABLE_PMI5 Position */
#define SGPIO_ENABLE_2_ENABLE_PMI5_Msk                        (0x01UL << SGPIO_ENABLE_2_ENABLE_PMI5_Pos)                /*!< SGPIO ENABLE_2: ENABLE_PMI5 Mask    */
#define SGPIO_ENABLE_2_ENABLE_PMI6_Pos                        6                                                         /*!< SGPIO ENABLE_2: ENABLE_PMI6 Position */
#define SGPIO_ENABLE_2_ENABLE_PMI6_Msk                        (0x01UL << SGPIO_ENABLE_2_ENABLE_PMI6_Pos)                /*!< SGPIO ENABLE_2: ENABLE_PMI6 Mask    */
#define SGPIO_ENABLE_2_ENABLE_PMI7_Pos                        7                                                         /*!< SGPIO ENABLE_2: ENABLE_PMI7 Position */
#define SGPIO_ENABLE_2_ENABLE_PMI7_Msk                        (0x01UL << SGPIO_ENABLE_2_ENABLE_PMI7_Pos)                /*!< SGPIO ENABLE_2: ENABLE_PMI7 Mask    */
#define SGPIO_ENABLE_2_ENABLE_PMI8_Pos                        8                                                         /*!< SGPIO ENABLE_2: ENABLE_PMI8 Position */
#define SGPIO_ENABLE_2_ENABLE_PMI8_Msk                        (0x01UL << SGPIO_ENABLE_2_ENABLE_PMI8_Pos)                /*!< SGPIO ENABLE_2: ENABLE_PMI8 Mask    */
#define SGPIO_ENABLE_2_ENABLE_PMI9_Pos                        9                                                         /*!< SGPIO ENABLE_2: ENABLE_PMI9 Position */
#define SGPIO_ENABLE_2_ENABLE_PMI9_Msk                        (0x01UL << SGPIO_ENABLE_2_ENABLE_PMI9_Pos)                /*!< SGPIO ENABLE_2: ENABLE_PMI9 Mask    */
#define SGPIO_ENABLE_2_ENABLE_PMI10_Pos                       10                                                        /*!< SGPIO ENABLE_2: ENABLE_PMI10 Position */
#define SGPIO_ENABLE_2_ENABLE_PMI10_Msk                       (0x01UL << SGPIO_ENABLE_2_ENABLE_PMI10_Pos)               /*!< SGPIO ENABLE_2: ENABLE_PMI10 Mask   */
#define SGPIO_ENABLE_2_ENABLE_PMI11_Pos                       11                                                        /*!< SGPIO ENABLE_2: ENABLE_PMI11 Position */
#define SGPIO_ENABLE_2_ENABLE_PMI11_Msk                       (0x01UL << SGPIO_ENABLE_2_ENABLE_PMI11_Pos)               /*!< SGPIO ENABLE_2: ENABLE_PMI11 Mask   */
#define SGPIO_ENABLE_2_ENABLE_PMI12_Pos                       12                                                        /*!< SGPIO ENABLE_2: ENABLE_PMI12 Position */
#define SGPIO_ENABLE_2_ENABLE_PMI12_Msk                       (0x01UL << SGPIO_ENABLE_2_ENABLE_PMI12_Pos)               /*!< SGPIO ENABLE_2: ENABLE_PMI12 Mask   */
#define SGPIO_ENABLE_2_ENABLE_PMI13_Pos                       13                                                        /*!< SGPIO ENABLE_2: ENABLE_PMI13 Position */
#define SGPIO_ENABLE_2_ENABLE_PMI13_Msk                       (0x01UL << SGPIO_ENABLE_2_ENABLE_PMI13_Pos)               /*!< SGPIO ENABLE_2: ENABLE_PMI13 Mask   */
#define SGPIO_ENABLE_2_ENABLE_PMI14_Pos                       14                                                        /*!< SGPIO ENABLE_2: ENABLE_PMI14 Position */
#define SGPIO_ENABLE_2_ENABLE_PMI14_Msk                       (0x01UL << SGPIO_ENABLE_2_ENABLE_PMI14_Pos)               /*!< SGPIO ENABLE_2: ENABLE_PMI14 Mask   */
#define SGPIO_ENABLE_2_ENABLE_PMI15_Pos                       15                                                        /*!< SGPIO ENABLE_2: ENABLE_PMI15 Position */
#define SGPIO_ENABLE_2_ENABLE_PMI15_Msk                       (0x01UL << SGPIO_ENABLE_2_ENABLE_PMI15_Pos)               /*!< SGPIO ENABLE_2: ENABLE_PMI15 Mask   */

// -------------------------------------  SGPIO_STATUS_2  -----------------------------------------
#define SGPIO_STATUS_2_STATUS_PMI0_Pos                        0                                                         /*!< SGPIO STATUS_2: STATUS_PMI0 Position */
#define SGPIO_STATUS_2_STATUS_PMI0_Msk                        (0x01UL << SGPIO_STATUS_2_STATUS_PMI0_Pos)                /*!< SGPIO STATUS_2: STATUS_PMI0 Mask    */
#define SGPIO_STATUS_2_STATUS_PMI1_Pos                        1                                                         /*!< SGPIO STATUS_2: STATUS_PMI1 Position */
#define SGPIO_STATUS_2_STATUS_PMI1_Msk                        (0x01UL << SGPIO_STATUS_2_STATUS_PMI1_Pos)                /*!< SGPIO STATUS_2: STATUS_PMI1 Mask    */
#define SGPIO_STATUS_2_STATUS_PMI2_Pos                        2                                                         /*!< SGPIO STATUS_2: STATUS_PMI2 Position */
#define SGPIO_STATUS_2_STATUS_PMI2_Msk                        (0x01UL << SGPIO_STATUS_2_STATUS_PMI2_Pos)                /*!< SGPIO STATUS_2: STATUS_PMI2 Mask    */
#define SGPIO_STATUS_2_STATUS_PMI3_Pos                        3                                                         /*!< SGPIO STATUS_2: STATUS_PMI3 Position */
#define SGPIO_STATUS_2_STATUS_PMI3_Msk                        (0x01UL << SGPIO_STATUS_2_STATUS_PMI3_Pos)                /*!< SGPIO STATUS_2: STATUS_PMI3 Mask    */
#define SGPIO_STATUS_2_STATUS_PMI4_Pos                        4                                                         /*!< SGPIO STATUS_2: STATUS_PMI4 Position */
#define SGPIO_STATUS_2_STATUS_PMI4_Msk                        (0x01UL << SGPIO_STATUS_2_STATUS_PMI4_Pos)                /*!< SGPIO STATUS_2: STATUS_PMI4 Mask    */
#define SGPIO_STATUS_2_STATUS_PMI5_Pos                        5                                                         /*!< SGPIO STATUS_2: STATUS_PMI5 Position */
#define SGPIO_STATUS_2_STATUS_PMI5_Msk                        (0x01UL << SGPIO_STATUS_2_STATUS_PMI5_Pos)                /*!< SGPIO STATUS_2: STATUS_PMI5 Mask    */
#define SGPIO_STATUS_2_STATUS_PMI6_Pos                        6                                                         /*!< SGPIO STATUS_2: STATUS_PMI6 Position */
#define SGPIO_STATUS_2_STATUS_PMI6_Msk                        (0x01UL << SGPIO_STATUS_2_STATUS_PMI6_Pos)                /*!< SGPIO STATUS_2: STATUS_PMI6 Mask    */
#define SGPIO_STATUS_2_STATUS_PMI7_Pos                        7                                                         /*!< SGPIO STATUS_2: STATUS_PMI7 Position */
#define SGPIO_STATUS_2_STATUS_PMI7_Msk                        (0x01UL << SGPIO_STATUS_2_STATUS_PMI7_Pos)                /*!< SGPIO STATUS_2: STATUS_PMI7 Mask    */
#define SGPIO_STATUS_2_STATUS_PMI8_Pos                        8                                                         /*!< SGPIO STATUS_2: STATUS_PMI8 Position */
#define SGPIO_STATUS_2_STATUS_PMI8_Msk                        (0x01UL << SGPIO_STATUS_2_STATUS_PMI8_Pos)                /*!< SGPIO STATUS_2: STATUS_PMI8 Mask    */
#define SGPIO_STATUS_2_STATUS_PMI9_Pos                        9                                                         /*!< SGPIO STATUS_2: STATUS_PMI9 Position */
#define SGPIO_STATUS_2_STATUS_PMI9_Msk                        (0x01UL << SGPIO_STATUS_2_STATUS_PMI9_Pos)                /*!< SGPIO STATUS_2: STATUS_PMI9 Mask    */
#define SGPIO_STATUS_2_STATUS_PMI10_Pos                       10                                                        /*!< SGPIO STATUS_2: STATUS_PMI10 Position */
#define SGPIO_STATUS_2_STATUS_PMI10_Msk                       (0x01UL << SGPIO_STATUS_2_STATUS_PMI10_Pos)               /*!< SGPIO STATUS_2: STATUS_PMI10 Mask   */
#define SGPIO_STATUS_2_STATUS_PMI11_Pos                       11                                                        /*!< SGPIO STATUS_2: STATUS_PMI11 Position */
#define SGPIO_STATUS_2_STATUS_PMI11_Msk                       (0x01UL << SGPIO_STATUS_2_STATUS_PMI11_Pos)               /*!< SGPIO STATUS_2: STATUS_PMI11 Mask   */
#define SGPIO_STATUS_2_STATUS_PMI12_Pos                       12                                                        /*!< SGPIO STATUS_2: STATUS_PMI12 Position */
#define SGPIO_STATUS_2_STATUS_PMI12_Msk                       (0x01UL << SGPIO_STATUS_2_STATUS_PMI12_Pos)               /*!< SGPIO STATUS_2: STATUS_PMI12 Mask   */
#define SGPIO_STATUS_2_STATUS_PMI13_Pos                       13                                                        /*!< SGPIO STATUS_2: STATUS_PMI13 Position */
#define SGPIO_STATUS_2_STATUS_PMI13_Msk                       (0x01UL << SGPIO_STATUS_2_STATUS_PMI13_Pos)               /*!< SGPIO STATUS_2: STATUS_PMI13 Mask   */
#define SGPIO_STATUS_2_STATUS_PMI14_Pos                       14                                                        /*!< SGPIO STATUS_2: STATUS_PMI14 Position */
#define SGPIO_STATUS_2_STATUS_PMI14_Msk                       (0x01UL << SGPIO_STATUS_2_STATUS_PMI14_Pos)               /*!< SGPIO STATUS_2: STATUS_PMI14 Mask   */
#define SGPIO_STATUS_2_STATUS_PMI15_Pos                       15                                                        /*!< SGPIO STATUS_2: STATUS_PMI15 Position */
#define SGPIO_STATUS_2_STATUS_PMI15_Msk                       (0x01UL << SGPIO_STATUS_2_STATUS_PMI15_Pos)               /*!< SGPIO STATUS_2: STATUS_PMI15 Mask   */

// -----------------------------------  SGPIO_CTR_STATUS_2  ---------------------------------------
#define SGPIO_CTR_STATUS_2_CTR_STATUS_PMI0_Pos                0                                                         /*!< SGPIO CTR_STATUS_2: CTR_STATUS_PMI0 Position */
#define SGPIO_CTR_STATUS_2_CTR_STATUS_PMI0_Msk                (0x01UL << SGPIO_CTR_STATUS_2_CTR_STATUS_PMI0_Pos)        /*!< SGPIO CTR_STATUS_2: CTR_STATUS_PMI0 Mask */
#define SGPIO_CTR_STATUS_2_CTR_STATUS_PMI1_Pos                1                                                         /*!< SGPIO CTR_STATUS_2: CTR_STATUS_PMI1 Position */
#define SGPIO_CTR_STATUS_2_CTR_STATUS_PMI1_Msk                (0x01UL << SGPIO_CTR_STATUS_2_CTR_STATUS_PMI1_Pos)        /*!< SGPIO CTR_STATUS_2: CTR_STATUS_PMI1 Mask */
#define SGPIO_CTR_STATUS_2_CTR_STATUS_PMI2_Pos                2                                                         /*!< SGPIO CTR_STATUS_2: CTR_STATUS_PMI2 Position */
#define SGPIO_CTR_STATUS_2_CTR_STATUS_PMI2_Msk                (0x01UL << SGPIO_CTR_STATUS_2_CTR_STATUS_PMI2_Pos)        /*!< SGPIO CTR_STATUS_2: CTR_STATUS_PMI2 Mask */
#define SGPIO_CTR_STATUS_2_CTR_STATUS_PMI3_Pos                3                                                         /*!< SGPIO CTR_STATUS_2: CTR_STATUS_PMI3 Position */
#define SGPIO_CTR_STATUS_2_CTR_STATUS_PMI3_Msk                (0x01UL << SGPIO_CTR_STATUS_2_CTR_STATUS_PMI3_Pos)        /*!< SGPIO CTR_STATUS_2: CTR_STATUS_PMI3 Mask */
#define SGPIO_CTR_STATUS_2_CTR_STATUS_PMI4_Pos                4                                                         /*!< SGPIO CTR_STATUS_2: CTR_STATUS_PMI4 Position */
#define SGPIO_CTR_STATUS_2_CTR_STATUS_PMI4_Msk                (0x01UL << SGPIO_CTR_STATUS_2_CTR_STATUS_PMI4_Pos)        /*!< SGPIO CTR_STATUS_2: CTR_STATUS_PMI4 Mask */
#define SGPIO_CTR_STATUS_2_CTR_STATUS_PMI5_Pos                5                                                         /*!< SGPIO CTR_STATUS_2: CTR_STATUS_PMI5 Position */
#define SGPIO_CTR_STATUS_2_CTR_STATUS_PMI5_Msk                (0x01UL << SGPIO_CTR_STATUS_2_CTR_STATUS_PMI5_Pos)        /*!< SGPIO CTR_STATUS_2: CTR_STATUS_PMI5 Mask */
#define SGPIO_CTR_STATUS_2_CTR_STATUS_PMI6_Pos                6                                                         /*!< SGPIO CTR_STATUS_2: CTR_STATUS_PMI6 Position */
#define SGPIO_CTR_STATUS_2_CTR_STATUS_PMI6_Msk                (0x01UL << SGPIO_CTR_STATUS_2_CTR_STATUS_PMI6_Pos)        /*!< SGPIO CTR_STATUS_2: CTR_STATUS_PMI6 Mask */
#define SGPIO_CTR_STATUS_2_CTR_STATUS_PMI7_Pos                7                                                         /*!< SGPIO CTR_STATUS_2: CTR_STATUS_PMI7 Position */
#define SGPIO_CTR_STATUS_2_CTR_STATUS_PMI7_Msk                (0x01UL << SGPIO_CTR_STATUS_2_CTR_STATUS_PMI7_Pos)        /*!< SGPIO CTR_STATUS_2: CTR_STATUS_PMI7 Mask */
#define SGPIO_CTR_STATUS_2_CTR_STATUS_PMI8_Pos                8                                                         /*!< SGPIO CTR_STATUS_2: CTR_STATUS_PMI8 Position */
#define SGPIO_CTR_STATUS_2_CTR_STATUS_PMI8_Msk                (0x01UL << SGPIO_CTR_STATUS_2_CTR_STATUS_PMI8_Pos)        /*!< SGPIO CTR_STATUS_2: CTR_STATUS_PMI8 Mask */
#define SGPIO_CTR_STATUS_2_CTR_STATUS_PMI9_Pos                9                                                         /*!< SGPIO CTR_STATUS_2: CTR_STATUS_PMI9 Position */
#define SGPIO_CTR_STATUS_2_CTR_STATUS_PMI9_Msk                (0x01UL << SGPIO_CTR_STATUS_2_CTR_STATUS_PMI9_Pos)        /*!< SGPIO CTR_STATUS_2: CTR_STATUS_PMI9 Mask */
#define SGPIO_CTR_STATUS_2_CTR_STATUS_PMI10_Pos               10                                                        /*!< SGPIO CTR_STATUS_2: CTR_STATUS_PMI10 Position */
#define SGPIO_CTR_STATUS_2_CTR_STATUS_PMI10_Msk               (0x01UL << SGPIO_CTR_STATUS_2_CTR_STATUS_PMI10_Pos)       /*!< SGPIO CTR_STATUS_2: CTR_STATUS_PMI10 Mask */
#define SGPIO_CTR_STATUS_2_CTR_STATUS_PMI11_Pos               11                                                        /*!< SGPIO CTR_STATUS_2: CTR_STATUS_PMI11 Position */
#define SGPIO_CTR_STATUS_2_CTR_STATUS_PMI11_Msk               (0x01UL << SGPIO_CTR_STATUS_2_CTR_STATUS_PMI11_Pos)       /*!< SGPIO CTR_STATUS_2: CTR_STATUS_PMI11 Mask */
#define SGPIO_CTR_STATUS_2_CTR_STATUS_PMI12_Pos               12                                                        /*!< SGPIO CTR_STATUS_2: CTR_STATUS_PMI12 Position */
#define SGPIO_CTR_STATUS_2_CTR_STATUS_PMI12_Msk               (0x01UL << SGPIO_CTR_STATUS_2_CTR_STATUS_PMI12_Pos)       /*!< SGPIO CTR_STATUS_2: CTR_STATUS_PMI12 Mask */
#define SGPIO_CTR_STATUS_2_CTR_STATUS_PMI13_Pos               13                                                        /*!< SGPIO CTR_STATUS_2: CTR_STATUS_PMI13 Position */
#define SGPIO_CTR_STATUS_2_CTR_STATUS_PMI13_Msk               (0x01UL << SGPIO_CTR_STATUS_2_CTR_STATUS_PMI13_Pos)       /*!< SGPIO CTR_STATUS_2: CTR_STATUS_PMI13 Mask */
#define SGPIO_CTR_STATUS_2_CTR_STATUS_PMI14_Pos               14                                                        /*!< SGPIO CTR_STATUS_2: CTR_STATUS_PMI14 Position */
#define SGPIO_CTR_STATUS_2_CTR_STATUS_PMI14_Msk               (0x01UL << SGPIO_CTR_STATUS_2_CTR_STATUS_PMI14_Pos)       /*!< SGPIO CTR_STATUS_2: CTR_STATUS_PMI14 Mask */
#define SGPIO_CTR_STATUS_2_CTR_STATUS_PMI15_Pos               15                                                        /*!< SGPIO CTR_STATUS_2: CTR_STATUS_PMI15 Position */
#define SGPIO_CTR_STATUS_2_CTR_STATUS_PMI15_Msk               (0x01UL << SGPIO_CTR_STATUS_2_CTR_STATUS_PMI15_Pos)       /*!< SGPIO CTR_STATUS_2: CTR_STATUS_PMI15 Mask */

// -----------------------------------  SGPIO_SET_STATUS_2  ---------------------------------------
#define SGPIO_SET_STATUS_2_CTR_STATUS_PMI0_Pos                0                                                         /*!< SGPIO SET_STATUS_2: CTR_STATUS_PMI0 Position */
#define SGPIO_SET_STATUS_2_CTR_STATUS_PMI0_Msk                (0x01UL << SGPIO_SET_STATUS_2_CTR_STATUS_PMI0_Pos)        /*!< SGPIO SET_STATUS_2: CTR_STATUS_PMI0 Mask */
#define SGPIO_SET_STATUS_2_CTR_STATUS_PMI1_Pos                1                                                         /*!< SGPIO SET_STATUS_2: CTR_STATUS_PMI1 Position */
#define SGPIO_SET_STATUS_2_CTR_STATUS_PMI1_Msk                (0x01UL << SGPIO_SET_STATUS_2_CTR_STATUS_PMI1_Pos)        /*!< SGPIO SET_STATUS_2: CTR_STATUS_PMI1 Mask */
#define SGPIO_SET_STATUS_2_CTR_STATUS_PMI2_Pos                2                                                         /*!< SGPIO SET_STATUS_2: CTR_STATUS_PMI2 Position */
#define SGPIO_SET_STATUS_2_CTR_STATUS_PMI2_Msk                (0x01UL << SGPIO_SET_STATUS_2_CTR_STATUS_PMI2_Pos)        /*!< SGPIO SET_STATUS_2: CTR_STATUS_PMI2 Mask */
#define SGPIO_SET_STATUS_2_CTR_STATUS_PMI3_Pos                3                                                         /*!< SGPIO SET_STATUS_2: CTR_STATUS_PMI3 Position */
#define SGPIO_SET_STATUS_2_CTR_STATUS_PMI3_Msk                (0x01UL << SGPIO_SET_STATUS_2_CTR_STATUS_PMI3_Pos)        /*!< SGPIO SET_STATUS_2: CTR_STATUS_PMI3 Mask */
#define SGPIO_SET_STATUS_2_CTR_STATUS_PMI4_Pos                4                                                         /*!< SGPIO SET_STATUS_2: CTR_STATUS_PMI4 Position */
#define SGPIO_SET_STATUS_2_CTR_STATUS_PMI4_Msk                (0x01UL << SGPIO_SET_STATUS_2_CTR_STATUS_PMI4_Pos)        /*!< SGPIO SET_STATUS_2: CTR_STATUS_PMI4 Mask */
#define SGPIO_SET_STATUS_2_CTR_STATUS_PMI5_Pos                5                                                         /*!< SGPIO SET_STATUS_2: CTR_STATUS_PMI5 Position */
#define SGPIO_SET_STATUS_2_CTR_STATUS_PMI5_Msk                (0x01UL << SGPIO_SET_STATUS_2_CTR_STATUS_PMI5_Pos)        /*!< SGPIO SET_STATUS_2: CTR_STATUS_PMI5 Mask */
#define SGPIO_SET_STATUS_2_CTR_STATUS_PMI6_Pos                6                                                         /*!< SGPIO SET_STATUS_2: CTR_STATUS_PMI6 Position */
#define SGPIO_SET_STATUS_2_CTR_STATUS_PMI6_Msk                (0x01UL << SGPIO_SET_STATUS_2_CTR_STATUS_PMI6_Pos)        /*!< SGPIO SET_STATUS_2: CTR_STATUS_PMI6 Mask */
#define SGPIO_SET_STATUS_2_CTR_STATUS_PMI7_Pos                7                                                         /*!< SGPIO SET_STATUS_2: CTR_STATUS_PMI7 Position */
#define SGPIO_SET_STATUS_2_CTR_STATUS_PMI7_Msk                (0x01UL << SGPIO_SET_STATUS_2_CTR_STATUS_PMI7_Pos)        /*!< SGPIO SET_STATUS_2: CTR_STATUS_PMI7 Mask */
#define SGPIO_SET_STATUS_2_CTR_STATUS_PMI8_Pos                8                                                         /*!< SGPIO SET_STATUS_2: CTR_STATUS_PMI8 Position */
#define SGPIO_SET_STATUS_2_CTR_STATUS_PMI8_Msk                (0x01UL << SGPIO_SET_STATUS_2_CTR_STATUS_PMI8_Pos)        /*!< SGPIO SET_STATUS_2: CTR_STATUS_PMI8 Mask */
#define SGPIO_SET_STATUS_2_CTR_STATUS_PMI9_Pos                9                                                         /*!< SGPIO SET_STATUS_2: CTR_STATUS_PMI9 Position */
#define SGPIO_SET_STATUS_2_CTR_STATUS_PMI9_Msk                (0x01UL << SGPIO_SET_STATUS_2_CTR_STATUS_PMI9_Pos)        /*!< SGPIO SET_STATUS_2: CTR_STATUS_PMI9 Mask */
#define SGPIO_SET_STATUS_2_CTR_STATUS_PMI10_Pos               10                                                        /*!< SGPIO SET_STATUS_2: CTR_STATUS_PMI10 Position */
#define SGPIO_SET_STATUS_2_CTR_STATUS_PMI10_Msk               (0x01UL << SGPIO_SET_STATUS_2_CTR_STATUS_PMI10_Pos)       /*!< SGPIO SET_STATUS_2: CTR_STATUS_PMI10 Mask */
#define SGPIO_SET_STATUS_2_CTR_STATUS_PMI11_Pos               11                                                        /*!< SGPIO SET_STATUS_2: CTR_STATUS_PMI11 Position */
#define SGPIO_SET_STATUS_2_CTR_STATUS_PMI11_Msk               (0x01UL << SGPIO_SET_STATUS_2_CTR_STATUS_PMI11_Pos)       /*!< SGPIO SET_STATUS_2: CTR_STATUS_PMI11 Mask */
#define SGPIO_SET_STATUS_2_CTR_STATUS_PMI12_Pos               12                                                        /*!< SGPIO SET_STATUS_2: CTR_STATUS_PMI12 Position */
#define SGPIO_SET_STATUS_2_CTR_STATUS_PMI12_Msk               (0x01UL << SGPIO_SET_STATUS_2_CTR_STATUS_PMI12_Pos)       /*!< SGPIO SET_STATUS_2: CTR_STATUS_PMI12 Mask */
#define SGPIO_SET_STATUS_2_CTR_STATUS_PMI13_Pos               13                                                        /*!< SGPIO SET_STATUS_2: CTR_STATUS_PMI13 Position */
#define SGPIO_SET_STATUS_2_CTR_STATUS_PMI13_Msk               (0x01UL << SGPIO_SET_STATUS_2_CTR_STATUS_PMI13_Pos)       /*!< SGPIO SET_STATUS_2: CTR_STATUS_PMI13 Mask */
#define SGPIO_SET_STATUS_2_CTR_STATUS_PMI14_Pos               14                                                        /*!< SGPIO SET_STATUS_2: CTR_STATUS_PMI14 Position */
#define SGPIO_SET_STATUS_2_CTR_STATUS_PMI14_Msk               (0x01UL << SGPIO_SET_STATUS_2_CTR_STATUS_PMI14_Pos)       /*!< SGPIO SET_STATUS_2: CTR_STATUS_PMI14 Mask */
#define SGPIO_SET_STATUS_2_CTR_STATUS_PMI15_Pos               15                                                        /*!< SGPIO SET_STATUS_2: CTR_STATUS_PMI15 Position */
#define SGPIO_SET_STATUS_2_CTR_STATUS_PMI15_Msk               (0x01UL << SGPIO_SET_STATUS_2_CTR_STATUS_PMI15_Pos)       /*!< SGPIO SET_STATUS_2: CTR_STATUS_PMI15 Mask */

// -------------------------------------  SGPIO_CLR_EN_3  -----------------------------------------
#define SGPIO_CLR_EN_3_CLR_EN_INPI0_Pos                       0                                                         /*!< SGPIO CLR_EN_3: CLR_EN_INPI0 Position */
#define SGPIO_CLR_EN_3_CLR_EN_INPI0_Msk                       (0x01UL << SGPIO_CLR_EN_3_CLR_EN_INPI0_Pos)               /*!< SGPIO CLR_EN_3: CLR_EN_INPI0 Mask   */
#define SGPIO_CLR_EN_3_CLR_EN_INPI1_Pos                       1                                                         /*!< SGPIO CLR_EN_3: CLR_EN_INPI1 Position */
#define SGPIO_CLR_EN_3_CLR_EN_INPI1_Msk                       (0x01UL << SGPIO_CLR_EN_3_CLR_EN_INPI1_Pos)               /*!< SGPIO CLR_EN_3: CLR_EN_INPI1 Mask   */
#define SGPIO_CLR_EN_3_CLR_EN_INPI2_Pos                       2                                                         /*!< SGPIO CLR_EN_3: CLR_EN_INPI2 Position */
#define SGPIO_CLR_EN_3_CLR_EN_INPI2_Msk                       (0x01UL << SGPIO_CLR_EN_3_CLR_EN_INPI2_Pos)               /*!< SGPIO CLR_EN_3: CLR_EN_INPI2 Mask   */
#define SGPIO_CLR_EN_3_CLR_EN_INPI3_Pos                       3                                                         /*!< SGPIO CLR_EN_3: CLR_EN_INPI3 Position */
#define SGPIO_CLR_EN_3_CLR_EN_INPI3_Msk                       (0x01UL << SGPIO_CLR_EN_3_CLR_EN_INPI3_Pos)               /*!< SGPIO CLR_EN_3: CLR_EN_INPI3 Mask   */
#define SGPIO_CLR_EN_3_CLR_EN_INPI4_Pos                       4                                                         /*!< SGPIO CLR_EN_3: CLR_EN_INPI4 Position */
#define SGPIO_CLR_EN_3_CLR_EN_INPI4_Msk                       (0x01UL << SGPIO_CLR_EN_3_CLR_EN_INPI4_Pos)               /*!< SGPIO CLR_EN_3: CLR_EN_INPI4 Mask   */
#define SGPIO_CLR_EN_3_CLR_EN_INPI5_Pos                       5                                                         /*!< SGPIO CLR_EN_3: CLR_EN_INPI5 Position */
#define SGPIO_CLR_EN_3_CLR_EN_INPI5_Msk                       (0x01UL << SGPIO_CLR_EN_3_CLR_EN_INPI5_Pos)               /*!< SGPIO CLR_EN_3: CLR_EN_INPI5 Mask   */
#define SGPIO_CLR_EN_3_CLR_EN_INPI6_Pos                       6                                                         /*!< SGPIO CLR_EN_3: CLR_EN_INPI6 Position */
#define SGPIO_CLR_EN_3_CLR_EN_INPI6_Msk                       (0x01UL << SGPIO_CLR_EN_3_CLR_EN_INPI6_Pos)               /*!< SGPIO CLR_EN_3: CLR_EN_INPI6 Mask   */
#define SGPIO_CLR_EN_3_CLR_EN_INPI7_Pos                       7                                                         /*!< SGPIO CLR_EN_3: CLR_EN_INPI7 Position */
#define SGPIO_CLR_EN_3_CLR_EN_INPI7_Msk                       (0x01UL << SGPIO_CLR_EN_3_CLR_EN_INPI7_Pos)               /*!< SGPIO CLR_EN_3: CLR_EN_INPI7 Mask   */
#define SGPIO_CLR_EN_3_CLR_EN_INPI8_Pos                       8                                                         /*!< SGPIO CLR_EN_3: CLR_EN_INPI8 Position */
#define SGPIO_CLR_EN_3_CLR_EN_INPI8_Msk                       (0x01UL << SGPIO_CLR_EN_3_CLR_EN_INPI8_Pos)               /*!< SGPIO CLR_EN_3: CLR_EN_INPI8 Mask   */
#define SGPIO_CLR_EN_3_CLR_EN_INPI9_Pos                       9                                                         /*!< SGPIO CLR_EN_3: CLR_EN_INPI9 Position */
#define SGPIO_CLR_EN_3_CLR_EN_INPI9_Msk                       (0x01UL << SGPIO_CLR_EN_3_CLR_EN_INPI9_Pos)               /*!< SGPIO CLR_EN_3: CLR_EN_INPI9 Mask   */
#define SGPIO_CLR_EN_3_CLR_EN_INPI10_Pos                      10                                                        /*!< SGPIO CLR_EN_3: CLR_EN_INPI10 Position */
#define SGPIO_CLR_EN_3_CLR_EN_INPI10_Msk                      (0x01UL << SGPIO_CLR_EN_3_CLR_EN_INPI10_Pos)              /*!< SGPIO CLR_EN_3: CLR_EN_INPI10 Mask  */
#define SGPIO_CLR_EN_3_CLR_EN_INPI11_Pos                      11                                                        /*!< SGPIO CLR_EN_3: CLR_EN_INPI11 Position */
#define SGPIO_CLR_EN_3_CLR_EN_INPI11_Msk                      (0x01UL << SGPIO_CLR_EN_3_CLR_EN_INPI11_Pos)              /*!< SGPIO CLR_EN_3: CLR_EN_INPI11 Mask  */
#define SGPIO_CLR_EN_3_CLR_EN_INPI12_Pos                      12                                                        /*!< SGPIO CLR_EN_3: CLR_EN_INPI12 Position */
#define SGPIO_CLR_EN_3_CLR_EN_INPI12_Msk                      (0x01UL << SGPIO_CLR_EN_3_CLR_EN_INPI12_Pos)              /*!< SGPIO CLR_EN_3: CLR_EN_INPI12 Mask  */
#define SGPIO_CLR_EN_3_CLR_EN_INPI13_Pos                      13                                                        /*!< SGPIO CLR_EN_3: CLR_EN_INPI13 Position */
#define SGPIO_CLR_EN_3_CLR_EN_INPI13_Msk                      (0x01UL << SGPIO_CLR_EN_3_CLR_EN_INPI13_Pos)              /*!< SGPIO CLR_EN_3: CLR_EN_INPI13 Mask  */
#define SGPIO_CLR_EN_3_CLR_EN_INPI14_Pos                      14                                                        /*!< SGPIO CLR_EN_3: CLR_EN_INPI14 Position */
#define SGPIO_CLR_EN_3_CLR_EN_INPI14_Msk                      (0x01UL << SGPIO_CLR_EN_3_CLR_EN_INPI14_Pos)              /*!< SGPIO CLR_EN_3: CLR_EN_INPI14 Mask  */
#define SGPIO_CLR_EN_3_CLR_EN_INPI15_Pos                      15                                                        /*!< SGPIO CLR_EN_3: CLR_EN_INPI15 Position */
#define SGPIO_CLR_EN_3_CLR_EN_INPI15_Msk                      (0x01UL << SGPIO_CLR_EN_3_CLR_EN_INPI15_Pos)              /*!< SGPIO CLR_EN_3: CLR_EN_INPI15 Mask  */

// -------------------------------------  SGPIO_SET_EN_3  -----------------------------------------
#define SGPIO_SET_EN_3_SET_EN_INPI0_Pos                       0                                                         /*!< SGPIO SET_EN_3: SET_EN_INPI0 Position */
#define SGPIO_SET_EN_3_SET_EN_INPI0_Msk                       (0x01UL << SGPIO_SET_EN_3_SET_EN_INPI0_Pos)               /*!< SGPIO SET_EN_3: SET_EN_INPI0 Mask   */
#define SGPIO_SET_EN_3_SET_EN_INPI1_Pos                       1                                                         /*!< SGPIO SET_EN_3: SET_EN_INPI1 Position */
#define SGPIO_SET_EN_3_SET_EN_INPI1_Msk                       (0x01UL << SGPIO_SET_EN_3_SET_EN_INPI1_Pos)               /*!< SGPIO SET_EN_3: SET_EN_INPI1 Mask   */
#define SGPIO_SET_EN_3_SET_EN_INPI2_Pos                       2                                                         /*!< SGPIO SET_EN_3: SET_EN_INPI2 Position */
#define SGPIO_SET_EN_3_SET_EN_INPI2_Msk                       (0x01UL << SGPIO_SET_EN_3_SET_EN_INPI2_Pos)               /*!< SGPIO SET_EN_3: SET_EN_INPI2 Mask   */
#define SGPIO_SET_EN_3_SET_EN_INPI3_Pos                       3                                                         /*!< SGPIO SET_EN_3: SET_EN_INPI3 Position */
#define SGPIO_SET_EN_3_SET_EN_INPI3_Msk                       (0x01UL << SGPIO_SET_EN_3_SET_EN_INPI3_Pos)               /*!< SGPIO SET_EN_3: SET_EN_INPI3 Mask   */
#define SGPIO_SET_EN_3_SET_EN_INPI4_Pos                       4                                                         /*!< SGPIO SET_EN_3: SET_EN_INPI4 Position */
#define SGPIO_SET_EN_3_SET_EN_INPI4_Msk                       (0x01UL << SGPIO_SET_EN_3_SET_EN_INPI4_Pos)               /*!< SGPIO SET_EN_3: SET_EN_INPI4 Mask   */
#define SGPIO_SET_EN_3_SET_EN_INPI5_Pos                       5                                                         /*!< SGPIO SET_EN_3: SET_EN_INPI5 Position */
#define SGPIO_SET_EN_3_SET_EN_INPI5_Msk                       (0x01UL << SGPIO_SET_EN_3_SET_EN_INPI5_Pos)               /*!< SGPIO SET_EN_3: SET_EN_INPI5 Mask   */
#define SGPIO_SET_EN_3_SET_EN_INPI6_Pos                       6                                                         /*!< SGPIO SET_EN_3: SET_EN_INPI6 Position */
#define SGPIO_SET_EN_3_SET_EN_INPI6_Msk                       (0x01UL << SGPIO_SET_EN_3_SET_EN_INPI6_Pos)               /*!< SGPIO SET_EN_3: SET_EN_INPI6 Mask   */
#define SGPIO_SET_EN_3_SET_EN_INPI7_Pos                       7                                                         /*!< SGPIO SET_EN_3: SET_EN_INPI7 Position */
#define SGPIO_SET_EN_3_SET_EN_INPI7_Msk                       (0x01UL << SGPIO_SET_EN_3_SET_EN_INPI7_Pos)               /*!< SGPIO SET_EN_3: SET_EN_INPI7 Mask   */
#define SGPIO_SET_EN_3_SET_EN_INPI8_Pos                       8                                                         /*!< SGPIO SET_EN_3: SET_EN_INPI8 Position */
#define SGPIO_SET_EN_3_SET_EN_INPI8_Msk                       (0x01UL << SGPIO_SET_EN_3_SET_EN_INPI8_Pos)               /*!< SGPIO SET_EN_3: SET_EN_INPI8 Mask   */
#define SGPIO_SET_EN_3_SET_EN_INPI9_Pos                       9                                                         /*!< SGPIO SET_EN_3: SET_EN_INPI9 Position */
#define SGPIO_SET_EN_3_SET_EN_INPI9_Msk                       (0x01UL << SGPIO_SET_EN_3_SET_EN_INPI9_Pos)               /*!< SGPIO SET_EN_3: SET_EN_INPI9 Mask   */
#define SGPIO_SET_EN_3_SET_EN_INPI10_Pos                      10                                                        /*!< SGPIO SET_EN_3: SET_EN_INPI10 Position */
#define SGPIO_SET_EN_3_SET_EN_INPI10_Msk                      (0x01UL << SGPIO_SET_EN_3_SET_EN_INPI10_Pos)              /*!< SGPIO SET_EN_3: SET_EN_INPI10 Mask  */
#define SGPIO_SET_EN_3_SET_EN_INPI11_Pos                      11                                                        /*!< SGPIO SET_EN_3: SET_EN_INPI11 Position */
#define SGPIO_SET_EN_3_SET_EN_INPI11_Msk                      (0x01UL << SGPIO_SET_EN_3_SET_EN_INPI11_Pos)              /*!< SGPIO SET_EN_3: SET_EN_INPI11 Mask  */
#define SGPIO_SET_EN_3_SET_EN_INPI12_Pos                      12                                                        /*!< SGPIO SET_EN_3: SET_EN_INPI12 Position */
#define SGPIO_SET_EN_3_SET_EN_INPI12_Msk                      (0x01UL << SGPIO_SET_EN_3_SET_EN_INPI12_Pos)              /*!< SGPIO SET_EN_3: SET_EN_INPI12 Mask  */
#define SGPIO_SET_EN_3_SET_EN_INPI13_Pos                      13                                                        /*!< SGPIO SET_EN_3: SET_EN_INPI13 Position */
#define SGPIO_SET_EN_3_SET_EN_INPI13_Msk                      (0x01UL << SGPIO_SET_EN_3_SET_EN_INPI13_Pos)              /*!< SGPIO SET_EN_3: SET_EN_INPI13 Mask  */
#define SGPIO_SET_EN_3_SET_EN_INPI14_Pos                      14                                                        /*!< SGPIO SET_EN_3: SET_EN_INPI14 Position */
#define SGPIO_SET_EN_3_SET_EN_INPI14_Msk                      (0x01UL << SGPIO_SET_EN_3_SET_EN_INPI14_Pos)              /*!< SGPIO SET_EN_3: SET_EN_INPI14 Mask  */
#define SGPIO_SET_EN_3_SET_EN_INPI15_Pos                      15                                                        /*!< SGPIO SET_EN_3: SET_EN_INPI15 Position */
#define SGPIO_SET_EN_3_SET_EN_INPI15_Msk                      (0x01UL << SGPIO_SET_EN_3_SET_EN_INPI15_Pos)              /*!< SGPIO SET_EN_3: SET_EN_INPI15 Mask  */

// -------------------------------------  SGPIO_ENABLE_3  -----------------------------------------
#define SGPIO_ENABLE_3_ENABLE3_INPI0_Pos                      0                                                         /*!< SGPIO ENABLE_3: ENABLE3_INPI0 Position */
#define SGPIO_ENABLE_3_ENABLE3_INPI0_Msk                      (0x01UL << SGPIO_ENABLE_3_ENABLE3_INPI0_Pos)              /*!< SGPIO ENABLE_3: ENABLE3_INPI0 Mask  */
#define SGPIO_ENABLE_3_ENABLE3_INPI1_Pos                      1                                                         /*!< SGPIO ENABLE_3: ENABLE3_INPI1 Position */
#define SGPIO_ENABLE_3_ENABLE3_INPI1_Msk                      (0x01UL << SGPIO_ENABLE_3_ENABLE3_INPI1_Pos)              /*!< SGPIO ENABLE_3: ENABLE3_INPI1 Mask  */
#define SGPIO_ENABLE_3_ENABLE3_INPI2_Pos                      2                                                         /*!< SGPIO ENABLE_3: ENABLE3_INPI2 Position */
#define SGPIO_ENABLE_3_ENABLE3_INPI2_Msk                      (0x01UL << SGPIO_ENABLE_3_ENABLE3_INPI2_Pos)              /*!< SGPIO ENABLE_3: ENABLE3_INPI2 Mask  */
#define SGPIO_ENABLE_3_ENABLE3_INPI3_Pos                      3                                                         /*!< SGPIO ENABLE_3: ENABLE3_INPI3 Position */
#define SGPIO_ENABLE_3_ENABLE3_INPI3_Msk                      (0x01UL << SGPIO_ENABLE_3_ENABLE3_INPI3_Pos)              /*!< SGPIO ENABLE_3: ENABLE3_INPI3 Mask  */
#define SGPIO_ENABLE_3_ENABLE3_INPI4_Pos                      4                                                         /*!< SGPIO ENABLE_3: ENABLE3_INPI4 Position */
#define SGPIO_ENABLE_3_ENABLE3_INPI4_Msk                      (0x01UL << SGPIO_ENABLE_3_ENABLE3_INPI4_Pos)              /*!< SGPIO ENABLE_3: ENABLE3_INPI4 Mask  */
#define SGPIO_ENABLE_3_ENABLE3_INPI5_Pos                      5                                                         /*!< SGPIO ENABLE_3: ENABLE3_INPI5 Position */
#define SGPIO_ENABLE_3_ENABLE3_INPI5_Msk                      (0x01UL << SGPIO_ENABLE_3_ENABLE3_INPI5_Pos)              /*!< SGPIO ENABLE_3: ENABLE3_INPI5 Mask  */
#define SGPIO_ENABLE_3_ENABLE3_INPI6_Pos                      6                                                         /*!< SGPIO ENABLE_3: ENABLE3_INPI6 Position */
#define SGPIO_ENABLE_3_ENABLE3_INPI6_Msk                      (0x01UL << SGPIO_ENABLE_3_ENABLE3_INPI6_Pos)              /*!< SGPIO ENABLE_3: ENABLE3_INPI6 Mask  */
#define SGPIO_ENABLE_3_ENABLE3_INPI7_Pos                      7                                                         /*!< SGPIO ENABLE_3: ENABLE3_INPI7 Position */
#define SGPIO_ENABLE_3_ENABLE3_INPI7_Msk                      (0x01UL << SGPIO_ENABLE_3_ENABLE3_INPI7_Pos)              /*!< SGPIO ENABLE_3: ENABLE3_INPI7 Mask  */
#define SGPIO_ENABLE_3_ENABLE3_INPI8_Pos                      8                                                         /*!< SGPIO ENABLE_3: ENABLE3_INPI8 Position */
#define SGPIO_ENABLE_3_ENABLE3_INPI8_Msk                      (0x01UL << SGPIO_ENABLE_3_ENABLE3_INPI8_Pos)              /*!< SGPIO ENABLE_3: ENABLE3_INPI8 Mask  */
#define SGPIO_ENABLE_3_ENABLE3_INPI9_Pos                      9                                                         /*!< SGPIO ENABLE_3: ENABLE3_INPI9 Position */
#define SGPIO_ENABLE_3_ENABLE3_INPI9_Msk                      (0x01UL << SGPIO_ENABLE_3_ENABLE3_INPI9_Pos)              /*!< SGPIO ENABLE_3: ENABLE3_INPI9 Mask  */
#define SGPIO_ENABLE_3_ENABLE3_INPI10_Pos                     10                                                        /*!< SGPIO ENABLE_3: ENABLE3_INPI10 Position */
#define SGPIO_ENABLE_3_ENABLE3_INPI10_Msk                     (0x01UL << SGPIO_ENABLE_3_ENABLE3_INPI10_Pos)             /*!< SGPIO ENABLE_3: ENABLE3_INPI10 Mask */
#define SGPIO_ENABLE_3_ENABLE3_INPI11_Pos                     11                                                        /*!< SGPIO ENABLE_3: ENABLE3_INPI11 Position */
#define SGPIO_ENABLE_3_ENABLE3_INPI11_Msk                     (0x01UL << SGPIO_ENABLE_3_ENABLE3_INPI11_Pos)             /*!< SGPIO ENABLE_3: ENABLE3_INPI11 Mask */
#define SGPIO_ENABLE_3_ENABLE3_INPI12_Pos                     12                                                        /*!< SGPIO ENABLE_3: ENABLE3_INPI12 Position */
#define SGPIO_ENABLE_3_ENABLE3_INPI12_Msk                     (0x01UL << SGPIO_ENABLE_3_ENABLE3_INPI12_Pos)             /*!< SGPIO ENABLE_3: ENABLE3_INPI12 Mask */
#define SGPIO_ENABLE_3_ENABLE3_INPI13_Pos                     13                                                        /*!< SGPIO ENABLE_3: ENABLE3_INPI13 Position */
#define SGPIO_ENABLE_3_ENABLE3_INPI13_Msk                     (0x01UL << SGPIO_ENABLE_3_ENABLE3_INPI13_Pos)             /*!< SGPIO ENABLE_3: ENABLE3_INPI13 Mask */
#define SGPIO_ENABLE_3_ENABLE3_INPI14_Pos                     14                                                        /*!< SGPIO ENABLE_3: ENABLE3_INPI14 Position */
#define SGPIO_ENABLE_3_ENABLE3_INPI14_Msk                     (0x01UL << SGPIO_ENABLE_3_ENABLE3_INPI14_Pos)             /*!< SGPIO ENABLE_3: ENABLE3_INPI14 Mask */
#define SGPIO_ENABLE_3_ENABLE3_INPI15_Pos                     15                                                        /*!< SGPIO ENABLE_3: ENABLE3_INPI15 Position */
#define SGPIO_ENABLE_3_ENABLE3_INPI15_Msk                     (0x01UL << SGPIO_ENABLE_3_ENABLE3_INPI15_Pos)             /*!< SGPIO ENABLE_3: ENABLE3_INPI15 Mask */

// -------------------------------------  SGPIO_STATUS_3  -----------------------------------------
#define SGPIO_STATUS_3_STATUS_INPI0_Pos                       0                                                         /*!< SGPIO STATUS_3: STATUS_INPI0 Position */
#define SGPIO_STATUS_3_STATUS_INPI0_Msk                       (0x01UL << SGPIO_STATUS_3_STATUS_INPI0_Pos)               /*!< SGPIO STATUS_3: STATUS_INPI0 Mask   */
#define SGPIO_STATUS_3_STATUS_INPI1_Pos                       1                                                         /*!< SGPIO STATUS_3: STATUS_INPI1 Position */
#define SGPIO_STATUS_3_STATUS_INPI1_Msk                       (0x01UL << SGPIO_STATUS_3_STATUS_INPI1_Pos)               /*!< SGPIO STATUS_3: STATUS_INPI1 Mask   */
#define SGPIO_STATUS_3_STATUS_INPI2_Pos                       2                                                         /*!< SGPIO STATUS_3: STATUS_INPI2 Position */
#define SGPIO_STATUS_3_STATUS_INPI2_Msk                       (0x01UL << SGPIO_STATUS_3_STATUS_INPI2_Pos)               /*!< SGPIO STATUS_3: STATUS_INPI2 Mask   */
#define SGPIO_STATUS_3_STATUS_INPI3_Pos                       3                                                         /*!< SGPIO STATUS_3: STATUS_INPI3 Position */
#define SGPIO_STATUS_3_STATUS_INPI3_Msk                       (0x01UL << SGPIO_STATUS_3_STATUS_INPI3_Pos)               /*!< SGPIO STATUS_3: STATUS_INPI3 Mask   */
#define SGPIO_STATUS_3_STATUS_INPI4_Pos                       4                                                         /*!< SGPIO STATUS_3: STATUS_INPI4 Position */
#define SGPIO_STATUS_3_STATUS_INPI4_Msk                       (0x01UL << SGPIO_STATUS_3_STATUS_INPI4_Pos)               /*!< SGPIO STATUS_3: STATUS_INPI4 Mask   */
#define SGPIO_STATUS_3_STATUS_INPI5_Pos                       5                                                         /*!< SGPIO STATUS_3: STATUS_INPI5 Position */
#define SGPIO_STATUS_3_STATUS_INPI5_Msk                       (0x01UL << SGPIO_STATUS_3_STATUS_INPI5_Pos)               /*!< SGPIO STATUS_3: STATUS_INPI5 Mask   */
#define SGPIO_STATUS_3_STATUS_INPI6_Pos                       6                                                         /*!< SGPIO STATUS_3: STATUS_INPI6 Position */
#define SGPIO_STATUS_3_STATUS_INPI6_Msk                       (0x01UL << SGPIO_STATUS_3_STATUS_INPI6_Pos)               /*!< SGPIO STATUS_3: STATUS_INPI6 Mask   */
#define SGPIO_STATUS_3_STATUS_INPI7_Pos                       7                                                         /*!< SGPIO STATUS_3: STATUS_INPI7 Position */
#define SGPIO_STATUS_3_STATUS_INPI7_Msk                       (0x01UL << SGPIO_STATUS_3_STATUS_INPI7_Pos)               /*!< SGPIO STATUS_3: STATUS_INPI7 Mask   */
#define SGPIO_STATUS_3_STATUS_INPI8_Pos                       8                                                         /*!< SGPIO STATUS_3: STATUS_INPI8 Position */
#define SGPIO_STATUS_3_STATUS_INPI8_Msk                       (0x01UL << SGPIO_STATUS_3_STATUS_INPI8_Pos)               /*!< SGPIO STATUS_3: STATUS_INPI8 Mask   */
#define SGPIO_STATUS_3_STATUS_INPI9_Pos                       9                                                         /*!< SGPIO STATUS_3: STATUS_INPI9 Position */
#define SGPIO_STATUS_3_STATUS_INPI9_Msk                       (0x01UL << SGPIO_STATUS_3_STATUS_INPI9_Pos)               /*!< SGPIO STATUS_3: STATUS_INPI9 Mask   */
#define SGPIO_STATUS_3_STATUS_INPI10_Pos                      10                                                        /*!< SGPIO STATUS_3: STATUS_INPI10 Position */
#define SGPIO_STATUS_3_STATUS_INPI10_Msk                      (0x01UL << SGPIO_STATUS_3_STATUS_INPI10_Pos)              /*!< SGPIO STATUS_3: STATUS_INPI10 Mask  */
#define SGPIO_STATUS_3_STATUS_INPI11_Pos                      11                                                        /*!< SGPIO STATUS_3: STATUS_INPI11 Position */
#define SGPIO_STATUS_3_STATUS_INPI11_Msk                      (0x01UL << SGPIO_STATUS_3_STATUS_INPI11_Pos)              /*!< SGPIO STATUS_3: STATUS_INPI11 Mask  */
#define SGPIO_STATUS_3_STATUS_INPI12_Pos                      12                                                        /*!< SGPIO STATUS_3: STATUS_INPI12 Position */
#define SGPIO_STATUS_3_STATUS_INPI12_Msk                      (0x01UL << SGPIO_STATUS_3_STATUS_INPI12_Pos)              /*!< SGPIO STATUS_3: STATUS_INPI12 Mask  */
#define SGPIO_STATUS_3_STATUS_INPI13_Pos                      13                                                        /*!< SGPIO STATUS_3: STATUS_INPI13 Position */
#define SGPIO_STATUS_3_STATUS_INPI13_Msk                      (0x01UL << SGPIO_STATUS_3_STATUS_INPI13_Pos)              /*!< SGPIO STATUS_3: STATUS_INPI13 Mask  */
#define SGPIO_STATUS_3_STATUS_INPI14_Pos                      14                                                        /*!< SGPIO STATUS_3: STATUS_INPI14 Position */
#define SGPIO_STATUS_3_STATUS_INPI14_Msk                      (0x01UL << SGPIO_STATUS_3_STATUS_INPI14_Pos)              /*!< SGPIO STATUS_3: STATUS_INPI14 Mask  */
#define SGPIO_STATUS_3_STATUS_INPI15_Pos                      15                                                        /*!< SGPIO STATUS_3: STATUS_INPI15 Position */
#define SGPIO_STATUS_3_STATUS_INPI15_Msk                      (0x01UL << SGPIO_STATUS_3_STATUS_INPI15_Pos)              /*!< SGPIO STATUS_3: STATUS_INPI15 Mask  */

// -----------------------------------  SGPIO_CTR_STATUS_3  ---------------------------------------
#define SGPIO_CTR_STATUS_3_CTR_STATUS_INPI0_Pos               0                                                         /*!< SGPIO CTR_STATUS_3: CTR_STATUS_INPI0 Position */
#define SGPIO_CTR_STATUS_3_CTR_STATUS_INPI0_Msk               (0x01UL << SGPIO_CTR_STATUS_3_CTR_STATUS_INPI0_Pos)       /*!< SGPIO CTR_STATUS_3: CTR_STATUS_INPI0 Mask */
#define SGPIO_CTR_STATUS_3_CTR_STATUS_INPI1_Pos               1                                                         /*!< SGPIO CTR_STATUS_3: CTR_STATUS_INPI1 Position */
#define SGPIO_CTR_STATUS_3_CTR_STATUS_INPI1_Msk               (0x01UL << SGPIO_CTR_STATUS_3_CTR_STATUS_INPI1_Pos)       /*!< SGPIO CTR_STATUS_3: CTR_STATUS_INPI1 Mask */
#define SGPIO_CTR_STATUS_3_CTR_STATUS_INPI2_Pos               2                                                         /*!< SGPIO CTR_STATUS_3: CTR_STATUS_INPI2 Position */
#define SGPIO_CTR_STATUS_3_CTR_STATUS_INPI2_Msk               (0x01UL << SGPIO_CTR_STATUS_3_CTR_STATUS_INPI2_Pos)       /*!< SGPIO CTR_STATUS_3: CTR_STATUS_INPI2 Mask */
#define SGPIO_CTR_STATUS_3_CTR_STATUS_INPI3_Pos               3                                                         /*!< SGPIO CTR_STATUS_3: CTR_STATUS_INPI3 Position */
#define SGPIO_CTR_STATUS_3_CTR_STATUS_INPI3_Msk               (0x01UL << SGPIO_CTR_STATUS_3_CTR_STATUS_INPI3_Pos)       /*!< SGPIO CTR_STATUS_3: CTR_STATUS_INPI3 Mask */
#define SGPIO_CTR_STATUS_3_CTR_STATUS_INPI4_Pos               4                                                         /*!< SGPIO CTR_STATUS_3: CTR_STATUS_INPI4 Position */
#define SGPIO_CTR_STATUS_3_CTR_STATUS_INPI4_Msk               (0x01UL << SGPIO_CTR_STATUS_3_CTR_STATUS_INPI4_Pos)       /*!< SGPIO CTR_STATUS_3: CTR_STATUS_INPI4 Mask */
#define SGPIO_CTR_STATUS_3_CTR_STATUS_INPI5_Pos               5                                                         /*!< SGPIO CTR_STATUS_3: CTR_STATUS_INPI5 Position */
#define SGPIO_CTR_STATUS_3_CTR_STATUS_INPI5_Msk               (0x01UL << SGPIO_CTR_STATUS_3_CTR_STATUS_INPI5_Pos)       /*!< SGPIO CTR_STATUS_3: CTR_STATUS_INPI5 Mask */
#define SGPIO_CTR_STATUS_3_CTR_STATUS_INPI6_Pos               6                                                         /*!< SGPIO CTR_STATUS_3: CTR_STATUS_INPI6 Position */
#define SGPIO_CTR_STATUS_3_CTR_STATUS_INPI6_Msk               (0x01UL << SGPIO_CTR_STATUS_3_CTR_STATUS_INPI6_Pos)       /*!< SGPIO CTR_STATUS_3: CTR_STATUS_INPI6 Mask */
#define SGPIO_CTR_STATUS_3_CTR_STATUS_INPI7_Pos               7                                                         /*!< SGPIO CTR_STATUS_3: CTR_STATUS_INPI7 Position */
#define SGPIO_CTR_STATUS_3_CTR_STATUS_INPI7_Msk               (0x01UL << SGPIO_CTR_STATUS_3_CTR_STATUS_INPI7_Pos)       /*!< SGPIO CTR_STATUS_3: CTR_STATUS_INPI7 Mask */
#define SGPIO_CTR_STATUS_3_CTR_STATUS_INPI8_Pos               8                                                         /*!< SGPIO CTR_STATUS_3: CTR_STATUS_INPI8 Position */
#define SGPIO_CTR_STATUS_3_CTR_STATUS_INPI8_Msk               (0x01UL << SGPIO_CTR_STATUS_3_CTR_STATUS_INPI8_Pos)       /*!< SGPIO CTR_STATUS_3: CTR_STATUS_INPI8 Mask */
#define SGPIO_CTR_STATUS_3_CTR_STATUS_INPI9_Pos               9                                                         /*!< SGPIO CTR_STATUS_3: CTR_STATUS_INPI9 Position */
#define SGPIO_CTR_STATUS_3_CTR_STATUS_INPI9_Msk               (0x01UL << SGPIO_CTR_STATUS_3_CTR_STATUS_INPI9_Pos)       /*!< SGPIO CTR_STATUS_3: CTR_STATUS_INPI9 Mask */
#define SGPIO_CTR_STATUS_3_CTR_STATUS_INPI10_Pos              10                                                        /*!< SGPIO CTR_STATUS_3: CTR_STATUS_INPI10 Position */
#define SGPIO_CTR_STATUS_3_CTR_STATUS_INPI10_Msk              (0x01UL << SGPIO_CTR_STATUS_3_CTR_STATUS_INPI10_Pos)      /*!< SGPIO CTR_STATUS_3: CTR_STATUS_INPI10 Mask */
#define SGPIO_CTR_STATUS_3_CTR_STATUS_INPI11_Pos              11                                                        /*!< SGPIO CTR_STATUS_3: CTR_STATUS_INPI11 Position */
#define SGPIO_CTR_STATUS_3_CTR_STATUS_INPI11_Msk              (0x01UL << SGPIO_CTR_STATUS_3_CTR_STATUS_INPI11_Pos)      /*!< SGPIO CTR_STATUS_3: CTR_STATUS_INPI11 Mask */
#define SGPIO_CTR_STATUS_3_CTR_STATUS_INPI12_Pos              12                                                        /*!< SGPIO CTR_STATUS_3: CTR_STATUS_INPI12 Position */
#define SGPIO_CTR_STATUS_3_CTR_STATUS_INPI12_Msk              (0x01UL << SGPIO_CTR_STATUS_3_CTR_STATUS_INPI12_Pos)      /*!< SGPIO CTR_STATUS_3: CTR_STATUS_INPI12 Mask */
#define SGPIO_CTR_STATUS_3_CTR_STATUS_INPI13_Pos              13                                                        /*!< SGPIO CTR_STATUS_3: CTR_STATUS_INPI13 Position */
#define SGPIO_CTR_STATUS_3_CTR_STATUS_INPI13_Msk              (0x01UL << SGPIO_CTR_STATUS_3_CTR_STATUS_INPI13_Pos)      /*!< SGPIO CTR_STATUS_3: CTR_STATUS_INPI13 Mask */
#define SGPIO_CTR_STATUS_3_CTR_STATUS_INPI14_Pos              14                                                        /*!< SGPIO CTR_STATUS_3: CTR_STATUS_INPI14 Position */
#define SGPIO_CTR_STATUS_3_CTR_STATUS_INPI14_Msk              (0x01UL << SGPIO_CTR_STATUS_3_CTR_STATUS_INPI14_Pos)      /*!< SGPIO CTR_STATUS_3: CTR_STATUS_INPI14 Mask */
#define SGPIO_CTR_STATUS_3_CTR_STATUS_INPI15_Pos              15                                                        /*!< SGPIO CTR_STATUS_3: CTR_STATUS_INPI15 Position */
#define SGPIO_CTR_STATUS_3_CTR_STATUS_INPI15_Msk              (0x01UL << SGPIO_CTR_STATUS_3_CTR_STATUS_INPI15_Pos)      /*!< SGPIO CTR_STATUS_3: CTR_STATUS_INPI15 Mask */

// -----------------------------------  SGPIO_SET_STATUS_3  ---------------------------------------
#define SGPIO_SET_STATUS_3_CTR_STATUS_INPI0_Pos               0                                                         /*!< SGPIO SET_STATUS_3: CTR_STATUS_INPI0 Position */
#define SGPIO_SET_STATUS_3_CTR_STATUS_INPI0_Msk               (0x01UL << SGPIO_SET_STATUS_3_CTR_STATUS_INPI0_Pos)       /*!< SGPIO SET_STATUS_3: CTR_STATUS_INPI0 Mask */
#define SGPIO_SET_STATUS_3_CTR_STATUS_INPI1_Pos               1                                                         /*!< SGPIO SET_STATUS_3: CTR_STATUS_INPI1 Position */
#define SGPIO_SET_STATUS_3_CTR_STATUS_INPI1_Msk               (0x01UL << SGPIO_SET_STATUS_3_CTR_STATUS_INPI1_Pos)       /*!< SGPIO SET_STATUS_3: CTR_STATUS_INPI1 Mask */
#define SGPIO_SET_STATUS_3_CTR_STATUS_INPI2_Pos               2                                                         /*!< SGPIO SET_STATUS_3: CTR_STATUS_INPI2 Position */
#define SGPIO_SET_STATUS_3_CTR_STATUS_INPI2_Msk               (0x01UL << SGPIO_SET_STATUS_3_CTR_STATUS_INPI2_Pos)       /*!< SGPIO SET_STATUS_3: CTR_STATUS_INPI2 Mask */
#define SGPIO_SET_STATUS_3_CTR_STATUS_INPI3_Pos               3                                                         /*!< SGPIO SET_STATUS_3: CTR_STATUS_INPI3 Position */
#define SGPIO_SET_STATUS_3_CTR_STATUS_INPI3_Msk               (0x01UL << SGPIO_SET_STATUS_3_CTR_STATUS_INPI3_Pos)       /*!< SGPIO SET_STATUS_3: CTR_STATUS_INPI3 Mask */
#define SGPIO_SET_STATUS_3_CTR_STATUS_INPI4_Pos               4                                                         /*!< SGPIO SET_STATUS_3: CTR_STATUS_INPI4 Position */
#define SGPIO_SET_STATUS_3_CTR_STATUS_INPI4_Msk               (0x01UL << SGPIO_SET_STATUS_3_CTR_STATUS_INPI4_Pos)       /*!< SGPIO SET_STATUS_3: CTR_STATUS_INPI4 Mask */
#define SGPIO_SET_STATUS_3_CTR_STATUS_INPI5_Pos               5                                                         /*!< SGPIO SET_STATUS_3: CTR_STATUS_INPI5 Position */
#define SGPIO_SET_STATUS_3_CTR_STATUS_INPI5_Msk               (0x01UL << SGPIO_SET_STATUS_3_CTR_STATUS_INPI5_Pos)       /*!< SGPIO SET_STATUS_3: CTR_STATUS_INPI5 Mask */
#define SGPIO_SET_STATUS_3_CTR_STATUS_INPI6_Pos               6                                                         /*!< SGPIO SET_STATUS_3: CTR_STATUS_INPI6 Position */
#define SGPIO_SET_STATUS_3_CTR_STATUS_INPI6_Msk               (0x01UL << SGPIO_SET_STATUS_3_CTR_STATUS_INPI6_Pos)       /*!< SGPIO SET_STATUS_3: CTR_STATUS_INPI6 Mask */
#define SGPIO_SET_STATUS_3_CTR_STATUS_INPI7_Pos               7                                                         /*!< SGPIO SET_STATUS_3: CTR_STATUS_INPI7 Position */
#define SGPIO_SET_STATUS_3_CTR_STATUS_INPI7_Msk               (0x01UL << SGPIO_SET_STATUS_3_CTR_STATUS_INPI7_Pos)       /*!< SGPIO SET_STATUS_3: CTR_STATUS_INPI7 Mask */
#define SGPIO_SET_STATUS_3_CTR_STATUS_INPI8_Pos               8                                                         /*!< SGPIO SET_STATUS_3: CTR_STATUS_INPI8 Position */
#define SGPIO_SET_STATUS_3_CTR_STATUS_INPI8_Msk               (0x01UL << SGPIO_SET_STATUS_3_CTR_STATUS_INPI8_Pos)       /*!< SGPIO SET_STATUS_3: CTR_STATUS_INPI8 Mask */
#define SGPIO_SET_STATUS_3_CTR_STATUS_INPI9_Pos               9                                                         /*!< SGPIO SET_STATUS_3: CTR_STATUS_INPI9 Position */
#define SGPIO_SET_STATUS_3_CTR_STATUS_INPI9_Msk               (0x01UL << SGPIO_SET_STATUS_3_CTR_STATUS_INPI9_Pos)       /*!< SGPIO SET_STATUS_3: CTR_STATUS_INPI9 Mask */
#define SGPIO_SET_STATUS_3_CTR_STATUS_INPI10_Pos              10                                                        /*!< SGPIO SET_STATUS_3: CTR_STATUS_INPI10 Position */
#define SGPIO_SET_STATUS_3_CTR_STATUS_INPI10_Msk              (0x01UL << SGPIO_SET_STATUS_3_CTR_STATUS_INPI10_Pos)      /*!< SGPIO SET_STATUS_3: CTR_STATUS_INPI10 Mask */
#define SGPIO_SET_STATUS_3_CTR_STATUS_INPI11_Pos              11                                                        /*!< SGPIO SET_STATUS_3: CTR_STATUS_INPI11 Position */
#define SGPIO_SET_STATUS_3_CTR_STATUS_INPI11_Msk              (0x01UL << SGPIO_SET_STATUS_3_CTR_STATUS_INPI11_Pos)      /*!< SGPIO SET_STATUS_3: CTR_STATUS_INPI11 Mask */
#define SGPIO_SET_STATUS_3_CTR_STATUS_INPI12_Pos              12                                                        /*!< SGPIO SET_STATUS_3: CTR_STATUS_INPI12 Position */
#define SGPIO_SET_STATUS_3_CTR_STATUS_INPI12_Msk              (0x01UL << SGPIO_SET_STATUS_3_CTR_STATUS_INPI12_Pos)      /*!< SGPIO SET_STATUS_3: CTR_STATUS_INPI12 Mask */
#define SGPIO_SET_STATUS_3_CTR_STATUS_INPI13_Pos              13                                                        /*!< SGPIO SET_STATUS_3: CTR_STATUS_INPI13 Position */
#define SGPIO_SET_STATUS_3_CTR_STATUS_INPI13_Msk              (0x01UL << SGPIO_SET_STATUS_3_CTR_STATUS_INPI13_Pos)      /*!< SGPIO SET_STATUS_3: CTR_STATUS_INPI13 Mask */
#define SGPIO_SET_STATUS_3_CTR_STATUS_INPI14_Pos              14                                                        /*!< SGPIO SET_STATUS_3: CTR_STATUS_INPI14 Position */
#define SGPIO_SET_STATUS_3_CTR_STATUS_INPI14_Msk              (0x01UL << SGPIO_SET_STATUS_3_CTR_STATUS_INPI14_Pos)      /*!< SGPIO SET_STATUS_3: CTR_STATUS_INPI14 Mask */
#define SGPIO_SET_STATUS_3_CTR_STATUS_INPI15_Pos              15                                                        /*!< SGPIO SET_STATUS_3: CTR_STATUS_INPI15 Position */
#define SGPIO_SET_STATUS_3_CTR_STATUS_INPI15_Msk              (0x01UL << SGPIO_SET_STATUS_3_CTR_STATUS_INPI15_Pos)      /*!< SGPIO SET_STATUS_3: CTR_STATUS_INPI15 Mask */

#endif

// ------------------------------------------------------------------------------------------------
// -----                                 Peripheral memory map                                -----
// ------------------------------------------------------------------------------------------------

#define LPC_SCT_BASE              0x40000000
#define LPC_GPDMA_BASE            0x40002000
#define LPC_SDMMC_BASE            0x40004000
#define LPC_EMC_BASE              0x40005000
#define LPC_USB0_BASE             0x40006000
#define LPC_USB1_BASE             0x40007000
#define LPC_LCD_BASE              0x40008000
#define LPC_ETHERNET_BASE         0x40010000
#define LPC_ATIMER_BASE           0x40040000
#define LPC_REGFILE_BASE          0x40041000
#define LPC_PMC_BASE              0x40042000
#define LPC_CREG_BASE             0x40043000
#define LPC_EVENTROUTER_BASE      0x40044000
#define LPC_RTC_BASE              0x40046000
#define LPC_CGU_BASE              0x40050000
#define LPC_CCU1_BASE             0x40051000
#define LPC_CCU2_BASE             0x40052000
#define LPC_RGU_BASE              0x40053000
#define LPC_WWDT_BASE             0x40080000
#define LPC_USART0_BASE           0x40081000
#define LPC_USART2_BASE           0x400C1000
#define LPC_USART3_BASE           0x400C2000
#define LPC_UART1_BASE            0x40082000
#define LPC_SSP0_BASE             0x40083000
#define LPC_SSP1_BASE             0x400C5000
#define LPC_TIMER0_BASE           0x40084000
#define LPC_TIMER1_BASE           0x40085000
#define LPC_TIMER2_BASE           0x400C3000
#define LPC_TIMER3_BASE           0x400C4000
#define LPC_SCU_BASE              0x40086000
#define LPC_GPIO_PIN_INT_BASE     0x40087000
#define LPC_GPIO_GROUP_INT0_BASE  0x40088000
#define LPC_GPIO_GROUP_INT1_BASE  0x40089000
#define LPC_MCPWM_BASE            0x400A0000
#define LPC_I2C0_BASE             0x400A1000
#define LPC_I2C1_BASE             0x400E0000
#define LPC_I2S0_BASE             0x400A2000
#define LPC_I2S1_BASE             0x400A3000
#define LPC_C_CAN1_BASE           0x400A4000
#define LPC_RITIMER_BASE          0x400C0000
#define LPC_QEI_BASE              0x400C6000
#define LPC_GIMA_BASE             0x400C7000
#define LPC_DAC_BASE              0x400E1000
#define LPC_C_CAN0_BASE           0x400E2000
#define LPC_ADC0_BASE             0x400E3000
#define LPC_ADC1_BASE             0x400E4000
#define LPC_GPIO_PORT_BASE        0x400F4000
#define LPC_SPI_BASE              0x40100000
#define LPC_SGPIO_BASE            0x40101000


// ------------------------------------------------------------------------------------------------
// -----                                Peripheral declaration                                -----
// ------------------------------------------------------------------------------------------------

#define LPC_SCT                   ((LPC_SCT_Type            *) LPC_SCT_BASE)
#define LPC_GPDMA                 ((LPC_GPDMA_Type          *) LPC_GPDMA_BASE)
#define LPC_SDMMC                 ((LPC_SDMMC_Type          *) LPC_SDMMC_BASE)
#define LPC_EMC                   ((LPC_EMC_Type            *) LPC_EMC_BASE)
#define LPC_USB0                  ((LPC_USB0_Type           *) LPC_USB0_BASE)
#define LPC_USB1                  ((LPC_USB1_Type           *) LPC_USB1_BASE)
#define LPC_LCD                   ((LPC_LCD_Type            *) LPC_LCD_BASE)
#define LPC_ETHERNET              ((LPC_ETHERNET_Type       *) LPC_ETHERNET_BASE)
#define LPC_ATIMER                ((LPC_ATIMER_Type         *) LPC_ATIMER_BASE)
#define LPC_REGFILE               ((LPC_REGFILE_Type        *) LPC_REGFILE_BASE)
#define LPC_PMC                   ((LPC_PMC_Type            *) LPC_PMC_BASE)
#define LPC_CREG                  ((LPC_CREG_Type           *) LPC_CREG_BASE)
#define LPC_EVENTROUTER           ((LPC_EVENTROUTER_Type    *) LPC_EVENTROUTER_BASE)
#define LPC_RTC                   ((LPC_RTC_Type            *) LPC_RTC_BASE)
#define LPC_CGU                   ((LPC_CGU_Type            *) LPC_CGU_BASE)
#define LPC_CCU1                  ((LPC_CCU1_Type           *) LPC_CCU1_BASE)
#define LPC_CCU2                  ((LPC_CCU2_Type           *) LPC_CCU2_BASE)
#define LPC_RGU                   ((LPC_RGU_Type            *) LPC_RGU_BASE)
#define LPC_WWDT                  ((LPC_WWDT_Type           *) LPC_WWDT_BASE)
#define LPC_USART0                ((LPC_USARTn_Type         *) LPC_USART0_BASE)
#define LPC_USART2                ((LPC_USARTn_Type         *) LPC_USART2_BASE)
#define LPC_USART3                ((LPC_USARTn_Type         *) LPC_USART3_BASE)
#define LPC_UART1                 ((LPC_UART1_Type          *) LPC_UART1_BASE)
#define LPC_SSP0                  ((LPC_SSPn_Type           *) LPC_SSP0_BASE)
#define LPC_SSP1                  ((LPC_SSPn_Type           *) LPC_SSP1_BASE)
#define LPC_TIMER0                ((LPC_TIMERn_Type         *) LPC_TIMER0_BASE)
#define LPC_TIMER1                ((LPC_TIMERn_Type         *) LPC_TIMER1_BASE)
#define LPC_TIMER2                ((LPC_TIMERn_Type         *) LPC_TIMER2_BASE)
#define LPC_TIMER3                ((LPC_TIMERn_Type         *) LPC_TIMER3_BASE)
#define LPC_SCU                   ((LPC_SCU_Type            *) LPC_SCU_BASE)
#define LPC_GPIO_PIN_INT          ((LPC_GPIO_PIN_INT_Type   *) LPC_GPIO_PIN_INT_BASE)
#define LPC_GPIO_GROUP_INT0       ((LPC_GPIO_GROUP_INTn_Type*) LPC_GPIO_GROUP_INT0_BASE)
#define LPC_GPIO_GROUP_INT1       ((LPC_GPIO_GROUP_INTn_Type*) LPC_GPIO_GROUP_INT1_BASE)
#define LPC_MCPWM                 ((LPC_MCPWM_Type          *) LPC_MCPWM_BASE)
#define LPC_I2C0                  ((LPC_I2Cn_Type           *) LPC_I2C0_BASE)
#define LPC_I2C1                  ((LPC_I2Cn_Type           *) LPC_I2C1_BASE)
#define LPC_I2S0                  ((LPC_I2Sn_Type           *) LPC_I2S0_BASE)
#define LPC_I2S1                  ((LPC_I2Sn_Type           *) LPC_I2S1_BASE)
#define LPC_C_CAN1                ((LPC_C_CANn_Type         *) LPC_C_CAN1_BASE)
#define LPC_RITIMER               ((LPC_RITIMER_Type        *) LPC_RITIMER_BASE)
#define LPC_QEI                   ((LPC_QEI_Type            *) LPC_QEI_BASE)
#define LPC_GIMA                  ((LPC_GIMA_Type           *) LPC_GIMA_BASE)
#define LPC_DAC                   ((LPC_DAC_Type            *) LPC_DAC_BASE)
#define LPC_C_CAN0                ((LPC_C_CANn_Type         *) LPC_C_CAN0_BASE)
#define LPC_ADC0                  ((LPC_ADCn_Type           *) LPC_ADC0_BASE)
#define LPC_ADC1                  ((LPC_ADCn_Type           *) LPC_ADC1_BASE)
#define LPC_GPIO_PORT             ((LPC_GPIO_PORT_Type      *) LPC_GPIO_PORT_BASE)
#define LPC_SPI                   ((LPC_SPI_Type            *) LPC_SPI_BASE)
#define LPC_SGPIO                 ((LPC_SGPIO_Type          *) LPC_SGPIO_BASE)


/** @} */ /* End of group Device_Peripheral_Registers */
/** @} */ /* End of group LPC43xx */
/** @} */ /* End of group (null) */

#ifdef __cplusplus
}
#endif 


#endif  // __LPC43xx_H__

