library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

library std;
use std.textio.all;

entity test is
end test;

architecture Behavior of test is
  signal a   : std_logic_vector(7 downto 0);
  signal clk : std_logic;
  file   src : text open read_mode is "in_file_name";
begin
  process
  begin
    for i in 1 to 10 loop
      clk <= '0'; wait for 50 ns;
      clk <= '1'; wait for 50 ns;
    end loop;
    wait;
  end process;

  process 
    variable l     : line;
    variable var_a : bit_vector(7 downto 0);
  begin
    wait until CLK'event and CLK = '1';
    readline(src, l); -- 1行読む
    read(l, var_a); -- デリミタ(空白)までを切り出して変数に代入
    a <= to_stdlogicvector(var_a); -- std_logic_vectorに変換して代入
  end process;
end Behavior;
