library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
--use ieee.std_logic_textio.all;  -- これと

library std;
use std.textio.all;             -- これが 必要!

entity edge is
end edge;

architecture RTL of edge is
  signal clk     : std_logic;
begin

  process
  begin
    for i in 1 to 10 loop
      wait for 50 ns;
      clk <= '0';
      wait for 50 ns;
      clk <= '1';
    end loop;
    wait;
  end process;

end RTL;
