### LEON3MP - a reference LEON3 for the GR-PCI-XC2V3000 board #### #### Introduction The LEON3MP provides a reference design for LEON3-based systems. This version is tailored for the GR-PCI-XC2V3000 board from Pender Electronic Design, and consists of the following IP cores:
1 - 4 LEON3 processor cores with MP support Multi-processor debug support unit (DSU) for LEON3 32-bit PROM/SRAM controller 8-/16-/32-/64-bit PROM/SRAM/SDRAM controller 32-bit PCI interface, initiator/target with FIFO and DMA Round-robin AHB arbiter and controller AHB/APB bridge with plug&play support Multi-processor interrupt controller 32-bit modular timer unit 1 - 2 UARTs with FIFO 10/100 ethernet MAC CAN interface Serial debug communication link Etherner debug communication link JTAG debug link |
The LEON3 MP design is provided together with GRLIB, and is located in grlib/designs/leon3-gr-pci-xc2v3000. #### LEON3MP Block diagram #### #### Reference architecture The LEON3MP is made up by cores from the GRLIB IP library, which are connected together via the AMBA AHB and APB buses. The plug&play configuration method of GRLIB makes it possible to assign any combination of addresses and interrupts to the cores. However, to be software compatible with simple operating systems such as the LEON Bare-C cross-compiler, some of the vital cores must be assigned to predefined addresses and interrupts. The table below shows the reference assigment in the LEON3MP design:
Core | Memory area | Interrupt
--- | --- | ---
Memory controller | 0x00000000 - 0x20000000 : PROM 0x20000000 - 0x40000000 : external I/O bus 0x40000000 - 0x80000000 : SRAM/SDRAM 0x80000000 - 0x80000100 : Memory controller registers (APB) | -
APB bridge | 0x80000000 - 0x80100000 : APB bus | -
UART | 0x80000100 - 0x80000200 : UART registers | 2
Interrupt controller | 0x80000200 - 0x80000300 : IRQ registers | -
Timer unit | 0x80000300 - 0x80000400 : timer registers | 8, 9
LEON3 debug support unit (DSU) | 0x90000000 - 0xA0000000 : DSU registers | -
Additional (optional) IP cores are assigned addresses and interrupts as desribed in the table below. These assignments are LEON3MP specific and can be changed without impact on software compatibility.
Core | Memory area | Interrupt
--- | --- | ---
PCI initiator/target interface | 0xE0000000 - 0xF0000000 : PCI initiator access 0xFFF80000 - 0xFFFA0000 : PCI special cycles 0x80000400 - 0x80000500 : PCI registers 0x80000600 - 0x80000700 : PCI DMA registers | -
PCI arbiter | 0x80000A00 - 0x80000B00 : PCI arbiter registers |
PCI trace buffer | 0x80010000 - 0x80020000 : PCI trace buffer registers | -
Serial debug communication link | 0x80000700 - 0x80000800 : AHB UART registers | -
Ethernet debug communication link | - | -
JTAG debug communication link | - | -
10/100 Mbit ethernet MAC | 0xFFFB0000 - 0xFFFB1000 : ethernet control registers | 12
CAN interface | 0xFFFC0000 - 0xFFFC1000 : CAN control registers | 13
On-chip RAM | 0xA0000000 - 0xA0100000 : On-chip RAM |
UART | 0x80000900 - 0x80000A00 : Secondary UART | 3
#### #### Configuration The configuartion of the LEON3MP design is defined through the config package located config.vhd. This file can be automatically generated using a GUI based on tkconfig. To launch the GUI, do 'make xconfig'. After the configuration is completed, save and exit the tool and config.vhd will be created automatically. Figure 1. LEON3MP configuration GUI #### Simulation To simulate the testbench, first compile the model for simulation. This can be done automatically for three different simulators. Execute one of the following commands: make vsim make ncsim make ghdl For vsim, start the simulation with 'vsim testbench' and do 'run 100'. This should print the current LEON3MP configuration: $ vsim -c -quiet testbench Reading /usr/local/model58/tcl/vsim/pref.tcl Reading /home/jiri/modelsim.tcl # 5.8 `# VSIM 1> run # LEON3 Demonstration design # GRLIB Version 0.13 # Target technology: virtex2 , memory library: virtex2 # ahbctrl: mst0: Gaisler Research Leon3 SPARC V8 Processor # ahbctrl: mst1: Gaisler Research AHB Debug UART # ahbctrl: mst2: Gaisler Research Fast 32-bit PCI Bridge # ahbctrl: mst3: Gaisler Research AMBA DMA controller # ahbctrl: mst5: Gaisler Research OC ethernet AHB interface # ahbctrl: slv0: Gaisler Research Simple SRAM Controller # ahbctrl: memory at 0x00000000, size 16 Mbyte, cacheable, prefetch # ahbctrl: memory at 0x40000000, size 16 Mbyte, cacheable, prefetch # ahbctrl: slv1: Gaisler Research AHB/APB Bridge # ahbctrl: memory at 0x80000000, size 1 Mbyte # ahbctrl: slv2: Gaisler Research Leon3 Debug Support Unit # ahbctrl: memory at 0x90000000, size 256 Mbyte # ahbctrl: slv4: Gaisler Research Fast 32-bit PCI Bridge # ahbctrl: memory at 0xe0000000, size 256 Mbyte # ahbctrl: I/O port at 0xfff80000, size 128kbyte # ahbctrl: slv5: Gaisler Research OC ethernet AHB interface # ahbctrl: I/O port at 0xfffb0000, size 4kbyte # ahbctrl: slv6: Gaisler Research OC CAN AHB interface # ahbctrl: I/O port at 0xfffc0000, size 4kbyte # ahbctrl: slv7: Gaisler Research Generic AHB SRAM module # ahbctrl: memory at 0xa0000000, size 1 Mbyte, cacheable, prefetch # ahbctrl: AHB arbiter/multiplexer rev 1 # ahbctrl: Common I/O area at 0xfff00000, 1 Mbyte # ahbctrl: Configuration area at 0xfffff000, 4 kbyte # apbctrl: APB Bridge at 0x80000000 rev 1 # apbctrl: slv1: Gaisler Research Generic UART # apbctrl: I/O ports at 0x80000100, size 256 byte # apbctrl: slv2: Gaisler Research Multi-processor Interrupt Ctrl. # apbctrl: I/O ports at 0x80000200, size 256 byte # apbctrl: slv3: Gaisler Research Modular Timer Unit # apbctrl: I/O ports at 0x80000300, size 256 byte # apbctrl: slv4: Gaisler Research Fast 32-bit PCI Bridge # apbctrl: I/O ports at 0x80000400, size 256 byte # apbctrl: slv5: Gaisler Research AMBA DMA controller # apbctrl: I/O ports at 0x80000500, size 256 byte # apbctrl: slv7: Gaisler Research AHB Debug UART # apbctrl: I/O ports at 0x80000700, size 256 byte # ahbram7: AHB SRAM Module rev 1, 2 kbytes # can_oc6: Opencores CAN MAC, rev 0, irq 13 # eth_oc5: Wishbone/AHB interface for OC ethernet MAC, irq 12 # eth_oc5: Opencores 10/100 Mbit ethernet MAC, rev 0 # pci_mtf4: 32-bit PCI/AHB bridge rev 0, 2 Mbyte PCI memory BAR, 8-word FIFOs # dmactrl5: 32-bit DMA controller & AHB/AHB bridge rev 0 # gptimer3: GR Timer Unit rev 0, 16-bit scaler, 1 32-bit timers, irq 8 # irqmp: Multi-processor Interrupt Controller rev 1, #cpu 1 # apbuart1: Generic UART rev 1, irq 2 # srctrl0: 32-bit PROM/SRAM controller rev 0 # ahbuart7: AHB Debug UART rev 0 # dsu3_2: LEON3 Debug support unit # leon3_0: LEON3 SPARC V8 processor rev 0 # leon3_0: icache 1*4 kbyte, dcache 1*4 kbyte` VSIM 2> run -all # **** GRLIB system test starting **** # Leon3 SPARC V8 Processor # register file # multiplier # radix-2 divider # cache system # Multi-processor Interrupt Ctrl. # Generic UART # Modular Timer Unit # Test passed, halting with IU error mode # # ** Failure: *** IU in error mode, simulation halted *** # Time: 669213500 ps Iteration: 1 Process: /testbench/iuerr File: testbench.vhd # Break at testbench.vhd line 263 # Stopped at testbench.vhd line 263 # #### Synthesis #### To synthesize and place&route, use the make utility and issue either 'make ise' or 'make ise-synp' to use the XST or Synplify tools respectively. Alternatively, the design can be implemented using the graphical XGrlib tool, which is started with 'make xgrlib'. Figure 2. XGrlib implementation tool To program the fpga, issue 'make ise-prog-fpga'. To re-program the configuration proms, do 'make ise-prog-prom'. After programming the proms, power-cycle the board to re-load the fpga. To get started quicker, suitable leon3mp.bit and leon3mp.msk files are provided in the bitfiles directory. The fpga or configuration proms can be programmed directly with this configuration, using the following commands: 'make ise-prog-fpga-ref' or 'make ise-prog-prom-ref '. #### Software development #### RTEMS: to develop RTEMS applications, download and install the LEON3 RTEMS Cross-compiler from gaisler.com. The LEON3 bsp automatically detects the location of UARTs, timers, interrupt controller and ethernet core using the plug&play information. Full sources of kernel, libraries and tools available. Bare-C: a LEON3 bare-C compiler is available for download from gaisler.com. Come with full source code for both the low-level I/O routines as well as the mkprom prom builder. eCos: a Leon3 port supporting FPU, SMP and single-vector trapping is available for ecos-current. Use Bare-C compiler to build. Linux: a Leon3 port of uClinux and linux-2.6.11 is available in the snapgear linux distribution. #### Debugging The on-chip debug support unit (DSU) makes debugging of target hardware relatively easy. The design support both serial, ethernet and JTAG debug interface, and the GRMON debug monitor can be attached with a serial cable, over a LAN, or using the Xilinx JTAG programming cable. Note that when you use the ethernet or the JTAG interface, you need specify the frequency of the AHB clock since it is not auto-detected. Below is a log from a debug session. $ grmon -u -grlib -jtag -freq 40 GRMON - The LEON multi purpose monitor v1.0.6 Copyright (C) 2004, Gaisler Research - all rights reserved. For latest updates, go to http://www.gaisler.com/ Comments or bug-reports to grmon@gaisler.com GRLIB DSU Monitor backend 1.0.1 (professional version) using JTAG cable on parallel port initialising ........... Component Vendor Leon3 SPARC V8 Processor Gaisler Research AHB Debug UART Gaisler Research Simple 32-bit PCI Target Gaisler Research 10/100 Mbit Ethernet MAC Opencores LEON2 Memory Controller European Space Agency AHB/APB Bridge Gaisler Research Leon3 Debug Support Unit Gaisler Research 10/100 Mbit Ethernet MAC Opencores Generic APB UART Gaisler Research Multi-processor Interrupt Ctrl Gaisler Research Modular Timer Unit Gaisler Research Use command 'info sys' to print a detailed report of attached cores grmon[grlib]> info sys 00.01:003 Gaisler Research Leon3 SPARC V8 Processor (ver 0) ahb master 0 01.01:007 Gaisler Research AHB Debug UART (ver 0) ahb master 1 apb: 80000700 - 80000800 baud rate 115200, ahb frequency 25.00 02.01:012 Gaisler Research Simple 32-bit PCI Target (ver 0) ahb master 2 03.08:005 Opencores 10/100 Mbit Ethernet MAC (ver 0) ahb master 3 00.04:00f European Space Agency LEON2 Memory Controller (ver 0) ahb: 00000000 - 20000000 ahb: 20000000 - 40000000 ahb: 40000000 - 80000000 apb: 80000000 - 80000100 32-bit sdram: 1 * 32 Mbyte @ 0x40000000, col 9, cas 2, ref 15.5 us 01.01:006 Gaisler Research AHB/APB Bridge (ver 0) ahb: 80000000 - 80100000 02.01:004 Gaisler Research Leon3 Debug Support Unit (ver 0) ahb: 90000000 - a0000000 AHB trace 64 lines CPU#0 win 8, hw breakpoints 2, itrace 64 lines icache 1 * 4 kbyte, 32 byte/line dcache 1 * 4 kbyte, 32 byte/line stack pointer 0x41fffff0 05.08:005 Opencores 10/100 Mbit Ethernet MAC (ver 0) irq 12 ahb: fffb0000 - fffb1000 01.01:00c Gaisler Research Generic APB UART (ver 1) irq 2 apb: 80000100 - 80000200 baud rate 38400, DSU mode 02.01:00d Gaisler Research Multi-processor Interrupt Ctrl (ver 1) apb: 80000200 - 80000300 03.01:011 Gaisler Research Modular Timer Unit (ver 0) irq 8 apb: 80000300 - 80000400 16-bit scaler, 2 * 32-bit timers, divisor 25 grmon[grlib]> lo ~/sparc-elf/src/examples/stanford section: .text at 0x40000000, size 61200 bytes section: .data at 0x4000ef10, size 2080 bytes total size: 63280 bytes (343.6 kbit/s) read 197 symbols entry point: 0x40000000 grmon[grlib]> run Starting Perm Towers Queens Intmm Mm Puzzle Quick Bubble Tree FFT 34 66 34 34 900 316 33 50 217 1100 Nonfloating point composite is 117 Floating point composite is 869 Program exited normally. grmon[grlib]> The LEON3MP test bench includes memory models of both boot-prom, sram and sdram. To build memory images for these models, do 'make soft' . Note: this will require that the bare-C compiler for LEON3 is installed, and /opt/sparc-elf/bin is added to the PATH.