CBX_HDL_LANGUAGE=VHDL
CBX_FILE=dq_dqs_inst.vhd
CBX_MODULE_PREFIX=UNUSED
CBX_REMOVE_OPTIONAL_WIRES=ON
CBXI_INSTANCE_NAME=UNUSED
DELAY_BUFFER_MODE=LOW
DELAY_DQS_ENABLE_BY_HALF_CYCLE=FALSE
device_family=stratixiii
DQ_HALF_RATE_USE_DATAOUTBYPASS=FALSE
DQ_INPUT_REG_ASYNC_MODE=NONE
DQ_INPUT_REG_CLK_SOURCE=CORE
DQ_INPUT_REG_MODE=DDIO
DQ_INPUT_REG_POWER_UP=HIGH
DQ_INPUT_REG_SYNC_MODE=NONE
DQ_INPUT_REG_USE_CLKN=FALSE
DQ_IPA_ADD_INPUT_CYCLE_DELAY=FALSE
DQ_IPA_ADD_PHASE_TRANSFER_REG=FALSE
DQ_IPA_BYPASS_OUTPUT_REGISTER=TRUE
DQ_IPA_INVERT_PHASE=FALSE
DQ_IPA_PHASE_SETTING=0
DQ_OE_REG_ASYNC_MODE=PRESET
DQ_OE_REG_MODE=DDIO
DQ_OE_REG_POWER_UP=HIGH
DQ_OE_REG_SYNC_MODE=NONE
DQ_OUTPUT_REG_ASYNC_MODE=NONE
DQ_OUTPUT_REG_MODE=DDIO
DQ_OUTPUT_REG_POWER_UP=HIGH
DQ_OUTPUT_REG_SYNC_MODE=NONE
DQS_CTRL_LATCHES_ENABLE=FALSE
DQS_DELAY_CHAIN_DELAYCTRLIN_SOURCE=CORE
DQS_DELAY_CHAIN_PHASE_SETTING=0
DQS_DQSN_MODE=DIFFERENTIAL
DQS_ENABLE_CTRL_ADD_PHASE_TRANSFER_REG=FALSE
DQS_ENABLE_CTRL_INVERT_PHASE=FALSE
DQS_ENABLE_CTRL_PHASE_SETTING=0
DQS_INPUT_FREQUENCY=UNUSED
DQS_OE_REG_ASYNC_MODE=PRESET
DQS_OE_REG_MODE=DDIO
DQS_OE_REG_POWER_UP=HIGH
DQS_OE_REG_SYNC_MODE=NONE
DQS_OFFSETCTRL_ENABLE=FALSE
DQS_OUTPUT_REG_ASYNC_MODE=NONE
DQS_OUTPUT_REG_MODE=DDIO
DQS_OUTPUT_REG_POWER_UP=LOW
DQS_OUTPUT_REG_SYNC_MODE=NONE
DQS_PHASE_SHIFT=0
IO_CLOCK_DIVIDER_CLK_SOURCE=CORE
IO_CLOCK_DIVIDER_INVERT_PHASE=FALSE
IO_CLOCK_DIVIDER_PHASE_SETTING=0
LEVEL_DQS_ENABLE=FALSE
NUMBER_OF_BIDIR_DQ=8
NUMBER_OF_CLK_DIVIDER=0
NUMBER_OF_INPUT_DQ=0
NUMBER_OF_OUTPUT_DQ=0
OCT_REG_MODE=FF
USE_DQ_INPUT_DELAY_CHAIN=TRUE
USE_DQ_IPA=FALSE
USE_DQ_IPA_PHASECTRLIN=FALSE
USE_DQ_OE_DELAY_CHAIN1=FALSE
USE_DQ_OE_DELAY_CHAIN2=FALSE
USE_DQ_OE_PATH=TRUE
USE_DQ_OUTPUT_DELAY_CHAIN1=FALSE
USE_DQ_OUTPUT_DELAY_CHAIN2=FALSE
USE_DQS=TRUE
USE_DQS_DELAY_CHAIN=FALSE
USE_DQS_DELAY_CHAIN_PHASECTRLIN=FALSE
USE_DQS_ENABLE=FALSE
USE_DQS_ENABLE_CTRL=FALSE
USE_DQS_ENABLE_CTRL_PHASECTRLIN=FALSE
USE_DQS_INPUT_DELAY_CHAIN=FALSE
USE_DQS_INPUT_PATH=FALSE
USE_DQS_OE_DELAY_CHAIN1=FALSE
USE_DQS_OE_DELAY_CHAIN2=FALSE
USE_DQS_OE_PATH=TRUE
USE_DQS_OUTPUT_DELAY_CHAIN1=FALSE
USE_DQS_OUTPUT_DELAY_CHAIN2=FALSE
USE_DQS_OUTPUT_PATH=TRUE
USE_DQSBUSOUT_DELAY_CHAIN=FALSE
USE_DQSENABLE_DELAY_CHAIN=FALSE
USE_DYNAMIC_OCT=TRUE
USE_HALF_RATE=FALSE
USE_IO_CLOCK_DIVIDER_MASTERIN=FALSE
USE_IO_CLOCK_DIVIDER_PHASECTRLIN=FALSE
USE_OCT_DELAY_CHAIN1=FALSE
USE_OCT_DELAY_CHAIN2=FALSE
bidir_dq_input_data_in
bidir_dq_input_data_out_high
bidir_dq_input_data_out_low
bidir_dq_io_config_ena
bidir_dq_oct_in
bidir_dq_oct_out
bidir_dq_oe_in
bidir_dq_oe_out
bidir_dq_output_data_in_high
bidir_dq_output_data_in_low
bidir_dq_output_data_out
bidir_dq_sreset
config_clk
config_datain
config_update
dq_input_reg_clk
dq_output_reg_clk
dqs_areset
dqs_bus_out
dqs_oct_in
dqs_oct_out
dqs_oe_in
dqs_oe_out
dqs_output_data_in_high
dqs_output_data_in_low
dqs_output_data_out
dqs_output_reg_clk
dqsn_areset
dqsn_bus_out
dqsn_oct_in
dqsn_oct_out
dqsn_oe_in
dqsn_oe_out
dqsn_output_data_in_high
dqsn_output_data_in_low
dqsn_output_data_out
oct_reg_clk
