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Defines | |
| #define | SPI_FMT_xSB_MASK (1 << 7) |
| #define | SPI_FMT_LSB (1 << 7) |
| #define | SPI_FMT_MSB (0 << 7) |
| #define | SPI_FMT_HDR_MASK (3 << 5) |
| #define | SPI_FMT_HDR_0 (0 << 5) |
| #define | SPI_FMT_HDR_1 (1 << 5) |
| #define | SPI_FMT_HDR_2 (2 << 5) |
| #define | SPI_ENABLE_FPGA 0x01 |
| #define | SPI_ENABLE_CODEC_A 0x02 |
| #define | SPI_ENABLE_CODEC_B 0x04 |
| #define | SPI_ENABLE_reserved 0x08 |
| #define | SPI_ENABLE_TX_A 0x10 |
| #define | SPI_ENABLE_RX_A 0x20 |
| #define | SPI_ENABLE_TX_B 0x40 |
| #define | SPI_ENABLE_RX_B 0x80 |
| #define SPI_ENABLE_CODEC_A 0x02 |
Referenced by usrp_9862_read(), and usrp_9862_write().
| #define SPI_ENABLE_CODEC_B 0x04 |
Referenced by usrp_9862_read(), and usrp_9862_write().
| #define SPI_ENABLE_FPGA 0x01 |
| #define SPI_ENABLE_reserved 0x08 |
| #define SPI_ENABLE_RX_A 0x20 |
| #define SPI_ENABLE_RX_B 0x80 |
| #define SPI_ENABLE_TX_A 0x10 |
| #define SPI_ENABLE_TX_B 0x40 |
| #define SPI_FMT_HDR_0 (0 << 5) |
| #define SPI_FMT_HDR_1 (1 << 5) |
Referenced by usrp_9862_read(), and usrp_9862_write().
| #define SPI_FMT_HDR_2 (2 << 5) |
| #define SPI_FMT_HDR_MASK (3 << 5) |
| #define SPI_FMT_LSB (1 << 7) |
| #define SPI_FMT_MSB (0 << 7) |
Referenced by usrp_9862_read(), and usrp_9862_write().
| #define SPI_FMT_xSB_MASK (1 << 7) |
1.5.5