usrp_commands.h File Reference
#include <usrp_interfaces.h>
#include <usrp_spi_defs.h>
Include dependency graph for usrp_commands.h:
This graph shows which files directly or indirectly include this file:
Go to the source code of this file.
Defines | |
| #define | MAX_EP0_PKTSIZE 64 |
| #define | VRT_VENDOR_IN 0xC0 |
| #define | VRT_VENDOR_OUT 0x40 |
| #define | VRQ_GET_STATUS 0x80 |
| #define | GS_TX_UNDERRUN 0 |
| #define | GS_RX_OVERRUN 1 |
| #define | VRQ_I2C_READ 0x81 |
| #define | VRQ_SPI_READ 0x82 |
| #define | VRQ_SET_LED 0x01 |
| #define | VRQ_FPGA_LOAD 0x02 |
| #define | FL_BEGIN 0 |
| #define | FL_XFER 1 |
| #define | FL_END 2 |
| #define | VRQ_FPGA_WRITE_REG 0x03 |
| #define | VRQ_FPGA_SET_RESET 0x04 |
| #define | VRQ_FPGA_SET_TX_ENABLE 0x05 |
| #define | VRQ_FPGA_SET_RX_ENABLE 0x06 |
| #define | VRQ_SET_SLEEP_BITS 0x07 |
| #define | SLEEP_ADC0 0x01 |
| #define | SLEEP_ADC1 0x02 |
| #define | SLEEP_DAC0 0x04 |
| #define | SLEEP_DAC1 0x08 |
| #define | VRQ_I2C_WRITE 0x08 |
| #define | VRQ_SPI_WRITE 0x09 |
| #define | VRQ_FPGA_SET_TX_RESET 0x0a |
| #define | VRQ_FPGA_SET_RX_RESET 0x0b |
| #define | USRP_HASH_SLOT_0_ADDR 0xe1e0 |
| #define | USRP_HASH_SLOT_1_ADDR 0xe1f0 |
Define Documentation
| #define FL_BEGIN 0 |
| #define FL_END 2 |
| #define FL_XFER 1 |
| #define GS_RX_OVERRUN 1 |
Referenced by usrp_check_rx_overrun().
| #define GS_TX_UNDERRUN 0 |
Referenced by usrp_check_tx_underrun().
| #define MAX_EP0_PKTSIZE 64 |
Referenced by usrp_eeprom_read(), usrp_i2c_read(), usrp_i2c_write(), usrp_spi_read(), and usrp_spi_write().
| #define SLEEP_ADC0 0x01 |
| #define SLEEP_ADC1 0x02 |
| #define SLEEP_DAC0 0x04 |
| #define SLEEP_DAC1 0x08 |
| #define USRP_HASH_SLOT_0_ADDR 0xe1e0 |
| #define USRP_HASH_SLOT_1_ADDR 0xe1f0 |
| #define VRQ_FPGA_LOAD 0x02 |
| #define VRQ_FPGA_SET_RESET 0x04 |
Referenced by usrp_set_fpga_reset().
| #define VRQ_FPGA_SET_RX_ENABLE 0x06 |
Referenced by usrp_set_fpga_rx_enable().
| #define VRQ_FPGA_SET_RX_RESET 0x0b |
Referenced by usrp_set_fpga_rx_reset().
| #define VRQ_FPGA_SET_TX_ENABLE 0x05 |
Referenced by usrp_set_fpga_tx_enable().
| #define VRQ_FPGA_SET_TX_RESET 0x0a |
Referenced by usrp_set_fpga_tx_reset().
| #define VRQ_FPGA_WRITE_REG 0x03 |
| #define VRQ_GET_STATUS 0x80 |
Referenced by _usrp_get_status().
| #define VRQ_I2C_READ 0x81 |
Referenced by usrp_i2c_read().
| #define VRQ_I2C_WRITE 0x08 |
Referenced by usrp_i2c_write().
| #define VRQ_SET_LED 0x01 |
Referenced by usrp_set_led().
| #define VRQ_SET_SLEEP_BITS 0x07 |
| #define VRQ_SPI_READ 0x82 |
Referenced by usrp_spi_read().
| #define VRQ_SPI_WRITE 0x09 |
Referenced by usrp_spi_write().
| #define VRT_VENDOR_IN 0xC0 |
| #define VRT_VENDOR_OUT 0x40 |
